From: Harry Wentland <harry.wentland@amd.com> To: Joe Perches <joe@perches.com>, linux-kernel@vger.kernel.org Cc: "Alex Deucher" <alexander.deucher@amd.com>, "David Airlie" <airlied@linux.ie>, dri-devel@lists.freedesktop.org, "Christian König" <christian.koenig@amd.com>, amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 2/4] drm: amd: Fix line continuation formats Date: Thu, 16 Nov 2017 10:38:41 -0500 [thread overview] Message-ID: <1b2c63b7-319a-caab-6809-197784c179ef@amd.com> (raw) In-Reply-To: <eee8836696843f983a9533d6441fa9f2d8cbe92f.1510845910.git.joe@perches.com> On 2017-11-16 10:27 AM, Joe Perches wrote: > Line continuations with excess spacing causes unexpected output. > > Miscellanea: > > o Added missing '\n' to a few of the coalesced pr_<level> formats > > Signed-off-by: Joe Perches <joe@perches.com> > --- > drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 11 ++++----- > .../amd/powerplay/hwmgr/process_pptables_v1_0.c | 6 ++--- > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 27 ++++++++-------------- > drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 6 ++--- > .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 9 +++----- > .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 6 ++--- > 6 files changed, 22 insertions(+), 43 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > index ced42484dcfc..6743786afcce 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > @@ -220,8 +220,7 @@ static void dpcd_set_lt_pattern_and_lane_settings( > size_in_bytes); > > dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING, > - "%s:\n %x VS set = %x PE set = %x \ > - max VS Reached = %x max PE Reached = %x\n", > + "%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", > __func__, > DP_TRAINING_LANE0_SET, > dpcd_lane[0].bits.VOLTAGE_SWING_SET, > @@ -558,8 +557,7 @@ static void dpcd_set_lane_settings( > */ > > dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING, > - "%s\n %x VS set = %x PE set = %x \ > - max VS Reached = %x max PE Reached = %x\n", > + "%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", > __func__, > DP_TRAINING_LANE0_SET, > dpcd_lane[0].bits.VOLTAGE_SWING_SET, > @@ -872,9 +870,8 @@ static bool perform_clock_recovery_sequence( > if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) { > ASSERT(0); > dm_logger_write(link->ctx->logger, LOG_ERROR, > - "%s: Link Training Error, could not \ > - get CR after %d tries. \ > - Possibly voltage swing issue", __func__, > + "%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue", Would probably be good to add a '\n' here as well but that's not the main intention of this patch. Either way patch is Reviewed-by: Harry Wentland <harry.wentland@amd.com> Harry > + __func__, > LINK_TRAINING_MAX_CR_RETRY); > > } > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c > index d1af1483c69b..813f827e4270 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c > @@ -523,8 +523,7 @@ static int get_pcie_table( > if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) > pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; > else > - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ > - Disregarding the excess entries... \n"); > + pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); > > pcie_table->count = pcie_count; > for (i = 0; i < pcie_count; i++) { > @@ -563,8 +562,7 @@ static int get_pcie_table( > if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) > pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; > else > - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ > - Disregarding the excess entries... \n"); > + pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); > > pcie_table->count = pcie_count; > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > index 4f79c21f27ed..9599fe0ba779 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > @@ -546,8 +546,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, > } > > if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) > - pr_info("Voltage value looks like a Leakage ID \ > - but it's not patched\n"); > + pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); > } > > /** > @@ -701,18 +700,14 @@ static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) > table_info->vdd_dep_on_mclk; > > PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, > - "VDD dependency on SCLK table is missing. \ > - This table is mandatory", return -EINVAL); > + "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL); > PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, > - "VDD dependency on SCLK table is empty. \ > - This table is mandatory", return -EINVAL); > + "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL); > > PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, > - "VDD dependency on MCLK table is missing. \ > - This table is mandatory", return -EINVAL); > + "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL); > PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, > - "VDD dependency on MCLK table is empty. \ > - This table is mandatory", return -EINVAL); > + "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL); > > table_info->max_clock_voltage_on_ac.sclk = > allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; > @@ -3415,8 +3410,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( > DPMTABLE_OD_UPDATE_SCLK)) { > result = vega10_populate_all_graphic_levels(hwmgr); > PP_ASSERT_WITH_CODE(!result, > - "Failed to populate SCLK during \ > - PopulateNewDPMClocksStates Function!", > + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", > return result); > } > > @@ -3425,8 +3419,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( > DPMTABLE_OD_UPDATE_MCLK)){ > result = vega10_populate_all_memory_levels(hwmgr); > PP_ASSERT_WITH_CODE(!result, > - "Failed to populate MCLK during \ > - PopulateNewDPMClocksStates Function!", > + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", > return result); > } > } else { > @@ -3543,8 +3536,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( > data->apply_optimized_settings) { > result = vega10_populate_all_graphic_levels(hwmgr); > PP_ASSERT_WITH_CODE(!result, > - "Failed to populate SCLK during \ > - PopulateNewDPMClocksStates Function!", > + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", > return result); > } > > @@ -3552,8 +3544,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( > (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { > result = vega10_populate_all_memory_levels(hwmgr); > PP_ASSERT_WITH_CODE(!result, > - "Failed to populate MCLK during \ > - PopulateNewDPMClocksStates Function!", > + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", > return result); > } > } > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c > index 4d672cd15785..ed4b37e566a3 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c > @@ -1732,8 +1732,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, > > if (0 != result) { > smu_data->smc_state_table.GraphicsBootLevel = 0; > - pr_err("VBIOS did not find boot engine clock value \ > - in dependency table. Using Graphics DPM level 0!"); > + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); > result = 0; > } > > @@ -1743,8 +1742,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, > > if (0 != result) { > smu_data->smc_state_table.MemoryBootLevel = 0; > - pr_err("VBIOS did not find boot engine clock value \ > - in dependency table. Using Memory DPM level 0!"); > + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n"); > result = 0; > } > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c > index 34128822b8fb..2ff682d44e8c 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c > @@ -911,8 +911,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, > hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, > &graphic_level->MinVddc); > PP_ASSERT_WITH_CODE((0 == result), > - "can not find VDDC voltage value for VDDC \ > - engine clock dependency table", return result); > + "can not find VDDC voltage value for VDDC engine clock dependency table", return result); > > /* SCLK frequency in units of 10KHz*/ > graphic_level->SclkFrequency = engine_clock; > @@ -1678,8 +1677,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, > > if (0 != result) { > smu_data->smc_state_table.GraphicsBootLevel = 0; > - pr_err("VBIOS did not find boot engine clock value \ > - in dependency table. Using Graphics DPM level 0!"); > + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); > result = 0; > } > > @@ -1689,8 +1687,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, > > if (0 != result) { > smu_data->smc_state_table.MemoryBootLevel = 0; > - pr_err("VBIOS did not find boot engine clock value \ > - in dependency table. Using Memory DPM level 0!"); > + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n"); > result = 0; > } > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c > index 2f979fb86824..f6f39d01d227 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c > @@ -381,10 +381,8 @@ static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr) > (rev_id == 0xc1) || > (rev_id == 0xc3)))) { > if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) { > - pr_err("Your firmware(0x%x) doesn't match \ > - SMU9_DRIVER_IF_VERSION(0x%x). \ > - Please update your firmware!\n", > - smc_driver_if_version, SMU9_DRIVER_IF_VERSION); > + pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n", > + smc_driver_if_version, SMU9_DRIVER_IF_VERSION); > return -EINVAL; > } > } >
WARNING: multiple messages have this Message-ID (diff)
From: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org> To: Joe Perches <joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: "Alex Deucher" <alexander.deucher-5C7GfCeVMHo@public.gmane.org>, "David Airlie" <airlied-cv59FeDIM0c@public.gmane.org>, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, "Christian König" <christian.koenig-5C7GfCeVMHo@public.gmane.org>, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Subject: Re: [PATCH 2/4] drm: amd: Fix line continuation formats Date: Thu, 16 Nov 2017 10:38:41 -0500 [thread overview] Message-ID: <1b2c63b7-319a-caab-6809-197784c179ef@amd.com> (raw) In-Reply-To: <eee8836696843f983a9533d6441fa9f2d8cbe92f.1510845910.git.joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org> On 2017-11-16 10:27 AM, Joe Perches wrote: > Line continuations with excess spacing causes unexpected output. > > Miscellanea: > > o Added missing '\n' to a few of the coalesced pr_<level> formats > > Signed-off-by: Joe Perches <joe@perches.com> > --- > drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 11 ++++----- > .../amd/powerplay/hwmgr/process_pptables_v1_0.c | 6 ++--- > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 27 ++++++++-------------- > drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 6 ++--- > .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 9 +++----- > .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 6 ++--- > 6 files changed, 22 insertions(+), 43 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > index ced42484dcfc..6743786afcce 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > @@ -220,8 +220,7 @@ static void dpcd_set_lt_pattern_and_lane_settings( > size_in_bytes); > > dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING, > - "%s:\n %x VS set = %x PE set = %x \ > - max VS Reached = %x max PE Reached = %x\n", > + "%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", > __func__, > DP_TRAINING_LANE0_SET, > dpcd_lane[0].bits.VOLTAGE_SWING_SET, > @@ -558,8 +557,7 @@ static void dpcd_set_lane_settings( > */ > > dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING, > - "%s\n %x VS set = %x PE set = %x \ > - max VS Reached = %x max PE Reached = %x\n", > + "%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", > __func__, > DP_TRAINING_LANE0_SET, > dpcd_lane[0].bits.VOLTAGE_SWING_SET, > @@ -872,9 +870,8 @@ static bool perform_clock_recovery_sequence( > if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) { > ASSERT(0); > dm_logger_write(link->ctx->logger, LOG_ERROR, > - "%s: Link Training Error, could not \ > - get CR after %d tries. \ > - Possibly voltage swing issue", __func__, > + "%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue", Would probably be good to add a '\n' here as well but that's not the main intention of this patch. Either way patch is Reviewed-by: Harry Wentland <harry.wentland@amd.com> Harry > + __func__, > LINK_TRAINING_MAX_CR_RETRY); > > } > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c > index d1af1483c69b..813f827e4270 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c > @@ -523,8 +523,7 @@ static int get_pcie_table( > if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) > pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; > else > - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ > - Disregarding the excess entries... \n"); > + pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); > > pcie_table->count = pcie_count; > for (i = 0; i < pcie_count; i++) { > @@ -563,8 +562,7 @@ static int get_pcie_table( > if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) > pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; > else > - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ > - Disregarding the excess entries... \n"); > + pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); > > pcie_table->count = pcie_count; > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > index 4f79c21f27ed..9599fe0ba779 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > @@ -546,8 +546,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, > } > > if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) > - pr_info("Voltage value looks like a Leakage ID \ > - but it's not patched\n"); > + pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); > } > > /** > @@ -701,18 +700,14 @@ static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) > table_info->vdd_dep_on_mclk; > > PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, > - "VDD dependency on SCLK table is missing. \ > - This table is mandatory", return -EINVAL); > + "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL); > PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, > - "VDD dependency on SCLK table is empty. \ > - This table is mandatory", return -EINVAL); > + "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL); > > PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, > - "VDD dependency on MCLK table is missing. \ > - This table is mandatory", return -EINVAL); > + "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL); > PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, > - "VDD dependency on MCLK table is empty. \ > - This table is mandatory", return -EINVAL); > + "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL); > > table_info->max_clock_voltage_on_ac.sclk = > allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; > @@ -3415,8 +3410,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( > DPMTABLE_OD_UPDATE_SCLK)) { > result = vega10_populate_all_graphic_levels(hwmgr); > PP_ASSERT_WITH_CODE(!result, > - "Failed to populate SCLK during \ > - PopulateNewDPMClocksStates Function!", > + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", > return result); > } > > @@ -3425,8 +3419,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( > DPMTABLE_OD_UPDATE_MCLK)){ > result = vega10_populate_all_memory_levels(hwmgr); > PP_ASSERT_WITH_CODE(!result, > - "Failed to populate MCLK during \ > - PopulateNewDPMClocksStates Function!", > + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", > return result); > } > } else { > @@ -3543,8 +3536,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( > data->apply_optimized_settings) { > result = vega10_populate_all_graphic_levels(hwmgr); > PP_ASSERT_WITH_CODE(!result, > - "Failed to populate SCLK during \ > - PopulateNewDPMClocksStates Function!", > + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", > return result); > } > > @@ -3552,8 +3544,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( > (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { > result = vega10_populate_all_memory_levels(hwmgr); > PP_ASSERT_WITH_CODE(!result, > - "Failed to populate MCLK during \ > - PopulateNewDPMClocksStates Function!", > + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", > return result); > } > } > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c > index 4d672cd15785..ed4b37e566a3 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c > @@ -1732,8 +1732,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, > > if (0 != result) { > smu_data->smc_state_table.GraphicsBootLevel = 0; > - pr_err("VBIOS did not find boot engine clock value \ > - in dependency table. Using Graphics DPM level 0!"); > + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); > result = 0; > } > > @@ -1743,8 +1742,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, > > if (0 != result) { > smu_data->smc_state_table.MemoryBootLevel = 0; > - pr_err("VBIOS did not find boot engine clock value \ > - in dependency table. Using Memory DPM level 0!"); > + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n"); > result = 0; > } > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c > index 34128822b8fb..2ff682d44e8c 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c > @@ -911,8 +911,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, > hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, > &graphic_level->MinVddc); > PP_ASSERT_WITH_CODE((0 == result), > - "can not find VDDC voltage value for VDDC \ > - engine clock dependency table", return result); > + "can not find VDDC voltage value for VDDC engine clock dependency table", return result); > > /* SCLK frequency in units of 10KHz*/ > graphic_level->SclkFrequency = engine_clock; > @@ -1678,8 +1677,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, > > if (0 != result) { > smu_data->smc_state_table.GraphicsBootLevel = 0; > - pr_err("VBIOS did not find boot engine clock value \ > - in dependency table. Using Graphics DPM level 0!"); > + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); > result = 0; > } > > @@ -1689,8 +1687,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, > > if (0 != result) { > smu_data->smc_state_table.MemoryBootLevel = 0; > - pr_err("VBIOS did not find boot engine clock value \ > - in dependency table. Using Memory DPM level 0!"); > + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n"); > result = 0; > } > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c > index 2f979fb86824..f6f39d01d227 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c > @@ -381,10 +381,8 @@ static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr) > (rev_id == 0xc1) || > (rev_id == 0xc3)))) { > if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) { > - pr_err("Your firmware(0x%x) doesn't match \ > - SMU9_DRIVER_IF_VERSION(0x%x). \ > - Please update your firmware!\n", > - smc_driver_if_version, SMU9_DRIVER_IF_VERSION); > + pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n", > + smc_driver_if_version, SMU9_DRIVER_IF_VERSION); > return -EINVAL; > } > } > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2017-11-16 15:38 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-11-16 15:27 [PATCH 0/4] treewide: Fix line continuation formats Joe Perches 2017-11-16 15:27 ` Joe Perches 2017-11-16 15:27 ` Joe Perches 2017-11-16 15:27 ` [PATCH 1/4] rk3399_dmc: Fix line continuation format Joe Perches 2017-11-22 5:13 ` Chanwoo Choi 2017-11-22 10:41 ` Joe Perches [not found] ` <CGME20171116152742epcas2p22b17887a4d7f2adcd3beb414988dbce3@epcms1p1> 2017-11-23 1:21 ` MyungJoo Ham 2017-11-23 1:21 ` MyungJoo Ham 2017-11-23 1:45 ` Chanwoo Choi 2017-11-23 2:07 ` Joe Perches 2017-11-23 2:12 ` Chanwoo Choi 2017-11-23 2:18 ` Joe Perches 2017-11-23 2:23 ` Chanwoo Choi 2017-11-23 2:29 ` Joe Perches 2017-11-23 2:35 ` Chanwoo Choi 2017-11-23 2:38 ` Joe Perches 2017-11-16 15:27 ` [PATCH 2/4] drm: amd: Fix line continuation formats Joe Perches 2017-11-16 15:27 ` Joe Perches 2017-11-16 15:38 ` Harry Wentland [this message] 2017-11-16 15:38 ` Harry Wentland 2017-11-16 15:50 ` Joe Perches 2017-11-16 15:50 ` Joe Perches 2017-11-17 19:52 ` Alex Deucher 2017-11-17 19:52 ` Alex Deucher 2017-11-16 15:27 ` [PATCH 3/4] [media] dibx000_common: Fix line continuation format Joe Perches 2017-11-16 15:27 ` [PATCH 4/4] ima: " Joe Perches 2017-11-16 15:27 ` Joe Perches 2017-11-16 17:11 ` [PATCH 0/4] treewide: Fix line continuation formats Mimi Zohar 2017-11-16 17:11 ` Mimi Zohar 2017-11-16 17:11 ` Mimi Zohar 2017-11-16 17:17 ` Joe Perches 2017-11-16 17:17 ` Joe Perches 2017-11-16 19:35 ` Mimi Zohar 2017-11-16 19:35 ` Mimi Zohar
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1b2c63b7-319a-caab-6809-197784c179ef@amd.com \ --to=harry.wentland@amd.com \ --cc=airlied@linux.ie \ --cc=alexander.deucher@amd.com \ --cc=amd-gfx@lists.freedesktop.org \ --cc=christian.koenig@amd.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=joe@perches.com \ --cc=linux-kernel@vger.kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.