* [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-10-02 19:27 ` Ville Syrjälä
2021-09-28 22:57 ` [Intel-gfx] [PATCH 02/24] drm/i915/pm: drop get_fifo_size vfunc Jani Nikula
` (26 subsequent siblings)
27 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
constify it while here. drop the put function since it was never
overloaded and always has done the same thing, no point in
indirecting it for show.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 70 ++++++++++++++++-------------
drivers/gpu/drm/i915/intel_uncore.h | 7 +--
2 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 678a99de07fe..aee572af8052 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -36,6 +36,12 @@
#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
+static void
+fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+{
+ uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
+}
+
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
{
@@ -248,7 +254,7 @@ fw_domain_put(const struct intel_uncore_forcewake_domain *d)
}
static void
-fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
{
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
@@ -396,7 +402,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
GEM_BUG_ON(!domain->wake_count);
if (--domain->wake_count == 0)
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
spin_unlock_irqrestore(&uncore->lock, irqflags);
@@ -454,7 +460,7 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
fw = uncore->fw_domains_active;
if (fw)
- uncore->funcs.force_wake_put(uncore, fw);
+ fw_domains_put(uncore, fw);
fw_domains_reset(uncore, uncore->fw_domains);
assert_forcewakes_inactive(uncore);
@@ -562,7 +568,7 @@ static void forcewake_early_sanitize(struct intel_uncore *uncore,
intel_uncore_forcewake_reset(uncore);
if (restore_forcewake) {
spin_lock_irq(&uncore->lock);
- uncore->funcs.force_wake_get(uncore, restore_forcewake);
+ fw_domains_get(uncore, restore_forcewake);
if (intel_uncore_has_fifo(uncore))
uncore->fifo_count = fifo_free_entries(uncore);
@@ -623,7 +629,7 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
}
if (fw_domains)
- uncore->funcs.force_wake_get(uncore, fw_domains);
+ fw_domains_get(uncore, fw_domains);
}
/**
@@ -644,7 +650,7 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
assert_rpm_wakelock_held(uncore->rpm);
@@ -711,7 +717,7 @@ void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_get(uncore, fw_domains);
@@ -733,7 +739,7 @@ static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
continue;
}
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
}
}
@@ -750,7 +756,7 @@ void intel_uncore_forcewake_put(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
spin_lock_irqsave(&uncore->lock, irqflags);
@@ -769,7 +775,7 @@ void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
struct intel_uncore_forcewake_domain *domain;
unsigned int tmp;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
fw_domains &= uncore->fw_domains;
@@ -793,7 +799,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_put(uncore, fw_domains);
@@ -801,7 +807,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
void assert_forcewakes_inactive(struct intel_uncore *uncore)
{
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
drm_WARN(&uncore->i915->drm, uncore->fw_domains_active,
@@ -818,7 +824,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
return;
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
spin_lock_irq(&uncore->lock);
@@ -1587,7 +1593,7 @@ static noinline void ___force_wake_auto(struct intel_uncore *uncore,
for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
fw_domain_arm_timer(domain);
- uncore->funcs.force_wake_get(uncore, fw_domains);
+ fw_domains_get(uncore, fw_domains);
}
static inline void __force_wake_auto(struct intel_uncore *uncore,
@@ -1837,6 +1843,18 @@ static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
fw_domain_fini(uncore, d->id);
}
+static const struct intel_uncore_fw_get uncore_get_fallback = {
+ .force_wake_get = fw_domains_get_with_fallback
+};
+
+static const struct intel_uncore_fw_get uncore_get_normal = {
+ .force_wake_get = fw_domains_get_normal,
+};
+
+static const struct intel_uncore_fw_get uncore_get_thread_status = {
+ .force_wake_get = fw_domains_get_with_thread_status
+};
+
static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
@@ -1852,8 +1870,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
intel_engine_mask_t emask = INTEL_INFO(i915)->platform_engine_mask;
int i;
- uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
- uncore->funcs.force_wake_put = fw_domains_put;
+ uncore->fw_get_funcs = &uncore_get_fallback;
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_RENDER_GEN9,
FORCEWAKE_ACK_RENDER_GEN9);
@@ -1878,8 +1895,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
}
} else if (IS_GRAPHICS_VER(i915, 9, 10)) {
- uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
- uncore->funcs.force_wake_put = fw_domains_put;
+ uncore->fw_get_funcs = &uncore_get_fallback;
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_RENDER_GEN9,
FORCEWAKE_ACK_RENDER_GEN9);
@@ -1889,16 +1905,13 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
- uncore->funcs.force_wake_get = fw_domains_get;
- uncore->funcs.force_wake_put = fw_domains_put;
+ uncore->fw_get_funcs = &uncore_get_normal;
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
- uncore->funcs.force_wake_get =
- fw_domains_get_with_thread_status;
- uncore->funcs.force_wake_put = fw_domains_put;
+ uncore->fw_get_funcs = &uncore_get_thread_status;
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
} else if (IS_IVYBRIDGE(i915)) {
@@ -1913,9 +1926,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
* (correctly) interpreted by the test below as MT
* forcewake being disabled.
*/
- uncore->funcs.force_wake_get =
- fw_domains_get_with_thread_status;
- uncore->funcs.force_wake_put = fw_domains_put;
+ uncore->fw_get_funcs = &uncore_get_thread_status;
/* We need to init first for ECOBUS access and then
* determine later if we want to reinit, in case of MT access is
@@ -1946,9 +1957,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
FORCEWAKE, FORCEWAKE_ACK);
}
} else if (GRAPHICS_VER(i915) == 6) {
- uncore->funcs.force_wake_get =
- fw_domains_get_with_thread_status;
- uncore->funcs.force_wake_put = fw_domains_put;
+ uncore->fw_get_funcs = &uncore_get_thread_status;
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE, FORCEWAKE_ACK);
}
@@ -2165,8 +2174,7 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
}
/* make sure fw funcs are set if and only if we have fw*/
- GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get);
- GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put);
+ GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->fw_get_funcs);
GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 2f31c50eeae2..3248e4e2c540 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -84,12 +84,12 @@ enum forcewake_domains {
FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1,
};
-struct intel_uncore_funcs {
+struct intel_uncore_fw_get {
void (*force_wake_get)(struct intel_uncore *uncore,
enum forcewake_domains domains);
- void (*force_wake_put)(struct intel_uncore *uncore,
- enum forcewake_domains domains);
+};
+struct intel_uncore_funcs {
enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
i915_reg_t r);
enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
@@ -150,6 +150,7 @@ struct intel_uncore {
unsigned int shadowed_reg_table_entries;
struct notifier_block pmic_bus_access_nb;
+ const struct intel_uncore_fw_get *fw_get_funcs;
struct intel_uncore_funcs funcs;
unsigned int fifo_count;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc
2021-09-28 22:57 ` [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc Jani Nikula
@ 2021-10-02 19:27 ` Ville Syrjälä
2021-10-04 0:33 ` Dave Airlie
2021-10-04 7:44 ` Sarvela, Tomi P
0 siblings, 2 replies; 36+ messages in thread
From: Ville Syrjälä @ 2021-10-02 19:27 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Dave Airlie, Dave Airlie, Sarvela, Tomi P
On Wed, Sep 29, 2021 at 01:57:45AM +0300, Jani Nikula wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> constify it while here. drop the put function since it was never
> overloaded and always has done the same thing, no point in
> indirecting it for show.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This has totally broken snb and ivb machines. Total death
ensues somewhere in uncore init after some backtraces fly by.
Didn't get any logs out to disk unfortunately. Please revert.
Sadly CI is still afraid to report when machines disappear.
For the bat report you at least get a list of machines that
were awol, but the shard run seems to not even mention that
all snbs suddenly vanished.
I've said it before and I'll say it again. We really should
*not* be loading i915 when the machine boots. That way we'd
at least get the machine up and running and can report that
loading i915 is the thing that killed it...
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 70 ++++++++++++++++-------------
> drivers/gpu/drm/i915/intel_uncore.h | 7 +--
> 2 files changed, 43 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 678a99de07fe..aee572af8052 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -36,6 +36,12 @@
>
> #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
>
> +static void
> +fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
> +{
> + uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
> +}
> +
> void
> intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
> {
> @@ -248,7 +254,7 @@ fw_domain_put(const struct intel_uncore_forcewake_domain *d)
> }
>
> static void
> -fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
> +fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
> {
> struct intel_uncore_forcewake_domain *d;
> unsigned int tmp;
> @@ -396,7 +402,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
>
> GEM_BUG_ON(!domain->wake_count);
> if (--domain->wake_count == 0)
> - uncore->funcs.force_wake_put(uncore, domain->mask);
> + fw_domains_put(uncore, domain->mask);
>
> spin_unlock_irqrestore(&uncore->lock, irqflags);
>
> @@ -454,7 +460,7 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
>
> fw = uncore->fw_domains_active;
> if (fw)
> - uncore->funcs.force_wake_put(uncore, fw);
> + fw_domains_put(uncore, fw);
>
> fw_domains_reset(uncore, uncore->fw_domains);
> assert_forcewakes_inactive(uncore);
> @@ -562,7 +568,7 @@ static void forcewake_early_sanitize(struct intel_uncore *uncore,
> intel_uncore_forcewake_reset(uncore);
> if (restore_forcewake) {
> spin_lock_irq(&uncore->lock);
> - uncore->funcs.force_wake_get(uncore, restore_forcewake);
> + fw_domains_get(uncore, restore_forcewake);
>
> if (intel_uncore_has_fifo(uncore))
> uncore->fifo_count = fifo_free_entries(uncore);
> @@ -623,7 +629,7 @@ static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
> }
>
> if (fw_domains)
> - uncore->funcs.force_wake_get(uncore, fw_domains);
> + fw_domains_get(uncore, fw_domains);
> }
>
> /**
> @@ -644,7 +650,7 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
> {
> unsigned long irqflags;
>
> - if (!uncore->funcs.force_wake_get)
> + if (!uncore->fw_get_funcs)
> return;
>
> assert_rpm_wakelock_held(uncore->rpm);
> @@ -711,7 +717,7 @@ void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
> {
> lockdep_assert_held(&uncore->lock);
>
> - if (!uncore->funcs.force_wake_get)
> + if (!uncore->fw_get_funcs)
> return;
>
> __intel_uncore_forcewake_get(uncore, fw_domains);
> @@ -733,7 +739,7 @@ static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
> continue;
> }
>
> - uncore->funcs.force_wake_put(uncore, domain->mask);
> + fw_domains_put(uncore, domain->mask);
> }
> }
>
> @@ -750,7 +756,7 @@ void intel_uncore_forcewake_put(struct intel_uncore *uncore,
> {
> unsigned long irqflags;
>
> - if (!uncore->funcs.force_wake_put)
> + if (!uncore->fw_get_funcs)
> return;
>
> spin_lock_irqsave(&uncore->lock, irqflags);
> @@ -769,7 +775,7 @@ void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
> struct intel_uncore_forcewake_domain *domain;
> unsigned int tmp;
>
> - if (!uncore->funcs.force_wake_put)
> + if (!uncore->fw_get_funcs)
> return;
>
> fw_domains &= uncore->fw_domains;
> @@ -793,7 +799,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
> {
> lockdep_assert_held(&uncore->lock);
>
> - if (!uncore->funcs.force_wake_put)
> + if (!uncore->fw_get_funcs)
> return;
>
> __intel_uncore_forcewake_put(uncore, fw_domains);
> @@ -801,7 +807,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
>
> void assert_forcewakes_inactive(struct intel_uncore *uncore)
> {
> - if (!uncore->funcs.force_wake_get)
> + if (!uncore->fw_get_funcs)
> return;
>
> drm_WARN(&uncore->i915->drm, uncore->fw_domains_active,
> @@ -818,7 +824,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
> if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
> return;
>
> - if (!uncore->funcs.force_wake_get)
> + if (!uncore->fw_get_funcs)
> return;
>
> spin_lock_irq(&uncore->lock);
> @@ -1587,7 +1593,7 @@ static noinline void ___force_wake_auto(struct intel_uncore *uncore,
> for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
> fw_domain_arm_timer(domain);
>
> - uncore->funcs.force_wake_get(uncore, fw_domains);
> + fw_domains_get(uncore, fw_domains);
> }
>
> static inline void __force_wake_auto(struct intel_uncore *uncore,
> @@ -1837,6 +1843,18 @@ static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
> fw_domain_fini(uncore, d->id);
> }
>
> +static const struct intel_uncore_fw_get uncore_get_fallback = {
> + .force_wake_get = fw_domains_get_with_fallback
> +};
> +
> +static const struct intel_uncore_fw_get uncore_get_normal = {
> + .force_wake_get = fw_domains_get_normal,
> +};
> +
> +static const struct intel_uncore_fw_get uncore_get_thread_status = {
> + .force_wake_get = fw_domains_get_with_thread_status
> +};
> +
> static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> {
> struct drm_i915_private *i915 = uncore->i915;
> @@ -1852,8 +1870,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> intel_engine_mask_t emask = INTEL_INFO(i915)->platform_engine_mask;
> int i;
>
> - uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
> - uncore->funcs.force_wake_put = fw_domains_put;
> + uncore->fw_get_funcs = &uncore_get_fallback;
> fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_RENDER_GEN9,
> FORCEWAKE_ACK_RENDER_GEN9);
> @@ -1878,8 +1895,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
> }
> } else if (IS_GRAPHICS_VER(i915, 9, 10)) {
> - uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
> - uncore->funcs.force_wake_put = fw_domains_put;
> + uncore->fw_get_funcs = &uncore_get_fallback;
> fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_RENDER_GEN9,
> FORCEWAKE_ACK_RENDER_GEN9);
> @@ -1889,16 +1905,13 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
> FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
> } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> - uncore->funcs.force_wake_get = fw_domains_get;
> - uncore->funcs.force_wake_put = fw_domains_put;
> + uncore->fw_get_funcs = &uncore_get_normal;
> fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
> fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
> FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> - uncore->funcs.force_wake_get =
> - fw_domains_get_with_thread_status;
> - uncore->funcs.force_wake_put = fw_domains_put;
> + uncore->fw_get_funcs = &uncore_get_thread_status;
> fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
> } else if (IS_IVYBRIDGE(i915)) {
> @@ -1913,9 +1926,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> * (correctly) interpreted by the test below as MT
> * forcewake being disabled.
> */
> - uncore->funcs.force_wake_get =
> - fw_domains_get_with_thread_status;
> - uncore->funcs.force_wake_put = fw_domains_put;
> + uncore->fw_get_funcs = &uncore_get_thread_status;
>
> /* We need to init first for ECOBUS access and then
> * determine later if we want to reinit, in case of MT access is
> @@ -1946,9 +1957,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> FORCEWAKE, FORCEWAKE_ACK);
> }
> } else if (GRAPHICS_VER(i915) == 6) {
> - uncore->funcs.force_wake_get =
> - fw_domains_get_with_thread_status;
> - uncore->funcs.force_wake_put = fw_domains_put;
> + uncore->fw_get_funcs = &uncore_get_thread_status;
> fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> FORCEWAKE, FORCEWAKE_ACK);
> }
> @@ -2165,8 +2174,7 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
> }
>
> /* make sure fw funcs are set if and only if we have fw*/
> - GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get);
> - GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put);
> + GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->fw_get_funcs);
> GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
> GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 2f31c50eeae2..3248e4e2c540 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -84,12 +84,12 @@ enum forcewake_domains {
> FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1,
> };
>
> -struct intel_uncore_funcs {
> +struct intel_uncore_fw_get {
> void (*force_wake_get)(struct intel_uncore *uncore,
> enum forcewake_domains domains);
> - void (*force_wake_put)(struct intel_uncore *uncore,
> - enum forcewake_domains domains);
> +};
>
> +struct intel_uncore_funcs {
> enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
> i915_reg_t r);
> enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
> @@ -150,6 +150,7 @@ struct intel_uncore {
> unsigned int shadowed_reg_table_entries;
>
> struct notifier_block pmic_bus_access_nb;
> + const struct intel_uncore_fw_get *fw_get_funcs;
> struct intel_uncore_funcs funcs;
>
> unsigned int fifo_count;
> --
> 2.30.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc
2021-10-02 19:27 ` Ville Syrjälä
@ 2021-10-04 0:33 ` Dave Airlie
2021-10-04 7:03 ` Saarinen, Jani
2021-10-04 7:44 ` Sarvela, Tomi P
1 sibling, 1 reply; 36+ messages in thread
From: Dave Airlie @ 2021-10-04 0:33 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Jani Nikula, Intel Graphics Development, Dave Airlie, Sarvela, Tomi P
On Sun, 3 Oct 2021 at 05:27, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
>
> On Wed, Sep 29, 2021 at 01:57:45AM +0300, Jani Nikula wrote:
> > From: Dave Airlie <airlied@redhat.com>
> >
> > constify it while here. drop the put function since it was never
> > overloaded and always has done the same thing, no point in
> > indirecting it for show.
> >
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Dave Airlie <airlied@redhat.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> This has totally broken snb and ivb machines. Total death
> ensues somewhere in uncore init after some backtraces fly by.
> Didn't get any logs out to disk unfortunately. Please revert.
>
> Sadly CI is still afraid to report when machines disappear.
> For the bat report you at least get a list of machines that
> were awol, but the shard run seems to not even mention that
> all snbs suddenly vanished.
>
> I've said it before and I'll say it again. We really should
> *not* be loading i915 when the machine boots. That way we'd
> at least get the machine up and running and can report that
> loading i915 is the thing that killed it...
That is frustrating, I've sent a oneline fix that should fix it up.
hopefully CI will pick it up.
Dave.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc
2021-10-04 0:33 ` Dave Airlie
@ 2021-10-04 7:03 ` Saarinen, Jani
2021-10-04 7:45 ` Jani Nikula
0 siblings, 1 reply; 36+ messages in thread
From: Saarinen, Jani @ 2021-10-04 7:03 UTC (permalink / raw)
To: Dave Airlie, Ville Syrjälä
Cc: Nikula, Jani, Intel Graphics Development, Dave Airlie, Sarvela, Tomi P
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Dave Airlie
> Sent: maanantai 4. lokakuuta 2021 3.33
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Nikula, Jani <jani.nikula@intel.com>; Intel Graphics Development <intel-
> gfx@lists.freedesktop.org>; Dave Airlie <airlied@redhat.com>; Sarvela, Tomi P
> <tomi.p.sarvela@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function
> into separate vfunc
>
> On Sun, 3 Oct 2021 at 05:27, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >
> > On Wed, Sep 29, 2021 at 01:57:45AM +0300, Jani Nikula wrote:
> > > From: Dave Airlie <airlied@redhat.com>
> > >
> > > constify it while here. drop the put function since it was never
> > > overloaded and always has done the same thing, no point in
> > > indirecting it for show.
> > >
> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > > Signed-off-by: Dave Airlie <airlied@redhat.com>
> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >
> > This has totally broken snb and ivb machines. Total death ensues
> > somewhere in uncore init after some backtraces fly by.
> > Didn't get any logs out to disk unfortunately. Please revert.
> >
> > Sadly CI is still afraid to report when machines disappear.
> > For the bat report you at least get a list of machines that were awol,
> > but the shard run seems to not even mention that all snbs suddenly
> > vanished.
> >
> > I've said it before and I'll say it again. We really should
> > *not* be loading i915 when the machine boots. That way we'd at least
> > get the machine up and running and can report that loading i915 is the
> > thing that killed it...
>
> That is frustrating, I've sent a oneline fix that should fix it up.
> hopefully CI will pick it up.
It seems it did (this for ivb, snb only):
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21231/index.html?hosts=snb%7Civb
>
> Dave.
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc
2021-10-04 7:03 ` Saarinen, Jani
@ 2021-10-04 7:45 ` Jani Nikula
0 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-10-04 7:45 UTC (permalink / raw)
To: Saarinen, Jani, Dave Airlie, Ville Syrjälä
Cc: Intel Graphics Development, Dave Airlie, Sarvela, Tomi P
On Mon, 04 Oct 2021, "Saarinen, Jani" <jani.saarinen@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Dave Airlie
>> Sent: maanantai 4. lokakuuta 2021 3.33
>> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Intel Graphics Development <intel-
>> gfx@lists.freedesktop.org>; Dave Airlie <airlied@redhat.com>; Sarvela, Tomi P
>> <tomi.p.sarvela@intel.com>
>> Subject: Re: [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function
>> into separate vfunc
>>
>> On Sun, 3 Oct 2021 at 05:27, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> >
>> > On Wed, Sep 29, 2021 at 01:57:45AM +0300, Jani Nikula wrote:
>> > > From: Dave Airlie <airlied@redhat.com>
>> > >
>> > > constify it while here. drop the put function since it was never
>> > > overloaded and always has done the same thing, no point in
>> > > indirecting it for show.
>> > >
>> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> > > Signed-off-by: Dave Airlie <airlied@redhat.com>
>> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >
>> > This has totally broken snb and ivb machines. Total death ensues
>> > somewhere in uncore init after some backtraces fly by.
>> > Didn't get any logs out to disk unfortunately. Please revert.
>> >
>> > Sadly CI is still afraid to report when machines disappear.
>> > For the bat report you at least get a list of machines that were awol,
>> > but the shard run seems to not even mention that all snbs suddenly
>> > vanished.
>> >
>> > I've said it before and I'll say it again. We really should
>> > *not* be loading i915 when the machine boots. That way we'd at least
>> > get the machine up and running and can report that loading i915 is the
>> > thing that killed it...
>>
>> That is frustrating, I've sent a oneline fix that should fix it up.
>> hopefully CI will pick it up.
> It seems it did (this for ivb, snb only):
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21231/index.html?hosts=snb%7Civb
Pushed now.
BR,
Jani.
>
>>
>> Dave.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc
2021-10-02 19:27 ` Ville Syrjälä
2021-10-04 0:33 ` Dave Airlie
@ 2021-10-04 7:44 ` Sarvela, Tomi P
1 sibling, 0 replies; 36+ messages in thread
From: Sarvela, Tomi P @ 2021-10-04 7:44 UTC (permalink / raw)
To: Ville Syrjälä, Nikula, Jani, Latvala, Petri
Cc: intel-gfx, Dave Airlie, Dave Airlie
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> On Wed, Sep 29, 2021 at 01:57:45AM +0300, Jani Nikula wrote:
> > From: Dave Airlie <airlied@redhat.com>
> >
> > constify it while here. drop the put function since it was never
> > overloaded and always has done the same thing, no point in
> > indirecting it for show.
> >
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Dave Airlie <airlied@redhat.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> This has totally broken snb and ivb machines. Total death
> ensues somewhere in uncore init after some backtraces fly by.
> Didn't get any logs out to disk unfortunately. Please revert.
>
> Sadly CI is still afraid to report when machines disappear.
> For the bat report you at least get a list of machines that
> were awol, but the shard run seems to not even mention that
> all snbs suddenly vanished.
>
> I've said it before and I'll say it again. We really should
> *not* be loading i915 when the machine boots. That way we'd
> at least get the machine up and running and can report that
> loading i915 is the thing that killed it...
Added Petri Latvala
The best way to handle i915 loading in BAT would be to blacklist
i915 in boot and have igt@i915_module_load@load as the first
thing in fast-feedback.testlist. This would catch any i915 issue
to a test and we wouldn't need to do tricks with ci@boot
pseudotest.
Most of the CI parts are already in place. The IGT commit to
change fast-feedback needs to be coordinated.
Tomi
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 02/24] drm/i915/pm: drop get_fifo_size vfunc.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 03/24] drm/i915: make update_wm take a dev_priv Jani Nikula
` (25 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
The i845_update_wm code was always calling the i845 variant,
and the i9xx_update_wm had only a choice between i830 and i9xx
paths, hardly worth the vfunc overhead.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++---------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 804c2a470e94..db0aa5bb4d18 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -330,8 +330,6 @@ struct drm_i915_display_funcs {
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe);
int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
- int (*get_fifo_size)(struct drm_i915_private *dev_priv,
- enum i9xx_plane_id i9xx_plane);
int (*compute_pipe_wm)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_intermediate_wm)(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 97b68bbbc689..0e0309733c79 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2342,7 +2342,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
else
wm_info = &i830_a_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+ if (DISPLAY_VER(dev_priv) == 2)
+ fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
+ else
+ fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2369,7 +2372,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
if (DISPLAY_VER(dev_priv) == 2)
wm_info = &i830_bc_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+ if (DISPLAY_VER(dev_priv) == 2)
+ fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
+ else
+ fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2485,7 +2491,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
pipe_mode = &crtc->config->hw.pipe_mode;
planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
&i845_wm_info,
- dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
+ i845_get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm;
@@ -8052,15 +8058,11 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.update_wm = i965_update_wm;
} else if (DISPLAY_VER(dev_priv) == 3) {
dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (DISPLAY_VER(dev_priv) == 2) {
- if (INTEL_NUM_PIPES(dev_priv) == 1) {
+ if (INTEL_NUM_PIPES(dev_priv) == 1)
dev_priv->display.update_wm = i845_update_wm;
- dev_priv->display.get_fifo_size = i845_get_fifo_size;
- } else {
+ else
dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i830_get_fifo_size;
- }
} else {
drm_err(&dev_priv->drm,
"unexpected fall-through in %s\n", __func__);
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 03/24] drm/i915: make update_wm take a dev_priv.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 02/24] drm/i915/pm: drop get_fifo_size vfunc Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 04/24] drm/i915/wm: provide wrappers around watermark vfuncs calls (v3) Jani Nikula
` (24 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
The crtc was never being used here.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 20 +++++++-------------
drivers/gpu/drm/i915/intel_pm.h | 2 +-
4 files changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f27c294beb92..566a7d2feb1a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2383,7 +2383,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
hsw_enable_ips(new_crtc_state);
@@ -2540,7 +2540,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else if (new_crtc_state->update_wm_pre)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
}
/*
@@ -3587,7 +3587,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
intel_enable_transcoder(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3654,7 +3654,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
@@ -3730,7 +3730,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
encoder->base.crtc = NULL;
intel_fbc_disable(crtc);
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
intel_disable_shared_dpll(crtc_state);
intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index db0aa5bb4d18..90e2f44e2deb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -341,7 +341,7 @@ struct drm_i915_display_funcs {
void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
- void (*update_wm)(struct intel_crtc *crtc);
+ void (*update_wm)(struct drm_i915_private *dev_priv);
int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
/* Returns the active state of the crtc, and if the crtc is active,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0e0309733c79..226f456cde3a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -881,9 +881,8 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
return enabled;
}
-static void pnv_update_wm(struct intel_crtc *unused_crtc)
+static void pnv_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct cxsr_latency *latency;
u32 reg;
@@ -2248,9 +2247,8 @@ static void vlv_optimize_watermarks(struct intel_atomic_state *state,
mutex_unlock(&dev_priv->wm.wm_mutex);
}
-static void i965_update_wm(struct intel_crtc *unused_crtc)
+static void i965_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
@@ -2324,9 +2322,8 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
#undef FW_WM
-static void i9xx_update_wm(struct intel_crtc *unused_crtc)
+static void i9xx_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
const struct intel_watermark_params *wm_info;
u32 fwater_lo;
u32 fwater_hi;
@@ -2476,9 +2473,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
intel_set_memory_cxsr(dev_priv, true);
}
-static void i845_update_wm(struct intel_crtc *unused_crtc)
+static void i845_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct drm_display_mode *pipe_mode;
u32 fwater_lo;
@@ -7136,7 +7132,7 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
/**
* intel_update_watermarks - update FIFO watermark values based on current modes
- * @crtc: the #intel_crtc on which to compute the WM
+ * @dev_priv: i915 device
*
* Calculate watermark values for the various WM regs based on current mode
* and plane configuration.
@@ -7167,12 +7163,10 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
* We don't use the sprite, so we can ignore that. And on Crestline we have
* to set the non-SR watermarks to 8.
*/
-void intel_update_watermarks(struct intel_crtc *crtc)
+void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
if (dev_priv->display.update_wm)
- dev_priv->display.update_wm(crtc);
+ dev_priv->display.update_wm(dev_priv);
}
void intel_enable_ipc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 941b3ae555c8..99bce0b4f5fb 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -29,7 +29,7 @@ struct skl_wm_level;
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
void intel_suspend_hw(struct drm_i915_private *dev_priv);
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
-void intel_update_watermarks(struct intel_crtc *crtc);
+void intel_update_watermarks(struct drm_i915_private *dev_priv);
void intel_init_pm(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_i915_private *dev_priv);
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 04/24] drm/i915/wm: provide wrappers around watermark vfuncs calls (v3)
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (2 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 03/24] drm/i915: make update_wm take a dev_priv Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 05/24] drm/i915: add wrappers around cdclk vtable funcs Jani Nikula
` (23 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This moves one wrapper from the pm->display side, and creates
wrappers for all the others, this should simplify things later.
One thing to note is that the code checks the existance of some
of these ptrs, so the wrappers are a bit complicated by that.
Suggested by Jani.
v2: fixup warnings in wrong place error.
v3 by Jani: fix intel_compute_global_watermarks() return value check
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 186 ++++++++++++-------
drivers/gpu/drm/i915/intel_pm.c | 39 ----
drivers/gpu/drm/i915/intel_pm.h | 1 -
3 files changed, 124 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 566a7d2feb1a..1c5c8834b333 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -126,6 +126,102 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
+
+/**
+ * intel_update_watermarks - update FIFO watermark values based on current modes
+ * @dev_priv: i915 device
+ *
+ * Calculate watermark values for the various WM regs based on current mode
+ * and plane configuration.
+ *
+ * There are several cases to deal with here:
+ * - normal (i.e. non-self-refresh)
+ * - self-refresh (SR) mode
+ * - lines are large relative to FIFO size (buffer can hold up to 2)
+ * - lines are small relative to FIFO size (buffer can hold more than 2
+ * lines), so need to account for TLB latency
+ *
+ * The normal calculation is:
+ * watermark = dotclock * bytes per pixel * latency
+ * where latency is platform & configuration dependent (we assume pessimal
+ * values here).
+ *
+ * The SR calculation is:
+ * watermark = (trunc(latency/line time)+1) * surface width *
+ * bytes per pixel
+ * where
+ * line time = htotal / dotclock
+ * surface width = hdisplay for normal plane and 64 for cursor
+ * and latency is assumed to be high, as above.
+ *
+ * The final value programmed to the register should always be rounded up,
+ * and include an extra 2 entries to account for clock crossings.
+ *
+ * We don't use the sprite, so we can ignore that. And on Crestline we have
+ * to set the non-SR watermarks to 8.
+ */
+static void intel_update_watermarks(struct drm_i915_private *dev_priv)
+{
+ if (dev_priv->display.update_wm)
+ dev_priv->display.update_wm(dev_priv);
+}
+
+static int intel_compute_pipe_wm(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_pipe_wm)
+ return dev_priv->display.compute_pipe_wm(state, crtc);
+ return 0;
+}
+
+static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (!dev_priv->display.compute_intermediate_wm)
+ return 0;
+ if (drm_WARN_ON(&dev_priv->drm,
+ !dev_priv->display.compute_pipe_wm))
+ return 0;
+ return dev_priv->display.compute_intermediate_wm(state, crtc);
+}
+
+static bool intel_initial_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.initial_watermarks) {
+ dev_priv->display.initial_watermarks(state, crtc);
+ return true;
+ }
+ return false;
+}
+
+static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.atomic_update_watermarks)
+ dev_priv->display.atomic_update_watermarks(state, crtc);
+}
+
+static void intel_optimize_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.optimize_watermarks)
+ dev_priv->display.optimize_watermarks(state, crtc);
+}
+
+static int intel_compute_global_watermarks(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_global_watermarks)
+ return dev_priv->display.compute_global_watermarks(state);
+ return 0;
+}
+
/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
@@ -2537,9 +2633,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
* we'll continue to update watermarks the old way, if flags tell
* us to.
*/
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
- else if (new_crtc_state->update_wm_pre)
+ if (!intel_initial_watermarks(state, crtc))
+ if (new_crtc_state->update_wm_pre)
intel_update_watermarks(dev_priv);
}
@@ -2912,8 +3007,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ intel_initial_watermarks(state, crtc);
intel_enable_transcoder(new_crtc_state);
if (new_crtc_state->has_pch_encoder)
@@ -3123,8 +3217,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) >= 11)
icl_set_pipe_chicken(new_crtc_state);
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ intel_initial_watermarks(state, crtc);
if (DISPLAY_VER(dev_priv) >= 11) {
const struct intel_dbuf_state *dbuf_state =
@@ -3541,7 +3634,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
- dev_priv->display.initial_watermarks(state, crtc);
+ intel_initial_watermarks(state, crtc);
intel_enable_transcoder(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3584,10 +3677,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
- else
- intel_update_watermarks(dev_priv);
+ if (!intel_initial_watermarks(state, crtc))
+ intel_update_watermarks(dev_priv);
intel_enable_transcoder(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -6765,32 +6856,23 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
return ret;
}
- if (dev_priv->display.compute_pipe_wm) {
- ret = dev_priv->display.compute_pipe_wm(state, crtc);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Target pipe watermarks are invalid\n");
- return ret;
- }
-
+ ret = intel_compute_pipe_wm(state, crtc);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Target pipe watermarks are invalid\n");
+ return ret;
}
- if (dev_priv->display.compute_intermediate_wm) {
- if (drm_WARN_ON(&dev_priv->drm,
- !dev_priv->display.compute_pipe_wm))
- return 0;
-
- /*
- * Calculate 'intermediate' watermarks that satisfy both the
- * old state and the new state. We can program these
- * immediately.
- */
- ret = dev_priv->display.compute_intermediate_wm(state, crtc);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "No valid intermediate pipe watermarks are possible\n");
- return ret;
- }
+ /*
+ * Calculate 'intermediate' watermarks that satisfy both the
+ * old state and the new state. We can program these
+ * immediately.
+ */
+ ret = intel_compute_intermediate_wm(state, crtc);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No valid intermediate pipe watermarks are possible\n");
+ return ret;
}
if (DISPLAY_VER(dev_priv) >= 9) {
@@ -8883,23 +8965,6 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
return 0;
}
-/*
- * Handle calculation of various watermark data at the end of the atomic check
- * phase. The code here should be run after the per-crtc and per-plane 'check'
- * handlers to ensure that all derived state has been updated.
- */
-static int calc_watermark_data(struct intel_atomic_state *state)
-{
- struct drm_device *dev = state->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- /* Is there platform-specific watermark information to calculate? */
- if (dev_priv->display.compute_global_watermarks)
- return dev_priv->display.compute_global_watermarks(state);
-
- return 0;
-}
-
static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
@@ -9546,7 +9611,7 @@ static int intel_atomic_check(struct drm_device *dev,
goto fail;
intel_fbc_choose_crtc(dev_priv, state);
- ret = calc_watermark_data(state);
+ ret = intel_compute_global_watermarks(state);
if (ret)
goto fail;
@@ -9720,8 +9785,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
- if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state, crtc);
+ intel_atomic_update_watermarks(state, crtc);
}
static void commit_pipe_post_planes(struct intel_atomic_state *state,
@@ -9848,9 +9912,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
/* FIXME unify this for all platforms */
if (!new_crtc_state->hw.active &&
- !HAS_GMCH(dev_priv) &&
- dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ !HAS_GMCH(dev_priv))
+ intel_initial_watermarks(state, crtc);
}
static void intel_commit_modeset_disables(struct intel_atomic_state *state)
@@ -10273,8 +10336,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
- if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state, crtc);
+ intel_optimize_watermarks(state, crtc);
}
intel_dbuf_post_plane_update(state);
@@ -11376,7 +11438,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
/* Write calculated watermark values back */
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
crtc_state->wm.need_postvbl_update = true;
- dev_priv->display.optimize_watermarks(intel_state, crtc);
+ intel_optimize_watermarks(intel_state, crtc);
to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 226f456cde3a..11c9df62391d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7130,45 +7130,6 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
}
-/**
- * intel_update_watermarks - update FIFO watermark values based on current modes
- * @dev_priv: i915 device
- *
- * Calculate watermark values for the various WM regs based on current mode
- * and plane configuration.
- *
- * There are several cases to deal with here:
- * - normal (i.e. non-self-refresh)
- * - self-refresh (SR) mode
- * - lines are large relative to FIFO size (buffer can hold up to 2)
- * - lines are small relative to FIFO size (buffer can hold more than 2
- * lines), so need to account for TLB latency
- *
- * The normal calculation is:
- * watermark = dotclock * bytes per pixel * latency
- * where latency is platform & configuration dependent (we assume pessimal
- * values here).
- *
- * The SR calculation is:
- * watermark = (trunc(latency/line time)+1) * surface width *
- * bytes per pixel
- * where
- * line time = htotal / dotclock
- * surface width = hdisplay for normal plane and 64 for cursor
- * and latency is assumed to be high, as above.
- *
- * The final value programmed to the register should always be rounded up,
- * and include an extra 2 entries to account for clock crossings.
- *
- * We don't use the sprite, so we can ignore that. And on Crestline we have
- * to set the non-SR watermarks to 8.
- */
-void intel_update_watermarks(struct drm_i915_private *dev_priv)
-{
- if (dev_priv->display.update_wm)
- dev_priv->display.update_wm(dev_priv);
-}
-
void intel_enable_ipc(struct drm_i915_private *dev_priv)
{
u32 val;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 99bce0b4f5fb..990cdcaf85ce 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -29,7 +29,6 @@ struct skl_wm_level;
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
void intel_suspend_hw(struct drm_i915_private *dev_priv);
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
-void intel_update_watermarks(struct drm_i915_private *dev_priv);
void intel_init_pm(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_i915_private *dev_priv);
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 05/24] drm/i915: add wrappers around cdclk vtable funcs.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (3 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 04/24] drm/i915/wm: provide wrappers around watermark vfuncs calls (v3) Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 06/24] drm/i915/display: add intel_fdi_link_train wrapper Jani Nikula
` (22 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This adds wrappers around all the vtable callers so they are in
one place.
Suggested by Jani.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 47 +++++++++++++++----
drivers/gpu/drm/i915/display/intel_cdclk.h | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_power.c | 2 +-
4 files changed, 44 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3a1cdb3937aa..ff01fe9be35c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -59,6 +59,37 @@
* dividers can be programmed correctly.
*/
+void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_config *cdclk_config)
+{
+ dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+}
+
+int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return dev_priv->display.bw_calc_min_cdclk(state);
+}
+
+static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
+{
+ dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+}
+
+static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state *cdclk_config)
+{
+ return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+}
+
+static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
+ int cdclk)
+{
+ return dev_priv->display.calc_voltage_level(cdclk);
+}
+
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
@@ -1466,7 +1497,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
* at least what the CDCLK frequency requires.
*/
cdclk_config->voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1808,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
@@ -1789,7 +1820,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
@@ -1956,7 +1987,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
&dev_priv->gmbus_mutex);
}
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2422,7 +2453,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
- dev_priv->display.calc_voltage_level(cdclk));
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk));
if (!cdclk_state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2431,7 +2462,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->actual.vco = vco;
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -2523,7 +2554,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
new_cdclk_state->active_pipes =
intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
- ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
+ ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state);
if (ret)
return ret;
@@ -2703,7 +2734,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
*/
void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+ intel_cdclk_get_cdclk(dev_priv, &dev_priv->cdclk.hw);
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b34eb00fb327..309b3f394e24 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -68,7 +68,9 @@ void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
const char *context);
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
-
+void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_config *cdclk_config);
+int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state);
struct intel_cdclk_state *
intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1c5c8834b333..839954195ffc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9160,7 +9160,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
*need_cdclk_calc = true;
- ret = dev_priv->display.bw_calc_min_cdclk(state);
+ ret = intel_cdclk_bw_calc_min_cdclk(state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cce1a926fcc1..a274e2b33e91 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
+ intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
drm_WARN_ON(&dev_priv->drm,
intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 06/24] drm/i915/display: add intel_fdi_link_train wrapper.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (4 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 05/24] drm/i915: add wrappers around cdclk vtable funcs Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 07/24] drm/i915: split clock gating init from display vtable Jani Nikula
` (21 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This wraps the fdi link training vfunc to make it clearer.
Suggested by Jani.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 8 ++++++++
drivers/gpu/drm/i915/display/intel_fdi.h | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 839954195ffc..c810e4d4a0b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2166,7 +2166,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
assert_pch_transcoder_disabled(dev_priv, pipe);
/* For PCH output, training FDI link */
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ intel_fdi_link_train(crtc, crtc_state);
/* We need to program the right clock selection before writing the pixel
* mutliplier into the DPLL. */
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 96ff12ad0873..d20669e53663 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -10,6 +10,14 @@
#include "intel_fdi.h"
#include "intel_sideband.h"
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ dev_priv->display.fdi_link_train(crtc, crtc_state);
+}
+
/* units of 100MHz */
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
index 60acf2133145..61cb216a09f5 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -26,4 +26,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
void lpt_fdi_program_mphy(struct drm_i915_private *i915);
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 07/24] drm/i915: split clock gating init from display vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (5 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 06/24] drm/i915/display: add intel_fdi_link_train wrapper Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 08/24] drm/i915: split watermark vfuncs " Jani Nikula
` (20 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This function is only used inside intel_pm.c
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 ++++++-
drivers/gpu/drm/i915/intel_pm.c | 48 ++++++++++++++++-----------------
2 files changed, 32 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90e2f44e2deb..b429298f23ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -323,6 +323,11 @@ struct intel_crtc;
struct intel_limit;
struct dpll;
+/* functions used internal in intel_pm.c */
+struct drm_i915_clock_gating_funcs {
+ void (*init_clock_gating)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
const struct drm_connector_state *old_conn_state);
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*init_clock_gating)(struct drm_i915_private *dev_priv);
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
/* clock updates for mode set */
/* cursor updates */
@@ -954,6 +958,9 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
+ /* pm private clock gating functions */
+ struct drm_i915_clock_gating_funcs clock_gating_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 11c9df62391d..34d6faee8969 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7869,7 +7869,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->display.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7896,52 +7896,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = adlp_init_clock_gating;
else if (IS_DG1(dev_priv))
- dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = dg1_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = gen12lp_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->display.init_clock_gating = icl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = icl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = skl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = skl_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
- dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = bxt_init_clock_gating;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->display.init_clock_gating = glk_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = glk_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = chv_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = chv_init_clock_gating;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = hsw_init_clock_gating;
else if (IS_IVYBRIDGE(dev_priv))
- dev_priv->display.init_clock_gating = ivb_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = ivb_init_clock_gating;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = vlv_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = vlv_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 6)
- dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = gen6_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 5)
- dev_priv->display.init_clock_gating = ilk_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = ilk_init_clock_gating;
else if (IS_G4X(dev_priv))
- dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = g4x_init_clock_gating;
else if (IS_I965GM(dev_priv))
- dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = i965gm_init_clock_gating;
else if (IS_I965G(dev_priv))
- dev_priv->display.init_clock_gating = i965g_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = i965g_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 3)
- dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = gen3_init_clock_gating;
else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
- dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = i85x_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 2)
- dev_priv->display.init_clock_gating = i830_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = i830_init_clock_gating;
else {
MISSING_CASE(INTEL_DEVID(dev_priv));
- dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating = nop_init_clock_gating;
}
}
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 08/24] drm/i915: split watermark vfuncs from display vtable.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (6 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 07/24] drm/i915: split clock gating init from display vtable Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 09/24] drm/i915: split color functions " Jani Nikula
` (19 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
These are the watermark api between display and pm.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 24 ++++++++----
drivers/gpu/drm/i915/intel_pm.c | 40 ++++++++++----------
3 files changed, 53 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c810e4d4a0b1..df3b5b393c5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->display.update_wm)
- dev_priv->display.update_wm(dev_priv);
+ if (dev_priv->wm_disp.update_wm)
+ dev_priv->wm_disp.update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_pipe_wm)
- return dev_priv->display.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp.compute_pipe_wm)
+ return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
return 0;
}
@@ -179,20 +179,20 @@ static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (!dev_priv->display.compute_intermediate_wm)
+ if (!dev_priv->wm_disp.compute_intermediate_wm)
return 0;
if (drm_WARN_ON(&dev_priv->drm,
- !dev_priv->display.compute_pipe_wm))
+ !dev_priv->wm_disp.compute_pipe_wm))
return 0;
- return dev_priv->display.compute_intermediate_wm(state, crtc);
+ return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
}
static bool intel_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.initial_watermarks) {
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp.initial_watermarks) {
+ dev_priv->wm_disp.initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp.atomic_update_watermarks)
+ dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp.optimize_watermarks)
+ dev_priv->wm_disp.optimize_watermarks(state, crtc);
}
static int intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_global_watermarks)
- return dev_priv->display.compute_global_watermarks(state);
+ if (dev_priv->wm_disp.compute_global_watermarks)
+ return dev_priv->wm_disp.compute_global_watermarks(state);
return 0;
}
@@ -3744,7 +3744,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->display.initial_watermarks)
+ if (!dev_priv->wm_disp.initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11405,7 +11405,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->display.optimize_watermarks)
+ if (!dev_priv->wm_disp.optimize_watermarks)
return;
state = drm_atomic_state_alloc(&dev_priv->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b429298f23ee..d9c3958ceea5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -328,13 +328,10 @@ struct drm_i915_clock_gating_funcs {
void (*init_clock_gating)(struct drm_i915_private *dev_priv);
};
-struct drm_i915_display_funcs {
- void (*get_cdclk)(struct drm_i915_private *dev_priv,
- struct intel_cdclk_config *cdclk_config);
- void (*set_cdclk)(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *cdclk_config,
- enum pipe pipe);
- int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
+/* functions used for watermark calcs for display. */
+struct drm_i915_wm_disp_funcs {
+ /* update_wm is for legacy wm management */
+ void (*update_wm)(struct drm_i915_private *dev_priv);
int (*compute_pipe_wm)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_intermediate_wm)(struct intel_atomic_state *state,
@@ -346,7 +343,15 @@ struct drm_i915_display_funcs {
void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
- void (*update_wm)(struct drm_i915_private *dev_priv);
+};
+
+struct drm_i915_display_funcs {
+ void (*get_cdclk)(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_config *cdclk_config);
+ void (*set_cdclk)(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe);
+ int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
/* Returns the active state of the crtc, and if the crtc is active,
@@ -961,6 +966,9 @@ struct drm_i915_private {
/* pm private clock gating functions */
struct drm_i915_clock_gating_funcs clock_gating_funcs;
+ /* pm display functions */
+ struct drm_i915_wm_disp_funcs wm_disp;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 34d6faee8969..b37888781ec9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7960,7 +7960,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (DISPLAY_VER(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
- dev_priv->display.compute_global_watermarks = skl_compute_wm;
+ dev_priv->wm_disp.compute_global_watermarks = skl_compute_wm;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
@@ -7968,12 +7968,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
(DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
- dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
- dev_priv->display.compute_intermediate_wm =
+ dev_priv->wm_disp.compute_pipe_wm = ilk_compute_pipe_wm;
+ dev_priv->wm_disp.compute_intermediate_wm =
ilk_compute_intermediate_wm;
- dev_priv->display.initial_watermarks =
+ dev_priv->wm_disp.initial_watermarks =
ilk_initial_watermarks;
- dev_priv->display.optimize_watermarks =
+ dev_priv->wm_disp.optimize_watermarks =
ilk_optimize_watermarks;
} else {
drm_dbg_kms(&dev_priv->drm,
@@ -7982,17 +7982,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
}
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev_priv);
- dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
- dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
- dev_priv->display.initial_watermarks = vlv_initial_watermarks;
- dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
- dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
+ dev_priv->wm_disp.compute_pipe_wm = vlv_compute_pipe_wm;
+ dev_priv->wm_disp.compute_intermediate_wm = vlv_compute_intermediate_wm;
+ dev_priv->wm_disp.initial_watermarks = vlv_initial_watermarks;
+ dev_priv->wm_disp.optimize_watermarks = vlv_optimize_watermarks;
+ dev_priv->wm_disp.atomic_update_watermarks = vlv_atomic_update_fifo;
} else if (IS_G4X(dev_priv)) {
g4x_setup_wm_latency(dev_priv);
- dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
- dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
- dev_priv->display.initial_watermarks = g4x_initial_watermarks;
- dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
+ dev_priv->wm_disp.compute_pipe_wm = g4x_compute_pipe_wm;
+ dev_priv->wm_disp.compute_intermediate_wm = g4x_compute_intermediate_wm;
+ dev_priv->wm_disp.initial_watermarks = g4x_initial_watermarks;
+ dev_priv->wm_disp.optimize_watermarks = g4x_optimize_watermarks;
} else if (IS_PINEVIEW(dev_priv)) {
if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
dev_priv->is_ddr3,
@@ -8006,18 +8006,18 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->fsb_freq, dev_priv->mem_freq);
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
- dev_priv->display.update_wm = NULL;
+ dev_priv->wm_disp.update_wm = NULL;
} else
- dev_priv->display.update_wm = pnv_update_wm;
+ dev_priv->wm_disp.update_wm = pnv_update_wm;
} else if (DISPLAY_VER(dev_priv) == 4) {
- dev_priv->display.update_wm = i965_update_wm;
+ dev_priv->wm_disp.update_wm = i965_update_wm;
} else if (DISPLAY_VER(dev_priv) == 3) {
- dev_priv->display.update_wm = i9xx_update_wm;
+ dev_priv->wm_disp.update_wm = i9xx_update_wm;
} else if (DISPLAY_VER(dev_priv) == 2) {
if (INTEL_NUM_PIPES(dev_priv) == 1)
- dev_priv->display.update_wm = i845_update_wm;
+ dev_priv->wm_disp.update_wm = i845_update_wm;
else
- dev_priv->display.update_wm = i9xx_update_wm;
+ dev_priv->wm_disp.update_wm = i9xx_update_wm;
} else {
drm_err(&dev_priv->drm,
"unexpected fall-through in %s\n", __func__);
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 09/24] drm/i915: split color functions from display vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (7 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 08/24] drm/i915: split watermark vfuncs " Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 10/24] drm/i915: split audio " Jani Nikula
` (18 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
These are only used internally in the color module
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 64 +++++++++++-----------
drivers/gpu/drm/i915/i915_drv.h | 39 +++++++------
2 files changed, 54 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index afcb4bf3826c..ed79075158dd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.load_luts(crtc_state);
+ dev_priv->color_funcs.load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.color_commit(crtc_state);
+ dev_priv->color_funcs.color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->display.color_check(crtc_state);
+ return dev_priv->color_funcs.color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->display.read_luts)
- dev_priv->display.read_luts(crtc_state);
+ if (dev_priv->color_funcs.read_luts)
+ dev_priv->color_funcs.read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.color_check = chv_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = chv_load_luts;
- dev_priv->display.read_luts = chv_read_luts;
+ dev_priv->color_funcs.color_check = chv_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = chv_load_luts;
+ dev_priv->color_funcs.read_luts = chv_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i965_load_luts;
- dev_priv->display.read_luts = i965_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i965_load_luts;
+ dev_priv->color_funcs.read_luts = i965_read_luts;
} else {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i9xx_load_luts;
- dev_priv->display.read_luts = i9xx_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i9xx_load_luts;
+ dev_priv->color_funcs.read_luts = i9xx_read_luts;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.color_check = icl_color_check;
+ dev_priv->color_funcs.color_check = icl_color_check;
else if (DISPLAY_VER(dev_priv) >= 10)
- dev_priv->display.color_check = glk_color_check;
+ dev_priv->color_funcs.color_check = glk_color_check;
else if (DISPLAY_VER(dev_priv) >= 7)
- dev_priv->display.color_check = ivb_color_check;
+ dev_priv->color_funcs.color_check = ivb_color_check;
else
- dev_priv->display.color_check = ilk_color_check;
+ dev_priv->color_funcs.color_check = ilk_color_check;
if (DISPLAY_VER(dev_priv) >= 9)
- dev_priv->display.color_commit = skl_color_commit;
+ dev_priv->color_funcs.color_commit = skl_color_commit;
else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- dev_priv->display.color_commit = hsw_color_commit;
+ dev_priv->color_funcs.color_commit = hsw_color_commit;
else
- dev_priv->display.color_commit = ilk_color_commit;
+ dev_priv->color_funcs.color_commit = ilk_color_commit;
if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->display.load_luts = icl_load_luts;
- dev_priv->display.read_luts = icl_read_luts;
+ dev_priv->color_funcs.load_luts = icl_load_luts;
+ dev_priv->color_funcs.read_luts = icl_read_luts;
} else if (DISPLAY_VER(dev_priv) == 10) {
- dev_priv->display.load_luts = glk_load_luts;
- dev_priv->display.read_luts = glk_read_luts;
+ dev_priv->color_funcs.load_luts = glk_load_luts;
+ dev_priv->color_funcs.read_luts = glk_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.load_luts = bdw_load_luts;
+ dev_priv->color_funcs.load_luts = bdw_load_luts;
} else if (DISPLAY_VER(dev_priv) >= 7) {
- dev_priv->display.load_luts = ivb_load_luts;
+ dev_priv->color_funcs.load_luts = ivb_load_luts;
} else {
- dev_priv->display.load_luts = ilk_load_luts;
- dev_priv->display.read_luts = ilk_read_luts;
+ dev_priv->color_funcs.load_luts = ilk_load_luts;
+ dev_priv->color_funcs.read_luts = ilk_read_luts;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d9c3958ceea5..04b2c710e16c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -345,6 +345,25 @@ struct drm_i915_wm_disp_funcs {
int (*compute_global_watermarks)(struct intel_atomic_state *state);
};
+struct intel_color_funcs {
+ int (*color_check)(struct intel_crtc_state *crtc_state);
+ /*
+ * Program double buffered color management registers during
+ * vblank evasion. The registers should then latch during the
+ * next vblank start, alongside any other double buffered registers
+ * involved with the same commit.
+ */
+ void (*color_commit)(const struct intel_crtc_state *crtc_state);
+ /*
+ * Load LUTs (and other single buffered color management
+ * registers). Will (hopefully) be called during the vblank
+ * following the latching of any double buffered registers
+ * involved with the same commit.
+ */
+ void (*load_luts)(const struct intel_crtc_state *crtc_state);
+ void (*read_luts)(struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -381,23 +400,6 @@ struct drm_i915_display_funcs {
/* render clock increase/decrease */
/* display clock increase/decrease */
/* pll clock increase/decrease */
-
- int (*color_check)(struct intel_crtc_state *crtc_state);
- /*
- * Program double buffered color management registers during
- * vblank evasion. The registers should then latch during the
- * next vblank start, alongside any other double buffered registers
- * involved with the same commit.
- */
- void (*color_commit)(const struct intel_crtc_state *crtc_state);
- /*
- * Load LUTs (and other single buffered color management
- * registers). Will (hopefully) be called during the vblank
- * following the latching of any double buffered registers
- * involved with the same commit.
- */
- void (*load_luts)(const struct intel_crtc_state *crtc_state);
- void (*read_luts)(struct intel_crtc_state *crtc_state);
};
@@ -972,6 +974,9 @@ struct drm_i915_private {
/* Display functions */
struct drm_i915_display_funcs display;
+ /* Display internal color functions */
+ struct intel_color_funcs color_funcs;
+
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 10/24] drm/i915: split audio functions from display vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (8 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 09/24] drm/i915: split color functions " Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 11/24] drm/i915: split cdclk " Jani Nikula
` (17 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
These are only used internally in the audio code
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 24 +++++++++++-----------
drivers/gpu/drm/i915/i915_drv.h | 19 +++++++++++------
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 4e0f96bf6158..bf96d1529775 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->display.audio_codec_enable)
- dev_priv->display.audio_codec_enable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_enable)
+ dev_priv->audio_funcs.audio_codec_enable(encoder,
crtc_state,
conn_state);
@@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->display.audio_codec_disable)
- dev_priv->display.audio_codec_disable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_disable)
+ dev_priv->audio_funcs.audio_codec_disable(encoder,
old_crtc_state,
old_conn_state);
@@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
- dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable = g4x_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable = g4x_audio_codec_disable;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
- dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable = hsw_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable = hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04b2c710e16c..35488822837b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,15 @@ struct intel_color_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
+struct intel_audio_funcs {
+ void (*audio_codec_enable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
+ void (*audio_codec_disable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state *old_conn_state);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -386,12 +395,7 @@ struct drm_i915_display_funcs {
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*audio_codec_enable)(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
- void (*audio_codec_disable)(struct intel_encoder *encoder,
- const struct intel_crtc_state *old_crtc_state,
- const struct drm_connector_state *old_conn_state);
+
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
@@ -977,6 +981,9 @@ struct drm_i915_private {
/* Display internal color functions */
struct intel_color_funcs color_funcs;
+ /* Display internal audio functions */
+ struct intel_audio_funcs audio_funcs;
+
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 11/24] drm/i915: split cdclk functions from display vtable.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (9 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 10/24] drm/i915: split audio " Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 12/24] drm/i915: split irq hotplug function " Jani Nikula
` (16 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This moves all the cdclk related functions into their own vtable.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 142 ++++++++++-----------
drivers/gpu/drm/i915/i915_drv.h | 8 +-
2 files changed, 78 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ff01fe9be35c..cf0a865df596 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->display.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_config)
{
- return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->display.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
+ if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2891,119 +2891,119 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level = ehl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level = icl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level = bxt_calc_voltage_level;
if (IS_GEMINILAKE(dev_priv))
dev_priv->cdclk.table = glk_cdclk_table;
else
dev_priv->cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = skl_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.set_cdclk = skl_set_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
} else if (IS_BROADWELL(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = bdw_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.set_cdclk = bdw_set_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = chv_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.set_cdclk = chv_set_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = vlv_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.set_cdclk = vlv_set_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
} else {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
}
if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
- dev_priv->display.get_cdclk = bxt_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = bxt_get_cdclk;
else if (DISPLAY_VER(dev_priv) == 9)
- dev_priv->display.get_cdclk = skl_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = skl_get_cdclk;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.get_cdclk = bdw_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = bdw_get_cdclk;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.get_cdclk = hsw_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = hsw_get_cdclk;
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->display.get_cdclk = vlv_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = vlv_get_cdclk;
else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
else if (IS_IRONLAKE(dev_priv))
- dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = fixed_450mhz_get_cdclk;
else if (IS_GM45(dev_priv))
- dev_priv->display.get_cdclk = gm45_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = gm45_get_cdclk;
else if (IS_G45(dev_priv))
- dev_priv->display.get_cdclk = g33_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
else if (IS_I965GM(dev_priv))
- dev_priv->display.get_cdclk = i965gm_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = i965gm_get_cdclk;
else if (IS_I965G(dev_priv))
- dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.get_cdclk = pnv_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = pnv_get_cdclk;
else if (IS_G33(dev_priv))
- dev_priv->display.get_cdclk = g33_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
else if (IS_I945GM(dev_priv))
- dev_priv->display.get_cdclk = i945gm_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = i945gm_get_cdclk;
else if (IS_I945G(dev_priv))
- dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
else if (IS_I915GM(dev_priv))
- dev_priv->display.get_cdclk = i915gm_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = i915gm_get_cdclk;
else if (IS_I915G(dev_priv))
- dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = fixed_333mhz_get_cdclk;
else if (IS_I865G(dev_priv))
- dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = fixed_266mhz_get_cdclk;
else if (IS_I85X(dev_priv))
- dev_priv->display.get_cdclk = i85x_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = i85x_get_cdclk;
else if (IS_I845G(dev_priv))
- dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = fixed_200mhz_get_cdclk;
else if (IS_I830(dev_priv))
- dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
- if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,
+ if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs.get_cdclk,
"Unknown platform. Assuming 133 MHz CDCLK\n"))
- dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
+ dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 35488822837b..373e840c3dd9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -373,7 +373,7 @@ struct intel_audio_funcs {
const struct drm_connector_state *old_conn_state);
};
-struct drm_i915_display_funcs {
+struct intel_cdclk_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
void (*set_cdclk)(struct drm_i915_private *dev_priv,
@@ -382,6 +382,9 @@ struct drm_i915_display_funcs {
int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
+};
+
+struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
@@ -984,6 +987,9 @@ struct drm_i915_private {
/* Display internal audio functions */
struct intel_audio_funcs audio_funcs;
+ /* Display CDCLK functions */
+ struct intel_cdclk_funcs cdclk_funcs;
+
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 12/24] drm/i915: split irq hotplug function from display vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (10 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 11/24] drm/i915: split cdclk " Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 13/24] drm/i915: split fdi link training " Jani Nikula
` (15 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This provide a service from irq to display, so make it separate
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 9 ++++++++-
drivers/gpu/drm/i915/i915_irq.c | 14 +++++++-------
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..05f76aba4f8a 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
- i915->display.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
+ i915->hotplug_funcs.hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 373e840c3dd9..e00979130f0a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -384,6 +384,10 @@ struct intel_cdclk_funcs {
u8 (*calc_voltage_level)(int cdclk);
};
+struct intel_hotplug_funcs {
+ void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -401,7 +405,7 @@ struct drm_i915_display_funcs {
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -978,6 +982,9 @@ struct drm_i915_private {
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
+ /* irq display functions */
+ struct intel_hotplug_funcs hotplug_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0a1681384c84..c35065f8f429 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup = i915_hpd_irq_setup;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup = dg1_hpd_irq_setup;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup = gen11_hpd_irq_setup;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup = bxt_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup = icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup = spt_hpd_irq_setup;
else
- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup = ilk_hpd_irq_setup;
}
}
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 13/24] drm/i915: split fdi link training from display vtable.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (11 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 12/24] drm/i915: split irq hotplug function " Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 14/24] drm/i915: split the dpll clock compute out " Jani Nikula
` (14 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
It may make sense to merge this with display again later,
however the fdi use of the vtable is limited to only a
few generations.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_fdi.c | 8 ++++----
drivers/gpu/drm/i915/i915_drv.h | 11 ++++++++---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index d20669e53663..f828bebe8962 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1017,11 +1017,11 @@ void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->display.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e00979130f0a..7004b1a068e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -388,6 +388,11 @@ struct intel_hotplug_funcs {
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
};
+struct intel_fdi_funcs {
+ void (*fdi_link_train)(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -403,9 +408,6 @@ struct drm_i915_display_funcs {
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*fdi_link_train)(struct intel_crtc *crtc,
- const struct intel_crtc_state *crtc_state);
-
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -985,6 +987,9 @@ struct drm_i915_private {
/* irq display functions */
struct intel_hotplug_funcs hotplug_funcs;
+ /* fdi display functions */
+ struct intel_fdi_funcs fdi_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 14/24] drm/i915: split the dpll clock compute out from display vtable.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (12 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 13/24] drm/i915: split fdi link training " Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:57 ` [Intel-gfx] [PATCH 15/24] drm/i915: constify fdi link training vtable Jani Nikula
` (13 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
this single function might be possible to merge later, but
for now it's simple to just split it out.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll.c | 16 ++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 8 +++++++-
3 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index df3b5b393c5f..37d40ab4049c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6834,10 +6834,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->display.crtc_compute_clock &&
+ dev_priv->dpll_funcs.crtc_compute_clock &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->display.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8864,7 +8864,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->display.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs.crtc_compute_clock)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 487d8721ecf8..7811f19acb6a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1369,21 +1369,21 @@ void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock = hsw_crtc_compute_clock;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock = ilk_crtc_compute_clock;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock = chv_crtc_compute_clock;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock = vlv_crtc_compute_clock;
else if (IS_G4X(dev_priv))
- dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock = g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock = pnv_crtc_compute_clock;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
else
- dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7004b1a068e1..ef62b2df0e82 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -393,6 +393,10 @@ struct intel_fdi_funcs {
const struct intel_crtc_state *crtc_state);
};
+struct intel_dpll_funcs {
+ int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -400,7 +404,6 @@ struct drm_i915_display_funcs {
struct intel_crtc_state *);
void (*get_initial_plane_config)(struct intel_crtc *,
struct intel_initial_plane_config *);
- int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*crtc_disable)(struct intel_atomic_state *state,
@@ -990,6 +993,9 @@ struct drm_i915_private {
/* fdi display functions */
struct intel_fdi_funcs fdi_funcs;
+ /* display pll funcs */
+ struct intel_dpll_funcs dpll_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 15/24] drm/i915: constify fdi link training vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (13 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 14/24] drm/i915: split the dpll clock compute out " Jani Nikula
@ 2021-09-28 22:57 ` Jani Nikula
2021-09-28 22:58 ` [Intel-gfx] [PATCH 16/24] drm/i915: constify hotplug function vtable Jani Nikula
` (12 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Put the vtable into ro memory.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_fdi.c | 20 ++++++++++++++++----
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index f828bebe8962..af01d1fa761e 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1013,15 +1013,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
}
+static const struct intel_fdi_funcs ilk_funcs = {
+ .fdi_link_train = ilk_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs gen6_funcs = {
+ .fdi_link_train = gen6_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs ivb_funcs = {
+ .fdi_link_train = ivb_manual_fdi_link_train,
+};
+
void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs = &ilk_funcs;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs = &gen6_funcs;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs = &ivb_funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef62b2df0e82..cd0abc89b5dd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -991,7 +991,7 @@ struct drm_i915_private {
struct intel_hotplug_funcs hotplug_funcs;
/* fdi display functions */
- struct intel_fdi_funcs fdi_funcs;
+ const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
struct intel_dpll_funcs dpll_funcs;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 16/24] drm/i915: constify hotplug function vtable.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (14 preceding siblings ...)
2021-09-28 22:57 ` [Intel-gfx] [PATCH 15/24] drm/i915: constify fdi link training vtable Jani Nikula
@ 2021-09-28 22:58 ` Jani Nikula
2021-09-28 22:58 ` [Intel-gfx] [PATCH 17/24] drm/i915: constify color " Jani Nikula
` (11 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Use a macro to avoid mistakes, this type of macro is only used
in a couple of places.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 28 +++++++++++++++-----
3 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 05f76aba4f8a..3c1cec953b42 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
- i915->hotplug_funcs.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs->hpd_irq_setup)
+ i915->hotplug_funcs->hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cd0abc89b5dd..0e8592445804 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -988,7 +988,7 @@ struct drm_i915_private {
struct drm_i915_wm_disp_funcs wm_disp;
/* irq display functions */
- struct intel_hotplug_funcs hotplug_funcs;
+ const struct intel_hotplug_funcs *hotplug_funcs;
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c35065f8f429..77680bca46ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4345,6 +4345,20 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
return ret;
}
+#define HPD_FUNCS(platform) \
+static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
+ .hpd_irq_setup = platform##_hpd_irq_setup, \
+}
+
+HPD_FUNCS(i915);
+HPD_FUNCS(dg1);
+HPD_FUNCS(gen11);
+HPD_FUNCS(bxt);
+HPD_FUNCS(icp);
+HPD_FUNCS(spt);
+HPD_FUNCS(ilk);
+#undef HPD_FUNCS
+
/**
* intel_irq_init - initializes irq support
* @dev_priv: i915 device instance
@@ -4395,20 +4409,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup = i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs = &i915_hpd_funcs;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup = dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs = &dg1_hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->hotplug_funcs.hpd_irq_setup = gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs = &gen11_hpd_funcs;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup = bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = &bxt_hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->hotplug_funcs.hpd_irq_setup = icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs = &icp_hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->hotplug_funcs.hpd_irq_setup = spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = &spt_hpd_funcs;
else
- dev_priv->hotplug_funcs.hpd_irq_setup = ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs = &ilk_hpd_funcs;
}
}
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 17/24] drm/i915: constify color function vtable.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (15 preceding siblings ...)
2021-09-28 22:58 ` [Intel-gfx] [PATCH 16/24] drm/i915: constify hotplug function vtable Jani Nikula
@ 2021-09-28 22:58 ` Jani Nikula
2021-09-28 22:58 ` [Intel-gfx] [PATCH 18/24] drm/i915: constify the audio " Jani Nikula
` (10 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This clarifies quite well what functions get used on what platforms
instead of having to decipher the old tree.
v2: fixed IVB mistake (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 138 ++++++++++++++-------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 93 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index ed79075158dd..f5923f1c38bd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.load_luts(crtc_state);
+ dev_priv->color_funcs->load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.color_commit(crtc_state);
+ dev_priv->color_funcs->color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->color_funcs.color_check(crtc_state);
+ return dev_priv->color_funcs->color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->color_funcs.read_luts)
- dev_priv->color_funcs.read_luts(crtc_state);
+ if (dev_priv->color_funcs->read_luts)
+ dev_priv->color_funcs->read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2092,6 +2092,76 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
}
}
+static const struct intel_color_funcs chv_color_funcs = {
+ .color_check = chv_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = chv_load_luts,
+ .read_luts = chv_read_luts,
+};
+
+static const struct intel_color_funcs i965_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i965_load_luts,
+ .read_luts = i965_read_luts,
+};
+
+static const struct intel_color_funcs i9xx_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i9xx_load_luts,
+ .read_luts = i9xx_read_luts,
+};
+
+static const struct intel_color_funcs icl_color_funcs = {
+ .color_check = icl_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = icl_load_luts,
+ .read_luts = icl_read_luts,
+};
+
+static const struct intel_color_funcs glk_color_funcs = {
+ .color_check = glk_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = glk_load_luts,
+ .read_luts = glk_read_luts,
+};
+
+static const struct intel_color_funcs skl_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs bdw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs hsw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ivb_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ilk_color_funcs = {
+ .color_check = ilk_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ilk_load_luts,
+ .read_luts = ilk_read_luts,
+};
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2101,52 +2171,28 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->color_funcs.color_check = chv_color_check;
- dev_priv->color_funcs.color_commit = i9xx_color_commit;
- dev_priv->color_funcs.load_luts = chv_load_luts;
- dev_priv->color_funcs.read_luts = chv_read_luts;
+ dev_priv->color_funcs = &chv_color_funcs;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->color_funcs.color_check = i9xx_color_check;
- dev_priv->color_funcs.color_commit = i9xx_color_commit;
- dev_priv->color_funcs.load_luts = i965_load_luts;
- dev_priv->color_funcs.read_luts = i965_read_luts;
+ dev_priv->color_funcs = &i965_color_funcs;
} else {
- dev_priv->color_funcs.color_check = i9xx_color_check;
- dev_priv->color_funcs.color_commit = i9xx_color_commit;
- dev_priv->color_funcs.load_luts = i9xx_load_luts;
- dev_priv->color_funcs.read_luts = i9xx_read_luts;
+ dev_priv->color_funcs = &i9xx_color_funcs;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->color_funcs.color_check = icl_color_check;
- else if (DISPLAY_VER(dev_priv) >= 10)
- dev_priv->color_funcs.color_check = glk_color_check;
- else if (DISPLAY_VER(dev_priv) >= 7)
- dev_priv->color_funcs.color_check = ivb_color_check;
- else
- dev_priv->color_funcs.color_check = ilk_color_check;
-
- if (DISPLAY_VER(dev_priv) >= 9)
- dev_priv->color_funcs.color_commit = skl_color_commit;
- else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- dev_priv->color_funcs.color_commit = hsw_color_commit;
- else
- dev_priv->color_funcs.color_commit = ilk_color_commit;
-
- if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->color_funcs.load_luts = icl_load_luts;
- dev_priv->color_funcs.read_luts = icl_read_luts;
- } else if (DISPLAY_VER(dev_priv) == 10) {
- dev_priv->color_funcs.load_luts = glk_load_luts;
- dev_priv->color_funcs.read_luts = glk_read_luts;
- } else if (DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->color_funcs.load_luts = bdw_load_luts;
- } else if (DISPLAY_VER(dev_priv) >= 7) {
- dev_priv->color_funcs.load_luts = ivb_load_luts;
- } else {
- dev_priv->color_funcs.load_luts = ilk_load_luts;
- dev_priv->color_funcs.read_luts = ilk_read_luts;
- }
+ dev_priv->color_funcs = &icl_color_funcs;
+ else if (DISPLAY_VER(dev_priv) == 10)
+ dev_priv->color_funcs = &glk_color_funcs;
+ else if (DISPLAY_VER(dev_priv) == 9)
+ dev_priv->color_funcs = &skl_color_funcs;
+ else if (DISPLAY_VER(dev_priv) == 8)
+ dev_priv->color_funcs = &bdw_color_funcs;
+ else if (DISPLAY_VER(dev_priv) == 7) {
+ if (IS_HASWELL(dev_priv))
+ dev_priv->color_funcs = &hsw_color_funcs;
+ else
+ dev_priv->color_funcs = &ivb_color_funcs;
+ } else
+ dev_priv->color_funcs = &ilk_color_funcs;
}
drm_crtc_enable_color_mgmt(&crtc->base,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0e8592445804..ddd921a0c141 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1000,7 +1000,7 @@ struct drm_i915_private {
struct drm_i915_display_funcs display;
/* Display internal color functions */
- struct intel_color_funcs color_funcs;
+ const struct intel_color_funcs *color_funcs;
/* Display internal audio functions */
struct intel_audio_funcs audio_funcs;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 18/24] drm/i915: constify the audio function vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (16 preceding siblings ...)
2021-09-28 22:58 ` [Intel-gfx] [PATCH 17/24] drm/i915: constify color " Jani Nikula
@ 2021-09-28 22:58 ` Jani Nikula
2021-09-28 22:58 ` [Intel-gfx] [PATCH 19/24] drm/i915: constify the dpll clock vtable Jani Nikula
` (9 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Move the functions into read-only tables.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 43 ++++++++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index bf96d1529775..03e8c05a74f6 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,10 +848,10 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->audio_funcs.audio_codec_enable)
- dev_priv->audio_funcs.audio_codec_enable(encoder,
- crtc_state,
- conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_enable(encoder,
+ crtc_state,
+ conn_state);
mutex_lock(&dev_priv->av_mutex);
encoder->audio_connector = connector;
@@ -893,10 +893,10 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->audio_funcs.audio_codec_disable)
- dev_priv->audio_funcs.audio_codec_disable(encoder,
- old_crtc_state,
- old_conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_disable(encoder,
+ old_crtc_state,
+ old_conn_state);
mutex_lock(&dev_priv->av_mutex);
encoder->audio_connector = NULL;
@@ -915,6 +915,21 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
}
+static const struct intel_audio_funcs g4x_audio_funcs = {
+ .audio_codec_enable = g4x_audio_codec_enable,
+ .audio_codec_disable = g4x_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs ilk_audio_funcs = {
+ .audio_codec_enable = ilk_audio_codec_enable,
+ .audio_codec_disable = ilk_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs hsw_audio_funcs = {
+ .audio_codec_enable = hsw_audio_codec_enable,
+ .audio_codec_disable = hsw_audio_codec_disable,
+};
+
/**
* intel_init_audio_hooks - Set up chip specific audio hooks
* @dev_priv: device private
@@ -922,17 +937,13 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable = g4x_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable = g4x_audio_codec_disable;
+ dev_priv->audio_funcs = &g4x_audio_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs = &ilk_audio_funcs;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->audio_funcs.audio_codec_enable = hsw_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable = hsw_audio_codec_disable;
+ dev_priv->audio_funcs = &hsw_audio_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs = &ilk_audio_funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ddd921a0c141..25d79e9df783 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1003,7 +1003,7 @@ struct drm_i915_private {
const struct intel_color_funcs *color_funcs;
/* Display internal audio functions */
- struct intel_audio_funcs audio_funcs;
+ const struct intel_audio_funcs *audio_funcs;
/* Display CDCLK functions */
struct intel_cdclk_funcs cdclk_funcs;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 19/24] drm/i915: constify the dpll clock vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (17 preceding siblings ...)
2021-09-28 22:58 ` [Intel-gfx] [PATCH 18/24] drm/i915: constify the audio " Jani Nikula
@ 2021-09-28 22:58 ` Jani Nikula
2021-09-28 22:58 ` [Intel-gfx] [PATCH 20/24] drm/i915: constify the cdclk vtable Jani Nikula
` (8 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Most the dpll vtable into read-only memory.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +--
drivers/gpu/drm/i915/display/intel_dpll.c | 48 ++++++++++++++++----
drivers/gpu/drm/i915/i915_drv.h | 2 +-
3 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 37d40ab4049c..d6c051dbfaf3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6834,10 +6834,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->dpll_funcs.crtc_compute_clock &&
+ dev_priv->dpll_funcs &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8864,7 +8864,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->dpll_funcs.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7811f19acb6a..784e3ee658b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1365,25 +1365,57 @@ static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
return 0;
}
+static const struct intel_dpll_funcs hsw_dpll_funcs = {
+ .crtc_compute_clock = hsw_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs ilk_dpll_funcs = {
+ .crtc_compute_clock = ilk_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs chv_dpll_funcs = {
+ .crtc_compute_clock = chv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs vlv_dpll_funcs = {
+ .crtc_compute_clock = vlv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs g4x_dpll_funcs = {
+ .crtc_compute_clock = g4x_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs pnv_dpll_funcs = {
+ .crtc_compute_clock = pnv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i9xx_dpll_funcs = {
+ .crtc_compute_clock = i9xx_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i8xx_dpll_funcs = {
+ .crtc_compute_clock = i8xx_crtc_compute_clock,
+};
+
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock = hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs = &hsw_dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock = ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs = &ilk_dpll_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock = chv_crtc_compute_clock;
+ dev_priv->dpll_funcs = &chv_dpll_funcs;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock = vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs = &vlv_dpll_funcs;
else if (IS_G4X(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock = g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs = &g4x_dpll_funcs;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock = pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs = &pnv_dpll_funcs;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->dpll_funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = &i9xx_dpll_funcs;
else
- dev_priv->dpll_funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = &i8xx_dpll_funcs;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 25d79e9df783..0ae643362e15 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -994,7 +994,7 @@ struct drm_i915_private {
const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
- struct intel_dpll_funcs dpll_funcs;
+ const struct intel_dpll_funcs *dpll_funcs;
/* Display functions */
struct drm_i915_display_funcs display;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 20/24] drm/i915: constify the cdclk vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (18 preceding siblings ...)
2021-09-28 22:58 ` [Intel-gfx] [PATCH 19/24] drm/i915: constify the dpll clock vtable Jani Nikula
@ 2021-09-28 22:58 ` Jani Nikula
2021-09-28 22:58 ` [Intel-gfx] [PATCH 21/24] drm/i915: drop unused function ptr and comments Jani Nikula
` (7 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This is a bit of a twisty one since each platform is slightly
different, so might take some more review care.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 300 ++++++++++++++-------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 206 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cf0a865df596..ecb28e8f1eb6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_config)
{
- return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
+ if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2884,6 +2884,157 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static struct intel_cdclk_funcs tgl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs ehl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = ehl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs icl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = icl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs bxt_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = bxt_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs skl_cdclk_funcs = {
+ .get_cdclk = skl_get_cdclk,
+ .set_cdclk = skl_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = skl_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs bdw_cdclk_funcs = {
+ .get_cdclk = bdw_get_cdclk,
+ .set_cdclk = bdw_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs chv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = chv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs vlv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = vlv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs hsw_cdclk_funcs = {
+ .get_cdclk = hsw_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* SNB, IVB, 965G, 945G */
+static struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
+ .get_cdclk = fixed_400mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs ilk_cdclk_funcs = {
+ .get_cdclk = fixed_450mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs gm45_cdclk_funcs = {
+ .get_cdclk = gm45_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* G45 uses G33 */
+
+static struct intel_cdclk_funcs i965gm_cdclk_funcs = {
+ .get_cdclk = i965gm_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* i965G uses fixed 400 */
+
+static struct intel_cdclk_funcs pnv_cdclk_funcs = {
+ .get_cdclk = pnv_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs g33_cdclk_funcs = {
+ .get_cdclk = g33_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i945gm_cdclk_funcs = {
+ .get_cdclk = i945gm_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* i945G uses fixed 400 */
+
+static struct intel_cdclk_funcs i915gm_cdclk_funcs = {
+ .get_cdclk = i915gm_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i915g_cdclk_funcs = {
+ .get_cdclk = fixed_333mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i865g_cdclk_funcs = {
+ .get_cdclk = fixed_266mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i85x_cdclk_funcs = {
+ .get_cdclk = i85x_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i845g_cdclk_funcs = {
+ .get_cdclk = fixed_200mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs i830_cdclk_funcs = {
+ .get_cdclk = fixed_133mhz_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
/**
* intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
* @dev_priv: i915 device
@@ -2891,119 +3042,78 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
dev_priv->cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = ehl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &ehl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = icl_calc_voltage_level;
+ dev_priv->cdclk_funcs = &icl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->cdclk_funcs.calc_voltage_level = bxt_calc_voltage_level;
+ dev_priv->cdclk_funcs = &bxt_cdclk_funcs;
if (IS_GEMINILAKE(dev_priv))
dev_priv->cdclk.table = glk_cdclk_table;
else
dev_priv->cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = skl_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs = &skl_cdclk_funcs;
} else if (IS_BROADWELL(dev_priv)) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = bdw_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs = &bdw_cdclk_funcs;
+ } else if (IS_HASWELL(dev_priv)) {
+ dev_priv->cdclk_funcs = &hsw_cdclk_funcs;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = chv_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs = &chv_cdclk_funcs;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.set_cdclk = vlv_set_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
- } else {
- dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->cdclk_funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs = &vlv_cdclk_funcs;
+ } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
+ dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+ } else if (IS_IRONLAKE(dev_priv)) {
+ dev_priv->cdclk_funcs = &ilk_cdclk_funcs;
+ } else if (IS_GM45(dev_priv)) {
+ dev_priv->cdclk_funcs = &gm45_cdclk_funcs;
+ } else if (IS_G45(dev_priv)) {
+ dev_priv->cdclk_funcs = &g33_cdclk_funcs;
+ } else if (IS_I965GM(dev_priv)) {
+ dev_priv->cdclk_funcs = &i965gm_cdclk_funcs;
+ } else if (IS_I965G(dev_priv)) {
+ dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+ } else if (IS_PINEVIEW(dev_priv)) {
+ dev_priv->cdclk_funcs = &pnv_cdclk_funcs;
+ } else if (IS_G33(dev_priv)) {
+ dev_priv->cdclk_funcs = &g33_cdclk_funcs;
+ } else if (IS_I945GM(dev_priv)) {
+ dev_priv->cdclk_funcs = &i945gm_cdclk_funcs;
+ } else if (IS_I945G(dev_priv)) {
+ dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+ } else if (IS_I915GM(dev_priv)) {
+ dev_priv->cdclk_funcs = &i915gm_cdclk_funcs;
+ } else if (IS_I915G(dev_priv)) {
+ dev_priv->cdclk_funcs = &i915g_cdclk_funcs;
+ } else if (IS_I865G(dev_priv)) {
+ dev_priv->cdclk_funcs = &i865g_cdclk_funcs;
+ } else if (IS_I85X(dev_priv)) {
+ dev_priv->cdclk_funcs = &i85x_cdclk_funcs;
+ } else if (IS_I845G(dev_priv)) {
+ dev_priv->cdclk_funcs = &i845g_cdclk_funcs;
+ } else if (IS_I830(dev_priv)) {
+ dev_priv->cdclk_funcs = &i830_cdclk_funcs;
}
- if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = bxt_get_cdclk;
- else if (DISPLAY_VER(dev_priv) == 9)
- dev_priv->cdclk_funcs.get_cdclk = skl_get_cdclk;
- else if (IS_BROADWELL(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = bdw_get_cdclk;
- else if (IS_HASWELL(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = hsw_get_cdclk;
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = vlv_get_cdclk;
- else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
- else if (IS_IRONLAKE(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_450mhz_get_cdclk;
- else if (IS_GM45(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = gm45_get_cdclk;
- else if (IS_G45(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
- else if (IS_I965GM(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = i965gm_get_cdclk;
- else if (IS_I965G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
- else if (IS_PINEVIEW(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = pnv_get_cdclk;
- else if (IS_G33(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
- else if (IS_I945GM(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = i945gm_get_cdclk;
- else if (IS_I945G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
- else if (IS_I915GM(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = i915gm_get_cdclk;
- else if (IS_I915G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_333mhz_get_cdclk;
- else if (IS_I865G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_266mhz_get_cdclk;
- else if (IS_I85X(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = i85x_get_cdclk;
- else if (IS_I845G(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_200mhz_get_cdclk;
- else if (IS_I830(dev_priv))
- dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
-
- if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs.get_cdclk,
- "Unknown platform. Assuming 133 MHz CDCLK\n"))
- dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
+ if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs,
+ "Unknown platform. Assuming i830\n"))
+ dev_priv->cdclk_funcs = &i830_cdclk_funcs;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ae643362e15..0f4de0461fe6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,7 +1006,7 @@ struct drm_i915_private {
const struct intel_audio_funcs *audio_funcs;
/* Display CDCLK functions */
- struct intel_cdclk_funcs cdclk_funcs;
+ const struct intel_cdclk_funcs *cdclk_funcs;
/* PCH chipset type */
enum intel_pch pch_type;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 21/24] drm/i915: drop unused function ptr and comments.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (19 preceding siblings ...)
2021-09-28 22:58 ` [Intel-gfx] [PATCH 20/24] drm/i915: constify the cdclk vtable Jani Nikula
@ 2021-09-28 22:58 ` Jani Nikula
2021-09-28 22:58 ` [Intel-gfx] [PATCH 22/24] drm/i915: constify display function vtable Jani Nikula
` (6 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
There was some excess comments and an unused vtbl ptr.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f4de0461fe6..5ddb434c1f10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -409,13 +409,6 @@ struct drm_i915_display_funcs {
void (*crtc_disable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
- void (*commit_modeset_disables)(struct intel_atomic_state *state);
-
- /* clock updates for mode set */
- /* cursor updates */
- /* render clock increase/decrease */
- /* display clock increase/decrease */
- /* pll clock increase/decrease */
};
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 22/24] drm/i915: constify display function vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (20 preceding siblings ...)
2021-09-28 22:58 ` [Intel-gfx] [PATCH 21/24] drm/i915: drop unused function ptr and comments Jani Nikula
@ 2021-09-28 22:58 ` Jani Nikula
2021-09-28 22:58 ` [Intel-gfx] [PATCH 23/24] drm/i915: constify clock gating init vtable Jani Nikula
` (5 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Make nice clear tables instead of having things in two places.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 81 ++++++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 52 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d6c051dbfaf3..bf3298cc1f6c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3798,7 +3798,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
+ dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
drm_atomic_state_put(state);
@@ -6007,7 +6007,7 @@ static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!i915->display.get_pipe_config(crtc, crtc_state))
+ if (!i915->display->get_pipe_config(crtc, crtc_state))
return false;
crtc_state->hw.active = true;
@@ -9817,7 +9817,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(state, crtc);
+ dev_priv->display->crtc_enable(state, crtc);
if (new_crtc_state->bigjoiner_slave)
return;
@@ -9905,7 +9905,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(state, crtc);
+ dev_priv->display->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -10285,7 +10285,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display.commit_modeset_enables(state);
+ dev_priv->display->commit_modeset_enables(state);
if (state->modeset) {
intel_encoders_update_complete(state);
@@ -11289,6 +11289,46 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
.atomic_state_free = intel_atomic_state_free,
};
+static const struct drm_i915_display_funcs skl_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = skl_commit_modeset_enables,
+ .get_initial_plane_config = skl_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs ddi_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs pch_split_display_funcs = {
+ .get_pipe_config = ilk_get_pipe_config,
+ .crtc_enable = ilk_crtc_enable,
+ .crtc_disable = ilk_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs vlv_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = valleyview_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs i9xx_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = i9xx_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
/**
* intel_init_display_hooks - initialize the display modesetting hooks
* @dev_priv: device private
@@ -11304,38 +11344,19 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
intel_dpll_init_clock_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display = &skl_display_funcs;
} else if (HAS_DDI(dev_priv)) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display = &ddi_display_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.get_pipe_config = ilk_get_pipe_config;
- dev_priv->display.crtc_enable = ilk_crtc_enable;
- dev_priv->display.crtc_disable = ilk_crtc_disable;
+ dev_priv->display = &pch_split_display_funcs;
} else if (IS_CHERRYVIEW(dev_priv) ||
IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.crtc_enable = valleyview_crtc_enable;
- dev_priv->display.crtc_disable = i9xx_crtc_disable;
+ dev_priv->display = &vlv_display_funcs;
} else {
- dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.crtc_enable = i9xx_crtc_enable;
- dev_priv->display.crtc_disable = i9xx_crtc_disable;
+ dev_priv->display = &i9xx_display_funcs;
}
intel_fdi_init_hook(dev_priv);
-
- if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
- dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
- } else {
- dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
- dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
- }
-
}
void intel_modeset_init_hw(struct drm_i915_private *i915)
@@ -11763,7 +11784,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
* can even allow for smooth boot transitions if the BIOS
* fb is large enough for the active pipe configuration.
*/
- i915->display.get_initial_plane_config(crtc, &plane_config);
+ i915->display->get_initial_plane_config(crtc, &plane_config);
/*
* If the fb is shared between multiple heads, we'll
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5ddb434c1f10..c94a70155937 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -990,7 +990,7 @@ struct drm_i915_private {
const struct intel_dpll_funcs *dpll_funcs;
/* Display functions */
- struct drm_i915_display_funcs display;
+ const struct drm_i915_display_funcs *display;
/* Display internal color functions */
const struct intel_color_funcs *color_funcs;
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 23/24] drm/i915: constify clock gating init vtable.
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (21 preceding siblings ...)
2021-09-28 22:58 ` [Intel-gfx] [PATCH 22/24] drm/i915: constify display function vtable Jani Nikula
@ 2021-09-28 22:58 ` Jani Nikula
2021-09-28 22:58 ` [Intel-gfx] [PATCH 24/24] drm/i915: constify display wm vtable Jani Nikula
` (4 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
I used a macro to avoid making any really silly mistakes here.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 78 +++++++++++++++++++++++----------
2 files changed, 55 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c94a70155937..21f2e97bf122 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -975,7 +975,7 @@ struct drm_i915_private {
struct workqueue_struct *flip_wq;
/* pm private clock gating functions */
- struct drm_i915_clock_gating_funcs clock_gating_funcs;
+ const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b37888781ec9..08e0195edeb7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7869,7 +7869,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7884,6 +7884,36 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
"No clock gating settings or workarounds applied.\n");
}
+#define CG_FUNCS(platform) \
+static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = { \
+ .init_clock_gating = platform##_init_clock_gating, \
+}
+
+CG_FUNCS(adlp);
+CG_FUNCS(dg1);
+CG_FUNCS(gen12lp);
+CG_FUNCS(icl);
+CG_FUNCS(cfl);
+CG_FUNCS(skl);
+CG_FUNCS(kbl);
+CG_FUNCS(bxt);
+CG_FUNCS(glk);
+CG_FUNCS(bdw);
+CG_FUNCS(chv);
+CG_FUNCS(hsw);
+CG_FUNCS(ivb);
+CG_FUNCS(vlv);
+CG_FUNCS(gen6);
+CG_FUNCS(ilk);
+CG_FUNCS(g4x);
+CG_FUNCS(i965gm);
+CG_FUNCS(i965g);
+CG_FUNCS(gen3);
+CG_FUNCS(i85x);
+CG_FUNCS(i830);
+CG_FUNCS(nop);
+#undef CG_FUNCS
+
/**
* intel_init_clock_gating_hooks - setup the clock gating hooks
* @dev_priv: device private
@@ -7896,52 +7926,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
else if (IS_DG1(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->clock_gating_funcs.init_clock_gating = gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->clock_gating_funcs.init_clock_gating = icl_init_clock_gating;
+ dev_priv->clock_gating_funcs = &icl_clock_gating_funcs;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs = &cfl_clock_gating_funcs;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = skl_init_clock_gating;
+ dev_priv->clock_gating_funcs = &skl_clock_gating_funcs;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs = &kbl_clock_gating_funcs;
else if (IS_BROXTON(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs = &bxt_clock_gating_funcs;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = glk_init_clock_gating;
+ dev_priv->clock_gating_funcs = &glk_clock_gating_funcs;
else if (IS_BROADWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs = &bdw_clock_gating_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = chv_init_clock_gating;
+ dev_priv->clock_gating_funcs = &chv_clock_gating_funcs;
else if (IS_HASWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = hsw_init_clock_gating;
+ dev_priv->clock_gating_funcs = &hsw_clock_gating_funcs;
else if (IS_IVYBRIDGE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = ivb_init_clock_gating;
+ dev_priv->clock_gating_funcs = &ivb_clock_gating_funcs;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = vlv_init_clock_gating;
+ dev_priv->clock_gating_funcs = &vlv_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 6)
- dev_priv->clock_gating_funcs.init_clock_gating = gen6_init_clock_gating;
+ dev_priv->clock_gating_funcs = &gen6_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 5)
- dev_priv->clock_gating_funcs.init_clock_gating = ilk_init_clock_gating;
+ dev_priv->clock_gating_funcs = &ilk_clock_gating_funcs;
else if (IS_G4X(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = g4x_init_clock_gating;
+ dev_priv->clock_gating_funcs = &g4x_clock_gating_funcs;
else if (IS_I965GM(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = i965gm_init_clock_gating;
+ dev_priv->clock_gating_funcs = &i965gm_clock_gating_funcs;
else if (IS_I965G(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = i965g_init_clock_gating;
+ dev_priv->clock_gating_funcs = &i965g_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 3)
- dev_priv->clock_gating_funcs.init_clock_gating = gen3_init_clock_gating;
+ dev_priv->clock_gating_funcs = &gen3_clock_gating_funcs;
else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating = i85x_init_clock_gating;
+ dev_priv->clock_gating_funcs = &i85x_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 2)
- dev_priv->clock_gating_funcs.init_clock_gating = i830_init_clock_gating;
+ dev_priv->clock_gating_funcs = &i830_clock_gating_funcs;
else {
MISSING_CASE(INTEL_DEVID(dev_priv));
- dev_priv->clock_gating_funcs.init_clock_gating = nop_init_clock_gating;
+ dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
}
}
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 24/24] drm/i915: constify display wm vtable
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (22 preceding siblings ...)
2021-09-28 22:58 ` [Intel-gfx] [PATCH 23/24] drm/i915: constify clock gating init vtable Jani Nikula
@ 2021-09-28 22:58 ` Jani Nikula
2021-09-28 23:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable, again Patchwork
` (3 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-28 22:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie, jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Use a nop table for the cases where CxSR doesn't init properly.
v2: use a nop table (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 34 ++++-----
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 80 ++++++++++++++------
3 files changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bf3298cc1f6c..b405779186e4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->wm_disp.update_wm)
- dev_priv->wm_disp.update_wm(dev_priv);
+ if (dev_priv->wm_disp->update_wm)
+ dev_priv->wm_disp->update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_pipe_wm)
- return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp->compute_pipe_wm)
+ return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
return 0;
}
@@ -179,20 +179,20 @@ static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (!dev_priv->wm_disp.compute_intermediate_wm)
+ if (!dev_priv->wm_disp->compute_intermediate_wm)
return 0;
if (drm_WARN_ON(&dev_priv->drm,
- !dev_priv->wm_disp.compute_pipe_wm))
+ !dev_priv->wm_disp->compute_pipe_wm))
return 0;
- return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
+ return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
}
static bool intel_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.initial_watermarks) {
- dev_priv->wm_disp.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp->initial_watermarks) {
+ dev_priv->wm_disp->initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.atomic_update_watermarks)
- dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp->atomic_update_watermarks)
+ dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.optimize_watermarks)
- dev_priv->wm_disp.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp->optimize_watermarks)
+ dev_priv->wm_disp->optimize_watermarks(state, crtc);
}
static int intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_global_watermarks)
- return dev_priv->wm_disp.compute_global_watermarks(state);
+ if (dev_priv->wm_disp->compute_global_watermarks)
+ return dev_priv->wm_disp->compute_global_watermarks(state);
return 0;
}
@@ -3744,7 +3744,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->wm_disp.initial_watermarks)
+ if (!dev_priv->wm_disp->initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11426,7 +11426,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->wm_disp.optimize_watermarks)
+ if (!dev_priv->wm_disp->optimize_watermarks)
return;
state = drm_atomic_state_alloc(&dev_priv->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 21f2e97bf122..63c939891f1c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -978,7 +978,7 @@ struct drm_i915_private {
const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
/* pm display functions */
- struct drm_i915_wm_disp_funcs wm_disp;
+ const struct drm_i915_wm_disp_funcs *wm_disp;
/* irq display functions */
const struct intel_hotplug_funcs *hotplug_funcs;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 08e0195edeb7..ef5f73934dab 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7975,6 +7975,51 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
}
}
+static const struct drm_i915_wm_disp_funcs skl_wm_funcs = {
+ .compute_global_watermarks = skl_compute_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs ilk_wm_funcs = {
+ .compute_pipe_wm = ilk_compute_pipe_wm,
+ .compute_intermediate_wm = ilk_compute_intermediate_wm,
+ .initial_watermarks = ilk_initial_watermarks,
+ .optimize_watermarks = ilk_optimize_watermarks,
+};
+
+static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
+ .compute_pipe_wm = vlv_compute_pipe_wm,
+ .compute_intermediate_wm = vlv_compute_intermediate_wm,
+ .initial_watermarks = vlv_initial_watermarks,
+ .optimize_watermarks = vlv_optimize_watermarks,
+ .atomic_update_watermarks = vlv_atomic_update_fifo,
+};
+
+static const struct drm_i915_wm_disp_funcs g4x_wm_funcs = {
+ .compute_pipe_wm = g4x_compute_pipe_wm,
+ .compute_intermediate_wm = g4x_compute_intermediate_wm,
+ .initial_watermarks = g4x_initial_watermarks,
+ .optimize_watermarks = g4x_optimize_watermarks,
+};
+
+static const struct drm_i915_wm_disp_funcs pnv_wm_funcs = {
+ .update_wm = pnv_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs i965_wm_funcs = {
+ .update_wm = i965_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs i9xx_wm_funcs = {
+ .update_wm = i9xx_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs i845_wm_funcs = {
+ .update_wm = i845_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs nop_funcs = {
+};
+
/* Set up chip specific power management-related functions */
void intel_init_pm(struct drm_i915_private *dev_priv)
{
@@ -7990,7 +8035,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (DISPLAY_VER(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
- dev_priv->wm_disp.compute_global_watermarks = skl_compute_wm;
+ dev_priv->wm_disp = &skl_wm_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
@@ -7998,31 +8043,19 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
(DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
- dev_priv->wm_disp.compute_pipe_wm = ilk_compute_pipe_wm;
- dev_priv->wm_disp.compute_intermediate_wm =
- ilk_compute_intermediate_wm;
- dev_priv->wm_disp.initial_watermarks =
- ilk_initial_watermarks;
- dev_priv->wm_disp.optimize_watermarks =
- ilk_optimize_watermarks;
+ dev_priv->wm_disp = &ilk_wm_funcs;
} else {
drm_dbg_kms(&dev_priv->drm,
"Failed to read display plane latency. "
"Disable CxSR\n");
+ dev_priv->wm_disp = &nop_funcs;
}
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev_priv);
- dev_priv->wm_disp.compute_pipe_wm = vlv_compute_pipe_wm;
- dev_priv->wm_disp.compute_intermediate_wm = vlv_compute_intermediate_wm;
- dev_priv->wm_disp.initial_watermarks = vlv_initial_watermarks;
- dev_priv->wm_disp.optimize_watermarks = vlv_optimize_watermarks;
- dev_priv->wm_disp.atomic_update_watermarks = vlv_atomic_update_fifo;
+ dev_priv->wm_disp = &vlv_wm_funcs;
} else if (IS_G4X(dev_priv)) {
g4x_setup_wm_latency(dev_priv);
- dev_priv->wm_disp.compute_pipe_wm = g4x_compute_pipe_wm;
- dev_priv->wm_disp.compute_intermediate_wm = g4x_compute_intermediate_wm;
- dev_priv->wm_disp.initial_watermarks = g4x_initial_watermarks;
- dev_priv->wm_disp.optimize_watermarks = g4x_optimize_watermarks;
+ dev_priv->wm_disp = &g4x_wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
dev_priv->is_ddr3,
@@ -8036,21 +8069,22 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->fsb_freq, dev_priv->mem_freq);
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
- dev_priv->wm_disp.update_wm = NULL;
+ dev_priv->wm_disp = &nop_funcs;
} else
- dev_priv->wm_disp.update_wm = pnv_update_wm;
+ dev_priv->wm_disp = &pnv_wm_funcs;
} else if (DISPLAY_VER(dev_priv) == 4) {
- dev_priv->wm_disp.update_wm = i965_update_wm;
+ dev_priv->wm_disp = &i965_wm_funcs;
} else if (DISPLAY_VER(dev_priv) == 3) {
- dev_priv->wm_disp.update_wm = i9xx_update_wm;
+ dev_priv->wm_disp = &i9xx_wm_funcs;
} else if (DISPLAY_VER(dev_priv) == 2) {
if (INTEL_NUM_PIPES(dev_priv) == 1)
- dev_priv->wm_disp.update_wm = i845_update_wm;
+ dev_priv->wm_disp = &i845_wm_funcs;
else
- dev_priv->wm_disp.update_wm = i9xx_update_wm;
+ dev_priv->wm_disp = &i9xx_wm_funcs;
} else {
drm_err(&dev_priv->drm,
"unexpected fall-through in %s\n", __func__);
+ dev_priv->wm_disp = &nop_funcs;
}
}
--
2.30.2
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable, again
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (23 preceding siblings ...)
2021-09-28 22:58 ` [Intel-gfx] [PATCH 24/24] drm/i915: constify display wm vtable Jani Nikula
@ 2021-09-28 23:38 ` Patchwork
2021-09-29 0:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
27 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2021-09-28 23:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: i915/display: split and constify vtable, again
URL : https://patchwork.freedesktop.org/series/95184/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
25d35099ae19 drm/i915/uncore: split the fw get function into separate vfunc
5f03d3269e3b drm/i915/pm: drop get_fifo_size vfunc.
24df6bfbd0d7 drm/i915: make update_wm take a dev_priv.
d4b95ca78a50 drm/i915/wm: provide wrappers around watermark vfuncs calls (v3)
-:10: WARNING:TYPO_SPELLING: 'existance' may be misspelled - perhaps 'existence'?
#10:
One thing to note is that the code checks the existance of some
^^^^^^^^^
-:31: CHECK:LINE_SPACING: Please don't use multiple blank lines
#31: FILE: drivers/gpu/drm/i915/display/intel_display.c:129:
+
-:75: WARNING:LINE_SPACING: Missing a blank line after declarations
#75: FILE: drivers/gpu/drm/i915/display/intel_display.c:173:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_pipe_wm)
-:84: WARNING:LINE_SPACING: Missing a blank line after declarations
#84: FILE: drivers/gpu/drm/i915/display/intel_display.c:182:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (!dev_priv->display.compute_intermediate_wm)
-:96: WARNING:LINE_SPACING: Missing a blank line after declarations
#96: FILE: drivers/gpu/drm/i915/display/intel_display.c:194:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.initial_watermarks) {
-:107: WARNING:LINE_SPACING: Missing a blank line after declarations
#107: FILE: drivers/gpu/drm/i915/display/intel_display.c:205:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.atomic_update_watermarks)
-:115: WARNING:LINE_SPACING: Missing a blank line after declarations
#115: FILE: drivers/gpu/drm/i915/display/intel_display.c:213:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.optimize_watermarks)
-:122: WARNING:LINE_SPACING: Missing a blank line after declarations
#122: FILE: drivers/gpu/drm/i915/display/intel_display.c:220:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_global_watermarks)
-:137: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (16, 20)
#137: FILE: drivers/gpu/drm/i915/display/intel_display.c:2636:
+ if (!intel_initial_watermarks(state, crtc))
+ if (new_crtc_state->update_wm_pre)
-:138: WARNING:TABSTOP: Statements should start on a tabstop
#138: FILE: drivers/gpu/drm/i915/display/intel_display.c:2637:
+ if (new_crtc_state->update_wm_pre)
-:179: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 12)
#179: FILE: drivers/gpu/drm/i915/display/intel_display.c:3680:
+ if (!intel_initial_watermarks(state, crtc))
+ intel_update_watermarks(dev_priv);
total: 0 errors, 10 warnings, 1 checks, 318 lines checked
d3c4c93bef02 drm/i915: add wrappers around cdclk vtable funcs.
-:32: WARNING:LINE_SPACING: Missing a blank line after declarations
#32: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:71:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return dev_priv->display.bw_calc_min_cdclk(state);
total: 0 errors, 1 warnings, 0 checks, 127 lines checked
c4b0939b010d drm/i915/display: add intel_fdi_link_train wrapper.
9d3f3b043262 drm/i915: split clock gating init from display vtable
8df3e5e24fe7 drm/i915: split watermark vfuncs from display vtable.
80ba7c9dbea7 drm/i915: split color functions from display vtable
a81f8a74d4b1 drm/i915: split audio functions from display vtable
3ae5dbfc9499 drm/i915: split cdclk functions from display vtable.
6e370e4bdfb0 drm/i915: split irq hotplug function from display vtable
79b631289768 drm/i915: split fdi link training from display vtable.
0395cf21d5df drm/i915: split the dpll clock compute out from display vtable.
d526b29f70d4 drm/i915: constify fdi link training vtable
6827900a4832 drm/i915: constify hotplug function vtable.
096e5c68a7c4 drm/i915: constify color function vtable.
-:197: CHECK:BRACES: Unbalanced braces around else statement
#197: FILE: drivers/gpu/drm/i915/display/intel_color.c:2194:
+ } else
total: 0 errors, 0 warnings, 1 checks, 187 lines checked
a78732944517 drm/i915: constify the audio function vtable
ddb35a2f7d67 drm/i915: constify the dpll clock vtable
878a6d800e78 drm/i915: constify the cdclk vtable
b7681cd2bcf8 drm/i915: drop unused function ptr and comments.
f29192572174 drm/i915: constify display function vtable
19f4875109d1 drm/i915: constify clock gating init vtable.
3b9c79bb2e0a drm/i915: constify display wm vtable
^ permalink raw reply [flat|nested] 36+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for i915/display: split and constify vtable, again
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (24 preceding siblings ...)
2021-09-28 23:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable, again Patchwork
@ 2021-09-29 0:09 ` Patchwork
2021-09-29 3:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-09-29 6:59 ` [Intel-gfx] [PATCH 00/24] " Jani Nikula
27 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2021-09-29 0:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7716 bytes --]
== Series Details ==
Series: i915/display: split and constify vtable, again
URL : https://patchwork.freedesktop.org/series/95184/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10655 -> Patchwork_21183
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21183:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-ehl-2}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-ehl-2/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-ehl-2/igt@i915_selftest@live@execlists.html
Known issues
------------
Here are the changes found in Patchwork_21183 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-sdma:
- fi-kbl-7500u: NOTRUN -> [SKIP][3] ([fdo#109271]) +27 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-kbl-7500u/igt@amdgpu/amd_basic@cs-sdma.html
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: [PASS][6] -> [FAIL][7] ([i915#1888])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-7500u: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-kbl-7500u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick: [DMESG-FAIL][13] ([i915#2927] / [i915#3428]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [FAIL][15] ([i915#1161]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
#### Warnings ####
* igt@kms_chamelium@vga-hpd-fast:
- fi-kbl-7500u: [{ABORT}][17] ([i915#1814]) -> [SKIP][18] ([fdo#109271])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-kbl-7500u/igt@kms_chamelium@vga-hpd-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/fi-kbl-7500u/igt@kms_chamelium@vga-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (45 -> 30)
------------------------------
Additional (1): fi-kbl-soraka
Missing (16): fi-ilk-m540 fi-bdw-5557u bat-adls-5 bat-dg1-6 fi-hsw-4200u fi-bdw-gvtdvm fi-bsw-cyan fi-snb-2520m bat-adlp-4 fi-ctg-p8600 fi-hsw-4770 fi-ivb-3770 fi-bdw-samus bat-jsl-2 bat-jsl-1 fi-snb-2600
Build changes
-------------
* Linux: CI_DRM_10655 -> Patchwork_21183
CI-20190529: 20190529
CI_DRM_10655: 88d6ecae86a7bb32e8bf2bd233f7f9f9c8bd7abc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6226: 18278534c085c35adcf62f158a8d5356e5496f8d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21183: 3b9c79bb2e0a0e22541ebfaf832ac62127522226 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3b9c79bb2e0a drm/i915: constify display wm vtable
19f4875109d1 drm/i915: constify clock gating init vtable.
f29192572174 drm/i915: constify display function vtable
b7681cd2bcf8 drm/i915: drop unused function ptr and comments.
878a6d800e78 drm/i915: constify the cdclk vtable
ddb35a2f7d67 drm/i915: constify the dpll clock vtable
a78732944517 drm/i915: constify the audio function vtable
096e5c68a7c4 drm/i915: constify color function vtable.
6827900a4832 drm/i915: constify hotplug function vtable.
d526b29f70d4 drm/i915: constify fdi link training vtable
0395cf21d5df drm/i915: split the dpll clock compute out from display vtable.
79b631289768 drm/i915: split fdi link training from display vtable.
6e370e4bdfb0 drm/i915: split irq hotplug function from display vtable
3ae5dbfc9499 drm/i915: split cdclk functions from display vtable.
a81f8a74d4b1 drm/i915: split audio functions from display vtable
80ba7c9dbea7 drm/i915: split color functions from display vtable
8df3e5e24fe7 drm/i915: split watermark vfuncs from display vtable.
9d3f3b043262 drm/i915: split clock gating init from display vtable
c4b0939b010d drm/i915/display: add intel_fdi_link_train wrapper.
d3c4c93bef02 drm/i915: add wrappers around cdclk vtable funcs.
d4b95ca78a50 drm/i915/wm: provide wrappers around watermark vfuncs calls (v3)
24df6bfbd0d7 drm/i915: make update_wm take a dev_priv.
5f03d3269e3b drm/i915/pm: drop get_fifo_size vfunc.
25d35099ae19 drm/i915/uncore: split the fw get function into separate vfunc
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/index.html
[-- Attachment #2: Type: text/html, Size: 9306 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for i915/display: split and constify vtable, again
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (25 preceding siblings ...)
2021-09-29 0:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-09-29 3:12 ` Patchwork
2021-09-29 6:59 ` [Intel-gfx] [PATCH 00/24] " Jani Nikula
27 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2021-09-29 3:12 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30269 bytes --]
== Series Details ==
Series: i915/display: split and constify vtable, again
URL : https://patchwork.freedesktop.org/series/95184/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10655_full -> Patchwork_21183_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_21183_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][1] ([fdo#111827])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@feature_discovery@chamelium.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-iclb: NOTRUN -> [SKIP][2] ([fdo#109314])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#2369] / [i915#3063] / [i915#3648])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb8/igt@gem_eio@unwedge-stress.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][5] ([i915#2846])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: NOTRUN -> [FAIL][10] ([i915#2842]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_params@no-bsd:
- shard-tglb: NOTRUN -> [SKIP][11] ([fdo#109283])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@gem_exec_params@no-bsd.html
* igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][12] ([fdo#112283])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@gem_exec_params@secure-non-root.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#644])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3323])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl3/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#3297])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@gem_userptr_blits@unsync-overlap.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][18] ([i915#3318])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl3/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl4/igt@gem_workarounds@suspend-resume.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl1/igt@gem_workarounds@suspend-resume.html
* igt@gen7_exec_parse@basic-allocation:
- shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271]) +33 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk7/igt@gen7_exec_parse@basic-allocation.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#2856])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_pm_rpm@cursor-dpms:
- shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#118] / [i915#95]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-glk4/igt@i915_pm_rpm@cursor-dpms.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk2/igt@i915_pm_rpm@cursor-dpms.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#110892])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [PASS][26] -> [DMESG-WARN][27] ([i915#180])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl3/igt@i915_suspend@debugfs-reader.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl1/igt@i915_suspend@debugfs-reader.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][28] ([fdo#110725] / [fdo#111614])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][29] ([fdo#111614])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb6/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-glk: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
- shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#110723])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_joiner@invalid-modeset:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#2705])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb8/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk7/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +5 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl7/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#3689] / [i915#3886])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb8/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +8 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl8/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][39] ([i915#3689]) +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb8/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
- shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271]) +194 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl8/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_chamelium@dp-crc-single:
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@kms_chamelium@dp-crc-single.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +13 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl7/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color@pipe-c-ctm-negative:
- shard-skl: [PASS][43] -> [DMESG-WARN][44] ([i915#1982]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl5/igt@kms_color@pipe-c-ctm-negative.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl6/igt@kms_color@pipe-c-ctm-negative.html
* igt@kms_color@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109278] / [i915#1149])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@kms_color@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk7/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][47] ([fdo#109284] / [fdo#111827]) +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +16 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl8/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][49] ([i915#1319])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3116]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb6/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@mei_interface:
- shard-tglb: NOTRUN -> [SKIP][51] ([fdo#111828])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb6/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-random:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#3359])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-32x10-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-tglb: [PASS][53] -> [INCOMPLETE][54] ([i915#2411] / [i915#456])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#109279] / [i915#3359]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][56] -> [FAIL][57] ([i915#2346])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][58] -> [FAIL][59] ([i915#2346] / [i915#533])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109274]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109280]) +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#111825]) +21 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][64] -> [FAIL][65] ([i915#1188]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][66] ([i915#180])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#533])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl7/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-glk: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk7/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][70] -> [FAIL][71] ([fdo#108145] / [i915#265])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][72] ([fdo#108145] / [i915#265]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][73] ([fdo#108145] / [i915#265]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109278]) +4 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-b-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#3536]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb8/igt@kms_plane_lowres@pipe-b-tiling-none.html
* igt@kms_plane_lowres@pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][76] ([fdo#112054]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_plane_lowres@pipe-d-tiling-yf.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2733])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_prime@basic-crc@first-to-second:
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#1836])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_prime@basic-crc@first-to-second.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#2920])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
- shard-tglb: NOTRUN -> [SKIP][81] ([i915#2920])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658]) +3 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-glk: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk7/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][84] ([i915#132] / [i915#3467])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][85] -> [SKIP][86] ([fdo#109441])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb3/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-tglb: NOTRUN -> [SKIP][87] ([fdo#111615]) +4 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][88] ([IGT#2])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl8/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-tglb: [PASS][89] -> [INCOMPLETE][90] ([i915#2828] / [i915#456])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2437])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl3/igt@kms_writeback@writeback-fb-id.html
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#2437])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_writeback@writeback-fb-id.html
* igt@perf@polling:
- shard-skl: [PASS][93] -> [FAIL][94] ([i915#1542]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl6/igt@perf@polling.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl3/igt@perf@polling.html
* igt@prime_nv_pcopy@test2:
- shard-kbl: NOTRUN -> [SKIP][95] ([fdo#109271]) +138 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl7/igt@prime_nv_pcopy@test2.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][96] ([fdo#109291])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@prime_nv_pcopy@test3_2.html
* igt@prime_vgem@basic-userptr:
- shard-tglb: NOTRUN -> [SKIP][97] ([i915#3301])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@fence-read-hang:
- shard-tglb: NOTRUN -> [SKIP][98] ([fdo#109295])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb6/igt@prime_vgem@fence-read-hang.html
* igt@sysfs_clients@create:
- shard-glk: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2994])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk7/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-0:
- shard-apl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2994]) +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl8/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@sema-25:
- shard-kbl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2994]) +2 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl3/igt@sysfs_clients@sema-25.html
- shard-tglb: NOTRUN -> [SKIP][102] ([i915#2994]) +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@sysfs_clients@sema-25.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][103] ([i915#2842]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
- shard-glk: [FAIL][105] ([i915#2842]) -> [PASS][106] +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][107] ([i915#2842]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_parallel@fds@vecs0:
- shard-iclb: [INCOMPLETE][109] ([i915#1895]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb7/igt@gem_exec_parallel@fds@vecs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@gem_exec_parallel@fds@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][111] ([i915#2190]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_offset@bad-flags:
- shard-glk: [DMESG-WARN][113] ([i915#118] / [i915#95]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-glk5/igt@gem_mmap_offset@bad-flags.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-glk2/igt@gem_mmap_offset@bad-flags.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][115] ([i915#454]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-skl: [DMESG-WARN][117] ([i915#1982]) -> [PASS][118] +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl6/igt@kms_color@pipe-c-ctm-0-25.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl3/igt@kms_color@pipe-c-ctm-0-25.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][119] ([i915#180]) -> [PASS][120] +4 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [DMESG-WARN][121] ([i915#180]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [INCOMPLETE][123] ([i915#2411] / [i915#4173] / [i915#456]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_fbcon_fbt@fbc-suspend.html
- shard-kbl: [INCOMPLETE][125] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][127] ([i915#2122]) -> [PASS][128] +2 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-iclb: [SKIP][129] ([i915#3701]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][131] ([i915#1188]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl4/igt@kms_hdr@bpc-switch.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl10/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][133] ([fdo#108145] / [i915#265]) -> [PASS][134] +2 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][135] ([fdo#109441]) -> [PASS][136] +2 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@suspend:
- shard-tglb: [INCOMPLETE][137] ([i915#456]) -> [PASS][138] +2 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb7/igt@kms_psr@suspend.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/shard-tglb3/igt@kms_psr@suspend.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][139] ([i915#180] / [i915#295]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl7/igt@kms_vblank@pipe-a-ts-contin
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21183/index.html
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^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again
2021-09-28 22:57 [Intel-gfx] [PATCH 00/24] i915/display: split and constify vtable, again Jani Nikula
` (26 preceding siblings ...)
2021-09-29 3:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-09-29 6:59 ` Jani Nikula
27 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-09-29 6:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Dave Airlie
On Wed, 29 Sep 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> I must have read the series several times over without spotting the
> issue, but finally figured it out with the help of [1].
>
> Return value and check added to intel_compute_global_watermarks() in
> patch 4, and a couple of patches rebased. Seems so obvious now...
>
> Fingers crossed.
>
> BR,
> Jani.
>
> [1] https://patchwork.freedesktop.org/patch/msgid/20210928223241.22149-1-jani.nikula@intel.com
Yay, finally pushed the lot, thanks for the patches and patience.
The lock debug patch seems like a worthwhile thing to have.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 36+ messages in thread