[Buildroot] [PATCH v3 1/4] infra: add support for MIPS NaN

[Buildroot] [PATCH v3 1/4] infra: add support for MIPS NaN

[Vicente Olivert Riera]

MIPS supports two different NaN encondings, legacy and 2008. Information
about MIPS NaN encodings can be found here:

  https://sourceware.org/binutils/docs/as/MIPS-NaN-Encodings.html

NaN legacy is the only option available for R2 cores and older.
NaN 2008 is the only option available for R6 cores.
R5 cores can have either NaN legacy or NaN 2008, depending on the
implementation. So, if the user selects a generic R5 target architecture
variant, we show a choice menu with both options available. For well
known R5 cores we directly select the NaN enconding they use.

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
Changes v2 -> v3:
 - Nothing
Changes v1 -> v2:
 - Define config symbol in arch/Config.in
 - Change string "NAN" to "NaN"
---
 arch/Config.in                                     |  3 ++
 arch/Config.in.mips                                | 32 ++++++++++++++++++++++
 package/gcc/gcc.mk                                 |  7 +++++
 .../toolchain-external/pkg-toolchain-external.mk   |  5 ++++
 toolchain/toolchain-wrapper.c                      |  3 ++
 5 files changed, 50 insertions(+)

diff --git a/arch/Config.in b/arch/Config.in
index 50377a9af..e921879d0 100644
--- a/arch/Config.in
+++ b/arch/Config.in
@@ -264,6 +264,9 @@ config BR2_GCC_TARGET_ARCH
 config BR2_GCC_TARGET_ABI
 	string
 
+config BR2_GCC_TARGET_NAN
+	string
+
 config BR2_GCC_TARGET_CPU
 	string
 
diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index 4e9ad12ad..a9c27a0e8 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -51,6 +51,7 @@ config BR2_mips_m5150
 	bool "M5150"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
+	select BR2_MIPS_NAN_2008
 config BR2_mips_m6250
 	bool "M6250"
 	depends on !BR2_ARCH_IS_64
@@ -59,6 +60,7 @@ config BR2_mips_p5600
 	bool "P5600"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
+	select BR2_MIPS_NAN_2008
 config BR2_mips_xburst
 	bool "XBurst"
 	depends on !BR2_ARCH_IS_64
@@ -126,6 +128,36 @@ config BR2_MIPS_SOFT_FLOAT
 	  floating point functions, then everything will need to be
 	  compiled with soft floating point support (-msoft-float).
 
+config BR2_MIPS_NAN_LEGACY
+	bool
+	default y		if BR2_MIPS_CPU_MIPS32 || BR2_MIPS_CPU_MIPS32R2 || BR2_MIPS_CPU_MIPS64 || BR2_MIPS_CPU_MIPS64R2
+
+config BR2_MIPS_NAN_2008
+	bool
+	default y		if BR2_MIPS_CPU_MIPS32R6 || BR2_MIPS_CPU_MIPS64R6
+
+choice
+	prompt "Target NaN"
+	depends on BR2_mips_32r5 || BR2_mips_64r5
+	default BR2_MIPS_ENABLE_NAN_2008
+
+	help
+	  NaN encoding to be used
+
+config BR2_MIPS_ENABLE_NAN_LEGACY
+	bool "legacy"
+	select BR2_MIPS_NAN_LEGACY
+
+config BR2_MIPS_ENABLE_NAN_2008
+	bool "2008"
+	depends on !BR2_MIPS_SOFT_FLOAT
+	select BR2_MIPS_NAN_2008
+endchoice
+
+config BR2_GCC_TARGET_NAN
+	default "legacy"	if BR2_MIPS_NAN_LEGACY
+	default "2008"		if BR2_MIPS_NAN_2008
+
 config BR2_ARCH
 	default "mips"		if BR2_mips
 	default "mipsel"	if BR2_mipsel
diff --git a/package/gcc/gcc.mk b/package/gcc/gcc.mk
index b52f9456b..c0249cd50 100644
--- a/package/gcc/gcc.mk
+++ b/package/gcc/gcc.mk
@@ -204,6 +204,9 @@ endif
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_ABI)),)
 HOST_GCC_COMMON_CONF_OPTS += --with-abi=$(BR2_GCC_TARGET_ABI)
 endif
+ifneq ($(call qstrip,$(BR2_GCC_TARGET_NAN)),)
+HOST_GCC_COMMON_CONF_OPTS += --with-nan=$(BR2_GCC_TARGET_NAN)
+endif
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU)),)
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU_REVISION)),)
 HOST_GCC_COMMON_CONF_OPTS += --with-cpu=$(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVISION))
@@ -254,6 +257,7 @@ HOST_GCC_COMMON_WRAPPER_TARGET_CPU := $(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_
 endif
 HOST_GCC_COMMON_WRAPPER_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 HOST_GCC_COMMON_WRAPPER_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
+HOST_GCC_COMMON_WRAPPER_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN))
 HOST_GCC_COMMON_WRAPPER_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 HOST_GCC_COMMON_WRAPPER_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
 HOST_GCC_COMMON_WRAPPER_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))
@@ -267,6 +271,9 @@ endif
 ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_ABI),)
 HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(HOST_GCC_COMMON_WRAPPER_TARGET_ABI)"'
 endif
+ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_NAN),)
+HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(HOST_GCC_COMMON_WRAPPER_TARGET_NAN)"'
+endif
 ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FPU),)
 HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FPU)"'
 endif
diff --git a/toolchain/toolchain-external/pkg-toolchain-external.mk b/toolchain/toolchain-external/pkg-toolchain-external.mk
index 826934505..29c0aade1 100644
--- a/toolchain/toolchain-external/pkg-toolchain-external.mk
+++ b/toolchain/toolchain-external/pkg-toolchain-external.mk
@@ -156,6 +156,7 @@ CC_TARGET_CPU_ := $(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVIS
 endif
 CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
+CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN))
 CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
 CC_TARGET_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_MODE))
@@ -178,6 +179,10 @@ ifneq ($(CC_TARGET_ABI_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mabi=$(CC_TARGET_ABI_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(CC_TARGET_ABI_)"'
 endif
+ifneq ($(CC_TARGET_NAN_),)
+TOOLCHAIN_EXTERNAL_CFLAGS += -mnan=$(CC_TARGET_NAN_)
+TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(CC_TARGET_NAN_)"'
+endif
 ifneq ($(CC_TARGET_FPU_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mfpu=$(CC_TARGET_FPU_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(CC_TARGET_FPU_)"'
diff --git a/toolchain/toolchain-wrapper.c b/toolchain/toolchain-wrapper.c
index 100aa181c..28066e425 100644
--- a/toolchain/toolchain-wrapper.c
+++ b/toolchain/toolchain-wrapper.c
@@ -51,6 +51,9 @@ static char *predef_args[] = {
 #ifdef BR_ABI
 	"-mabi=" BR_ABI,
 #endif
+#ifdef BR_NAN
+	"-mnan=" BR_NAN,
+#endif
 #ifdef BR_FPU
 	"-mfpu=" BR_FPU,
 #endif
-- 
2.13.0

[Buildroot] [PATCH v3 2/4] infra: add support for MIPS32 FP mode

[Vicente Olivert Riera]

MIPS32 support different FP modes (32,xx,64), so give the user the
opportunity to choose between them. That will cause host-gcc to be built
using the --with-fp-32=[32|xx|64] configure option. Also the
-mfp[32|xx|64] gcc option will be added to TARGET_CFLAGS and to the
toolchain wrapper.

FP mode option shouldn't be used for soft-float, so we add logic in the
toolchain wrapper if -msoft-float is among the arguments in order to not
append the -fp[[32|xx|64] option, otherwise the compilation may fail.

Information about FP modes here:

- https://sourceware.org/binutils/docs/as/MIPS-Options.html
- https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#5._Generating_modeless_code

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
Changes v2 -> v3:
 - Change toolchain-wrapper.c to not add FP32 mode option when
   -msoft-float is used.
Changes v1 -> v2:
 - Nothing. Patch introduced in v2.
---
 arch/Config.in                                     |  3 +++
 arch/Config.in.mips                                | 25 ++++++++++++++++++++++
 package/gcc/gcc.mk                                 |  7 ++++++
 .../toolchain-external/pkg-toolchain-external.mk   |  5 +++++
 toolchain/toolchain-wrapper.c                      | 10 +++++++++
 5 files changed, 50 insertions(+)

diff --git a/arch/Config.in b/arch/Config.in
index e921879d0..f385745e4 100644
--- a/arch/Config.in
+++ b/arch/Config.in
@@ -267,6 +267,9 @@ config BR2_GCC_TARGET_ABI
 config BR2_GCC_TARGET_NAN
 	string
 
+config BR2_GCC_TARGET_FP32_MODE
+	string
+
 config BR2_GCC_TARGET_CPU
 	string
 
diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index a9c27a0e8..2303bd367 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -128,6 +128,31 @@ config BR2_MIPS_SOFT_FLOAT
 	  floating point functions, then everything will need to be
 	  compiled with soft floating point support (-msoft-float).
 
+choice
+	prompt "FP mode"
+	depends on !BR2_ARCH_IS_64 && !BR2_MIPS_SOFT_FLOAT
+	default BR2_MIPS_FP32_MODE_XX
+
+	help
+	  FP mode to be used
+
+config BR2_MIPS_FP32_MODE_32
+	bool "32"
+	depends on !BR2_MIPS_CPU_MIPS32R6
+
+config BR2_MIPS_FP32_MODE_XX
+	bool "xx"
+
+config BR2_MIPS_FP32_MODE_64
+	bool "64"
+	depends on !BR2_MIPS_CPU_MIPS32
+endchoice
+
+config BR2_GCC_TARGET_FP32_MODE
+	default "32"	if BR2_MIPS_FP32_MODE_32
+	default "xx"	if BR2_MIPS_FP32_MODE_XX
+	default "64"	if BR2_MIPS_FP32_MODE_64
+
 config BR2_MIPS_NAN_LEGACY
 	bool
 	default y		if BR2_MIPS_CPU_MIPS32 || BR2_MIPS_CPU_MIPS32R2 || BR2_MIPS_CPU_MIPS64 || BR2_MIPS_CPU_MIPS64R2
diff --git a/package/gcc/gcc.mk b/package/gcc/gcc.mk
index c0249cd50..4edcf5280 100644
--- a/package/gcc/gcc.mk
+++ b/package/gcc/gcc.mk
@@ -207,6 +207,9 @@ endif
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_NAN)),)
 HOST_GCC_COMMON_CONF_OPTS += --with-nan=$(BR2_GCC_TARGET_NAN)
 endif
+ifneq ($(call qstrip,$(BR2_GCC_TARGET_FP32_MODE)),)
+HOST_GCC_COMMON_CONF_OPTS += --with-fp-32=$(BR2_GCC_TARGET_FP32_MODE)
+endif
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU)),)
 ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU_REVISION)),)
 HOST_GCC_COMMON_CONF_OPTS += --with-cpu=$(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVISION))
@@ -258,6 +261,7 @@ endif
 HOST_GCC_COMMON_WRAPPER_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 HOST_GCC_COMMON_WRAPPER_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
 HOST_GCC_COMMON_WRAPPER_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN))
+HOST_GCC_COMMON_WRAPPER_TARGET_FP32_MODE := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
 HOST_GCC_COMMON_WRAPPER_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 HOST_GCC_COMMON_WRAPPER_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
 HOST_GCC_COMMON_WRAPPER_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))
@@ -274,6 +278,9 @@ endif
 ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_NAN),)
 HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(HOST_GCC_COMMON_WRAPPER_TARGET_NAN)"'
 endif
+ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FP32_MODE),)
+HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FP32_MODE)"'
+endif
 ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FPU),)
 HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FPU)"'
 endif
diff --git a/toolchain/toolchain-external/pkg-toolchain-external.mk b/toolchain/toolchain-external/pkg-toolchain-external.mk
index 29c0aade1..ccb298bec 100644
--- a/toolchain/toolchain-external/pkg-toolchain-external.mk
+++ b/toolchain/toolchain-external/pkg-toolchain-external.mk
@@ -157,6 +157,7 @@ endif
 CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
 CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN))
+CC_TARGET_FP32_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
 CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
 CC_TARGET_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_MODE))
@@ -183,6 +184,10 @@ ifneq ($(CC_TARGET_NAN_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mnan=$(CC_TARGET_NAN_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(CC_TARGET_NAN_)"'
 endif
+ifneq ($(CC_TARGET_FP32_MODE_),)
+TOOLCHAIN_EXTERNAL_CFLAGS += -mfp$(CC_TARGET_FP32_MODE_)
+TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(CC_TARGET_FP32_MODE_)"'
+endif
 ifneq ($(CC_TARGET_FPU_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mfpu=$(CC_TARGET_FPU_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(CC_TARGET_FPU_)"'
diff --git a/toolchain/toolchain-wrapper.c b/toolchain/toolchain-wrapper.c
index 28066e425..761e72541 100644
--- a/toolchain/toolchain-wrapper.c
+++ b/toolchain/toolchain-wrapper.c
@@ -254,6 +254,16 @@ int main(int argc, char **argv)
 		*cur++ = "-mfloat-abi=" BR_FLOAT_ABI;
 #endif
 
+#ifdef BR_FP32_MODE
+	/* add fp32 mode if soft-float is not args or hard-float overrides soft-float */
+	int add_fp32_mode = 1;
+	for (i = 1; i < argc; i++) {
+		if (strcmp(argv[i], "-msoft-float") == 0) add_fp32_mode = 0;
+		else if (strcmp(argv[i], "-mhard-float") == 0) add_fp32_mode = 1;
+	}
+	if (add_fp32_mode == 1) *cur++ = "-mfp" BR_FP32_MODE;
+#endif
+
 #if defined(BR_ARCH) || \
     defined(BR_CPU)
 	/* Add our -march/cpu flags, but only if none of
-- 
2.13.0

[Buildroot] [PATCH v3 3/4] infra: add MIPS DSP support

[Vicente Olivert Riera]

This patch adds support for the MIPS DSP ASE. They come in three
versions, DSP (r1), DSPr2 and DSPr3. Each one of them is a superset of
the other, so selecting DSPr2 will imply DSP (r1) as well, and selecting
DSPr3 will imply both DSP (r1) and DSPr2 as well.

For generic target architecture variants we let the user choose between
the different compatible versions. For well known cores the user can
only choose the DSP version that specific core would implement, or none,
since implementing the DSP module in a core may be optional.

DSP (r1) and DSPr2 are available since MIPS release version 2.
DSPr3 is only available since MIPS release version 6.

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
Changes v1 -> v3:
 - Nothing. Patch introduced in v3.
---
 arch/Config.in.mips                                | 69 ++++++++++++++++++++++
 .../toolchain-external/pkg-toolchain-external.mk   |  5 ++
 toolchain/toolchain-wrapper.c                      |  3 +
 3 files changed, 77 insertions(+)

diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index 2303bd367..97d59acc8 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -16,6 +16,22 @@ config BR2_MIPS_CPU_MIPS64R5
 config BR2_MIPS_CPU_MIPS64R6
 	bool
 
+# mips cpu features
+config BR2_MIPS_CPU_HAS_DSP_R1
+	bool
+config BR2_MIPS_CPU_HAS_DSP_R2
+	bool
+config BR2_MIPS_CPU_HAS_DSP_R3
+	bool
+
+# some cpu features are optional depending on the core
+config BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
+	bool
+config BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
+	bool
+config BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
+	bool
+
 choice
 	prompt "Target Architecture Variant"
 	depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el
@@ -35,27 +51,37 @@ config BR2_mips_32r2
 	bool "Generic MIPS32R2"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R2
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 config BR2_mips_32r5
 	bool "Generic MIPS32R5"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 config BR2_mips_32r6
 	bool "Generic MIPS32R6"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R6
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
 config BR2_mips_interaptiv
 	bool "interAptiv"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R2
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 config BR2_mips_m5150
 	bool "M5150"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
 	select BR2_MIPS_NAN_2008
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 config BR2_mips_m6250
 	bool "M6250"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R6
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
 config BR2_mips_p5600
 	bool "P5600"
 	depends on !BR2_ARCH_IS_64
@@ -82,14 +108,21 @@ config BR2_mips_64r2
 	bool "Generic MIPS64R2"
 	depends on BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS64R2
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 config BR2_mips_64r5
 	bool "Generic MIPS64R5"
 	depends on BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS64R5
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 config BR2_mips_64r6
 	bool "Generic MIPS64R6"
 	depends on BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS64R6
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
+	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
 config BR2_mips_i6400
 	bool "I6400"
 	depends on BR2_ARCH_IS_64
@@ -183,6 +216,42 @@ config BR2_GCC_TARGET_NAN
 	default "legacy"	if BR2_MIPS_NAN_LEGACY
 	default "2008"		if BR2_MIPS_NAN_2008
 
+choice
+	prompt "DSP support"
+	depends on BR2_MIPS_CPU_MIPS32R2 || BR2_MIPS_CPU_MIPS64R2 || \
+		BR2_MIPS_CPU_MIPS32R5 || BR2_MIPS_CPU_MIPS64R5 || \
+		BR2_MIPS_CPU_MIPS32R6 || BR2_MIPS_CPU_MIPS64R6
+	default BR2_MIPS_ENABLE_DSP_NONE
+
+	help
+	  For some CPU cores, the DSP extension is optional.
+	  Select this option if you are certain your particular
+	  implementation has DSP support and you want to use it.
+	  
+config BR2_MIPS_ENABLE_DSP_NONE
+	bool "None"
+
+config BR2_MIPS_ENABLE_DSP_R1
+	bool "dsp"
+	depends on BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
+	select BR2_MIPS_CPU_HAS_DSP_R1
+
+config BR2_MIPS_ENABLE_DSP_R2
+	bool "dspr2"
+	depends on BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
+	select BR2_MIPS_CPU_HAS_DSP_R2
+
+config BR2_MIPS_ENABLE_DSP_R3
+	bool "dspr3"
+	depends on BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
+	select BR2_MIPS_CPU_HAS_DSP_R3
+endchoice
+
+config BR2_GCC_TARGET_DSP
+	default "dsp"		if BR2_MIPS_CPU_HAS_DSP_R1
+	default "dspr2"		if BR2_MIPS_CPU_HAS_DSP_R2
+	default "dspr3"		if BR2_MIPS_CPU_HAS_DSP_R3
+
 config BR2_ARCH
 	default "mips"		if BR2_mips
 	default "mipsel"	if BR2_mipsel
diff --git a/toolchain/toolchain-external/pkg-toolchain-external.mk b/toolchain/toolchain-external/pkg-toolchain-external.mk
index ccb298bec..ce3a48db8 100644
--- a/toolchain/toolchain-external/pkg-toolchain-external.mk
+++ b/toolchain/toolchain-external/pkg-toolchain-external.mk
@@ -157,6 +157,7 @@ endif
 CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
 CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
 CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN))
+CC_TARGET_DSP_ := $(call qstrip,$(BR2_GCC_TARGET_DSP))
 CC_TARGET_FP32_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
 CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
 CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
@@ -184,6 +185,10 @@ ifneq ($(CC_TARGET_NAN_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mnan=$(CC_TARGET_NAN_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(CC_TARGET_NAN_)"'
 endif
+ifneq ($(CC_TARGET_DSP_),)
+TOOLCHAIN_EXTERNAL_CFLAGS += -m$(CC_TARGET_DSP_)
+TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_DSP='"$(CC_TARGET_DSP_)"'
+endif
 ifneq ($(CC_TARGET_FP32_MODE_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mfp$(CC_TARGET_FP32_MODE_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(CC_TARGET_FP32_MODE_)"'
diff --git a/toolchain/toolchain-wrapper.c b/toolchain/toolchain-wrapper.c
index 761e72541..670e00884 100644
--- a/toolchain/toolchain-wrapper.c
+++ b/toolchain/toolchain-wrapper.c
@@ -54,6 +54,9 @@ static char *predef_args[] = {
 #ifdef BR_NAN
 	"-mnan=" BR_NAN,
 #endif
+#ifdef BR_DSP
+	"-m" BR_DSP,
+#endif
 #ifdef BR_FPU
 	"-mfpu=" BR_FPU,
 #endif
-- 
2.13.0

[Buildroot] [PATCH v3 4/4] infra: add support for MIPS MSA

[Vicente Olivert Riera]

This patch adds support for MIPS SIMD Architecture (MSA) extension. This
feature is available since MIPS release version 5 and is mutually
exclusive with the MIPS DSP extension.

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
Changes v1 -> v3:
 - Nothing. Patch introduced in v3.
---
 arch/Config.in.mips                                 | 21 +++++++++++++++++++++
 .../toolchain-external/pkg-toolchain-external.mk    |  4 ++++
 toolchain/toolchain-wrapper.c                       |  3 +++
 3 files changed, 28 insertions(+)

diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index 97d59acc8..1eb2cd158 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -23,6 +23,8 @@ config BR2_MIPS_CPU_HAS_DSP_R2
 	bool
 config BR2_MIPS_CPU_HAS_DSP_R3
 	bool
+config BR2_MIPS_CPU_HAS_MSA
+	bool
 
 # some cpu features are optional depending on the core
 config BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
@@ -31,6 +33,8 @@ config BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 	bool
 config BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
 	bool
+config BR2_MIPS_CPU_MAYBE_HAS_MSA
+	bool
 
 choice
 	prompt "Target Architecture Variant"
@@ -59,6 +63,7 @@ config BR2_mips_32r5
 	select BR2_MIPS_CPU_MIPS32R5
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_32r6
 	bool "Generic MIPS32R6"
 	depends on !BR2_ARCH_IS_64
@@ -66,6 +71,7 @@ config BR2_mips_32r6
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_interaptiv
 	bool "interAptiv"
 	depends on !BR2_ARCH_IS_64
@@ -87,6 +93,7 @@ config BR2_mips_p5600
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
 	select BR2_MIPS_NAN_2008
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_xburst
 	bool "XBurst"
 	depends on !BR2_ARCH_IS_64
@@ -116,6 +123,7 @@ config BR2_mips_64r5
 	select BR2_MIPS_CPU_MIPS64R5
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_64r6
 	bool "Generic MIPS64R6"
 	depends on BR2_ARCH_IS_64
@@ -123,14 +131,17 @@ config BR2_mips_64r6
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2
 	select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_i6400
 	bool "I6400"
 	depends on BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS64R6
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_p6600
 	bool "P6600"
 	depends on BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS64R6
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 endchoice
 
 
@@ -252,6 +263,16 @@ config BR2_GCC_TARGET_DSP
 	default "dspr2"		if BR2_MIPS_CPU_HAS_DSP_R2
 	default "dspr3"		if BR2_MIPS_CPU_HAS_DSP_R3
 
+config BR2_MIPS_ENABLE_MSA
+	bool "Enable MSA extension support"
+	depends on BR2_MIPS_CPU_MAYBE_HAS_MSA && BR2_MIPS_FP32_MODE_64
+	depends on !(BR2_MIPS_CPU_HAS_DSP_R1 || BR2_MIPS_CPU_HAS_DSP_R2 || BR2_MIPS_CPU_HAS_DSP_R3)
+	select BR2_MIPS_CPU_HAS_MSA
+	help
+	  For some CPU cores, the MSA extension is optional.
+	  Select this option if you are certain your particular
+	  implementation has MSA support and you want to use it.
+
 config BR2_ARCH
 	default "mips"		if BR2_mips
 	default "mipsel"	if BR2_mipsel
diff --git a/toolchain/toolchain-external/pkg-toolchain-external.mk b/toolchain/toolchain-external/pkg-toolchain-external.mk
index ce3a48db8..28dca1690 100644
--- a/toolchain/toolchain-external/pkg-toolchain-external.mk
+++ b/toolchain/toolchain-external/pkg-toolchain-external.mk
@@ -189,6 +189,10 @@ ifneq ($(CC_TARGET_DSP_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -m$(CC_TARGET_DSP_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_DSP='"$(CC_TARGET_DSP_)"'
 endif
+ifneq ($(BR2_MIPS_CPU_HAS_MSA),)
+TOOLCHAIN_EXTERNAL_CFLAGS += -mmsa
+TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_MSA
+endif
 ifneq ($(CC_TARGET_FP32_MODE_),)
 TOOLCHAIN_EXTERNAL_CFLAGS += -mfp$(CC_TARGET_FP32_MODE_)
 TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(CC_TARGET_FP32_MODE_)"'
diff --git a/toolchain/toolchain-wrapper.c b/toolchain/toolchain-wrapper.c
index 670e00884..3e001e6ea 100644
--- a/toolchain/toolchain-wrapper.c
+++ b/toolchain/toolchain-wrapper.c
@@ -57,6 +57,9 @@ static char *predef_args[] = {
 #ifdef BR_DSP
 	"-m" BR_DSP,
 #endif
+#ifdef BR_MSA
+	"-mmsa",
+#endif
 #ifdef BR_FPU
 	"-mfpu=" BR_FPU,
 #endif
-- 
2.13.0

[Buildroot] [PATCH v3 1/4] infra: add support for MIPS NaN

[Arnout Vandecappelle]

 Hi Vicente,

 Pfew, more complexity... Patch looks good in general, but I think it shows that
we need some refactoring.

 I also wonder about external toolchains. I guess they'll either be multiarch,
or they support just one specific NaN encoding, right? In case of multiarch, all
is well. But an external toolchain built for one specific NaN encoding, will
that still work when you select the other encoding in Buildroot? Or will the
external toolchain infra detect that and bail out?


On 23-06-17 19:28, Vicente Olivert Riera wrote:
> MIPS supports two different NaN encondings, legacy and 2008. Information
                                  ^^^^^^^^^^encodings

> about MIPS NaN encodings can be found here:
> 
>   https://sourceware.org/binutils/docs/as/MIPS-NaN-Encodings.html
> 
> NaN legacy is the only option available for R2 cores and older.
> NaN 2008 is the only option available for R6 cores.
> R5 cores can have either NaN legacy or NaN 2008, depending on the
> implementation. So, if the user selects a generic R5 target architecture
> variant, we show a choice menu with both options available. For well
> known R5 cores we directly select the NaN enconding they use.
> 
> Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
> ---
> Changes v2 -> v3:
>  - Nothing
> Changes v1 -> v2:
>  - Define config symbol in arch/Config.in
>  - Change string "NAN" to "NaN"
> ---
>  arch/Config.in                                     |  3 ++
>  arch/Config.in.mips                                | 32 ++++++++++++++++++++++
>  package/gcc/gcc.mk                                 |  7 +++++
>  .../toolchain-external/pkg-toolchain-external.mk   |  5 ++++
>  toolchain/toolchain-wrapper.c                      |  3 ++
>  5 files changed, 50 insertions(+)
> 
> diff --git a/arch/Config.in b/arch/Config.in
> index 50377a9af..e921879d0 100644
> --- a/arch/Config.in
> +++ b/arch/Config.in
> @@ -264,6 +264,9 @@ config BR2_GCC_TARGET_ARCH
>  config BR2_GCC_TARGET_ABI
>  	string
>  
> +config BR2_GCC_TARGET_NAN
> +	string
> +

 It's a pity that we need separate Kconfig options for all of these
arch-specific tuning options. That's where some refactoring would be useful, so
that all the arch-specific stuff can be collected in an arch-specific makefile,
and gcc.mk and toolchain-external.mk etc. just use one variable that contains
everything. If you then need to add another option like that, you just need to
modify the arch-specific files.

>  config BR2_GCC_TARGET_CPU
>  	string
>  
> diff --git a/arch/Config.in.mips b/arch/Config.in.mips
> index 4e9ad12ad..a9c27a0e8 100644
> --- a/arch/Config.in.mips
> +++ b/arch/Config.in.mips
> @@ -51,6 +51,7 @@ config BR2_mips_m5150
>  	bool "M5150"
>  	depends on !BR2_ARCH_IS_64
>  	select BR2_MIPS_CPU_MIPS32R5
> +	select BR2_MIPS_NAN_2008
>  config BR2_mips_m6250
>  	bool "M6250"
>  	depends on !BR2_ARCH_IS_64
> @@ -59,6 +60,7 @@ config BR2_mips_p5600
>  	bool "P5600"
>  	depends on !BR2_ARCH_IS_64
>  	select BR2_MIPS_CPU_MIPS32R5
> +	select BR2_MIPS_NAN_2008
>  config BR2_mips_xburst
>  	bool "XBurst"
>  	depends on !BR2_ARCH_IS_64
> @@ -126,6 +128,36 @@ config BR2_MIPS_SOFT_FLOAT
>  	  floating point functions, then everything will need to be
>  	  compiled with soft floating point support (-msoft-float).
>  
> +config BR2_MIPS_NAN_LEGACY
> +	bool
> +	default y		if BR2_MIPS_CPU_MIPS32 || BR2_MIPS_CPU_MIPS32R2 || BR2_MIPS_CPU_MIPS64 || BR2_MIPS_CPU_MIPS64R2

 Don't put spaces between y and if, and do only one per line.

 However, mixing these default y with select from BR2_mips_m5150 etc. is not
good. Either you have a list of default y here, or you do select from
BR2_MIPS_CPU_MIPS32 etc. I have a slight preference for the latter.

> +
> +config BR2_MIPS_NAN_2008
> +	bool
> +	default y		if BR2_MIPS_CPU_MIPS32R6 || BR2_MIPS_CPU_MIPS64R6
> +
> +choice
> +	prompt "Target NaN"
> +	depends on BR2_mips_32r5 || BR2_mips_64r5
> +	default BR2_MIPS_ENABLE_NAN_2008
> +
> +	help
> +	  NaN encoding to be used
> +
> +config BR2_MIPS_ENABLE_NAN_LEGACY
> +	bool "legacy"
> +	select BR2_MIPS_NAN_LEGACY
> +
> +config BR2_MIPS_ENABLE_NAN_2008
> +	bool "2008"
> +	depends on !BR2_MIPS_SOFT_FLOAT
> +	select BR2_MIPS_NAN_2008
> +endchoice
> +
> +config BR2_GCC_TARGET_NAN
> +	default "legacy"	if BR2_MIPS_NAN_LEGACY
> +	default "2008"		if BR2_MIPS_NAN_2008
> +
>  config BR2_ARCH
>  	default "mips"		if BR2_mips
>  	default "mipsel"	if BR2_mipsel
> diff --git a/package/gcc/gcc.mk b/package/gcc/gcc.mk
> index b52f9456b..c0249cd50 100644
> --- a/package/gcc/gcc.mk
> +++ b/package/gcc/gcc.mk
> @@ -204,6 +204,9 @@ endif
>  ifneq ($(call qstrip,$(BR2_GCC_TARGET_ABI)),)
>  HOST_GCC_COMMON_CONF_OPTS += --with-abi=$(BR2_GCC_TARGET_ABI)
>  endif
> +ifneq ($(call qstrip,$(BR2_GCC_TARGET_NAN)),)
> +HOST_GCC_COMMON_CONF_OPTS += --with-nan=$(BR2_GCC_TARGET_NAN)

 You're just doing the same thing as in the rest of the file, but this is not
good: it should be qstripped. And behold, 50 lines below it is already
qstripped, as HOST_GCC_COMMON_WRAPPER_TARGET_NAN :-). Refactoring opportunity!
But of course, that needs to be a separate patch (and you don't need to do that
now if you don't feel up to it).


> +endif
>  ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU)),)
>  ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU_REVISION)),)
>  HOST_GCC_COMMON_CONF_OPTS += --with-cpu=$(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVISION))
> @@ -254,6 +257,7 @@ HOST_GCC_COMMON_WRAPPER_TARGET_CPU := $(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_
>  endif
>  HOST_GCC_COMMON_WRAPPER_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
>  HOST_GCC_COMMON_WRAPPER_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
> +HOST_GCC_COMMON_WRAPPER_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN))

 Damn this file is crap :-) Should be = instead of :=. But of course keeping
consistency is more important.

>  HOST_GCC_COMMON_WRAPPER_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
>  HOST_GCC_COMMON_WRAPPER_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
>  HOST_GCC_COMMON_WRAPPER_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))
> @@ -267,6 +271,9 @@ endif
>  ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_ABI),)
>  HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(HOST_GCC_COMMON_WRAPPER_TARGET_ABI)"'
>  endif
> +ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_NAN),)
> +HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(HOST_GCC_COMMON_WRAPPER_TARGET_NAN)"'
> +endif
>  ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FPU),)
>  HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FPU)"'
>  endif
> diff --git a/toolchain/toolchain-external/pkg-toolchain-external.mk b/toolchain/toolchain-external/pkg-toolchain-external.mk
> index 826934505..29c0aade1 100644
> --- a/toolchain/toolchain-external/pkg-toolchain-external.mk
> +++ b/toolchain/toolchain-external/pkg-toolchain-external.mk
> @@ -156,6 +156,7 @@ CC_TARGET_CPU_ := $(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVIS
>  endif
>  CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
>  CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
> +CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN))

 Again, this doesn't make sense -- this is exactly the same as
HOST_GCC_COMMON_WRAPPER_TARGET_NAN...

 So it smells like one simple refactoring opportunity would be to move this
stuff to e.g. toolchain.mk, or toolchain-wrapper.mk.

 But OK, all that refactoring, pretty nice but not needed for acceptance of this
patch.

 Regards,
 Arnout

>  CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
>  CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
>  CC_TARGET_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_MODE))
> @@ -178,6 +179,10 @@ ifneq ($(CC_TARGET_ABI_),)
>  TOOLCHAIN_EXTERNAL_CFLAGS += -mabi=$(CC_TARGET_ABI_)
>  TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(CC_TARGET_ABI_)"'
>  endif
> +ifneq ($(CC_TARGET_NAN_),)
> +TOOLCHAIN_EXTERNAL_CFLAGS += -mnan=$(CC_TARGET_NAN_)
> +TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(CC_TARGET_NAN_)"'
> +endif
>  ifneq ($(CC_TARGET_FPU_),)
>  TOOLCHAIN_EXTERNAL_CFLAGS += -mfpu=$(CC_TARGET_FPU_)
>  TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(CC_TARGET_FPU_)"'
> diff --git a/toolchain/toolchain-wrapper.c b/toolchain/toolchain-wrapper.c
> index 100aa181c..28066e425 100644
> --- a/toolchain/toolchain-wrapper.c
> +++ b/toolchain/toolchain-wrapper.c
> @@ -51,6 +51,9 @@ static char *predef_args[] = {
>  #ifdef BR_ABI
>  	"-mabi=" BR_ABI,
>  #endif
> +#ifdef BR_NAN
> +	"-mnan=" BR_NAN,
> +#endif
>  #ifdef BR_FPU
>  	"-mfpu=" BR_FPU,
>  #endif
> 

-- 
Arnout Vandecappelle                          arnout at mind be
Senior Embedded Software Architect            +32-16-286500
Essensium/Mind                                http://www.mind.be
G.Geenslaan 9, 3001 Leuven, Belgium           BE 872 984 063 RPR Leuven
LinkedIn profile: http://www.linkedin.com/in/arnoutvandecappelle
GPG fingerprint:  7493 020B C7E3 8618 8DEC 222C 82EB F404 F9AC 0DDF

[Buildroot] [PATCH v3 1/4] infra: add support for MIPS NaN

[Arnout Vandecappelle]

On 23-06-17 23:56, Arnout Vandecappelle wrote:
>> +config BR2_MIPS_NAN_LEGACY
>> +	bool
>> +	default y		if BR2_MIPS_CPU_MIPS32 || BR2_MIPS_CPU_MIPS32R2 || BR2_MIPS_CPU_MIPS64 || BR2_MIPS_CPU_MIPS64R2
>  Don't put spaces between y and if, and do only one per line.
> 
>  However, mixing these default y with select from BR2_mips_m5150 etc. is not
> good. Either you have a list of default y here, or you do select from
> BR2_MIPS_CPU_MIPS32 etc. I have a slight preference for the latter.

 Just to be clear: this is the only thing that needs to be changed in this
patch, then it's OK for me.

 Oh, and also what happens with external toolchains configured for the wrong NaN.

 Regards,
 Arnout

-- 
Arnout Vandecappelle                          arnout at mind be
Senior Embedded Software Architect            +32-16-286500
Essensium/Mind                                http://www.mind.be
G.Geenslaan 9, 3001 Leuven, Belgium           BE 872 984 063 RPR Leuven
LinkedIn profile: http://www.linkedin.com/in/arnoutvandecappelle
GPG fingerprint:  7493 020B C7E3 8618 8DEC 222C 82EB F404 F9AC 0DDF

[Buildroot] [PATCH v3 1/4] infra: add support for MIPS NaN

[Vicente Olivert Riera]

Hello Arnout,

first of all, thanks for the review.

On 24/06/17 09:51, Arnout Vandecappelle wrote:
> 
> 
> On 23-06-17 23:56, Arnout Vandecappelle wrote:
>>> +config BR2_MIPS_NAN_LEGACY
>>> +	bool
>>> +	default y		if BR2_MIPS_CPU_MIPS32 || BR2_MIPS_CPU_MIPS32R2 || BR2_MIPS_CPU_MIPS64 || BR2_MIPS_CPU_MIPS64R2
>>  Don't put spaces between y and if, and do only one per line.
>>
>>  However, mixing these default y with select from BR2_mips_m5150 etc. is not
>> good. Either you have a list of default y here, or you do select from
>> BR2_MIPS_CPU_MIPS32 etc. I have a slight preference for the latter.
> 
>  Just to be clear: this is the only thing that needs to be changed in this
> patch, then it's OK for me.

I'll change that. Thanks.

There is also one more important change to do for fixing uClibc
compilation. I'll include it as well.

> 
>  Oh, and also what happens with external toolchains configured for the wrong NaN.

Some external toolchains can build code for both NaN. For instance, the
ones that are included in Buildroot...

  toolchain-external-codescape-img-mips
  toolchain-external-codescape-mti-mips
  toolchain-external-codesourcery-mips

...they do support both NaN. In that case, nothing has to be done.

But, if your external toolchain only supports one NaN, then you need to
make that external toolchain depend on either BR2_MIPS_NAN_LEGACY or
BR2_MIPS_NAN_2008.

Regards,

Vincent

> 
>  Regards,
>  Arnout
>