From: "Chang S. Bae" <chang.seok.bae@intel.com> To: Eric Biggers <ebiggers@kernel.org> Cc: <linux-kernel@vger.kernel.org>, <linux-crypto@vger.kernel.org>, <dm-devel@redhat.com>, <elliott@hpe.com>, <gmazyland@gmail.com>, <luto@kernel.org>, <dave.hansen@linux.intel.com>, <tglx@linutronix.de>, <bp@alien8.de>, <mingo@kernel.org>, <x86@kernel.org>, <herbert@gondor.apana.org.au>, <ardb@kernel.org>, <dan.j.williams@intel.com>, <bernie.keany@intel.com>, <charishma1.gairuboyina@intel.com>, <lalithambika.krishnakumar@intel.com>, <nhuck@google.com>, "David S. Miller" <davem@davemloft.net>, Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com> Subject: Re: [PATCH v8 12/12] crypto: x86/aes-kl - Implement the AES-XTS algorithm Date: Wed, 7 Jun 2023 15:06:48 -0700 [thread overview] Message-ID: <1ce70878-cf3a-7cde-be8f-3279c34493d1@intel.com> (raw) In-Reply-To: <20230607053558.GC941@sol.localdomain> On 6/6/2023 10:35 PM, Eric Biggers wrote: > On Sat, Jun 03, 2023 at 08:22:27AM -0700, Chang S. Bae wrote: > > Can you also mention why you are doing this? I suppose it might as well be > done, but I'm not seeing how it would actually matter. While this crypto implementation is in the kernel mode, userspace can call it: https://docs.kernel.org/crypto/userspace-if.html And those AES instructions are executable in userspace. Say someone takes a key handle out of the kernel code and then decrypts some disk image from userspace. At least, this is enforced not to do. > What other sorts of key usage restrictions does AES-KL support? Are any other > ones useful here? Besides this, there are additional bits to restrict using encryption and decryption respectively. This can be found in Section 1.1.1.1 'Handle Restrictions' in its whitepaper: https://www.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html >> Subsequently the key handle could be corrupted or fail with handle >> restrictions. Then, encrypt()/decrypt() returns -EINVAL. > > Aren't these scenarios actually impossible? At least without memory corruption. Yes, in the dm-crypt path, I think. But, the key handle can be tainted in the userspace -> API path. I think this may help users as this feature can do some integrity checks at first and then populate an error right away if it goes wrong. >> Thus, advertise it with a unique name 'xts-aes-aeskl' in /proc/crypto while >> not replacing AES-NI under the generic name 'xts(aes)' with a lower priority. > > The above sentence seems to say that xts-aes-aeskl does *not* have a lower > priority than xts-aes-aesni. But actually it does. No, it does not say that. This needs to call out the latter part more clearly. >> Then, the performance is unlikely better than 64-bit which has already a gap >> vs. AES-NI. > > I don't understand what this sentence is trying to say. This is in another section for explaining why 64-bitness only. I kinda added another point to avoid 32-bit code. But, anyways it is known that 32-bit kernel mode is being deprecated. Then, the 128-bit register story seems to be enough there. >> +config AS_HAS_KEYLOCKER >> + def_bool $(as-instr,encodekey256 %eax$(comma)%eax) >> + help >> + Supported by binutils >= 2.36 and LLVM integrated assembler >= V12 > > It looks like arch/x86/Kconfig.assembler would be a better place for this. Yeah, the commit 5e8ebd841a44 ("x86: probe assembler capabilities via kconfig instead of makefile") moved those over there. >> + >> +#define IN1 %xmm8 >> +#define IN IN1 > > Why do both IN1 and IN exist? Shouldn't there just be IN? Oh, this is a silly leftover from the CBC code as it has multiple inputs. #define IN %xmm8 then, s/IN1/IN/g >> + >> +#define AREG %rax > > Shouldn't %rax just be hardcoded? I thought this (or any other) renaming helps to read. Maybe I'm missing something. Can I get to know your thought on this? >> +#define HANDLEP %rdi > > This should be called CTX, to match the function prototypes. > >> +#define UKEYP OUTP > > This should be called IN_KEY, to match the function prototypes. Okay. But, OTOH, the prototype itself is somewhat generic. Then its argument naming does not always match with what is supposed to be meant in the code. Thus, AES-NI renamed those like ctx -> KEYP in_key -> UKEY ... So, another option can be leaving some comments there, e.g. '# ctx is renamed to KEYP'. >> + >> +.Lsetkey_end: >> + movdqu STATE1, (HANDLEP) >> + movdqu STATE2, 0x10(HANDLEP) >> + movdqu STATE3, 0x20(HANDLEP) > > The moves to the ctx should use movdqa, since it is aligned. Reading the manual, the difference is whether generating #GP or not when any misaligned memory operand comes. Then, MOVDQA all here seems to be saying please check the alignment every time. But, HANDLEP is known to have an aligned address. Then, the plain move seems to be enough and coherent with the glue code -- avoid unnecessary sanity checks. >> + >> + xor AREG, AREG >> + FRAME_END >> + RET >> +SYM_FUNC_END(__aeskl_setkey) > > This function always returns 0, so it really should return void. Yeah, fair enough. > In the common case (successful AES-256 encryption) this is executing 'jmp' > twice. I think the code should be rearranged to eliminate these jmps. Ah, right. I think a good point! Let me tweak this for those most likely cases. > __aeskl_xts_encrypt() and __aeskl_xts_decrypt() are very similar. To reduce > code duplication, can you consider generating them from a macro that takes an > argument that indicates whether it is encrypt or decrypt? Yeah, I can see the code that prepares operands is common between them. But, I'm not sure folding them together can make it more readable. > Something that your AES-KL code does that's a bit ugly is that it abuses > 'struct crypto_aes_ctx' to store a Keylocker key handle instead > of the actual AES key schedule which the struct is supposed to be for. > > The proper way to represent that would be to make the tfm context for > xts-aes-aeskl be a union of crypto_aes_ctx and a Keylocker specific context. Agreed. I think this is likely the fallout of that struct aesni_xts_ctx fix. Previously, the field was a byte array which itself is not necessarily representing the extended-key format. Now the fix changed it to be more specific. Accordingly, Key Locker has to specify it. Thanks, Chang
WARNING: multiple messages have this Message-ID (diff)
From: "Chang S. Bae" <chang.seok.bae@intel.com> To: Eric Biggers <ebiggers@kernel.org> Cc: x86@kernel.org, herbert@gondor.apana.org.au, "David S. Miller" <davem@davemloft.net>, ardb@kernel.org, dave.hansen@linux.intel.com, dan.j.williams@intel.com, linux-kernel@vger.kernel.org, charishma1.gairuboyina@intel.com, mingo@kernel.org, lalithambika.krishnakumar@intel.com, dm-devel@redhat.com, Ingo Molnar <mingo@redhat.com>, bp@alien8.de, linux-crypto@vger.kernel.org, luto@kernel.org, "H. Peter Anvin" <hpa@zytor.com>, bernie.keany@intel.com, tglx@linutronix.de, nhuck@google.com, gmazyland@gmail.com, elliott@hpe.com Subject: Re: [dm-devel] [PATCH v8 12/12] crypto: x86/aes-kl - Implement the AES-XTS algorithm Date: Wed, 7 Jun 2023 15:06:48 -0700 [thread overview] Message-ID: <1ce70878-cf3a-7cde-be8f-3279c34493d1@intel.com> (raw) In-Reply-To: <20230607053558.GC941@sol.localdomain> On 6/6/2023 10:35 PM, Eric Biggers wrote: > On Sat, Jun 03, 2023 at 08:22:27AM -0700, Chang S. Bae wrote: > > Can you also mention why you are doing this? I suppose it might as well be > done, but I'm not seeing how it would actually matter. While this crypto implementation is in the kernel mode, userspace can call it: https://docs.kernel.org/crypto/userspace-if.html And those AES instructions are executable in userspace. Say someone takes a key handle out of the kernel code and then decrypts some disk image from userspace. At least, this is enforced not to do. > What other sorts of key usage restrictions does AES-KL support? Are any other > ones useful here? Besides this, there are additional bits to restrict using encryption and decryption respectively. This can be found in Section 1.1.1.1 'Handle Restrictions' in its whitepaper: https://www.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html >> Subsequently the key handle could be corrupted or fail with handle >> restrictions. Then, encrypt()/decrypt() returns -EINVAL. > > Aren't these scenarios actually impossible? At least without memory corruption. Yes, in the dm-crypt path, I think. But, the key handle can be tainted in the userspace -> API path. I think this may help users as this feature can do some integrity checks at first and then populate an error right away if it goes wrong. >> Thus, advertise it with a unique name 'xts-aes-aeskl' in /proc/crypto while >> not replacing AES-NI under the generic name 'xts(aes)' with a lower priority. > > The above sentence seems to say that xts-aes-aeskl does *not* have a lower > priority than xts-aes-aesni. But actually it does. No, it does not say that. This needs to call out the latter part more clearly. >> Then, the performance is unlikely better than 64-bit which has already a gap >> vs. AES-NI. > > I don't understand what this sentence is trying to say. This is in another section for explaining why 64-bitness only. I kinda added another point to avoid 32-bit code. But, anyways it is known that 32-bit kernel mode is being deprecated. Then, the 128-bit register story seems to be enough there. >> +config AS_HAS_KEYLOCKER >> + def_bool $(as-instr,encodekey256 %eax$(comma)%eax) >> + help >> + Supported by binutils >= 2.36 and LLVM integrated assembler >= V12 > > It looks like arch/x86/Kconfig.assembler would be a better place for this. Yeah, the commit 5e8ebd841a44 ("x86: probe assembler capabilities via kconfig instead of makefile") moved those over there. >> + >> +#define IN1 %xmm8 >> +#define IN IN1 > > Why do both IN1 and IN exist? Shouldn't there just be IN? Oh, this is a silly leftover from the CBC code as it has multiple inputs. #define IN %xmm8 then, s/IN1/IN/g >> + >> +#define AREG %rax > > Shouldn't %rax just be hardcoded? I thought this (or any other) renaming helps to read. Maybe I'm missing something. Can I get to know your thought on this? >> +#define HANDLEP %rdi > > This should be called CTX, to match the function prototypes. > >> +#define UKEYP OUTP > > This should be called IN_KEY, to match the function prototypes. Okay. But, OTOH, the prototype itself is somewhat generic. Then its argument naming does not always match with what is supposed to be meant in the code. Thus, AES-NI renamed those like ctx -> KEYP in_key -> UKEY ... So, another option can be leaving some comments there, e.g. '# ctx is renamed to KEYP'. >> + >> +.Lsetkey_end: >> + movdqu STATE1, (HANDLEP) >> + movdqu STATE2, 0x10(HANDLEP) >> + movdqu STATE3, 0x20(HANDLEP) > > The moves to the ctx should use movdqa, since it is aligned. Reading the manual, the difference is whether generating #GP or not when any misaligned memory operand comes. Then, MOVDQA all here seems to be saying please check the alignment every time. But, HANDLEP is known to have an aligned address. Then, the plain move seems to be enough and coherent with the glue code -- avoid unnecessary sanity checks. >> + >> + xor AREG, AREG >> + FRAME_END >> + RET >> +SYM_FUNC_END(__aeskl_setkey) > > This function always returns 0, so it really should return void. Yeah, fair enough. > In the common case (successful AES-256 encryption) this is executing 'jmp' > twice. I think the code should be rearranged to eliminate these jmps. Ah, right. I think a good point! Let me tweak this for those most likely cases. > __aeskl_xts_encrypt() and __aeskl_xts_decrypt() are very similar. To reduce > code duplication, can you consider generating them from a macro that takes an > argument that indicates whether it is encrypt or decrypt? Yeah, I can see the code that prepares operands is common between them. But, I'm not sure folding them together can make it more readable. > Something that your AES-KL code does that's a bit ugly is that it abuses > 'struct crypto_aes_ctx' to store a Keylocker key handle instead > of the actual AES key schedule which the struct is supposed to be for. > > The proper way to represent that would be to make the tfm context for > xts-aes-aeskl be a union of crypto_aes_ctx and a Keylocker specific context. Agreed. I think this is likely the fallout of that struct aesni_xts_ctx fix. Previously, the field was a byte array which itself is not necessarily representing the extended-key format. Now the fix changed it to be more specific. Accordingly, Key Locker has to specify it. Thanks, Chang -- dm-devel mailing list dm-devel@redhat.com https://listman.redhat.com/mailman/listinfo/dm-devel
next prev parent reply other threads:[~2023-06-07 22:07 UTC|newest] Thread overview: 247+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-12 21:12 [PATCH v5 00/12] x86: Support Key Locker Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 01/12] Documentation/x86: Document " Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2023-06-05 10:52 ` Bagas Sanjaya 2023-06-05 10:52 ` [dm-devel] " Bagas Sanjaya 2022-01-12 21:12 ` [PATCH v5 02/12] x86/cpufeature: Enumerate Key Locker feature Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 03/12] x86/insn: Add Key Locker instructions to the opcode map Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 04/12] x86/asm: Add a wrapper function for the LOADIWKEY instruction Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 05/12] x86/msr-index: Add MSRs for Key Locker internal wrapping key Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 06/12] x86/keylocker: Define Key Locker CPUID leaf Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 07/12] x86/cpu/keylocker: Load an internal wrapping key at boot-time Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-08-23 15:49 ` Evan Green 2022-08-23 15:49 ` [dm-devel] " Evan Green 2022-08-24 22:20 ` Chang S. Bae 2022-08-24 22:20 ` [dm-devel] " Chang S. Bae 2022-08-24 22:52 ` Evan Green 2022-08-24 22:52 ` [dm-devel] " Evan Green 2022-08-25 1:06 ` Chang S. Bae 2022-08-25 1:06 ` [dm-devel] " Chang S. Bae 2022-08-25 15:31 ` Evan Green 2022-08-25 15:31 ` [dm-devel] " Evan Green 2022-08-31 23:08 ` Chang S. Bae 2022-08-31 23:08 ` [dm-devel] " Chang S. Bae 2022-09-06 16:22 ` Evan Green 2022-09-06 16:22 ` [dm-devel] " Evan Green 2022-09-06 16:46 ` Chang S. Bae 2022-09-06 16:46 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 08/12] x86/PM/keylocker: Restore internal wrapping key on resume from ACPI S3/4 Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-29 17:31 ` [PATCH v5-fix " Chang S. Bae 2022-01-29 17:31 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 09/12] x86/cpu: Add a configuration and command line option for Key Locker Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 10/12] crypto: x86/aes - Prepare for a new AES implementation Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 11/12] crypto: x86/aes-kl - Support AES algorithm using Key Locker instructions Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-12 21:12 ` [PATCH v5 12/12] crypto: x86/aes-kl - Support XTS mode Chang S. Bae 2022-01-12 21:12 ` [dm-devel] " Chang S. Bae 2022-01-13 22:16 ` [PATCH v5 00/12] x86: Support Key Locker Dave Hansen 2022-01-13 22:16 ` [dm-devel] " Dave Hansen 2022-01-13 22:34 ` Bae, Chang Seok 2022-01-13 22:34 ` [dm-devel] " Bae, Chang Seok 2023-04-10 22:59 ` [PATCH v6 " Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 01/12] Documentation/x86: Document " Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 02/12] x86/cpufeature: Enumerate Key Locker feature Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 03/12] x86/insn: Add Key Locker instructions to the opcode map Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 04/12] x86/asm: Add a wrapper function for the LOADIWKEY instruction Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 05/12] x86/msr-index: Add MSRs for Key Locker internal wrapping key Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 06/12] x86/keylocker: Define Key Locker CPUID leaf Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 07/12] x86/cpu/keylocker: Load an internal wrapping key at boot-time Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-05-05 23:05 ` Eric Biggers 2023-05-05 23:05 ` [dm-devel] " Eric Biggers 2023-05-08 18:18 ` Chang S. Bae 2023-05-08 18:18 ` [dm-devel] " Chang S. Bae 2023-05-08 21:56 ` Dave Hansen 2023-05-08 21:56 ` [dm-devel] " Dave Hansen 2023-05-09 0:31 ` Chang S. Bae 2023-05-09 0:31 ` [dm-devel] " Chang S. Bae 2023-05-09 0:51 ` Dave Hansen 2023-05-09 0:51 ` [dm-devel] " Dave Hansen 2023-05-08 19:18 ` Elliott, Robert (Servers) 2023-05-08 19:18 ` [dm-devel] " Elliott, Robert (Servers) 2023-05-08 20:15 ` Chang S. Bae 2023-05-08 20:15 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 08/12] x86/PM/keylocker: Restore internal wrapping key on resume from ACPI S3/4 Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-05-05 23:09 ` Eric Biggers 2023-05-05 23:09 ` [dm-devel] " Eric Biggers 2023-05-08 18:18 ` Chang S. Bae 2023-05-08 18:18 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 09/12] x86/cpu: Add a configuration and command line option for Key Locker Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 10/12] crypto: x86/aes - Prepare for a new AES implementation Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-05-05 23:27 ` Eric Biggers 2023-05-05 23:27 ` [dm-devel] " Eric Biggers 2023-05-09 0:55 ` Chang S. Bae 2023-05-09 0:55 ` [dm-devel] " Chang S. Bae 2023-05-11 19:05 ` Chang S. Bae 2023-05-11 19:05 ` [dm-devel] " Chang S. Bae 2023-05-11 21:39 ` Eric Biggers 2023-05-11 21:39 ` [dm-devel] " Eric Biggers 2023-05-11 23:19 ` Chang S. Bae 2023-05-11 23:19 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 11/12] crypto: x86/aes-kl - Support AES algorithm using Key Locker instructions Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-05-06 0:01 ` Eric Biggers 2023-05-06 0:01 ` [dm-devel] " Eric Biggers 2023-05-08 18:18 ` Chang S. Bae 2023-05-08 18:18 ` [dm-devel] " Chang S. Bae 2023-05-24 17:18 ` Chang S. Bae 2023-05-24 17:18 ` [dm-devel] " Chang S. Bae 2023-05-12 17:52 ` Milan Broz 2023-05-12 17:52 ` [dm-devel] " Milan Broz 2023-05-08 19:21 ` Elliott, Robert (Servers) 2023-05-08 19:21 ` [dm-devel] " Elliott, Robert (Servers) 2023-05-08 19:24 ` Elliott, Robert (Servers) 2023-05-08 19:24 ` [dm-devel] " Elliott, Robert (Servers) 2023-05-08 20:00 ` Chang S. Bae 2023-05-08 20:00 ` [dm-devel] " Chang S. Bae 2023-04-10 22:59 ` [PATCH v6 12/12] crypto: x86/aes-kl - Support XTS mode Chang S. Bae 2023-04-10 22:59 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 00/12] x86: Support Key Locker Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 01/12] Documentation/x86: Document " Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 02/12] x86/cpufeature: Enumerate Key Locker feature Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 03/12] x86/insn: Add Key Locker instructions to the opcode map Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 04/12] x86/asm: Add a wrapper function for the LOADIWKEY instruction Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 05/12] x86/msr-index: Add MSRs for Key Locker wrapping key Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 06/12] x86/keylocker: Define Key Locker CPUID leaf Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 07/12] x86/cpu/keylocker: Load a wrapping key at boot-time Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 08/12] x86/PM/keylocker: Restore the wrapping key on the resume from ACPI S3/4 Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 09/12] x86/cpu: Add a configuration and command line option for Key Locker Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 10/12] crypto: x86/aesni - Use the proper data type in struct aesni_xts_ctx Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-26 6:54 ` Eric Biggers 2023-05-26 6:54 ` [dm-devel] " Eric Biggers 2023-05-30 20:50 ` Chang S. Bae 2023-05-30 20:50 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [PATCH v7 11/12] crypto: x86/aes - Prepare for a new AES implementation Chang S. Bae 2023-05-24 16:57 ` [dm-devel] " Chang S. Bae 2023-05-24 16:57 ` [dm-devel] [PATCH v7 12/12] crypto: x86/aes-kl - Implement the AES-XTS algorithm Chang S. Bae 2023-05-24 16:57 ` Chang S. Bae 2023-05-26 7:23 ` Eric Biggers 2023-05-26 7:23 ` [dm-devel] " Eric Biggers 2023-05-30 20:49 ` Chang S. Bae 2023-05-30 20:49 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 00/12] x86: Support Key Locker Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 01/12] Documentation/x86: Document " Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-05 10:54 ` Bagas Sanjaya 2023-06-05 10:54 ` [dm-devel] " Bagas Sanjaya 2023-06-06 2:17 ` Randy Dunlap 2023-06-06 2:17 ` [dm-devel] " Randy Dunlap 2023-06-06 4:18 ` Chang S. Bae 2023-06-06 4:18 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 02/12] x86/cpufeature: Enumerate Key Locker feature Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 03/12] x86/insn: Add Key Locker instructions to the opcode map Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 04/12] x86/asm: Add a wrapper function for the LOADIWKEY instruction Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 05/12] x86/msr-index: Add MSRs for Key Locker wrapping key Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 06/12] x86/keylocker: Define Key Locker CPUID leaf Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 07/12] x86/cpu/keylocker: Load a wrapping key at boot-time Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 08/12] x86/PM/keylocker: Restore the wrapping key on the resume from ACPI S3/4 Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 09/12] x86/cpu: Add a configuration and command line option for Key Locker Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 16:37 ` Borislav Petkov 2023-06-03 16:37 ` [dm-devel] " Borislav Petkov 2023-06-04 22:13 ` Chang S. Bae 2023-06-04 22:13 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 10/12] crypto: x86/aesni - Use the proper data type in struct aesni_xts_ctx Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-04 15:34 ` Eric Biggers 2023-06-04 15:34 ` [dm-devel] " Eric Biggers 2023-06-04 22:02 ` Chang S. Bae 2023-06-04 22:02 ` [dm-devel] " Chang S. Bae 2023-06-05 2:46 ` Eric Biggers 2023-06-05 2:46 ` [dm-devel] " Eric Biggers 2023-06-05 4:41 ` Chang S. Bae 2023-06-05 4:41 ` Chang S. Bae 2023-06-21 12:06 ` [PATCH] crypto: x86/aesni: Align the address before aes_set_key_common() Chang S. Bae 2023-07-14 8:51 ` Herbert Xu 2023-06-03 15:22 ` [PATCH v8 11/12] crypto: x86/aes - Prepare for a new AES-XTS implementation Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-03 15:22 ` [PATCH v8 12/12] crypto: x86/aes-kl - Implement the AES-XTS algorithm Chang S. Bae 2023-06-03 15:22 ` [dm-devel] " Chang S. Bae 2023-06-07 5:35 ` Eric Biggers 2023-06-07 5:35 ` [dm-devel] " Eric Biggers 2023-06-07 22:06 ` Chang S. Bae [this message] 2023-06-07 22:06 ` Chang S. Bae 2024-03-11 21:32 ` [PATCH] crypto: x86/aesni - Update aesni_set_key() to return void Chang S. Bae 2024-03-12 2:15 ` Eric Biggers 2024-03-12 7:46 ` Ard Biesheuvel 2024-03-12 15:03 ` Chang S. Bae 2024-03-12 15:18 ` Ard Biesheuvel 2024-03-12 15:37 ` Chang S. Bae 2024-03-22 23:04 ` [PATCH v2 0/2] crypto: x86/aesni - Simplify AES key expansion code Chang S. Bae 2024-03-22 23:04 ` [PATCH v2 1/2] crypto: x86/aesni - Rearrange AES key size check Chang S. Bae 2024-03-22 23:04 ` [PATCH v2 2/2] crypto: x86/aesni - Update aesni_set_key() to return void Chang S. Bae 2024-03-28 10:57 ` [PATCH v2 0/2] crypto: x86/aesni - Simplify AES key expansion code Herbert Xu 2024-03-29 1:53 ` [PATCH v9 00/14] x86: Support Key Locker Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 01/14] Documentation/x86: Document " Chang S. Bae 2024-03-31 15:48 ` Randy Dunlap 2024-03-29 1:53 ` [PATCH v9 02/14] x86/cpufeature: Enumerate Key Locker feature Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 03/14] x86/insn: Add Key Locker instructions to the opcode map Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 04/14] x86/asm: Add a wrapper function for the LOADIWKEY instruction Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 05/14] x86/msr-index: Add MSRs for Key Locker wrapping key Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 06/14] x86/keylocker: Define Key Locker CPUID leaf Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 07/14] x86/cpu/keylocker: Load a wrapping key at boot time Chang S. Bae 2024-04-07 23:04 ` [PATCH v9a " Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 08/14] x86/PM/keylocker: Restore the wrapping key on the resume from ACPI S3/4 Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 09/14] x86/hotplug/keylocker: Ensure wrapping key backup capability Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 10/14] x86/cpu/keylocker: Check Gather Data Sampling mitigation Chang S. Bae 2024-03-29 6:57 ` Pawan Gupta 2024-04-07 23:04 ` [PATCH v9a " Chang S. Bae 2024-04-19 0:01 ` Pawan Gupta 2024-04-22 7:49 ` Chang S. Bae 2024-04-19 17:47 ` [PATCH 15/14] x86/gds: Lock GDS mitigation when keylocker feature is present Pawan Gupta 2024-04-19 18:03 ` Daniel Sneddon 2024-04-19 20:19 ` Pawan Gupta 2024-04-19 20:33 ` Daniel Sneddon 2024-04-22 7:35 ` Chang S. Bae 2024-04-22 21:32 ` Pawan Gupta 2024-04-22 22:13 ` Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 11/14] x86/cpu/keylocker: Check Register File Data Sampling mitigation Chang S. Bae 2024-03-29 6:20 ` Pawan Gupta 2024-04-07 23:04 ` [PATCH v9a " Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 12/14] x86/Kconfig: Add a configuration for Key Locker Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 13/14] crypto: x86/aes - Prepare for new AES-XTS implementation Chang S. Bae 2024-03-29 1:53 ` [PATCH v9 14/14] crypto: x86/aes-kl - Implement the AES-XTS algorithm Chang S. Bae 2024-04-07 23:24 ` [PATCH v9 00/14] x86: Support Key Locker Chang S. Bae 2024-04-08 1:48 ` Eric Biggers 2024-04-15 22:16 ` Chang S. Bae 2024-04-15 22:54 ` Eric Biggers 2024-04-15 22:58 ` Chang S. Bae
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