* [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
@ 2020-11-06 2:32 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-11-06 2:32 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
After claiming the interrupt by reading the claim register we want to
clear the register to make sure the interrupt doesn't appear at the next
read.
This matches the documentation for the claim register as it clears the
pending bit (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html
This also matches the current hardware.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/ibex_plic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index f49fa67c91..235e6b88ff 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
/* Return the current claimed interrupt */
ret = s->claim;
+ /* Clear the claimed interrupt */
+ s->claim = 0x00000000;
+
/* Update the interrupt status after the claim */
ibex_plic_update(s);
}
--
2.28.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
@ 2020-11-06 2:32 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-11-06 2:32 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
After claiming the interrupt by reading the claim register we want to
clear the register to make sure the interrupt doesn't appear at the next
read.
This matches the documentation for the claim register as it clears the
pending bit (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html
This also matches the current hardware.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/ibex_plic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index f49fa67c91..235e6b88ff 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
/* Return the current claimed interrupt */
ret = s->claim;
+ /* Clear the claimed interrupt */
+ s->claim = 0x00000000;
+
/* Update the interrupt status after the claim */
ibex_plic_update(s);
}
--
2.28.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
2020-11-06 2:32 ` Alistair Francis
@ 2020-11-06 14:20 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-11-06 14:20 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23, bmeng.cn, palmer
On 11/6/20 3:32 AM, Alistair Francis wrote:
> After claiming the interrupt by reading the claim register we want to
> clear the register to make sure the interrupt doesn't appear at the next
> read.
>
> This matches the documentation for the claim register as it clears the
> pending bit (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html
"When an interrupt is claimed by a target the relevant bit of IP is
cleared." Correct.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> This also matches the current hardware.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/ibex_plic.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> index f49fa67c91..235e6b88ff 100644
> --- a/hw/intc/ibex_plic.c
> +++ b/hw/intc/ibex_plic.c
> @@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
> /* Return the current claimed interrupt */
> ret = s->claim;
>
> + /* Clear the claimed interrupt */
> + s->claim = 0x00000000;
> +
> /* Update the interrupt status after the claim */
> ibex_plic_update(s);
> }
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
@ 2020-11-06 14:20 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-11-06 14:20 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair23
On 11/6/20 3:32 AM, Alistair Francis wrote:
> After claiming the interrupt by reading the claim register we want to
> clear the register to make sure the interrupt doesn't appear at the next
> read.
>
> This matches the documentation for the claim register as it clears the
> pending bit (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html
"When an interrupt is claimed by a target the relevant bit of IP is
cleared." Correct.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> This also matches the current hardware.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/ibex_plic.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> index f49fa67c91..235e6b88ff 100644
> --- a/hw/intc/ibex_plic.c
> +++ b/hw/intc/ibex_plic.c
> @@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
> /* Return the current claimed interrupt */
> ret = s->claim;
>
> + /* Clear the claimed interrupt */
> + s->claim = 0x00000000;
> +
> /* Update the interrupt status after the claim */
> ibex_plic_update(s);
> }
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
2020-11-06 14:20 ` Philippe Mathieu-Daudé
@ 2020-11-09 23:11 ` Alistair Francis
-1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-11-09 23:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: open list:RISC-V, Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Fri, Nov 6, 2020 at 6:20 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 11/6/20 3:32 AM, Alistair Francis wrote:
> > After claiming the interrupt by reading the claim register we want to
> > clear the register to make sure the interrupt doesn't appear at the next
> > read.
> >
> > This matches the documentation for the claim register as it clears the
> > pending bit (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html
>
> "When an interrupt is claimed by a target the relevant bit of IP is
> cleared." Correct.
Yep, I improved this.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Thanks
Alistair
>
> >
> > This also matches the current hardware.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/intc/ibex_plic.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> > index f49fa67c91..235e6b88ff 100644
> > --- a/hw/intc/ibex_plic.c
> > +++ b/hw/intc/ibex_plic.c
> > @@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
> > /* Return the current claimed interrupt */
> > ret = s->claim;
> >
> > + /* Clear the claimed interrupt */
> > + s->claim = 0x00000000;
> > +
> > /* Update the interrupt status after the claim */
> > ibex_plic_update(s);
> > }
> >
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
@ 2020-11-09 23:11 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2020-11-09 23:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng, Palmer Dabbelt
On Fri, Nov 6, 2020 at 6:20 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 11/6/20 3:32 AM, Alistair Francis wrote:
> > After claiming the interrupt by reading the claim register we want to
> > clear the register to make sure the interrupt doesn't appear at the next
> > read.
> >
> > This matches the documentation for the claim register as it clears the
> > pending bit (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html
>
> "When an interrupt is claimed by a target the relevant bit of IP is
> cleared." Correct.
Yep, I improved this.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Thanks
Alistair
>
> >
> > This also matches the current hardware.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/intc/ibex_plic.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> > index f49fa67c91..235e6b88ff 100644
> > --- a/hw/intc/ibex_plic.c
> > +++ b/hw/intc/ibex_plic.c
> > @@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
> > /* Return the current claimed interrupt */
> > ret = s->claim;
> >
> > + /* Clear the claimed interrupt */
> > + s->claim = 0x00000000;
> > +
> > /* Update the interrupt status after the claim */
> > ibex_plic_update(s);
> > }
> >
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-11-09 23:24 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-11-06 2:32 [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read Alistair Francis
2020-11-06 2:32 ` Alistair Francis
2020-11-06 14:20 ` Philippe Mathieu-Daudé
2020-11-06 14:20 ` Philippe Mathieu-Daudé
2020-11-09 23:11 ` Alistair Francis
2020-11-09 23:11 ` Alistair Francis
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