* [U-Boot] [PATCH] net: zynq_gem: Remove check for Versal
@ 2019-09-11 8:42 Michal Simek
2019-10-08 7:42 ` Michal Simek
0 siblings, 1 reply; 2+ messages in thread
From: Michal Simek @ 2019-09-11 8:42 UTC (permalink / raw)
To: u-boot
From: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
This patch removes check for Versal platform
in gem driver as it now supports clock setting
through clock framework.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
This patch depends on https://lists.denx.de/pipermail/u-boot/2019-September/383239.html
Joe: I would take this together with versal clock driver when reviewed.
---
drivers/net/zynq_gem.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index a35ecab79ee9..a7a6ce987f07 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -463,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev)
break;
}
-#if !defined(CONFIG_ARCH_VERSAL)
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
dev_err(dev, "failed to set tx clock rate\n");
@@ -475,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev)
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
-#else
- debug("requested clk_rate %ld\n", clk_rate);
-#endif
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH] net: zynq_gem: Remove check for Versal
2019-09-11 8:42 [U-Boot] [PATCH] net: zynq_gem: Remove check for Versal Michal Simek
@ 2019-10-08 7:42 ` Michal Simek
0 siblings, 0 replies; 2+ messages in thread
From: Michal Simek @ 2019-10-08 7:42 UTC (permalink / raw)
To: u-boot
st 11. 9. 2019 v 10:42 odesÃlatel Michal Simek <michal.simek@xilinx.com> napsal:
>
> From: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
>
> This patch removes check for Versal platform
> in gem driver as it now supports clock setting
> through clock framework.
>
> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> This patch depends on https://lists.denx.de/pipermail/u-boot/2019-September/383239.html
>
> Joe: I would take this together with versal clock driver when reviewed.
> ---
> drivers/net/zynq_gem.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index a35ecab79ee9..a7a6ce987f07 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -463,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev)
> break;
> }
>
> -#if !defined(CONFIG_ARCH_VERSAL)
> ret = clk_set_rate(&priv->clk, clk_rate);
> if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
> dev_err(dev, "failed to set tx clock rate\n");
> @@ -475,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev)
> dev_err(dev, "failed to enable tx clock\n");
> return ret;
> }
> -#else
> - debug("requested clk_rate %ld\n", clk_rate);
> -#endif
>
> setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
> ZYNQ_GEM_NWCTRL_TXEN_MASK);
> --
> 2.17.1
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
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