* [PATCH v5 1/9] drm/i915/tgl: Add DC3CO required register and bits
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
@ 2019-08-09 18:32 ` Anshuman Gupta
2019-08-09 18:32 ` [PATCH v5 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
` (15 subsequent siblings)
16 siblings, 0 replies; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-09 18:32 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a947bd0a294..3e0783ebbbe6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4198,6 +4198,7 @@ enum {
#define _VTOTAL_A 0x6000c
#define _VBLANK_A 0x60010
#define _VSYNC_A 0x60014
+#define _EXITLINE_A 0x60018
#define _PIPEASRC 0x6001c
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
@@ -4244,11 +4245,16 @@ enum {
#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
+#define EXITLINE_ENABLE (1 << 31)
+#define EXITLINE_MASK (0x1fff)
+#define EXITLINE_SHIFT 0
+
/* HSW+ eDP PSR registers */
#define HSW_EDP_PSR_BASE 0x64800
#define BDW_EDP_PSR_BASE 0x6f800
@@ -10040,6 +10046,8 @@ enum skl_power_gate {
/* GEN9 DC */
#define DC_STATE_EN _MMIO(0x45504)
#define DC_STATE_DISABLE 0
+#define DC_STATE_EN_DC3CO (1 << 30)
+#define DC_STATE_DC3CO_STATUS (1 << 29)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
--
2.21.0
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v5 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
2019-08-09 18:32 ` [PATCH v5 1/9] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
@ 2019-08-09 18:32 ` Anshuman Gupta
2019-08-09 18:32 ` [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state Anshuman Gupta
` (14 subsequent siblings)
16 siblings, 0 replies; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-09 18:32 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_power.c | 29 ++++++++++++++-----
drivers/gpu/drm/i915/i915_params.c | 3 +-
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e3bea2b74ce2..e2ef202aeeef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -717,7 +717,11 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
- if (INTEL_GEN(dev_priv) >= 11)
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+ | DC_STATE_EN_DC9;
+ else if (IS_GEN(dev_priv, 11))
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
@@ -3946,14 +3950,17 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
- if (INTEL_GEN(dev_priv) >= 11) {
- max_dc = 2;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
* suspend/resume, so allow it unconditionally.
*/
mask = DC_STATE_EN_DC9;
+ } else if (IS_GEN(dev_priv, 11)) {
+ max_dc = 2;
+ mask = DC_STATE_EN_DC9;
} else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
max_dc = 2;
mask = 0;
@@ -3972,7 +3979,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
requested_dc = enable_dc;
} else if (enable_dc == -1) {
requested_dc = max_dc;
- } else if (enable_dc > max_dc && enable_dc <= 2) {
+ } else if (enable_dc > max_dc && enable_dc <= 4) {
DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
enable_dc, max_dc);
requested_dc = max_dc;
@@ -3981,10 +3988,16 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
requested_dc = max_dc;
}
- if (requested_dc > 1)
- mask |= DC_STATE_EN_UPTO_DC6;
- if (requested_dc > 0)
- mask |= DC_STATE_EN_UPTO_DC5;
+ if (requested_dc == 4) {
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+ } else if (requested_dc == 3) {
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+ } else {
+ if (requested_dc > 1)
+ mask |= DC_STATE_EN_UPTO_DC6;
+ if (requested_dc > 0)
+ mask |= DC_STATE_EN_UPTO_DC5;
+ }
DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..4f1806f65040 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
- "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+ "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+ "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
i915_param_named_unsafe(enable_fbc, int, 0600,
"Enable frame buffer compression for power savings "
--
2.21.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
2019-08-09 18:32 ` [PATCH v5 1/9] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
2019-08-09 18:32 ` [PATCH v5 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
@ 2019-08-09 18:32 ` Anshuman Gupta
2019-08-11 7:46 ` Anshuman Gupta
2019-08-13 14:46 ` Imre Deak
2019-08-09 18:32 ` [PATCH v5 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
` (13 subsequent siblings)
16 siblings, 2 replies; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-09 18:32 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these power domains will disallow
DC3CO when any external displays are connected and at
time of modeset and aux programming.
Renaming "DC Off" power well to "DC5 Off" power well.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_power.c | 69 ++++++++++++++++++-
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e2ef202aeeef..c9e92d48cdab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
-static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+ * Delay of 200us DC3CO Exit time B.Spec 49196
+ */
+ udelay(200);
+}
+
+void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
gen9_enable_dc5(dev_priv);
}
+static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ tgl_disallow_dc3co(dev_priv);
+}
+
+static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (!dev_priv->psr.sink_psr2_support)
+ return;
+
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_allow_dc3co(dev_priv);
+}
+
+static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ /*
+ * Checking alone DC_STATE_EN is not enough as DC5 power well also
+ * allow/disallow DC3CO to make sure both are not enabled at same time
+ */
+ return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
+}
+
static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \
+ TGL_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
TGL_PW_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
@@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
.is_enabled = gen9_dc_off_power_well_enabled,
};
+static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = tgl_dc3co_power_well_enable,
+ .disable = tgl_dc3co_power_well_disable,
+ .is_enabled = tgl_dc3co_power_well_enabled,
+};
+
static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = bxt_dpio_cmn_power_well_enable,
@@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "DC off",
+ .name = "DC5 off",
.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = DISP_PW_ID_NONE,
},
+ {
+ .name = "DC3CO off",
+ .domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
+ .ops = &tgl_dc3co_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
{
.name = "power well 2",
.domains = TGL_PW_2_POWER_DOMAINS,
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
2019-08-09 18:32 ` [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state Anshuman Gupta
@ 2019-08-11 7:46 ` Anshuman Gupta
2019-08-13 14:46 ` Imre Deak
1 sibling, 0 replies; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-11 7:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these power domains will disallow
DC3CO when any external displays are connected and at
time of modeset and aux programming.
Renaming "DC Off" power well to "DC5 Off" power well.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
v6: Fixed minor unwanted change.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_power.c | 67 ++++++++++++++++++-
1 file changed, 66 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e2ef202aeeef..7ca9992bb663 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -791,6 +791,25 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+ * Delay of 200us DC3CO Exit time B.Spec 49196
+ */
+ udelay(200);
+}
+
static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
gen9_enable_dc5(dev_priv);
}
+static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ tgl_disallow_dc3co(dev_priv);
+}
+
+static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (!dev_priv->psr.sink_psr2_support)
+ return;
+
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_allow_dc3co(dev_priv);
+}
+
+static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ /*
+ * Checking alone DC_STATE_EN is not enough as DC5 power well also
+ * allow/disallow DC3CO to make sure both are not enabled at same time
+ */
+ return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
+}
+
static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \
+ TGL_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
TGL_PW_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
@@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
.is_enabled = gen9_dc_off_power_well_enabled,
};
+static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = tgl_dc3co_power_well_enable,
+ .disable = tgl_dc3co_power_well_disable,
+ .is_enabled = tgl_dc3co_power_well_enabled,
+};
+
static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = bxt_dpio_cmn_power_well_enable,
@@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "DC off",
+ .name = "DC5 off",
.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = DISP_PW_ID_NONE,
},
+ {
+ .name = "DC3CO off",
+ .domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
+ .ops = &tgl_dc3co_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
{
.name = "power well 2",
.domains = TGL_PW_2_POWER_DOMAINS,
--
2.21.0
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^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
2019-08-09 18:32 ` [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state Anshuman Gupta
2019-08-11 7:46 ` Anshuman Gupta
@ 2019-08-13 14:46 ` Imre Deak
2019-08-27 13:01 ` Gupta, Anshuman
1 sibling, 1 reply; 31+ messages in thread
From: Imre Deak @ 2019-08-13 14:46 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx
On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
> "DC3CO Off" power well inherits its power domains from
> "DC Off" power well, these power domains will disallow
> DC3CO when any external displays are connected and at
> time of modeset and aux programming.
> Renaming "DC Off" power well to "DC5 Off" power well.
>
> v2: commit log improvement.
> v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
> Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
> Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
> to a appropriate place haswell_crtc_enable(). [Imre]
> Changed the DC3CO power well enabled call back logic as
> recommended in review comments. [Imre]
> v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
> v5: using udelay() instead of waiting for DC3CO exit status.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 69 ++++++++++++++++++-
> 1 file changed, 67 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index e2ef202aeeef..c9e92d48cdab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
> dev_priv->csr.dc_state = val & mask;
> }
>
> -static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> +{
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> +}
> +
> +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + val = I915_READ(DC_STATE_EN);
> + val &= ~DC_STATE_DC3CO_STATUS;
> + I915_WRITE(DC_STATE_EN, val);
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + /*
> + * Delay of 200us DC3CO Exit time B.Spec 49196
> + */
> + udelay(200);
> +}
> +
> +void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> {
> assert_can_enable_dc9(dev_priv);
>
> @@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> gen9_enable_dc5(dev_priv);
> }
>
> +static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
Should be called dc3co_off power well.
> +{
> + tgl_disallow_dc3co(dev_priv);
> +}
> +
> +static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + if (!dev_priv->psr.sink_psr2_support)
> + return;
We could end up enabling DC3CO while PSR2 is disabled after disabling
a PSR2 capable output, which is against the spec.
I'm thinking now that we should have a single dc_off power well and a
new interface setting the max allowed DC state (DC3CO, DC5/6).
(Right now I think there is also a missing re-enabling of DC3CO when
disabling DC5/6).
> +
> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
> + tgl_allow_dc3co(dev_priv);
> +}
> +
> +static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + /*
> + * Checking alone DC_STATE_EN is not enough as DC5 power well also
> + * allow/disallow DC3CO to make sure both are not enabled at same time
> + */
> + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> +}
> +
> static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> @@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> +#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \
> + TGL_PW_2_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> TGL_PW_2_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> @@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
> .is_enabled = gen9_dc_off_power_well_enabled,
> };
>
> +static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = tgl_dc3co_power_well_enable,
> + .disable = tgl_dc3co_power_well_disable,
> + .is_enabled = tgl_dc3co_power_well_enabled,
> +};
> +
> static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> .enable = bxt_dpio_cmn_power_well_enable,
> @@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> },
> },
> {
> - .name = "DC off",
> + .name = "DC5 off",
> .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> .ops = &gen9_dc_off_power_well_ops,
> .id = DISP_PW_ID_NONE,
> },
> + {
> + .name = "DC3CO off",
> + .domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
> + .ops = &tgl_dc3co_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + },
> {
> .name = "power well 2",
> .domains = TGL_PW_2_POWER_DOMAINS,
> --
> 2.21.0
>
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
2019-08-13 14:46 ` Imre Deak
@ 2019-08-27 13:01 ` Gupta, Anshuman
2019-08-27 13:20 ` Imre Deak
0 siblings, 1 reply; 31+ messages in thread
From: Gupta, Anshuman @ 2019-08-27 13:01 UTC (permalink / raw)
To: imre.deak; +Cc: jani.nikula, intel-gfx
On 8/13/2019 8:16 PM, Imre Deak wrote:
> On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
>> "DC3CO Off" power well inherits its power domains from
>> "DC Off" power well, these power domains will disallow
>> DC3CO when any external displays are connected and at
>> time of modeset and aux programming.
>> Renaming "DC Off" power well to "DC5 Off" power well.
>>
>> v2: commit log improvement.
>> v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
>> Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
>> Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
>> to a appropriate place haswell_crtc_enable(). [Imre]
>> Changed the DC3CO power well enabled call back logic as
>> recommended in review comments. [Imre]
>> v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
>> v5: using udelay() instead of waiting for DC3CO exit status.
>>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Animesh Manna <animesh.manna@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> ---
>> .../drm/i915/display/intel_display_power.c | 69 ++++++++++++++++++-
>> 1 file changed, 67 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index e2ef202aeeef..c9e92d48cdab 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
>> dev_priv->csr.dc_state = val & mask;
>> }
>>
>> -static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
>> +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
>> +{
>> + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
>> +}
>> +
>> +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
>> +{
>> + u32 val;
>> +
>> + val = I915_READ(DC_STATE_EN);
>> + val &= ~DC_STATE_DC3CO_STATUS;
>> + I915_WRITE(DC_STATE_EN, val);
>> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>> + /*
>> + * Delay of 200us DC3CO Exit time B.Spec 49196
>> + */
>> + udelay(200);
>> +}
>> +
>> +void bxt_enable_dc9(struct drm_i915_private *dev_priv)
>> {
>> assert_can_enable_dc9(dev_priv);
>>
>> @@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
>> gen9_enable_dc5(dev_priv);
>> }
>>
>> +static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
>> + struct i915_power_well *power_well)
>
> Should be called dc3co_off power well.
>
>> +{
>> + tgl_disallow_dc3co(dev_priv);
>> +}
>> +
>> +static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
>> + struct i915_power_well *power_well)
>> +{
>> + if (!dev_priv->psr.sink_psr2_support)
>> + return;
>
> We could end up enabling DC3CO while PSR2 is disabled after disabling
> a PSR2 capable output, which is against the spec.
>
> I'm thinking now that we should have a single dc_off power well and a
> new interface setting the max allowed DC state (DC3CO, DC5/6).
Hi Imre,
Could you please comment if below part of new API code
set_max_dc_state() is ok? with respect to our DC3CO design sync.
static void set_target_dc_state(struct drm_i915_private *dev_priv)
{
gen9_dc_off_power_well_disable(dev_priv, NULL);
}
void set_max_dc_state(struct drm_i915_private *dev_priv, u32 state)
{
bool dc_off_enabled;
struct i915_power_domains *power_domains =
&dev_priv->power_domains;
/* need to define an id for DC off power well "TGL_DISP_DC_OFF"*/
dc_off_enabled = intel_display_power_well_is_enabled(dev_priv,
TGL_DISP_DC_OFF);
mutex_lock(&power_domains->lock);
if (dc_off_enabled) {
dev_priv->csr.max_dc_state = state;
} else {
dev_priv->csr.max_dc_state = state;
set_target_dc_state(dev_priv);
}
mutex_unlock(&power_domains->lock);
}
gen9_dc_off_power_well_disable will enable max_dc_state to DC_STATE_EN
register accordingly. There can be only issue according to me here when
"DC off" power well is disable (this will happen when we want to set
max_dc_state to dc5 in dc5_idle_thread). In that case we need to
manually call set_target_dc_state()->gen9_dc_off_power_well_disable().
Thanks,
Anshuman Gupta.
>
> (Right now I think there is also a missing re-enabling of DC3CO when
> disabling DC5/6).
>
>> +
>> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
>> + tgl_allow_dc3co(dev_priv);
>> +}
>> +
>> +static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
>> + struct i915_power_well *power_well)
>> +{
>> + /*
>> + * Checking alone DC_STATE_EN is not enough as DC5 power well also
>> + * allow/disallow DC3CO to make sure both are not enabled at same time
>> + */
>> + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
>> + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
>> +}
>> +
>> static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
>> struct i915_power_well *power_well)
>> {
>> @@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
>> BIT_ULL(POWER_DOMAIN_INIT))
>>
>> +#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \
>> + TGL_PW_2_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_MODESET) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>> +
>> #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>> TGL_PW_2_POWER_DOMAINS | \
>> BIT_ULL(POWER_DOMAIN_MODESET) | \
>> @@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
>> .is_enabled = gen9_dc_off_power_well_enabled,
>> };
>>
>> +static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
>> + .sync_hw = i9xx_power_well_sync_hw_noop,
>> + .enable = tgl_dc3co_power_well_enable,
>> + .disable = tgl_dc3co_power_well_disable,
>> + .is_enabled = tgl_dc3co_power_well_enabled,
>> +};
>> +
>> static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
>> .sync_hw = i9xx_power_well_sync_hw_noop,
>> .enable = bxt_dpio_cmn_power_well_enable,
>> @@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>> },
>> },
>> {
>> - .name = "DC off",
>> + .name = "DC5 off",
>> .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
>> .ops = &gen9_dc_off_power_well_ops,
>> .id = DISP_PW_ID_NONE,
>> },
>> + {
>> + .name = "DC3CO off",
>> + .domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
>> + .ops = &tgl_dc3co_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + },
>> {
>> .name = "power well 2",
>> .domains = TGL_PW_2_POWER_DOMAINS,
>> --
>> 2.21.0
>>
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
2019-08-27 13:01 ` Gupta, Anshuman
@ 2019-08-27 13:20 ` Imre Deak
2019-08-27 16:17 ` Gupta, Anshuman
0 siblings, 1 reply; 31+ messages in thread
From: Imre Deak @ 2019-08-27 13:20 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: jani.nikula, intel-gfx
On Tue, Aug 27, 2019 at 06:31:31PM +0530, Gupta, Anshuman wrote:
>
>
> On 8/13/2019 8:16 PM, Imre Deak wrote:
> > On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
> > > "DC3CO Off" power well inherits its power domains from
> > > "DC Off" power well, these power domains will disallow
> > > DC3CO when any external displays are connected and at
> > > time of modeset and aux programming.
> > > Renaming "DC Off" power well to "DC5 Off" power well.
> > >
> > > v2: commit log improvement.
> > > v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
> > > Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
> > > Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
> > > to a appropriate place haswell_crtc_enable(). [Imre]
> > > Changed the DC3CO power well enabled call back logic as
> > > recommended in review comments. [Imre]
> > > v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
> > > v5: using udelay() instead of waiting for DC3CO exit status.
> > >
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Animesh Manna <animesh.manna@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_power.c | 69 ++++++++++++++++++-
> > > 1 file changed, 67 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index e2ef202aeeef..c9e92d48cdab 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
> > > dev_priv->csr.dc_state = val & mask;
> > > }
> > > -static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> > > +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> > > +{
> > > + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> > > +}
> > > +
> > > +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
> > > +{
> > > + u32 val;
> > > +
> > > + val = I915_READ(DC_STATE_EN);
> > > + val &= ~DC_STATE_DC3CO_STATUS;
> > > + I915_WRITE(DC_STATE_EN, val);
> > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > + /*
> > > + * Delay of 200us DC3CO Exit time B.Spec 49196
> > > + */
> > > + udelay(200);
> > > +}
> > > +
> > > +void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> > > {
> > > assert_can_enable_dc9(dev_priv);
> > > @@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> > > gen9_enable_dc5(dev_priv);
> > > }
> > > +static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
> > > + struct i915_power_well *power_well)
> >
> > Should be called dc3co_off power well.
> >
> > > +{
> > > + tgl_disallow_dc3co(dev_priv);
> > > +}
> > > +
> > > +static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
> > > + struct i915_power_well *power_well)
> > > +{
> > > + if (!dev_priv->psr.sink_psr2_support)
> > > + return;
> >
> > We could end up enabling DC3CO while PSR2 is disabled after disabling
> > a PSR2 capable output, which is against the spec.
> >
> > I'm thinking now that we should have a single dc_off power well and a
> > new interface setting the max allowed DC state (DC3CO, DC5/6).
> Hi Imre,
>
> Could you please comment if below part of new API code set_max_dc_state() is
> ok? with respect to our DC3CO design sync.
>
> static void set_target_dc_state(struct drm_i915_private *dev_priv)
> {
> gen9_dc_off_power_well_disable(dev_priv, NULL);
> }
>
> void set_max_dc_state(struct drm_i915_private *dev_priv, u32 state)
> {
> bool dc_off_enabled;
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> /* need to define an id for DC off power well "TGL_DISP_DC_OFF"*/
> dc_off_enabled = intel_display_power_well_is_enabled(dev_priv,
> TGL_DISP_DC_OFF);
dc_off_enabled can get stale this way until you acquire the lock.
Probably easier to lookup_power_well() and then check its state with the
lock held.
>
> mutex_lock(&power_domains->lock);
> if (dc_off_enabled) {
> dev_priv->csr.max_dc_state = state;
> } else {
> dev_priv->csr.max_dc_state = state;
> set_target_dc_state(dev_priv);
> }
> mutex_unlock(&power_domains->lock);
> }
> gen9_dc_off_power_well_disable will enable max_dc_state to DC_STATE_EN
> register accordingly.
>
> There can be only issue according to me here when "DC off" power well
> is disable (this will happen when we want to set max_dc_state to dc5
> in dc5_idle_thread). In that case we need to manually call
> set_target_dc_state()->gen9_dc_off_power_well_disable().
In that case you could just call power_well->enable(), ->disable(), and
in the ->disable() hook you'd enable the DC state accorindg to
csr.max_dc_state?
>
> Thanks,
> Anshuman Gupta.
> >
> > (Right now I think there is also a missing re-enabling of DC3CO when
> > disabling DC5/6).
> >
> > > +
> > > + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
> > > + tgl_allow_dc3co(dev_priv);
> > > +}
> > > +
> > > +static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
> > > + struct i915_power_well *power_well)
> > > +{
> > > + /*
> > > + * Checking alone DC_STATE_EN is not enough as DC5 power well also
> > > + * allow/disallow DC3CO to make sure both are not enabled at same time
> > > + */
> > > + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> > > + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> > > +}
> > > +
> > > static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
> > > struct i915_power_well *power_well)
> > > {
> > > @@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > > BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> > > BIT_ULL(POWER_DOMAIN_INIT))
> > > +#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \
> > > + TGL_PW_2_POWER_DOMAINS | \
> > > + BIT_ULL(POWER_DOMAIN_MODESET) | \
> > > + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > > + BIT_ULL(POWER_DOMAIN_INIT))
> > > +
> > > #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > > TGL_PW_2_POWER_DOMAINS | \
> > > BIT_ULL(POWER_DOMAIN_MODESET) | \
> > > @@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
> > > .is_enabled = gen9_dc_off_power_well_enabled,
> > > };
> > > +static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
> > > + .sync_hw = i9xx_power_well_sync_hw_noop,
> > > + .enable = tgl_dc3co_power_well_enable,
> > > + .disable = tgl_dc3co_power_well_disable,
> > > + .is_enabled = tgl_dc3co_power_well_enabled,
> > > +};
> > > +
> > > static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
> > > .sync_hw = i9xx_power_well_sync_hw_noop,
> > > .enable = bxt_dpio_cmn_power_well_enable,
> > > @@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > > },
> > > },
> > > {
> > > - .name = "DC off",
> > > + .name = "DC5 off",
> > > .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > > .ops = &gen9_dc_off_power_well_ops,
> > > .id = DISP_PW_ID_NONE,
> > > },
> > > + {
> > > + .name = "DC3CO off",
> > > + .domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
> > > + .ops = &tgl_dc3co_power_well_ops,
> > > + .id = DISP_PW_ID_NONE,
> > > + },
> > > {
> > > .name = "power well 2",
> > > .domains = TGL_PW_2_POWER_DOMAINS,
> > > --
> > > 2.21.0
> > >
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state
2019-08-27 13:20 ` Imre Deak
@ 2019-08-27 16:17 ` Gupta, Anshuman
0 siblings, 0 replies; 31+ messages in thread
From: Gupta, Anshuman @ 2019-08-27 16:17 UTC (permalink / raw)
To: imre.deak; +Cc: jani.nikula, intel-gfx
On 8/27/2019 6:50 PM, Imre Deak wrote:
> On Tue, Aug 27, 2019 at 06:31:31PM +0530, Gupta, Anshuman wrote:
>>
>>
>> On 8/13/2019 8:16 PM, Imre Deak wrote:
>>> On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
>>>> "DC3CO Off" power well inherits its power domains from
>>>> "DC Off" power well, these power domains will disallow
>>>> DC3CO when any external displays are connected and at
>>>> time of modeset and aux programming.
>>>> Renaming "DC Off" power well to "DC5 Off" power well.
>>>>
>>>> v2: commit log improvement.
>>>> v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
>>>> Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
>>>> Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
>>>> to a appropriate place haswell_crtc_enable(). [Imre]
>>>> Changed the DC3CO power well enabled call back logic as
>>>> recommended in review comments. [Imre]
>>>> v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
>>>> v5: using udelay() instead of waiting for DC3CO exit status.
>>>>
>>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>> Cc: Imre Deak <imre.deak@intel.com>
>>>> Cc: Animesh Manna <animesh.manna@intel.com>
>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>>>> ---
>>>> .../drm/i915/display/intel_display_power.c | 69 ++++++++++++++++++-
>>>> 1 file changed, 67 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>>> index e2ef202aeeef..c9e92d48cdab 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>>> @@ -791,7 +791,26 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
>>>> dev_priv->csr.dc_state = val & mask;
>>>> }
>>>> -static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
>>>> +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
>>>> +{
>>>> + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
>>>> +}
>>>> +
>>>> +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
>>>> +{
>>>> + u32 val;
>>>> +
>>>> + val = I915_READ(DC_STATE_EN);
>>>> + val &= ~DC_STATE_DC3CO_STATUS;
>>>> + I915_WRITE(DC_STATE_EN, val);
>>>> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>>>> + /*
>>>> + * Delay of 200us DC3CO Exit time B.Spec 49196
>>>> + */
>>>> + udelay(200);
>>>> +}
>>>> +
>>>> +void bxt_enable_dc9(struct drm_i915_private *dev_priv)
>>>> {
>>>> assert_can_enable_dc9(dev_priv);
>>>> @@ -1007,6 +1026,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
>>>> gen9_enable_dc5(dev_priv);
>>>> }
>>>> +static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
>>>> + struct i915_power_well *power_well)
>>>
>>> Should be called dc3co_off power well.
>>>
>>>> +{
>>>> + tgl_disallow_dc3co(dev_priv);
>>>> +}
>>>> +
>>>> +static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
>>>> + struct i915_power_well *power_well)
>>>> +{
>>>> + if (!dev_priv->psr.sink_psr2_support)
>>>> + return;
>>>
>>> We could end up enabling DC3CO while PSR2 is disabled after disabling
>>> a PSR2 capable output, which is against the spec.
>>>
>>> I'm thinking now that we should have a single dc_off power well and a
>>> new interface setting the max allowed DC state (DC3CO, DC5/6).
>> Hi Imre,
>>
>> Could you please comment if below part of new API code set_max_dc_state() is
>> ok? with respect to our DC3CO design sync.
>>
>> static void set_target_dc_state(struct drm_i915_private *dev_priv)
>> {
>> gen9_dc_off_power_well_disable(dev_priv, NULL);
>> }
>>
>> void set_max_dc_state(struct drm_i915_private *dev_priv, u32 state)
>> {
>> bool dc_off_enabled;
>> struct i915_power_domains *power_domains = &dev_priv->power_domains;
>> /* need to define an id for DC off power well "TGL_DISP_DC_OFF"*/
>> dc_off_enabled = intel_display_power_well_is_enabled(dev_priv,
>> TGL_DISP_DC_OFF);
>
> dc_off_enabled can get stale this way until you acquire the lock.
> Probably easier to lookup_power_well() and then check its state with the
> lock held.
>
>>
>> mutex_lock(&power_domains->lock);
>> if (dc_off_enabled) {
>> dev_priv->csr.max_dc_state = state;
>> } else {
>> dev_priv->csr.max_dc_state = state;
>> set_target_dc_state(dev_priv);
>> }
>> mutex_unlock(&power_domains->lock);
>> }
>
>> gen9_dc_off_power_well_disable will enable max_dc_state to DC_STATE_EN
>> register accordingly.
>>
>> There can be only issue according to me here when "DC off" power well
>> is disable (this will happen when we want to set max_dc_state to dc5
>> in dc5_idle_thread). In that case we need to manually call
>> set_target_dc_state()->gen9_dc_off_power_well_disable().
>
> In that case you could just call power_well->enable(), ->disable(), and
> in the ->disable() hook you'd enable the DC state accorindg to
> csr.max_dc_state?
Thanks for suggestion, will incorporate suggesting approach.
Thanks,
Anshuman
>
>>
>> Thanks,
>> Anshuman Gupta.
>>>
>>> (Right now I think there is also a missing re-enabling of DC3CO when
>>> disabling DC5/6).
>>>
>>>> +
>>>> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
>>>> + tgl_allow_dc3co(dev_priv);
>>>> +}
>>>> +
>>>> +static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
>>>> + struct i915_power_well *power_well)
>>>> +{
>>>> + /*
>>>> + * Checking alone DC_STATE_EN is not enough as DC5 power well also
>>>> + * allow/disallow DC3CO to make sure both are not enabled at same time
>>>> + */
>>>> + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
>>>> + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
>>>> +}
>>>> +
>>>> static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
>>>> struct i915_power_well *power_well)
>>>> {
>>>> @@ -2611,6 +2657,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>>>> BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
>>>> BIT_ULL(POWER_DOMAIN_INIT))
>>>> +#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \
>>>> + TGL_PW_2_POWER_DOMAINS | \
>>>> + BIT_ULL(POWER_DOMAIN_MODESET) | \
>>>> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
>>>> + BIT_ULL(POWER_DOMAIN_INIT))
>>>> +
>>>> #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>>>> TGL_PW_2_POWER_DOMAINS | \
>>>> BIT_ULL(POWER_DOMAIN_MODESET) | \
>>>> @@ -2715,6 +2767,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
>>>> .is_enabled = gen9_dc_off_power_well_enabled,
>>>> };
>>>> +static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
>>>> + .sync_hw = i9xx_power_well_sync_hw_noop,
>>>> + .enable = tgl_dc3co_power_well_enable,
>>>> + .disable = tgl_dc3co_power_well_disable,
>>>> + .is_enabled = tgl_dc3co_power_well_enabled,
>>>> +};
>>>> +
>>>> static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
>>>> .sync_hw = i9xx_power_well_sync_hw_noop,
>>>> .enable = bxt_dpio_cmn_power_well_enable,
>>>> @@ -3626,11 +3685,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>>>> },
>>>> },
>>>> {
>>>> - .name = "DC off",
>>>> + .name = "DC5 off",
>>>> .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
>>>> .ops = &gen9_dc_off_power_well_ops,
>>>> .id = DISP_PW_ID_NONE,
>>>> },
>>>> + {
>>>> + .name = "DC3CO off",
>>>> + .domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
>>>> + .ops = &tgl_dc3co_power_well_ops,
>>>> + .id = DISP_PW_ID_NONE,
>>>> + },
>>>> {
>>>> .name = "power well 2",
>>>> .domains = TGL_PW_2_POWER_DOMAINS,
>>>> --
>>>> 2.21.0
>>>>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (2 preceding siblings ...)
2019-08-09 18:32 ` [PATCH v5 3/9] drm/i915/tgl: Add power well to enable DC3CO state Anshuman Gupta
@ 2019-08-09 18:32 ` Anshuman Gupta
2019-08-13 14:52 ` Imre Deak
2019-08-09 18:32 ` [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 Anshuman Gupta
` (12 subsequent siblings)
16 siblings, 1 reply; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-09 18:32 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
As per B.Specs DC5 and DC6 not allowed when DC3CO is enabled
and DC3CO should be enabled only during VIDEO playback.
Which essentially means both can DC5 and DC3CO can not be
enabled at same time, it makes DC3CO and DC5 mutual exclusive.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c9e92d48cdab..167839060154 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -996,6 +996,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /* DC3CO and DC5/6 are mutually exclusive */
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_allow_dc3co(dev_priv);
+
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -1020,6 +1024,10 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
if (!dev_priv->csr.dmc_payload)
return;
+ /* DC3CO and DC5/6 are mutually exclusive */
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_disallow_dc3co(dev_priv);
+
if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(dev_priv);
else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
--
2.21.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
2019-08-09 18:32 ` [PATCH v5 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
@ 2019-08-13 14:52 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2019-08-13 14:52 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx
On Sat, Aug 10, 2019 at 12:02:18AM +0530, Anshuman Gupta wrote:
> As per B.Specs DC5 and DC6 not allowed when DC3CO is enabled
> and DC3CO should be enabled only during VIDEO playback.
> Which essentially means both can DC5 and DC3CO can not be
> enabled at same time, it makes DC3CO and DC5 mutual exclusive.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c9e92d48cdab..167839060154 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -996,6 +996,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> + /* DC3CO and DC5/6 are mutually exclusive */
> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
> + tgl_allow_dc3co(dev_priv);
Ah ok, here is the re-enabling I was looking for in the previous patch.
I think this change could've been part of the previous patch. However
this re-enables DC3CO regardless of any PSR2 condition.
> +
> dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
> /* Can't read out voltage_level so can't use intel_cdclk_changed() */
> WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
> @@ -1020,6 +1024,10 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> if (!dev_priv->csr.dmc_payload)
> return;
>
> + /* DC3CO and DC5/6 are mutually exclusive */
> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
> + tgl_disallow_dc3co(dev_priv);
> +
> if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
> skl_enable_dc6(dev_priv);
> else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
> --
> 2.21.0
>
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (3 preceding siblings ...)
2019-08-09 18:32 ` [PATCH v5 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
@ 2019-08-09 18:32 ` Anshuman Gupta
2019-08-13 15:47 ` Imre Deak
2019-08-14 9:46 ` Imre Deak
2019-08-09 18:32 ` [PATCH v5 6/9] drm/i915/tgl: Add VIDEO power domain Anshuman Gupta
` (11 subsequent siblings)
16 siblings, 2 replies; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-09 18:32 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
We need to have a S/W flag based upon which driver can switch to DC3CO.
If it is only edp display connected and it has psr2 capability,
then set a prefer_dc3co flag to true, which will be used to
switch to dc3co as well as to program DC3CO PSR2 transcoder
early exitline event.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915/display/intel_display_power.c | 105 ++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 5 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_pm.h | 2 +
6 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 647f49ca86ff..1ec204c14a10 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6448,6 +6448,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (WARN_ON(intel_crtc->active))
return;
+ /* Enable PSR2 transcoder exit line */
+ if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
+ tgl_enable_psr2_transcoder_exitline(pipe_config);
intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
@@ -13685,6 +13688,8 @@ static int intel_atomic_check(struct drm_device *dev,
"[modeset]" : "[fastset]");
}
+ tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
+
return 0;
fail:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 167839060154..04a02c88ff93 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -18,6 +18,7 @@
#include "intel_hotplug.h"
#include "intel_sideband.h"
#include "intel_tc.h"
+#include "intel_pm.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -791,6 +792,110 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate)
+{
+ u32 linetime_us, val, exit_scanlines;
+ u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+ if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
+ return;
+
+ linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
+ if (WARN_ON(!linetime_us))
+ return;
+ /*
+ * DC3CO Exit time 200us B.Spec 49196
+ * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+ * Exit line event need to program above calculated scan lines before
+ * next VBLANK.
+ */
+ exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
+ if (WARN_ON(exit_scanlines > crtc_vdisplay))
+ return;
+
+ exit_scanlines = crtc_vdisplay - exit_scanlines;
+ exit_scanlines <<= EXITLINE_SHIFT;
+ val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+ val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+ val |= exit_scanlines;
+ val |= EXITLINE_ENABLE;
+ I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state)
+{
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_connector *connector, *edp_connector = NULL;
+ struct drm_connector_state *connector_state;
+ int i;
+
+ for_each_new_connector_in_state(state, connector, connector_state, i) {
+ if (connector_state->crtc != &crtc->base)
+ continue;
+
+ if (connector->status == connector_status_connected &&
+ connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+ return false;
+ else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
+ connector->status == connector_status_connected)
+ edp_connector = connector;
+ }
+
+ if (edp_connector)
+ return true;
+
+ return false;
+}
+
+/*
+ * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
+ * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
+ * edp display should be connected.
+ * TODO: Prefer DC3CO over DC5 only in video playback.
+ */
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc_state *crtc_state, *mode_changed_cstate;
+ struct intel_crtc *crtc;
+ int i;
+ u32 val;
+
+ dev_priv->csr.prefer_dc3co = false;
+
+ if (!IS_TIGERLAKE(dev_priv))
+ return;
+
+ if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ return;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ if (crtc->pipe == PIPE_A)
+ mode_changed_cstate = crtc_state;
+ if (!crtc_state->has_psr2 && crtc_state->base.active) {
+ dev_priv->csr.prefer_dc3co = false;
+ return;
+ } else if (crtc_state->has_psr2) {
+ if (tgl_is_only_edp_connected(crtc_state) &&
+ crtc_state->base.active) {
+ dev_priv->csr.prefer_dc3co = true;
+ continue;
+ } else {
+ dev_priv->csr.prefer_dc3co = false;
+ return;
+ }
+ }
+ }
+
+ if (dev_priv->csr.prefer_dc3co) {
+ val = I915_READ(EXITLINE(mode_changed_cstate->cpu_transcoder));
+ if (!(val & EXITLINE_ENABLE))
+ mode_changed_cstate->base.mode_changed = true;
+ }
+}
+
static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
{
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 97f2562fc5d3..46e1bcfa490a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -12,6 +12,8 @@
struct drm_i915_private;
struct intel_encoder;
+struct intel_crtc_state;
+struct intel_atomic_state;
enum intel_display_power_domain {
POWER_DOMAIN_DISPLAY_CORE,
@@ -246,6 +248,9 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915);
void intel_display_power_resume_early(struct drm_i915_private *i915);
void intel_display_power_suspend(struct drm_i915_private *i915);
void intel_display_power_resume(struct drm_i915_private *i915);
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+ struct intel_atomic_state *state);
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate);
const char *
intel_display_power_domain_str(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3cdb5bf489f2..7ca0703209a4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -332,6 +332,7 @@ struct intel_csr {
u32 dc_state;
u32 allowed_dc_mask;
intel_wakeref_t wakeref;
+ bool prefer_dc3co;
};
enum i915_cache_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 780df8db2eba..634e43219164 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4584,7 +4584,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
return ret;
}
-static uint_fixed_16_16_t
+uint_fixed_16_16_t
intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
{
u32 pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index e3573e1e16e3..454e92c06dff 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
+#include "i915_drv.h"
#include "i915_reg.h"
struct drm_device;
@@ -76,6 +77,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
+uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate);
unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5
2019-08-09 18:32 ` [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 Anshuman Gupta
@ 2019-08-13 15:47 ` Imre Deak
2019-08-19 12:57 ` Gupta, Anshuman
2019-08-14 9:46 ` Imre Deak
1 sibling, 1 reply; 31+ messages in thread
From: Imre Deak @ 2019-08-13 15:47 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx
On Sat, Aug 10, 2019 at 12:02:19AM +0530, Anshuman Gupta wrote:
> We need to have a S/W flag based upon which driver can switch to DC3CO.
> If it is only edp display connected and it has psr2 capability,
> then set a prefer_dc3co flag to true, which will be used to
> switch to dc3co as well as to program DC3CO PSR2 transcoder
> early exitline event.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +
> .../drm/i915/display/intel_display_power.c | 105 ++++++++++++++++++
> .../drm/i915/display/intel_display_power.h | 5 +
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.h | 2 +
> 6 files changed, 119 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 647f49ca86ff..1ec204c14a10 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6448,6 +6448,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> if (WARN_ON(intel_crtc->active))
> return;
> + /* Enable PSR2 transcoder exit line */
> + if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
> + tgl_enable_psr2_transcoder_exitline(pipe_config);
This is part of PSR2 programming, so should be done somewhere below
intel_psr_enable() imo.
>
> intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
>
> @@ -13685,6 +13688,8 @@ static int intel_atomic_check(struct drm_device *dev,
> "[modeset]" : "[fastset]");
> }
>
> + tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
I think this belongs to intel_modeset_checks(), where we could also do
all necessary pipe locking (since now I can't see how we would prevent
allowing DC3CO when an external output is enabled asynchronously). This
would be akin to CDCLK rate change, but I defer on this to Ville.
> +
> return 0;
>
> fail:
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 167839060154..04a02c88ff93 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -18,6 +18,7 @@
> #include "intel_hotplug.h"
> #include "intel_sideband.h"
> #include "intel_tc.h"
> +#include "intel_pm.h"
>
> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> enum i915_power_well_id power_well_id);
> @@ -791,6 +792,110 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
> dev_priv->csr.dc_state = val & mask;
> }
>
> +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate)
> +{
> + u32 linetime_us, val, exit_scanlines;
> + u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
> + struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> +
> + if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
> + return;
Where's the TRANSCODER-A restriction coming from?
> +
> + linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
> + if (WARN_ON(!linetime_us))
> + return;
> + /*
> + * DC3CO Exit time 200us B.Spec 49196
> + * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
> + * Exit line event need to program above calculated scan lines before
> + * next VBLANK.
> + */
> + exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
> + if (WARN_ON(exit_scanlines > crtc_vdisplay))
> + return;
> +
> + exit_scanlines = crtc_vdisplay - exit_scanlines;
> + exit_scanlines <<= EXITLINE_SHIFT;
> + val = I915_READ(EXITLINE(cstate->cpu_transcoder));
> + val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
> + val |= exit_scanlines;
> + val |= EXITLINE_ENABLE;
> + I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
> +}
> +
> +static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_atomic_state *state = crtc_state->base.state;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_connector *connector, *edp_connector = NULL;
> + struct drm_connector_state *connector_state;
> + int i;
> +
> + for_each_new_connector_in_state(state, connector, connector_state, i) {
> + if (connector_state->crtc != &crtc->base)
> + continue;
> +
> + if (connector->status == connector_status_connected &&
> + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> + return false;
> + else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
> + connector->status == connector_status_connected)
> + edp_connector = connector;
> + }
> +
> + if (edp_connector)
> + return true;
> +
> + return false;
> +}
> +
> +/*
> + * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
> + * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
> + * edp display should be connected.
> + * TODO: Prefer DC3CO over DC5 only in video playback.
> + */
> +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
> + struct intel_atomic_state *state)
> +{
> + struct intel_crtc_state *crtc_state, *mode_changed_cstate;
> + struct intel_crtc *crtc;
> + int i;
> + u32 val;
> +
> + dev_priv->csr.prefer_dc3co = false;
> +
> + if (!IS_TIGERLAKE(dev_priv))
> + return;
> +
> + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
> + return;
> +
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> + if (crtc->pipe == PIPE_A)
> + mode_changed_cstate = crtc_state;
Where is the PIPE-A restriction coming from? Couldn't we simply pick the
crtc state that has the PSR2 sink?
> + if (!crtc_state->has_psr2 && crtc_state->base.active) {
> + dev_priv->csr.prefer_dc3co = false;
> + return;
> + } else if (crtc_state->has_psr2) {
> + if (tgl_is_only_edp_connected(crtc_state) &&
> + crtc_state->base.active) {
> + dev_priv->csr.prefer_dc3co = true;
> + continue;
> + } else {
> + dev_priv->csr.prefer_dc3co = false;
> + return;
> + }
> + }
> + }
> +
> + if (dev_priv->csr.prefer_dc3co) {
> + val = I915_READ(EXITLINE(mode_changed_cstate->cpu_transcoder));
No HW access during the modeset check phase is the rule. You could just
use the old prefer_dc3co value, no?
> + if (!(val & EXITLINE_ENABLE))
> + mode_changed_cstate->base.mode_changed = true;
> + }
> +}
> +
> static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> {
> gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 97f2562fc5d3..46e1bcfa490a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -12,6 +12,8 @@
>
> struct drm_i915_private;
> struct intel_encoder;
> +struct intel_crtc_state;
> +struct intel_atomic_state;
>
> enum intel_display_power_domain {
> POWER_DOMAIN_DISPLAY_CORE,
> @@ -246,6 +248,9 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915);
> void intel_display_power_resume_early(struct drm_i915_private *i915);
> void intel_display_power_suspend(struct drm_i915_private *i915);
> void intel_display_power_resume(struct drm_i915_private *i915);
> +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
> + struct intel_atomic_state *state);
> +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate);
>
> const char *
> intel_display_power_domain_str(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3cdb5bf489f2..7ca0703209a4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -332,6 +332,7 @@ struct intel_csr {
> u32 dc_state;
> u32 allowed_dc_mask;
> intel_wakeref_t wakeref;
> + bool prefer_dc3co;
> };
>
> enum i915_cache_level {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 780df8db2eba..634e43219164 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4584,7 +4584,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
> return ret;
> }
>
> -static uint_fixed_16_16_t
> +uint_fixed_16_16_t
> intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> {
> u32 pixel_rate;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index e3573e1e16e3..454e92c06dff 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -8,6 +8,7 @@
>
> #include <linux/types.h>
>
> +#include "i915_drv.h"
> #include "i915_reg.h"
>
> struct drm_device;
> @@ -76,6 +77,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
> u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
>
> u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
> +uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate);
>
> unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
> unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
> --
> 2.21.0
>
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5
2019-08-13 15:47 ` Imre Deak
@ 2019-08-19 12:57 ` Gupta, Anshuman
2019-08-19 13:23 ` Imre Deak
0 siblings, 1 reply; 31+ messages in thread
From: Gupta, Anshuman @ 2019-08-19 12:57 UTC (permalink / raw)
To: imre.deak, Ville Syrjälä; +Cc: jani.nikula, intel-gfx
On 8/13/2019 9:17 PM, Imre Deak wrote:
> On Sat, Aug 10, 2019 at 12:02:19AM +0530, Anshuman Gupta wrote:
>> We need to have a S/W flag based upon which driver can switch to DC3CO.
>> If it is only edp display connected and it has psr2 capability,
>> then set a prefer_dc3co flag to true, which will be used to
>> switch to dc3co as well as to program DC3CO PSR2 transcoder
>> early exitline event.
>>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Animesh Manna <animesh.manna@intel.com>
>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 5 +
>> .../drm/i915/display/intel_display_power.c | 105 ++++++++++++++++++
>> .../drm/i915/display/intel_display_power.h | 5 +
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_pm.c | 2 +-
>> drivers/gpu/drm/i915/intel_pm.h | 2 +
>> 6 files changed, 119 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 647f49ca86ff..1ec204c14a10 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -6448,6 +6448,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>>
>> if (WARN_ON(intel_crtc->active))
>> return;
>> + /* Enable PSR2 transcoder exit line */
>> + if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
>> + tgl_enable_psr2_transcoder_exitline(pipe_config);
>
> This is part of PSR2 programming, so should be done somewhere below
> intel_psr_enable() imo.
>
>>
>> intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
>>
>> @@ -13685,6 +13688,8 @@ static int intel_atomic_check(struct drm_device *dev,
>> "[modeset]" : "[fastset]");
>> }
>>
>> + tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
>
> I think this belongs to intel_modeset_checks(), where we could also do
> all necessary pipe locking (since now I can't see how we would prevent
> allowing DC3CO when an external output is enabled asynchronously). This
> would be akin to CDCLK rate change, but I defer on this to Ville.
Hi Ville,
Could you please provide your inputs on DC3CO design perspective,
whether we should have pipe locking in order to maintain consistent
state for dc3co.
I feel there can be two way to maintain consistent state.
1. Ensure necessary locking on current crtc before calculating
prefer_dc3co state, this will block the asynchronous commit.
2. We can make the prefer_dc3co state to false from enable powerwell
callback which will trigger by getting a reference count for PG2 power
domains if any external output is enabled.
(DC3CO will be disallowed from power well enable callback if any
external output is enabled akin to DC5/DC6, here we want to make
prefer_dc3co atomic state consistent).
Thanks ,
Anshuman Gupta.
>
>> +
>> return 0;
>>
>> fail:
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 167839060154..04a02c88ff93 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -18,6 +18,7 @@
>> #include "intel_hotplug.h"
>> #include "intel_sideband.h"
>> #include "intel_tc.h"
>> +#include "intel_pm.h"
>>
>> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
>> enum i915_power_well_id power_well_id);
>> @@ -791,6 +792,110 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
>> dev_priv->csr.dc_state = val & mask;
>> }
>>
>> +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate)
>> +{
>> + u32 linetime_us, val, exit_scanlines;
>> + u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
>> + struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
>> +
>> + if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
>> + return;
>
> Where's the TRANSCODER-A restriction coming from?
>
>> +
>> + linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
>> + if (WARN_ON(!linetime_us))
>> + return;
>> + /*
>> + * DC3CO Exit time 200us B.Spec 49196
>> + * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
>> + * Exit line event need to program above calculated scan lines before
>> + * next VBLANK.
>> + */
>> + exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
>> + if (WARN_ON(exit_scanlines > crtc_vdisplay))
>> + return;
>> +
>> + exit_scanlines = crtc_vdisplay - exit_scanlines;
>> + exit_scanlines <<= EXITLINE_SHIFT;
>> + val = I915_READ(EXITLINE(cstate->cpu_transcoder));
>> + val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
>> + val |= exit_scanlines;
>> + val |= EXITLINE_ENABLE;
>> + I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
>> +}
>> +
>> +static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state)
>> +{
>> + struct drm_atomic_state *state = crtc_state->base.state;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + struct drm_connector *connector, *edp_connector = NULL;
>> + struct drm_connector_state *connector_state;
>> + int i;
>> +
>> + for_each_new_connector_in_state(state, connector, connector_state, i) {
>> + if (connector_state->crtc != &crtc->base)
>> + continue;
>> +
>> + if (connector->status == connector_status_connected &&
>> + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
>> + return false;
>> + else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
>> + connector->status == connector_status_connected)
>> + edp_connector = connector;
>> + }
>> +
>> + if (edp_connector)
>> + return true;
>> +
>> + return false;
>> +}
>> +
>> +/*
>> + * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
>> + * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
>> + * edp display should be connected.
>> + * TODO: Prefer DC3CO over DC5 only in video playback.
>> + */
>> +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
>> + struct intel_atomic_state *state)
>> +{
>> + struct intel_crtc_state *crtc_state, *mode_changed_cstate;
>> + struct intel_crtc *crtc;
>> + int i;
>> + u32 val;
>> +
>> + dev_priv->csr.prefer_dc3co = false;
>> +
>> + if (!IS_TIGERLAKE(dev_priv))
>> + return;
>> +
>> + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
>> + return;
>> +
>> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
>> + if (crtc->pipe == PIPE_A)
>> + mode_changed_cstate = crtc_state;
>
> Where is the PIPE-A restriction coming from? Couldn't we simply pick the
> crtc state that has the PSR2 sink?
>
>> + if (!crtc_state->has_psr2 && crtc_state->base.active) {
>> + dev_priv->csr.prefer_dc3co = false;
>> + return;
>> + } else if (crtc_state->has_psr2) {
>> + if (tgl_is_only_edp_connected(crtc_state) &&
>> + crtc_state->base.active) {
>> + dev_priv->csr.prefer_dc3co = true;
>> + continue;
>> + } else {
>> + dev_priv->csr.prefer_dc3co = false;
>> + return;
>> + }
>> + }
>> + }
>> +
>> + if (dev_priv->csr.prefer_dc3co) {
>> + val = I915_READ(EXITLINE(mode_changed_cstate->cpu_transcoder));
>
> No HW access during the modeset check phase is the rule. You could just
> use the old prefer_dc3co value, no?
>
>> + if (!(val & EXITLINE_ENABLE))
>> + mode_changed_cstate->base.mode_changed = true;
>> + }
>> +}
>> +
>> static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
>> {
>> gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index 97f2562fc5d3..46e1bcfa490a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -12,6 +12,8 @@
>>
>> struct drm_i915_private;
>> struct intel_encoder;
>> +struct intel_crtc_state;
>> +struct intel_atomic_state;
>>
>> enum intel_display_power_domain {
>> POWER_DOMAIN_DISPLAY_CORE,
>> @@ -246,6 +248,9 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915);
>> void intel_display_power_resume_early(struct drm_i915_private *i915);
>> void intel_display_power_suspend(struct drm_i915_private *i915);
>> void intel_display_power_resume(struct drm_i915_private *i915);
>> +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
>> + struct intel_atomic_state *state);
>> +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate);
>>
>> const char *
>> intel_display_power_domain_str(struct drm_i915_private *i915,
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 3cdb5bf489f2..7ca0703209a4 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -332,6 +332,7 @@ struct intel_csr {
>> u32 dc_state;
>> u32 allowed_dc_mask;
>> intel_wakeref_t wakeref;
>> + bool prefer_dc3co;
>> };
>>
>> enum i915_cache_level {
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 780df8db2eba..634e43219164 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4584,7 +4584,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
>> return ret;
>> }
>>
>> -static uint_fixed_16_16_t
>> +uint_fixed_16_16_t
>> intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
>> {
>> u32 pixel_rate;
>> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
>> index e3573e1e16e3..454e92c06dff 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.h
>> +++ b/drivers/gpu/drm/i915/intel_pm.h
>> @@ -8,6 +8,7 @@
>>
>> #include <linux/types.h>
>>
>> +#include "i915_drv.h"
>> #include "i915_reg.h"
>>
>> struct drm_device;
>> @@ -76,6 +77,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
>> u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
>>
>> u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
>> +uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate);
>>
>> unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
>> unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
>> --
>> 2.21.0
>>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5
2019-08-19 12:57 ` Gupta, Anshuman
@ 2019-08-19 13:23 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2019-08-19 13:23 UTC (permalink / raw)
To: Gupta, Anshuman, Ville Syrjälä; +Cc: jani.nikula, intel-gfx
On Mon, Aug 19, 2019 at 06:27:48PM +0530, Gupta, Anshuman wrote:
>
>
> On 8/13/2019 9:17 PM, Imre Deak wrote:
> > On Sat, Aug 10, 2019 at 12:02:19AM +0530, Anshuman Gupta wrote:
> > > We need to have a S/W flag based upon which driver can switch to DC3CO.
> > > If it is only edp display connected and it has psr2 capability,
> > > then set a prefer_dc3co flag to true, which will be used to
> > > switch to dc3co as well as to program DC3CO PSR2 transcoder
> > > early exitline event.
> > >
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Animesh Manna <animesh.manna@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 5 +
> > > .../drm/i915/display/intel_display_power.c | 105 ++++++++++++++++++
> > > .../drm/i915/display/intel_display_power.h | 5 +
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > drivers/gpu/drm/i915/intel_pm.c | 2 +-
> > > drivers/gpu/drm/i915/intel_pm.h | 2 +
> > > 6 files changed, 119 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 647f49ca86ff..1ec204c14a10 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -6448,6 +6448,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > > if (WARN_ON(intel_crtc->active))
> > > return;
> > > + /* Enable PSR2 transcoder exit line */
> > > + if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
> > > + tgl_enable_psr2_transcoder_exitline(pipe_config);
> >
> > This is part of PSR2 programming, so should be done somewhere below
> > intel_psr_enable() imo.
> >
> > > intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
> > > @@ -13685,6 +13688,8 @@ static int intel_atomic_check(struct drm_device *dev,
> > > "[modeset]" : "[fastset]");
> > > }
> > > + tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
> >
> > I think this belongs to intel_modeset_checks(), where we could also do
> > all necessary pipe locking (since now I can't see how we would prevent
> > allowing DC3CO when an external output is enabled asynchronously). This
> > would be akin to CDCLK rate change, but I defer on this to Ville.
> Hi Ville,
> Could you please provide your inputs on DC3CO design perspective,
> whether we should have pipe locking in order to maintain consistent state
> for dc3co.
>
> I feel there can be two way to maintain consistent state.
>
> 1. Ensure necessary locking on current crtc before calculating prefer_dc3co
> state, this will block the asynchronous commit.
>
> 2. We can make the prefer_dc3co state to false from enable powerwell
> callback which will trigger by getting a reference count for PG2 power
> domains if any external output is enabled.
>
> (DC3CO will be disallowed from power well enable callback if any external
> output is enabled akin to DC5/DC6, here we want to make prefer_dc3co atomic
> state consistent).
Actually the latest idea based on further discussions was: since all DC
states will be disabled if there is an external output enabled, we
wouldn't need to compute prefer_dc3co. We could just enable/disable
DC3CO (with a new enable_dc3co() API) whenever enabling/disabling PSR2
and during a page-flip/from the page-idle work. That together with the
current state of the dc_off power well determines if any of DC5/6 or
DC3co is enabled atm.
>
> Thanks ,
> Anshuman Gupta.
> >
> > > +
> > > return 0;
> > > fail:
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 167839060154..04a02c88ff93 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -18,6 +18,7 @@
> > > #include "intel_hotplug.h"
> > > #include "intel_sideband.h"
> > > #include "intel_tc.h"
> > > +#include "intel_pm.h"
> > > bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> > > enum i915_power_well_id power_well_id);
> > > @@ -791,6 +792,110 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
> > > dev_priv->csr.dc_state = val & mask;
> > > }
> > > +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate)
> > > +{
> > > + u32 linetime_us, val, exit_scanlines;
> > > + u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
> > > + struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> > > +
> > > + if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
> > > + return;
> >
> > Where's the TRANSCODER-A restriction coming from?
> >
> > > +
> > > + linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
> > > + if (WARN_ON(!linetime_us))
> > > + return;
> > > + /*
> > > + * DC3CO Exit time 200us B.Spec 49196
> > > + * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
> > > + * Exit line event need to program above calculated scan lines before
> > > + * next VBLANK.
> > > + */
> > > + exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
> > > + if (WARN_ON(exit_scanlines > crtc_vdisplay))
> > > + return;
> > > +
> > > + exit_scanlines = crtc_vdisplay - exit_scanlines;
> > > + exit_scanlines <<= EXITLINE_SHIFT;
> > > + val = I915_READ(EXITLINE(cstate->cpu_transcoder));
> > > + val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
> > > + val |= exit_scanlines;
> > > + val |= EXITLINE_ENABLE;
> > > + I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
> > > +}
> > > +
> > > +static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct drm_atomic_state *state = crtc_state->base.state;
> > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > + struct drm_connector *connector, *edp_connector = NULL;
> > > + struct drm_connector_state *connector_state;
> > > + int i;
> > > +
> > > + for_each_new_connector_in_state(state, connector, connector_state, i) {
> > > + if (connector_state->crtc != &crtc->base)
> > > + continue;
> > > +
> > > + if (connector->status == connector_status_connected &&
> > > + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> > > + return false;
> > > + else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
> > > + connector->status == connector_status_connected)
> > > + edp_connector = connector;
> > > + }
> > > +
> > > + if (edp_connector)
> > > + return true;
> > > +
> > > + return false;
> > > +}
> > > +
> > > +/*
> > > + * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
> > > + * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
> > > + * edp display should be connected.
> > > + * TODO: Prefer DC3CO over DC5 only in video playback.
> > > + */
> > > +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
> > > + struct intel_atomic_state *state)
> > > +{
> > > + struct intel_crtc_state *crtc_state, *mode_changed_cstate;
> > > + struct intel_crtc *crtc;
> > > + int i;
> > > + u32 val;
> > > +
> > > + dev_priv->csr.prefer_dc3co = false;
> > > +
> > > + if (!IS_TIGERLAKE(dev_priv))
> > > + return;
> > > +
> > > + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
> > > + return;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> > > + if (crtc->pipe == PIPE_A)
> > > + mode_changed_cstate = crtc_state;
> >
> > Where is the PIPE-A restriction coming from? Couldn't we simply pick the
> > crtc state that has the PSR2 sink?
> >
> > > + if (!crtc_state->has_psr2 && crtc_state->base.active) {
> > > + dev_priv->csr.prefer_dc3co = false;
> > > + return;
> > > + } else if (crtc_state->has_psr2) {
> > > + if (tgl_is_only_edp_connected(crtc_state) &&
> > > + crtc_state->base.active) {
> > > + dev_priv->csr.prefer_dc3co = true;
> > > + continue;
> > > + } else {
> > > + dev_priv->csr.prefer_dc3co = false;
> > > + return;
> > > + }
> > > + }
> > > + }
> > > +
> > > + if (dev_priv->csr.prefer_dc3co) {
> > > + val = I915_READ(EXITLINE(mode_changed_cstate->cpu_transcoder));
> >
> > No HW access during the modeset check phase is the rule. You could just
> > use the old prefer_dc3co value, no?
> >
> > > + if (!(val & EXITLINE_ENABLE))
> > > + mode_changed_cstate->base.mode_changed = true;
> > > + }
> > > +}
> > > +
> > > static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> > > {
> > > gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > index 97f2562fc5d3..46e1bcfa490a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > @@ -12,6 +12,8 @@
> > > struct drm_i915_private;
> > > struct intel_encoder;
> > > +struct intel_crtc_state;
> > > +struct intel_atomic_state;
> > > enum intel_display_power_domain {
> > > POWER_DOMAIN_DISPLAY_CORE,
> > > @@ -246,6 +248,9 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915);
> > > void intel_display_power_resume_early(struct drm_i915_private *i915);
> > > void intel_display_power_suspend(struct drm_i915_private *i915);
> > > void intel_display_power_resume(struct drm_i915_private *i915);
> > > +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
> > > + struct intel_atomic_state *state);
> > > +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate);
> > > const char *
> > > intel_display_power_domain_str(struct drm_i915_private *i915,
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 3cdb5bf489f2..7ca0703209a4 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -332,6 +332,7 @@ struct intel_csr {
> > > u32 dc_state;
> > > u32 allowed_dc_mask;
> > > intel_wakeref_t wakeref;
> > > + bool prefer_dc3co;
> > > };
> > > enum i915_cache_level {
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 780df8db2eba..634e43219164 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4584,7 +4584,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
> > > return ret;
> > > }
> > > -static uint_fixed_16_16_t
> > > +uint_fixed_16_16_t
> > > intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> > > {
> > > u32 pixel_rate;
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > > index e3573e1e16e3..454e92c06dff 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.h
> > > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > > @@ -8,6 +8,7 @@
> > > #include <linux/types.h>
> > > +#include "i915_drv.h"
> > > #include "i915_reg.h"
> > > struct drm_device;
> > > @@ -76,6 +77,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
> > > u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
> > > u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
> > > +uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate);
> > > unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
> > > unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
> > > --
> > > 2.21.0
> > >
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5
2019-08-09 18:32 ` [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 Anshuman Gupta
2019-08-13 15:47 ` Imre Deak
@ 2019-08-14 9:46 ` Imre Deak
1 sibling, 0 replies; 31+ messages in thread
From: Imre Deak @ 2019-08-14 9:46 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx
On Sat, Aug 10, 2019 at 12:02:19AM +0530, Anshuman Gupta wrote:
> We need to have a S/W flag based upon which driver can switch to DC3CO.
> If it is only edp display connected and it has psr2 capability,
> then set a prefer_dc3co flag to true, which will be used to
> switch to dc3co as well as to program DC3CO PSR2 transcoder
> early exitline event.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +
> .../drm/i915/display/intel_display_power.c | 105 ++++++++++++++++++
> .../drm/i915/display/intel_display_power.h | 5 +
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.h | 2 +
> 6 files changed, 119 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 647f49ca86ff..1ec204c14a10 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6448,6 +6448,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> if (WARN_ON(intel_crtc->active))
> return;
> + /* Enable PSR2 transcoder exit line */
> + if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
> + tgl_enable_psr2_transcoder_exitline(pipe_config);
>
> intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
>
> @@ -13685,6 +13688,8 @@ static int intel_atomic_check(struct drm_device *dev,
> "[modeset]" : "[fastset]");
> }
>
> + tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
> +
> return 0;
>
> fail:
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 167839060154..04a02c88ff93 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -18,6 +18,7 @@
> #include "intel_hotplug.h"
> #include "intel_sideband.h"
> #include "intel_tc.h"
> +#include "intel_pm.h"
>
> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> enum i915_power_well_id power_well_id);
> @@ -791,6 +792,110 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
> dev_priv->csr.dc_state = val & mask;
> }
>
> +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate)
> +{
> + u32 linetime_us, val, exit_scanlines;
> + u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
> + struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> +
> + if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
> + return;
> +
> + linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
> + if (WARN_ON(!linetime_us))
> + return;
> + /*
> + * DC3CO Exit time 200us B.Spec 49196
> + * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
> + * Exit line event need to program above calculated scan lines before
> + * next VBLANK.
> + */
> + exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
> + if (WARN_ON(exit_scanlines > crtc_vdisplay))
> + return;
> +
> + exit_scanlines = crtc_vdisplay - exit_scanlines;
> + exit_scanlines <<= EXITLINE_SHIFT;
> + val = I915_READ(EXITLINE(cstate->cpu_transcoder));
> + val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
> + val |= exit_scanlines;
> + val |= EXITLINE_ENABLE;
> + I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
> +}
> +
> +static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_atomic_state *state = crtc_state->base.state;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_connector *connector, *edp_connector = NULL;
> + struct drm_connector_state *connector_state;
> + int i;
> +
> + for_each_new_connector_in_state(state, connector, connector_state, i) {
> + if (connector_state->crtc != &crtc->base)
> + continue;
> +
> + if (connector->status == connector_status_connected &&
> + connector->connector_type != DRM_MODE_CONNECTOR_eDP)
> + return false;
> + else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
> + connector->status == connector_status_connected)
> + edp_connector = connector;
> + }
> +
> + if (edp_connector)
> + return true;
> +
> + return false;
> +}
> +
> +/*
> + * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
> + * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
> + * edp display should be connected.
> + * TODO: Prefer DC3CO over DC5 only in video playback.
> + */
> +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
> + struct intel_atomic_state *state)
One more thing here: this function will set prefer_dc3co if there is
only a PSR2 eDP output connected. However DC states will be disabled
whenever an external display is connected, so I wonder if we could just
depend on that and allow DC3CO (instead of the default DC5/6 state) from
the PSR2 enabling/disabling and page flip/idle thread functions.
> +{
> + struct intel_crtc_state *crtc_state, *mode_changed_cstate;
> + struct intel_crtc *crtc;
> + int i;
> + u32 val;
> +
> + dev_priv->csr.prefer_dc3co = false;
> +
> + if (!IS_TIGERLAKE(dev_priv))
> + return;
> +
> + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
> + return;
> +
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> + if (crtc->pipe == PIPE_A)
> + mode_changed_cstate = crtc_state;
> + if (!crtc_state->has_psr2 && crtc_state->base.active) {
> + dev_priv->csr.prefer_dc3co = false;
> + return;
> + } else if (crtc_state->has_psr2) {
> + if (tgl_is_only_edp_connected(crtc_state) &&
> + crtc_state->base.active) {
> + dev_priv->csr.prefer_dc3co = true;
> + continue;
> + } else {
> + dev_priv->csr.prefer_dc3co = false;
> + return;
> + }
> + }
> + }
> +
> + if (dev_priv->csr.prefer_dc3co) {
> + val = I915_READ(EXITLINE(mode_changed_cstate->cpu_transcoder));
> + if (!(val & EXITLINE_ENABLE))
> + mode_changed_cstate->base.mode_changed = true;
> + }
> +}
> +
> static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> {
> gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 97f2562fc5d3..46e1bcfa490a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -12,6 +12,8 @@
>
> struct drm_i915_private;
> struct intel_encoder;
> +struct intel_crtc_state;
> +struct intel_atomic_state;
>
> enum intel_display_power_domain {
> POWER_DOMAIN_DISPLAY_CORE,
> @@ -246,6 +248,9 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915);
> void intel_display_power_resume_early(struct drm_i915_private *i915);
> void intel_display_power_suspend(struct drm_i915_private *i915);
> void intel_display_power_resume(struct drm_i915_private *i915);
> +void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
> + struct intel_atomic_state *state);
> +void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate);
>
> const char *
> intel_display_power_domain_str(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3cdb5bf489f2..7ca0703209a4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -332,6 +332,7 @@ struct intel_csr {
> u32 dc_state;
> u32 allowed_dc_mask;
> intel_wakeref_t wakeref;
> + bool prefer_dc3co;
> };
>
> enum i915_cache_level {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 780df8db2eba..634e43219164 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4584,7 +4584,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
> return ret;
> }
>
> -static uint_fixed_16_16_t
> +uint_fixed_16_16_t
> intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> {
> u32 pixel_rate;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index e3573e1e16e3..454e92c06dff 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -8,6 +8,7 @@
>
> #include <linux/types.h>
>
> +#include "i915_drv.h"
> #include "i915_reg.h"
>
> struct drm_device;
> @@ -76,6 +77,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
> u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
>
> u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
> +uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate);
>
> unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
> unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
> --
> 2.21.0
>
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 6/9] drm/i915/tgl: Add VIDEO power domain
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (4 preceding siblings ...)
2019-08-09 18:32 ` [PATCH v5 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 Anshuman Gupta
@ 2019-08-09 18:32 ` Anshuman Gupta
2019-08-09 18:32 ` [PATCH v5 7/9] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
` (10 subsequent siblings)
16 siblings, 0 replies; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-09 18:32 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The Power domain name VIDEO is inspired from the fact that
DC3CO should be enabled only during VIDEO playback.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well,
which can disallow DC5/6 and allow DC3CO.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 04a02c88ff93..2667d205fa36 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -122,6 +122,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
return "VGA";
case POWER_DOMAIN_AUDIO:
return "AUDIO";
+ case POWER_DOMAIN_VIDEO:
+ return "VIDEO";
case POWER_DOMAIN_AUX_A:
return "AUX_A";
case POWER_DOMAIN_AUX_B:
@@ -2778,6 +2780,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
TGL_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_VIDEO) | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 46e1bcfa490a..7f4dc8bd2ee4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -66,6 +66,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_OTHER,
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO,
+ POWER_DOMAIN_VIDEO,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7ca0703209a4..0a025c692118 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -333,6 +333,12 @@ struct intel_csr {
u32 allowed_dc_mask;
intel_wakeref_t wakeref;
bool prefer_dc3co;
+ intel_wakeref_t dc5_wakeref;
+ /*
+ * Mutex to protect dc5_wakeref which make maintain proper
+ * power domain reference count of POWER_DOMAIN_VIDEO
+ */
+ struct mutex dc5_mutex;
};
enum i915_cache_level {
--
2.21.0
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v5 7/9] drm/i915/tgl: DC3CO PSR2 helper
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (5 preceding siblings ...)
2019-08-09 18:32 ` [PATCH v5 6/9] drm/i915/tgl: Add VIDEO power domain Anshuman Gupta
@ 2019-08-09 18:32 ` Anshuman Gupta
2019-08-13 16:05 ` Imre Deak
2019-08-09 18:32 ` [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
` (9 subsequent siblings)
16 siblings, 1 reply; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-09 18:32 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add dc3co helper functions to enable/disable psr2 deep sleep.
Disallow DC3CO state before PSR2 exit, it essentially does
that by putting a reference to POWER_DOMAIN_VIDEO before
PSR2 exit.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ad7044ea1efe..42f27df8445d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -533,6 +533,49 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
I915_WRITE(EDP_PSR2_CTL, val);
}
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+ int idle_frames = 0;
+
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL);
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+ int idle_frames;
+
+ /*
+ * Let's use 6 as the minimum to cover all known cases including the
+ * off-by-one issue that HW has in some cases.
+ */
+ idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+ idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL);
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+{
+ intel_wakeref_t wakeref __maybe_unused;
+
+ /* Before PSR2 exit disallow dc3co*/
+ mutex_lock(&dev_priv->csr.dc5_mutex);
+ wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+ if (wakeref)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO,
+ dev_priv->csr.dc5_wakeref);
+ mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
@@ -789,6 +832,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
}
if (dev_priv->psr.psr2_enabled) {
+ tgl_disallow_dc3co_on_psr2_exit(dev_priv);
val = I915_READ(EDP_PSR2_CTL);
WARN_ON(!(val & EDP_PSR2_ENABLE));
I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index dc818826f36d..6fb4c385489c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value);
bool intel_psr_enabled(struct intel_dp *intel_dp);
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PSR_H__ */
--
2.21.0
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^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 7/9] drm/i915/tgl: DC3CO PSR2 helper
2019-08-09 18:32 ` [PATCH v5 7/9] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
@ 2019-08-13 16:05 ` Imre Deak
0 siblings, 0 replies; 31+ messages in thread
From: Imre Deak @ 2019-08-13 16:05 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx
On Sat, Aug 10, 2019 at 12:02:21AM +0530, Anshuman Gupta wrote:
> Add dc3co helper functions to enable/disable psr2 deep sleep.
> Disallow DC3CO state before PSR2 exit, it essentially does
> that by putting a reference to POWER_DOMAIN_VIDEO before
> PSR2 exit.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
> 2 files changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index ad7044ea1efe..42f27df8445d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -533,6 +533,49 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> I915_WRITE(EDP_PSR2_CTL, val);
> }
>
> +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> + int idle_frames = 0;
> +
> + idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
> + val = I915_READ(EDP_PSR2_CTL);
> + val &= ~EDP_PSR2_IDLE_FRAME_MASK;
> + val |= idle_frames;
> + I915_WRITE(EDP_PSR2_CTL, val);
This could be factored out to a helper and reused elsewhere.
> +}
> +
> +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> + int idle_frames;
> +
> + /*
> + * Let's use 6 as the minimum to cover all known cases including the
> + * off-by-one issue that HW has in some cases.
> + */
> + idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> + idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
> + idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
> + val = I915_READ(EDP_PSR2_CTL);
> + val &= ~EDP_PSR2_IDLE_FRAME_MASK;
> + val |= idle_frames;
> + I915_WRITE(EDP_PSR2_CTL, val);
> +}
> +
> +static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
> +{
> + intel_wakeref_t wakeref __maybe_unused;
> +
> + /* Before PSR2 exit disallow dc3co*/
> + mutex_lock(&dev_priv->csr.dc5_mutex);
> + wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref);
> + if (wakeref)
> + intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO,
> + dev_priv->csr.dc5_wakeref);
> + mutex_unlock(&dev_priv->csr.dc5_mutex);
> +}
> +
> static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state)
> {
> @@ -789,6 +832,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
> }
>
> if (dev_priv->psr.psr2_enabled) {
> + tgl_disallow_dc3co_on_psr2_exit(dev_priv);
> val = I915_READ(EDP_PSR2_CTL);
> WARN_ON(!(val & EDP_PSR2_ENABLE));
> I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index dc818826f36d..6fb4c385489c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
> int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
> u32 *out_value);
> bool intel_psr_enabled(struct intel_dp *intel_dp);
> +void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
> +void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
>
> #endif /* __INTEL_PSR_H__ */
> --
> 2.21.0
>
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (6 preceding siblings ...)
2019-08-09 18:32 ` [PATCH v5 7/9] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
@ 2019-08-09 18:32 ` Anshuman Gupta
2019-08-10 6:17 ` kbuild test robot
2019-08-10 6:32 ` kbuild test robot
2019-08-09 18:32 ` [PATCH v5 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
` (8 subsequent siblings)
16 siblings, 2 replies; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-09 18:32 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
DC5 and DC6 saves more power, but can't be entered during video
playback because there are not enough idle frames in a row to meet
most PSR2 panel deep sleep entry requirement typically 4 frames.
It will be worthy to enable DC3CO after completion of each flip
and switch back to DC5 when display is idle, as driver doesn't
differentiate between video playback and a normal flip.
It is safer to allow DC5 after 6 idle frame, as PSR2 requires
minimum 6 idle frame.
v2: calculated s/w state to switch over dc3co when there is an
update. [Imre]
used cancel_delayed_work_sync() in order to avoid any race
with already scheduled delayed work. [Imre]
v3: cancel_delayed_work_sync() may blocked the commit work.
Hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +
.../drm/i915/display/intel_display_power.c | 77 +++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 5 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 87 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1ec204c14a10..906a8e6ec9e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14082,6 +14082,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
}
+
+ tgl_switch_to_dc3co_after_flip(dev_priv);
intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
/*
@@ -16157,6 +16159,7 @@ int intel_modeset_init(struct drm_device *dev)
init_llist_head(&dev_priv->atomic_helper.free_list);
INIT_WORK(&dev_priv->atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
+ INIT_DELAYED_WORK(&dev_priv->csr.idle_work, intel_dc5_idle_thread);
intel_init_quirks(dev_priv);
@@ -17100,6 +17103,7 @@ void intel_modeset_driver_remove(struct drm_device *dev)
flush_workqueue(dev_priv->modeset_wq);
flush_work(&dev_priv->atomic_helper.free_work);
+ flush_delayed_work(&dev_priv->csr.idle_work);
WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2667d205fa36..31d0f389ac17 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,7 @@
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_pm.h"
+#include "intel_psr.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -825,6 +826,46 @@ void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate)
I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
}
+void tgl_switch_to_dc3co_after_flip(struct drm_i915_private *dev_priv)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *cstate;
+ u32 delay;
+
+ if (!dev_priv->csr.prefer_dc3co)
+ return;
+
+ mutex_lock(&dev_priv->psr.lock);
+ if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
+ goto unlock;
+
+ /*
+ * As every flip go through intel_atomic_commit, so tracking a
+ * atomic commit will be a hint for idle frames.
+ * Delayed work for 6 idle frames will be enough to allow dc6
+ * over dc3co for deepest power savings.
+ * At every atomic commit first cancel the delayed work ,
+ * when delayed schedules that means display has been idle
+ * for the 6 idle frame.
+ */
+ cancel_delayed_work(&dev_priv->csr.idle_work);
+ mutex_lock(&dev_priv->csr.dc5_mutex);
+ if (!dev_priv->csr.dc5_wakeref) {
+ dev_priv->csr.dc5_wakeref =
+ intel_display_power_get(dev_priv, POWER_DOMAIN_VIDEO);
+ tgl_psr2_deep_sleep_disable(dev_priv);
+ }
+ mutex_unlock(&dev_priv->csr.dc5_mutex);
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ cstate = to_intel_crtc_state(crtc->base.state);
+
+ delay = DC5_REQ_IDLE_FRAMES * intel_get_frame_time_us(cstate);
+ schedule_delayed_work(&dev_priv->csr.idle_work,
+ usecs_to_jiffies(delay));
+unlock:
+ mutex_unlock(&dev_priv->psr.lock);
+}
+
static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state)
{
struct drm_atomic_state *state = crtc_state->base.state;
@@ -898,6 +939,20 @@ void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
}
}
+void intel_dc5_idle_thread(struct work_struct *work)
+{
+ intel_wakeref_t wakeref __maybe_unused;
+ struct drm_i915_private *dev_priv =
+ container_of(work, typeof(*dev_priv), csr.idle_work.work);
+
+ mutex_lock(&dev_priv->csr.dc5_mutex);
+ wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+ if (wakeref)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO, wakeref);
+ tgl_psr2_deep_sleep_enable(dev_priv);
+ mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
{
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
@@ -1168,6 +1223,27 @@ static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
+u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
+{
+ u32 pixel_rate, crtc_htotal, crtc_vtotal;
+ u32 frametime_us;
+
+ if (!cstate || !cstate->base.active)
+ return 0;
+
+ pixel_rate = cstate->pixel_rate;
+
+ if (WARN_ON(pixel_rate == 0))
+ return 0;
+
+ crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
+ crtc_vtotal = cstate->base.adjusted_mode.crtc_vtotal;
+ frametime_us = DIV_ROUND_UP(crtc_htotal * crtc_vtotal * 1000ULL,
+ pixel_rate);
+
+ return frametime_us;
+}
+
static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -4242,6 +4318,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
mutex_init(&power_domains->lock);
+ mutex_init(&dev_priv->csr.dc5_mutex);
INIT_DELAYED_WORK(&power_domains->async_put_work,
intel_display_power_put_async_work);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 7f4dc8bd2ee4..91e3946e35fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -10,6 +10,8 @@
#include "intel_runtime_pm.h"
#include "i915_reg.h"
+#define DC5_REQ_IDLE_FRAMES 6
+
struct drm_i915_private;
struct intel_encoder;
struct intel_crtc_state;
@@ -249,9 +251,12 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915);
void intel_display_power_resume_early(struct drm_i915_private *i915);
void intel_display_power_suspend(struct drm_i915_private *i915);
void intel_display_power_resume(struct drm_i915_private *i915);
+void intel_dc5_idle_thread(struct work_struct *work);
+u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate);
void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
struct intel_atomic_state *state);
void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate);
+void tgl_switch_to_dc3co_after_flip(struct drm_i915_private *dev_priv);
const char *
intel_display_power_domain_str(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0a025c692118..6c86138c15b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -331,6 +331,7 @@ struct intel_csr {
u32 mmiodata[20];
u32 dc_state;
u32 allowed_dc_mask;
+ struct delayed_work idle_work;
intel_wakeref_t wakeref;
bool prefer_dc3co;
intel_wakeref_t dc5_wakeref;
--
2.21.0
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^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness
2019-08-09 18:32 ` [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
@ 2019-08-10 6:17 ` kbuild test robot
2019-08-10 6:32 ` kbuild test robot
1 sibling, 0 replies; 31+ messages in thread
From: kbuild test robot @ 2019-08-10 6:17 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1078 bytes --]
Hi Anshuman,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc3 next-20190809]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Anshuman-Gupta/DC3CO-Support-for-TGL/20190810-121051
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-10) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
ld: drivers/gpu/drm/i915/display/intel_display_power.o: in function `intel_get_frame_time_us.part.34':
>> intel_display_power.c:(.text+0x29fb): undefined reference to `__udivdi3'
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 28082 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness
2019-08-09 18:32 ` [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-08-10 6:17 ` kbuild test robot
@ 2019-08-10 6:32 ` kbuild test robot
1 sibling, 0 replies; 31+ messages in thread
From: kbuild test robot @ 2019-08-10 6:32 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: jani.nikula, intel-gfx, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1036 bytes --]
Hi Anshuman,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc3 next-20190809]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Anshuman-Gupta/DC3CO-Support-for-TGL/20190810-121051
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-d002-201931 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-10) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
>> ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 38259 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (7 preceding siblings ...)
2019-08-09 18:32 ` [PATCH v5 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
@ 2019-08-09 18:32 ` Anshuman Gupta
2019-08-09 19:13 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev2) Patchwork
` (7 subsequent siblings)
16 siblings, 0 replies; 31+ messages in thread
From: Anshuman Gupta @ 2019-08-09 18:32 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index bddbbd959d1b..b2b310b4f6dc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2431,6 +2431,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
+ /*
+ * TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter.
+ */
+ if (IS_TIGERLAKE(dev_priv))
+ seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
if (INTEL_GEN(dev_priv) >= 12) {
dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3e0783ebbbe6..bd91c6fd030f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7280,6 +7280,8 @@ enum {
#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
+#define DMC_DEBUG3 _MMIO(0x101090)
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29)
--
2.21.0
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^ permalink raw reply related [flat|nested] 31+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev2)
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (8 preceding siblings ...)
2019-08-09 18:32 ` [PATCH v5 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
@ 2019-08-09 19:13 ` Patchwork
2019-08-09 19:17 ` ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
16 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-08-09 19:13 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev2)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
15a54f3bbd2d drm/i915/tgl: Add DC3CO required register and bits
fdc2aa531791 drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
d3de049eb81d drm/i915/tgl: Add power well to enable DC3CO state
-:53: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#53: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:810:
+ udelay(200);
total: 0 errors, 0 warnings, 1 checks, 103 lines checked
33b33a568003 drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
93607c38915a drm/i915/tgl: Add helper function to prefer dc3co over dc5
805147a87236 drm/i915/tgl: Add VIDEO power domain
a3fb8832856a drm/i915/tgl: DC3CO PSR2 helper
d56b369fa284 drm/i915/tgl: switch between dc3co and dc5 based on display idleness
8658e38e3d18 drm/i915/tgl: Add DC3CO counter in i915_dmc_info
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^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL (rev2)
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (9 preceding siblings ...)
2019-08-09 19:13 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev2) Patchwork
@ 2019-08-09 19:17 ` Patchwork
2019-08-09 19:33 ` ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
16 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-08-09 19:17 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev2)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/tgl: Add DC3CO required register and bits
Okay!
Commit: drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Okay!
Commit: drm/i915/tgl: Add power well to enable DC3CO state
+drivers/gpu/drm/i915/display/intel_display_power.c:813:6: warning: symbol 'bxt_enable_dc9' was not declared. Should it be static?
Commit: drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
Okay!
Commit: drm/i915/tgl: Add helper function to prefer dc3co over dc5
Okay!
Commit: drm/i915/tgl: Add VIDEO power domain
Okay!
Commit: drm/i915/tgl: DC3CO PSR2 helper
+drivers/gpu/drm/i915/display/intel_psr.c:557:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_psr.c:558:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_psr.c:558:23: warning: expression using sizeof(void)
Commit: drm/i915/tgl: switch between dc3co and dc5 based on display idleness
Okay!
Commit: drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Okay!
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* ✓ Fi.CI.BAT: success for DC3CO Support for TGL (rev2)
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (10 preceding siblings ...)
2019-08-09 19:17 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-08-09 19:33 ` Patchwork
2019-08-10 16:18 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
16 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-08-09 19:33 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev2)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6668 -> Patchwork_13952
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/
Known issues
------------
Here are the changes found in Patchwork_13952 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([fdo#108511])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#109485])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_exec_reloc@basic-gtt:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-icl-u3/igt@gem_exec_reloc@basic-gtt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-icl-u3/igt@gem_exec_reloc@basic-gtt.html
* igt@gem_mmap@basic-small-bo:
- fi-glk-dsi: [INCOMPLETE][11] ([fdo#103359] / [k.org#198133]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-glk-dsi/igt@gem_mmap@basic-small-bo.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-glk-dsi/igt@gem_mmap@basic-small-bo.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][13] ([fdo#109380]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][15] ([fdo#109485]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][17] ([fdo#102614]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][19] ([fdo#109271]) -> [PASS][20] +23 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (54 -> 47)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6668 -> Patchwork_13952
CI-20190529: 20190529
CI_DRM_6668: 8bb86058e927a93ec2d79fcb48a4ddd752003621 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13952: 8658e38e3d188e08348a42803b3ab8524af830de @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 116 modules
ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
scripts/Makefile.modpost:105: recipe for target 'modules-modpost' failed
make[1]: *** [modules-modpost] Error 1
Makefile:1298: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
8658e38e3d18 drm/i915/tgl: Add DC3CO counter in i915_dmc_info
d56b369fa284 drm/i915/tgl: switch between dc3co and dc5 based on display idleness
a3fb8832856a drm/i915/tgl: DC3CO PSR2 helper
805147a87236 drm/i915/tgl: Add VIDEO power domain
93607c38915a drm/i915/tgl: Add helper function to prefer dc3co over dc5
33b33a568003 drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
d3de049eb81d drm/i915/tgl: Add power well to enable DC3CO state
fdc2aa531791 drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
15a54f3bbd2d drm/i915/tgl: Add DC3CO required register and bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ Fi.CI.IGT: failure for DC3CO Support for TGL (rev2)
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (11 preceding siblings ...)
2019-08-09 19:33 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-08-10 16:18 ` Patchwork
2019-08-11 8:12 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev3) Patchwork
` (3 subsequent siblings)
16 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-08-10 16:18 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev2)
URL : https://patchwork.freedesktop.org/series/64923/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6668_full -> Patchwork_13952_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13952_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13952_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13952_full:
### IGT changes ###
#### Possible regressions ####
* igt@perf_pmu@busy-no-semaphores-rcs0:
- shard-apl: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl7/igt@perf_pmu@busy-no-semaphores-rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-apl1/igt@perf_pmu@busy-no-semaphores-rcs0.html
* igt@runner@aborted:
- shard-apl: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-apl1/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_13952_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([fdo#108566]) +7 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl4/igt@gem_ctx_isolation@rcs0-s3.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +11 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +5 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [PASS][10] -> [DMESG-WARN][11] ([fdo#108686])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-glk5/igt@gem_tiled_swapping@non-threaded.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-glk7/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-iclb: [PASS][12] -> [INCOMPLETE][13] ([fdo#107713])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb1/igt@kms_busy@extended-modeset-hang-newfb-render-c.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb7/igt@kms_busy@extended-modeset-hang-newfb-render-c.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-random:
- shard-skl: [PASS][14] -> [FAIL][15] ([fdo#103232])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][16] -> [INCOMPLETE][17] ([fdo#110741])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][18] -> [FAIL][19] ([fdo#105767])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_flip@modeset-vs-vblank-race-interruptible:
- shard-kbl: [PASS][20] -> [FAIL][21] ([fdo#103060])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl3/igt@kms_flip@modeset-vs-vblank-race-interruptible.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-kbl3/igt@kms_flip@modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-glk: [PASS][22] -> [FAIL][23] ([fdo#100368])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-glk9/igt@kms_flip@plain-flip-ts-check-interruptible.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-glk8/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [PASS][24] -> [FAIL][25] ([fdo#103167]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-apl: [PASS][26] -> [DMESG-WARN][27] ([fdo#108566])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [PASS][28] -> [INCOMPLETE][29] ([fdo#103665])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [PASS][30] -> [SKIP][31] ([fdo#109441])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][32] -> [FAIL][33] ([fdo#99912])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl6/igt@kms_setmode@basic.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-apl2/igt@kms_setmode@basic.html
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-iclb: [PASS][34] -> [FAIL][35] ([fdo#105010])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb5/igt@perf_pmu@rc6-runtime-pm-long.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb5/igt@perf_pmu@rc6-runtime-pm-long.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [SKIP][36] ([fdo#109276]) -> [PASS][37] +5 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb6/igt@gem_ctx_isolation@vcs1-none.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb1/igt@gem_ctx_isolation@vcs1-none.html
* igt@gem_exec_flush@basic-wb-rw-default:
- shard-apl: [INCOMPLETE][38] ([fdo#103927]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl5/igt@gem_exec_flush@basic-wb-rw-default.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-apl2/igt@gem_exec_flush@basic-wb-rw-default.html
* igt@gem_exec_schedule@deep-bsd:
- shard-iclb: [SKIP][40] ([fdo#111325]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb4/igt@gem_exec_schedule@deep-bsd.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb3/igt@gem_exec_schedule@deep-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [DMESG-WARN][42] ([fdo#108566]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-kbl3/igt@gem_softpin@noreloc-s3.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-kbl7/igt@gem_softpin@noreloc-s3.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][44] ([fdo#108566]) -> [PASS][45] +4 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [INCOMPLETE][46] ([fdo#104108]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-skl8/igt@gem_workarounds@suspend-resume-fd.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-skl10/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo:
- shard-iclb: [INCOMPLETE][48] ([fdo#107713]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb7/igt@kms_ccs@pipe-a-ccs-on-another-bo.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb3/igt@kms_ccs@pipe-a-ccs-on-another-bo.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][50] ([fdo#105363]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-panning-vs-hang:
- shard-snb: [INCOMPLETE][52] ([fdo#105411]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-snb1/igt@kms_flip@flip-vs-panning-vs-hang.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-snb4/igt@kms_flip@flip-vs-panning-vs-hang.html
* igt@kms_frontbuffer_tracking@fbcpsr-badstride:
- shard-iclb: [FAIL][54] ([fdo#103167]) -> [PASS][55] +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-badstride.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-badstride.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [INCOMPLETE][56] ([fdo#104108] / [fdo#106978]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-skl9/igt@kms_frontbuffer_tracking@psr-suspend.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-skl8/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][58] ([fdo#109441]) -> [PASS][59] +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-apl: [FAIL][60] ([fdo#105010]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-apl1/igt@perf_pmu@rc6-runtime-pm-long.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-apl3/igt@perf_pmu@rc6-runtime-pm-long.html
- shard-glk: [FAIL][62] ([fdo#105010]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-glk4/igt@perf_pmu@rc6-runtime-pm-long.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-glk2/igt@perf_pmu@rc6-runtime-pm-long.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [FAIL][64] ([fdo#111330]) -> [SKIP][65] ([fdo#109276])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6668/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/shard-iclb7/igt@gem_mocs_settings@mocs-settings-bsd2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6668 -> Patchwork_13952
CI-20190529: 20190529
CI_DRM_6668: 8bb86058e927a93ec2d79fcb48a4ddd752003621 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13952: 8658e38e3d188e08348a42803b3ab8524af830de @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13952/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev3)
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (12 preceding siblings ...)
2019-08-10 16:18 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-08-11 8:12 ` Patchwork
2019-08-11 8:16 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
16 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-08-11 8:12 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev3)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2054d249c446 drm/i915/tgl: Add DC3CO required register and bits
4baba79d9dae drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
0b870884f799 drm/i915/tgl: Add power well to enable DC3CO state
-:53: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#53: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:810:
+ udelay(200);
total: 0 errors, 0 warnings, 1 checks, 101 lines checked
90090f91b4ff drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
009a62ac40eb drm/i915/tgl: Add helper function to prefer dc3co over dc5
ecf16f51f1d5 drm/i915/tgl: Add VIDEO power domain
593a0fd308b8 drm/i915/tgl: DC3CO PSR2 helper
72d3d56414e2 drm/i915/tgl: switch between dc3co and dc5 based on display idleness
b2921c6c42ee drm/i915/tgl: Add DC3CO counter in i915_dmc_info
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL (rev3)
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (13 preceding siblings ...)
2019-08-11 8:12 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev3) Patchwork
@ 2019-08-11 8:16 ` Patchwork
2019-08-11 8:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-11 15:08 ` ✓ Fi.CI.IGT: " Patchwork
16 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-08-11 8:16 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev3)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/tgl: Add DC3CO required register and bits
Okay!
Commit: drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Okay!
Commit: drm/i915/tgl: Add power well to enable DC3CO state
Okay!
Commit: drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
Okay!
Commit: drm/i915/tgl: Add helper function to prefer dc3co over dc5
Okay!
Commit: drm/i915/tgl: Add VIDEO power domain
Okay!
Commit: drm/i915/tgl: DC3CO PSR2 helper
+drivers/gpu/drm/i915/display/intel_psr.c:557:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_psr.c:558:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_psr.c:558:23: warning: expression using sizeof(void)
Commit: drm/i915/tgl: switch between dc3co and dc5 based on display idleness
Okay!
Commit: drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* ✓ Fi.CI.BAT: success for DC3CO Support for TGL (rev3)
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (14 preceding siblings ...)
2019-08-11 8:16 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-08-11 8:37 ` Patchwork
2019-08-11 15:08 ` ✓ Fi.CI.IGT: " Patchwork
16 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-08-11 8:37 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev3)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6677 -> Patchwork_13965
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/
Known issues
------------
Here are the changes found in Patchwork_13965 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-ilk-650: [PASS][1] -> [DMESG-WARN][2] ([fdo#106387])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-ilk-650/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-ilk-650/igt@debugfs_test@read_all_entries.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [PASS][3] -> [FAIL][4] ([fdo#107707])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][5] -> [FAIL][6] ([fdo#108511])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][7] -> [DMESG-FAIL][8] ([fdo#111108])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_requests:
- fi-byt-j1900: [PASS][9] -> [INCOMPLETE][10] ([fdo#102657])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-byt-j1900/igt@i915_selftest@live_requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-byt-j1900/igt@i915_selftest@live_requests.html
* igt@kms_addfb_basic@bad-pitch-256:
- fi-icl-u3: [PASS][11] -> [DMESG-WARN][12] ([fdo#107724])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-icl-u3/igt@kms_addfb_basic@bad-pitch-256.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-icl-u3/igt@kms_addfb_basic@bad-pitch-256.html
* igt@kms_busy@basic-flip-c:
- fi-skl-6770hq: [PASS][13] -> [SKIP][14] ([fdo#109271] / [fdo#109278]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-skl-6770hq/igt@kms_busy@basic-flip-c.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-skl-6770hq/igt@kms_busy@basic-flip-c.html
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: [PASS][15] -> [SKIP][16] ([fdo#109271]) +23 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7500u: [PASS][17] -> [SKIP][18] ([fdo#109271]) +23 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-kbl-7500u/igt@prime_vgem@basic-fence-flip.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-kbl-7500u/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-read:
- fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-icl-u3/igt@gem_mmap_gtt@basic-read.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-icl-u3/igt@gem_mmap_gtt@basic-read.html
* igt@gem_mmap_gtt@basic-write-no-prefault:
- {fi-icl-dsi}: [DMESG-WARN][21] ([fdo#106107]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-icl-dsi/igt@gem_mmap_gtt@basic-write-no-prefault.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-icl-dsi/igt@gem_mmap_gtt@basic-write-no-prefault.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [FAIL][23] ([fdo#107707]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
* {igt@i915_selftest@live_gt_timelines}:
- fi-bsw-kefka: [DMESG-WARN][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-bsw-kefka/igt@i915_selftest@live_gt_timelines.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-bsw-kefka/igt@i915_selftest@live_gt_timelines.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [SKIP][27] ([fdo#109271] / [fdo#109278]) -> [PASS][28] +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
* igt@kms_chamelium@dp-edid-read:
- {fi-icl-u4}: [FAIL][29] ([fdo#111045] / [fdo#111046 ]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-icl-u4/igt@kms_chamelium@dp-edid-read.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-icl-u4/igt@kms_chamelium@dp-edid-read.html
#### Warnings ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [FAIL][31] ([fdo#109483]) -> [DMESG-WARN][32] ([fdo#102505] / [fdo#110390])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
Participating hosts (55 -> 46)
------------------------------
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-whl-u fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6677 -> Patchwork_13965
CI-20190529: 20190529
CI_DRM_6677: c590f3dd9c365a31c77a82bd5ed79434a6605254 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13965: b2921c6c42ee7325dfcc7c87a4e690f0b82fda13 @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 116 modules
ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
scripts/Makefile.modpost:105: recipe for target 'modules-modpost' failed
make[1]: *** [modules-modpost] Error 1
Makefile:1298: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
b2921c6c42ee drm/i915/tgl: Add DC3CO counter in i915_dmc_info
72d3d56414e2 drm/i915/tgl: switch between dc3co and dc5 based on display idleness
593a0fd308b8 drm/i915/tgl: DC3CO PSR2 helper
ecf16f51f1d5 drm/i915/tgl: Add VIDEO power domain
009a62ac40eb drm/i915/tgl: Add helper function to prefer dc3co over dc5
90090f91b4ff drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
0b870884f799 drm/i915/tgl: Add power well to enable DC3CO state
4baba79d9dae drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
2054d249c446 drm/i915/tgl: Add DC3CO required register and bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* ✓ Fi.CI.IGT: success for DC3CO Support for TGL (rev3)
2019-08-09 18:32 [PATCH v5 0/9] DC3CO Support for TGL Anshuman Gupta
` (15 preceding siblings ...)
2019-08-11 8:37 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-08-11 15:08 ` Patchwork
16 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-08-11 15:08 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev3)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6677_full -> Patchwork_13965_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13965_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_bad_destroy@invalid-default-ctx:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb7/igt@gem_ctx_bad_destroy@invalid-default-ctx.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb4/igt@gem_ctx_bad_destroy@invalid-default-ctx.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb1/igt@gem_exec_balancer@smoke.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb7/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +21 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-skl1/igt@gem_softpin@noreloc-s3.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-skl3/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_rpm@i2c:
- shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#104097])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-hsw2/igt@i915_pm_rpm@i2c.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-hsw7/igt@i915_pm_rpm@i2c.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-kbl7/igt@i915_suspend@sysfs-reader.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-kbl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-random:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#103232])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][25] -> [DMESG-WARN][26] ([fdo#108566]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl: [PASS][27] -> [INCOMPLETE][28] ([fdo#103665])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-kbl7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-kbl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf@polling:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#110728])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-skl2/igt@perf@polling.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-skl9/igt@perf@polling.html
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-glk: [PASS][31] -> [FAIL][32] ([fdo#105010])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-glk9/igt@perf_pmu@rc6-runtime-pm-long.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-glk2/igt@perf_pmu@rc6-runtime-pm-long.html
#### Possible fixes ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +5 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-apl3/igt@gem_ctx_isolation@bcs0-s3.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-apl7/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][35] ([fdo#110841]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_balancer@invalid-balancer:
- shard-apl: [INCOMPLETE][37] ([fdo#103927]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-apl8/igt@gem_exec_balancer@invalid-balancer.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-apl1/igt@gem_exec_balancer@invalid-balancer.html
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- shard-skl: [DMESG-WARN][39] ([fdo#106107]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-skl1/igt@gem_exec_reloc@basic-gtt-cpu-active.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-skl5/igt@gem_exec_reloc@basic-gtt-cpu-active.html
* igt@gem_exec_schedule@independent-blt:
- shard-hsw: [FAIL][41] -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-hsw7/igt@gem_exec_schedule@independent-blt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-hsw2/igt@gem_exec_schedule@independent-blt.html
* igt@gem_exec_schedule@preempt-bsd:
- shard-iclb: [SKIP][43] ([fdo#111325]) -> [PASS][44] +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb8/igt@gem_exec_schedule@preempt-bsd.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-hsw: [FAIL][45] ([fdo#103355]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-hsw: [FAIL][47] ([fdo#102887]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-hsw1/igt@kms_flip@2x-flip-vs-expired-vblank.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-hsw6/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][49] ([fdo#103167]) -> [PASS][50] +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [INCOMPLETE][51] ([fdo#103665]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][53] ([fdo#103166]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][57] ([fdo#99912]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-apl1/igt@kms_setmode@basic.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-apl3/igt@kms_setmode@basic.html
- shard-kbl: [FAIL][59] ([fdo#99912]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-kbl7/igt@kms_setmode@basic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-kbl6/igt@kms_setmode@basic.html
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-apl: [FAIL][61] ([fdo#105010]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-apl5/igt@perf_pmu@rc6-runtime-pm-long.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-apl2/igt@perf_pmu@rc6-runtime-pm-long.html
- shard-hsw: [FAIL][63] ([fdo#105010]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-hsw4/igt@perf_pmu@rc6-runtime-pm-long.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-hsw2/igt@perf_pmu@rc6-runtime-pm-long.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][65] ([fdo#109276]) -> [PASS][66] +18 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][67] ([fdo#111329]) -> [SKIP][68] ([fdo#109276])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][69] ([fdo#111330]) -> [SKIP][70] ([fdo#109276]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6677/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/shard-iclb6/igt@gem_mocs_settings@mocs-reset-bsd2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6677 -> Patchwork_13965
CI-20190529: 20190529
CI_DRM_6677: c590f3dd9c365a31c77a82bd5ed79434a6605254 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5127: f43f5fa12ac1b93febfe3eeb9e9985f5f3e2eff0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13965: b2921c6c42ee7325dfcc7c87a4e690f0b82fda13 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13965/
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