* [PATCHv5 0/5]Odroid n2 using eMMC would fail to boot up
@ 2020-02-03 15:13 ` Anand Moon
0 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
u-boot-amlogic, u-boot
Here are some small changes to fix booting of Odroid N2 using eMMC.
Fixed the clk tunnig during mmc initialization.
Added two new patches to fix warning
Build and tested on top of below patches
[0] https://patchwork.ozlabs.org/patch/1213648/
[1] https://patchwork.ozlabs.org/patch/1213650/
Tested on below eMMC module on Odroid N2 and C2
new orange - eMMC AJNB4R 14.6 GiB MMC 5.1
old back - eMMC CGND3R 58.2 GiB MMC 5.0
Prevoius changes:
Fixed the clk tuning as per mainline kernel
[3]v1 https://patchwork.ozlabs.org/cover/1201206/
[4]v2 https://patchwork.ozlabs.org/cover/1215217/
[5]v3 https://www.mail-archive.com/u-boot@lists.denx.de/msg351859.html
[6]v4 https://patchwork.ozlabs.org/cover/1227205/
-Anand
Anand Moon (5):
mmc: meson-gx: Fix clk phase tuning for MMC
mmc: meson-gx: Use proper compatible string as per the dts
arm: dts: gx: Move common nodes to the -u-boot.dtsi
arm: dts: g12: Move common nodes to the -u-boot.dtsi
arm: dts: s400: Move common nodes to the -u-boot.dtsi
arch/arm/dts/meson-axg-s400-u-boot.dtsi | 16 +++++
arch/arm/dts/meson-axg-s400.dts | 9 ---
arch/arm/dts/meson-g12-common-u-boot.dtsi | 12 ++++
arch/arm/dts/meson-g12a-sei510.dts | 9 ---
arch/arm/dts/meson-g12a-u200.dts | 9 ---
arch/arm/dts/meson-g12b-odroid-n2.dts | 9 ---
arch/arm/dts/meson-gx-u-boot.dtsi | 15 +++++
arch/arm/dts/meson-gxbb-nanopi-k2.dts | 9 ---
arch/arm/dts/meson-gxbb-odroidc2.dts | 9 ---
arch/arm/dts/meson-gxbb-p20x.dtsi | 9 ---
arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ---
arch/arm/dts/meson-gxl-s905x-khadas-vim.dts | 5 --
arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 9 ---
arch/arm/dts/meson-gxl-s905x-p212.dtsi | 10 ---
arch/arm/dts/meson-gxm-khadas-vim2.dts | 10 ---
arch/arm/dts/meson-khadas-vim3.dtsi | 9 ---
arch/arm/dts/meson-sm1-sei610.dts | 9 ---
arch/arm/include/asm/arch-meson/sd_emmc.h | 35 +++++++---
drivers/mmc/meson_gx_mmc.c | 66 ++++++++++++++++---
19 files changed, 126 insertions(+), 143 deletions(-)
--
2.25.0
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
2020-02-03 15:13 ` Anand Moon
@ 2020-02-03 15:13 ` Anand Moon
-1 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: u-boot
As per mainline line kernel fix the clk tuning phase for mmc,
set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
As per S905, S905X, AGX and S922X datasheet set the default
values for clk tuning.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
2 files changed, 50 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index e3a72c8b66..b7a99947b3 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -7,6 +7,7 @@
#define __SD_EMMC_H__
#include <mmc.h>
+#include <linux/bitops.h>
#define SDIO_PORT_A 0
#define SDIO_PORT_B 1
@@ -19,15 +20,24 @@
#define CLK_MAX_DIV 63
#define CLK_SRC_24M (0 << 6)
#define CLK_SRC_DIV2 (1 << 6)
-#define CLK_CO_PHASE_000 (0 << 8)
-#define CLK_CO_PHASE_090 (1 << 8)
-#define CLK_CO_PHASE_180 (2 << 8)
-#define CLK_CO_PHASE_270 (3 << 8)
-#define CLK_TX_PHASE_000 (0 << 10)
-#define CLK_TX_PHASE_090 (1 << 10)
-#define CLK_TX_PHASE_180 (2 << 10)
-#define CLK_TX_PHASE_270 (3 << 10)
-#define CLK_ALWAYS_ON BIT(24)
+
+#define CRYSTAL_24MHZ 0
+#define CLK_PHASE_0 0
+#define CLK_PHASE_180 2
+
+#define CLK_DIV_MASK GENMASK(5, 0)
+#define CLK_SRC_MASK GENMASK(7, 6)
+#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
+#define CLK_TX_PHASE_MASK GENMASK(11, 10)
+#define CLK_RX_PHASE_MASK GENMASK(13, 12)
+
+#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define CLK_V2_ALWAYS_ON BIT(24)
+
+#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define CLK_V3_ALWAYS_ON BIT(28)
#define MESON_SD_EMMC_CFG 0x44
#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 86c1a7164a..03fb70e717 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -16,6 +16,10 @@
#include <asm/arch/sd_emmc.h>
#include <linux/log2.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
static inline void *get_regbase(const struct mmc *mmc)
{
struct meson_mmc_platdata *pdata = mmc->priv;
@@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
}
clk_div = DIV_ROUND_UP(clk, mmc->clock);
- /* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
-
- /* 180 phase tx clock */
- meson_mmc_clk |= CLK_TX_PHASE_000;
+ /* Clock divider */
+ meson_mmc_clk |= CLK_DIV_MASK;
+ /* Clock source : Crystal 24MHz */
+ meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
+ /* Core clock phase 2:180 */
+ meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+ /* TX clock phase 2:180 */
+ meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
+ /* RX clock phase 0:180 */
+ meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
+
+#ifdef CONFIG_MESON_GX
+ /* TX clock delay line */
+ meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
+ /* RX clock delay line */
+ meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
+ /* clk always on */
+ meson_mmc_clk |= CLK_V2_ALWAYS_ON;
+#endif
+#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
+ /* TX clock delay line */
+ meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
+ /* RX clock delay line */
+ meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
+ /* clk always on */
+ meson_mmc_clk |= CLK_V3_ALWAYS_ON;
+#endif
/* clock settings */
meson_mmc_clk |= clk_src;
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-03 15:13 ` Anand Moon
0 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
u-boot-amlogic, u-boot
As per mainline line kernel fix the clk tuning phase for mmc,
set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
As per S905, S905X, AGX and S922X datasheet set the default
values for clk tuning.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
2 files changed, 50 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index e3a72c8b66..b7a99947b3 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -7,6 +7,7 @@
#define __SD_EMMC_H__
#include <mmc.h>
+#include <linux/bitops.h>
#define SDIO_PORT_A 0
#define SDIO_PORT_B 1
@@ -19,15 +20,24 @@
#define CLK_MAX_DIV 63
#define CLK_SRC_24M (0 << 6)
#define CLK_SRC_DIV2 (1 << 6)
-#define CLK_CO_PHASE_000 (0 << 8)
-#define CLK_CO_PHASE_090 (1 << 8)
-#define CLK_CO_PHASE_180 (2 << 8)
-#define CLK_CO_PHASE_270 (3 << 8)
-#define CLK_TX_PHASE_000 (0 << 10)
-#define CLK_TX_PHASE_090 (1 << 10)
-#define CLK_TX_PHASE_180 (2 << 10)
-#define CLK_TX_PHASE_270 (3 << 10)
-#define CLK_ALWAYS_ON BIT(24)
+
+#define CRYSTAL_24MHZ 0
+#define CLK_PHASE_0 0
+#define CLK_PHASE_180 2
+
+#define CLK_DIV_MASK GENMASK(5, 0)
+#define CLK_SRC_MASK GENMASK(7, 6)
+#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
+#define CLK_TX_PHASE_MASK GENMASK(11, 10)
+#define CLK_RX_PHASE_MASK GENMASK(13, 12)
+
+#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define CLK_V2_ALWAYS_ON BIT(24)
+
+#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define CLK_V3_ALWAYS_ON BIT(28)
#define MESON_SD_EMMC_CFG 0x44
#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 86c1a7164a..03fb70e717 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -16,6 +16,10 @@
#include <asm/arch/sd_emmc.h>
#include <linux/log2.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
static inline void *get_regbase(const struct mmc *mmc)
{
struct meson_mmc_platdata *pdata = mmc->priv;
@@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
}
clk_div = DIV_ROUND_UP(clk, mmc->clock);
- /* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
-
- /* 180 phase tx clock */
- meson_mmc_clk |= CLK_TX_PHASE_000;
+ /* Clock divider */
+ meson_mmc_clk |= CLK_DIV_MASK;
+ /* Clock source : Crystal 24MHz */
+ meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
+ /* Core clock phase 2:180 */
+ meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+ /* TX clock phase 2:180 */
+ meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
+ /* RX clock phase 0:180 */
+ meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
+
+#ifdef CONFIG_MESON_GX
+ /* TX clock delay line */
+ meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
+ /* RX clock delay line */
+ meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
+ /* clk always on */
+ meson_mmc_clk |= CLK_V2_ALWAYS_ON;
+#endif
+#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
+ /* TX clock delay line */
+ meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
+ /* RX clock delay line */
+ meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
+ /* clk always on */
+ meson_mmc_clk |= CLK_V3_ALWAYS_ON;
+#endif
/* clock settings */
meson_mmc_clk |= clk_src;
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
2020-02-03 15:13 ` Anand Moon
@ 2020-02-03 15:41 ` Jerome Brunet
-1 siblings, 0 replies; 20+ messages in thread
From: Jerome Brunet @ 2020-02-03 15:41 UTC (permalink / raw)
To: u-boot
On Mon 03 Feb 2020 at 16:13, Anand Moon <linux.amoon@gmail.com> wrote:
> As per mainline line kernel fix the clk tuning phase for mmc,
> set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
> As per S905, S905X, AGX and S922X datasheet set the default
> values for clk tuning.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
> drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
> 2 files changed, 50 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> index e3a72c8b66..b7a99947b3 100644
> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> @@ -7,6 +7,7 @@
> #define __SD_EMMC_H__
>
> #include <mmc.h>
> +#include <linux/bitops.h>
>
> #define SDIO_PORT_A 0
> #define SDIO_PORT_B 1
> @@ -19,15 +20,24 @@
> #define CLK_MAX_DIV 63
> #define CLK_SRC_24M (0 << 6)
> #define CLK_SRC_DIV2 (1 << 6)
> -#define CLK_CO_PHASE_000 (0 << 8)
> -#define CLK_CO_PHASE_090 (1 << 8)
> -#define CLK_CO_PHASE_180 (2 << 8)
> -#define CLK_CO_PHASE_270 (3 << 8)
> -#define CLK_TX_PHASE_000 (0 << 10)
> -#define CLK_TX_PHASE_090 (1 << 10)
> -#define CLK_TX_PHASE_180 (2 << 10)
> -#define CLK_TX_PHASE_270 (3 << 10)
> -#define CLK_ALWAYS_ON BIT(24)
> +
> +#define CRYSTAL_24MHZ 0
> +#define CLK_PHASE_0 0
> +#define CLK_PHASE_180 2
> +
> +#define CLK_DIV_MASK GENMASK(5, 0)
> +#define CLK_SRC_MASK GENMASK(7, 6)
> +#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
> +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> +
> +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
> +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
> +#define CLK_V2_ALWAYS_ON BIT(24)
> +
> +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
> +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
> +#define CLK_V3_ALWAYS_ON BIT(28)
>
> #define MESON_SD_EMMC_CFG 0x44
> #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index 86c1a7164a..03fb70e717 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -16,6 +16,10 @@
> #include <asm/arch/sd_emmc.h>
> #include <linux/log2.h>
>
> +#include <linux/bitops.h>
> +#include <linux/compat.h>
> +#include <linux/bitfield.h>
> +
> static inline void *get_regbase(const struct mmc *mmc)
> {
> struct meson_mmc_platdata *pdata = mmc->priv;
> @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> }
> clk_div = DIV_ROUND_UP(clk, mmc->clock);
>
> - /* 180 phase core clock */
> - meson_mmc_clk |= CLK_CO_PHASE_180;
> -
> - /* 180 phase tx clock */
> - meson_mmc_clk |= CLK_TX_PHASE_000;
> + /* Clock divider */
> + meson_mmc_clk |= CLK_DIV_MASK;
> + /* Clock source : Crystal 24MHz */
> + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> + /* Core clock phase 2:180 */
> + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> + /* TX clock phase 2:180 */
> + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
I think I mentionned already but this is not aligned with the setting
used by the linux driver. If you have problems with these, please report
it to the linux mailing list
> + /* RX clock phase 0:180 */
> + meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> +
> +#ifdef CONFIG_MESON_GX
> + /* TX clock delay line */
> + meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
> + /* RX clock delay line */
> + meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
Why do you need to this ?
> + /* clk always on */
> + meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> +#endif
> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> + /* TX clock delay line */
> + meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
> + /* RX clock delay line */
> + meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
> + /* clk always on */
> + meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> +#endif
>
> /* clock settings */
> meson_mmc_clk |= clk_src;
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-03 15:41 ` Jerome Brunet
0 siblings, 0 replies; 20+ messages in thread
From: Jerome Brunet @ 2020-02-03 15:41 UTC (permalink / raw)
To: Anand Moon, Neil Armstrong, Peng Fan, Jaehoon Chung,
u-boot-amlogic, u-boot
On Mon 03 Feb 2020 at 16:13, Anand Moon <linux.amoon@gmail.com> wrote:
> As per mainline line kernel fix the clk tuning phase for mmc,
> set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
> As per S905, S905X, AGX and S922X datasheet set the default
> values for clk tuning.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
> drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
> 2 files changed, 50 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> index e3a72c8b66..b7a99947b3 100644
> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> @@ -7,6 +7,7 @@
> #define __SD_EMMC_H__
>
> #include <mmc.h>
> +#include <linux/bitops.h>
>
> #define SDIO_PORT_A 0
> #define SDIO_PORT_B 1
> @@ -19,15 +20,24 @@
> #define CLK_MAX_DIV 63
> #define CLK_SRC_24M (0 << 6)
> #define CLK_SRC_DIV2 (1 << 6)
> -#define CLK_CO_PHASE_000 (0 << 8)
> -#define CLK_CO_PHASE_090 (1 << 8)
> -#define CLK_CO_PHASE_180 (2 << 8)
> -#define CLK_CO_PHASE_270 (3 << 8)
> -#define CLK_TX_PHASE_000 (0 << 10)
> -#define CLK_TX_PHASE_090 (1 << 10)
> -#define CLK_TX_PHASE_180 (2 << 10)
> -#define CLK_TX_PHASE_270 (3 << 10)
> -#define CLK_ALWAYS_ON BIT(24)
> +
> +#define CRYSTAL_24MHZ 0
> +#define CLK_PHASE_0 0
> +#define CLK_PHASE_180 2
> +
> +#define CLK_DIV_MASK GENMASK(5, 0)
> +#define CLK_SRC_MASK GENMASK(7, 6)
> +#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
> +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> +
> +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
> +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
> +#define CLK_V2_ALWAYS_ON BIT(24)
> +
> +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
> +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
> +#define CLK_V3_ALWAYS_ON BIT(28)
>
> #define MESON_SD_EMMC_CFG 0x44
> #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index 86c1a7164a..03fb70e717 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -16,6 +16,10 @@
> #include <asm/arch/sd_emmc.h>
> #include <linux/log2.h>
>
> +#include <linux/bitops.h>
> +#include <linux/compat.h>
> +#include <linux/bitfield.h>
> +
> static inline void *get_regbase(const struct mmc *mmc)
> {
> struct meson_mmc_platdata *pdata = mmc->priv;
> @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> }
> clk_div = DIV_ROUND_UP(clk, mmc->clock);
>
> - /* 180 phase core clock */
> - meson_mmc_clk |= CLK_CO_PHASE_180;
> -
> - /* 180 phase tx clock */
> - meson_mmc_clk |= CLK_TX_PHASE_000;
> + /* Clock divider */
> + meson_mmc_clk |= CLK_DIV_MASK;
> + /* Clock source : Crystal 24MHz */
> + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> + /* Core clock phase 2:180 */
> + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> + /* TX clock phase 2:180 */
> + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
I think I mentionned already but this is not aligned with the setting
used by the linux driver. If you have problems with these, please report
it to the linux mailing list
> + /* RX clock phase 0:180 */
> + meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> +
> +#ifdef CONFIG_MESON_GX
> + /* TX clock delay line */
> + meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
> + /* RX clock delay line */
> + meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
Why do you need to this ?
> + /* clk always on */
> + meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> +#endif
> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> + /* TX clock delay line */
> + meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
> + /* RX clock delay line */
> + meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
> + /* clk always on */
> + meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> +#endif
>
> /* clock settings */
> meson_mmc_clk |= clk_src;
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
2020-02-03 15:41 ` Jerome Brunet
@ 2020-02-03 16:38 ` Anand Moon
-1 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 16:38 UTC (permalink / raw)
To: u-boot
Hi Jerome,
Thanks for your review,
On Mon, 3 Feb 2020 at 21:11, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Mon 03 Feb 2020 at 16:13, Anand Moon <linux.amoon@gmail.com> wrote:
>
> > As per mainline line kernel fix the clk tuning phase for mmc,
> > set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
> > As per S905, S905X, AGX and S922X datasheet set the default
> > values for clk tuning.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
> > drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
> > 2 files changed, 50 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > index e3a72c8b66..b7a99947b3 100644
> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > @@ -7,6 +7,7 @@
> > #define __SD_EMMC_H__
> >
> > #include <mmc.h>
> > +#include <linux/bitops.h>
> >
> > #define SDIO_PORT_A 0
> > #define SDIO_PORT_B 1
> > @@ -19,15 +20,24 @@
> > #define CLK_MAX_DIV 63
> > #define CLK_SRC_24M (0 << 6)
> > #define CLK_SRC_DIV2 (1 << 6)
> > -#define CLK_CO_PHASE_000 (0 << 8)
> > -#define CLK_CO_PHASE_090 (1 << 8)
> > -#define CLK_CO_PHASE_180 (2 << 8)
> > -#define CLK_CO_PHASE_270 (3 << 8)
> > -#define CLK_TX_PHASE_000 (0 << 10)
> > -#define CLK_TX_PHASE_090 (1 << 10)
> > -#define CLK_TX_PHASE_180 (2 << 10)
> > -#define CLK_TX_PHASE_270 (3 << 10)
> > -#define CLK_ALWAYS_ON BIT(24)
> > +
> > +#define CRYSTAL_24MHZ 0
> > +#define CLK_PHASE_0 0
> > +#define CLK_PHASE_180 2
> > +
> > +#define CLK_DIV_MASK GENMASK(5, 0)
> > +#define CLK_SRC_MASK GENMASK(7, 6)
> > +#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> > +
> > +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
> > +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
> > +#define CLK_V2_ALWAYS_ON BIT(24)
> > +
> > +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
> > +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
> > +#define CLK_V3_ALWAYS_ON BIT(28)
> >
> > #define MESON_SD_EMMC_CFG 0x44
> > #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> > index 86c1a7164a..03fb70e717 100644
> > --- a/drivers/mmc/meson_gx_mmc.c
> > +++ b/drivers/mmc/meson_gx_mmc.c
> > @@ -16,6 +16,10 @@
> > #include <asm/arch/sd_emmc.h>
> > #include <linux/log2.h>
> >
> > +#include <linux/bitops.h>
> > +#include <linux/compat.h>
> > +#include <linux/bitfield.h>
> > +
> > static inline void *get_regbase(const struct mmc *mmc)
> > {
> > struct meson_mmc_platdata *pdata = mmc->priv;
> > @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> > }
> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >
> > - /* 180 phase core clock */
> > - meson_mmc_clk |= CLK_CO_PHASE_180;
> > -
> > - /* 180 phase tx clock */
> > - meson_mmc_clk |= CLK_TX_PHASE_000;
> > + /* Clock divider */
> > + meson_mmc_clk |= CLK_DIV_MASK;
> > + /* Clock source : Crystal 24MHz */
> > + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> > + /* Core clock phase 2:180 */
> > + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> > + /* TX clock phase 2:180 */
> > + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
>
> I think I mentionned already but this is not aligned with the setting
> used by the linux driver. If you have problems with these, please report
> it to the linux mailing list
Yes I will try to send this changes to linux driver since these are
the recommend
default values as per the datasheets, see below.
Cfg_tx_phase: TX clock phase 0: 0 phase, 1: 90 phase, 2: 180 phase, 3:
270 phase. Recommended value: 2
>
> > + /* RX clock phase 0:180 */
> > + meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> > +
> > +#ifdef CONFIG_MESON_GX
> > + /* TX clock delay line */
> > + meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
> > + /* RX clock delay line */
> > + meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
>
> Why do you need to this ?
As these are part of the linux driver, I added these,
I will check if this changes are needed in u-boot.
>
> > + /* clk always on */
> > + meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> > +#endif
> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> > + /* TX clock delay line */
> > + meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
> > + /* RX clock delay line */
> > + meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
> > + /* clk always on */
> > + meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> > +#endif
> >
> > /* clock settings */
> > meson_mmc_clk |= clk_src;
>
-Anand
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-03 16:38 ` Anand Moon
0 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 16:38 UTC (permalink / raw)
To: Jerome Brunet
Cc: Neil Armstrong, Peng Fan, Jaehoon Chung, u-boot-amlogic,
U-Boot Mailing List
Hi Jerome,
Thanks for your review,
On Mon, 3 Feb 2020 at 21:11, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Mon 03 Feb 2020 at 16:13, Anand Moon <linux.amoon@gmail.com> wrote:
>
> > As per mainline line kernel fix the clk tuning phase for mmc,
> > set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
> > As per S905, S905X, AGX and S922X datasheet set the default
> > values for clk tuning.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> > arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
> > drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
> > 2 files changed, 50 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > index e3a72c8b66..b7a99947b3 100644
> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> > @@ -7,6 +7,7 @@
> > #define __SD_EMMC_H__
> >
> > #include <mmc.h>
> > +#include <linux/bitops.h>
> >
> > #define SDIO_PORT_A 0
> > #define SDIO_PORT_B 1
> > @@ -19,15 +20,24 @@
> > #define CLK_MAX_DIV 63
> > #define CLK_SRC_24M (0 << 6)
> > #define CLK_SRC_DIV2 (1 << 6)
> > -#define CLK_CO_PHASE_000 (0 << 8)
> > -#define CLK_CO_PHASE_090 (1 << 8)
> > -#define CLK_CO_PHASE_180 (2 << 8)
> > -#define CLK_CO_PHASE_270 (3 << 8)
> > -#define CLK_TX_PHASE_000 (0 << 10)
> > -#define CLK_TX_PHASE_090 (1 << 10)
> > -#define CLK_TX_PHASE_180 (2 << 10)
> > -#define CLK_TX_PHASE_270 (3 << 10)
> > -#define CLK_ALWAYS_ON BIT(24)
> > +
> > +#define CRYSTAL_24MHZ 0
> > +#define CLK_PHASE_0 0
> > +#define CLK_PHASE_180 2
> > +
> > +#define CLK_DIV_MASK GENMASK(5, 0)
> > +#define CLK_SRC_MASK GENMASK(7, 6)
> > +#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> > +
> > +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
> > +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
> > +#define CLK_V2_ALWAYS_ON BIT(24)
> > +
> > +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
> > +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
> > +#define CLK_V3_ALWAYS_ON BIT(28)
> >
> > #define MESON_SD_EMMC_CFG 0x44
> > #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> > index 86c1a7164a..03fb70e717 100644
> > --- a/drivers/mmc/meson_gx_mmc.c
> > +++ b/drivers/mmc/meson_gx_mmc.c
> > @@ -16,6 +16,10 @@
> > #include <asm/arch/sd_emmc.h>
> > #include <linux/log2.h>
> >
> > +#include <linux/bitops.h>
> > +#include <linux/compat.h>
> > +#include <linux/bitfield.h>
> > +
> > static inline void *get_regbase(const struct mmc *mmc)
> > {
> > struct meson_mmc_platdata *pdata = mmc->priv;
> > @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> > }
> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >
> > - /* 180 phase core clock */
> > - meson_mmc_clk |= CLK_CO_PHASE_180;
> > -
> > - /* 180 phase tx clock */
> > - meson_mmc_clk |= CLK_TX_PHASE_000;
> > + /* Clock divider */
> > + meson_mmc_clk |= CLK_DIV_MASK;
> > + /* Clock source : Crystal 24MHz */
> > + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> > + /* Core clock phase 2:180 */
> > + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> > + /* TX clock phase 2:180 */
> > + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
>
> I think I mentionned already but this is not aligned with the setting
> used by the linux driver. If you have problems with these, please report
> it to the linux mailing list
Yes I will try to send this changes to linux driver since these are
the recommend
default values as per the datasheets, see below.
Cfg_tx_phase: TX clock phase 0: 0 phase, 1: 90 phase, 2: 180 phase, 3:
270 phase. Recommended value: 2
>
> > + /* RX clock phase 0:180 */
> > + meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> > +
> > +#ifdef CONFIG_MESON_GX
> > + /* TX clock delay line */
> > + meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
> > + /* RX clock delay line */
> > + meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
>
> Why do you need to this ?
As these are part of the linux driver, I added these,
I will check if this changes are needed in u-boot.
>
> > + /* clk always on */
> > + meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> > +#endif
> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> > + /* TX clock delay line */
> > + meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
> > + /* RX clock delay line */
> > + meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
> > + /* clk always on */
> > + meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> > +#endif
> >
> > /* clock settings */
> > meson_mmc_clk |= clk_src;
>
-Anand
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
2020-02-03 16:38 ` Anand Moon
@ 2020-02-03 17:44 ` Jerome Brunet
-1 siblings, 0 replies; 20+ messages in thread
From: Jerome Brunet @ 2020-02-03 17:44 UTC (permalink / raw)
To: u-boot
On Mon 03 Feb 2020 at 17:38, Anand Moon <linux.amoon@gmail.com> wrote:
> Hi Jerome,
>
> Thanks for your review,
>
> On Mon, 3 Feb 2020 at 21:11, Jerome Brunet <jbrunet@baylibre.com> wrote:
>>
>>
>> On Mon 03 Feb 2020 at 16:13, Anand Moon <linux.amoon@gmail.com> wrote:
>>
>> > As per mainline line kernel fix the clk tuning phase for mmc,
>> > set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
Which version ?
I don't recall any version of mainline linux kernel which has used these
default settings.
>> > As per S905, S905X, AGX and S922X datasheet set the default
>> > values for clk tuning.
>> >
>> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>> > ---
>> > arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
>> > drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
>> > 2 files changed, 50 insertions(+), 14 deletions(-)
>> >
>> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > index e3a72c8b66..b7a99947b3 100644
>> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > @@ -7,6 +7,7 @@
>> > #define __SD_EMMC_H__
>> >
>> > #include <mmc.h>
>> > +#include <linux/bitops.h>
>> >
>> > #define SDIO_PORT_A 0
>> > #define SDIO_PORT_B 1
>> > @@ -19,15 +20,24 @@
>> > #define CLK_MAX_DIV 63
>> > #define CLK_SRC_24M (0 << 6)
>> > #define CLK_SRC_DIV2 (1 << 6)
>> > -#define CLK_CO_PHASE_000 (0 << 8)
>> > -#define CLK_CO_PHASE_090 (1 << 8)
>> > -#define CLK_CO_PHASE_180 (2 << 8)
>> > -#define CLK_CO_PHASE_270 (3 << 8)
>> > -#define CLK_TX_PHASE_000 (0 << 10)
>> > -#define CLK_TX_PHASE_090 (1 << 10)
>> > -#define CLK_TX_PHASE_180 (2 << 10)
>> > -#define CLK_TX_PHASE_270 (3 << 10)
>> > -#define CLK_ALWAYS_ON BIT(24)
>> > +
>> > +#define CRYSTAL_24MHZ 0
>> > +#define CLK_PHASE_0 0
>> > +#define CLK_PHASE_180 2
>> > +
>> > +#define CLK_DIV_MASK GENMASK(5, 0)
>> > +#define CLK_SRC_MASK GENMASK(7, 6)
>> > +#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
>> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
>> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
>> > +
>> > +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
>> > +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
>> > +#define CLK_V2_ALWAYS_ON BIT(24)
>> > +
>> > +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
>> > +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
>> > +#define CLK_V3_ALWAYS_ON BIT(28)
>> >
>> > #define MESON_SD_EMMC_CFG 0x44
>> > #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
>> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>> > index 86c1a7164a..03fb70e717 100644
>> > --- a/drivers/mmc/meson_gx_mmc.c
>> > +++ b/drivers/mmc/meson_gx_mmc.c
>> > @@ -16,6 +16,10 @@
>> > #include <asm/arch/sd_emmc.h>
>> > #include <linux/log2.h>
>> >
>> > +#include <linux/bitops.h>
>> > +#include <linux/compat.h>
>> > +#include <linux/bitfield.h>
>> > +
>> > static inline void *get_regbase(const struct mmc *mmc)
>> > {
>> > struct meson_mmc_platdata *pdata = mmc->priv;
>> > @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>> > }
>> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
>> >
>> > - /* 180 phase core clock */
>> > - meson_mmc_clk |= CLK_CO_PHASE_180;
>> > -
>> > - /* 180 phase tx clock */
>> > - meson_mmc_clk |= CLK_TX_PHASE_000;
>> > + /* Clock divider */
>> > + meson_mmc_clk |= CLK_DIV_MASK;
>> > + /* Clock source : Crystal 24MHz */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>> > + /* Core clock phase 2:180 */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
>> > + /* TX clock phase 2:180 */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
>>
>> I think I mentionned already but this is not aligned with the setting
>> used by the linux driver. If you have problems with these, please report
>> it to the linux mailing list
>
> Yes I will try to send this changes to linux driver since these are
> the recommend
> default values as per the datasheets, see below.
> Cfg_tx_phase: TX clock phase 0: 0 phase, 1: 90 phase, 2: 180 phase, 3:
> 270 phase. Recommended value: 2
Well we already had that discussion 2 years ago regarding the
recommended setting. The fact is that it did not work that well.
Please the try the setting implemented in the linux driver
Core: 180, Tx: 0, Rx:0 and report issue to linux-ml. Thx
>
>>
>> > + /* RX clock phase 0:180 */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>> > +
>> > +#ifdef CONFIG_MESON_GX
>> > + /* TX clock delay line */
>> > + meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
>> > + /* RX clock delay line */
>> > + meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
>>
>> Why do you need to this ?
>
> As these are part of the linux driver, I added these,
> I will check if this changes are needed in u-boot.
The linux driver never wrote the MASK value to register, which would set
all the bits to 1. It does not make sense.
The fact is that the linux kernel has not been using the rx and tx
delays at all since v5.2
It would better to just let these values alone.
>>
>> > + /* clk always on */
>> > + meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>> > +#endif
>> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
>> > + /* TX clock delay line */
>> > + meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
>> > + /* RX clock delay line */
>> > + meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
>> > + /* clk always on */
>> > + meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>> > +#endif
>> >
>> > /* clock settings */
>> > meson_mmc_clk |= clk_src;
>>
>
> -Anand
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-03 17:44 ` Jerome Brunet
0 siblings, 0 replies; 20+ messages in thread
From: Jerome Brunet @ 2020-02-03 17:44 UTC (permalink / raw)
To: Anand Moon
Cc: Neil Armstrong, Peng Fan, Jaehoon Chung, u-boot-amlogic,
U-Boot Mailing List
On Mon 03 Feb 2020 at 17:38, Anand Moon <linux.amoon@gmail.com> wrote:
> Hi Jerome,
>
> Thanks for your review,
>
> On Mon, 3 Feb 2020 at 21:11, Jerome Brunet <jbrunet@baylibre.com> wrote:
>>
>>
>> On Mon 03 Feb 2020 at 16:13, Anand Moon <linux.amoon@gmail.com> wrote:
>>
>> > As per mainline line kernel fix the clk tuning phase for mmc,
>> > set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
Which version ?
I don't recall any version of mainline linux kernel which has used these
default settings.
>> > As per S905, S905X, AGX and S922X datasheet set the default
>> > values for clk tuning.
>> >
>> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>> > ---
>> > arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
>> > drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
>> > 2 files changed, 50 insertions(+), 14 deletions(-)
>> >
>> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > index e3a72c8b66..b7a99947b3 100644
>> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > @@ -7,6 +7,7 @@
>> > #define __SD_EMMC_H__
>> >
>> > #include <mmc.h>
>> > +#include <linux/bitops.h>
>> >
>> > #define SDIO_PORT_A 0
>> > #define SDIO_PORT_B 1
>> > @@ -19,15 +20,24 @@
>> > #define CLK_MAX_DIV 63
>> > #define CLK_SRC_24M (0 << 6)
>> > #define CLK_SRC_DIV2 (1 << 6)
>> > -#define CLK_CO_PHASE_000 (0 << 8)
>> > -#define CLK_CO_PHASE_090 (1 << 8)
>> > -#define CLK_CO_PHASE_180 (2 << 8)
>> > -#define CLK_CO_PHASE_270 (3 << 8)
>> > -#define CLK_TX_PHASE_000 (0 << 10)
>> > -#define CLK_TX_PHASE_090 (1 << 10)
>> > -#define CLK_TX_PHASE_180 (2 << 10)
>> > -#define CLK_TX_PHASE_270 (3 << 10)
>> > -#define CLK_ALWAYS_ON BIT(24)
>> > +
>> > +#define CRYSTAL_24MHZ 0
>> > +#define CLK_PHASE_0 0
>> > +#define CLK_PHASE_180 2
>> > +
>> > +#define CLK_DIV_MASK GENMASK(5, 0)
>> > +#define CLK_SRC_MASK GENMASK(7, 6)
>> > +#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
>> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
>> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
>> > +
>> > +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
>> > +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
>> > +#define CLK_V2_ALWAYS_ON BIT(24)
>> > +
>> > +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
>> > +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
>> > +#define CLK_V3_ALWAYS_ON BIT(28)
>> >
>> > #define MESON_SD_EMMC_CFG 0x44
>> > #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
>> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>> > index 86c1a7164a..03fb70e717 100644
>> > --- a/drivers/mmc/meson_gx_mmc.c
>> > +++ b/drivers/mmc/meson_gx_mmc.c
>> > @@ -16,6 +16,10 @@
>> > #include <asm/arch/sd_emmc.h>
>> > #include <linux/log2.h>
>> >
>> > +#include <linux/bitops.h>
>> > +#include <linux/compat.h>
>> > +#include <linux/bitfield.h>
>> > +
>> > static inline void *get_regbase(const struct mmc *mmc)
>> > {
>> > struct meson_mmc_platdata *pdata = mmc->priv;
>> > @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>> > }
>> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
>> >
>> > - /* 180 phase core clock */
>> > - meson_mmc_clk |= CLK_CO_PHASE_180;
>> > -
>> > - /* 180 phase tx clock */
>> > - meson_mmc_clk |= CLK_TX_PHASE_000;
>> > + /* Clock divider */
>> > + meson_mmc_clk |= CLK_DIV_MASK;
>> > + /* Clock source : Crystal 24MHz */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>> > + /* Core clock phase 2:180 */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
>> > + /* TX clock phase 2:180 */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
>>
>> I think I mentionned already but this is not aligned with the setting
>> used by the linux driver. If you have problems with these, please report
>> it to the linux mailing list
>
> Yes I will try to send this changes to linux driver since these are
> the recommend
> default values as per the datasheets, see below.
> Cfg_tx_phase: TX clock phase 0: 0 phase, 1: 90 phase, 2: 180 phase, 3:
> 270 phase. Recommended value: 2
Well we already had that discussion 2 years ago regarding the
recommended setting. The fact is that it did not work that well.
Please the try the setting implemented in the linux driver
Core: 180, Tx: 0, Rx:0 and report issue to linux-ml. Thx
>
>>
>> > + /* RX clock phase 0:180 */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
>> > +
>> > +#ifdef CONFIG_MESON_GX
>> > + /* TX clock delay line */
>> > + meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
>> > + /* RX clock delay line */
>> > + meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
>>
>> Why do you need to this ?
>
> As these are part of the linux driver, I added these,
> I will check if this changes are needed in u-boot.
The linux driver never wrote the MASK value to register, which would set
all the bits to 1. It does not make sense.
The fact is that the linux kernel has not been using the rx and tx
delays at all since v5.2
It would better to just let these values alone.
>>
>> > + /* clk always on */
>> > + meson_mmc_clk |= CLK_V2_ALWAYS_ON;
>> > +#endif
>> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
>> > + /* TX clock delay line */
>> > + meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
>> > + /* RX clock delay line */
>> > + meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
>> > + /* clk always on */
>> > + meson_mmc_clk |= CLK_V3_ALWAYS_ON;
>> > +#endif
>> >
>> > /* clock settings */
>> > meson_mmc_clk |= clk_src;
>>
>
> -Anand
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
2020-02-03 17:44 ` Jerome Brunet
@ 2020-02-04 3:09 ` Anand Moon
-1 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-04 3:09 UTC (permalink / raw)
To: u-boot
Hi Jerome,
Thanks for your review comments,
On Mon, 3 Feb 2020 at 23:14, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Mon 03 Feb 2020 at 17:38, Anand Moon <linux.amoon@gmail.com> wrote:
>
> > Hi Jerome,
> >
> > Thanks for your review,
> >
> > On Mon, 3 Feb 2020 at 21:11, Jerome Brunet <jbrunet@baylibre.com> wrote:
> >>
> >>
> >> On Mon 03 Feb 2020 at 16:13, Anand Moon <linux.amoon@gmail.com> wrote:
> >>
> >> > As per mainline line kernel fix the clk tuning phase for mmc,
> >> > set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
>
> Which version ?
> I don't recall any version of mainline linux kernel which has used these
> default settings.
Ok typo, I was just referring the datasheet for the default values,
>
> >> > As per S905, S905X, AGX and S922X datasheet set the default
> >> > values for clk tuning.
> >> >
> >> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >> > ---
> >> > arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
> >> > drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
> >> > 2 files changed, 50 insertions(+), 14 deletions(-)
> >> >
> >> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > index e3a72c8b66..b7a99947b3 100644
> >> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > @@ -7,6 +7,7 @@
> >> > #define __SD_EMMC_H__
> >> >
> >> > #include <mmc.h>
> >> > +#include <linux/bitops.h>
> >> >
> >> > #define SDIO_PORT_A 0
> >> > #define SDIO_PORT_B 1
> >> > @@ -19,15 +20,24 @@
> >> > #define CLK_MAX_DIV 63
> >> > #define CLK_SRC_24M (0 << 6)
> >> > #define CLK_SRC_DIV2 (1 << 6)
> >> > -#define CLK_CO_PHASE_000 (0 << 8)
> >> > -#define CLK_CO_PHASE_090 (1 << 8)
> >> > -#define CLK_CO_PHASE_180 (2 << 8)
> >> > -#define CLK_CO_PHASE_270 (3 << 8)
> >> > -#define CLK_TX_PHASE_000 (0 << 10)
> >> > -#define CLK_TX_PHASE_090 (1 << 10)
> >> > -#define CLK_TX_PHASE_180 (2 << 10)
> >> > -#define CLK_TX_PHASE_270 (3 << 10)
> >> > -#define CLK_ALWAYS_ON BIT(24)
> >> > +
> >> > +#define CRYSTAL_24MHZ 0
> >> > +#define CLK_PHASE_0 0
> >> > +#define CLK_PHASE_180 2
> >> > +
> >> > +#define CLK_DIV_MASK GENMASK(5, 0)
> >> > +#define CLK_SRC_MASK GENMASK(7, 6)
> >> > +#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
> >> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> >> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> >> > +
> >> > +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
> >> > +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
> >> > +#define CLK_V2_ALWAYS_ON BIT(24)
> >> > +
> >> > +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
> >> > +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
> >> > +#define CLK_V3_ALWAYS_ON BIT(28)
> >> >
> >> > #define MESON_SD_EMMC_CFG 0x44
> >> > #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
> >> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >> > index 86c1a7164a..03fb70e717 100644
> >> > --- a/drivers/mmc/meson_gx_mmc.c
> >> > +++ b/drivers/mmc/meson_gx_mmc.c
> >> > @@ -16,6 +16,10 @@
> >> > #include <asm/arch/sd_emmc.h>
> >> > #include <linux/log2.h>
> >> >
> >> > +#include <linux/bitops.h>
> >> > +#include <linux/compat.h>
> >> > +#include <linux/bitfield.h>
> >> > +
> >> > static inline void *get_regbase(const struct mmc *mmc)
> >> > {
> >> > struct meson_mmc_platdata *pdata = mmc->priv;
> >> > @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >> > }
> >> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >> >
> >> > - /* 180 phase core clock */
> >> > - meson_mmc_clk |= CLK_CO_PHASE_180;
> >> > -
> >> > - /* 180 phase tx clock */
> >> > - meson_mmc_clk |= CLK_TX_PHASE_000;
> >> > + /* Clock divider */
> >> > + meson_mmc_clk |= CLK_DIV_MASK;
> >> > + /* Clock source : Crystal 24MHz */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >> > + /* Core clock phase 2:180 */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> >> > + /* TX clock phase 2:180 */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
> >>
> >> I think I mentionned already but this is not aligned with the setting
> >> used by the linux driver. If you have problems with these, please report
> >> it to the linux mailing list
> >
> > Yes I will try to send this changes to linux driver since these are
> > the recommend
> > default values as per the datasheets, see below.
> > Cfg_tx_phase: TX clock phase 0: 0 phase, 1: 90 phase, 2: 180 phase, 3:
> > 270 phase. Recommended value: 2
>
> Well we already had that discussion 2 years ago regarding the
> recommended setting. The fact is that it did not work that well.
>
> Please the try the setting implemented in the linux driver
> Core: 180, Tx: 0, Rx:0 and report issue to linux-ml. Thx
>
Ok I will used the linux-ml setting over here as well in u-boot.
> >
> >>
> >> > + /* RX clock phase 0:180 */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> >> > +
> >> > +#ifdef CONFIG_MESON_GX
> >> > + /* TX clock delay line */
> >> > + meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
> >> > + /* RX clock delay line */
> >> > + meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
> >>
> >> Why do you need to this ?
> >
> > As these are part of the linux driver, I added these,
> > I will check if this changes are needed in u-boot.
>
> The linux driver never wrote the MASK value to register, which would set
> all the bits to 1. It does not make sense.
>
> The fact is that the linux kernel has not been using the rx and tx
> delays at all since v5.2
>
> It would better to just let these values alone.
Ok. I will drop this changes and stick to linux-ml changes for u-boot driver.
>
> >>
> >> > + /* clk always on */
> >> > + meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> >> > +#endif
> >> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> >> > + /* TX clock delay line */
> >> > + meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
> >> > + /* RX clock delay line */
> >> > + meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
> >> > + /* clk always on */
> >> > + meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> >> > +#endif
> >> >
> >> > /* clock settings */
> >> > meson_mmc_clk |= clk_src;
> >>
> >
> > -Anand
>
-Anand
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
@ 2020-02-04 3:09 ` Anand Moon
0 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-04 3:09 UTC (permalink / raw)
To: Jerome Brunet
Cc: Neil Armstrong, Peng Fan, Jaehoon Chung, u-boot-amlogic,
U-Boot Mailing List
Hi Jerome,
Thanks for your review comments,
On Mon, 3 Feb 2020 at 23:14, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Mon 03 Feb 2020 at 17:38, Anand Moon <linux.amoon@gmail.com> wrote:
>
> > Hi Jerome,
> >
> > Thanks for your review,
> >
> > On Mon, 3 Feb 2020 at 21:11, Jerome Brunet <jbrunet@baylibre.com> wrote:
> >>
> >>
> >> On Mon 03 Feb 2020 at 16:13, Anand Moon <linux.amoon@gmail.com> wrote:
> >>
> >> > As per mainline line kernel fix the clk tuning phase for mmc,
> >> > set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
>
> Which version ?
> I don't recall any version of mainline linux kernel which has used these
> default settings.
Ok typo, I was just referring the datasheet for the default values,
>
> >> > As per S905, S905X, AGX and S922X datasheet set the default
> >> > values for clk tuning.
> >> >
> >> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >> > ---
> >> > arch/arm/include/asm/arch-meson/sd_emmc.h | 28 ++++++++++++------
> >> > drivers/mmc/meson_gx_mmc.c | 36 +++++++++++++++++++----
> >> > 2 files changed, 50 insertions(+), 14 deletions(-)
> >> >
> >> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > index e3a72c8b66..b7a99947b3 100644
> >> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> >> > @@ -7,6 +7,7 @@
> >> > #define __SD_EMMC_H__
> >> >
> >> > #include <mmc.h>
> >> > +#include <linux/bitops.h>
> >> >
> >> > #define SDIO_PORT_A 0
> >> > #define SDIO_PORT_B 1
> >> > @@ -19,15 +20,24 @@
> >> > #define CLK_MAX_DIV 63
> >> > #define CLK_SRC_24M (0 << 6)
> >> > #define CLK_SRC_DIV2 (1 << 6)
> >> > -#define CLK_CO_PHASE_000 (0 << 8)
> >> > -#define CLK_CO_PHASE_090 (1 << 8)
> >> > -#define CLK_CO_PHASE_180 (2 << 8)
> >> > -#define CLK_CO_PHASE_270 (3 << 8)
> >> > -#define CLK_TX_PHASE_000 (0 << 10)
> >> > -#define CLK_TX_PHASE_090 (1 << 10)
> >> > -#define CLK_TX_PHASE_180 (2 << 10)
> >> > -#define CLK_TX_PHASE_270 (3 << 10)
> >> > -#define CLK_ALWAYS_ON BIT(24)
> >> > +
> >> > +#define CRYSTAL_24MHZ 0
> >> > +#define CLK_PHASE_0 0
> >> > +#define CLK_PHASE_180 2
> >> > +
> >> > +#define CLK_DIV_MASK GENMASK(5, 0)
> >> > +#define CLK_SRC_MASK GENMASK(7, 6)
> >> > +#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
> >> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> >> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> >> > +
> >> > +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
> >> > +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
> >> > +#define CLK_V2_ALWAYS_ON BIT(24)
> >> > +
> >> > +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
> >> > +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
> >> > +#define CLK_V3_ALWAYS_ON BIT(28)
> >> >
> >> > #define MESON_SD_EMMC_CFG 0x44
> >> > #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
> >> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> >> > index 86c1a7164a..03fb70e717 100644
> >> > --- a/drivers/mmc/meson_gx_mmc.c
> >> > +++ b/drivers/mmc/meson_gx_mmc.c
> >> > @@ -16,6 +16,10 @@
> >> > #include <asm/arch/sd_emmc.h>
> >> > #include <linux/log2.h>
> >> >
> >> > +#include <linux/bitops.h>
> >> > +#include <linux/compat.h>
> >> > +#include <linux/bitfield.h>
> >> > +
> >> > static inline void *get_regbase(const struct mmc *mmc)
> >> > {
> >> > struct meson_mmc_platdata *pdata = mmc->priv;
> >> > @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >> > }
> >> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
> >> >
> >> > - /* 180 phase core clock */
> >> > - meson_mmc_clk |= CLK_CO_PHASE_180;
> >> > -
> >> > - /* 180 phase tx clock */
> >> > - meson_mmc_clk |= CLK_TX_PHASE_000;
> >> > + /* Clock divider */
> >> > + meson_mmc_clk |= CLK_DIV_MASK;
> >> > + /* Clock source : Crystal 24MHz */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> >> > + /* Core clock phase 2:180 */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> >> > + /* TX clock phase 2:180 */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
> >>
> >> I think I mentionned already but this is not aligned with the setting
> >> used by the linux driver. If you have problems with these, please report
> >> it to the linux mailing list
> >
> > Yes I will try to send this changes to linux driver since these are
> > the recommend
> > default values as per the datasheets, see below.
> > Cfg_tx_phase: TX clock phase 0: 0 phase, 1: 90 phase, 2: 180 phase, 3:
> > 270 phase. Recommended value: 2
>
> Well we already had that discussion 2 years ago regarding the
> recommended setting. The fact is that it did not work that well.
>
> Please the try the setting implemented in the linux driver
> Core: 180, Tx: 0, Rx:0 and report issue to linux-ml. Thx
>
Ok I will used the linux-ml setting over here as well in u-boot.
> >
> >>
> >> > + /* RX clock phase 0:180 */
> >> > + meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> >> > +
> >> > +#ifdef CONFIG_MESON_GX
> >> > + /* TX clock delay line */
> >> > + meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
> >> > + /* RX clock delay line */
> >> > + meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
> >>
> >> Why do you need to this ?
> >
> > As these are part of the linux driver, I added these,
> > I will check if this changes are needed in u-boot.
>
> The linux driver never wrote the MASK value to register, which would set
> all the bits to 1. It does not make sense.
>
> The fact is that the linux kernel has not been using the rx and tx
> delays at all since v5.2
>
> It would better to just let these values alone.
Ok. I will drop this changes and stick to linux-ml changes for u-boot driver.
>
> >>
> >> > + /* clk always on */
> >> > + meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> >> > +#endif
> >> > +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> >> > + /* TX clock delay line */
> >> > + meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
> >> > + /* RX clock delay line */
> >> > + meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
> >> > + /* clk always on */
> >> > + meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> >> > +#endif
> >> >
> >> > /* clock settings */
> >> > meson_mmc_clk |= clk_src;
> >>
> >
> > -Anand
>
-Anand
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCHv5 2/5] mmc: meson-gx: Use proper compatible string as per the dts
2020-02-03 15:13 ` Anand Moon
@ 2020-02-03 15:13 ` Anand Moon
-1 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: u-boot
Use proper compatible string as per the dts so that mmc driver
could be tuned properly. SoC family S905, S905X have common clk
tuning parameters setting, while AGX and G12 have common clk tuning
parameters setting for mmc driver.
Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch in this series.
---
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 7 +++
drivers/mmc/meson_gx_mmc.c | 62 +++++++++++++++--------
2 files changed, 49 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index b7a99947b3..bb48b97ed1 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -13,6 +13,12 @@
#define SDIO_PORT_B 1
#define SDIO_PORT_C 2
+enum mmc_compatible {
+ MMC_COMPATIBLE_GXBB,
+ MMC_COMPATIBLE_GX,
+ MMC_COMPATIBLE_AXG,
+};
+
#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
@@ -91,6 +97,7 @@
struct meson_mmc_platdata {
struct mmc_config cfg;
struct mmc mmc;
+ int compat;
void *regbase;
void *w_buf;
};
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 03fb70e717..bf613e00ca 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
writel(val, get_regbase(mmc) + offset);
}
-static void meson_mmc_config_clock(struct mmc *mmc)
+static void meson_mmc_config_clock(struct mmc *mmc,
+ struct meson_mmc_platdata *pdata)
{
uint32_t meson_mmc_clk = 0;
unsigned int clk, clk_src, clk_div;
@@ -66,22 +67,28 @@ static void meson_mmc_config_clock(struct mmc *mmc)
/* RX clock phase 0:180 */
meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
-#ifdef CONFIG_MESON_GX
- /* TX clock delay line */
- meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
- /* RX clock delay line */
- meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
- /* clk always on */
- meson_mmc_clk |= CLK_V2_ALWAYS_ON;
-#endif
-#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
- /* TX clock delay line */
- meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
- /* RX clock delay line */
- meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
- /* clk always on */
- meson_mmc_clk |= CLK_V3_ALWAYS_ON;
-#endif
+ switch (pdata->compat) {
+ case MMC_COMPATIBLE_GXBB:
+ case MMC_COMPATIBLE_GX:
+ /* TX clock delay line */
+ meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
+ /* RX clock delay line */
+ meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
+ /* clk always on */
+ meson_mmc_clk |= CLK_V2_ALWAYS_ON;
+ break;
+ case MMC_COMPATIBLE_AXG:
+ /* TX clock delay line */
+ meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
+ /* RX clock delay line */
+ meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
+ /* clk always on */
+ meson_mmc_clk |= CLK_V3_ALWAYS_ON;
+ break;
+ default:
+ debug("no compatible supported");
+ break;
+ }
/* clock settings */
meson_mmc_clk |= clk_src;
@@ -93,9 +100,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
static int meson_dm_mmc_set_ios(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct meson_mmc_platdata *pdata =
+ (struct meson_mmc_platdata *)dev_get_driver_data(dev);
uint32_t meson_mmc_cfg;
- meson_mmc_config_clock(mmc);
+ meson_mmc_config_clock(mmc, pdata);
meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
@@ -332,9 +341,22 @@ int meson_mmc_bind(struct udevice *dev)
return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
}
+static const struct meson_mmc_platdata gxbb_data = {
+ .compat = MMC_COMPATIBLE_GXBB,
+};
+
+static const struct meson_mmc_platdata gx_data = {
+ .compat = MMC_COMPATIBLE_GX,
+};
+
+static const struct meson_mmc_platdata axg_data = {
+ .compat = MMC_COMPATIBLE_AXG,
+};
+
static const struct udevice_id meson_mmc_match[] = {
- { .compatible = "amlogic,meson-gx-mmc" },
- { .compatible = "amlogic,meson-axg-mmc" },
+ { .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
+ { .compatible = "amlogic,meson-gx-mmc", .data = (ulong)&gx_data },
+ { .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
{ /* sentinel */ }
};
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCHv5 2/5] mmc: meson-gx: Use proper compatible string as per the dts
@ 2020-02-03 15:13 ` Anand Moon
0 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
u-boot-amlogic, u-boot
Use proper compatible string as per the dts so that mmc driver
could be tuned properly. SoC family S905, S905X have common clk
tuning parameters setting, while AGX and G12 have common clk tuning
parameters setting for mmc driver.
Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch in this series.
---
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 7 +++
drivers/mmc/meson_gx_mmc.c | 62 +++++++++++++++--------
2 files changed, 49 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index b7a99947b3..bb48b97ed1 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -13,6 +13,12 @@
#define SDIO_PORT_B 1
#define SDIO_PORT_C 2
+enum mmc_compatible {
+ MMC_COMPATIBLE_GXBB,
+ MMC_COMPATIBLE_GX,
+ MMC_COMPATIBLE_AXG,
+};
+
#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
@@ -91,6 +97,7 @@
struct meson_mmc_platdata {
struct mmc_config cfg;
struct mmc mmc;
+ int compat;
void *regbase;
void *w_buf;
};
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 03fb70e717..bf613e00ca 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -37,7 +37,8 @@ static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
writel(val, get_regbase(mmc) + offset);
}
-static void meson_mmc_config_clock(struct mmc *mmc)
+static void meson_mmc_config_clock(struct mmc *mmc,
+ struct meson_mmc_platdata *pdata)
{
uint32_t meson_mmc_clk = 0;
unsigned int clk, clk_src, clk_div;
@@ -66,22 +67,28 @@ static void meson_mmc_config_clock(struct mmc *mmc)
/* RX clock phase 0:180 */
meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
-#ifdef CONFIG_MESON_GX
- /* TX clock delay line */
- meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
- /* RX clock delay line */
- meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
- /* clk always on */
- meson_mmc_clk |= CLK_V2_ALWAYS_ON;
-#endif
-#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
- /* TX clock delay line */
- meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
- /* RX clock delay line */
- meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
- /* clk always on */
- meson_mmc_clk |= CLK_V3_ALWAYS_ON;
-#endif
+ switch (pdata->compat) {
+ case MMC_COMPATIBLE_GXBB:
+ case MMC_COMPATIBLE_GX:
+ /* TX clock delay line */
+ meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
+ /* RX clock delay line */
+ meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
+ /* clk always on */
+ meson_mmc_clk |= CLK_V2_ALWAYS_ON;
+ break;
+ case MMC_COMPATIBLE_AXG:
+ /* TX clock delay line */
+ meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
+ /* RX clock delay line */
+ meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
+ /* clk always on */
+ meson_mmc_clk |= CLK_V3_ALWAYS_ON;
+ break;
+ default:
+ debug("no compatible supported");
+ break;
+ }
/* clock settings */
meson_mmc_clk |= clk_src;
@@ -93,9 +100,11 @@ static void meson_mmc_config_clock(struct mmc *mmc)
static int meson_dm_mmc_set_ios(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct meson_mmc_platdata *pdata =
+ (struct meson_mmc_platdata *)dev_get_driver_data(dev);
uint32_t meson_mmc_cfg;
- meson_mmc_config_clock(mmc);
+ meson_mmc_config_clock(mmc, pdata);
meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
@@ -332,9 +341,22 @@ int meson_mmc_bind(struct udevice *dev)
return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
}
+static const struct meson_mmc_platdata gxbb_data = {
+ .compat = MMC_COMPATIBLE_GXBB,
+};
+
+static const struct meson_mmc_platdata gx_data = {
+ .compat = MMC_COMPATIBLE_GX,
+};
+
+static const struct meson_mmc_platdata axg_data = {
+ .compat = MMC_COMPATIBLE_AXG,
+};
+
static const struct udevice_id meson_mmc_match[] = {
- { .compatible = "amlogic,meson-gx-mmc" },
- { .compatible = "amlogic,meson-axg-mmc" },
+ { .compatible = "amlogic,meson-gxbb-mmc", .data = (ulong)&gxbb_data },
+ { .compatible = "amlogic,meson-gx-mmc", .data = (ulong)&gx_data },
+ { .compatible = "amlogic,meson-axg-mmc", .data = (ulong)&axg_data },
{ /* sentinel */ }
};
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCHv5 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
2020-02-03 15:13 ` Anand Moon
@ 2020-02-03 15:13 ` Anand Moon
-1 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: u-boot
Move u-boot specific common nodes in the dts files to
meson-gx-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.
mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch in this series
---
arch/arm/dts/meson-gx-u-boot.dtsi | 15 +++++++++++++++
arch/arm/dts/meson-gxbb-nanopi-k2.dts | 9 ---------
arch/arm/dts/meson-gxbb-odroidc2.dts | 9 ---------
arch/arm/dts/meson-gxbb-p20x.dtsi | 9 ---------
arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
arch/arm/dts/meson-gxl-s905x-khadas-vim.dts | 5 -----
arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 9 ---------
arch/arm/dts/meson-gxl-s905x-p212.dtsi | 10 ----------
arch/arm/dts/meson-gxm-khadas-vim2.dts | 10 ----------
9 files changed, 15 insertions(+), 71 deletions(-)
diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
index b84e5edba4..13be3a7b8f 100644
--- a/arch/arm/dts/meson-gx-u-boot.dtsi
+++ b/arch/arm/dts/meson-gx-u-boot.dtsi
@@ -8,6 +8,21 @@
soc {
u-boot,dm-pre-reloc;
};
+
+ aliases {
+ serial0 = &uart_AO;
+ serial1 = &uart_A;
+ serial2 = &uart_AO_B;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ mmc0 = &sd_emmc_a;
+ mmc1 = &sd_emmc_b;
+ mmc2 = &sd_emmc_c;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
};
&vpu {
diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
index cbe99bd4e0..11690d6c46 100644
--- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
+++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
@@ -11,15 +11,6 @@
/ {
compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory at 0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
index 54954b314a..f8cd76a2ef 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -14,15 +14,6 @@
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
model = "Hardkernel ODROID-C2";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory at 0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
index 0be0f2a5d2..c9822e50f9 100644
--- a/arch/arm/dts/meson-gxbb-p20x.dtsi
+++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
@@ -8,15 +8,6 @@
#include "meson-gxbb.dtsi"
/ {
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory at 0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
index 82b1c48511..4f9072a83e 100644
--- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
+++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
@@ -16,16 +16,6 @@
"amlogic,meson-gxl";
model = "Libre Computer Board AML-S805X-AC";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- spi0 = &spifc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
cvbs-connector {
/*
* The pads are present but no connector is soldered on
diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
index ceb34afe42..072e4575d2 100644
--- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
@@ -26,11 +26,6 @@
};
};
- aliases {
- serial2 = &uart_AO_B;
- ethernet0 = ðmac;
- };
-
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
index a23252efc6..8d3965ab42 100644
--- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
@@ -15,15 +15,6 @@
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
model = "Libre Computer Board AML-S905X-CC";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
cvbs-connector {
compatible = "composite-video-connector";
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
index a1b31013ab..70f437fc3a 100644
--- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
@@ -13,16 +13,6 @@
#include "meson-gxl-s905x.dtsi"
/ {
- aliases {
- serial0 = &uart_AO;
- serial1 = &uart_A;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory at 0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
index 782e9edac8..4e68e289d3 100644
--- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
+++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
@@ -16,16 +16,6 @@
compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
model = "Khadas VIM2";
- aliases {
- serial0 = &uart_AO;
- serial1 = &uart_A;
- serial2 = &uart_AO_B;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory at 0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCHv5 3/5] arm: dts: gx: Move common nodes to the -u-boot.dtsi
@ 2020-02-03 15:13 ` Anand Moon
0 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
u-boot-amlogic, u-boot
Move u-boot specific common nodes in the dts files to
meson-gx-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.
mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch in this series
---
arch/arm/dts/meson-gx-u-boot.dtsi | 15 +++++++++++++++
arch/arm/dts/meson-gxbb-nanopi-k2.dts | 9 ---------
arch/arm/dts/meson-gxbb-odroidc2.dts | 9 ---------
arch/arm/dts/meson-gxbb-p20x.dtsi | 9 ---------
arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 10 ----------
arch/arm/dts/meson-gxl-s905x-khadas-vim.dts | 5 -----
arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 9 ---------
arch/arm/dts/meson-gxl-s905x-p212.dtsi | 10 ----------
arch/arm/dts/meson-gxm-khadas-vim2.dts | 10 ----------
9 files changed, 15 insertions(+), 71 deletions(-)
diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi
index b84e5edba4..13be3a7b8f 100644
--- a/arch/arm/dts/meson-gx-u-boot.dtsi
+++ b/arch/arm/dts/meson-gx-u-boot.dtsi
@@ -8,6 +8,21 @@
soc {
u-boot,dm-pre-reloc;
};
+
+ aliases {
+ serial0 = &uart_AO;
+ serial1 = &uart_A;
+ serial2 = &uart_AO_B;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ mmc0 = &sd_emmc_a;
+ mmc1 = &sd_emmc_b;
+ mmc2 = &sd_emmc_c;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
};
&vpu {
diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
index cbe99bd4e0..11690d6c46 100644
--- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
+++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
@@ -11,15 +11,6 @@
/ {
compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
index 54954b314a..f8cd76a2ef 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -14,15 +14,6 @@
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
model = "Hardkernel ODROID-C2";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi
index 0be0f2a5d2..c9822e50f9 100644
--- a/arch/arm/dts/meson-gxbb-p20x.dtsi
+++ b/arch/arm/dts/meson-gxbb-p20x.dtsi
@@ -8,15 +8,6 @@
#include "meson-gxbb.dtsi"
/ {
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
index 82b1c48511..4f9072a83e 100644
--- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
+++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
@@ -16,16 +16,6 @@
"amlogic,meson-gxl";
model = "Libre Computer Board AML-S805X-AC";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- spi0 = &spifc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
cvbs-connector {
/*
* The pads are present but no connector is soldered on
diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
index ceb34afe42..072e4575d2 100644
--- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
@@ -26,11 +26,6 @@
};
};
- aliases {
- serial2 = &uart_AO_B;
- ethernet0 = ðmac;
- };
-
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
index a23252efc6..8d3965ab42 100644
--- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
@@ -15,15 +15,6 @@
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
model = "Libre Computer Board AML-S905X-CC";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
cvbs-connector {
compatible = "composite-video-connector";
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
index a1b31013ab..70f437fc3a 100644
--- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
@@ -13,16 +13,6 @@
#include "meson-gxl-s905x.dtsi"
/ {
- aliases {
- serial0 = &uart_AO;
- serial1 = &uart_A;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
index 782e9edac8..4e68e289d3 100644
--- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
+++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
@@ -16,16 +16,6 @@
compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
model = "Khadas VIM2";
- aliases {
- serial0 = &uart_AO;
- serial1 = &uart_A;
- serial2 = &uart_AO_B;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCHv5 4/5] arm: dts: g12: Move common nodes to the -u-boot.dtsi
2020-02-03 15:13 ` Anand Moon
@ 2020-02-03 15:13 ` Anand Moon
-1 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: u-boot
Move u-boot specific common nodes in the dts files to
meson-g12-common-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.
mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch in this series
---
arch/arm/dts/meson-g12-common-u-boot.dtsi | 12 ++++++++++++
arch/arm/dts/meson-g12a-sei510.dts | 9 ---------
arch/arm/dts/meson-g12a-u200.dts | 9 ---------
arch/arm/dts/meson-g12b-odroid-n2.dts | 9 ---------
arch/arm/dts/meson-khadas-vim3.dtsi | 9 ---------
arch/arm/dts/meson-sm1-sei610.dts | 9 ---------
6 files changed, 12 insertions(+), 45 deletions(-)
diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
index 38fd3d3feb..347b8ded22 100644
--- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
+++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
@@ -8,6 +8,18 @@
soc {
u-boot,dm-pre-reloc;
};
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ mmc0 = &sd_emmc_a;
+ mmc1 = &sd_emmc_b;
+ mmc2 = &sd_emmc_c;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
};
&canvas {
diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
index c7a8736885..c6a48ebbe5 100644
--- a/arch/arm/dts/meson-g12a-sei510.dts
+++ b/arch/arm/dts/meson-g12a-sei510.dts
@@ -28,11 +28,6 @@
};
};
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
mono_dac: audio-codec-0 {
compatible = "maxim,max98357a";
#sound-dai-cells = <0>;
@@ -49,10 +44,6 @@
sound-name-prefix = "MIC";
};
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
cvbs-connector {
compatible = "composite-video-connector";
diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
index 8551fbd4a4..8be7b6985b 100644
--- a/arch/arm/dts/meson-g12a-u200.dts
+++ b/arch/arm/dts/meson-g12a-u200.dts
@@ -13,15 +13,6 @@
compatible = "amlogic,u200", "amlogic,g12a";
model = "Amlogic Meson G12A U200 Development Board";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
cvbs-connector {
compatible = "composite-video-connector";
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
index 42f1540575..a37f66a5e0 100644
--- a/arch/arm/dts/meson-g12b-odroid-n2.dts
+++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
@@ -15,15 +15,6 @@
compatible = "hardkernel,odroid-n2", "amlogic,g12b";
model = "Hardkernel ODROID-N2";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory at 0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
index 8647da7d66..c6b0ce9a88 100644
--- a/arch/arm/dts/meson-khadas-vim3.dtsi
+++ b/arch/arm/dts/meson-khadas-vim3.dtsi
@@ -11,15 +11,6 @@
/ {
model = "Khadas VIM3";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory at 0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
index 3435aaa4e8..4372708811 100644
--- a/arch/arm/dts/meson-sm1-sei610.dts
+++ b/arch/arm/dts/meson-sm1-sei610.dts
@@ -14,15 +14,6 @@
compatible = "seirobotics,sei610", "amlogic,sm1";
model = "SEI Robotics SEI610";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCHv5 4/5] arm: dts: g12: Move common nodes to the -u-boot.dtsi
@ 2020-02-03 15:13 ` Anand Moon
0 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
u-boot-amlogic, u-boot
Move u-boot specific common nodes in the dts files to
meson-g12-common-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.
mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch in this series
---
arch/arm/dts/meson-g12-common-u-boot.dtsi | 12 ++++++++++++
arch/arm/dts/meson-g12a-sei510.dts | 9 ---------
arch/arm/dts/meson-g12a-u200.dts | 9 ---------
arch/arm/dts/meson-g12b-odroid-n2.dts | 9 ---------
arch/arm/dts/meson-khadas-vim3.dtsi | 9 ---------
arch/arm/dts/meson-sm1-sei610.dts | 9 ---------
6 files changed, 12 insertions(+), 45 deletions(-)
diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi
index 38fd3d3feb..347b8ded22 100644
--- a/arch/arm/dts/meson-g12-common-u-boot.dtsi
+++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi
@@ -8,6 +8,18 @@
soc {
u-boot,dm-pre-reloc;
};
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ mmc0 = &sd_emmc_a;
+ mmc1 = &sd_emmc_b;
+ mmc2 = &sd_emmc_c;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
};
&canvas {
diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
index c7a8736885..c6a48ebbe5 100644
--- a/arch/arm/dts/meson-g12a-sei510.dts
+++ b/arch/arm/dts/meson-g12a-sei510.dts
@@ -28,11 +28,6 @@
};
};
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
mono_dac: audio-codec-0 {
compatible = "maxim,max98357a";
#sound-dai-cells = <0>;
@@ -49,10 +44,6 @@
sound-name-prefix = "MIC";
};
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
cvbs-connector {
compatible = "composite-video-connector";
diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
index 8551fbd4a4..8be7b6985b 100644
--- a/arch/arm/dts/meson-g12a-u200.dts
+++ b/arch/arm/dts/meson-g12a-u200.dts
@@ -13,15 +13,6 @@
compatible = "amlogic,u200", "amlogic,g12a";
model = "Amlogic Meson G12A U200 Development Board";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
cvbs-connector {
compatible = "composite-video-connector";
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
index 42f1540575..a37f66a5e0 100644
--- a/arch/arm/dts/meson-g12b-odroid-n2.dts
+++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
@@ -15,15 +15,6 @@
compatible = "hardkernel,odroid-n2", "amlogic,g12b";
model = "Hardkernel ODROID-N2";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
index 8647da7d66..c6b0ce9a88 100644
--- a/arch/arm/dts/meson-khadas-vim3.dtsi
+++ b/arch/arm/dts/meson-khadas-vim3.dtsi
@@ -11,15 +11,6 @@
/ {
model = "Khadas VIM3";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
index 3435aaa4e8..4372708811 100644
--- a/arch/arm/dts/meson-sm1-sei610.dts
+++ b/arch/arm/dts/meson-sm1-sei610.dts
@@ -14,15 +14,6 @@
compatible = "seirobotics,sei610", "amlogic,sm1";
model = "SEI Robotics SEI610";
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCHv5 5/5] arm: dts: s400: Move common nodes to the -u-boot.dtsi
2020-02-03 15:13 ` Anand Moon
@ 2020-02-03 15:13 ` Anand Moon
-1 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: u-boot
Move u-boot specific common nodes in the dts files to
meson-axg-s400-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.
mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch is the series
---
arch/arm/dts/meson-axg-s400-u-boot.dtsi | 16 ++++++++++++++++
arch/arm/dts/meson-axg-s400.dts | 9 ---------
2 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
index c46eb3f38d..74241e9fcd 100644
--- a/arch/arm/dts/meson-axg-s400-u-boot.dtsi
+++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
@@ -2,6 +2,22 @@
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ serial1 = &uart_A;
+ mmc1 = &sd_emmc_b;
+ mmc2 = &sd_emmc_c;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
/* wifi module */
&sd_emmc_b {
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
index 18778ada7b..feb84255ad 100644
--- a/arch/arm/dts/meson-axg-s400.dts
+++ b/arch/arm/dts/meson-axg-s400.dts
@@ -55,11 +55,6 @@
};
};
- aliases {
- serial0 = &uart_AO;
- serial1 = &uart_A;
- };
-
linein: audio-codec at 0 {
#sound-dai-cells = <0>;
compatible = "everest,es7241";
@@ -100,10 +95,6 @@
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory at 0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCHv5 5/5] arm: dts: s400: Move common nodes to the -u-boot.dtsi
@ 2020-02-03 15:13 ` Anand Moon
0 siblings, 0 replies; 20+ messages in thread
From: Anand Moon @ 2020-02-03 15:13 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Peng Fan, Jaehoon Chung,
u-boot-amlogic, u-boot
Move u-boot specific common nodes in the dts files to
meson-axg-s400-u-boot.dtsi. This allows us to keep the basic
dts[i] files up-to-date with the ones in kernel,
but at the same time allowing the u-boot to add its own
properties to the existing nodes.
Also add missing mmc alias to dts nodes to avoid
below debug warning.
mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
New patch is the series
---
arch/arm/dts/meson-axg-s400-u-boot.dtsi | 16 ++++++++++++++++
arch/arm/dts/meson-axg-s400.dts | 9 ---------
2 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
index c46eb3f38d..74241e9fcd 100644
--- a/arch/arm/dts/meson-axg-s400-u-boot.dtsi
+++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
@@ -2,6 +2,22 @@
/*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ serial1 = &uart_A;
+ mmc1 = &sd_emmc_b;
+ mmc2 = &sd_emmc_c;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
/* wifi module */
&sd_emmc_b {
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
index 18778ada7b..feb84255ad 100644
--- a/arch/arm/dts/meson-axg-s400.dts
+++ b/arch/arm/dts/meson-axg-s400.dts
@@ -55,11 +55,6 @@
};
};
- aliases {
- serial0 = &uart_AO;
- serial1 = &uart_A;
- };
-
linein: audio-codec@0 {
#sound-dai-cells = <0>;
compatible = "everest,es7241";
@@ -100,10 +95,6 @@
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
--
2.25.0
^ permalink raw reply related [flat|nested] 20+ messages in thread