* [PATCH 0/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks @ 2020-02-19 8:49 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2020-02-19 8:49 UTC (permalink / raw) To: jbrunet Cc: Neil Armstrong, linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel Like on the AXG SoCs, the SPICC controllers can make use of an external clock source instead of it's internal divider over xtal to provide a better SCLK clock frequency. This serie adds the new clock IDs and the associated clocks in the g12a driver. Neil Armstrong (2): dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: g12a: add support for the SPICC SCLK Source clocks drivers/clk/meson/g12a.c | 129 ++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 6 +- include/dt-bindings/clock/g12a-clkc.h | 2 + 3 files changed, 136 insertions(+), 1 deletion(-) -- 2.22.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks @ 2020-02-19 8:49 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2020-02-19 8:49 UTC (permalink / raw) To: jbrunet Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel, Neil Armstrong Like on the AXG SoCs, the SPICC controllers can make use of an external clock source instead of it's internal divider over xtal to provide a better SCLK clock frequency. This serie adds the new clock IDs and the associated clocks in the g12a driver. Neil Armstrong (2): dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: g12a: add support for the SPICC SCLK Source clocks drivers/clk/meson/g12a.c | 129 ++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 6 +- include/dt-bindings/clock/g12a-clkc.h | 2 + 3 files changed, 136 insertions(+), 1 deletion(-) -- 2.22.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks @ 2020-02-19 8:49 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2020-02-19 8:49 UTC (permalink / raw) To: jbrunet Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel, Neil Armstrong Like on the AXG SoCs, the SPICC controllers can make use of an external clock source instead of it's internal divider over xtal to provide a better SCLK clock frequency. This serie adds the new clock IDs and the associated clocks in the g12a driver. Neil Armstrong (2): dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: g12a: add support for the SPICC SCLK Source clocks drivers/clk/meson/g12a.c | 129 ++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 6 +- include/dt-bindings/clock/g12a-clkc.h | 2 + 3 files changed, 136 insertions(+), 1 deletion(-) -- 2.22.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs 2020-02-19 8:49 ` Neil Armstrong (?) @ 2020-02-19 8:49 ` Neil Armstrong -1 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2020-02-19 8:49 UTC (permalink / raw) To: jbrunet, devicetree Cc: Neil Armstrong, linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- include/dt-bindings/clock/g12a-clkc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 0837c1a7ae49..b0d65d73db96 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -143,5 +143,7 @@ #define CLKID_CPU1_CLK 253 #define CLKID_CPU2_CLK 254 #define CLKID_CPU3_CLK 255 +#define CLKID_SPICC0_SCLK 258 +#define CLKID_SPICC1_SCLK 261 #endif /* __G12A_CLKC_H */ -- 2.22.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/2] dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs @ 2020-02-19 8:49 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2020-02-19 8:49 UTC (permalink / raw) To: jbrunet, devicetree Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel, Neil Armstrong Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- include/dt-bindings/clock/g12a-clkc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 0837c1a7ae49..b0d65d73db96 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -143,5 +143,7 @@ #define CLKID_CPU1_CLK 253 #define CLKID_CPU2_CLK 254 #define CLKID_CPU3_CLK 255 +#define CLKID_SPICC0_SCLK 258 +#define CLKID_SPICC1_SCLK 261 #endif /* __G12A_CLKC_H */ -- 2.22.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/2] dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs @ 2020-02-19 8:49 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2020-02-19 8:49 UTC (permalink / raw) To: jbrunet, devicetree Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel, Neil Armstrong Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- include/dt-bindings/clock/g12a-clkc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 0837c1a7ae49..b0d65d73db96 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -143,5 +143,7 @@ #define CLKID_CPU1_CLK 253 #define CLKID_CPU2_CLK 254 #define CLKID_CPU3_CLK 255 +#define CLKID_SPICC0_SCLK 258 +#define CLKID_SPICC1_SCLK 261 #endif /* __G12A_CLKC_H */ -- 2.22.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs 2020-02-19 8:49 ` Neil Armstrong (?) @ 2020-02-26 15:29 ` Rob Herring -1 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2020-02-26 15:29 UTC (permalink / raw) To: Neil Armstrong Cc: jbrunet, devicetree, Neil Armstrong, linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel On Wed, 19 Feb 2020 09:49:27 +0100, Neil Armstrong wrote: > Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > include/dt-bindings/clock/g12a-clkc.h | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs @ 2020-02-26 15:29 ` Rob Herring 0 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2020-02-26 15:29 UTC (permalink / raw) To: Neil Armstrong Cc: devicetree, Neil Armstrong, linux-kernel, linux-amlogic, linux-clk, linux-arm-kernel, jbrunet On Wed, 19 Feb 2020 09:49:27 +0100, Neil Armstrong wrote: > Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > include/dt-bindings/clock/g12a-clkc.h | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs @ 2020-02-26 15:29 ` Rob Herring 0 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2020-02-26 15:29 UTC (permalink / raw) To: Neil Armstrong Cc: devicetree, Neil Armstrong, linux-kernel, linux-amlogic, linux-clk, linux-arm-kernel, jbrunet On Wed, 19 Feb 2020 09:49:27 +0100, Neil Armstrong wrote: > Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > include/dt-bindings/clock/g12a-clkc.h | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks 2020-02-19 8:49 ` Neil Armstrong (?) @ 2020-02-19 8:49 ` Neil Armstrong -1 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2020-02-19 8:49 UTC (permalink / raw) To: jbrunet Cc: Neil Armstrong, linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC controller to provide a more complete range of frequencies instead of the SPICC internal divider over Xtal. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/clk/meson/g12a.c | 129 +++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 6 +- 2 files changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index d2760a021301..fad616cac01e 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -3862,6 +3862,111 @@ static struct clk_regmap g12a_ts = { }, }; +/* SPICC SCLK source clock */ + +static const struct clk_parent_data spicc_sclk_parent_data[] = { + { .fw_name = "xtal", }, + { .hw = &g12a_clk81.hw }, + { .hw = &g12a_fclk_div4.hw }, + { .hw = &g12a_fclk_div3.hw }, + { .hw = &g12a_fclk_div5.hw }, + { .hw = &g12a_fclk_div7.hw }, +}; + +static struct clk_regmap g12a_spicc0_sclk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SPICC_CLK_CNTL, + .mask = 7, + .shift = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = spicc_sclk_parent_data, + .num_parents = ARRAY_SIZE(spicc_sclk_parent_data), + }, +}; + +static struct clk_regmap g12a_spicc0_sclk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SPICC_CLK_CNTL, + .shift = 0, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc0_sclk_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_spicc0_sclk = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SPICC_CLK_CNTL, + .bit_idx = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc0_sclk_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_spicc1_sclk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SPICC_CLK_CNTL, + .mask = 7, + .shift = 23, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = spicc_sclk_parent_data, + .num_parents = ARRAY_SIZE(spicc_sclk_parent_data), + }, +}; + +static struct clk_regmap g12a_spicc1_sclk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SPICC_CLK_CNTL, + .shift = 16, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc1_sclk_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_spicc1_sclk = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SPICC_CLK_CNTL, + .bit_idx = 22, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc1_sclk_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + #define MESON_GATE(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw) @@ -4159,6 +4264,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, [CLKID_TS_DIV] = &g12a_ts_div.hw, [CLKID_TS] = &g12a_ts.hw, + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -4408,6 +4519,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw, [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw, [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw, + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -4642,6 +4759,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw, [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw, [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw, + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -4877,6 +5000,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &sm1_cpu1_clk, &sm1_cpu2_clk, &sm1_cpu3_clk, + &g12a_spicc0_sclk_sel, + &g12a_spicc0_sclk_div, + &g12a_spicc0_sclk, + &g12a_spicc1_sclk_sel, + &g12a_spicc1_sclk_div, + &g12a_spicc1_sclk, }; static const struct reg_sequence g12a_init_regs[] = { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 9df4068aced1..a8852556836e 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -255,8 +255,12 @@ #define CLKID_DSU_CLK_DYN1 249 #define CLKID_DSU_CLK_DYN 250 #define CLKID_DSU_CLK_FINAL 251 +#define CLKID_SPICC0_SCLK_SEL 256 +#define CLKID_SPICC0_SCLK_DIV 257 +#define CLKID_SPICC1_SCLK_SEL 259 +#define CLKID_SPICC1_SCLK_DIV 260 -#define NR_CLKS 256 +#define NR_CLKS 262 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/g12a-clkc.h> -- 2.22.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks @ 2020-02-19 8:49 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2020-02-19 8:49 UTC (permalink / raw) To: jbrunet Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel, Neil Armstrong This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC controller to provide a more complete range of frequencies instead of the SPICC internal divider over Xtal. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/clk/meson/g12a.c | 129 +++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 6 +- 2 files changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index d2760a021301..fad616cac01e 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -3862,6 +3862,111 @@ static struct clk_regmap g12a_ts = { }, }; +/* SPICC SCLK source clock */ + +static const struct clk_parent_data spicc_sclk_parent_data[] = { + { .fw_name = "xtal", }, + { .hw = &g12a_clk81.hw }, + { .hw = &g12a_fclk_div4.hw }, + { .hw = &g12a_fclk_div3.hw }, + { .hw = &g12a_fclk_div5.hw }, + { .hw = &g12a_fclk_div7.hw }, +}; + +static struct clk_regmap g12a_spicc0_sclk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SPICC_CLK_CNTL, + .mask = 7, + .shift = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = spicc_sclk_parent_data, + .num_parents = ARRAY_SIZE(spicc_sclk_parent_data), + }, +}; + +static struct clk_regmap g12a_spicc0_sclk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SPICC_CLK_CNTL, + .shift = 0, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc0_sclk_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_spicc0_sclk = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SPICC_CLK_CNTL, + .bit_idx = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc0_sclk_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_spicc1_sclk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SPICC_CLK_CNTL, + .mask = 7, + .shift = 23, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = spicc_sclk_parent_data, + .num_parents = ARRAY_SIZE(spicc_sclk_parent_data), + }, +}; + +static struct clk_regmap g12a_spicc1_sclk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SPICC_CLK_CNTL, + .shift = 16, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc1_sclk_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_spicc1_sclk = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SPICC_CLK_CNTL, + .bit_idx = 22, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc1_sclk_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + #define MESON_GATE(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw) @@ -4159,6 +4264,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, [CLKID_TS_DIV] = &g12a_ts_div.hw, [CLKID_TS] = &g12a_ts.hw, + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -4408,6 +4519,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw, [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw, [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw, + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -4642,6 +4759,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw, [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw, [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw, + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -4877,6 +5000,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &sm1_cpu1_clk, &sm1_cpu2_clk, &sm1_cpu3_clk, + &g12a_spicc0_sclk_sel, + &g12a_spicc0_sclk_div, + &g12a_spicc0_sclk, + &g12a_spicc1_sclk_sel, + &g12a_spicc1_sclk_div, + &g12a_spicc1_sclk, }; static const struct reg_sequence g12a_init_regs[] = { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 9df4068aced1..a8852556836e 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -255,8 +255,12 @@ #define CLKID_DSU_CLK_DYN1 249 #define CLKID_DSU_CLK_DYN 250 #define CLKID_DSU_CLK_FINAL 251 +#define CLKID_SPICC0_SCLK_SEL 256 +#define CLKID_SPICC0_SCLK_DIV 257 +#define CLKID_SPICC1_SCLK_SEL 259 +#define CLKID_SPICC1_SCLK_DIV 260 -#define NR_CLKS 256 +#define NR_CLKS 262 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/g12a-clkc.h> -- 2.22.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks @ 2020-02-19 8:49 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2020-02-19 8:49 UTC (permalink / raw) To: jbrunet Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel, Neil Armstrong This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC controller to provide a more complete range of frequencies instead of the SPICC internal divider over Xtal. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/clk/meson/g12a.c | 129 +++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 6 +- 2 files changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index d2760a021301..fad616cac01e 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -3862,6 +3862,111 @@ static struct clk_regmap g12a_ts = { }, }; +/* SPICC SCLK source clock */ + +static const struct clk_parent_data spicc_sclk_parent_data[] = { + { .fw_name = "xtal", }, + { .hw = &g12a_clk81.hw }, + { .hw = &g12a_fclk_div4.hw }, + { .hw = &g12a_fclk_div3.hw }, + { .hw = &g12a_fclk_div5.hw }, + { .hw = &g12a_fclk_div7.hw }, +}; + +static struct clk_regmap g12a_spicc0_sclk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SPICC_CLK_CNTL, + .mask = 7, + .shift = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = spicc_sclk_parent_data, + .num_parents = ARRAY_SIZE(spicc_sclk_parent_data), + }, +}; + +static struct clk_regmap g12a_spicc0_sclk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SPICC_CLK_CNTL, + .shift = 0, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc0_sclk_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_spicc0_sclk = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SPICC_CLK_CNTL, + .bit_idx = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc0_sclk_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_spicc1_sclk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SPICC_CLK_CNTL, + .mask = 7, + .shift = 23, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = spicc_sclk_parent_data, + .num_parents = ARRAY_SIZE(spicc_sclk_parent_data), + }, +}; + +static struct clk_regmap g12a_spicc1_sclk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SPICC_CLK_CNTL, + .shift = 16, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc1_sclk_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_spicc1_sclk = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SPICC_CLK_CNTL, + .bit_idx = 22, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc1_sclk_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + #define MESON_GATE(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw) @@ -4159,6 +4264,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, [CLKID_TS_DIV] = &g12a_ts_div.hw, [CLKID_TS] = &g12a_ts.hw, + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -4408,6 +4519,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw, [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw, [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw, + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -4642,6 +4759,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw, [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw, [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw, + [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, + [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -4877,6 +5000,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &sm1_cpu1_clk, &sm1_cpu2_clk, &sm1_cpu3_clk, + &g12a_spicc0_sclk_sel, + &g12a_spicc0_sclk_div, + &g12a_spicc0_sclk, + &g12a_spicc1_sclk_sel, + &g12a_spicc1_sclk_div, + &g12a_spicc1_sclk, }; static const struct reg_sequence g12a_init_regs[] = { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 9df4068aced1..a8852556836e 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -255,8 +255,12 @@ #define CLKID_DSU_CLK_DYN1 249 #define CLKID_DSU_CLK_DYN 250 #define CLKID_DSU_CLK_FINAL 251 +#define CLKID_SPICC0_SCLK_SEL 256 +#define CLKID_SPICC0_SCLK_DIV 257 +#define CLKID_SPICC1_SCLK_SEL 259 +#define CLKID_SPICC1_SCLK_DIV 260 -#define NR_CLKS 256 +#define NR_CLKS 262 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/g12a-clkc.h> -- 2.22.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 0/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks 2020-02-19 8:49 ` Neil Armstrong (?) @ 2020-02-19 17:57 ` Jerome Brunet -1 siblings, 0 replies; 16+ messages in thread From: Jerome Brunet @ 2020-02-19 17:57 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel On Wed 19 Feb 2020 at 09:49, Neil Armstrong <narmstrong@baylibre.com> wrote: > Like on the AXG SoCs, the SPICC controllers can make use of an external clock > source instead of it's internal divider over xtal to provide a better SCLK > clock frequency. > > This serie adds the new clock IDs and the associated clocks in the g12a driver. > > Neil Armstrong (2): > dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs > clk: meson: g12a: add support for the SPICC SCLK Source clocks > > drivers/clk/meson/g12a.c | 129 ++++++++++++++++++++++++++ > drivers/clk/meson/g12a.h | 6 +- > include/dt-bindings/clock/g12a-clkc.h | 2 + > 3 files changed, 136 insertions(+), 1 deletion(-) Applied. Thx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks @ 2020-02-19 17:57 ` Jerome Brunet 0 siblings, 0 replies; 16+ messages in thread From: Jerome Brunet @ 2020-02-19 17:57 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel On Wed 19 Feb 2020 at 09:49, Neil Armstrong <narmstrong@baylibre.com> wrote: > Like on the AXG SoCs, the SPICC controllers can make use of an external clock > source instead of it's internal divider over xtal to provide a better SCLK > clock frequency. > > This serie adds the new clock IDs and the associated clocks in the g12a driver. > > Neil Armstrong (2): > dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs > clk: meson: g12a: add support for the SPICC SCLK Source clocks > > drivers/clk/meson/g12a.c | 129 ++++++++++++++++++++++++++ > drivers/clk/meson/g12a.h | 6 +- > include/dt-bindings/clock/g12a-clkc.h | 2 + > 3 files changed, 136 insertions(+), 1 deletion(-) Applied. Thx _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks @ 2020-02-19 17:57 ` Jerome Brunet 0 siblings, 0 replies; 16+ messages in thread From: Jerome Brunet @ 2020-02-19 17:57 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-amlogic, linux-clk, linux-arm-kernel, linux-kernel On Wed 19 Feb 2020 at 09:49, Neil Armstrong <narmstrong@baylibre.com> wrote: > Like on the AXG SoCs, the SPICC controllers can make use of an external clock > source instead of it's internal divider over xtal to provide a better SCLK > clock frequency. > > This serie adds the new clock IDs and the associated clocks in the g12a driver. > > Neil Armstrong (2): > dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs > clk: meson: g12a: add support for the SPICC SCLK Source clocks > > drivers/clk/meson/g12a.c | 129 ++++++++++++++++++++++++++ > drivers/clk/meson/g12a.h | 6 +- > include/dt-bindings/clock/g12a-clkc.h | 2 + > 3 files changed, 136 insertions(+), 1 deletion(-) Applied. Thx _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks 2020-02-19 8:49 ` Neil Armstrong ` (4 preceding siblings ...) (?) @ 2020-04-16 16:08 ` patchwork-bot+linux-amlogic -1 siblings, 0 replies; 16+ messages in thread From: patchwork-bot+linux-amlogic @ 2020-04-16 16:08 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-amlogic, khilman Hello: This series was applied to khilman/linux-amlogic.git (refs/heads/for-next). On Wed, 19 Feb 2020 09:49:26 +0100 you wrote: > Like on the AXG SoCs, the SPICC controllers can make use of an external clock > source instead of it's internal divider over xtal to provide a better SCLK > clock frequency. > > This serie adds the new clock IDs and the associated clocks in the g12a driver. > > Neil Armstrong (2): > dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs > clk: meson: g12a: add support for the SPICC SCLK Source clocks > > [...] Here is a summary with links: - [1/2] dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs https://git.kernel.org/khilman/linux-amlogic/c/51a0c29b229ebc33f25398532797639d8c5aafe7 - [2/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks https://git.kernel.org/khilman/linux-amlogic/c/a18c8e0b76979881f3b31e96c398e62ab30a1662 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.wiki.kernel.org/userdoc/pwbot _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-04-16 16:08 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-19 8:49 [PATCH 0/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks Neil Armstrong 2020-02-19 8:49 ` Neil Armstrong 2020-02-19 8:49 ` Neil Armstrong 2020-02-19 8:49 ` [PATCH 1/2] dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs Neil Armstrong 2020-02-19 8:49 ` Neil Armstrong 2020-02-19 8:49 ` Neil Armstrong 2020-02-26 15:29 ` Rob Herring 2020-02-26 15:29 ` Rob Herring 2020-02-26 15:29 ` Rob Herring 2020-02-19 8:49 ` [PATCH 2/2] clk: meson: g12a: add support for the SPICC SCLK Source clocks Neil Armstrong 2020-02-19 8:49 ` Neil Armstrong 2020-02-19 8:49 ` Neil Armstrong 2020-02-19 17:57 ` [PATCH 0/2] " Jerome Brunet 2020-02-19 17:57 ` Jerome Brunet 2020-02-19 17:57 ` Jerome Brunet 2020-04-16 16:08 ` patchwork-bot+linux-amlogic
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