回复: Re: 回复: [PATCH] x86/spec_ctrl: Fix several bugs in SPEC_CTRL_ENTRY_FROM_INTR_IST

回复: Re: 回复: [PATCH] x86/spec_ctrl: Fix several bugs in SPEC_CTRL_ENTRY_FROM_INTR_IST

[zhenzhong.duan]

[-- Attachment #1.1: Type: text/plain, Size: 801 bytes --]


2018年2月14日 20:21于 Andrew Cooper <andrew.cooper3@citrix.com>写道：
>
> On 14/02/18 12:08, zhenzhong.duan wrote: 
> > 
> > > @@ -286,13 +286,13 @@ 
> > >      setz %dl 
> > >      and %dl, STACK_CPUINFO_FIELD(use_shadow_spec_ctrl)(%r14) 
> > Is it safe to remove the 'xor %edx, %edx' above? setz set whole byte 1 
> > or 0. 
> > 
>
> It is safe, but it is not a good idea. 
>
> Using setz is an 8bit operation, which will suffer a register merge 
> stall in the pipeline as we know for certain at this point that the 
> upper bits of %edx are nonzero at this point.  (An encoding which 
> allowed setz %eax would have been far more useful in 64bit code.) 
>
Thanks for explain. But just curious does processor has ideas the whole register is zeroed and avoid a merge?

thanks
zduan

[-- Attachment #1.2: Type: text/html, Size: 1124 bytes --]

[-- Attachment #2: Type: text/plain, Size: 157 bytes --]

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

Re: 回复: Re: 回复: [PATCH] x86/spec_ctrl: Fix several bugs in SPEC_CTRL_ENTRY_FROM_INTR_IST

[Andrew Cooper]

[-- Attachment #1.1: Type: text/plain, Size: 1073 bytes --]

On 14/02/18 13:04, zhenzhong.duan wrote:
>
> 2018年2月14日 20:21于 Andrew Cooper <andrew.cooper3@citrix.com
> <mailto:andrew.cooper3@citrix.com>>写道：
> >
> > On 14/02/18 12:08, zhenzhong.duan wrote:
> > >
> > > > @@ -286,13 +286,13 @@
> > > >      setz %dl
> > > >      and %dl, STACK_CPUINFO_FIELD(use_shadow_spec_ctrl)(%r14)
> > > Is it safe to remove the 'xor %edx, %edx' above? setz set whole
> byte 1
> > > or 0.
> > >
> >
> > It is safe, but it is not a good idea.
> >
> > Using setz is an 8bit operation, which will suffer a register merge
> > stall in the pipeline as we know for certain at this point that the
> > upper bits of %edx are nonzero at this point.  (An encoding which
> > allowed setz %eax would have been far more useful in 64bit code.)
> >
> Thanks for explain. But just curious does processor has ideas the
> whole register is zeroed and avoid a merge?
>

Yes.  See the Zeroing Idioms section in the optimisation manual. 
Tracking which registers are zero helps breaks read-after-write data
dependences in the pipeline.

~Andrew

[-- Attachment #1.2: Type: text/html, Size: 1847 bytes --]

[-- Attachment #2: Type: text/plain, Size: 157 bytes --]

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel