How to request an IRQ for NMI on MIPS Processor

How to request an IRQ for NMI on MIPS Processor

[Adeel Malik]

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Hi All,
          In my embedded design, I intend to use NMI of MIPS 4Kc processor
(rather than IRQ0 or IRQ1 .....) for an external Interrupt Source. The
external Interrupt source is a video capture device which interrupts the
MIPS 4Kc CPU via its NMI (Non-Maskable Interrupt) line, whenever it has one
complete frame. I need to write the driver for that device in Linux-2.4.20.
The request_irq function provided by Linux takes a digit value from 0 to 5
to map external interrupt sources to any one of CPUs Interrupt pins. How can
I request and implement my interrupt handler routine for the NMI of MIPS
processor ?.
 
Regards,
ADEEL MALIK,


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Re: How to request an IRQ for NMI on MIPS Processor

[Ralf Baechle]

On Tue, Nov 04, 2003 at 04:56:08PM +0500, Adeel Malik wrote:

>           In my embedded design, I intend to use NMI of MIPS 4Kc processor
> (rather than IRQ0 or IRQ1 .....) for an external Interrupt Source. The
> external Interrupt source is a video capture device which interrupts the
> MIPS 4Kc CPU via its NMI (Non-Maskable Interrupt) line, whenever it has one
> complete frame. I need to write the driver for that device in Linux-2.4.20.
> The request_irq function provided by Linux takes a digit value from 0 to 5
> to map external interrupt sources to any one of CPUs Interrupt pins. How can
> I request and implement my interrupt handler routine for the NMI of MIPS
> processor ?.

Is there any particular reason for using the NMI?

NMI on MIPS is pretty much miss-designed for use in application code; it's
use should be limited to debugging and recovery from catastrophical
failure.  The reason for this is the way this exception is handled:

  - the BEV, TS, SR, NMI and ERL bits in c0_status are overwritten - that is
    their old state is lost.
  - c0_errorepc is overwritten - again that means the old value is lost so
    in case the NMI interrupts an exception handler that uses this register
    such as the cache error handler you can not resume execution.
  - the program counter is set to 0xbfc00000.  Most likely a slow flash
    memory is mapped at this address but in any case it's an uncached
    segment of the address space so execution will be even slower.
  - execution will pass through the firmware.  That means you can only
    use the NMI at all if firmware provides some kind of hook.

It seems pretty clear to me that the MIPS designers never intended the
NMI for anything else than catastrophic events.

  Ralf

Re: How to request an IRQ for NMI on MIPS Processor

[Ralf Baechle]

On Tue, Nov 11, 2003 at 01:26:53PM +0800, Liu Hongming (Alan) wrote:

> I have understood your situation.
>  
> Under this situation,I think you need not use request_irq.

Request_irq is just the software interface; it could be used to drive
any kind of interrupt mechanism, even NMI or the two MIPS software
interrupts.  The actual problem here is the underlying hardware
mechanism and firmware.

> Just keep your 'interrupt' handler in BIOS or bootloader,
> of course,it is different with Rest Exception,since 
> many registers' status are not the same as hardware-reseting.
> You could detect the difference.Right?

Note the firmware is usually in some kind of PROM (sloooow) and also
running uncached.  One reasons of many why the MIPS NMI is only a good
idea for fatal events.

  Ralf

RE: How to request an IRQ for NMI on MIPS Processor

[Liu Hongming (Alan)]

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Hi Adeel,
 
I have understood your situation.
 
Under this situation,I think you need not use request_irq.
Just keep your 'interrupt' handler in BIOS or bootloader,
of course,it is different with Rest Exception,since 
many registers' status are not the same as hardware-reseting.
You could detect the difference.Right?
 
 
Alan Liu
 
-----Original Message-----
From: Adeel Malik [mailto:AdeelM@quartics.com]
Sent: Tuesday, November 11, 2003 1:22 PM
To: Liu Hongming (Alan)
Cc: Ralf Baechle; linux-mips@linux-mips.org
Subject: RE: How to request an IRQ for NMI on MIPS Processor


Liu,
      In my board the interrupt was routed directly to an NMI line of MIPS
CPU rather than regular IRQs 0 - 5.   I went through the MIPS Architecture
Programming Guide Document, describing Interrupt and Exception Handling for
MIPS Processor. It is written there that although a Non-Maskable Interrupt
(NMI) includes "interrupt" in its name, it is more correctly described as an
NMI exception because it does not affect, nor is it controlled by the
processor interrupt system. 
 
Secondly, Linux Kernel especially the Embedded Linux Versions for various
Processors doesn't support the use of NMI as a regular IRQ.
 
The Interrupt Vector Address of all the Hardware Interrupt from IRQ0 - IRQ5
for MIPS Processor have the same vector location that is 0x80000180 or
0x80000380 which is a cached access, but the vector Location of NMI is
0xbfc00000 which is an un-cached access. So one needs to modify the
boot-code which is error-prone if it is possible at all.
 
Thatswhy we don't find much code related to NMIs in Linux.
 
ADEEL MALIK,

-----Original Message-----
From: linux-mips-bounce@linux-mips.org
[mailto:linux-mips-bounce@linux-mips.org]On Behalf Of Liu Hongming (Alan)
Sent: Tuesday, November 11, 2003 9:39 AM
To: Ralf Baechle; Liu Hongming (Alan)
Cc: Adeel Malik; linux-mips@linux-mips.org
Subject: RE: How to request an IRQ for NMI on MIPS Processor




Hi Ralf, 

I have never used these kind of boards.It seems to me 
NMI is implemented by interrupt controller,to cpu,it is a 
normal interrupt source.If 'NMI' in Adeel's board is like 
what you repeated,request_irq could just use cpu's pin number 
as the 'irq' parameter. I think NMI has been used in many 
boards that only means 'non-maskable' to interrupt controller, 
not cpu. If it is this case, NMI interrupt is a normal case. 

Regards, 
Alan Liu 

-----Original Message----- 
From: Ralf Baechle [ mailto:ralf@linux-mips.org <mailto:ralf@linux-mips.org>
] 
Sent: Tuesday, November 11, 2003 11:40 AM 
To: Liu Hongming (Alan) 
Cc: Adeel Malik; linux-mips@linux-mips.org 
Subject: Re: How to request an IRQ for NMI on MIPS Processor 


Liu, 

On Tue, Nov 11, 2003 at 10:51:50AM +0800, Liu Hongming (Alan) wrote: 

> when using request_irq(...),the parameter irq is a value specified by you,

> of course,when porting linux for your board,you should have specified
value 
> for every IRQ. 0--5 only means CPU pin for interrupt,unless that only one 
> interrupt 
> may occur on this pin,you will use other value in request_irq,instead of 
> 0-5. 
>  
> all in all, when we touch request_irq,it is board specific.When your board

> has 
> been made out,all interrupts have specific route to cpu(unless you have
IRQ 
> router,since embedded,need this??).If you have more external interrupts
than 
> cpu pins,maybe you have cascaded many interrupt using one cpu pin.So, 
> the parameter irq in request_irq is determined by your board and your 
> porting 
> for interrupt handling.Just ask that guy that ported linux.He will tell 
> you.If you 
> are using linux ported by others,have a look at BSP codes. 

your answer is correct for normal interrupts, not the NMI.  The NMI goes 
through the firmware and none of the board support code so far bothered 
to make it available via request_irq as it has several severe limitations. 
To repeat one of my prior postings about the NMI: 

NMI on MIPS is pretty much miss-designed for use in application code; it's 
use should be limited to debugging and recovery from catastrophical 
failure.  The reason for this is the way this exception is handled: 
 

  - the BEV, TS, SR, NMI and ERL bits in c0_status are overwritten - that is

    their old state is lost. 
  - c0_errorepc is overwritten - again that means the old value is lost so 
    in case the NMI interrupts an exception handler that uses this register 
    such as the cache error handler you can not resume execution. 
  - the program counter is set to 0xbfc00000.  Most likely a slow flash 
    memory is mapped at this address but in any case it's an uncached 
    segment of the address space so execution will be even slower. 
  - execution will pass through the firmware.  That means you can only 
    use the NMI at all if firmware provides some kind of hook. 
 

It seems pretty clear to me that the MIPS designers never intended the 
NMI for anything else than catastrophic events. 

  Ralf 


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RE: How to request an IRQ for NMI on MIPS Processor

[Adeel Malik]

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Liu,
      In my board the interrupt was routed directly to an NMI line of MIPS
CPU rather than regular IRQs 0 - 5.   I went through the MIPS Architecture
Programming Guide Document, describing Interrupt and Exception Handling for
MIPS Processor. It is written there that although a Non-Maskable Interrupt
(NMI) includes "interrupt" in its name, it is more correctly described as an
NMI exception because it does not affect, nor is it controlled by the
processor interrupt system. 
 
Secondly, Linux Kernel especially the Embedded Linux Versions for various
Processors doesn't support the use of NMI as a regular IRQ.
 
The Interrupt Vector Address of all the Hardware Interrupt from IRQ0 - IRQ5
for MIPS Processor have the same vector location that is 0x80000180 or
0x80000380 which is a cached access, but the vector Location of NMI is
0xbfc00000 which is an un-cached access. So one needs to modify the
boot-code which is error-prone if it is possible at all.
 
Thatswhy we don't find much code related to NMIs in Linux.
 
ADEEL MALIK,

-----Original Message-----
From: linux-mips-bounce@linux-mips.org
[mailto:linux-mips-bounce@linux-mips.org]On Behalf Of Liu Hongming (Alan)
Sent: Tuesday, November 11, 2003 9:39 AM
To: Ralf Baechle; Liu Hongming (Alan)
Cc: Adeel Malik; linux-mips@linux-mips.org
Subject: RE: How to request an IRQ for NMI on MIPS Processor




Hi Ralf, 

I have never used these kind of boards.It seems to me 
NMI is implemented by interrupt controller,to cpu,it is a 
normal interrupt source.If 'NMI' in Adeel's board is like 
what you repeated,request_irq could just use cpu's pin number 
as the 'irq' parameter. I think NMI has been used in many 
boards that only means 'non-maskable' to interrupt controller, 
not cpu. If it is this case, NMI interrupt is a normal case. 

Regards, 
Alan Liu 

-----Original Message----- 
From: Ralf Baechle [ mailto:ralf@linux-mips.org <mailto:ralf@linux-mips.org>
] 
Sent: Tuesday, November 11, 2003 11:40 AM 
To: Liu Hongming (Alan) 
Cc: Adeel Malik; linux-mips@linux-mips.org 
Subject: Re: How to request an IRQ for NMI on MIPS Processor 


Liu, 

On Tue, Nov 11, 2003 at 10:51:50AM +0800, Liu Hongming (Alan) wrote: 

> when using request_irq(...),the parameter irq is a value specified by you,

> of course,when porting linux for your board,you should have specified
value 
> for every IRQ. 0--5 only means CPU pin for interrupt,unless that only one 
> interrupt 
> may occur on this pin,you will use other value in request_irq,instead of 
> 0-5. 
>  
> all in all, when we touch request_irq,it is board specific.When your board

> has 
> been made out,all interrupts have specific route to cpu(unless you have
IRQ 
> router,since embedded,need this??).If you have more external interrupts
than 
> cpu pins,maybe you have cascaded many interrupt using one cpu pin.So, 
> the parameter irq in request_irq is determined by your board and your 
> porting 
> for interrupt handling.Just ask that guy that ported linux.He will tell 
> you.If you 
> are using linux ported by others,have a look at BSP codes. 

your answer is correct for normal interrupts, not the NMI.  The NMI goes 
through the firmware and none of the board support code so far bothered 
to make it available via request_irq as it has several severe limitations. 
To repeat one of my prior postings about the NMI: 

NMI on MIPS is pretty much miss-designed for use in application code; it's 
use should be limited to debugging and recovery from catastrophical 
failure.  The reason for this is the way this exception is handled: 
 

  - the BEV, TS, SR, NMI and ERL bits in c0_status are overwritten - that is

    their old state is lost. 
  - c0_errorepc is overwritten - again that means the old value is lost so 
    in case the NMI interrupts an exception handler that uses this register 
    such as the cache error handler you can not resume execution. 
  - the program counter is set to 0xbfc00000.  Most likely a slow flash 
    memory is mapped at this address but in any case it's an uncached 
    segment of the address space so execution will be even slower. 
  - execution will pass through the firmware.  That means you can only 
    use the NMI at all if firmware provides some kind of hook. 
 

It seems pretty clear to me that the MIPS designers never intended the 
NMI for anything else than catastrophic events. 

  Ralf 


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RE: How to request an IRQ for NMI on MIPS Processor

[Liu Hongming (Alan)]

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Hi Ralf,

I have never used these kind of boards.It seems to me 
NMI is implemented by interrupt controller,to cpu,it is a 
normal interrupt source.If 'NMI' in Adeel's board is like 
what you repeated,request_irq could just use cpu's pin number
as the 'irq' parameter. I think NMI has been used in many
boards that only means 'non-maskable' to interrupt controller,
not cpu. If it is this case, NMI interrupt is a normal case.

Regards,
Alan Liu

-----Original Message-----
From: Ralf Baechle [mailto:ralf@linux-mips.org]
Sent: Tuesday, November 11, 2003 11:40 AM
To: Liu Hongming (Alan)
Cc: Adeel Malik; linux-mips@linux-mips.org
Subject: Re: How to request an IRQ for NMI on MIPS Processor


Liu,

On Tue, Nov 11, 2003 at 10:51:50AM +0800, Liu Hongming (Alan) wrote:

> when using request_irq(...),the parameter irq is a value specified by you,
> of course,when porting linux for your board,you should have specified
value
> for every IRQ. 0--5 only means CPU pin for interrupt,unless that only one
> interrupt
> may occur on this pin,you will use other value in request_irq,instead of
> 0-5.
>  
> all in all, when we touch request_irq,it is board specific.When your board
> has
> been made out,all interrupts have specific route to cpu(unless you have
IRQ
> router,since embedded,need this??).If you have more external interrupts
than
> cpu pins,maybe you have cascaded many interrupt using one cpu pin.So,
> the parameter irq in request_irq is determined by your board and your
> porting
> for interrupt handling.Just ask that guy that ported linux.He will tell
> you.If you
> are using linux ported by others,have a look at BSP codes.

your answer is correct for normal interrupts, not the NMI.  The NMI goes
through the firmware and none of the board support code so far bothered
to make it available via request_irq as it has several severe limitations.
To repeat one of my prior postings about the NMI:

NMI on MIPS is pretty much miss-designed for use in application code; it's
use should be limited to debugging and recovery from catastrophical
failure.  The reason for this is the way this exception is handled:
 

  - the BEV, TS, SR, NMI and ERL bits in c0_status are overwritten - that is
    their old state is lost.
  - c0_errorepc is overwritten - again that means the old value is lost so
    in case the NMI interrupts an exception handler that uses this register
    such as the cache error handler you can not resume execution.
  - the program counter is set to 0xbfc00000.  Most likely a slow flash
    memory is mapped at this address but in any case it's an uncached
    segment of the address space so execution will be even slower.
  - execution will pass through the firmware.  That means you can only
    use the NMI at all if firmware provides some kind of hook.
 

It seems pretty clear to me that the MIPS designers never intended the
NMI for anything else than catastrophic events.

  Ralf

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Re: How to request an IRQ for NMI on MIPS Processor

[Ralf Baechle]

Liu,

On Tue, Nov 11, 2003 at 10:51:50AM +0800, Liu Hongming (Alan) wrote:

> when using request_irq(...),the parameter irq is a value specified by you,
> of course,when porting linux for your board,you should have specified value
> for every IRQ. 0--5 only means CPU pin for interrupt,unless that only one
> interrupt
> may occur on this pin,you will use other value in request_irq,instead of
> 0-5.
>  
> all in all, when we touch request_irq,it is board specific.When your board
> has
> been made out,all interrupts have specific route to cpu(unless you have IRQ
> router,since embedded,need this??).If you have more external interrupts than
> cpu pins,maybe you have cascaded many interrupt using one cpu pin.So,
> the parameter irq in request_irq is determined by your board and your
> porting
> for interrupt handling.Just ask that guy that ported linux.He will tell
> you.If you
> are using linux ported by others,have a look at BSP codes.

your answer is correct for normal interrupts, not the NMI.  The NMI goes
through the firmware and none of the board support code so far bothered
to make it available via request_irq as it has several severe limitations.
To repeat one of my prior postings about the NMI:

NMI on MIPS is pretty much miss-designed for use in application code; it's
use should be limited to debugging and recovery from catastrophical
failure.  The reason for this is the way this exception is handled:
                                                                                
  - the BEV, TS, SR, NMI and ERL bits in c0_status are overwritten - that is
    their old state is lost.
  - c0_errorepc is overwritten - again that means the old value is lost so
    in case the NMI interrupts an exception handler that uses this register
    such as the cache error handler you can not resume execution.
  - the program counter is set to 0xbfc00000.  Most likely a slow flash
    memory is mapped at this address but in any case it's an uncached
    segment of the address space so execution will be even slower.
  - execution will pass through the firmware.  That means you can only
    use the NMI at all if firmware provides some kind of hook.
                                                                                
It seems pretty clear to me that the MIPS designers never intended the
NMI for anything else than catastrophic events.

  Ralf

RE: How to request an IRQ for NMI on MIPS Processor

[Liu Hongming (Alan)]

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hi Malik,

when using request_irq(...),the parameter irq is a value specified by you,
of course,when porting linux for your board,you should have specified value
for every IRQ. 0--5 only means CPU pin for interrupt,unless that only one
interrupt
may occur on this pin,you will use other value in request_irq,instead of
0-5.
 
all in all, when we touch request_irq,it is board specific.When your board
has
been made out,all interrupts have specific route to cpu(unless you have IRQ
router,since embedded,need this??).If you have more external interrupts than
cpu pins,maybe you have cascaded many interrupt using one cpu pin.So,
the parameter irq in request_irq is determined by your board and your
porting
for interrupt handling.Just ask that guy that ported linux.He will tell
you.If you
are using linux ported by others,have a look at BSP codes.
 
Regards,
Alan Liu
 
-----Original Message-----
From: Adeel Malik [mailto:AdeelM@quartics.com]
Sent: Tuesday, November 04, 2003 7:56 PM
To: linux-mips@linux-mips.org
Subject: How to request an IRQ for NMI on MIPS Processor


Hi All,
          In my embedded design, I intend to use NMI of MIPS 4Kc processor
(rather than IRQ0 or IRQ1 .....) for an external Interrupt Source. The
external Interrupt source is a video capture device which interrupts the
MIPS 4Kc CPU via its NMI (Non-Maskable Interrupt) line, whenever it has one
complete frame. I need to write the driver for that device in Linux-2.4.20.
The request_irq function provided by Linux takes a digit value from 0 to 5
to map external interrupt sources to any one of CPUs Interrupt pins. How can
I request and implement my interrupt handler routine for the NMI of MIPS
processor ?.
 
Regards,
ADEEL MALIK,


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Re: How to request an IRQ for NMI on MIPS Processor

[Ralf Baechle]

On Tue, Nov 04, 2003 at 05:58:32PM +0500, Adeel Malik wrote:

> Hi Ralph,
        ^^

Who is that guy? ;-)

> 	   Thanks for the reply. Yes you are right that NMI isn't meant to
> be used as a regular IRQ of MIPS Processor. But somehow the board designer
> connected the External Interrupt from video capture device to the NMI and
> now I am thinking as how to how implement the Interrupt handler routine for
> the NMI of MIPS processor. Do you think that we need to re-route the Board
> or there may be some patch available describing the implementation of
> Interrupt handler for NMI of MIPS 4Kc.

As I said the NMI goes through the firmware so the way how to handle the
NMI on your specific board is entirely upto the firmware.  This is also
why you don't find much code related to NMIs in Linux.

I think it's highly desirable to fix this little hardware problem even
though that is going to involve some cost.  To look at things a bit more
from the Linux side:

 - NMI may even interrupt a previous NMI.  Again that means you'll lose your
   previous state, dead.
 - NMI means you have to paranoidly check the interrupt code.

Hmm...  Here's a little idea.  Bits 8 and 9 in the status and cause
registers are for the MIPS sofware interrupt bits which Linux doesn't use
at all.  NMI could use those so on return from NMI a normal maskable
interrupt would be triggered.  That would minimize the NMI path and
complications that could arise from it's not-maskability.

  Ralf

RE: How to request an IRQ for NMI on MIPS Processor

[Adeel Malik]

Hi Ralph,
	   Thanks for the reply. Yes you are right that NMI isn't meant to
be used as a regular IRQ of MIPS Processor. But somehow the board designer
connected the External Interrupt from video capture device to the NMI and
now I am thinking as how to how implement the Interrupt handler routine for
the NMI of MIPS processor. Do you think that we need to re-route the Board
or there may be some patch available describing the implementation of
Interrupt handler for NMI of MIPS 4Kc.

Regards, 	

ADEEL MALIK,


-----Original Message-----
From: linux-mips-bounce@linux-mips.org
[mailto:linux-mips-bounce@linux-mips.org]On Behalf Of Ralf Baechle
Sent: Tuesday, November 04, 2003 5:31 PM
To: Adeel Malik
Cc: linux-mips@linux-mips.org
Subject: Re: How to request an IRQ for NMI on MIPS Processor


On Tue, Nov 04, 2003 at 04:56:08PM +0500, Adeel Malik wrote:

>           In my embedded design, I intend to use NMI of MIPS 4Kc processor
> (rather than IRQ0 or IRQ1 .....) for an external Interrupt Source. The
> external Interrupt source is a video capture device which interrupts the
> MIPS 4Kc CPU via its NMI (Non-Maskable Interrupt) line, whenever it has
one
> complete frame. I need to write the driver for that device in
Linux-2.4.20.
> The request_irq function provided by Linux takes a digit value from 0 to 5
> to map external interrupt sources to any one of CPUs Interrupt pins. How
can
> I request and implement my interrupt handler routine for the NMI of MIPS
> processor ?.

Is there any particular reason for using the NMI?

NMI on MIPS is pretty much miss-designed for use in application code; it's
use should be limited to debugging and recovery from catastrophical
failure.  The reason for this is the way this exception is handled:

  - the BEV, TS, SR, NMI and ERL bits in c0_status are overwritten - that is
    their old state is lost.
  - c0_errorepc is overwritten - again that means the old value is lost so
    in case the NMI interrupts an exception handler that uses this register
    such as the cache error handler you can not resume execution.
  - the program counter is set to 0xbfc00000.  Most likely a slow flash
    memory is mapped at this address but in any case it's an uncached
    segment of the address space so execution will be even slower.
  - execution will pass through the firmware.  That means you can only
    use the NMI at all if firmware provides some kind of hook.

It seems pretty clear to me that the MIPS designers never intended the
NMI for anything else than catastrophic events.

  Ralf