* [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
@ 2008-12-05 11:49 Jean-Christophe PLAGNIOL-VILLARD
2008-12-14 11:37 ` Shin-ichiro KAWASAKI
0 siblings, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-12-05 11:49 UTC (permalink / raw)
To: qemu-devel
Cc: Takashi Yoshii, Nobuhiro Iwamatsu, Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Takashi Yoshii <yoshii.takashi@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
---
hw/sh7750.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++--
hw/sh7750_regnames.c | 2 +
hw/sh7750_regs.h | 11 +++++++++
3 files changed, 69 insertions(+), 3 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 4ae90b1..78843f3 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -42,8 +42,12 @@ typedef struct SH7750State {
uint32_t periph_freq;
/* SDRAM controller */
uint32_t bcr1;
- uint32_t bcr2;
+ uint16_t bcr2;
+ uint16_t bcr3;
+ uint32_t bcr4;
uint16_t rfcr;
+ /* PCMCIA controller */
+ uint16_t pcr;
/* IO ports */
uint16_t gpioic;
uint32_t pctra;
@@ -67,7 +71,10 @@ typedef struct SH7750State {
struct intc_desc intc;
} SH7750State;
-
+static int inline is_sh7751r_cpu(SH7750State * s)
+{
+ return (s->cpu->id & (SH_CPU_SH7751R));
+}
/**********************************************************************
I/O ports
**********************************************************************/
@@ -212,8 +219,17 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
switch (addr) {
case SH7750_BCR2_A7:
return s->bcr2;
+ case SH7750_BCR3_A7:
+ if(is_sh7751r_cpu(s)) {
+ return s->bcr3;
+ } else {
+ error_access("word read", addr);
+ assert(0);
+ }
case SH7750_FRQCR_A7:
return 0;
+ case SH7750_PCR_A7:
+ return s->pcr;
case SH7750_RFCR_A7:
fprintf(stderr,
"Read access to refresh count register, incrementing\n");
@@ -222,6 +238,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
return porta_lines(s);
case SH7750_PDTRB_A7:
return portb_lines(s);
+ case SH7750_RTCOR_A7:
+ case SH7750_RTCNT_A7:
+ case SH7750_RTCSR_A7:
+ ignore_access("word read", addr);
+ return 0;
case 0x1fd00000:
return s->icr;
default:
@@ -238,6 +259,12 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
case SH7750_BCR1_A7:
return s->bcr1;
case SH7750_BCR4_A7:
+ if(is_sh7751r_cpu(s)) {
+ return s->bcr4;
+ } else {
+ error_access("long read", addr);
+ assert(0);
+ }
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
@@ -274,9 +301,17 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
}
}
+#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
+ && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
+
+ if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
+ ignore_access("word write", addr);
+ return;
+ }
+
switch (addr) {
/* PRECHARGE ? XXXXX */
case SH7750_PRECHARGE0_A7:
@@ -301,8 +336,18 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
s->bcr2 = mem_value;
return;
case SH7750_BCR3_A7:
- case SH7750_RTCOR_A7:
+ if(is_sh7751r_cpu(s)) {
+ s->bcr3 = mem_value;
+ return;
+ } else {
+ error_access("word write", addr);
+ assert(0);
+ }
+ case SH7750_PCR_A7:
+ s->pcr = mem_value;
+ return;
case SH7750_RTCNT_A7:
+ case SH7750_RTCOR_A7:
case SH7750_RTCSR_A7:
ignore_access("word write", addr);
return;
@@ -349,6 +394,14 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
s->bcr1 = mem_value;
return;
case SH7750_BCR4_A7:
+ if(is_sh7751r_cpu(s)) {
+ s->bcr4 = mem_value;
+ return;
+ } else {
+ error_access("long write", addr);
+ assert(0);
+ }
+ return;
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
diff --git a/hw/sh7750_regnames.c b/hw/sh7750_regnames.c
index 51283c9..77993c1 100644
--- a/hw/sh7750_regnames.c
+++ b/hw/sh7750_regnames.c
@@ -79,6 +79,8 @@ static regname_t regnames[] = {
REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
+ REGNAME(SH7750_SDMR2_A7)
+ REGNAME(SH7750_SDMR3_A7)
REGNAME(SH7750_PRECHARGE0_A7)
REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
};
diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
index c8fb328..4ed471b 100644
--- a/hw/sh7750_regs.h
+++ b/hw/sh7750_regs.h
@@ -979,6 +979,17 @@
#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
+/* Synchronous DRAM mode registers - SDMR */
+#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
+#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
+#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
+
+#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
+#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
+#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
+
/*
* Direct Memory Access Controller (DMAC)
*/
--
1.5.6.5
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-05 11:49 [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support Jean-Christophe PLAGNIOL-VILLARD
@ 2008-12-14 11:37 ` Shin-ichiro KAWASAKI
2008-12-14 14:51 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 16+ messages in thread
From: Shin-ichiro KAWASAKI @ 2008-12-14 11:37 UTC (permalink / raw)
To: qemu-devel
Cc: Takashi Yoshii, Jean-Christophe PLAGNIOL-VILLARD, Nobuhiro Iwamatsu
Hi, Jean-san.
Thanks for your work. Please find my comments on the patch, in line.
# When I send mail to your address from my PC,
# mail delivery error happens as follows.
#
# ----- Transcript of session follows -----
# 451 4.4.1 reply: read error from mx1.ovh.net.
# 451 4.4.1 reply: read error from mx2.ovh.net.
# <your mail address >... Deferred: Connection timed out with mx2.ovh.net.
#
# How can I keep in touch with you?
Regards,
Shin-ichiro KAWASAKI
Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> Cc: Takashi Yoshii <yoshii.takashi@renesas.com>
> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
> ---
> hw/sh7750.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++--
> hw/sh7750_regnames.c | 2 +
> hw/sh7750_regs.h | 11 +++++++++
> 3 files changed, 69 insertions(+), 3 deletions(-)
>
> diff --git a/hw/sh7750.c b/hw/sh7750.c
> index 4ae90b1..78843f3 100644
> --- a/hw/sh7750.c
> +++ b/hw/sh7750.c
> @@ -42,8 +42,12 @@ typedef struct SH7750State {
> uint32_t periph_freq;
> /* SDRAM controller */
> uint32_t bcr1;
> - uint32_t bcr2;
> + uint16_t bcr2;
> + uint16_t bcr3;
> + uint32_t bcr4;
> uint16_t rfcr;
> + /* PCMCIA controller */
> + uint16_t pcr;
> /* IO ports */
> uint16_t gpioic;
> uint32_t pctra;
> @@ -67,7 +71,10 @@ typedef struct SH7750State {
> struct intc_desc intc;
> } SH7750State;
>
> -
> +static int inline is_sh7751r_cpu(SH7750State * s)
> +{
> + return (s->cpu->id & (SH_CPU_SH7751R));
> +}
> /**********************************************************************
> I/O ports
> **********************************************************************/
> @@ -212,8 +219,17 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> switch (addr) {
> case SH7750_BCR2_A7:
> return s->bcr2;
> + case SH7750_BCR3_A7:
> + if(is_sh7751r_cpu(s)) {
> + return s->bcr3;
> + } else {
> + error_access("word read", addr);
> + assert(0);
> + }
BCR3 exists not only for SH7751R, but also SH7750.
I think is_shh751r_cpu() check and error handling
should be removed to simplify the differcence.
> case SH7750_FRQCR_A7:
> return 0;
> + case SH7750_PCR_A7:
> + return s->pcr;
> case SH7750_RFCR_A7:
> fprintf(stderr,
> "Read access to refresh count register, incrementing\n");
> @@ -222,6 +238,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> return porta_lines(s);
> case SH7750_PDTRB_A7:
> return portb_lines(s);
> + case SH7750_RTCOR_A7:
> + case SH7750_RTCNT_A7:
> + case SH7750_RTCSR_A7:
> + ignore_access("word read", addr);
> + return 0;
> case 0x1fd00000:
> return s->icr;
> default:
> @@ -238,6 +259,12 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
> case SH7750_BCR1_A7:
> return s->bcr1;
> case SH7750_BCR4_A7:
> + if(is_sh7751r_cpu(s)) {
> + return s->bcr4;
> + } else {
> + error_access("long read", addr);
> + assert(0);
> + }
For BCR4, same as above.
> case SH7750_WCR1_A7:
> case SH7750_WCR2_A7:
> case SH7750_WCR3_A7:
> @@ -274,9 +301,17 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
> }
> }
>
> +#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
> + && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
> static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
> uint32_t mem_value)
> {
> +
> + if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
> + ignore_access("word write", addr);
> + return;
> + }
> +
SRMR2 and SDMR3 region overlaps with the PRECHARGE0/1 register.
If you introduce them, PRECHARGE0/1 register should be removed.
# U-Boot does not seem to touch these regions. Does it?
Compared to 'if' statement, 'switch-case' might be more easy to
understand, like as follows.
case SH7750_SDMR2 ... SH7750_SDMR2 + SDMR2_REGNB
> switch (addr) {
> /* PRECHARGE ? XXXXX */
> case SH7750_PRECHARGE0_A7:
> @@ -301,8 +336,18 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
> s->bcr2 = mem_value;
> return;
> case SH7750_BCR3_A7:
> - case SH7750_RTCOR_A7:
> + if(is_sh7751r_cpu(s)) {
> + s->bcr3 = mem_value;
> + return;
> + } else {
> + error_access("word write", addr);
> + assert(0);
> + }
Same as readw for BCR3.
> + case SH7750_PCR_A7:
> + s->pcr = mem_value;
> + return;
> case SH7750_RTCNT_A7:
> + case SH7750_RTCOR_A7:
> case SH7750_RTCSR_A7:
> ignore_access("word write", addr);
> return;
> @@ -349,6 +394,14 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
> s->bcr1 = mem_value;
> return;
> case SH7750_BCR4_A7:
> + if(is_sh7751r_cpu(s)) {
> + s->bcr4 = mem_value;
> + return;
> + } else {
> + error_access("long write", addr);
> + assert(0);
> + }
> + return;
> case SH7750_WCR1_A7:
> case SH7750_WCR2_A7:
> case SH7750_WCR3_A7:
> diff --git a/hw/sh7750_regnames.c b/hw/sh7750_regnames.c
> index 51283c9..77993c1 100644
> --- a/hw/sh7750_regnames.c
> +++ b/hw/sh7750_regnames.c
> @@ -79,6 +79,8 @@ static regname_t regnames[] = {
> REGNAME(SH7750_ICR_A7)
> REGNAME(SH7750_BCR3_A7)
> REGNAME(SH7750_BCR4_A7)
> + REGNAME(SH7750_SDMR2_A7)
> + REGNAME(SH7750_SDMR3_A7)
> REGNAME(SH7750_PRECHARGE0_A7)
> REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
> };
> diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
> index c8fb328..4ed471b 100644
> --- a/hw/sh7750_regs.h
> +++ b/hw/sh7750_regs.h
> @@ -979,6 +979,17 @@
>
> #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
>
> +/* Synchronous DRAM mode registers - SDMR */
> +#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
> +#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
> +#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
> +#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
> +
> +#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
> +#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
> +#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
> +#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
> +
> /*
> * Direct Memory Access Controller (DMAC)
> */
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-14 11:37 ` Shin-ichiro KAWASAKI
@ 2008-12-14 14:51 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-14 15:36 ` Shin-ichiro KAWASAKI
0 siblings, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-12-14 14:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Takashi Yoshii, Nobuhiro Iwamatsu
> >
> > -
> > +static int inline is_sh7751r_cpu(SH7750State * s)
> > +{
> > + return (s->cpu->id & (SH_CPU_SH7751R));
> > +}
> > /**********************************************************************
> > I/O ports
> > **********************************************************************/
> > @@ -212,8 +219,17 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> > switch (addr) {
> > case SH7750_BCR2_A7:
> > return s->bcr2;
> > + case SH7750_BCR3_A7:
> > + if(is_sh7751r_cpu(s)) {
> > + return s->bcr3;
> > + } else {
> > + error_access("word read", addr);
> > + assert(0);
> > + }
>
> BCR3 exists not only for SH7751R, but also SH7750.
> I think is_shh751r_cpu() check and error handling
> should be removed to simplify the differcence.
as write in the SH7751r datasheet
Bus Control Register 3 (BCR3) (SH7751R Only)
Bus Control Register 4 (BCR4) (SH7751R Only)
That's why I've add the check
>
> > case SH7750_FRQCR_A7:
> > return 0;
> > + case SH7750_PCR_A7:
> > + return s->pcr;
> > case SH7750_RFCR_A7:
> > fprintf(stderr,
> > "Read access to refresh count register, incrementing\n");
> > @@ -222,6 +238,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> > return porta_lines(s);
> > case SH7750_PDTRB_A7:
> > return portb_lines(s);
> > + case SH7750_RTCOR_A7:
> > + case SH7750_RTCNT_A7:
> > + case SH7750_RTCSR_A7:
> > + ignore_access("word read", addr);
> > + return 0;
> > case 0x1fd00000:
> > return s->icr;
> > default:
> > @@ -238,6 +259,12 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
> > case SH7750_BCR1_A7:
> > return s->bcr1;
> > case SH7750_BCR4_A7:
> > + if(is_sh7751r_cpu(s)) {
> > + return s->bcr4;
> > + } else {
> > + error_access("long read", addr);
> > + assert(0);
> > + }
>
> For BCR4, same as above.
>
> > case SH7750_WCR1_A7:
> > case SH7750_WCR2_A7:
> > case SH7750_WCR3_A7:
> > @@ -274,9 +301,17 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
> > }
> > }
> >
> > +#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
> > + && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
> > static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
> > uint32_t mem_value)
> > {
> > +
> > + if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
> > + ignore_access("word write", addr);
> > + return;
> > + }
> > +
>
> SRMR2 and SDMR3 region overlaps with the PRECHARGE0/1 register.
> If you introduce them, PRECHARGE0/1 register should be removed.
> # U-Boot does not seem to touch these regions. Does it?
IIRC no I'll check it
>
> Compared to 'if' statement, 'switch-case' might be more easy to
> understand, like as follows.
> case SH7750_SDMR2 ... SH7750_SDMR2 + SDMR2_REGNB
ok evenif it's a gcc only extension
Best Regards,
J.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-14 14:51 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2008-12-14 15:36 ` Shin-ichiro KAWASAKI
2008-12-14 16:37 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-14 17:28 ` Aurelien Jarno
0 siblings, 2 replies; 16+ messages in thread
From: Shin-ichiro KAWASAKI @ 2008-12-14 15:36 UTC (permalink / raw)
To: qemu-devel, Takashi Yoshii, Nobuhiro Iwamatsu
Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>
>>> -
>>> +static int inline is_sh7751r_cpu(SH7750State * s)
>>> +{
>>> + return (s->cpu->id & (SH_CPU_SH7751R));
>>> +}
>>> /**********************************************************************
>>> I/O ports
>>> **********************************************************************/
>>> @@ -212,8 +219,17 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
>>> switch (addr) {
>>> case SH7750_BCR2_A7:
>>> return s->bcr2;
>>> + case SH7750_BCR3_A7:
>>> + if(is_sh7751r_cpu(s)) {
>>> + return s->bcr3;
>>> + } else {
>>> + error_access("word read", addr);
>>> + assert(0);
>>> + }
>> BCR3 exists not only for SH7751R, but also SH7750.
>> I think is_shh751r_cpu() check and error handling
>> should be removed to simplify the differcence.
> as write in the SH7751r datasheet
>
> Bus Control Register 3 (BCR3) (SH7751R Only)
> Bus Control Register 4 (BCR4) (SH7751R Only)
>
> That's why I've add the check
I see. Your code is right, but let me add one more comment.
- SH7750 and SH7751 ... does not have BCR3 nor BCR4
- SH7750R and SH7751R ... have BCR3 and BCR4
So, to make it better, how about renaming "is_h7751r_cpu()"
into "has_bcr3_and_bcr4()"? It will be like this.
static int inline has_bcr3_and_bcr4(SH7750State * s)
{
return (s->cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R));
}
>> Compared to 'if' statement, 'switch-case' might be more easy to
>> understand, like as follows.
>> case SH7750_SDMR2 ... SH7750_SDMR2 + SDMR2_REGNB
> ok elvenif it's a gcc ony extension
Ah, gccism policy seems not clear in QEMU project.
This extension is used in many hw/*.c, so I guessed it
as a QEMU's usual implementation style.
I hope comments on it from main developers.
Regards,
Shin-ichiro KAWASAKI
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-14 15:36 ` Shin-ichiro KAWASAKI
@ 2008-12-14 16:37 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-14 17:24 ` Thiemo Seufer
2008-12-14 17:28 ` Aurelien Jarno
1 sibling, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-12-14 16:37 UTC (permalink / raw)
To: Shin-ichiro KAWASAKI; +Cc: Takashi Yoshii, Nobuhiro Iwamatsu, qemu-devel
On 00:36 Mon 15 Dec , Shin-ichiro KAWASAKI wrote:
> Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>> -
>>>> +static int inline is_sh7751r_cpu(SH7750State * s)
>>>> +{
>>>> + return (s->cpu->id & (SH_CPU_SH7751R));
>>>> +}
>>>> /**********************************************************************
>>>> I/O ports
>>>> **********************************************************************/
>>>> @@ -212,8 +219,17 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
>>>> switch (addr) {
>>>> case SH7750_BCR2_A7:
>>>> return s->bcr2;
>>>> + case SH7750_BCR3_A7:
>>>> + if(is_sh7751r_cpu(s)) {
>>>> + return s->bcr3;
>>>> + } else {
>>>> + error_access("word read", addr);
>>>> + assert(0);
>>>> + }
>>> BCR3 exists not only for SH7751R, but also SH7750.
>>> I think is_shh751r_cpu() check and error handling
>>> should be removed to simplify the differcence.
>> as write in the SH7751r datasheet
>>
>> Bus Control Register 3 (BCR3) (SH7751R Only)
>> Bus Control Register 4 (BCR4) (SH7751R Only)
>>
>> That's why I've add the check
>
> I see. Your code is right, but let me add one more comment.
>
> - SH7750 and SH7751 ... does not have BCR3 nor BCR4
> - SH7750R and SH7751R ... have BCR3 and BCR4
>
> So, to make it better, how about renaming "is_h7751r_cpu()"
> into "has_bcr3_and_bcr4()"? It will be like this.
>
> static int inline has_bcr3_and_bcr4(SH7750State * s)
> {
> return (s->cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R));
> }
I've download the SH7750 & SH7751 datasheet and yes as it's only availlable on
'R' cpu revision
I'll update as it
>
>
>>> Compared to 'if' statement, 'switch-case' might be more easy to
>>> understand, like as follows.
>>> case SH7750_SDMR2 ... SH7750_SDMR2 + SDMR2_REGNB
>> ok elvenif it's a gcc ony extension
>
> Ah, gccism policy seems not clear in QEMU project.
> This extension is used in many hw/*.c, so I guessed it
> as a QEMU's usual implementation style.
> I hope comments on it from main developers.
>
Yes it will be nice
Best Regards,
J.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-14 16:37 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2008-12-14 17:24 ` Thiemo Seufer
2008-12-15 0:37 ` Shin-ichiro KAWASAKI
0 siblings, 1 reply; 16+ messages in thread
From: Thiemo Seufer @ 2008-12-14 17:24 UTC (permalink / raw)
To: Shin-ichiro KAWASAKI, qemu-devel, Takashi Yoshii, Nobuhiro Iwamatsu
Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 00:36 Mon 15 Dec , Shin-ichiro KAWASAKI wrote:
> > Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>>> -
> >>>> +static int inline is_sh7751r_cpu(SH7750State * s)
> >>>> +{
> >>>> + return (s->cpu->id & (SH_CPU_SH7751R));
> >>>> +}
> >>>> /**********************************************************************
> >>>> I/O ports
> >>>> **********************************************************************/
> >>>> @@ -212,8 +219,17 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> >>>> switch (addr) {
> >>>> case SH7750_BCR2_A7:
> >>>> return s->bcr2;
> >>>> + case SH7750_BCR3_A7:
> >>>> + if(is_sh7751r_cpu(s)) {
> >>>> + return s->bcr3;
> >>>> + } else {
> >>>> + error_access("word read", addr);
> >>>> + assert(0);
> >>>> + }
> >>> BCR3 exists not only for SH7751R, but also SH7750.
> >>> I think is_shh751r_cpu() check and error handling
> >>> should be removed to simplify the differcence.
> >> as write in the SH7751r datasheet
> >>
> >> Bus Control Register 3 (BCR3) (SH7751R Only)
> >> Bus Control Register 4 (BCR4) (SH7751R Only)
> >>
> >> That's why I've add the check
> >
> > I see. Your code is right, but let me add one more comment.
> >
> > - SH7750 and SH7751 ... does not have BCR3 nor BCR4
> > - SH7750R and SH7751R ... have BCR3 and BCR4
> >
> > So, to make it better, how about renaming "is_h7751r_cpu()"
> > into "has_bcr3_and_bcr4()"? It will be like this.
> >
> > static int inline has_bcr3_and_bcr4(SH7750State * s)
> > {
> > return (s->cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R));
> > }
> I've download the SH7750 & SH7751 datasheet and yes as it's only availlable on
> 'R' cpu revision
>
> I'll update as it
> >
> >
> >>> Compared to 'if' statement, 'switch-case' might be more easy to
> >>> understand, like as follows.
> >>> case SH7750_SDMR2 ... SH7750_SDMR2 + SDMR2_REGNB
> >> ok elvenif it's a gcc ony extension
> >
> > Ah, gccism policy seems not clear in QEMU project.
> > This extension is used in many hw/*.c, so I guessed it
> > as a QEMU's usual implementation style.
> > I hope comments on it from main developers.
> >
> Yes it will be nice
I believe "no new gcc-isms" would be a good policy.
Thiemo
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-14 15:36 ` Shin-ichiro KAWASAKI
2008-12-14 16:37 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2008-12-14 17:28 ` Aurelien Jarno
2008-12-17 9:18 ` [Qemu-devel] [PATCH V2] SH7750/51: add register BCR3, BCR4, " Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 1 reply; 16+ messages in thread
From: Aurelien Jarno @ 2008-12-14 17:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Takashi Yoshii, Nobuhiro Iwamatsu
On Mon, Dec 15, 2008 at 12:36:21AM +0900, Shin-ichiro KAWASAKI wrote:
> Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>>
> >>>-
> >>>+static int inline is_sh7751r_cpu(SH7750State * s)
> >>>+{
> >>>+ return (s->cpu->id & (SH_CPU_SH7751R));
> >>>+}
> >>> /**********************************************************************
> >>> I/O ports
> >>> **********************************************************************/
> >>>@@ -212,8 +219,17 @@ static uint32_t sh7750_mem_readw(void *opaque,
> >>>target_phys_addr_t addr)
> >>> switch (addr) {
> >>> case SH7750_BCR2_A7:
> >>> return s->bcr2;
> >>>+ case SH7750_BCR3_A7:
> >>>+ if(is_sh7751r_cpu(s)) {
> >>>+ return s->bcr3;
> >>>+ } else {
> >>>+ error_access("word read", addr);
> >>>+ assert(0);
> >>>+ }
> >>BCR3 exists not only for SH7751R, but also SH7750.
> >>I think is_shh751r_cpu() check and error handling
> >>should be removed to simplify the differcence.
> >as write in the SH7751r datasheet
> >
> >Bus Control Register 3 (BCR3) (SH7751R Only)
> >Bus Control Register 4 (BCR4) (SH7751R Only)
> >
> >That's why I've add the check
>
> I see. Your code is right, but let me add one more comment.
>
> - SH7750 and SH7751 ... does not have BCR3 nor BCR4
> - SH7750R and SH7751R ... have BCR3 and BCR4
>
> So, to make it better, how about renaming "is_h7751r_cpu()"
> into "has_bcr3_and_bcr4()"? It will be like this.
>
> static int inline has_bcr3_and_bcr4(SH7750State * s)
> {
> return (s->cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R));
> }
Those functions are probably available on more CPU than those ones, or
in future CPU. I would suggest to use the new features field introduced
in revision 6013.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-14 17:24 ` Thiemo Seufer
@ 2008-12-15 0:37 ` Shin-ichiro KAWASAKI
2008-12-15 1:08 ` Thiemo Seufer
0 siblings, 1 reply; 16+ messages in thread
From: Shin-ichiro KAWASAKI @ 2008-12-15 0:37 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: Takashi Yoshii, Nobuhiro Iwamatsu, qemu-devel
Thiemo Seufer wrote:
> Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 00:36 Mon 15 Dec , Shin-ichiro KAWASAKI wrote:
>>> Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>>>> -
>>>>>> +static int inline is_sh7751r_cpu(SH7750State * s)
>>>>>> +{
>>>>>> + return (s->cpu->id & (SH_CPU_SH7751R));
>>>>>> +}
>>>>>> /**********************************************************************
>>>>>> I/O ports
>>>>>> **********************************************************************/
>>>>>> @@ -212,8 +219,17 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
>>>>>> switch (addr) {
>>>>>> case SH7750_BCR2_A7:
>>>>>> return s->bcr2;
>>>>>> + case SH7750_BCR3_A7:
>>>>>> + if(is_sh7751r_cpu(s)) {
>>>>>> + return s->bcr3;
>>>>>> + } else {
>>>>>> + error_access("word read", addr);
>>>>>> + assert(0);
>>>>>> + }
>>>>> BCR3 exists not only for SH7751R, but also SH7750.
>>>>> I think is_shh751r_cpu() check and error handling
>>>>> should be removed to simplify the differcence.
>>>> as write in the SH7751r datasheet
>>>>
>>>> Bus Control Register 3 (BCR3) (SH7751R Only)
>>>> Bus Control Register 4 (BCR4) (SH7751R Only)
>>>>
>>>> That's why I've add the check
>>> I see. Your code is right, but let me add one more comment.
>>>
>>> - SH7750 and SH7751 ... does not have BCR3 nor BCR4
>>> - SH7750R and SH7751R ... have BCR3 and BCR4
>>>
>>> So, to make it better, how about renaming "is_h7751r_cpu()"
>>> into "has_bcr3_and_bcr4()"? It will be like this.
>>>
>>> static int inline has_bcr3_and_bcr4(SH7750State * s)
>>> {
>>> return (s->cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R));
>>> }
>> I've download the SH7750 & SH7751 datasheet and yes as it's only availlable on
>> 'R' cpu revision
>>
>> I'll update as it
>>>
>>>>> Compared to 'if' statement, 'switch-case' might be more easy to
>>>>> understand, like as follows.
>>>>> case SH7750_SDMR2 ... SH7750_SDMR2 + SDMR2_REGNB
>>>> ok elvenif it's a gcc ony extension
>>> Ah, gccism policy seems not clear in QEMU project.
>>> This extension is used in many hw/*.c, so I guessed it
>>> as a QEMU's usual implementation style.
>>> I hope comments on it from main developers.
>>>
>> Yes it will be nice
>
> I believe "no new gcc-isms" would be a good policy.
Thank you. I'll follow it.
So, my suggestion about 'if' vs 'switch-case' is not appropriate.
Regards,
Shin-ichiro KAWASAKI
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-15 0:37 ` Shin-ichiro KAWASAKI
@ 2008-12-15 1:08 ` Thiemo Seufer
0 siblings, 0 replies; 16+ messages in thread
From: Thiemo Seufer @ 2008-12-15 1:08 UTC (permalink / raw)
To: Shin-ichiro KAWASAKI; +Cc: Takashi Yoshii, Nobuhiro Iwamatsu, qemu-devel
Shin-ichiro KAWASAKI wrote:
[snip]
>>>>>> Compared to 'if' statement, 'switch-case' might be more easy to
>>>>>> understand, like as follows.
>>>>>> case SH7750_SDMR2 ... SH7750_SDMR2 + SDMR2_REGNB
>>>>> ok elvenif it's a gcc ony extension
>>>> Ah, gccism policy seems not clear in QEMU project.
>>>> This extension is used in many hw/*.c, so I guessed it
>>>> as a QEMU's usual implementation style.
>>>> I hope comments on it from main developers.
>>>>
>>> Yes it will be nice
>>
>> I believe "no new gcc-isms" would be a good policy.
>
> Thank you. I'll follow it.
Be aware that this was only my personal opinion, and not well-stated at
that. From the recent discussion on IRC I believe we have now the rough
consensus:
"Use GCC extensions only when it improves the code significantly".
> So, my suggestion about 'if' vs 'switch-case' is not appropriate.
For the specific patch I believe the 'if' version is better. My opinion
is largely formed by the 'SH7750_SDMR2 + SDMR2_REGNB' term: If this
state doesn't deserve its own name, then it is probably not clear enough
to be used in a case statement.
Thiemo
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH V2] SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-14 17:28 ` Aurelien Jarno
@ 2008-12-17 9:18 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-18 15:51 ` Aurelien Jarno
0 siblings, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-12-17 9:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
hw/sh7750.c | 65 ++++++++++++++++++++++++++++++++++++++++-------
hw/sh7750_regnames.c | 4 +-
hw/sh7750_regs.h | 13 ++++++++-
target-sh4/cpu.h | 1 +
target-sh4/translate.c | 2 +
5 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 4d1a806..cee3a41 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -42,8 +42,12 @@ typedef struct SH7750State {
uint32_t periph_freq;
/* SDRAM controller */
uint32_t bcr1;
- uint32_t bcr2;
+ uint16_t bcr2;
+ uint16_t bcr3;
+ uint32_t bcr4;
uint16_t rfcr;
+ /* PCMCIA controller */
+ uint16_t pcr;
/* IO ports */
uint16_t gpioic;
uint32_t pctra;
@@ -66,7 +70,10 @@ typedef struct SH7750State {
struct intc_desc intc;
} SH7750State;
-
+static int inline has_bcr3_and_bcr4(SH7750State * s)
+{
+ return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
+}
/**********************************************************************
I/O ports
**********************************************************************/
@@ -211,8 +218,17 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
switch (addr) {
case SH7750_BCR2_A7:
return s->bcr2;
+ case SH7750_BCR3_A7:
+ if(has_bcr3_and_bcr4(s)) {
+ return s->bcr3;
+ } else {
+ error_access("word read", addr);
+ assert(0);
+ }
case SH7750_FRQCR_A7:
return 0;
+ case SH7750_PCR_A7:
+ return s->pcr;
case SH7750_RFCR_A7:
fprintf(stderr,
"Read access to refresh count register, incrementing\n");
@@ -221,6 +237,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
return porta_lines(s);
case SH7750_PDTRB_A7:
return portb_lines(s);
+ case SH7750_RTCOR_A7:
+ case SH7750_RTCNT_A7:
+ case SH7750_RTCSR_A7:
+ ignore_access("word read", addr);
+ return 0;
default:
error_access("word read", addr);
assert(0);
@@ -235,6 +256,12 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
case SH7750_BCR1_A7:
return s->bcr1;
case SH7750_BCR4_A7:
+ if(has_bcr3_and_bcr4(s)) {
+ return s->bcr4;
+ } else {
+ error_access("long read", addr);
+ assert(0);
+ }
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
@@ -271,19 +298,19 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
}
}
+#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
+ && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
- switch (addr) {
- /* PRECHARGE ? XXXXX */
- case SH7750_PRECHARGE0_A7:
- case SH7750_PRECHARGE1_A7:
+
+ if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
ignore_access("byte write", addr);
return;
- default:
- error_access("byte write", addr);
- assert(0);
}
+
+ error_access("byte write", addr);
+ assert(0);
}
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
@@ -298,8 +325,18 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
s->bcr2 = mem_value;
return;
case SH7750_BCR3_A7:
- case SH7750_RTCOR_A7:
+ if(has_bcr3_and_bcr4(s)) {
+ s->bcr3 = mem_value;
+ return;
+ } else {
+ error_access("word write", addr);
+ assert(0);
+ }
+ case SH7750_PCR_A7:
+ s->pcr = mem_value;
+ return;
case SH7750_RTCNT_A7:
+ case SH7750_RTCOR_A7:
case SH7750_RTCSR_A7:
ignore_access("word write", addr);
return;
@@ -343,6 +380,14 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
s->bcr1 = mem_value;
return;
case SH7750_BCR4_A7:
+ if(has_bcr3_and_bcr4(s)) {
+ s->bcr4 = mem_value;
+ return;
+ } else {
+ error_access("long write", addr);
+ assert(0);
+ }
+ return;
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
diff --git a/hw/sh7750_regnames.c b/hw/sh7750_regnames.c
index 51283c9..4928151 100644
--- a/hw/sh7750_regnames.c
+++ b/hw/sh7750_regnames.c
@@ -79,8 +79,8 @@ static regname_t regnames[] = {
REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
- REGNAME(SH7750_PRECHARGE0_A7)
- REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
+ REGNAME(SH7750_SDMR2_A7)
+ REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, 0}
};
const char *regname(uint32_t addr)
diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
index c8fb328..5a23a2c 100644
--- a/hw/sh7750_regs.h
+++ b/hw/sh7750_regs.h
@@ -979,6 +979,17 @@
#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
+/* Synchronous DRAM mode registers - SDMR */
+#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
+#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
+#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
+
+#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
+#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
+#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
+
/*
* Direct Memory Access Controller (DMAC)
*/
@@ -1262,7 +1273,5 @@
*/
#define SH7750_BCR3_A7 0x1f800050
#define SH7750_BCR4_A7 0x1e0a00f0
-#define SH7750_PRECHARGE0_A7 0x1f900088
-#define SH7750_PRECHARGE1_A7 0x1f940088
#endif
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 226417f..da6b81c 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -95,6 +95,7 @@ typedef struct tlb_t {
enum sh_features {
SH_FEATURE_SH4A = 1,
+ SH_FEATURE_BCR3_AND_BCR4 = 2,
};
typedef struct CPUSH4State {
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2d3981c..ed4a26b 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -217,12 +217,14 @@ static sh4_def_t sh4_defs[] = {
.pvr = 0x00050000,
.prr = 0x00000100,
.cvr = 0x00110000,
+ .features = SH_FEATURE_BCR3_AND_BCR4,
}, {
.name = "SH7751R",
.id = SH_CPU_SH7751R,
.pvr = 0x04050005,
.prr = 0x00000113,
.cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
+ .features = SH_FEATURE_BCR3_AND_BCR4,
}, {
.name = "SH7785",
.id = SH_CPU_SH7785,
--
1.5.6.5
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH V2] SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-17 9:18 ` [Qemu-devel] [PATCH V2] SH7750/51: add register BCR3, BCR4, " Jean-Christophe PLAGNIOL-VILLARD
@ 2008-12-18 15:51 ` Aurelien Jarno
2008-12-18 21:47 ` [U-Boot] [PATCH V3] " Jean-Christophe PLAGNIOL-VILLARD
2008-12-18 21:49 ` [Qemu-devel] " Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 2 replies; 16+ messages in thread
From: Aurelien Jarno @ 2008-12-18 15:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Jean-Christophe PLAGNIOL-VILLARD
On Wed, Dec 17, 2008 at 10:18:52AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> hw/sh7750.c | 65 ++++++++++++++++++++++++++++++++++++++++-------
> hw/sh7750_regnames.c | 4 +-
> hw/sh7750_regs.h | 13 ++++++++-
> target-sh4/cpu.h | 1 +
> target-sh4/translate.c | 2 +
> 5 files changed, 71 insertions(+), 14 deletions(-)
>
> diff --git a/hw/sh7750.c b/hw/sh7750.c
> index 4d1a806..cee3a41 100644
> --- a/hw/sh7750.c
> +++ b/hw/sh7750.c
> @@ -42,8 +42,12 @@ typedef struct SH7750State {
> uint32_t periph_freq;
> /* SDRAM controller */
> uint32_t bcr1;
> - uint32_t bcr2;
> + uint16_t bcr2;
> + uint16_t bcr3;
> + uint32_t bcr4;
> uint16_t rfcr;
> + /* PCMCIA controller */
> + uint16_t pcr;
> /* IO ports */
> uint16_t gpioic;
> uint32_t pctra;
> @@ -66,7 +70,10 @@ typedef struct SH7750State {
> struct intc_desc intc;
> } SH7750State;
>
> -
> +static int inline has_bcr3_and_bcr4(SH7750State * s)
> +{
> + return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
> +}
> /**********************************************************************
> I/O ports
> **********************************************************************/
> @@ -211,8 +218,17 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> switch (addr) {
> case SH7750_BCR2_A7:
> return s->bcr2;
> + case SH7750_BCR3_A7:
> + if(has_bcr3_and_bcr4(s)) {
> + return s->bcr3;
> + } else {
> + error_access("word read", addr);
> + assert(0);
Do we really want an assert() here? That means that the user from the
virtual machine can kill the machine.
What happens on a real CPU? I would guess an exception is triggered.
> + }
> case SH7750_FRQCR_A7:
> return 0;
> + case SH7750_PCR_A7:
> + return s->pcr;
> case SH7750_RFCR_A7:
> fprintf(stderr,
> "Read access to refresh count register, incrementing\n");
> @@ -221,6 +237,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> return porta_lines(s);
> case SH7750_PDTRB_A7:
> return portb_lines(s);
> + case SH7750_RTCOR_A7:
> + case SH7750_RTCNT_A7:
> + case SH7750_RTCSR_A7:
> + ignore_access("word read", addr);
> + return 0;
> default:
> error_access("word read", addr);
> assert(0);
> @@ -235,6 +256,12 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
> case SH7750_BCR1_A7:
> return s->bcr1;
> case SH7750_BCR4_A7:
> + if(has_bcr3_and_bcr4(s)) {
> + return s->bcr4;
> + } else {
> + error_access("long read", addr);
> + assert(0);
> + }
> case SH7750_WCR1_A7:
> case SH7750_WCR2_A7:
> case SH7750_WCR3_A7:
> @@ -271,19 +298,19 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
> }
> }
>
> +#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
> + && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
> static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
> uint32_t mem_value)
> {
> - switch (addr) {
> - /* PRECHARGE ? XXXXX */
> - case SH7750_PRECHARGE0_A7:
> - case SH7750_PRECHARGE1_A7:
> +
> + if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
> ignore_access("byte write", addr);
> return;
> - default:
> - error_access("byte write", addr);
> - assert(0);
> }
> +
> + error_access("byte write", addr);
> + assert(0);
> }
>
> static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
> @@ -298,8 +325,18 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
> s->bcr2 = mem_value;
> return;
> case SH7750_BCR3_A7:
> - case SH7750_RTCOR_A7:
> + if(has_bcr3_and_bcr4(s)) {
> + s->bcr3 = mem_value;
> + return;
> + } else {
> + error_access("word write", addr);
> + assert(0);
> + }
> + case SH7750_PCR_A7:
> + s->pcr = mem_value;
> + return;
> case SH7750_RTCNT_A7:
> + case SH7750_RTCOR_A7:
> case SH7750_RTCSR_A7:
> ignore_access("word write", addr);
> return;
> @@ -343,6 +380,14 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
> s->bcr1 = mem_value;
> return;
> case SH7750_BCR4_A7:
> + if(has_bcr3_and_bcr4(s)) {
> + s->bcr4 = mem_value;
> + return;
> + } else {
> + error_access("long write", addr);
> + assert(0);
> + }
> + return;
> case SH7750_WCR1_A7:
> case SH7750_WCR2_A7:
> case SH7750_WCR3_A7:
> diff --git a/hw/sh7750_regnames.c b/hw/sh7750_regnames.c
> index 51283c9..4928151 100644
> --- a/hw/sh7750_regnames.c
> +++ b/hw/sh7750_regnames.c
> @@ -79,8 +79,8 @@ static regname_t regnames[] = {
> REGNAME(SH7750_ICR_A7)
> REGNAME(SH7750_BCR3_A7)
> REGNAME(SH7750_BCR4_A7)
> - REGNAME(SH7750_PRECHARGE0_A7)
> - REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
> + REGNAME(SH7750_SDMR2_A7)
> + REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, 0}
> };
>
> const char *regname(uint32_t addr)
> diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
> index c8fb328..5a23a2c 100644
> --- a/hw/sh7750_regs.h
> +++ b/hw/sh7750_regs.h
> @@ -979,6 +979,17 @@
>
> #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
>
> +/* Synchronous DRAM mode registers - SDMR */
> +#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
> +#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
> +#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
> +#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
> +
> +#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
> +#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
> +#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
> +#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
> +
> /*
> * Direct Memory Access Controller (DMAC)
> */
> @@ -1262,7 +1273,5 @@
> */
> #define SH7750_BCR3_A7 0x1f800050
> #define SH7750_BCR4_A7 0x1e0a00f0
> -#define SH7750_PRECHARGE0_A7 0x1f900088
> -#define SH7750_PRECHARGE1_A7 0x1f940088
>
> #endif
> diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
> index 226417f..da6b81c 100644
> --- a/target-sh4/cpu.h
> +++ b/target-sh4/cpu.h
> @@ -95,6 +95,7 @@ typedef struct tlb_t {
>
> enum sh_features {
> SH_FEATURE_SH4A = 1,
> + SH_FEATURE_BCR3_AND_BCR4 = 2,
> };
>
> typedef struct CPUSH4State {
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 2d3981c..ed4a26b 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -217,12 +217,14 @@ static sh4_def_t sh4_defs[] = {
> .pvr = 0x00050000,
> .prr = 0x00000100,
> .cvr = 0x00110000,
> + .features = SH_FEATURE_BCR3_AND_BCR4,
> }, {
> .name = "SH7751R",
> .id = SH_CPU_SH7751R,
> .pvr = 0x04050005,
> .prr = 0x00000113,
> .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
> + .features = SH_FEATURE_BCR3_AND_BCR4,
> }, {
> .name = "SH7785",
> .id = SH_CPU_SH7785,
> --
> 1.5.6.5
>
>
>
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V3] SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-18 15:51 ` Aurelien Jarno
@ 2008-12-18 21:47 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-18 21:50 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-18 21:49 ` [Qemu-devel] " Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-12-18 21:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
Since V2:
As disscuss with Paul Mundt
Just bail out with a bogus access.
Trying to access bcr3 or bcr4 or non R revision is not something an address
error exception woulbe generated for
Best Regards,
J.
hw/sh7750.c | 52 ++++++++++++++++++++++++++++++++++++++---------
hw/sh7750_regnames.c | 4 +-
hw/sh7750_regs.h | 13 ++++++++++-
target-sh4/cpu.h | 1 +
target-sh4/translate.c | 2 +
5 files changed, 58 insertions(+), 14 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 4d1a806..4b0f669 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -42,8 +42,12 @@ typedef struct SH7750State {
uint32_t periph_freq;
/* SDRAM controller */
uint32_t bcr1;
- uint32_t bcr2;
+ uint16_t bcr2;
+ uint16_t bcr3;
+ uint32_t bcr4;
uint16_t rfcr;
+ /* PCMCIA controller */
+ uint16_t pcr;
/* IO ports */
uint16_t gpioic;
uint32_t pctra;
@@ -66,7 +70,10 @@ typedef struct SH7750State {
struct intc_desc intc;
} SH7750State;
-
+static int inline has_bcr3_and_bcr4(SH7750State * s)
+{
+ return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
+}
/**********************************************************************
I/O ports
**********************************************************************/
@@ -211,8 +218,14 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
switch (addr) {
case SH7750_BCR2_A7:
return s->bcr2;
+ case SH7750_BCR3_A7:
+ if(!has_bcr3_and_bcr4(s))
+ error_access("word read", addr);
+ return s->bcr3;
case SH7750_FRQCR_A7:
return 0;
+ case SH7750_PCR_A7:
+ return s->pcr;
case SH7750_RFCR_A7:
fprintf(stderr,
"Read access to refresh count register, incrementing\n");
@@ -221,6 +234,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
return porta_lines(s);
case SH7750_PDTRB_A7:
return portb_lines(s);
+ case SH7750_RTCOR_A7:
+ case SH7750_RTCNT_A7:
+ case SH7750_RTCSR_A7:
+ ignore_access("word read", addr);
+ return 0;
default:
error_access("word read", addr);
assert(0);
@@ -235,6 +253,9 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
case SH7750_BCR1_A7:
return s->bcr1;
case SH7750_BCR4_A7:
+ if(has_bcr3_and_bcr4(s))
+ error_access("long read", addr);
+ return s->bcr4;
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
@@ -271,19 +292,19 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
}
}
+#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
+ && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
- switch (addr) {
- /* PRECHARGE ? XXXXX */
- case SH7750_PRECHARGE0_A7:
- case SH7750_PRECHARGE1_A7:
+
+ if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
ignore_access("byte write", addr);
return;
- default:
- error_access("byte write", addr);
- assert(0);
}
+
+ error_access("byte write", addr);
+ assert(0);
}
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
@@ -298,8 +319,15 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
s->bcr2 = mem_value;
return;
case SH7750_BCR3_A7:
- case SH7750_RTCOR_A7:
+ if(has_bcr3_and_bcr4(s))
+ error_access("word write", addr);
+ s->bcr3 = mem_value;
+ return;
+ case SH7750_PCR_A7:
+ s->pcr = mem_value;
+ return;
case SH7750_RTCNT_A7:
+ case SH7750_RTCOR_A7:
case SH7750_RTCSR_A7:
ignore_access("word write", addr);
return;
@@ -343,6 +371,10 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
s->bcr1 = mem_value;
return;
case SH7750_BCR4_A7:
+ if(has_bcr3_and_bcr4(s))
+ error_access("long write", addr);
+ s->bcr4 = mem_value;
+ return;
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
diff --git a/hw/sh7750_regnames.c b/hw/sh7750_regnames.c
index 51283c9..4928151 100644
--- a/hw/sh7750_regnames.c
+++ b/hw/sh7750_regnames.c
@@ -79,8 +79,8 @@ static regname_t regnames[] = {
REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
- REGNAME(SH7750_PRECHARGE0_A7)
- REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
+ REGNAME(SH7750_SDMR2_A7)
+ REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, 0}
};
const char *regname(uint32_t addr)
diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
index c8fb328..5a23a2c 100644
--- a/hw/sh7750_regs.h
+++ b/hw/sh7750_regs.h
@@ -979,6 +979,17 @@
#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
+/* Synchronous DRAM mode registers - SDMR */
+#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
+#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
+#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
+
+#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
+#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
+#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
+
/*
* Direct Memory Access Controller (DMAC)
*/
@@ -1262,7 +1273,5 @@
*/
#define SH7750_BCR3_A7 0x1f800050
#define SH7750_BCR4_A7 0x1e0a00f0
-#define SH7750_PRECHARGE0_A7 0x1f900088
-#define SH7750_PRECHARGE1_A7 0x1f940088
#endif
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 226417f..da6b81c 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -95,6 +95,7 @@ typedef struct tlb_t {
enum sh_features {
SH_FEATURE_SH4A = 1,
+ SH_FEATURE_BCR3_AND_BCR4 = 2,
};
typedef struct CPUSH4State {
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2d3981c..ed4a26b 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -217,12 +217,14 @@ static sh4_def_t sh4_defs[] = {
.pvr = 0x00050000,
.prr = 0x00000100,
.cvr = 0x00110000,
+ .features = SH_FEATURE_BCR3_AND_BCR4,
}, {
.name = "SH7751R",
.id = SH_CPU_SH7751R,
.pvr = 0x04050005,
.prr = 0x00000113,
.cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
+ .features = SH_FEATURE_BCR3_AND_BCR4,
}, {
.name = "SH7785",
.id = SH_CPU_SH7785,
--
1.5.6.5
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH V3] SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-18 15:51 ` Aurelien Jarno
2008-12-18 21:47 ` [U-Boot] [PATCH V3] " Jean-Christophe PLAGNIOL-VILLARD
@ 2008-12-18 21:49 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-18 23:33 ` [Qemu-devel] [PATCH V4] " Jean-Christophe PLAGNIOL-VILLARD
1 sibling, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-12-18 21:49 UTC (permalink / raw)
To: qemu-devel; +Cc: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
Since V2:
As disscuss with Paul Mundt
Just bail out with a bogus access.
Trying to access bcr3 or bcr4 or non R revision is not something an address
error exception woulbe generated for
Best Regards,
J.
hw/sh7750.c | 52 ++++++++++++++++++++++++++++++++++++++---------
hw/sh7750_regnames.c | 4 +-
hw/sh7750_regs.h | 13 ++++++++++-
target-sh4/cpu.h | 1 +
target-sh4/translate.c | 2 +
5 files changed, 58 insertions(+), 14 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 4d1a806..4b0f669 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -42,8 +42,12 @@ typedef struct SH7750State {
uint32_t periph_freq;
/* SDRAM controller */
uint32_t bcr1;
- uint32_t bcr2;
+ uint16_t bcr2;
+ uint16_t bcr3;
+ uint32_t bcr4;
uint16_t rfcr;
+ /* PCMCIA controller */
+ uint16_t pcr;
/* IO ports */
uint16_t gpioic;
uint32_t pctra;
@@ -66,7 +70,10 @@ typedef struct SH7750State {
struct intc_desc intc;
} SH7750State;
-
+static int inline has_bcr3_and_bcr4(SH7750State * s)
+{
+ return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
+}
/**********************************************************************
I/O ports
**********************************************************************/
@@ -211,8 +218,14 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
switch (addr) {
case SH7750_BCR2_A7:
return s->bcr2;
+ case SH7750_BCR3_A7:
+ if(!has_bcr3_and_bcr4(s))
+ error_access("word read", addr);
+ return s->bcr3;
case SH7750_FRQCR_A7:
return 0;
+ case SH7750_PCR_A7:
+ return s->pcr;
case SH7750_RFCR_A7:
fprintf(stderr,
"Read access to refresh count register, incrementing\n");
@@ -221,6 +234,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
return porta_lines(s);
case SH7750_PDTRB_A7:
return portb_lines(s);
+ case SH7750_RTCOR_A7:
+ case SH7750_RTCNT_A7:
+ case SH7750_RTCSR_A7:
+ ignore_access("word read", addr);
+ return 0;
default:
error_access("word read", addr);
assert(0);
@@ -235,6 +253,9 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
case SH7750_BCR1_A7:
return s->bcr1;
case SH7750_BCR4_A7:
+ if(has_bcr3_and_bcr4(s))
+ error_access("long read", addr);
+ return s->bcr4;
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
@@ -271,19 +292,19 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
}
}
+#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
+ && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
- switch (addr) {
- /* PRECHARGE ? XXXXX */
- case SH7750_PRECHARGE0_A7:
- case SH7750_PRECHARGE1_A7:
+
+ if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
ignore_access("byte write", addr);
return;
- default:
- error_access("byte write", addr);
- assert(0);
}
+
+ error_access("byte write", addr);
+ assert(0);
}
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
@@ -298,8 +319,15 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
s->bcr2 = mem_value;
return;
case SH7750_BCR3_A7:
- case SH7750_RTCOR_A7:
+ if(has_bcr3_and_bcr4(s))
+ error_access("word write", addr);
+ s->bcr3 = mem_value;
+ return;
+ case SH7750_PCR_A7:
+ s->pcr = mem_value;
+ return;
case SH7750_RTCNT_A7:
+ case SH7750_RTCOR_A7:
case SH7750_RTCSR_A7:
ignore_access("word write", addr);
return;
@@ -343,6 +371,10 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
s->bcr1 = mem_value;
return;
case SH7750_BCR4_A7:
+ if(has_bcr3_and_bcr4(s))
+ error_access("long write", addr);
+ s->bcr4 = mem_value;
+ return;
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
diff --git a/hw/sh7750_regnames.c b/hw/sh7750_regnames.c
index 51283c9..4928151 100644
--- a/hw/sh7750_regnames.c
+++ b/hw/sh7750_regnames.c
@@ -79,8 +79,8 @@ static regname_t regnames[] = {
REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
- REGNAME(SH7750_PRECHARGE0_A7)
- REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
+ REGNAME(SH7750_SDMR2_A7)
+ REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, 0}
};
const char *regname(uint32_t addr)
diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
index c8fb328..5a23a2c 100644
--- a/hw/sh7750_regs.h
+++ b/hw/sh7750_regs.h
@@ -979,6 +979,17 @@
#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
+/* Synchronous DRAM mode registers - SDMR */
+#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
+#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
+#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
+
+#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
+#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
+#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
+
/*
* Direct Memory Access Controller (DMAC)
*/
@@ -1262,7 +1273,5 @@
*/
#define SH7750_BCR3_A7 0x1f800050
#define SH7750_BCR4_A7 0x1e0a00f0
-#define SH7750_PRECHARGE0_A7 0x1f900088
-#define SH7750_PRECHARGE1_A7 0x1f940088
#endif
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 226417f..da6b81c 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -95,6 +95,7 @@ typedef struct tlb_t {
enum sh_features {
SH_FEATURE_SH4A = 1,
+ SH_FEATURE_BCR3_AND_BCR4 = 2,
};
typedef struct CPUSH4State {
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2d3981c..ed4a26b 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -217,12 +217,14 @@ static sh4_def_t sh4_defs[] = {
.pvr = 0x00050000,
.prr = 0x00000100,
.cvr = 0x00110000,
+ .features = SH_FEATURE_BCR3_AND_BCR4,
}, {
.name = "SH7751R",
.id = SH_CPU_SH7751R,
.pvr = 0x04050005,
.prr = 0x00000113,
.cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
+ .features = SH_FEATURE_BCR3_AND_BCR4,
}, {
.name = "SH7785",
.id = SH_CPU_SH7785,
--
1.5.6.5
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V3] SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-18 21:47 ` [U-Boot] [PATCH V3] " Jean-Christophe PLAGNIOL-VILLARD
@ 2008-12-18 21:50 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-12-18 21:50 UTC (permalink / raw)
To: u-boot
On 22:47 Thu 18 Dec , Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
Sorry send to the wrong ML
Best Regards,
J.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH V4] SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-18 21:49 ` [Qemu-devel] " Jean-Christophe PLAGNIOL-VILLARD
@ 2008-12-18 23:33 ` Jean-Christophe PLAGNIOL-VILLARD
2009-02-07 15:19 ` Aurelien Jarno
0 siblings, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2008-12-18 23:33 UTC (permalink / raw)
To: qemu-devel; +Cc: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
Since V2:
As disscuss with Paul Mundt
Just bail out with a bogus access.
Trying to access bcr3 or bcr4 or non R revision is not something an address
error exception woulbe generated for
Since V3:
Fix forgeedt invert of the bcr3/4 check
Best Regards,
J.
hw/sh7750.c | 52 ++++++++++++++++++++++++++++++++++++++---------
hw/sh7750_regnames.c | 4 +-
hw/sh7750_regs.h | 13 ++++++++++-
target-sh4/cpu.h | 1 +
target-sh4/translate.c | 2 +
5 files changed, 58 insertions(+), 14 deletions(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 4d1a806..e09fcda 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -42,8 +42,12 @@ typedef struct SH7750State {
uint32_t periph_freq;
/* SDRAM controller */
uint32_t bcr1;
- uint32_t bcr2;
+ uint16_t bcr2;
+ uint16_t bcr3;
+ uint32_t bcr4;
uint16_t rfcr;
+ /* PCMCIA controller */
+ uint16_t pcr;
/* IO ports */
uint16_t gpioic;
uint32_t pctra;
@@ -66,7 +70,10 @@ typedef struct SH7750State {
struct intc_desc intc;
} SH7750State;
-
+static int inline has_bcr3_and_bcr4(SH7750State * s)
+{
+ return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
+}
/**********************************************************************
I/O ports
**********************************************************************/
@@ -211,8 +218,14 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
switch (addr) {
case SH7750_BCR2_A7:
return s->bcr2;
+ case SH7750_BCR3_A7:
+ if(!has_bcr3_and_bcr4(s))
+ error_access("word read", addr);
+ return s->bcr3;
case SH7750_FRQCR_A7:
return 0;
+ case SH7750_PCR_A7:
+ return s->pcr;
case SH7750_RFCR_A7:
fprintf(stderr,
"Read access to refresh count register, incrementing\n");
@@ -221,6 +234,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
return porta_lines(s);
case SH7750_PDTRB_A7:
return portb_lines(s);
+ case SH7750_RTCOR_A7:
+ case SH7750_RTCNT_A7:
+ case SH7750_RTCSR_A7:
+ ignore_access("word read", addr);
+ return 0;
default:
error_access("word read", addr);
assert(0);
@@ -235,6 +253,9 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
case SH7750_BCR1_A7:
return s->bcr1;
case SH7750_BCR4_A7:
+ if(!has_bcr3_and_bcr4(s))
+ error_access("long read", addr);
+ return s->bcr4;
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
@@ -271,19 +292,19 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
}
}
+#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
+ && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
- switch (addr) {
- /* PRECHARGE ? XXXXX */
- case SH7750_PRECHARGE0_A7:
- case SH7750_PRECHARGE1_A7:
+
+ if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
ignore_access("byte write", addr);
return;
- default:
- error_access("byte write", addr);
- assert(0);
}
+
+ error_access("byte write", addr);
+ assert(0);
}
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
@@ -298,8 +319,15 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
s->bcr2 = mem_value;
return;
case SH7750_BCR3_A7:
- case SH7750_RTCOR_A7:
+ if(!has_bcr3_and_bcr4(s))
+ error_access("word write", addr);
+ s->bcr3 = mem_value;
+ return;
+ case SH7750_PCR_A7:
+ s->pcr = mem_value;
+ return;
case SH7750_RTCNT_A7:
+ case SH7750_RTCOR_A7:
case SH7750_RTCSR_A7:
ignore_access("word write", addr);
return;
@@ -343,6 +371,10 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
s->bcr1 = mem_value;
return;
case SH7750_BCR4_A7:
+ if(!has_bcr3_and_bcr4(s))
+ error_access("long write", addr);
+ s->bcr4 = mem_value;
+ return;
case SH7750_WCR1_A7:
case SH7750_WCR2_A7:
case SH7750_WCR3_A7:
diff --git a/hw/sh7750_regnames.c b/hw/sh7750_regnames.c
index 51283c9..4928151 100644
--- a/hw/sh7750_regnames.c
+++ b/hw/sh7750_regnames.c
@@ -79,8 +79,8 @@ static regname_t regnames[] = {
REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7)
- REGNAME(SH7750_PRECHARGE0_A7)
- REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
+ REGNAME(SH7750_SDMR2_A7)
+ REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, 0}
};
const char *regname(uint32_t addr)
diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
index c8fb328..5a23a2c 100644
--- a/hw/sh7750_regs.h
+++ b/hw/sh7750_regs.h
@@ -979,6 +979,17 @@
#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
+/* Synchronous DRAM mode registers - SDMR */
+#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
+#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
+#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
+
+#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
+#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
+#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
+#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
+
/*
* Direct Memory Access Controller (DMAC)
*/
@@ -1262,7 +1273,5 @@
*/
#define SH7750_BCR3_A7 0x1f800050
#define SH7750_BCR4_A7 0x1e0a00f0
-#define SH7750_PRECHARGE0_A7 0x1f900088
-#define SH7750_PRECHARGE1_A7 0x1f940088
#endif
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 226417f..da6b81c 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -95,6 +95,7 @@ typedef struct tlb_t {
enum sh_features {
SH_FEATURE_SH4A = 1,
+ SH_FEATURE_BCR3_AND_BCR4 = 2,
};
typedef struct CPUSH4State {
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2d3981c..ed4a26b 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -217,12 +217,14 @@ static sh4_def_t sh4_defs[] = {
.pvr = 0x00050000,
.prr = 0x00000100,
.cvr = 0x00110000,
+ .features = SH_FEATURE_BCR3_AND_BCR4,
}, {
.name = "SH7751R",
.id = SH_CPU_SH7751R,
.pvr = 0x04050005,
.prr = 0x00000113,
.cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
+ .features = SH_FEATURE_BCR3_AND_BCR4,
}, {
.name = "SH7785",
.id = SH_CPU_SH7785,
--
1.5.6.5
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH V4] SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
2008-12-18 23:33 ` [Qemu-devel] [PATCH V4] " Jean-Christophe PLAGNIOL-VILLARD
@ 2009-02-07 15:19 ` Aurelien Jarno
0 siblings, 0 replies; 16+ messages in thread
From: Aurelien Jarno @ 2009-02-07 15:19 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: qemu-devel
On Fri, Dec 19, 2008 at 12:33:14AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> Since V2:
> As disscuss with Paul Mundt
> Just bail out with a bogus access.
> Trying to access bcr3 or bcr4 or non R revision is not something an address
> error exception woulbe generated for
>
> Since V3:
> Fix forgeedt invert of the bcr3/4 check
>
> Best Regards,
> J.
> hw/sh7750.c | 52 ++++++++++++++++++++++++++++++++++++++---------
> hw/sh7750_regnames.c | 4 +-
> hw/sh7750_regs.h | 13 ++++++++++-
> target-sh4/cpu.h | 1 +
> target-sh4/translate.c | 2 +
> 5 files changed, 58 insertions(+), 14 deletions(-)
Thanks, applied.
> diff --git a/hw/sh7750.c b/hw/sh7750.c
> index 4d1a806..e09fcda 100644
> --- a/hw/sh7750.c
> +++ b/hw/sh7750.c
> @@ -42,8 +42,12 @@ typedef struct SH7750State {
> uint32_t periph_freq;
> /* SDRAM controller */
> uint32_t bcr1;
> - uint32_t bcr2;
> + uint16_t bcr2;
> + uint16_t bcr3;
> + uint32_t bcr4;
> uint16_t rfcr;
> + /* PCMCIA controller */
> + uint16_t pcr;
> /* IO ports */
> uint16_t gpioic;
> uint32_t pctra;
> @@ -66,7 +70,10 @@ typedef struct SH7750State {
> struct intc_desc intc;
> } SH7750State;
>
> -
> +static int inline has_bcr3_and_bcr4(SH7750State * s)
> +{
> + return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
> +}
> /**********************************************************************
> I/O ports
> **********************************************************************/
> @@ -211,8 +218,14 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> switch (addr) {
> case SH7750_BCR2_A7:
> return s->bcr2;
> + case SH7750_BCR3_A7:
> + if(!has_bcr3_and_bcr4(s))
> + error_access("word read", addr);
> + return s->bcr3;
> case SH7750_FRQCR_A7:
> return 0;
> + case SH7750_PCR_A7:
> + return s->pcr;
> case SH7750_RFCR_A7:
> fprintf(stderr,
> "Read access to refresh count register, incrementing\n");
> @@ -221,6 +234,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> return porta_lines(s);
> case SH7750_PDTRB_A7:
> return portb_lines(s);
> + case SH7750_RTCOR_A7:
> + case SH7750_RTCNT_A7:
> + case SH7750_RTCSR_A7:
> + ignore_access("word read", addr);
> + return 0;
> default:
> error_access("word read", addr);
> assert(0);
> @@ -235,6 +253,9 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
> case SH7750_BCR1_A7:
> return s->bcr1;
> case SH7750_BCR4_A7:
> + if(!has_bcr3_and_bcr4(s))
> + error_access("long read", addr);
> + return s->bcr4;
> case SH7750_WCR1_A7:
> case SH7750_WCR2_A7:
> case SH7750_WCR3_A7:
> @@ -271,19 +292,19 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
> }
> }
>
> +#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
> + && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
> static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
> uint32_t mem_value)
> {
> - switch (addr) {
> - /* PRECHARGE ? XXXXX */
> - case SH7750_PRECHARGE0_A7:
> - case SH7750_PRECHARGE1_A7:
> +
> + if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
> ignore_access("byte write", addr);
> return;
> - default:
> - error_access("byte write", addr);
> - assert(0);
> }
> +
> + error_access("byte write", addr);
> + assert(0);
> }
>
> static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
> @@ -298,8 +319,15 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
> s->bcr2 = mem_value;
> return;
> case SH7750_BCR3_A7:
> - case SH7750_RTCOR_A7:
> + if(!has_bcr3_and_bcr4(s))
> + error_access("word write", addr);
> + s->bcr3 = mem_value;
> + return;
> + case SH7750_PCR_A7:
> + s->pcr = mem_value;
> + return;
> case SH7750_RTCNT_A7:
> + case SH7750_RTCOR_A7:
> case SH7750_RTCSR_A7:
> ignore_access("word write", addr);
> return;
> @@ -343,6 +371,10 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
> s->bcr1 = mem_value;
> return;
> case SH7750_BCR4_A7:
> + if(!has_bcr3_and_bcr4(s))
> + error_access("long write", addr);
> + s->bcr4 = mem_value;
> + return;
> case SH7750_WCR1_A7:
> case SH7750_WCR2_A7:
> case SH7750_WCR3_A7:
> diff --git a/hw/sh7750_regnames.c b/hw/sh7750_regnames.c
> index 51283c9..4928151 100644
> --- a/hw/sh7750_regnames.c
> +++ b/hw/sh7750_regnames.c
> @@ -79,8 +79,8 @@ static regname_t regnames[] = {
> REGNAME(SH7750_ICR_A7)
> REGNAME(SH7750_BCR3_A7)
> REGNAME(SH7750_BCR4_A7)
> - REGNAME(SH7750_PRECHARGE0_A7)
> - REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
> + REGNAME(SH7750_SDMR2_A7)
> + REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, 0}
> };
>
> const char *regname(uint32_t addr)
> diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
> index c8fb328..5a23a2c 100644
> --- a/hw/sh7750_regs.h
> +++ b/hw/sh7750_regs.h
> @@ -979,6 +979,17 @@
>
> #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
>
> +/* Synchronous DRAM mode registers - SDMR */
> +#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
> +#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
> +#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
> +#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
> +
> +#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
> +#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
> +#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
> +#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
> +
> /*
> * Direct Memory Access Controller (DMAC)
> */
> @@ -1262,7 +1273,5 @@
> */
> #define SH7750_BCR3_A7 0x1f800050
> #define SH7750_BCR4_A7 0x1e0a00f0
> -#define SH7750_PRECHARGE0_A7 0x1f900088
> -#define SH7750_PRECHARGE1_A7 0x1f940088
>
> #endif
> diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
> index 226417f..da6b81c 100644
> --- a/target-sh4/cpu.h
> +++ b/target-sh4/cpu.h
> @@ -95,6 +95,7 @@ typedef struct tlb_t {
>
> enum sh_features {
> SH_FEATURE_SH4A = 1,
> + SH_FEATURE_BCR3_AND_BCR4 = 2,
> };
>
> typedef struct CPUSH4State {
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 2d3981c..ed4a26b 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -217,12 +217,14 @@ static sh4_def_t sh4_defs[] = {
> .pvr = 0x00050000,
> .prr = 0x00000100,
> .cvr = 0x00110000,
> + .features = SH_FEATURE_BCR3_AND_BCR4,
> }, {
> .name = "SH7751R",
> .id = SH_CPU_SH7751R,
> .pvr = 0x04050005,
> .prr = 0x00000113,
> .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
> + .features = SH_FEATURE_BCR3_AND_BCR4,
> }, {
> .name = "SH7785",
> .id = SH_CPU_SH7785,
> --
> 1.5.6.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 16+ messages in thread
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2008-12-05 11:49 [Qemu-devel] [PATCH] SH7750/51: add register BCR3, NCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support Jean-Christophe PLAGNIOL-VILLARD
2008-12-14 11:37 ` Shin-ichiro KAWASAKI
2008-12-14 14:51 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-14 15:36 ` Shin-ichiro KAWASAKI
2008-12-14 16:37 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-14 17:24 ` Thiemo Seufer
2008-12-15 0:37 ` Shin-ichiro KAWASAKI
2008-12-15 1:08 ` Thiemo Seufer
2008-12-14 17:28 ` Aurelien Jarno
2008-12-17 9:18 ` [Qemu-devel] [PATCH V2] SH7750/51: add register BCR3, BCR4, " Jean-Christophe PLAGNIOL-VILLARD
2008-12-18 15:51 ` Aurelien Jarno
2008-12-18 21:47 ` [U-Boot] [PATCH V3] " Jean-Christophe PLAGNIOL-VILLARD
2008-12-18 21:50 ` Jean-Christophe PLAGNIOL-VILLARD
2008-12-18 21:49 ` [Qemu-devel] " Jean-Christophe PLAGNIOL-VILLARD
2008-12-18 23:33 ` [Qemu-devel] [PATCH V4] " Jean-Christophe PLAGNIOL-VILLARD
2009-02-07 15:19 ` Aurelien Jarno
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