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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: <linuxppc-dev@ozlabs.org>
Cc: Kumar Gala <kumar.gala@freescale.com>
Subject: [PATCH 10/16] powerpc/mm: Remove flush_HPTE()
Date: Mon, 15 Dec 2008 16:44:51 +1100	[thread overview]
Message-ID: <20081215054549.686BEDDFB1@ozlabs.org> (raw)
In-Reply-To: <1229319836.100184.344640589620.qpush@grosgo>

The function flush_HPTE() is used in only one place, the implementation
of DEBUG_PAGEALLOC on ppc32.

It's actually a dup of flush_tlb_page() though it's -slightly- more
efficient on hash based processors. We remove it and replace it by
a direct call to the hash flush code on those processors and to
flush_tlb_page() for everybody else.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

 arch/powerpc/mm/mmu_decl.h   |   17 -----------------
 arch/powerpc/mm/pgtable_32.c |    6 +++++-
 2 files changed, 5 insertions(+), 18 deletions(-)

--- linux-work.orig/arch/powerpc/mm/mmu_decl.h	2008-12-10 17:01:18.000000000 +1100
+++ linux-work/arch/powerpc/mm/mmu_decl.h	2008-12-10 17:01:35.000000000 +1100
@@ -58,17 +58,14 @@ extern phys_addr_t lowmem_end_addr;
  * architectures.  -- Dan
  */
 #if defined(CONFIG_8xx)
-#define flush_HPTE(X, va, pg)	_tlbie(va, 0 /* 8xx doesn't care about PID */)
 #define MMU_init_hw()		do { } while(0)
 #define mmu_mapin_ram()		(0UL)
 
 #elif defined(CONFIG_4xx)
-#define flush_HPTE(pid, va, pg)	_tlbie(va, pid)
 extern void MMU_init_hw(void);
 extern unsigned long mmu_mapin_ram(void);
 
 #elif defined(CONFIG_FSL_BOOKE)
-#define flush_HPTE(pid, va, pg)	_tlbie(va, pid)
 extern void MMU_init_hw(void);
 extern unsigned long mmu_mapin_ram(void);
 extern void adjust_total_lowmem(void);
@@ -77,18 +74,4 @@ extern void adjust_total_lowmem(void);
 /* anything 32-bit except 4xx or 8xx */
 extern void MMU_init_hw(void);
 extern unsigned long mmu_mapin_ram(void);
-
-/* Be careful....this needs to be updated if we ever encounter 603 SMPs,
- * which includes all new 82xx processors.  We need tlbie/tlbsync here
- * in that case (I think). -- Dan.
- */
-static inline void flush_HPTE(unsigned context, unsigned long va,
-			      unsigned long pdval)
-{
-	if ((Hash != 0) &&
-	    mmu_has_feature(MMU_FTR_HPTE_TABLE))
-		flush_hash_pages(0, va, pdval, 1);
-	else
-		_tlbie(va);
-}
 #endif
Index: linux-work/arch/powerpc/mm/pgtable_32.c
===================================================================
--- linux-work.orig/arch/powerpc/mm/pgtable_32.c	2008-12-10 17:01:49.000000000 +1100
+++ linux-work/arch/powerpc/mm/pgtable_32.c	2008-12-10 17:04:36.000000000 +1100
@@ -342,7 +342,11 @@ static int __change_page_attr(struct pag
 		return -EINVAL;
 	set_pte_at(&init_mm, address, kpte, mk_pte(page, prot));
 	wmb();
-	flush_HPTE(0, address, pmd_val(*kpmd));
+#ifdef CONFIG_PPC_STD_MMU
+	flush_hash_pages(0, address, pmd_val(*kpmd), 1);
+#else
+	flush_tlb_page(NULL, address);
+#endif
 	pte_unmap(kpte);
 
 	return 0;

  parent reply	other threads:[~2008-12-15  5:44 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-12-15  5:43 [PATCH 0/16] powerpc: Preliminary work to enable SMP BookE (v2) Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 1/16] powerpc: Fix bogus cache flushing on all 40x and BookE processors v2 Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 2/16] powerpc: Fix asm EMIT_BUG_ENTRY with !CONFIG_BUG Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 3/16] powerpc/4xx: Extended DCR support v2 Benjamin Herrenschmidt
2008-12-17 17:33   ` Josh Boyer
2008-12-15  5:44 ` [PATCH 4/16] powerpc/fsl-booke: Fix problem with _tlbil_va Benjamin Herrenschmidt
2008-12-15  6:59   ` Stephen Rothwell
2008-12-15  7:04     ` Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 5/16] powerpc/mm: Add local_flush_tlb_mm() to SW loaded TLB implementations Benjamin Herrenschmidt
2008-12-15 20:30   ` Kumar Gala
2008-12-15  5:44 ` [PATCH 6/16] powerpc/mm: Split mmu_context handling v3 Benjamin Herrenschmidt
2008-12-15 15:43   ` Arnd Bergmann
2008-12-15 20:20     ` Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 7/16] powerpc/mm: Rework context management for CPUs with no hash table v2 Benjamin Herrenschmidt
2008-12-17 21:30   ` Kumar Gala
2008-12-15  5:44 ` [PATCH 8/16] powerpc/mm: Rename tlb_32.c and tlb_64.c to tlb_hash32.c and tlb_hash64.c Benjamin Herrenschmidt
2008-12-15 20:36   ` Kumar Gala
2008-12-15 20:46     ` Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 9/16] powerpc/mm: Introduce MMU features v2 Benjamin Herrenschmidt
2008-12-15  5:44 ` Benjamin Herrenschmidt [this message]
2008-12-15  5:44 ` [PATCH 11/16] powerpc/mm: Add SMP support to no-hash TLB handling v3 Benjamin Herrenschmidt
2008-12-15 20:19   ` Kumar Gala
2008-12-15 20:46     ` Benjamin Herrenschmidt
2008-12-15 20:57       ` Kumar Gala
2008-12-15 21:03         ` Benjamin Herrenschmidt
2008-12-15 21:10           ` Kumar Gala
2008-12-15 21:18             ` Benjamin Herrenschmidt
2008-12-15 22:19               ` Kumar Gala
2008-12-15 23:31                 ` Benjamin Herrenschmidt
2008-12-15  5:45 ` [PATCH 12/16] powerpc/mm: Split low level tlb invalidate for nohash processors Benjamin Herrenschmidt
2008-12-15  5:45 ` [PATCH 13/16] powerpc/44x: No need to mask MSR:CE, ME or DE in _tlbil_va on 440 Benjamin Herrenschmidt
2008-12-15 12:25   ` [PATCH 13/16] powerpc/44x: No need to mask MSR:CE,ME " Josh Boyer
2008-12-15  5:45 ` [PATCH 14/16] powerpc/mm: Runtime allocation of mmu context maps for nohash CPUs v2 Benjamin Herrenschmidt
2008-12-17 21:21   ` Kumar Gala
2008-12-15  5:45 ` [PATCH 15/16] powerpc/mm: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED Benjamin Herrenschmidt
2008-12-15 20:54   ` Kumar Gala
2008-12-15 21:01     ` Benjamin Herrenschmidt
2008-12-15 21:08       ` Kumar Gala
2008-12-15 21:03     ` Michael Ellerman
2008-12-15 21:05       ` Benjamin Herrenschmidt
2008-12-15  5:45 ` [PATCH 16/16] powerpc/44x: 44x TLB doesn't need "Guarded" set for all pages Benjamin Herrenschmidt

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