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From: Kumar Gala <kumar.gala@freescale.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH 14/16] powerpc/mm: Runtime allocation of mmu context maps for nohash CPUs v2
Date: Wed, 17 Dec 2008 15:21:39 -0600	[thread overview]
Message-ID: <F5CAFB16-FADD-4DB6-B18D-ED3AA02AE992@freescale.com> (raw)
In-Reply-To: <20081215054607.5DF5DDDFB7@ozlabs.org>

> /*
>  * Initialize the context management stuff.
> @@ -326,13 +344,56 @@ void __init mmu_context_init(void)
> 	init_mm.context.active = NR_CPUS;
>
> 	/*
> +	 *   The MPC8xx has only 16 contexts.  We rotate through them on  
> each
> +	 * task switch.  A better way would be to keep track of tasks that
> +	 * own contexts, and implement an LRU usage.  That way very active
> +	 * tasks don't always have to pay the TLB reload overhead.  The
> +	 * kernel pages are mapped shared, so the kernel can run on behalf
> +	 * of any task that makes a kernel entry.  Shared does not mean they
> +	 * are not protected, just that the ASID comparison is not  
> performed.
> +	 *      -- Dan
> +	 *
> +	 * The IBM4xx has 256 contexts, so we can just rotate through these
> +	 * as a way of "switching" contexts.  If the TID of the TLB is zero,
> +	 * the PID/TID comparison is disabled, so we can use a TID of zero
> +	 * to represent all kernel pages as shared among all contexts.

can expand the comment of change it to say all other nonhash parts  
40x, 4xx, fsl-booke right now have 256 contexts.

>
> +	 * 	-- Dan
> +	 */
> +	if (mmu_has_feature(MMU_FTR_TYPE_8xx)) {
> +		first_context = 0;
> +		last_context = 15;
> +	} else {
> +		first_context = 1;
> +		last_context = 255;
> +	}

  reply	other threads:[~2008-12-17 21:21 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-12-15  5:43 [PATCH 0/16] powerpc: Preliminary work to enable SMP BookE (v2) Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 1/16] powerpc: Fix bogus cache flushing on all 40x and BookE processors v2 Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 2/16] powerpc: Fix asm EMIT_BUG_ENTRY with !CONFIG_BUG Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 3/16] powerpc/4xx: Extended DCR support v2 Benjamin Herrenschmidt
2008-12-17 17:33   ` Josh Boyer
2008-12-15  5:44 ` [PATCH 4/16] powerpc/fsl-booke: Fix problem with _tlbil_va Benjamin Herrenschmidt
2008-12-15  6:59   ` Stephen Rothwell
2008-12-15  7:04     ` Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 5/16] powerpc/mm: Add local_flush_tlb_mm() to SW loaded TLB implementations Benjamin Herrenschmidt
2008-12-15 20:30   ` Kumar Gala
2008-12-15  5:44 ` [PATCH 6/16] powerpc/mm: Split mmu_context handling v3 Benjamin Herrenschmidt
2008-12-15 15:43   ` Arnd Bergmann
2008-12-15 20:20     ` Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 7/16] powerpc/mm: Rework context management for CPUs with no hash table v2 Benjamin Herrenschmidt
2008-12-17 21:30   ` Kumar Gala
2008-12-15  5:44 ` [PATCH 8/16] powerpc/mm: Rename tlb_32.c and tlb_64.c to tlb_hash32.c and tlb_hash64.c Benjamin Herrenschmidt
2008-12-15 20:36   ` Kumar Gala
2008-12-15 20:46     ` Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 9/16] powerpc/mm: Introduce MMU features v2 Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 10/16] powerpc/mm: Remove flush_HPTE() Benjamin Herrenschmidt
2008-12-15  5:44 ` [PATCH 11/16] powerpc/mm: Add SMP support to no-hash TLB handling v3 Benjamin Herrenschmidt
2008-12-15 20:19   ` Kumar Gala
2008-12-15 20:46     ` Benjamin Herrenschmidt
2008-12-15 20:57       ` Kumar Gala
2008-12-15 21:03         ` Benjamin Herrenschmidt
2008-12-15 21:10           ` Kumar Gala
2008-12-15 21:18             ` Benjamin Herrenschmidt
2008-12-15 22:19               ` Kumar Gala
2008-12-15 23:31                 ` Benjamin Herrenschmidt
2008-12-15  5:45 ` [PATCH 12/16] powerpc/mm: Split low level tlb invalidate for nohash processors Benjamin Herrenschmidt
2008-12-15  5:45 ` [PATCH 13/16] powerpc/44x: No need to mask MSR:CE, ME or DE in _tlbil_va on 440 Benjamin Herrenschmidt
2008-12-15 12:25   ` [PATCH 13/16] powerpc/44x: No need to mask MSR:CE,ME " Josh Boyer
2008-12-15  5:45 ` [PATCH 14/16] powerpc/mm: Runtime allocation of mmu context maps for nohash CPUs v2 Benjamin Herrenschmidt
2008-12-17 21:21   ` Kumar Gala [this message]
2008-12-15  5:45 ` [PATCH 15/16] powerpc/mm: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED Benjamin Herrenschmidt
2008-12-15 20:54   ` Kumar Gala
2008-12-15 21:01     ` Benjamin Herrenschmidt
2008-12-15 21:08       ` Kumar Gala
2008-12-15 21:03     ` Michael Ellerman
2008-12-15 21:05       ` Benjamin Herrenschmidt
2008-12-15  5:45 ` [PATCH 16/16] powerpc/44x: 44x TLB doesn't need "Guarded" set for all pages Benjamin Herrenschmidt

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