Re: [PATCH 1/4] onenand init: Rename board-n800-flash.c to gpmc-onenand.c

Re: [PATCH 1/4] onenand init: Rename board-n800-flash.c to gpmc-onenand.c

[vimal singh]

'gpmc-onenand.c' is still confusing name. This is not going to used in
all boards anyway.


On Thu, Apr 30, 2009 at 3:20 AM, Tony Lindgren <tony@atomide.com> wrote:
> Rename board-n800-flash.c to gpmc-onenand.c.
>
> Signed-off-by: Tony Lindgren <tony@atommide.com>
> ---
>  arch/arm/mach-omap2/Makefile           |    4 ++--
>  arch/arm/mach-omap2/gpmc-onenand.c     |    0
>  2 files changed, 2 insertions(+), 2 deletions(-)
>  rename arch/arm/mach-omap2/{board-n800-flash.c => gpmc-onenand.c} (100%)
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 76acefa..9127a94 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -55,14 +55,14 @@ obj-$(CONFIG_MACH_OMAP_LDP)         += board-ldp.o \
>  obj-$(CONFIG_MACH_OMAP_APOLLON)                += board-apollon.o \
>                                           board-apollon-mmc.o  \
>                                           board-apollon-keys.o
> -obj-$(CONFIG_MACH_NOKIA_N800)          += board-n800.o board-n800-flash.o \
> +obj-$(CONFIG_MACH_NOKIA_N800)          += board-n800.o gpmc-onenand.o \
>                                           board-n800-mmc.o board-n800-bt.o \
>                                           board-n800-usb.o \
>                                           board-n800-dsp.o \
>                                           board-n800-camera.o
>  obj-$(CONFIG_MACH_NOKIA_N810)          += board-n810.o
>  obj-$(CONFIG_MACH_NOKIA_RX51)          += board-rx51.o \
> -                                          board-n800-flash.o \
> +                                          gpmc-onenand.o \
>                                           board-rx51-flash.o \
>                                           board-rx51-sdram.o \
>                                           board-rx51-video.o \
> diff --git a/arch/arm/mach-omap2/board-n800-flash.c
b/arch/arm/mach-omap2/gpmc-onenand.c
> similarity index 100%
> rename from arch/arm/mach-omap2/board-n800-flash.c
> rename to arch/arm/mach-omap2/gpmc-onenand.c
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>



-- 
---
Regards,
\/ | |\/| /-\ |_

Re: [PATCH 1/4] onenand init: Rename board-n800-flash.c to gpmc-onenand.c

[Tony Lindgren]

* vimal singh <vimalsingh@ti.com> [090429 23:33]:
> 'gpmc-onenand.c' is still confusing name. This is not going to used in
> all boards anyway.

Why do you think this cannot be used for all boards?

The GPMC timings are totally based on the onenand chip features.

Regards,

Tony

 
> On Thu, Apr 30, 2009 at 3:20 AM, Tony Lindgren <tony@atomide.com> wrote:
> > Rename board-n800-flash.c to gpmc-onenand.c.
> >
> > Signed-off-by: Tony Lindgren <tony@atommide.com>
> > ---
> >  arch/arm/mach-omap2/Makefile           |    4 ++--
> >  arch/arm/mach-omap2/gpmc-onenand.c     |    0
> >  2 files changed, 2 insertions(+), 2 deletions(-)
> >  rename arch/arm/mach-omap2/{board-n800-flash.c => gpmc-onenand.c} (100%)
> >
> > diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> > index 76acefa..9127a94 100644
> > --- a/arch/arm/mach-omap2/Makefile
> > +++ b/arch/arm/mach-omap2/Makefile
> > @@ -55,14 +55,14 @@ obj-$(CONFIG_MACH_OMAP_LDP)         += board-ldp.o \
> >  obj-$(CONFIG_MACH_OMAP_APOLLON)                += board-apollon.o \
> >                                           board-apollon-mmc.o  \
> >                                           board-apollon-keys.o
> > -obj-$(CONFIG_MACH_NOKIA_N800)          += board-n800.o board-n800-flash.o \
> > +obj-$(CONFIG_MACH_NOKIA_N800)          += board-n800.o gpmc-onenand.o \
> >                                           board-n800-mmc.o board-n800-bt.o \
> >                                           board-n800-usb.o \
> >                                           board-n800-dsp.o \
> >                                           board-n800-camera.o
> >  obj-$(CONFIG_MACH_NOKIA_N810)          += board-n810.o
> >  obj-$(CONFIG_MACH_NOKIA_RX51)          += board-rx51.o \
> > -                                          board-n800-flash.o \
> > +                                          gpmc-onenand.o \
> >                                           board-rx51-flash.o \
> >                                           board-rx51-sdram.o \
> >                                           board-rx51-video.o \
> > diff --git a/arch/arm/mach-omap2/board-n800-flash.c
> b/arch/arm/mach-omap2/gpmc-onenand.c
> > similarity index 100%
> > rename from arch/arm/mach-omap2/board-n800-flash.c
> > rename to arch/arm/mach-omap2/gpmc-onenand.c
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >
> 
> 
> 
> -- 
> ---
> Regards,
> \/ | |\/| /-\ |_
> 
> 

[PATCH] onenand_init: Allow disabling sync read and write based on flags (Re: [PATCH 1/4] onenand init: Rename board-n800-flash.c to gpmc-onenand.c)

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 541 bytes --]

* Tony Lindgren <tony@atomide.com> [090430 07:06]:
> * vimal singh <vimalsingh@ti.com> [090429 23:33]:
> > 'gpmc-onenand.c' is still confusing name. This is not going to used in
> > all boards anyway.
> 
> Why do you think this cannot be used for all boards?
> 
> The GPMC timings are totally based on the onenand chip features.

And these two patches make omap3430sdp to work with the gpmc-onenand
code. Sync mode does not work, but it seems like it was never enabled
for sdp anyways.

Similar patch should work for other boards too.

Tony

[-- Attachment #2: onenand-add-flags.patch --]
[-- Type: text/x-diff, Size: 5227 bytes --]

>From 75b228c97d5df66ef5eba81bb6a25627e6e77941 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Thu, 30 Apr 2009 11:43:19 -0700
Subject: [PATCH] onenand_init: Allow disabling sync read and write based on flags

Allow disabling sync read and write based on flags

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index fc79183..e9ace8c 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -85,20 +85,24 @@ static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
 	writew(value, addr);
 }
 
-static void set_onenand_cfg(void __iomem *onenand_base, int latency,
-			    int sync_write, int hf)
+static void set_onenand_cfg(struct omap_onenand_platform_data *cfg,
+				void __iomem *onenand_base,
+				int latency, int hf) 
 {
 	u32 reg;
 
 	reg = omap2_onenand_readw(onenand_base + ONENAND_REG_SYS_CFG1);
 	reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
 	reg |=	(latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
-		ONENAND_SYS_CFG1_SYNC_READ |
 		ONENAND_SYS_CFG1_BL_16;
-	if (sync_write)
-		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
+	if (cfg->flags & ONENAND_DIS_SYNC_READ)
+		reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
 	else
+		reg |= ONENAND_SYS_CFG1_SYNC_READ;
+	if (cfg->flags & ONENAND_DIS_SYNC_WRITE)
 		reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
+	else
+		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
 	if (hf)
 		reg |= ONENAND_SYS_CFG1_HF;
 	else
@@ -106,8 +110,9 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
 	omap2_onenand_writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 }
 
-static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
-				       int freq)
+static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+					void __iomem *onenand_base,
+					int freq)
 {
 	struct gpmc_timings t;
 	const int t_cer  = 15;
@@ -119,6 +124,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
 	int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
 	int err, ticks_cez, sync_write = 0, first_time = 0, hf = 0;
+	int cs = cfg->cs;
 	u32 reg;
 
 	if (!freq) {
@@ -160,7 +166,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		t_ach   = 6;
 		t_aavdh = 6;
 		t_rdyo  = 9;
-		if (cpu_is_omap34xx())
+		if (cpu_is_omap34xx() && !(cfg->flags & ONENAND_DIS_SYNC_WRITE))
 			sync_write = 1;
 		break;
 	case 66:
@@ -171,7 +177,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		t_ach   = 6;
 		t_aavdh = 6;
 		t_rdyo  = 11;
-		if (cpu_is_omap34xx())
+		if (cpu_is_omap34xx() && !(cfg->flags & ONENAND_DIS_SYNC_WRITE))
 			sync_write = 1;
 		break;
 	default:
@@ -198,7 +204,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		latency = 4;
 
 	if (first_time)
-		set_onenand_cfg(onenand_base, latency, sync_write, hf);
+		set_onenand_cfg(cfg, onenand_base, latency, hf);
 
 	if (div == 1) {
 		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -244,7 +250,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		     ticks_cez);
 
 	/* Write */
-	if (sync_write) {
+	if (!(cfg->flags & ONENAND_DIS_SYNC_WRITE)) {
 		t.adv_wr_off = t.adv_rd_off;
 		t.we_on  = 0;
 		t.we_off = t.cs_rd_off;
@@ -272,7 +278,8 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
 			  GPMC_CONFIG1_WRAPBURST_SUPP |
 			  GPMC_CONFIG1_READMULTIPLE_SUPP |
-			  GPMC_CONFIG1_READTYPE_SYNC |
+			  ((cfg->flags & ONENAND_DIS_SYNC_READ) ? 0 :
+				GPMC_CONFIG1_READTYPE_SYNC) |
 			  (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
 			  (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
 			  GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
@@ -288,7 +295,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 	if (err)
 		return err;
 
-	set_onenand_cfg(onenand_base, latency, sync_write, hf);
+	set_onenand_cfg(cfg, onenand_base, latency, hf);
 
 	return 0;
 }
@@ -298,7 +305,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
 	struct device *dev = &gpmc_onenand_device.dev;
 
 	/* Set sync timings in GPMC */
-	if (omap2_onenand_set_sync_mode(gpmc_onenand_data->cs, onenand_base,
+	if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
 			freq) < 0) {
 		dev_err(dev, "Unable to set synchronous mode\n");
 		return -EINVAL;
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h
index 2a391fa..562b2a9 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/mach/onenand.h
@@ -14,6 +14,9 @@
 
 #ifndef __ASM_ARCH_OMAP_ONENAND_H__
 
+#define ONENAND_DIS_SYNC_READ	(1 << 0)
+#define ONENAND_DIS_SYNC_WRITE	(1 << 1)
+
 struct omap_onenand_platform_data {
 	int			cs;
 	int			gpio_irq;
@@ -21,6 +24,7 @@ struct omap_onenand_platform_data {
 	int			nr_parts;
 	int                     (*onenand_setup)(void __iomem *, int freq);
 	int			dma_channel;
+	u8			flags;
 };
 
 int omap2_onenand_rephase(void);

[PATCH] onenand init: Convert omap3430sdp to use gpmc-onenand (Re: [PATCH] onenand_init: Allow disabling sync read and write based on flags (Re: [PATCH 1/4] onenand init: Rename board-n800-flash.c to gpmc-onenand.c))

[Tony Lindgren]

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[-- Attachment #2: convert-3430sdp.patch --]
[-- Type: text/x-diff, Size: 2383 bytes --]

>From b5c750c4d3f523df5759c3b7cbda321d056f7045 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Thu, 30 Apr 2009 11:46:41 -0700
Subject: [PATCH] onenand init: Convert omap3430sdp to use gpmc-onenand

Convert omap3430sdp to use gpmc-onenand. Note that sync mode
does not seem to work for some reason, so disable it with flags.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/board-3430sdp-flash.c b/arch/arm/mach-omap2/board-3430sdp-flash.c
index f0e25a4..ab3fc1a 100644
--- a/arch/arm/mach-omap2/board-3430sdp-flash.c
+++ b/arch/arm/mach-omap2/board-3430sdp-flash.c
@@ -103,8 +103,6 @@ static struct platform_device sdp_nor_device = {
 	.resource	= &sdp_nor_resource,
 };
 
-static int sdp_onenand_setup(void __iomem *, int freq);
-
 static struct mtd_partition sdp_onenand_partitions[] = {
 	{
 		.name		= "X-Loader-OneNAND",
@@ -138,30 +136,10 @@ static struct mtd_partition sdp_onenand_partitions[] = {
 static struct omap_onenand_platform_data sdp_onenand_data = {
 	.parts		= sdp_onenand_partitions,
 	.nr_parts	= ARRAY_SIZE(sdp_onenand_partitions),
-	.onenand_setup	= sdp_onenand_setup,
 	.dma_channel	= -1,	/* disable DMA in OMAP OneNAND driver */
+	.flags		= ONENAND_DIS_SYNC_READ | ONENAND_DIS_SYNC_WRITE,
 };
 
-static struct platform_device sdp_onenand_device = {
-	.name		= "omap2-onenand",
-	.id		= -1,
-	.dev = {
-		.platform_data = &sdp_onenand_data,
-	},
-};
-
-/*
- * sdp_onenand_setup - The function configures the onenand flash.
- * @onenand_base: Onenand base address
- *
- * @return int:	Currently always returning zero.
- */
-static int sdp_onenand_setup(void __iomem *onenand_base, int freq)
-{
-	/* Onenand setup does nothing at present */
-	return 0;
-}
-
 static struct mtd_partition sdp_nand_partitions[] = {
 	/* All the partition sizes are listed in terms of NAND block size */
 	{
@@ -262,7 +240,7 @@ void __init sdp3430_flash_init(void)
 		} else {
 			ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 			if ((ret & 0x3F) == (ONENAND_MAP >> 24))
-			onenandcs = cs;
+				onenandcs = cs;
 		}
 		cs++;
 	}
@@ -284,7 +262,6 @@ void __init sdp3430_flash_init(void)
 
 	if (onenandcs < GPMC_CS_NUM) {
 		sdp_onenand_data.cs = onenandcs;
-		if (platform_device_register(&sdp_onenand_device) < 0)
-			printk(KERN_ERR "Unable to register OneNAND device\n");
+		gpmc_onenand_init(&sdp_onenand_data);
 	}
 }

Re: [PATCH] onenand_init: Allow disabling sync read and write based on flags, v2 (Re: [PATCH 1/4] onenand init: Rename board-n800-flash.c to gpmc-onenand.c)

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 730 bytes --]

* Tony Lindgren <tony@atomide.com> [090430 11:56]:
> * Tony Lindgren <tony@atomide.com> [090430 07:06]:
> > * vimal singh <vimalsingh@ti.com> [090429 23:33]:
> > > 'gpmc-onenand.c' is still confusing name. This is not going to used in
> > > all boards anyway.
> > 
> > Why do you think this cannot be used for all boards?
> > 
> > The GPMC timings are totally based on the onenand chip features.
> 
> And these two patches make omap3430sdp to work with the gpmc-onenand
> code. Sync mode does not work, but it seems like it was never enabled
> for sdp anyways.
> 
> Similar patch should work for other boards too.

Setting the sync_write depends on flags and processor, not just flags.
Here's a fixed version of this patch.

Tony

[-- Attachment #2: onenand-add-flags-v2.patch --]
[-- Type: text/x-diff, Size: 5183 bytes --]

>From 7c9f55ca7dcf9768fee7128fab5f5cf3cacc1e21 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Thu, 30 Apr 2009 11:43:19 -0700
Subject: [PATCH] onenand_init: Allow disabling sync read and write based on flags, v2

Allow disabling sync read and write based on flags

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index fc79183..4583c79 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -86,15 +86,18 @@ static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
 }
 
 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
-			    int sync_write, int hf)
+				int sync_read, int sync_write, int hf)
 {
 	u32 reg;
 
 	reg = omap2_onenand_readw(onenand_base + ONENAND_REG_SYS_CFG1);
 	reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
 	reg |=	(latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
-		ONENAND_SYS_CFG1_SYNC_READ |
 		ONENAND_SYS_CFG1_BL_16;
+	if (sync_read)
+		reg |= ONENAND_SYS_CFG1_SYNC_READ;
+	else
+		reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
 	if (sync_write)
 		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
 	else
@@ -106,8 +109,9 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
 	omap2_onenand_writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 }
 
-static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
-				       int freq)
+static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+					void __iomem *onenand_base,
+					int freq)
 {
 	struct gpmc_timings t;
 	const int t_cer  = 15;
@@ -118,9 +122,19 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 	const int t_wph  = 30;
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
 	int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
-	int err, ticks_cez, sync_write = 0, first_time = 0, hf = 0;
+	int err, ticks_cez, sync_read, sync_write, first_time = 0, hf = 0;
+	int cs = cfg->cs;
 	u32 reg;
 
+	if (cfg->flags & ONENAND_DIS_SYNC_READ)
+		sync_read = 0;
+	else
+		sync_read = 1;
+	if (cpu_is_omap24xx() || (cfg->flags & ONENAND_DIS_SYNC_WRITE))
+		sync_write = 0;
+	else
+		sync_write = 1;
+
 	if (!freq) {
 		/* Very first call freq is not known */
 		err = omap2_onenand_set_async_mode(cs, onenand_base);
@@ -160,8 +174,6 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		t_ach   = 6;
 		t_aavdh = 6;
 		t_rdyo  = 9;
-		if (cpu_is_omap34xx())
-			sync_write = 1;
 		break;
 	case 66:
 		min_gpmc_clk_period = 15; /* 66 MHz */
@@ -171,8 +183,6 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		t_ach   = 6;
 		t_aavdh = 6;
 		t_rdyo  = 11;
-		if (cpu_is_omap34xx())
-			sync_write = 1;
 		break;
 	default:
 		min_gpmc_clk_period = 18; /* 54 MHz */
@@ -182,6 +192,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		t_ach   = 9;
 		t_aavdh = 7;
 		t_rdyo  = 15;
+		sync_write = 0;
 		break;
 	}
 
@@ -198,7 +209,8 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		latency = 4;
 
 	if (first_time)
-		set_onenand_cfg(onenand_base, latency, sync_write, hf);
+		set_onenand_cfg(onenand_base, latency,
+					sync_read, sync_write, hf);
 
 	if (div == 1) {
 		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -272,7 +284,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
 			  GPMC_CONFIG1_WRAPBURST_SUPP |
 			  GPMC_CONFIG1_READMULTIPLE_SUPP |
-			  GPMC_CONFIG1_READTYPE_SYNC |
+			  (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
 			  (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
 			  (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
 			  GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
@@ -288,7 +300,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 	if (err)
 		return err;
 
-	set_onenand_cfg(onenand_base, latency, sync_write, hf);
+	set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
 
 	return 0;
 }
@@ -298,7 +310,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
 	struct device *dev = &gpmc_onenand_device.dev;
 
 	/* Set sync timings in GPMC */
-	if (omap2_onenand_set_sync_mode(gpmc_onenand_data->cs, onenand_base,
+	if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
 			freq) < 0) {
 		dev_err(dev, "Unable to set synchronous mode\n");
 		return -EINVAL;
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h
index 2a391fa..562b2a9 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/mach/onenand.h
@@ -14,6 +14,9 @@
 
 #ifndef __ASM_ARCH_OMAP_ONENAND_H__
 
+#define ONENAND_DIS_SYNC_READ	(1 << 0)
+#define ONENAND_DIS_SYNC_WRITE	(1 << 1)
+
 struct omap_onenand_platform_data {
 	int			cs;
 	int			gpio_irq;
@@ -21,6 +24,7 @@ struct omap_onenand_platform_data {
 	int			nr_parts;
 	int                     (*onenand_setup)(void __iomem *, int freq);
 	int			dma_channel;
+	u8			flags;
 };
 
 int omap2_onenand_rephase(void);

Re: [PATCH] onenand_init: Allow disabling sync read and write based on flags (Re: [PATCH 1/4] onenand init: Rename board-n800-flash.c to gpmc-onenand.c)

[Adrian Hunter]

Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [090430 07:06]:
>> * vimal singh <vimalsingh@ti.com> [090429 23:33]:
>>> 'gpmc-onenand.c' is still confusing name. This is not going to used in
>>> all boards anyway.
>> Why do you think this cannot be used for all boards?
>>
>> The GPMC timings are totally based on the onenand chip features.
> 
> And these two patches make omap3430sdp to work with the gpmc-onenand
> code. Sync mode does not work, but it seems like it was never enabled
> for sdp anyways.
> 
> Similar patch should work for other boards too.
> 
> Tony
> 

This is not quite right.  OneNAND only allows 3 possibilities:

1. Async: call 'omap2_onenand_set_async_mode()'

2. Sync Read: call 'omap2_onenand_set_sync_mode()' but force 'sync_write' variable to be always zero

3. Sync Read and Sync Write: call 'omap2_onenand_set_sync_mode()' as now

Re: [PATCH] onenand_init: Allow disabling sync read and write based on flags, v3

[Tony Lindgren]

[-- Attachment #1: Type: text/plain, Size: 1220 bytes --]

* Adrian Hunter <adrian.hunter@nokia.com> [090504 01:27]:
> Tony Lindgren wrote:
>> * Tony Lindgren <tony@atomide.com> [090430 07:06]:
>>> * vimal singh <vimalsingh@ti.com> [090429 23:33]:
>>>> 'gpmc-onenand.c' is still confusing name. This is not going to used in
>>>> all boards anyway.
>>> Why do you think this cannot be used for all boards?
>>>
>>> The GPMC timings are totally based on the onenand chip features.
>>
>> And these two patches make omap3430sdp to work with the gpmc-onenand
>> code. Sync mode does not work, but it seems like it was never enabled
>> for sdp anyways.
>>
>> Similar patch should work for other boards too.
>>
>> Tony
>>
>
> This is not quite right.  OneNAND only allows 3 possibilities:
>
> 1. Async: call 'omap2_onenand_set_async_mode()'
>
> 2. Sync Read: call 'omap2_onenand_set_sync_mode()' but force 'sync_write' variable to be always zero
>
> 3. Sync Read and Sync Write: call 'omap2_onenand_set_sync_mode()' as now

Thanks. I take it that you mean that we need to leave out the sync write
option from the possible combinations. Here's the updated version, let
me know if you had something else in mind.

This patch also moves the cpu_is_24xx() test to the init.

Regards,

Tony


[-- Attachment #2: onenand-add-flags-v3.patch --]
[-- Type: text/x-diff, Size: 6708 bytes --]

>From 27f14d9d80b20bbc03b99927ce5f0d2e409ab890 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Thu, 30 Apr 2009 11:43:19 -0700
Subject: [PATCH] onenand_init: Allow disabling sync read and write based on flags, v3

Allow disabling sync read and write based on flags

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
index e882e4b..74e7ea4 100644
--- a/arch/arm/mach-omap2/board-n800.c
+++ b/arch/arm/mach-omap2/board-n800.c
@@ -722,6 +722,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
 	.gpio_irq	= 26,
 	.parts		= onenand_partitions,
 	.nr_parts	= ARRAY_SIZE(onenand_partitions),
+	.flags		= ONENAND_SYNC_READ,
 };
 
 static void __init board_onenand_init(void)
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 7b1ee3d..55e8568 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -515,6 +515,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
 	.gpio_irq	= 65,
 	.parts		= onenand_partitions,
 	.nr_parts	= ARRAY_SIZE(onenand_partitions),
+	.flags		= ONENAND_SYNC_READWRITE,
 };
 
 static void __init board_onenand_init(void)
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index fc79183..d243228 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -86,15 +86,18 @@ static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
 }
 
 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
-			    int sync_write, int hf)
+				int sync_read, int sync_write, int hf)
 {
 	u32 reg;
 
 	reg = omap2_onenand_readw(onenand_base + ONENAND_REG_SYS_CFG1);
 	reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
 	reg |=	(latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
-		ONENAND_SYS_CFG1_SYNC_READ |
 		ONENAND_SYS_CFG1_BL_16;
+	if (sync_read)
+		reg |= ONENAND_SYS_CFG1_SYNC_READ;
+	else
+		reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
 	if (sync_write)
 		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
 	else
@@ -106,8 +109,9 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
 	omap2_onenand_writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 }
 
-static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
-				       int freq)
+static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+					void __iomem *onenand_base,
+					int freq)
 {
 	struct gpmc_timings t;
 	const int t_cer  = 15;
@@ -118,9 +122,17 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 	const int t_wph  = 30;
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
 	int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
-	int err, ticks_cez, sync_write = 0, first_time = 0, hf = 0;
+	int err, ticks_cez, sync_read = 0, sync_write = 0, first_time = 0, hf = 0;
+	int cs = cfg->cs;
 	u32 reg;
 
+	if (cfg->flags & ONENAND_SYNC_READ) {
+		sync_read = 1;
+	} else if (cfg->flags & ONENAND_SYNC_READWRITE) {
+		sync_read = 1;
+		sync_write = 1;
+	}
+
 	if (!freq) {
 		/* Very first call freq is not known */
 		err = omap2_onenand_set_async_mode(cs, onenand_base);
@@ -160,8 +172,6 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		t_ach   = 6;
 		t_aavdh = 6;
 		t_rdyo  = 9;
-		if (cpu_is_omap34xx())
-			sync_write = 1;
 		break;
 	case 66:
 		min_gpmc_clk_period = 15; /* 66 MHz */
@@ -171,8 +181,6 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		t_ach   = 6;
 		t_aavdh = 6;
 		t_rdyo  = 11;
-		if (cpu_is_omap34xx())
-			sync_write = 1;
 		break;
 	default:
 		min_gpmc_clk_period = 18; /* 54 MHz */
@@ -182,6 +190,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		t_ach   = 9;
 		t_aavdh = 7;
 		t_rdyo  = 15;
+		sync_write = 0;
 		break;
 	}
 
@@ -198,7 +207,8 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 		latency = 4;
 
 	if (first_time)
-		set_onenand_cfg(onenand_base, latency, sync_write, hf);
+		set_onenand_cfg(onenand_base, latency,
+					sync_read, sync_write, hf);
 
 	if (div == 1) {
 		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -272,7 +282,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
 			  GPMC_CONFIG1_WRAPBURST_SUPP |
 			  GPMC_CONFIG1_READMULTIPLE_SUPP |
-			  GPMC_CONFIG1_READTYPE_SYNC |
+			  (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
 			  (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
 			  (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
 			  GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
@@ -288,7 +298,7 @@ static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
 	if (err)
 		return err;
 
-	set_onenand_cfg(onenand_base, latency, sync_write, hf);
+	set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
 
 	return 0;
 }
@@ -298,7 +308,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
 	struct device *dev = &gpmc_onenand_device.dev;
 
 	/* Set sync timings in GPMC */
-	if (omap2_onenand_set_sync_mode(gpmc_onenand_data->cs, onenand_base,
+	if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
 			freq) < 0) {
 		dev_err(dev, "Unable to set synchronous mode\n");
 		return -EINVAL;
@@ -313,6 +323,13 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 	gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
 	gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
 
+	if (cpu_is_omap24xx() &&
+			(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
+		printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
+		gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
+		gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
+	}
+
 	if (platform_device_register(&gpmc_onenand_device) < 0) {
 		printk(KERN_ERR "Unable to register OneNAND device\n");
 		return;
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h
index 2a391fa..bb66d0b 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/mach/onenand.h
@@ -14,6 +14,9 @@
 
 #ifndef __ASM_ARCH_OMAP_ONENAND_H__
 
+#define ONENAND_SYNC_READ	(1 << 0)
+#define ONENAND_SYNC_READWRITE	(1 << 1)
+
 struct omap_onenand_platform_data {
 	int			cs;
 	int			gpio_irq;
@@ -21,6 +24,7 @@ struct omap_onenand_platform_data {
 	int			nr_parts;
 	int                     (*onenand_setup)(void __iomem *, int freq);
 	int			dma_channel;
+	u8			flags;
 };
 
 int omap2_onenand_rephase(void);

[PATCH 1/4] onenand init: Rename board-n800-flash.c to gpmc-onenand.c

[Tony Lindgren]

Rename board-n800-flash.c to gpmc-onenand.c.

Signed-off-by: Tony Lindgren <tony@atommide.com>
---
 arch/arm/mach-omap2/Makefile           |    4 ++--
 arch/arm/mach-omap2/gpmc-onenand.c     |    0 
 2 files changed, 2 insertions(+), 2 deletions(-)
 rename arch/arm/mach-omap2/{board-n800-flash.c => gpmc-onenand.c} (100%)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 76acefa..9127a94 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -55,14 +55,14 @@ obj-$(CONFIG_MACH_OMAP_LDP)		+= board-ldp.o \
 obj-$(CONFIG_MACH_OMAP_APOLLON)		+= board-apollon.o \
 					   board-apollon-mmc.o	\
 					   board-apollon-keys.o
-obj-$(CONFIG_MACH_NOKIA_N800)		+= board-n800.o board-n800-flash.o \
+obj-$(CONFIG_MACH_NOKIA_N800)		+= board-n800.o gpmc-onenand.o \
 					   board-n800-mmc.o board-n800-bt.o \
 					   board-n800-usb.o \
 					   board-n800-dsp.o \
 					   board-n800-camera.o
 obj-$(CONFIG_MACH_NOKIA_N810)		+= board-n810.o
 obj-$(CONFIG_MACH_NOKIA_RX51)		+= board-rx51.o \
-					   board-n800-flash.o \
+					   gpmc-onenand.o \
 					   board-rx51-flash.o \
 					   board-rx51-sdram.o \
 					   board-rx51-video.o \
diff --git a/arch/arm/mach-omap2/board-n800-flash.c b/arch/arm/mach-omap2/gpmc-onenand.c
similarity index 100%
rename from arch/arm/mach-omap2/board-n800-flash.c
rename to arch/arm/mach-omap2/gpmc-onenand.c