* [U-Boot] [PATCH 1/7] mx27: basic cpu support
2009-05-19 23:55 [U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
@ 2009-05-19 23:55 ` Ilya Yanok
2009-05-23 0:22 ` Jean-Christophe PLAGNIOL-VILLARD
` (2 more replies)
2009-05-19 23:55 ` [U-Boot] [PATCH 2/7] serial_mx31: allow it to work with mx27 too and rename to serial_mxc Ilya Yanok
` (6 subsequent siblings)
7 siblings, 3 replies; 42+ messages in thread
From: Ilya Yanok @ 2009-05-19 23:55 UTC (permalink / raw)
To: u-boot
This patch adds generic code to support Freescale's i.MX27 SoCs.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
cpu/arm926ejs/mx27/Makefile | 44 +++
cpu/arm926ejs/mx27/generic.c | 237 ++++++++++++++
cpu/arm926ejs/mx27/interrupt.c | 201 ++++++++++++
include/asm-arm/arch-mx27/asm-offsets.h | 16 +
include/asm-arm/arch-mx27/clock.h | 17 +
include/asm-arm/arch-mx27/imx-regs.h | 508 +++++++++++++++++++++++++++++++
6 files changed, 1023 insertions(+), 0 deletions(-)
create mode 100644 cpu/arm926ejs/mx27/Makefile
create mode 100644 cpu/arm926ejs/mx27/generic.c
create mode 100644 cpu/arm926ejs/mx27/interrupt.c
create mode 100644 include/asm-arm/arch-mx27/asm-offsets.h
create mode 100644 include/asm-arm/arch-mx27/clock.h
create mode 100644 include/asm-arm/arch-mx27/imx-regs.h
diff --git a/cpu/arm926ejs/mx27/Makefile b/cpu/arm926ejs/mx27/Makefile
new file mode 100644
index 0000000..c86f3c2
--- /dev/null
+++ b/cpu/arm926ejs/mx27/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = interrupt.o generic.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
new file mode 100644
index 0000000..850d5e6
--- /dev/null
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * get the system pll clock in Hz
+ *
+ * mfi + mfn / (mfd +1)
+ * f = 2 * f_ref * --------------------
+ * pd + 1
+ */
+unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+{
+ unsigned int mfi = (pll >> 10) & 0xf;
+ unsigned int mfn = pll & 0x3ff;
+ unsigned int mfd = (pll >> 16) & 0x3ff;
+ unsigned int pd = (pll >> 26) & 0xf;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+
+ return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
+ (mfd + 1) * (pd + 1));
+}
+
+static ulong clk_in_32k(void)
+{
+ return 1024 * CONFIG_MX27_CLK32;
+}
+
+static ulong clk_in_26m(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ if (readl(&pll->CSCR) & CSCR_OSC26M_DIV1P5) {
+ /* divide by 1.5 */
+ return 26000000 * 2 / 3;
+ } else {
+ return 26000000;
+ }
+}
+
+ulong imx_get_mpllclk(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ ulong cscr = readl(&pll->CSCR);
+ ulong fref;
+
+ if (cscr & CSCR_MCU_SEL)
+ fref = clk_in_26m();
+ else
+ fref = clk_in_32k();
+
+ return imx_decode_pll(readl(&pll->MPCTL0), fref);
+}
+
+ulong imx_get_armclk(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ ulong cscr = readl(&pll->CSCR);
+ ulong fref = imx_get_mpllclk();
+ ulong div;
+
+ if (!(cscr & CSCR_ARM_SRC_MPLL))
+ fref = lldiv((fref * 2), 3);
+
+ div = ((cscr >> 12) & 0x3) + 1;
+
+ return lldiv(fref, div);
+}
+
+ulong imx_get_ahbclk(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ ulong cscr = readl(&pll->CSCR);
+ ulong fref = imx_get_mpllclk();
+ ulong div;
+
+ div = ((cscr >> 8) & 0x3) + 1;
+
+ return lldiv(fref * 2, 3 * div);
+}
+
+ulong imx_get_spllclk(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ ulong cscr = readl(&pll->CSCR);
+ ulong fref;
+
+ if (cscr & CSCR_SP_SEL)
+ fref = clk_in_26m();
+ else
+ fref = clk_in_32k();
+
+ return imx_decode_pll(readl(&pll->SPCTL0), fref);
+}
+
+static ulong imx_decode_perclk(ulong div)
+{
+ return lldiv((imx_get_mpllclk() * 2), (div * 3));
+}
+
+ulong imx_get_perclk1(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ return imx_decode_perclk((readl(&pll->PCDR1) & 0x3f) + 1);
+}
+
+ulong imx_get_perclk2(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ return imx_decode_perclk(((readl(&pll->PCDR1) >> 8) & 0x3f) + 1);
+}
+
+ulong imx_get_perclk3(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ return imx_decode_perclk(((readl(&pll->PCDR1) >> 16) & 0x3f) + 1);
+}
+
+ulong imx_get_perclk4(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ return imx_decode_perclk(((readl(&pll->PCDR1) >> 24) & 0x3f) + 1);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo (void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale i.MX27 at %s MHz\n\n",
+ strmhz(buf, imx_get_mpllclk()));
+ return 0;
+}
+#endif
+
+void imx_gpio_mode(int gpio_mode)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+ unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+ unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+ unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
+ unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
+ unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
+ unsigned int tmp;
+
+ /* Pullup enable */
+ if (gpio_mode & GPIO_PUEN)
+ writel(readl(®s->port[port].PUEN) | (1 << pin),
+ ®s->port[port].PUEN);
+ else
+ writel(readl(®s->port[port].PUEN) & ~(1 << pin),
+ ®s->port[port].PUEN);
+
+ /* Data direction */
+ if (gpio_mode & GPIO_OUT)
+ writel(readl(®s->port[port].DDIR) | 1 << pin,
+ ®s->port[port].DDIR);
+ else
+ writel(readl(®s->port[port].DDIR) & ~(1 << pin),
+ ®s->port[port].DDIR);
+
+ /* Primary / alternate function */
+ if (gpio_mode & GPIO_AF)
+ writel(readl(®s->port[port].GPR) | (1 << pin),
+ ®s->port[port].GPR);
+ else
+ writel(readl(®s->port[port].GPR) & ~(1 << pin),
+ ®s->port[port].GPR);
+
+ /* use as gpio? */
+ if (!(gpio_mode & (GPIO_PF | GPIO_AF)))
+ writel(readl(®s->port[port].GIUS) | (1 << pin),
+ ®s->port[port].GIUS);
+ else
+ writel(readl(®s->port[port].GIUS) & ~(1 << pin),
+ ®s->port[port].GIUS);
+
+ /* Output / input configuration */
+ if (pin < 16) {
+ tmp = readl(®s->port[port].OCR1);
+ tmp &= ~(3 << (pin * 2));
+ tmp |= (ocr << (pin * 2));
+ writel(tmp, ®s->port[port].OCR1);
+
+ writel(readl(®s->port[port].ICONFA1) & ~(3 << (pin * 2)),
+ ®s->port[port].ICONFA1);
+ writel(readl(®s->port[port].ICONFA1) | aout << (pin * 2),
+ ®s->port[port].ICONFA1);
+ writel(readl(®s->port[port].ICONFB1) & ~(3 << (pin * 2)),
+ ®s->port[port].ICONFB1);
+ writel(readl(®s->port[port].ICONFB1) | bout << (pin * 2),
+ ®s->port[port].ICONFB1);
+ } else {
+ pin -= 16;
+
+ tmp = readl(®s->port[port].OCR2);
+ tmp &= ~(3 << (pin * 2));
+ tmp |= (ocr << (pin * 2));
+ writel(tmp, ®s->port[port].OCR2);
+
+ writel(readl(®s->port[port].ICONFA2) & ~(3 << (pin * 2)),
+ ®s->port[port].ICONFA2);
+ writel(readl(®s->port[port].ICONFA2) | aout << (pin * 2),
+ ®s->port[port].ICONFA2);
+ writel(readl(®s->port[port].ICONFB2) & ~(3 << (pin * 2)),
+ ®s->port[port].ICONFB2);
+ writel(readl(®s->port[port].ICONFB2) | bout << (pin * 2),
+ ®s->port[port].ICONFB2);
+ }
+}
+
diff --git a/cpu/arm926ejs/mx27/interrupt.c b/cpu/arm926ejs/mx27/interrupt.c
new file mode 100644
index 0000000..8f3e809
--- /dev/null
+++ b/cpu/arm926ejs/mx27/interrupt.c
@@ -0,0 +1,201 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1 << 15) /* Software reset */
+#define GPTCR_FRR (1 << 8) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
+#define GPTCR_TEN 1 /* Timer enable */
+
+static ulong timestamp;
+static ulong lastinc;
+
+/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
+#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, CONFIG_MX27_CLK32);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ time *= CONFIG_MX27_CLK32;
+ do_div(time, CONFIG_SYS_HZ);
+ return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us = us * CONFIG_MX27_CLK32 + 999999;
+ do_div(us, 1000000);
+ return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ do_div(tick, TICK_PER_TIME);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us += US_PER_TICK - 1;
+ do_div(us, US_PER_TICK);
+ return us;
+}
+#endif
+
+/* nothing really to do with interrupts, just starts up a counter. */
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init(void)
+{
+ int i;
+ struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ /* setup GP Timer 1 */
+ writel(GPTCR_SWR, ®s->GPT_TCTL);
+
+ writel(readl(&pll->PCCR0) | PCCR0_GPT1_EN, &pll->PCCR0);
+ writel(readl(&pll->PCCR1) | PCCR1_PERCLK1_EN, &pll->PCCR1);
+
+ for (i = 0; i < 100; i++)
+ writel(0, ®s->GPT_TCTL); /* We have no udelay by now */
+ writel(0, ®s->GPT_TPRER); /* 32Khz */
+ /* Freerun Mode, PERCLK1 input */
+ writel(readl(®s->GPT_TCTL) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+ ®s->GPT_TCTL);
+ writel(readl(®s->GPT_TCTL) | GPTCR_TEN, ®s->GPT_TCTL);
+
+ return 0;
+}
+
+void reset_timer_masked(void)
+{
+ struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+ /* reset time */
+ /* capture current incrementer value time */
+ lastinc = readl(®s->GPT_TCN);
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+unsigned long long get_ticks (void)
+{
+ struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+ ulong now = readl(®s->GPT_TCN); /* current tick value */
+
+ if (now >= lastinc) /* normal mode (non roll) */
+ /* move stamp forward with absolut diff ticks */
+ timestamp += (now - lastinc);
+ else /* we have rollover of incrementer */
+ timestamp += (0xFFFFFFFF - lastinc) + now;
+ lastinc = now;
+ return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+ /*
+ * get_ticks() returns a long long (64 bit), it wraps in
+ * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+ * 5 * 10^6 days - long enough.
+ */
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = time_to_tick(t);
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay (unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = us_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ */
+void reset_cpu (ulong ignored)
+{
+ struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
+ /* Disable watchdog and set Time-Out field to 0 */
+ writel(0x00000000, ®s->WCR);
+
+ /* Write Service Sequence */
+ writel(0x00005555, ®s->WSR);
+ writel(0x0000AAAA, ®s->WSR);
+
+ /* Enable watchdog */
+ writel(WCR_WDE, ®s->WCR);
+
+ while (1);
+ /*NOTREACHED*/
+}
diff --git a/include/asm-arm/arch-mx27/asm-offsets.h b/include/asm-arm/arch-mx27/asm-offsets.h
new file mode 100644
index 0000000..497afe5
--- /dev/null
+++ b/include/asm-arm/arch-mx27/asm-offsets.h
@@ -0,0 +1,16 @@
+#define AIPI1_PSR0 0x10000000
+#define AIPI1_PSR1 0x10000004
+#define AIPI2_PSR0 0x10020000
+#define AIPI2_PSR1 0x10020004
+#define CSCR 0x10027000
+#define MPCTL0 0x10027004
+#define SPCTL0 0x1002700c
+#define PCDR0 0x10027018
+#define PCDR1 0x1002701c
+#define PCCR0 0x10027020
+#define PCCR1 0x10027024
+#define ESDCTL0_ROF 0x00
+#define ESDCFG0_ROF 0x04
+#define ESDCTL1_ROF 0x08
+#define ESDCFG1_ROF 0x0C
+#define ESDMISC_ROF 0x10
diff --git a/include/asm-arm/arch-mx27/clock.h b/include/asm-arm/arch-mx27/clock.h
new file mode 100644
index 0000000..f6615d9
--- /dev/null
+++ b/include/asm-arm/arch-mx27/clock.h
@@ -0,0 +1,17 @@
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+
+ulong imx_get_mpllclk(void);
+ulong imx_get_armclk(void);
+ulong imx_get_spllclk(void);
+ulong imx_get_fclk(void);
+ulong imx_get_hclk(void);
+ulong imx_get_bclk(void);
+ulong imx_get_perclk1(void);
+ulong imx_get_perclk2(void);
+ulong imx_get_perclk3(void);
+ulong imx_get_ahbclk(void);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/include/asm-arm/arch-mx27/imx-regs.h b/include/asm-arm/arch-mx27/imx-regs.h
new file mode 100644
index 0000000..16d2142
--- /dev/null
+++ b/include/asm-arm/arch-mx27/imx-regs.h
@@ -0,0 +1,508 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+
+#ifndef __ASSEMBLY__
+
+extern void imx_gpio_mode (int gpio_mode);
+
+/* AIPI */
+struct aipi_regs {
+ u32 PSR0;
+ u32 PSR1;
+};
+
+/* System Control */
+struct system_control_regs {
+ u32 res[5];
+ u32 FMCR;
+ u32 GPCR;
+ u32 WBCR;
+ u32 DSCR1;
+ u32 DSCR2;
+ u32 DSCR3;
+ u32 DSCR4;
+ u32 DSCR5;
+ u32 DSCR6;
+ u32 DSCR7;
+ u32 DSCR8;
+ u32 DSCR9;
+ u32 DSCR10;
+ u32 DSCR11;
+ u32 DSCR12;
+ u32 DSCR13;
+ u32 PSCR;
+ u32 PMCR;
+ u32 res1;
+ u32 DCVR0;
+ u32 DCVR1;
+ u32 DCVR2;
+ u32 DCVR3;
+};
+
+/* Chip Select Registers */
+struct weim_regs {
+ u32 CS0U; /* Chip Select 0 Upper Register */
+ u32 CS0L; /* Chip Select 0 Lower Register */
+ u32 CS0A; /* Chip Select 0 Addition Register */
+ u32 pad0;
+ u32 CS1U; /* Chip Select 1 Upper Register */
+ u32 CS1L; /* Chip Select 1 Lower Register */
+ u32 CS1A; /* Chip Select 1 Addition Register */
+ u32 pad1;
+ u32 CS2U; /* Chip Select 2 Upper Register */
+ u32 CS2L; /* Chip Select 2 Lower Register */
+ u32 CS2A; /* Chip Select 2 Addition Register */
+ u32 pad2;
+ u32 CS3U; /* Chip Select 3 Upper Register */
+ u32 CS3L; /* Chip Select 3 Lower Register */
+ u32 CS3A; /* Chip Select 3 Addition Register */
+ u32 pad3;
+ u32 CS4U; /* Chip Select 4 Upper Register */
+ u32 CS4L; /* Chip Select 4 Lower Register */
+ u32 CS4A; /* Chip Select 4 Addition Register */
+ u32 pad4;
+ u32 CS5U; /* Chip Select 5 Upper Register */
+ u32 CS5L; /* Chip Select 5 Lower Register */
+ u32 CS5A; /* Chip Select 5 Addition Register */
+ u32 pad5;
+ u32 EIM; /* WEIM Configuration Register */
+};
+
+/* SDRAM Controller registers */
+struct esdramc_regs {
+/* Enhanced SDRAM Control Register 0 */
+ u32 ESDCTL0;
+/* Enhanced SDRAM Configuration Register 0 */
+ u32 ESDCFG0;
+/* Enhanced SDRAM Control Register 1 */
+ u32 ESDCTL1;
+/* Enhanced SDRAM Configuration Register 1 */
+ u32 ESDCFG1;
+/* Enhanced SDRAM Miscellanious Register */
+ u32 ESDMISC;
+};
+
+/* Watchdog Registers*/
+struct wdog_regs {
+ u32 WCR;
+ u32 WSR;
+ u32 WSTR;
+};
+
+/* PLL registers */
+struct pll_regs {
+ u32 CSCR; /* Clock Source Control Register */
+ u32 MPCTL0; /* MCU PLL Control Register 0 */
+ u32 MPCTL1; /* MCU PLL Control Register 1 */
+ u32 SPCTL0; /* System PLL Control Register 0 */
+ u32 SPCTL1; /* System PLL Control Register 1 */
+ u32 OSC26MCTL; /* Oscillator 26M Register */
+ u32 PCDR0; /* Peripheral Clock Divider Register 0 */
+ u32 PCDR1; /* Peripheral Clock Divider Register 1 */
+ u32 PCCR0; /* Peripheral Clock Control Register 0 */
+ u32 PCCR1; /* Peripheral Clock Control Register 1 */
+ u32 CCSR; /* Clock Control Status Register */
+};
+
+/*
+ * Definitions for the clocksource registers
+ */
+struct gpt_regs {
+ u32 GPT_TCTL;
+ u32 GPT_TPRER;
+ u32 GPT_TCMP;
+ u32 GPT_TCR;
+ u32 GPT_TCN;
+ u32 GPT_TSTAT;
+};
+
+/*
+ * GPIO Module and I/O Multiplexer
+ */
+#define PORTA 0
+#define PORTB 1
+#define PORTC 2
+#define PORTD 3
+#define PORTE 4
+#define PORTF 5
+
+struct gpio_regs {
+ struct {
+ u32 DDIR;
+ u32 OCR1;
+ u32 OCR2;
+ u32 ICONFA1;
+ u32 ICONFA2;
+ u32 ICONFB1;
+ u32 ICONFB2;
+ u32 DR;
+ u32 GIUS;
+ u32 SSR;
+ u32 ICR1;
+ u32 ICR2;
+ u32 IMR;
+ u32 ISR;
+ u32 GPR;
+ u32 SWR;
+ u32 PUEN;
+ u32 res[0x2f];
+ } port[6];
+};
+
+/* IIM Control Registers */
+struct iim_regs {
+ u32 IIM_STAT;
+ u32 IIM_STATM;
+ u32 IIM_ERR;
+ u32 IIM_EMASK;
+ u32 IIM_FCTL;
+ u32 IIM_UA;
+ u32 IIM_LA;
+ u32 IIM_SDAT;
+ u32 IIM_PREV;
+ u32 IIM_SREV;
+ u32 IIM_PROG_P;
+ u32 IIM_SCS0;
+ u32 IIM_SCS1;
+ u32 IIM_SCS2;
+ u32 IIM_SCS3;
+ u32 res[0x1f0];
+ u32 IIM_BANK_AREA0[0x100];
+};
+#endif
+
+#define IMX_IO_BASE 0x10000000
+
+#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
+#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
+#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
+#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
+#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
+#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
+#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
+#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
+#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
+#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
+#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
+#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
+#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
+#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
+#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
+#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE)
+#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
+#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
+#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
+#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
+#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
+#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
+
+#define IMX_ESD_BASE (0xD8001000)
+#define IMX_WEIM_BASE (0xD8002000)
+
+/* FMCR System Control bit definition*/
+#define UART4_RXD_CTL (1<<25)
+#define UART4_RTS_CTL (1<<24)
+#define KP_COL6_CTL (1<<18)
+#define KP_ROW7_CTL (1<<17)
+#define KP_ROW6_CTL (1<<16)
+#define PC_WAIT_B_CTL (1<<14)
+#define PC_READY_CTL (1<<13)
+#define PC_VS1_CTL (1<<12)
+#define PC_VS2_CTL (1<<11)
+#define PC_BVD1_CTL (1<<10)
+#define PC_BVD2_CTL (1<<9)
+#define IOS16_CTL (1<<8)
+#define NF_FMS (1<<5)
+#define NF_16BIT_SEL (1<<4)
+#define SLCDC_SEL (1<<2)
+#define SDCS1_SEL (1<<1)
+#define SDCS0_SEL (1<<0)
+
+
+/* important definition of some bits of WCR */
+#define WCR_WDE 0x04
+
+#define CSCR_MPEN (1 << 0)
+#define CSCR_SPEN (1 << 1)
+#define CSCR_FPM_EN (1 << 2)
+#define CSCR_OSC26M_DIS (1 << 3)
+#define CSCR_OSC26M_DIV1P5 (1 << 4)
+#define CSCR_AHB_DIV
+#define CSCR_ARM_DIV
+#define CSCR_ARM_SRC_MPLL (1 << 15)
+#define CSCR_MCU_SEL (1 << 16)
+#define CSCR_SP_SEL (1 << 17)
+#define CSCR_MPLL_RESTART (1 << 18)
+#define CSCR_SPLL_RESTART (1 << 19)
+#define CSCR_MSHC_SEL (1 << 20)
+#define CSCR_H264_SEL (1 << 21)
+#define CSCR_SSI1_SEL (1 << 22)
+#define CSCR_SSI2_SEL (1 << 23)
+#define CSCR_SD_CNT
+#define CSCR_USB_DIV
+#define CSCR_UPDATE_DIS (1 << 31)
+
+#define MPCTL1_BRMO (1 << 6)
+#define MPCTL1_LF (1 << 15)
+
+#define PCCR0_SSI2_EN (1 << 0)
+#define PCCR0_SSI1_EN (1 << 1)
+#define PCCR0_SLCDC_EN (1 << 2)
+#define PCCR0_SDHC3_EN (1 << 3)
+#define PCCR0_SDHC2_EN (1 << 4)
+#define PCCR0_SDHC1_EN (1 << 5)
+#define PCCR0_SDC_EN (1 << 6)
+#define PCCR0_SAHARA_EN (1 << 7)
+#define PCCR0_RTIC_EN (1 << 8)
+#define PCCR0_RTC_EN (1 << 9)
+#define PCCR0_PWM_EN (1 << 11)
+#define PCCR0_OWIRE_EN (1 << 12)
+#define PCCR0_MSHC_EN (1 << 13)
+#define PCCR0_LCDC_EN (1 << 14)
+#define PCCR0_KPP_EN (1 << 15)
+#define PCCR0_IIM_EN (1 << 16)
+#define PCCR0_I2C2_EN (1 << 17)
+#define PCCR0_I2C1_EN (1 << 18)
+#define PCCR0_GPT6_EN (1 << 19)
+#define PCCR0_GPT5_EN (1 << 20)
+#define PCCR0_GPT4_EN (1 << 21)
+#define PCCR0_GPT3_EN (1 << 22)
+#define PCCR0_GPT2_EN (1 << 23)
+#define PCCR0_GPT1_EN (1 << 24)
+#define PCCR0_GPIO_EN (1 << 25)
+#define PCCR0_FEC_EN (1 << 26)
+#define PCCR0_EMMA_EN (1 << 27)
+#define PCCR0_DMA_EN (1 << 28)
+#define PCCR0_CSPI3_EN (1 << 29)
+#define PCCR0_CSPI2_EN (1 << 30)
+#define PCCR0_CSPI1_EN (1 << 31)
+
+#define PCCR1_MSHC_BAUDEN (1 << 2)
+#define PCCR1_NFC_BAUDEN (1 << 3)
+#define PCCR1_SSI2_BAUDEN (1 << 4)
+#define PCCR1_SSI1_BAUDEN (1 << 5)
+#define PCCR1_H264_BAUDEN (1 << 6)
+#define PCCR1_PERCLK4_EN (1 << 7)
+#define PCCR1_PERCLK3_EN (1 << 8)
+#define PCCR1_PERCLK2_EN (1 << 9)
+#define PCCR1_PERCLK1_EN (1 << 10)
+#define PCCR1_HCLK_USB (1 << 11)
+#define PCCR1_HCLK_SLCDC (1 << 12)
+#define PCCR1_HCLK_SAHARA (1 << 13)
+#define PCCR1_HCLK_RTIC (1 << 14)
+#define PCCR1_HCLK_LCDC (1 << 15)
+#define PCCR1_HCLK_H264 (1 << 16)
+#define PCCR1_HCLK_FEC (1 << 17)
+#define PCCR1_HCLK_EMMA (1 << 18)
+#define PCCR1_HCLK_EMI (1 << 19)
+#define PCCR1_HCLK_DMA (1 << 20)
+#define PCCR1_HCLK_CSI (1 << 21)
+#define PCCR1_HCLK_BROM (1 << 22)
+#define PCCR1_HCLK_ATA (1 << 23)
+#define PCCR1_WDT_EN (1 << 24)
+#define PCCR1_USB_EN (1 << 25)
+#define PCCR1_UART6_EN (1 << 26)
+#define PCCR1_UART5_EN (1 << 27)
+#define PCCR1_UART4_EN (1 << 28)
+#define PCCR1_UART3_EN (1 << 29)
+#define PCCR1_UART2_EN (1 << 30)
+#define PCCR1_UART1_EN (1 << 31)
+
+/* SDRAM Controller registers bitfields */
+#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
+#define ESDCTL_BL (1 << 7)
+#define ESDCTL_FP (1 << 8)
+#define ESDCTL_PWDT(x) (((x) & 3) << 10)
+#define ESDCTL_SREFR(x) (((x) & 7) << 13)
+#define ESDCTL_DSIZ_16_UPPER (0 << 16)
+#define ESDCTL_DSIZ_16_LOWER (1 << 16)
+#define ESDCTL_DSIZ_32 (2 << 16)
+#define ESDCTL_COL8 (0 << 20)
+#define ESDCTL_COL9 (1 << 20)
+#define ESDCTL_COL10 (2 << 20)
+#define ESDCTL_ROW11 (0 << 24)
+#define ESDCTL_ROW12 (1 << 24)
+#define ESDCTL_ROW13 (2 << 24)
+#define ESDCTL_ROW14 (3 << 24)
+#define ESDCTL_ROW15 (4 << 24)
+#define ESDCTL_SP (1 << 27)
+#define ESDCTL_SMODE_NORMAL (0 << 28)
+#define ESDCTL_SMODE_PRECHARGE (1 << 28)
+#define ESDCTL_SMODE_AUTO_REF (2 << 28)
+#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
+#define ESDCTL_SMODE_MAN_REF (4 << 28)
+#define ESDCTL_SDE (1 << 31)
+
+#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
+#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
+#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
+#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
+#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
+#define ESDCFG_TWR (1 << 15)
+#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
+#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
+#define ESDCFG_TWTR (1 << 20)
+#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
+
+#define ESDMISC_RST (1 << 1)
+#define ESDMISC_MDDREN (1 << 2)
+#define ESDMISC_MDDR_DL_RST (1 << 3)
+#define ESDMISC_MDDR_MDIS (1 << 4)
+#define ESDMISC_LHD (1 << 5)
+#define ESDMISC_MA10_SHARE (1 << 6)
+#define ESDMISC_SDRAM_RDY (1 << 31)
+
+#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
+#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
+#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
+#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
+#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
+#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
+#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
+#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
+#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
+
+#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
+#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
+#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
+#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
+#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
+#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
+#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
+#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
+#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
+#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
+#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
+#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
+#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
+#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
+#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
+#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
+#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
+#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
+
+#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
+#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
+#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
+#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
+#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
+#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
+#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
+#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
+#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
+#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
+#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
+#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
+#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
+#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
+#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
+#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
+#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
+#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
+#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
+#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
+#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
+#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
+#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
+#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
+#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
+#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
+#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
+#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
+#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
+
+/* Clocksource Bitfields */
+#define TCTL_SWR (1<<15) /* Software reset */
+#define TCTL_FRR (1<<8) /* Freerun / restart */
+#define TCTL_CAP (3<<6) /* Capture Edge */
+#define TCTL_OM (1<<5) /* output mode */
+#define TCTL_IRQEN (1<<4) /* interrupt enable */
+#define TCTL_CLKSOURCE (1) /* Clock source bit position */
+#define TCTL_TEN (1) /* Timer enable */
+#define TPRER_PRES (0xff) /* Prescale */
+#define TSTAT_CAPT (1<<1) /* Capture event */
+#define TSTAT_COMP (1) /* Compare event */
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT)
+
+#define GPIO_OUT (1 << 8)
+#define GPIO_IN (0 << 8)
+#define GPIO_PUEN (1 << 9)
+
+#define GPIO_PF (1 << 10)
+#define GPIO_AF (1 << 11)
+
+#define GPIO_OCR_SHIFT 12
+#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT 14
+#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT 16
+#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
+
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+
+/* Definitions for i.MX27 TO2 */
+#define IIM0_MAC 5
+#define IIM0_SCC_KEY 11
+#define IIM1_SUID 1
+
+#endif /* _IMX_REGS_H */
+
--
1.6.0.6
^ permalink raw reply related [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 1/7] mx27: basic cpu support
2009-05-19 23:55 ` [U-Boot] [PATCH 1/7] mx27: basic cpu support Ilya Yanok
@ 2009-05-23 0:22 ` Jean-Christophe PLAGNIOL-VILLARD
2009-05-26 19:25 ` Wolfgang Denk
2009-05-28 22:57 ` Wolfgang Denk
2009-05-28 23:04 ` Wolfgang Denk
2 siblings, 1 reply; 42+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-05-23 0:22 UTC (permalink / raw)
To: u-boot
> diff --git a/cpu/arm926ejs/mx27/interrupt.c b/cpu/arm926ejs/mx27/interrupt.c
please rename it timer.c
> new file mode 100644
> index 0000000..8f3e809
> --- /dev/null
> +++ b/cpu/arm926ejs/mx27/interrupt.c
> @@ -0,0 +1,201 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Alex Zuepke <azu@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> + *
> + * (C) Copyright 2009
> + * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
<snip>
> +
> +/*
> + * Reset the cpu by setting up the watchdog timer and let it time out
> + */
> +void reset_cpu (ulong ignored)
please move to a reset.c file
> +{
> + struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
> + /* Disable watchdog and set Time-Out field to 0 */
> + writel(0x00000000, ®s->WCR);
> +
> + /* Write Service Sequence */
> + writel(0x00005555, ®s->WSR);
> + writel(0x0000AAAA, ®s->WSR);
> +
> + /* Enable watchdog */
> + writel(WCR_WDE, ®s->WCR);
> +
> + while (1);
> + /*NOTREACHED*/
> +}
> diff --git a/include/asm-arm/arch-mx27/asm-offsets.h b/include/asm-arm/arch-mx27/asm-offsets.h
> new file mode 100644
> index 0000000..497afe5
> --- /dev/null
> +++ b/include/asm-arm/arch-mx27/asm-offsets.h
please add GPL header and copyright
> @@ -0,0 +1,16 @@
> +#define AIPI1_PSR0 0x10000000
> +#define AIPI1_PSR1 0x10000004
> +#define AIPI2_PSR0 0x10020000
> +#define AIPI2_PSR1 0x10020004
> +#define CSCR 0x10027000
> +#define MPCTL0 0x10027004
> +#define SPCTL0 0x1002700c
> +#define PCDR0 0x10027018
> +#define PCDR1 0x1002701c
> +#define PCCR0 0x10027020
> +#define PCCR1 0x10027024
> +#define ESDCTL0_ROF 0x00
> +#define ESDCFG0_ROF 0x04
> +#define ESDCTL1_ROF 0x08
> +#define ESDCFG1_ROF 0x0C
> +#define ESDMISC_ROF 0x10
> diff --git a/include/asm-arm/arch-mx27/clock.h b/include/asm-arm/arch-mx27/clock.h
> new file mode 100644
> index 0000000..f6615d9
> --- /dev/null
> +++ b/include/asm-arm/arch-mx27/clock.h
> @@ -0,0 +1,17 @@
please add GPL header and copyright
> +
> +#ifndef __ASM_ARCH_CLOCK_H
> +#define __ASM_ARCH_CLOCK_H
> +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
> +
> +ulong imx_get_mpllclk(void);
> +ulong imx_get_armclk(void);
> +ulong imx_get_spllclk(void);
> +ulong imx_get_fclk(void);
> +ulong imx_get_hclk(void);
> +ulong imx_get_bclk(void);
> +ulong imx_get_perclk1(void);
> +ulong imx_get_perclk2(void);
> +ulong imx_get_perclk3(void);
> +ulong imx_get_ahbclk(void);
> +
> +#endif /* __ASM_ARCH_CLOCK_H */
> diff --git a/include/asm-arm/arch-mx27/imx-regs.h b/include/asm-arm/arch-mx27/imx-regs.h
> new file mode 100644
> index 0000000..16d2142
> --- /dev/null
> +++ b/include/asm-arm/arch-mx27/imx-regs.h
> @@ -0,0 +1,508 @@
> +/*
> + *
> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _IMX_REGS_H
> +#define _IMX_REGS_H
> +
> +#ifndef __ASSEMBLY__
> +
> +extern void imx_gpio_mode (int gpio_mode);
> +
> +/* AIPI */
> +struct aipi_regs {
> + u32 PSR0;
please do not use uppercase
> + u32 PSR1;
> +};
> +
> +/* System Control */
> +struct system_control_regs {
> + u32 res[5];
> + u32 FMCR;
> + u32 GPCR;
> + u32 WBCR;
> + u32 DSCR1;
> + u32 DSCR2;
> + u32 DSCR3;
> + u32 DSCR4;
> + u32 DSCR5;
> + u32 DSCR6;
> + u32 DSCR7;
> + u32 DSCR8;
> + u32 DSCR9;
> + u32 DSCR10;
> + u32 DSCR11;
> + u32 DSCR12;
> + u32 DSCR13;
> + u32 PSCR;
> + u32 PMCR;
> + u32 res1;
> + u32 DCVR0;
> + u32 DCVR1;
> + u32 DCVR2;
> + u32 DCVR3;
> +};
> +
> +/* Chip Select Registers */
> +struct weim_regs {
> + u32 CS0U; /* Chip Select 0 Upper Register */
^^^^
whitespace please fix
and please check the other comments
> + u32 CS0L; /* Chip Select 0 Lower Register */
> + u32 CS0A; /* Chip Select 0 Addition Register */
<snip>
+
> +/* FMCR System Control bit definition*/
> +#define UART4_RXD_CTL (1<<25)
please add space before and after '<<'
> +#define UART4_RTS_CTL (1<<24)
> +#define KP_COL6_CTL (1<<18)
> +#define KP_ROW7_CTL (1<<17)
> +#define KP_ROW6_CTL (1<<16)
> +#define PC_WAIT_B_CTL (1<<14)
> +#define PC_READY_CTL (1<<13)
> +#define PC_VS1_CTL (1<<12)
> +#define PC_VS2_CTL (1<<11)
> +#define PC_BVD1_CTL (1<<10)
> +#define PC_BVD2_CTL (1<<9)
> +#define IOS16_CTL (1<<8)
> +#define NF_FMS (1<<5)
> +#define NF_16BIT_SEL (1<<4)
> +#define SLCDC_SEL (1<<2)
> +#define SDCS1_SEL (1<<1)
> +#define SDCS0_SEL (1<<0)
> +
Best Regards,
J.
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 1/7] mx27: basic cpu support
2009-05-23 0:22 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2009-05-26 19:25 ` Wolfgang Denk
0 siblings, 0 replies; 42+ messages in thread
From: Wolfgang Denk @ 2009-05-26 19:25 UTC (permalink / raw)
To: u-boot
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message <20090523002250.GA20889@game.jcrosoft.org> you wrote:
>
> > --- /dev/null
> > +++ b/include/asm-arm/arch-mx27/asm-offsets.h
> please add GPL header and copyright
For this file this makes not much sense. This file will be
auto-generated from other header files which have all GPL headers and
such. Please consider this file a temporary workaround only.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Writing a book is like washing an elephant: there's no good place to
begin or end, and it's hard to keep track of what you've already
covered.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 1/7] mx27: basic cpu support
2009-05-19 23:55 ` [U-Boot] [PATCH 1/7] mx27: basic cpu support Ilya Yanok
2009-05-23 0:22 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2009-05-28 22:57 ` Wolfgang Denk
2009-05-28 23:04 ` Wolfgang Denk
2 siblings, 0 replies; 42+ messages in thread
From: Wolfgang Denk @ 2009-05-28 22:57 UTC (permalink / raw)
To: u-boot
Dear Ilya Yanok,
In message <1242777361-6717-2-git-send-email-yanok@emcraft.com> you wrote:
> This patch adds generic code to support Freescale's i.MX27 SoCs.
...
> +void imx_gpio_mode(int gpio_mode)
> +{
> + struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
> + unsigned int pin = gpio_mode & GPIO_PIN_MASK;
> + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
> + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
> + unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
> + unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
> + unsigned int tmp;
> +
> + /* Pullup enable */
> + if (gpio_mode & GPIO_PUEN)
> + writel(readl(®s->port[port].PUEN) | (1 << pin),
> + ®s->port[port].PUEN);
> + else
> + writel(readl(®s->port[port].PUEN) & ~(1 << pin),
> + ®s->port[port].PUEN);
Please use curly braces for multiline if-else statements (2 lines in
both the if and the else branch here, and more of these down below in
the file).
> + if (now >= lastinc) /* normal mode (non roll) */
> + /* move stamp forward with absolut diff ticks */
> + timestamp += (now - lastinc);
> + else /* we have rollover of incrementer */
> + timestamp += (0xFFFFFFFF - lastinc) + now;
Ditto. Braces, please.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"In Christianity neither morality nor religion come into contact with
reality at any point." - Friedrich Nietzsche
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 1/7] mx27: basic cpu support
2009-05-19 23:55 ` [U-Boot] [PATCH 1/7] mx27: basic cpu support Ilya Yanok
2009-05-23 0:22 ` Jean-Christophe PLAGNIOL-VILLARD
2009-05-28 22:57 ` Wolfgang Denk
@ 2009-05-28 23:04 ` Wolfgang Denk
2 siblings, 0 replies; 42+ messages in thread
From: Wolfgang Denk @ 2009-05-28 23:04 UTC (permalink / raw)
To: u-boot
Dear Ilya Yanok,
In message <1242777361-6717-2-git-send-email-yanok@emcraft.com> you wrote:
> This patch adds generic code to support Freescale's i.MX27 SoCs.
>
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---
> cpu/arm926ejs/mx27/Makefile | 44 +++
> cpu/arm926ejs/mx27/generic.c | 237 ++++++++++++++
> cpu/arm926ejs/mx27/interrupt.c | 201 ++++++++++++
> include/asm-arm/arch-mx27/asm-offsets.h | 16 +
> include/asm-arm/arch-mx27/clock.h | 17 +
> include/asm-arm/arch-mx27/imx-regs.h | 508 +++++++++++++++++++++++++++++++
> 6 files changed, 1023 insertions(+), 0 deletions(-)
> create mode 100644 cpu/arm926ejs/mx27/Makefile
> create mode 100644 cpu/arm926ejs/mx27/generic.c
> create mode 100644 cpu/arm926ejs/mx27/interrupt.c
> create mode 100644 include/asm-arm/arch-mx27/asm-offsets.h
> create mode 100644 include/asm-arm/arch-mx27/clock.h
> create mode 100644 include/asm-arm/arch-mx27/imx-regs.h
...
> +/* System Control */
> +struct system_control_regs {
> + u32 res[5];
> + u32 FMCR;
> + u32 GPCR;
> + u32 WBCR;
> + u32 DSCR1;
> + u32 DSCR2;
> + u32 DSCR3;
> + u32 DSCR4;
> + u32 DSCR5;
> + u32 DSCR6;
> + u32 DSCR7;
> + u32 DSCR8;
> + u32 DSCR9;
> + u32 DSCR10;
> + u32 DSCR11;
> + u32 DSCR12;
> + u32 DSCR13;
> + u32 PSCR;
> + u32 PMCR;
> + u32 res1;
> + u32 DCVR0;
> + u32 DCVR1;
> + u32 DCVR2;
> + u32 DCVR3;
> +};
> +
> +/* Chip Select Registers */
> +struct weim_regs {
> + u32 CS0U; /* Chip Select 0 Upper Register */
> + u32 CS0L; /* Chip Select 0 Lower Register */
> + u32 CS0A; /* Chip Select 0 Addition Register */
> + u32 pad0;
> + u32 CS1U; /* Chip Select 1 Upper Register */
> + u32 CS1L; /* Chip Select 1 Lower Register */
> + u32 CS1A; /* Chip Select 1 Addition Register */
> + u32 pad1;
> + u32 CS2U; /* Chip Select 2 Upper Register */
> + u32 CS2L; /* Chip Select 2 Lower Register */
> + u32 CS2A; /* Chip Select 2 Addition Register */
> + u32 pad2;
> + u32 CS3U; /* Chip Select 3 Upper Register */
> + u32 CS3L; /* Chip Select 3 Lower Register */
> + u32 CS3A; /* Chip Select 3 Addition Register */
> + u32 pad3;
> + u32 CS4U; /* Chip Select 4 Upper Register */
> + u32 CS4L; /* Chip Select 4 Lower Register */
> + u32 CS4A; /* Chip Select 4 Addition Register */
> + u32 pad4;
> + u32 CS5U; /* Chip Select 5 Upper Register */
> + u32 CS5L; /* Chip Select 5 Lower Register */
> + u32 CS5A; /* Chip Select 5 Addition Register */
> + u32 pad5;
> + u32 EIM; /* WEIM Configuration Register */
> +};
here and everywhere in the code: identifiers are lower case only.
Upper case is reserved for macros only.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A conservative is a man who believes that nothing should be done for
the first time. - Alfred E. Wiggam
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 2/7] serial_mx31: allow it to work with mx27 too and rename to serial_mxc
2009-05-19 23:55 [U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
2009-05-19 23:55 ` [U-Boot] [PATCH 1/7] mx27: basic cpu support Ilya Yanok
@ 2009-05-19 23:55 ` Ilya Yanok
2009-05-23 0:25 ` Jean-Christophe PLAGNIOL-VILLARD
2009-05-19 23:55 ` [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27 Ilya Yanok
` (5 subsequent siblings)
7 siblings, 1 reply; 42+ messages in thread
From: Ilya Yanok @ 2009-05-19 23:55 UTC (permalink / raw)
To: u-boot
UART hardware on i.MX27 is the same as on the i.MX31 so we just
need to provide the driver with correct address of the registers.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
drivers/serial/Makefile | 2 +-
drivers/serial/serial_mx31.c | 226 -----------------------------------
drivers/serial/serial_mxc.c | 247 +++++++++++++++++++++++++++++++++++++++
include/configs/imx31_litekit.h | 2 +-
include/configs/imx31_phycore.h | 2 +-
include/configs/mx31ads.h | 2 +-
include/configs/qong.h | 2 +-
7 files changed, 252 insertions(+), 231 deletions(-)
delete mode 100644 drivers/serial/serial_mx31.c
create mode 100644 drivers/serial/serial_mxc.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 14c818d..9a572e9 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -40,7 +40,7 @@ COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
-COBJS-$(CONFIG_MX31_UART) += serial_mx31.o
+COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
diff --git a/drivers/serial/serial_mx31.c b/drivers/serial/serial_mx31.c
deleted file mode 100644
index 7c0682a..0000000
--- a/drivers/serial/serial_mx31.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/arch/mx31.h>
-
-#define __REG(x) (*((volatile u32 *)(x)))
-
-#ifdef CONFIG_SYS_MX31_UART1
-#define UART_PHYS 0x43f90000
-#elif defined(CONFIG_SYS_MX31_UART2)
-#define UART_PHYS 0x43f94000
-#elif defined(CONFIG_SYS_MX31_UART3)
-#define UART_PHYS 0x5000c000
-#elif defined(CONFIG_SYS_MX31_UART4)
-#define UART_PHYS 0x43fb0000
-#elif defined(CONFIG_SYS_MX31_UART5)
-#define UART_PHYS 0x43fb4000
-#else
-#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver"
-#endif
-
-/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx31) */
-
-/* UART Control Register Bit Fields.*/
-#define URXD_CHARRDY (1<<15)
-#define URXD_ERR (1<<14)
-#define URXD_OVRRUN (1<<13)
-#define URXD_FRMERR (1<<12)
-#define URXD_BRK (1<<11)
-#define URXD_PRERR (1<<10)
-#define URXD_RX_DATA (0xFF)
-#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
-#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
-#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
-#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
-#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
-#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
-#define UCR1_IREN (1<<7) /* Infrared interface enable */
-#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
-#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
-#define UCR1_SNDBRK (1<<4) /* Send break */
-#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
-#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
-#define UCR1_DOZE (1<<1) /* Doze */
-#define UCR1_UARTEN (1<<0) /* UART enabled */
-#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
-#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
-#define UCR2_CTSC (1<<13) /* CTS pin control */
-#define UCR2_CTS (1<<12) /* Clear to send */
-#define UCR2_ESCEN (1<<11) /* Escape enable */
-#define UCR2_PREN (1<<8) /* Parity enable */
-#define UCR2_PROE (1<<7) /* Parity odd/even */
-#define UCR2_STPB (1<<6) /* Stop */
-#define UCR2_WS (1<<5) /* Word size */
-#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
-#define UCR2_TXEN (1<<2) /* Transmitter enabled */
-#define UCR2_RXEN (1<<1) /* Receiver enabled */
-#define UCR2_SRST (1<<0) /* SW reset */
-#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
-#define UCR3_PARERREN (1<<12) /* Parity enable */
-#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
-#define UCR3_DSR (1<<10) /* Data set ready */
-#define UCR3_DCD (1<<9) /* Data carrier detect */
-#define UCR3_RI (1<<8) /* Ring indicator */
-#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
-#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
-#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
-#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
-#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
-#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
-#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
-#define UCR3_BPEN (1<<0) /* Preset registers enable */
-#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
-#define UCR4_INVR (1<<9) /* Inverted infrared reception */
-#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
-#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
-#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
-#define UCR4_IRSC (1<<5) /* IR special case */
-#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
-#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
-#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
-#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
-#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
-#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
-#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
-#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
-#define USR1_RTSD (1<<12) /* RTS delta */
-#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
-#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
-#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
-#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
-#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
-#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
-#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
-#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
-#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
-#define USR2_IDLE (1<<12) /* Idle condition */
-#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
-#define USR2_WAKE (1<<7) /* Wake */
-#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
-#define USR2_TXDC (1<<3) /* Transmitter complete */
-#define USR2_BRCD (1<<2) /* Break condition */
-#define USR2_ORE (1<<1) /* Overrun error */
-#define USR2_RDR (1<<0) /* Recv data ready */
-#define UTS_FRCPERR (1<<13) /* Force parity error */
-#define UTS_LOOP (1<<12) /* Loop tx and rx */
-#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
-#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
-#define UTS_SOFTRST (1<<0) /* Software reset */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg (void)
-{
- u32 clk = mx31_get_ipg_clk();
-
- if (!gd->baudrate)
- gd->baudrate = CONFIG_BAUDRATE;
-
- __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
- __REG(UART_PHYS + UBIR) = 0xf;
- __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
-
-}
-
-int serial_getc (void)
-{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
- return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
-}
-
-void serial_putc (const char c)
-{
- __REG(UART_PHYS + UTXD) = c;
-
- /* wait for transmitter to be ready */
- while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc ('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc (void)
-{
- /* If receive fifo is empty, return false */
- if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- return 0;
- return 1;
-}
-
-void
-serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
- __REG(UART_PHYS + UCR1) = 0x0;
- __REG(UART_PHYS + UCR2) = 0x0;
-
- while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
-
- __REG(UART_PHYS + UCR3) = 0x0704;
- __REG(UART_PHYS + UCR4) = 0x8000;
- __REG(UART_PHYS + UESC) = 0x002b;
- __REG(UART_PHYS + UTIM) = 0x0;
-
- __REG(UART_PHYS + UTS) = 0x0;
-
- serial_setbrg();
-
- __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
-
- __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
-
- return 0;
-}
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
new file mode 100644
index 0000000..acc5b7d
--- /dev/null
+++ b/drivers/serial/serial_mxc.c
@@ -0,0 +1,247 @@
+/*
+ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#ifdef CONFIG_MX31
+#include <asm/arch/mx31.h>
+#else
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#endif
+
+#define __REG(x) (*((volatile u32 *)(x)))
+
+#ifdef CONFIG_SYS_MX31_UART1
+#define UART_PHYS 0x43f90000
+#elif defined(CONFIG_SYS_MX31_UART2)
+#define UART_PHYS 0x43f94000
+#elif defined(CONFIG_SYS_MX31_UART3)
+#define UART_PHYS 0x5000c000
+#elif defined(CONFIG_SYS_MX31_UART4)
+#define UART_PHYS 0x43fb0000
+#elif defined(CONFIG_SYS_MX31_UART5)
+#define UART_PHYS 0x43fb4000
+#elif defined(CONFIG_SYS_MX27_UART1)
+#define UART_PHYS 0x1000a000
+#elif defined(CONFIG_SYS_MX27_UART2)
+#define UART_PHYS 0x1000b000
+#elif defined(CONFIG_SYS_MX27_UART3)
+#define UART_PHYS 0x1000c000
+#elif defined(CONFIG_SYS_MX27_UART4)
+#define UART_PHYS 0x1000d000
+#elif defined(CONFIG_SYS_MX27_UART5)
+#define UART_PHYS 0x1001b000
+#elif defined(CONFIG_SYS_MX27_UART6)
+#define UART_PHYS 0x1001c000
+#else
+#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver"
+#endif
+
+/* Register definitions */
+#define URXD 0x0 /* Receiver Register */
+#define UTXD 0x40 /* Transmitter Register */
+#define UCR1 0x80 /* Control Register 1 */
+#define UCR2 0x84 /* Control Register 2 */
+#define UCR3 0x88 /* Control Register 3 */
+#define UCR4 0x8c /* Control Register 4 */
+#define UFCR 0x90 /* FIFO Control Register */
+#define USR1 0x94 /* Status Register 1 */
+#define USR2 0x98 /* Status Register 2 */
+#define UESC 0x9c /* Escape Character Register */
+#define UTIM 0xa0 /* Escape Timer Register */
+#define UBIR 0xa4 /* BRM Incremental Register */
+#define UBMR 0xa8 /* BRM Modulator Register */
+#define UBRC 0xac /* Baud Rate Count Register */
+#define UTS 0xb4 /* UART Test Register (mx31) */
+
+/* UART Control Register Bit Fields.*/
+#define URXD_CHARRDY (1<<15)
+#define URXD_ERR (1<<14)
+#define URXD_OVRRUN (1<<13)
+#define URXD_FRMERR (1<<12)
+#define URXD_BRK (1<<11)
+#define URXD_PRERR (1<<10)
+#define URXD_RX_DATA (0xFF)
+#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
+#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
+#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
+#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
+#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
+#define UCR1_IREN (1<<7) /* Infrared interface enable */
+#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
+#define UCR1_SNDBRK (1<<4) /* Send break */
+#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
+#define UCR1_DOZE (1<<1) /* Doze */
+#define UCR1_UARTEN (1<<0) /* UART enabled */
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC (1<<13) /* CTS pin control */
+#define UCR2_CTS (1<<12) /* Clear to send */
+#define UCR2_ESCEN (1<<11) /* Escape enable */
+#define UCR2_PREN (1<<8) /* Parity enable */
+#define UCR2_PROE (1<<7) /* Parity odd/even */
+#define UCR2_STPB (1<<6) /* Stop */
+#define UCR2_WS (1<<5) /* Word size */
+#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
+#define UCR2_TXEN (1<<2) /* Transmitter enabled */
+#define UCR2_RXEN (1<<1) /* Receiver enabled */
+#define UCR2_SRST (1<<0) /* SW reset */
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
+#define UCR3_PARERREN (1<<12) /* Parity enable */
+#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
+#define UCR3_DSR (1<<10) /* Data set ready */
+#define UCR3_DCD (1<<9) /* Data carrier detect */
+#define UCR3_RI (1<<8) /* Ring indicator */
+#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
+#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
+#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
+#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
+#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
+#define UCR4_IRSC (1<<5) /* IR special case */
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
+#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
+#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
+#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD (1<<12) /* RTS delta */
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
+#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
+#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE (1<<12) /* Idle condition */
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
+#define USR2_WAKE (1<<7) /* Wake */
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
+#define USR2_TXDC (1<<3) /* Transmitter complete */
+#define USR2_BRCD (1<<2) /* Break condition */
+#define USR2_ORE (1<<1) /* Overrun error */
+#define USR2_RDR (1<<0) /* Recv data ready */
+#define UTS_FRCPERR (1<<13) /* Force parity error */
+#define UTS_LOOP (1<<12) /* Loop tx and rx */
+#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
+#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
+#define UTS_SOFTRST (1<<0) /* Software reset */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg (void)
+{
+#ifdef CONFIG_MX31
+ u32 clk = mx31_get_ipg_clk();
+#else
+ u32 clk = imx_get_perclk1();
+#endif
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
+ __REG(UART_PHYS + UBIR) = 0xf;
+ __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
+
+}
+
+int serial_getc (void)
+{
+ while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+ return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
+}
+
+void serial_putc (const char c)
+{
+ __REG(UART_PHYS + UTXD) = c;
+
+ /* wait for transmitter to be ready */
+ while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc ('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int serial_tstc (void)
+{
+ /* If receive fifo is empty, return false */
+ if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ return 0;
+ return 1;
+}
+
+void
+serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init (void)
+{
+ __REG(UART_PHYS + UCR1) = 0x0;
+ __REG(UART_PHYS + UCR2) = 0x0;
+
+ while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
+
+ __REG(UART_PHYS + UCR3) = 0x0704;
+ __REG(UART_PHYS + UCR4) = 0x8000;
+ __REG(UART_PHYS + UESC) = 0x002b;
+ __REG(UART_PHYS + UTIM) = 0x0;
+
+ __REG(UART_PHYS + UTS) = 0x0;
+
+ serial_setbrg();
+
+ __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
+
+ __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
+
+ return 0;
+}
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 9ac6eec..74f54c0 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -60,7 +60,7 @@
* Hardware drivers
*/
-#define CONFIG_MX31_UART 1
+#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
#define CONFIG_HARD_SPI 1
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index cbc0b92..cb42a7c 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -64,7 +64,7 @@
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
-#define CONFIG_MX31_UART 1
+#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
/* allow to overwrite serial and ethaddr */
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index c31c06a..363ea1b 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -57,7 +57,7 @@
* Hardware drivers
*/
-#define CONFIG_MX31_UART 1
+#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
#define CONFIG_HARD_SPI 1
diff --git a/include/configs/qong.h b/include/configs/qong.h
index a67006a..12bdc69 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -49,7 +49,7 @@
* Hardware drivers
*/
-#define CONFIG_MX31_UART 1
+#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
/* FPGA */
--
1.6.0.6
^ permalink raw reply related [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-05-19 23:55 [U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
2009-05-19 23:55 ` [U-Boot] [PATCH 1/7] mx27: basic cpu support Ilya Yanok
2009-05-19 23:55 ` [U-Boot] [PATCH 2/7] serial_mx31: allow it to work with mx27 too and rename to serial_mxc Ilya Yanok
@ 2009-05-19 23:55 ` Ilya Yanok
2009-05-26 5:38 ` Ben Warren
2009-06-15 14:01 ` Johan
2009-05-19 23:55 ` [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3 Ilya Yanok
` (4 subsequent siblings)
7 siblings, 2 replies; 42+ messages in thread
From: Ilya Yanok @ 2009-05-19 23:55 UTC (permalink / raw)
To: u-boot
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
cpu/arm926ejs/mx27/generic.c | 10 +
drivers/net/Makefile | 1 +
drivers/net/fec_imx27.c | 705 ++++++++++++++++++++++++++++++++++++++++++
drivers/net/fec_imx27.h | 302 ++++++++++++++++++
include/netdev.h | 1 +
5 files changed, 1019 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/fec_imx27.c
create mode 100644 drivers/net/fec_imx27.h
diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
index 850d5e6..e820d94 100644
--- a/cpu/arm926ejs/mx27/generic.c
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -20,6 +20,7 @@
#include <common.h>
#include <div64.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
@@ -159,6 +160,15 @@ int print_cpuinfo (void)
}
#endif
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FEC_IMX27)
+ return fecimx27_initialize(bis);
+#else
+ return 0;
+#endif
+}
+
void imx_gpio_mode(int gpio_mode)
{
struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a360a50..ac68beb 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
COBJS-$(CONFIG_TULIP) += dc2114x.o
COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
COBJS-$(CONFIG_DNET) += dnet.o
+COBJS-$(CONFIG_FEC_IMX27) += fec_imx27.o
COBJS-$(CONFIG_E1000) += e1000.o
COBJS-$(CONFIG_EEPRO100) += eepro100.o
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
diff --git a/drivers/net/fec_imx27.c b/drivers/net/fec_imx27.c
new file mode 100644
index 0000000..4ade348
--- /dev/null
+++ b/drivers/net/fec_imx27.c
@@ -0,0 +1,705 @@
+/*
+ * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
+ * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
+ * (C) Copyright 2008 Armadeus Systems nc
+ * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <miiphy.h>
+#include "fec_imx27.h"
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_MII
+#error "CONFIG_MII has to be defined!"
+#endif
+
+#undef DEBUG
+
+struct nbuf {
+ uint8_t data[1500]; /**< actual data */
+ int length; /**< actual length */
+ int used; /**< buffer in use or not */
+ uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
+};
+
+struct fec_priv gfec = {
+ .eth = (struct ethernet_regs *)IMX_FEC_BASE,
+ .xcv_type = MII100,
+ .rbd_base = NULL,
+ .rbd_index = 0,
+ .tbd_base = NULL,
+ .tbd_index = 0,
+ .bd = NULL,
+};
+
+/*
+ * MII-interface related functions
+ */
+static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
+ uint16_t *retVal)
+{
+ struct eth_device *edev = eth_get_dev_by_name(dev);
+ struct fec_priv *fec = (struct fec_priv *)edev->priv;
+
+ uint32_t reg; /* convenient holder for the PHY register */
+ uint32_t phy; /* convenient holder for the PHY */
+ uint32_t start;
+
+ /*
+ * reading from any PHY's register is done by properly
+ * programming the FEC's MII data register.
+ */
+ writel(FEC_IEVENT_MII, &fec->eth->ievent);
+ reg = regAddr << FEC_MII_DATA_RA_SHIFT;
+ phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
+
+ writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
+ phy | reg, &fec->eth->mii_data);
+
+ /*
+ * wait for the related interrupt
+ */
+ start = get_timer_masked();
+ while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
+ if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ printf("Read MDIO failed...\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear mii interrupt bit
+ */
+ writel(FEC_IEVENT_MII, &fec->eth->ievent);
+
+ /*
+ * it's now safe to read the PHY's register
+ */
+ *retVal = readl(&fec->eth->mii_data);
+ debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
+ regAddr, *retVal);
+ return 0;
+}
+
+static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
+ uint16_t data)
+{
+ struct eth_device *edev = eth_get_dev_by_name(dev);
+ struct fec_priv *fec = (struct fec_priv *)edev->priv;
+
+ uint32_t reg; /* convenient holder for the PHY register */
+ uint32_t phy; /* convenient holder for the PHY */
+ uint32_t start;
+
+ reg = regAddr << FEC_MII_DATA_RA_SHIFT;
+ phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
+
+ writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
+ FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
+
+ /*
+ * wait for the MII interrupt
+ */
+ start = get_timer_masked();
+ while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
+ if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ printf("Write MDIO failed...\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear MII interrupt bit
+ */
+ writel(FEC_IEVENT_MII, &fec->eth->ievent);
+ debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
+ regAddr, data);
+
+ return 0;
+}
+
+static int miiphy_restart_aneg(struct eth_device *dev)
+{
+ /*
+ * Wake up from sleep if necessary
+ * Reset PHY, then delay 300ns
+ */
+ miiphy_write(dev->name, 0, PHY_MIPGSR, 0x00FF);
+ miiphy_write(dev->name, 0, PHY_BMCR, PHY_BMCR_RESET);
+ udelay(1000);
+
+ /*
+ * Set the auto-negotiation advertisement register bits
+ */
+ miiphy_write(dev->name, 0, PHY_ANAR, 0x1e0);
+ miiphy_write(dev->name, 0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+ return 0;
+}
+
+static int miiphy_wait_aneg(struct eth_device *dev)
+{
+ uint32_t start;
+ uint16_t status;
+
+ /*
+ * Wait for AN completion
+ */
+ start = get_timer_masked(); /* get_time_ns(); */
+ do {
+ if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
+ printf("%s: Autonegotiation timeout\n", dev->name);
+ return -1;
+ }
+
+ if (miiphy_read(dev->name, 0, PHY_BMSR, &status)) {
+ printf("%s: Autonegotiation failed. status: 0x%04x\n",
+ dev->name, status);
+ return -1;
+ }
+ } while (!(status & PHY_BMSR_LS));
+
+ return 0;
+}
+static int fec_rx_task_enable(struct fec_priv *fec)
+{
+ writel(1 << 24, &fec->eth->r_des_active);
+ return 0;
+}
+
+static int fec_rx_task_disable(struct fec_priv *fec)
+{
+ return 0;
+}
+
+static int fec_tx_task_enable(struct fec_priv *fec)
+{
+ writel(1 << 24, &fec->eth->x_des_active);
+ return 0;
+}
+
+static int fec_tx_task_disable(struct fec_priv *fec)
+{
+ return 0;
+}
+
+/**
+ * Initialize receive task's buffer descriptors
+ * @param[in] fec all we know about the device yet
+ * @param[in] count receive buffer count to be allocated
+ * @param[in] size size of each receive buffer
+ * @return 0 on success
+ *
+ * For this task we need additional memory for the data buffers. And each
+ * data buffer requires some alignment. Thy must be aligned to a specific
+ * boundary each (DB_DATA_ALIGNMENT).
+ */
+static int fec_rbd_init(struct fec_priv *fec, int count, int size, int once)
+{
+ int ix;
+ uint32_t p = 0;
+
+ if (!once) {
+ /* reserve data memory and consider alignment */
+ p = (uint32_t)malloc(size * count + DB_DATA_ALIGNMENT);
+ memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
+ p += DB_DATA_ALIGNMENT-1;
+ p &= ~(DB_DATA_ALIGNMENT-1);
+ }
+
+ for (ix = 0; ix < count; ix++) {
+ if (!once) {
+ writel(p, &fec->rbd_base[ix].data_pointer);
+ p += size;
+ }
+ writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
+ writew(0, &fec->rbd_base[ix].data_length);
+ }
+ /*
+ * mark the last RBD to close the ring
+ */
+ writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
+ fec->rbd_index = 0;
+
+ return 0;
+}
+
+/**
+ * Initialize transmit task's buffer descriptors
+ * @param[in] fec all we know about the device yet
+ *
+ * Transmit buffers are created externally. We only have to init the BDs here.\n
+ * Note: There is a race condition in the hardware. When only one BD is in
+ * use it must be marked with the WRAP bit to use it for every transmitt.
+ * This bit in combination with the READY bit results into double transmit
+ * of each data buffer. It seems the state machine checks READY earlier then
+ * resetting it after the first transfer.
+ * Using two BDs solves this issue.
+ */
+static void fec_tbd_init(struct fec_priv *fec)
+{
+ writew(0x0000, &fec->tbd_base[0].status);
+ writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
+ fec->tbd_index = 0;
+}
+
+/**
+ * Mark the given read buffer descriptor as free
+ * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
+ * @param[in] pRbd buffer descriptor to mark free again
+ */
+static void fec_rbd_clean(int last, struct fec_bd *pRbd)
+{
+ /*
+ * Reset buffer descriptor as empty
+ */
+ if (last)
+ writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
+ else
+ writew(FEC_RBD_EMPTY, &pRbd->status);
+ /*
+ * no data in it
+ */
+ writew(0, &pRbd->data_length);
+}
+
+static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ int i;
+
+ for (i = 0; i < 6; i++)
+ mac[6-1-i] = readl(&iim->IIM_BANK_AREA0[IIM0_MAC + i]);
+
+ return is_valid_ether_addr(mac);
+}
+
+static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
+{
+ struct fec_priv *fec = (struct fec_priv *)dev->priv;
+
+ writel(0, &fec->eth->iaddr1);
+ writel(0, &fec->eth->iaddr2);
+ writel(0, &fec->eth->gaddr1);
+ writel(0, &fec->eth->gaddr2);
+
+ /*
+ * Set physical address
+ */
+ writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
+ &fec->eth->paddr1);
+ writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
+
+ return 0;
+}
+
+/**
+ * Start the FEC engine
+ * @param[in] dev Our device to handle
+ */
+static int fec_open(struct eth_device *edev)
+{
+ struct fec_priv *fec = (struct fec_priv *)edev->priv;
+
+ debug("fec_open: fec_open(dev)\n");
+ /* full-duplex, heartbeat disabled */
+ writel(1 << 2, &fec->eth->x_cntrl);
+ fec->rbd_index = 0;
+
+ /*
+ * Enable FEC-Lite controller
+ */
+ writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
+
+ miiphy_wait_aneg(edev);
+ miiphy_speed(edev->name, 0);
+ miiphy_duplex(edev->name, 0);
+
+ /*
+ * Enable SmartDMA receive task
+ */
+ fec_rx_task_enable(fec);
+
+ udelay(100000);
+ return 0;
+}
+
+static int fec_init(struct eth_device *dev, bd_t* bd)
+{
+ static int once;
+ uint32_t base;
+ struct fec_priv *fec = (struct fec_priv *)dev->priv;
+
+ if (!once) {
+ /*
+ * reserve memory for both buffer descriptor chains at once
+ * Datasheet forces the startaddress of each chain is 16 byte
+ * aligned
+ */
+ base = (uint32_t)malloc((2 + FEC_RBD_NUM) *
+ sizeof(struct fec_bd) + DB_ALIGNMENT);
+ memset((void *)base, 0, (2 + FEC_RBD_NUM) *
+ sizeof(struct fec_bd) + DB_ALIGNMENT);
+ base += (DB_ALIGNMENT-1);
+ base &= ~(DB_ALIGNMENT-1);
+
+ fec->rbd_base = (struct fec_bd *)base;
+
+ base += FEC_RBD_NUM * sizeof(struct fec_bd);
+
+ fec->tbd_base = (struct fec_bd *)base;
+ }
+
+ /*
+ * Set interrupt mask register
+ */
+ writel(0x00000000, &fec->eth->imask);
+
+ /*
+ * Clear FEC-Lite interrupt event register(IEVENT)
+ */
+ writel(0xffffffff, &fec->eth->ievent);
+
+
+ /*
+ * Set FEC-Lite receive control register(R_CNTRL):
+ */
+ if (fec->xcv_type == SEVENWIRE) {
+ /*
+ * Frame length=1518; 7-wire mode
+ */
+ writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */
+ } else {
+ /*
+ * Frame length=1518; MII mode;
+ */
+ writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
+ /*
+ * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
+ * and do not drop the Preamble.
+ */
+ writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
+ &fec->eth->mii_speed);
+ debug("fec_init: mii_speed %#lx\n",
+ (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
+ }
+ /*
+ * Set Opcode/Pause Duration Register
+ */
+ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
+ writel(0x2, &fec->eth->x_wmrk);
+ /*
+ * Set multicast address filter
+ */
+ writel(0x00000000, &fec->eth->gaddr1);
+ writel(0x00000000, &fec->eth->gaddr2);
+
+
+ /* clear MIB RAM */
+ long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
+ while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
+ *mib_ptr++ = 0;
+
+ /* FIFO receive start register */
+ writel(0x520, &fec->eth->r_fstart);
+
+ /* size and address of each buffer */
+ writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
+ writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
+ writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
+
+ /*
+ * Initialize RxBD/TxBD rings
+ */
+ fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE, once);
+ fec_tbd_init(fec);
+
+
+ if (fec->xcv_type != SEVENWIRE)
+ miiphy_restart_aneg(dev);
+
+ once = 1; /* malloc done now (and once) */
+
+ fec_open(dev);
+ return 0;
+}
+
+/**
+ * Halt the FEC engine
+ * @param[in] dev Our device to handle
+ */
+static void fec_halt(struct eth_device *dev)
+{
+ struct fec_priv *fec = &gfec;
+ int counter = 0xffff;
+
+ /*
+ * issue graceful stop command to the FEC transmitter if necessary
+ */
+ writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
+ &fec->eth->x_cntrl);
+
+ debug("eth_halt: wait for stop regs\n");
+ /*
+ * wait for graceful stop to register
+ */
+ while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
+ ; /* FIXME ensure time */
+
+ /*
+ * Disable SmartDMA tasks
+ */
+ fec_tx_task_disable(fec);
+ fec_rx_task_disable(fec);
+
+ /*
+ * Disable the Ethernet Controller
+ * Note: this will also reset the BD index counter!
+ */
+ writel(0, &fec->eth->ecntrl);
+ fec->rbd_index = 0;
+ fec->tbd_index = 0;
+ debug("eth_halt: done\n");
+}
+
+/**
+ * Transmit one frame
+ * @param[in] dev Our ethernet device to handle
+ * @param[in] packet Pointer to the data to be transmitted
+ * @param[in] length Data count in bytes
+ * @return 0 on success
+ */
+static int fec_send(struct eth_device *dev, volatile void* packet, int length)
+{
+ unsigned int status;
+
+ /*
+ * This routine transmits one frame. This routine only accepts
+ * 6-byte Ethernet addresses.
+ */
+ struct fec_priv *fec = (struct fec_priv *)dev->priv;
+
+ /*
+ * Check for valid length of data.
+ */
+ if ((length > 1500) || (length <= 0)) {
+ printf("Payload (%d) to large!\n", length);
+ return -1;
+ }
+
+ /*
+ * Setup the transmit buffer
+ * Note: We are always using the first buffer for transmission,
+ * the second will be empty and only used to stop the DMA engine
+ */
+ writew(length, &fec->tbd_base[fec->tbd_index].data_length);
+ writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
+ /*
+ * update BD's status now
+ * This block:
+ * - is always the last in a chain (means no chain)
+ * - should transmitt the CRC
+ * - might be the last BD in the list, so the address counter should
+ * wrap (-> keep the WRAP flag)
+ */
+ status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
+ status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
+ writew(status, &fec->tbd_base[fec->tbd_index].status);
+
+ /*
+ * Enable SmartDMA transmit task
+ */
+ fec_tx_task_enable(fec);
+
+ /*
+ * wait until frame is sent .
+ */
+ while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
+ /* FIXME: Timeout */
+ }
+ debug("fec_send: status 0x%x index %d\n",
+ readw(&fec->tbd_base[fec->tbd_index].status),
+ fec->tbd_index);
+ /* for next transmission use the other buffer */
+ if (fec->tbd_index)
+ fec->tbd_index = 0;
+ else
+ fec->tbd_index = 1;
+
+ return 0;
+}
+
+/**
+ * Pull one frame from the card
+ * @param[in] dev Our ethernet device to handle
+ * @return Length of packet read
+ */
+static int fec_recv(struct eth_device *dev)
+{
+ struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
+ unsigned long ievent;
+ int frame_length, len = 0;
+ struct nbuf *frame;
+ uint16_t bd_status;
+ uchar buff[FEC_MAX_PKT_SIZE];
+
+ /*
+ * Check if any critical events have happened
+ */
+ ievent = readl(&fec->eth->ievent);
+ writel(ievent, &fec->eth->ievent);
+ debug("fec_recv: ievent 0x%x\n", ievent);
+ if (ievent & FEC_IEVENT_BABR) {
+ fec_halt(dev);
+ fec_init(dev, fec->bd);
+ printf("some error: 0x%08lx\n", ievent);
+ return 0;
+ }
+ if (ievent & FEC_IEVENT_HBERR) {
+ /* Heartbeat error */
+ writel(0x00000001 | readl(&fec->eth->x_cntrl),
+ &fec->eth->x_cntrl);
+ }
+ if (ievent & FEC_IEVENT_GRA) {
+ /* Graceful stop complete */
+ if (readl(&fec->eth->x_cntrl) & 0x00000001) {
+ fec_halt(dev);
+ writel(~0x00000001 & readl(&fec->eth->x_cntrl),
+ &fec->eth->x_cntrl);
+ fec_init(dev, fec->bd);
+ }
+ }
+
+ /*
+ * ensure reading the right buffer status
+ */
+ bd_status = readw(&rbd->status);
+ debug("fec_recv: status 0x%x\n", bd_status);
+
+ if (!(bd_status & FEC_RBD_EMPTY)) {
+ if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
+ ((readw(&rbd->data_length) - 4) > 14)) {
+ /*
+ * Get buffer address and size
+ */
+ frame = (struct nbuf *)readl(&rbd->data_pointer);
+ frame_length = readw(&rbd->data_length) - 4;
+ /*
+ * Fill the buffer and pass it to upper layers
+ */
+ memcpy(buff, frame->data, frame_length);
+ NetReceive(buff, frame_length);
+ len = frame_length;
+ } else {
+ if (bd_status & FEC_RBD_ERR)
+ printf("error frame: 0x%08lx 0x%08x\n",
+ (ulong)rbd->data_pointer,
+ bd_status);
+ }
+ /*
+ * free the current buffer, restart the engine
+ * and move forward to the next buffer
+ */
+ fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
+ fec_rx_task_enable(fec);
+ fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
+ }
+ debug("fec_recv: stop\n");
+
+ return len;
+}
+
+static int fec_probe(bd_t *bd)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ struct eth_device *edev;
+ struct fec_priv *fec = &gfec;
+ unsigned char ethaddr_str[20];
+ unsigned char ethaddr[6];
+ char *tmp = getenv("ethaddr");
+ char *end;
+
+ /* enable FEC clock */
+ writel(readl(&pll->PCCR1) | PCCR1_HCLK_FEC, &pll->PCCR1);
+ writel(readl(&pll->PCCR0) | PCCR0_FEC_EN, &pll->PCCR0);
+
+ /* create and fill edev struct */
+ edev = (struct eth_device *)malloc(sizeof(struct eth_device));
+ edev->priv = fec;
+ edev->init = fec_init;
+ edev->send = fec_send;
+ edev->recv = fec_recv;
+ edev->halt = fec_halt;
+
+ fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
+ fec->bd = bd;
+
+ /* Reset chip. */
+ writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
+ while (readl(&fec->eth->ecntrl) & 1)
+ udelay(10);
+
+ fec->xcv_type = MII100;
+
+ sprintf(edev->name, "FEC ETHERNET");
+
+ miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
+
+ eth_register(edev);
+
+ if ((NULL != tmp) && (12 <= strlen(tmp))) {
+ int i;
+ /* convert MAC from string to int */
+ for (i = 0; i < 6; i++) {
+ ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+ if (tmp)
+ tmp = (*end) ? end + 1 : end;
+ }
+ } else if (fec_get_hwaddr(edev, ethaddr) == 0) {
+ printf("got MAC address from EEPROM: %pM\n", ethaddr);
+ setenv("ethaddr", (char *)ethaddr_str);
+ }
+ memcpy(edev->enetaddr, ethaddr, 6);
+ fec_set_hwaddr(edev, ethaddr);
+
+ return 0;
+}
+
+int fecimx27_initialize(bd_t *bd)
+{
+ int lout = 1;
+ static int once;
+
+ if (!once) {
+ debug("eth_init: fec_probe(bd)\n");
+ lout = fec_probe(bd);
+ once = 1;
+ }
+ return lout;
+}
+
diff --git a/drivers/net/fec_imx27.h b/drivers/net/fec_imx27.h
new file mode 100644
index 0000000..926c0d7
--- /dev/null
+++ b/drivers/net/fec_imx27.h
@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
+ * (C) Copyright 2008 Armadeus Systems, nc
+ * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * This file is based on mpc4200fec.h
+ * (C) Copyright Motorola, Inc., 2000
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+
+#ifndef __IMX27_FEC_H
+#define __IMX27_FEC_H
+
+/**
+ * Layout description of the FEC
+ */
+struct ethernet_regs {
+
+/* [10:2]addr = 00 */
+
+/* Control and status Registers (offset 000-1FF) */
+
+ uint32_t RES0[1]; /* MBAR_ETH + 0x000 */
+ uint32_t ievent; /* MBAR_ETH + 0x004 */
+ uint32_t imask; /* MBAR_ETH + 0x008 */
+
+ uint32_t RES1[1]; /* MBAR_ETH + 0x00C */
+ uint32_t r_des_active; /* MBAR_ETH + 0x010 */
+ uint32_t x_des_active; /* MBAR_ETH + 0x014 */
+ uint32_t RES2[3]; /* MBAR_ETH + 0x018-20 */
+ uint32_t ecntrl; /* MBAR_ETH + 0x024 */
+
+ uint32_t RES3[6]; /* MBAR_ETH + 0x028-03C */
+ uint32_t mii_data; /* MBAR_ETH + 0x040 */
+ uint32_t mii_speed; /* MBAR_ETH + 0x044 */
+ uint32_t RES4[7]; /* MBAR_ETH + 0x048-60 */
+ uint32_t mib_control; /* MBAR_ETH + 0x064 */
+
+ uint32_t RES5[7]; /* MBAR_ETH + 0x068-80 */
+ uint32_t r_cntrl; /* MBAR_ETH + 0x084 */
+ uint32_t RES6[15]; /* MBAR_ETH + 0x088-C0 */
+ uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */
+ uint32_t RES7[7]; /* MBAR_ETH + 0x0C8-E0 */
+ uint32_t paddr1; /* MBAR_ETH + 0x0E4 */
+ uint32_t paddr2; /* MBAR_ETH + 0x0E8 */
+ uint32_t op_pause; /* MBAR_ETH + 0x0EC */
+
+ uint32_t RES8[10]; /* MBAR_ETH + 0x0F0-114 */
+ uint32_t iaddr1; /* MBAR_ETH + 0x118 */
+ uint32_t iaddr2; /* MBAR_ETH + 0x11C */
+ uint32_t gaddr1; /* MBAR_ETH + 0x120 */
+ uint32_t gaddr2; /* MBAR_ETH + 0x124 */
+ uint32_t RES9[7]; /* MBAR_ETH + 0x128-140 */
+
+ uint32_t x_wmrk; /* MBAR_ETH + 0x144 */
+ uint32_t RES10[1]; /* MBAR_ETH + 0x148 */
+ uint32_t r_bound; /* MBAR_ETH + 0x14C */
+ uint32_t r_fstart; /* MBAR_ETH + 0x150 */
+ uint32_t RES11[11]; /* MBAR_ETH + 0x154-17C */
+ uint32_t erdsr; /* MBAR_ETH + 0x180 */
+ uint32_t etdsr; /* MBAR_ETH + 0x184 */
+ uint32_t emrbr; /* MBAR_ETH + 0x188 */
+ uint32_t RES12[29]; /* MBAR_ETH + 0x18C-1FC */
+
+/* MIB COUNTERS (Offset 200-2FF) */
+
+ uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */
+ uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */
+ uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
+ uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
+ uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */
+ uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */
+ uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */
+ uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */
+ uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */
+ uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */
+ uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */
+ uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */
+ uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */
+ uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */
+ uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
+ uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
+ uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
+ uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */
+ uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */
+ uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
+ uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */
+ uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */
+ uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */
+ uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */
+ uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */
+ uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */
+ uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */
+ uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */
+ uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */
+ uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
+
+ uint32_t RES13[2]; /* MBAR_ETH + 0x278-27C */
+ uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */
+ uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */
+ uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
+ uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
+ uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */
+ uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */
+ uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */
+ uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */
+ uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */
+
+ uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
+
+ uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */
+ uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
+ uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
+ uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
+ uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
+ uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
+ uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
+ uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */
+ uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */
+ uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
+ uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */
+ uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */
+ uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */
+ uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */
+ uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
+
+ uint32_t RES14[6]; /* MBAR_ETH + 0x2E4-2FC */
+
+ uint32_t RES15[64]; /* MBAR_ETH + 0x300-3FF */
+};
+
+#define FEC_IEVENT_HBERR 0x80000000
+#define FEC_IEVENT_BABR 0x40000000
+#define FEC_IEVENT_BABT 0x20000000
+#define FEC_IEVENT_GRA 0x10000000
+#define FEC_IEVENT_TXF 0x08000000
+#define FEC_IEVENT_TXB 0x04000000
+#define FEC_IEVENT_RXF 0x02000000
+#define FEC_IEVENT_RXB 0x01000000
+#define FEC_IEVENT_MII 0x00800000
+#define FEC_IEVENT_EBERR 0x00400000
+#define FEC_IEVENT_LC 0x00200000
+#define FEC_IEVENT_RL 0x00100000
+#define FEC_IEVENT_UN 0x00080000
+
+#define FEC_IMASK_HBERR 0x80000000
+#define FEC_IMASK_BABR 0x40000000
+#define FEC_IMASKT_BABT 0x20000000
+#define FEC_IMASK_GRA 0x10000000
+#define FEC_IMASKT_TXF 0x08000000
+#define FEC_IMASK_TXB 0x04000000
+#define FEC_IMASKT_RXF 0x02000000
+#define FEC_IMASK_RXB 0x01000000
+#define FEC_IMASK_MII 0x00800000
+#define FEC_IMASK_EBERR 0x00400000
+#define FEC_IMASK_LC 0x00200000
+#define FEC_IMASKT_RL 0x00100000
+#define FEC_IMASK_UN 0x00080000
+
+
+#define FEC_RCNTRL_MAX_FL_SHIFT 16
+#define FEC_RCNTRL_LOOP 0x00000001
+#define FEC_RCNTRL_DRT 0x00000002
+#define FEC_RCNTRL_MII_MODE 0x00000004
+#define FEC_RCNTRL_PROM 0x00000008
+#define FEC_RCNTRL_BC_REJ 0x00000010
+#define FEC_RCNTRL_FCE 0x00000020
+
+#define FEC_TCNTRL_GTS 0x00000001
+#define FEC_TCNTRL_HBC 0x00000002
+#define FEC_TCNTRL_FDEN 0x00000004
+#define FEC_TCNTRL_TFC_PAUSE 0x00000008
+#define FEC_TCNTRL_RFC_PAUSE 0x00000010
+
+#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
+#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
+
+/**
+ * @brief Descriptor buffer alignment
+ *
+ * i.MX27 requires a 16 byte alignment (but for the first element only)
+ */
+#define DB_ALIGNMENT 16
+
+/**
+ * @brief Data buffer alignment
+ *
+ * i.MX27 requires a four byte alignment for transmit and 16 bits
+ * alignment for receive so take 16
+ * Note: Valid for member data_pointer in struct buffer_descriptor
+ */
+#define DB_DATA_ALIGNMENT 16
+
+/**
+ * @brief Receive & Transmit Buffer Descriptor definitions
+ *
+ * Note: The first BD must be aligned (see DB_ALIGNMENT)
+ */
+struct fec_bd {
+ uint16_t data_length; /* payload's length in bytes */
+ uint16_t status; /* BD's staus (see datasheet) */
+ uint32_t data_pointer; /* payload's buffer address */
+};
+
+/**
+ * Supported phy types on this platform
+ */
+enum xceiver_type {
+ SEVENWIRE, /* 7-wire */
+ MII10, /* MII 10Mbps */
+ MII100 /* MII 100Mbps */
+};
+
+/**
+ * @brief i.MX27-FEC private structure
+ */
+struct fec_priv {
+ struct ethernet_regs *eth; /* pointer to register'S base */
+ enum xceiver_type xcv_type; /* transceiver type */
+ struct fec_bd *rbd_base; /* RBD ring */
+ int rbd_index; /* next receive BD to read */
+ struct fec_bd *tbd_base; /* TBD ring */
+ int tbd_index; /* next transmit BD to write */
+ bd_t *bd;
+};
+
+/**
+ * @brief Numbers of buffer descriptors for receiving
+ *
+ * The number defines the stocked memory buffers for the receiving task.
+ * Larger values makes no sense in this limited environment.
+ */
+#define FEC_RBD_NUM 64
+
+/**
+ * @brief Define the ethernet packet size limit in memory
+ *
+ * Note: Do not shrink this number. This will force the FEC to spread larger
+ * frames in more than one BD. This is nothing to worry about, but the current
+ * driver can't handle it.
+ */
+#define FEC_MAX_PKT_SIZE 1536
+
+/* Receive BD status bits */
+#define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */
+#define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */
+/* Receive BD status: Buffer is last in frame (useless here!) */
+#define FEC_RBD_LAST 0x0800
+#define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */
+/* Receive BD status: The received frame is broadcast frame */
+#define FEC_RBD_BC 0x0080
+/* Receive BD status: The received frame is multicast frame */
+#define FEC_RBD_MC 0x0040
+#define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */
+#define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */
+#define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */
+#define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */
+#define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */
+#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
+ FEC_RBD_OV | FEC_RBD_TR)
+
+/* Transmit BD status bits */
+#define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */
+#define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */
+#define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */
+#define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */
+#define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */
+
+/* MII-related definitios */
+#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
+#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
+#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
+#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
+#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
+#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
+#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
+
+#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
+#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
+
+#endif /* __IMX27_FEC_H */
diff --git a/include/netdev.h b/include/netdev.h
index 63cf730..2d999ad 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -49,6 +49,7 @@ int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
int eth_3com_initialize (bd_t * bis);
int fec_initialize (bd_t *bis);
+int fecimx27_initialize (bd_t *bis);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
--
1.6.0.6
^ permalink raw reply related [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-05-19 23:55 ` [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27 Ilya Yanok
@ 2009-05-26 5:38 ` Ben Warren
2009-06-07 23:08 ` Ilya Yanok
2009-11-17 2:46 ` alfred steele
2009-06-15 14:01 ` Johan
1 sibling, 2 replies; 42+ messages in thread
From: Ben Warren @ 2009-05-26 5:38 UTC (permalink / raw)
To: u-boot
Hi Ilya,
Thanks for making all the improvements:
Ilya Yanok wrote:
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---
> cpu/arm926ejs/mx27/generic.c | 10 +
> drivers/net/Makefile | 1 +
> drivers/net/fec_imx27.c | 705 ++++++++++++++++++++++++++++++++++++++++++
> drivers/net/fec_imx27.h | 302 ++++++++++++++++++
> include/netdev.h | 1 +
> 5 files changed, 1019 insertions(+), 0 deletions(-)
> create mode 100644 drivers/net/fec_imx27.c
> create mode 100644 drivers/net/fec_imx27.h
>
>
Naive question: Is this FEC truly unique to the iMX27? If not you
should pick a more generic name.
<snip>
> diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
> index 850d5e6..e820d94 100644
> --- a/cpu/arm926ejs/mx27/generic.c
> +++ b/cpu/arm926ejs/mx27/generic.c
> @@ -20,6 +20,7 @@
>
> #include <common.h>
> #include <div64.h>
> +#include <netdev.h>
> #include <asm/io.h>
> #include <asm/arch/imx-regs.h>
>
> @@ -159,6 +160,15 @@ int print_cpuinfo (void)
> }
> #endif
>
> +int cpu_eth_init(bd_t *bis)
> +{
> +#if defined(CONFIG_FEC_IMX27)
> + return fecimx27_initialize(bis);
> +#else
> + return 0;
> +#endif
> +}
> +
> void imx_gpio_mode(int gpio_mode)
> {
> struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index a360a50..ac68beb 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
> COBJS-$(CONFIG_TULIP) += dc2114x.o
> COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
> COBJS-$(CONFIG_DNET) += dnet.o
> +COBJS-$(CONFIG_FEC_IMX27) += fec_imx27.o
>
Please keep this sorted alphabetically.
> COBJS-$(CONFIG_E1000) += e1000.o
> COBJS-$(CONFIG_EEPRO100) += eepro100.o
> COBJS-$(CONFIG_ENC28J60) += enc28j60.o
> diff --git a/drivers/net/fec_imx27.c b/drivers/net/fec_imx27.c
> new file mode 100644
> index 0000000..4ade348
> --- /dev/null
> +++ b/drivers/net/fec_imx27.c
> @@ -0,0 +1,705 @@
> +/*
> + * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
> + * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
> + * (C) Copyright 2008 Armadeus Systems nc
> + * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <net.h>
> +#include <miiphy.h>
> +#include "fec_imx27.h"
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifndef CONFIG_MII
> +#error "CONFIG_MII has to be defined!"
> +#endif
> +
> +#undef DEBUG
> +
> +struct nbuf {
> + uint8_t data[1500]; /**< actual data */
>
I think 'u8' and friends are more commonly used in U-boot, but am not
too fussy about this.
> + int length; /**< actual length */
> + int used; /**< buffer in use or not */
> + uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
> +};
> +
> +struct fec_priv gfec = {
> + .eth = (struct ethernet_regs *)IMX_FEC_BASE,
> + .xcv_type = MII100,
> + .rbd_base = NULL,
> + .rbd_index = 0,
> + .tbd_base = NULL,
> + .tbd_index = 0,
> + .bd = NULL,
> +};
> +
> +/*
> + * MII-interface related functions
> + */
> +static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
> + uint16_t *retVal)
> +{
> + struct eth_device *edev = eth_get_dev_by_name(dev);
> + struct fec_priv *fec = (struct fec_priv *)edev->priv;
> +
> + uint32_t reg; /* convenient holder for the PHY register */
> + uint32_t phy; /* convenient holder for the PHY */
> + uint32_t start;
> +
> + /*
> + * reading from any PHY's register is done by properly
> + * programming the FEC's MII data register.
> + */
> + writel(FEC_IEVENT_MII, &fec->eth->ievent);
> + reg = regAddr << FEC_MII_DATA_RA_SHIFT;
> + phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
> +
> + writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
> + phy | reg, &fec->eth->mii_data);
> +
> + /*
> + * wait for the related interrupt
> + */
> + start = get_timer_masked();
> + while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
> + if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
> + printf("Read MDIO failed...\n");
> + return -1;
> + }
> + }
> +
> + /*
> + * clear mii interrupt bit
> + */
> + writel(FEC_IEVENT_MII, &fec->eth->ievent);
> +
> + /*
> + * it's now safe to read the PHY's register
> + */
> + *retVal = readl(&fec->eth->mii_data);
> + debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
> + regAddr, *retVal);
> + return 0;
> +}
> +
> +static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
> + uint16_t data)
> +{
> + struct eth_device *edev = eth_get_dev_by_name(dev);
> + struct fec_priv *fec = (struct fec_priv *)edev->priv;
> +
> + uint32_t reg; /* convenient holder for the PHY register */
> + uint32_t phy; /* convenient holder for the PHY */
> + uint32_t start;
> +
> + reg = regAddr << FEC_MII_DATA_RA_SHIFT;
> + phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
> +
> + writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
> + FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
> +
> + /*
> + * wait for the MII interrupt
> + */
> + start = get_timer_masked();
> + while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
> + if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
> + printf("Write MDIO failed...\n");
> + return -1;
> + }
> + }
> +
> + /*
> + * clear MII interrupt bit
> + */
> + writel(FEC_IEVENT_MII, &fec->eth->ievent);
> + debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
> + regAddr, data);
> +
> + return 0;
> +}
> +
> +static int miiphy_restart_aneg(struct eth_device *dev)
> +{
> + /*
> + * Wake up from sleep if necessary
> + * Reset PHY, then delay 300ns
> + */
> + miiphy_write(dev->name, 0, PHY_MIPGSR, 0x00FF);
> + miiphy_write(dev->name, 0, PHY_BMCR, PHY_BMCR_RESET);
> + udelay(1000);
> +
> + /*
> + * Set the auto-negotiation advertisement register bits
> + */
> + miiphy_write(dev->name, 0, PHY_ANAR, 0x1e0);
> + miiphy_write(dev->name, 0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
> +
> + return 0;
> +}
> +
> +static int miiphy_wait_aneg(struct eth_device *dev)
> +{
> + uint32_t start;
> + uint16_t status;
> +
> + /*
> + * Wait for AN completion
> + */
> + start = get_timer_masked(); /* get_time_ns(); */
> + do {
> + if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
> + printf("%s: Autonegotiation timeout\n", dev->name);
> + return -1;
> + }
> +
> + if (miiphy_read(dev->name, 0, PHY_BMSR, &status)) {
> + printf("%s: Autonegotiation failed. status: 0x%04x\n",
> + dev->name, status);
> + return -1;
> + }
> + } while (!(status & PHY_BMSR_LS));
> +
> + return 0;
> +}
> +static int fec_rx_task_enable(struct fec_priv *fec)
> +{
> + writel(1 << 24, &fec->eth->r_des_active);
> + return 0;
> +}
> +
> +static int fec_rx_task_disable(struct fec_priv *fec)
> +{
> + return 0;
> +}
> +
> +static int fec_tx_task_enable(struct fec_priv *fec)
> +{
> + writel(1 << 24, &fec->eth->x_des_active);
> + return 0;
> +}
> +
> +static int fec_tx_task_disable(struct fec_priv *fec)
> +{
> + return 0;
> +}
> +
> +/**
> + * Initialize receive task's buffer descriptors
> + * @param[in] fec all we know about the device yet
> + * @param[in] count receive buffer count to be allocated
> + * @param[in] size size of each receive buffer
> + * @return 0 on success
> + *
> + * For this task we need additional memory for the data buffers. And each
> + * data buffer requires some alignment. Thy must be aligned to a specific
> + * boundary each (DB_DATA_ALIGNMENT).
> + */
> +static int fec_rbd_init(struct fec_priv *fec, int count, int size, int once)
> +{
> + int ix;
> + uint32_t p = 0;
> +
> + if (!once) {
> + /* reserve data memory and consider alignment */
> + p = (uint32_t)malloc(size * count + DB_DATA_ALIGNMENT);
> + memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
> + p += DB_DATA_ALIGNMENT-1;
> + p &= ~(DB_DATA_ALIGNMENT-1);
> + }
> +
> + for (ix = 0; ix < count; ix++) {
> + if (!once) {
> + writel(p, &fec->rbd_base[ix].data_pointer);
> + p += size;
> + }
> + writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
> + writew(0, &fec->rbd_base[ix].data_length);
> + }
> + /*
> + * mark the last RBD to close the ring
> + */
> + writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
> + fec->rbd_index = 0;
> +
> + return 0;
> +}
> +
> +/**
> + * Initialize transmit task's buffer descriptors
> + * @param[in] fec all we know about the device yet
> + *
> + * Transmit buffers are created externally. We only have to init the BDs here.\n
> + * Note: There is a race condition in the hardware. When only one BD is in
> + * use it must be marked with the WRAP bit to use it for every transmitt.
> + * This bit in combination with the READY bit results into double transmit
> + * of each data buffer. It seems the state machine checks READY earlier then
> + * resetting it after the first transfer.
> + * Using two BDs solves this issue.
> + */
> +static void fec_tbd_init(struct fec_priv *fec)
> +{
> + writew(0x0000, &fec->tbd_base[0].status);
> + writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
> + fec->tbd_index = 0;
> +}
> +
> +/**
> + * Mark the given read buffer descriptor as free
> + * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
> + * @param[in] pRbd buffer descriptor to mark free again
> + */
> +static void fec_rbd_clean(int last, struct fec_bd *pRbd)
> +{
> + /*
> + * Reset buffer descriptor as empty
> + */
> + if (last)
> + writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
> + else
> + writew(FEC_RBD_EMPTY, &pRbd->status);
> + /*
> + * no data in it
> + */
> + writew(0, &pRbd->data_length);
> +}
> +
> +static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
> +{
> + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
> + int i;
> +
> + for (i = 0; i < 6; i++)
> + mac[6-1-i] = readl(&iim->IIM_BANK_AREA0[IIM0_MAC + i]);
> +
> + return is_valid_ether_addr(mac);
> +}
> +
> +static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
> +{
> + struct fec_priv *fec = (struct fec_priv *)dev->priv;
> +
> + writel(0, &fec->eth->iaddr1);
> + writel(0, &fec->eth->iaddr2);
> + writel(0, &fec->eth->gaddr1);
> + writel(0, &fec->eth->gaddr2);
> +
> + /*
> + * Set physical address
> + */
> + writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
> + &fec->eth->paddr1);
> + writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
> +
> + return 0;
> +}
> +
> +/**
> + * Start the FEC engine
> + * @param[in] dev Our device to handle
> + */
> +static int fec_open(struct eth_device *edev)
> +{
> + struct fec_priv *fec = (struct fec_priv *)edev->priv;
> +
> + debug("fec_open: fec_open(dev)\n");
> + /* full-duplex, heartbeat disabled */
> + writel(1 << 2, &fec->eth->x_cntrl);
> + fec->rbd_index = 0;
> +
> + /*
> + * Enable FEC-Lite controller
> + */
> + writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
> +
> + miiphy_wait_aneg(edev);
> + miiphy_speed(edev->name, 0);
> + miiphy_duplex(edev->name, 0);
> +
> + /*
> + * Enable SmartDMA receive task
> + */
> + fec_rx_task_enable(fec);
> +
> + udelay(100000);
> + return 0;
> +}
> +
> +static int fec_init(struct eth_device *dev, bd_t* bd)
> +{
> + static int once;
> + uint32_t base;
> + struct fec_priv *fec = (struct fec_priv *)dev->priv;
> +
> + if (!once) {
> + /*
> + * reserve memory for both buffer descriptor chains at once
> + * Datasheet forces the startaddress of each chain is 16 byte
> + * aligned
> + */
> + base = (uint32_t)malloc((2 + FEC_RBD_NUM) *
> + sizeof(struct fec_bd) + DB_ALIGNMENT);
> + memset((void *)base, 0, (2 + FEC_RBD_NUM) *
> + sizeof(struct fec_bd) + DB_ALIGNMENT);
> + base += (DB_ALIGNMENT-1);
> + base &= ~(DB_ALIGNMENT-1);
> +
> + fec->rbd_base = (struct fec_bd *)base;
> +
> + base += FEC_RBD_NUM * sizeof(struct fec_bd);
> +
> + fec->tbd_base = (struct fec_bd *)base;
> + }
>
If it's possible that an SOC will someday exist with more than one
controller this singleton stuff will have to go. Do you really need it
here? Your 'halt' function should free the memory so that it's safe to
call init() more than once.
<snip>
> sprintf(edev->name, "FEC ETHERNET");
>
You have a very specific driver name. Why make it generic here?
> +
> + miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
> +
> + eth_register(edev);
> +
> + if ((NULL != tmp) && (12 <= strlen(tmp))) {
> + int i;
> + /* convert MAC from string to int */
> + for (i = 0; i < 6; i++) {
> + ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
> + if (tmp)
> + tmp = (*end) ? end + 1 : end;
> + }
> + } else if (fec_get_hwaddr(edev, ethaddr) == 0) {
> + printf("got MAC address from EEPROM: %pM\n", ethaddr);
> + setenv("ethaddr", (char *)ethaddr_str);
> + }
> + memcpy(edev->enetaddr, ethaddr, 6);
> + fec_set_hwaddr(edev, ethaddr);
> +
> + return 0;
> +}
> +
> +int fecimx27_initialize(bd_t *bd)
> +{
> + int lout = 1;
> + static int once;
> +
> + if (!once) {
> + debug("eth_init: fec_probe(bd)\n");
> + lout = fec_probe(bd);
> + once = 1;
> + }
> + return lout;
> +}
>
I don't like this singleton stuff. You're artificially limiting this
driver to a single instance.
<snip>
hanks for your submission!
Ben
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-05-26 5:38 ` Ben Warren
@ 2009-06-07 23:08 ` Ilya Yanok
2009-11-17 2:46 ` alfred steele
1 sibling, 0 replies; 42+ messages in thread
From: Ilya Yanok @ 2009-06-07 23:08 UTC (permalink / raw)
To: u-boot
Hi Ben,
thanks for the review.
Ben Warren wrote:
> Naive question: Is this FEC truly unique to the iMX27? If not you
> should pick a more generic name.
Uh... I think the hardware is pretty the same as that is handled by
mcffec.c driver but merging won't be very easy...
Regards, Ilya.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-05-26 5:38 ` Ben Warren
2009-06-07 23:08 ` Ilya Yanok
@ 2009-11-17 2:46 ` alfred steele
2009-11-17 2:59 ` Ben Warren
2009-11-17 6:34 ` Wolfgang Denk
1 sibling, 2 replies; 42+ messages in thread
From: alfred steele @ 2009-11-17 2:46 UTC (permalink / raw)
To: u-boot
> Thanks for your submission!
What is the current design on the mxc fec interface's attainment of a
MAC address. From the kernel driver it looks like it looks at the
IIM(IC identification registers) on the MXC platform(like mx51/35) to
look for a programmed mac address and then the set the fec mac to the
same .
Looks like with the current mxc_fec driver there is not support for
the same. I am thinking of a mechanism to hardcode a fake MAC which
would subsequently be picked up by the kernel without using the
bd_info structure.
Any comments/suggestions?
-Alfred.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-11-17 2:46 ` alfred steele
@ 2009-11-17 2:59 ` Ben Warren
2009-11-19 1:54 ` alfred steele
2009-11-17 6:34 ` Wolfgang Denk
1 sibling, 1 reply; 42+ messages in thread
From: Ben Warren @ 2009-11-17 2:59 UTC (permalink / raw)
To: u-boot
Hi Alfred,
alfred steele wrote:
>> Thanks for your submission!
>>
> What is the current design on the mxc fec interface's attainment of a
> MAC address. From the kernel driver it looks like it looks at the
> IIM(IC identification registers) on the MXC platform(like mx51/35) to
> look for a programmed mac address and then the set the fec mac to the
> same .
>
> Looks like with the current mxc_fec driver there is not support for
> the same. I am thinking of a mechanism to hardcode a fake MAC which
> would subsequently be picked up by the kernel without using the
> bd_info structure.
> Any comments/suggestions?
>
> -Alfred.
>
I don't know much about this driver, but it appears to be doing things
incorrectly. The correct flow is as follows. It is documented in
'doc/README.enetaddr':
1. The driver's initialize() function read from NVRAM if available. MAC
address is stuffed into dev->enetaddr. The initialize() function should
not try to get the address from the environment, which is where the
imx27 driver goes wrong.
2. After all drivers have been initialized, eth_initialize() ( in
net/eth.c) reads from the environment. If the value in the environment
is valid and the value in dev->enetaddr is valid and both are different,
the user is warned. The value in the environment overwrites the value
in dev->enetaddr
3. When a network operation is performed, the driver's init() function
is called, which is where the address is programmed into the device.
As you can see, if the device is never used, step 3 is never exected and
the device is never programmed. This is how it's supposed to work,
since the U-boot design philosophy dictates that hardware is never
touched unless it is used in U-boot. I'm pretty sure hard-coding a fake
MAC address would run afoul of this rule.
regards,
Ben
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-11-17 2:59 ` Ben Warren
@ 2009-11-19 1:54 ` alfred steele
2009-11-19 3:30 ` Ben Warren
0 siblings, 1 reply; 42+ messages in thread
From: alfred steele @ 2009-11-19 1:54 UTC (permalink / raw)
To: u-boot
On Mon, Nov 16, 2009 at 8:59 PM, Ben Warren <biggerbadderben@gmail.com> wrote:
> Hi Alfred,
>
> alfred steele wrote:
>>>
>>> Thanks for your submission!
>>>
>>
>> What is the current design on the mxc fec interface's attainment of a
>> MAC address. From the kernel driver it looks like it looks at the
>> IIM(IC identification registers) on the MXC platform(like mx51/35) to
>> look for a programmed mac address and then the set the fec mac to the
>> same .
>>
>> Looks like with the current mxc_fec driver there is not support for
>> the same. I am thinking of a mechanism to hardcode a fake MAC which
>> would subsequently be picked up by the kernel without using the
>> bd_info structure.
>> Any comments/suggestions?
>>
>> -Alfred.
>>
>
> I don't know much about this driver, but it appears to be doing things
> incorrectly. ?The correct flow is as follows. ?It is documented in
> 'doc/README.enetaddr':
>
> 1. The driver's initialize() function read from NVRAM if available. ?MAC
> address is stuffed into dev->enetaddr. ?The initialize() function should not
> try to get the address from the environment, which is where the imx27 driver
> goes wrong.
> 2. After all drivers have been initialized, eth_initialize() ( in net/eth.c)
> reads from the environment. ?If the value in the environment is valid and
> the value in dev->enetaddr is valid and both are different, the user is
> warned. ?The value in the environment overwrites the value in dev->enetaddr
> 3. When a network operation is performed, the driver's init() function is
> called, which is where the address is programmed into the device.
>
> As you can see, if the device is never used, step 3 is never exected and the
> device is never programmed. ?This is how it's supposed to work, since the
> U-boot design philosophy dictates that hardware is never touched unless it
> is used in U-boot. ?I'm pretty sure hard-coding a fake MAC address would run
> afoul of this rule.
Is there a way to pass the information to kernel using either the
dev->enetaddr without programming the IIM module register. Would i
have to use bd_info structure or can we do without it.? This problem
is specific to the mx27 i guess.
-Alfred
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-11-19 1:54 ` alfred steele
@ 2009-11-19 3:30 ` Ben Warren
0 siblings, 0 replies; 42+ messages in thread
From: Ben Warren @ 2009-11-19 3:30 UTC (permalink / raw)
To: u-boot
Alfred,
On Wed, Nov 18, 2009 at 5:54 PM, alfred steele <alfred.jaquez@gmail.com>wrote:
> On Mon, Nov 16, 2009 at 8:59 PM, Ben Warren <biggerbadderben@gmail.com>
> wrote:
> > Hi Alfred,
> >
> > alfred steele wrote:
> >>>
> >>> Thanks for your submission!
> >>>
> >>
> >> What is the current design on the mxc fec interface's attainment of a
> >> MAC address. From the kernel driver it looks like it looks at the
> >> IIM(IC identification registers) on the MXC platform(like mx51/35) to
> >> look for a programmed mac address and then the set the fec mac to the
> >> same .
> >>
> >> Looks like with the current mxc_fec driver there is not support for
> >> the same. I am thinking of a mechanism to hardcode a fake MAC which
> >> would subsequently be picked up by the kernel without using the
> >> bd_info structure.
> >> Any comments/suggestions?
> >>
> >> -Alfred.
> >>
> >
> > I don't know much about this driver, but it appears to be doing things
> > incorrectly. The correct flow is as follows. It is documented in
> > 'doc/README.enetaddr':
> >
> > 1. The driver's initialize() function read from NVRAM if available. MAC
> > address is stuffed into dev->enetaddr. The initialize() function should
> not
> > try to get the address from the environment, which is where the imx27
> driver
> > goes wrong.
> > 2. After all drivers have been initialized, eth_initialize() ( in
> net/eth.c)
> > reads from the environment. If the value in the environment is valid and
> > the value in dev->enetaddr is valid and both are different, the user is
> > warned. The value in the environment overwrites the value in
> dev->enetaddr
> > 3. When a network operation is performed, the driver's init() function is
> > called, which is where the address is programmed into the device.
> >
> > As you can see, if the device is never used, step 3 is never exected and
> the
> > device is never programmed. This is how it's supposed to work, since the
> > U-boot design philosophy dictates that hardware is never touched unless
> it
> > is used in U-boot. I'm pretty sure hard-coding a fake MAC address would
> run
> > afoul of this rule.
> Is there a way to pass the information to kernel using either the
> dev->enetaddr without programming the IIM module register. Would i
> have to use bd_info structure or can we do without it.? This problem
> is specific to the mx27 i guess.
> -Alfred
>
I'm pretty sure it's a much-discussed ARM peculiarity. Not at all my area
of expertise, so I'll leave it to others to suggest options.
regards,
Ben
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-11-17 2:46 ` alfred steele
2009-11-17 2:59 ` Ben Warren
@ 2009-11-17 6:34 ` Wolfgang Denk
1 sibling, 0 replies; 42+ messages in thread
From: Wolfgang Denk @ 2009-11-17 6:34 UTC (permalink / raw)
To: u-boot
Dear Alfred Steele,
In message <528f13590911161846q6a91df8awa309d4e1f990d134@mail.gmail.com> you wrote:
> > Thanks for your submission!
> What is the current design on the mxc fec interface's attainment of a
> MAC address. From the kernel driver it looks like it looks at the
There is none.
> IIM(IC identification registers) on the MXC platform(like mx51/35) to
> look for a programmed mac address and then the set the fec mac to the
> same .
>
> Looks like with the current mxc_fec driver there is not support for
> the same. I am thinking of a mechanism to hardcode a fake MAC which
> would subsequently be picked up by the kernel without using the
> bd_info structure.
You must not do this. First, you must not use any "fake" addresses at
all (especially not since the board most probably has a real one in
the environment). Second, read the FAQ
(http://www.denx.de/wiki/view/DULG/EthernetDoesNotWorkInLinux).
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
ATTENTION: Despite Any Other Listing of Product Contents Found Here-
on, the Consumer is Advised That, in Actuality, This Product Consists
Of 99.9999999999% Empty Space.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-05-19 23:55 ` [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27 Ilya Yanok
2009-05-26 5:38 ` Ben Warren
@ 2009-06-15 14:01 ` Johan
2009-06-15 19:59 ` Eric Lammerts
1 sibling, 1 reply; 42+ messages in thread
From: Johan @ 2009-06-15 14:01 UTC (permalink / raw)
To: u-boot
I have trouble using your patch together with our LogicPD iMX27
Litekit. Seems like the FEC driver does not work well. Here is some
output from when I try to load files with tftp
U-Boot 2009.06-rc1 (jun 15 2009 - 15:46:31)
CPU: Freescale i.MX27 at 399 MHz
DRAM: 128 MB
Flash: 2 MB
NAND: 64 MiB
In: serial
Out: serial
Err: serial
MMC: MXC MCI: 0
Hit any key to stop autoboot: 0
=> tftp 0xa0800000 uImage
FEC ETHERNET: Link is up - 100/Full
TFTP from server 172.16.140.75; our IP address is 172.16.140.76
Filename 'uImage'.
Load address: 0xa0800000
Loading: #####T #####################T #########################T ############T#
#########################T ########################################
##T ####################################T #########T T #########
Retry count exceeded; starting again
TFTP from server 172.16.140.75; our IP address is 172.16.140.76
Filename 'uImage'.
Load address: 0xa0800000
Loading: ####################
I have downloaded the imx27lite head from the u-boot testing branch. I
have also tried to patch the u-boot-2009.06-rc3 branch with your
patches, but it does not seem to be any different. Do you have any
ideas what might be wrong?
/Johan
2009/5/20 Ilya Yanok <yanok@emcraft.com>:
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---
> ?cpu/arm926ejs/mx27/generic.c | ? 10 +
> ?drivers/net/Makefile ? ? ? ? | ? ?1 +
> ?drivers/net/fec_imx27.c ? ? ?| ?705 ++++++++++++++++++++++++++++++++++++++++++
> ?drivers/net/fec_imx27.h ? ? ?| ?302 ++++++++++++++++++
> ?include/netdev.h ? ? ? ? ? ? | ? ?1 +
> ?5 files changed, 1019 insertions(+), 0 deletions(-)
> ?create mode 100644 drivers/net/fec_imx27.c
> ?create mode 100644 drivers/net/fec_imx27.h
>
> diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
> index 850d5e6..e820d94 100644
> --- a/cpu/arm926ejs/mx27/generic.c
> +++ b/cpu/arm926ejs/mx27/generic.c
> @@ -20,6 +20,7 @@
>
> ?#include <common.h>
> ?#include <div64.h>
> +#include <netdev.h>
> ?#include <asm/io.h>
> ?#include <asm/arch/imx-regs.h>
>
> @@ -159,6 +160,15 @@ int print_cpuinfo (void)
> ?}
> ?#endif
>
> +int cpu_eth_init(bd_t *bis)
> +{
> +#if defined(CONFIG_FEC_IMX27)
> + ? ? ? return fecimx27_initialize(bis);
> +#else
> + ? ? ? return 0;
> +#endif
> +}
> +
> ?void imx_gpio_mode(int gpio_mode)
> ?{
> ? ? ? ?struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index a360a50..ac68beb 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
> ?COBJS-$(CONFIG_TULIP) += dc2114x.o
> ?COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
> ?COBJS-$(CONFIG_DNET) += dnet.o
> +COBJS-$(CONFIG_FEC_IMX27) += fec_imx27.o
> ?COBJS-$(CONFIG_E1000) += e1000.o
> ?COBJS-$(CONFIG_EEPRO100) += eepro100.o
> ?COBJS-$(CONFIG_ENC28J60) += enc28j60.o
> diff --git a/drivers/net/fec_imx27.c b/drivers/net/fec_imx27.c
> new file mode 100644
> index 0000000..4ade348
> --- /dev/null
> +++ b/drivers/net/fec_imx27.c
> @@ -0,0 +1,705 @@
> +/*
> + * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
> + * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
> + * (C) Copyright 2008 Armadeus Systems nc
> + * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <net.h>
> +#include <miiphy.h>
> +#include "fec_imx27.h"
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifndef CONFIG_MII
> +#error "CONFIG_MII has to be defined!"
> +#endif
> +
> +#undef DEBUG
> +
> +struct nbuf {
> + ? ? ? uint8_t data[1500]; ? ? /**< actual data */
> + ? ? ? int length; ? ? ? ? ? ? /**< actual length */
> + ? ? ? int used; ? ? ? ? ? ? ? /**< buffer in use or not */
> + ? ? ? uint8_t head[16]; ? ? ? /**< MAC header(6 + 6 + 2) + 2(aligned) */
> +};
> +
> +struct fec_priv gfec = {
> + ? ? ? .eth ? ? ? = (struct ethernet_regs *)IMX_FEC_BASE,
> + ? ? ? .xcv_type ?= MII100,
> + ? ? ? .rbd_base ?= NULL,
> + ? ? ? .rbd_index = 0,
> + ? ? ? .tbd_base ?= NULL,
> + ? ? ? .tbd_index = 0,
> + ? ? ? .bd ? ? ? ?= NULL,
> +};
> +
> +/*
> + * MII-interface related functions
> + */
> +static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
> + ? ? ? ? ? ? ? uint16_t *retVal)
> +{
> + ? ? ? struct eth_device *edev = eth_get_dev_by_name(dev);
> + ? ? ? struct fec_priv *fec = (struct fec_priv *)edev->priv;
> +
> + ? ? ? uint32_t reg; ? ? ? ? ? /* convenient holder for the PHY register */
> + ? ? ? uint32_t phy; ? ? ? ? ? /* convenient holder for the PHY */
> + ? ? ? uint32_t start;
> +
> + ? ? ? /*
> + ? ? ? ?* reading from any PHY's register is done by properly
> + ? ? ? ?* programming the FEC's MII data register.
> + ? ? ? ?*/
> + ? ? ? writel(FEC_IEVENT_MII, &fec->eth->ievent);
> + ? ? ? reg = regAddr << FEC_MII_DATA_RA_SHIFT;
> + ? ? ? phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
> +
> + ? ? ? writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
> + ? ? ? ? ? ? ? ? ? ? ? phy | reg, &fec->eth->mii_data);
> +
> + ? ? ? /*
> + ? ? ? ?* wait for the related interrupt
> + ? ? ? ?*/
> + ? ? ? start = get_timer_masked();
> + ? ? ? while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
> + ? ? ? ? ? ? ? if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
> + ? ? ? ? ? ? ? ? ? ? ? printf("Read MDIO failed...\n");
> + ? ? ? ? ? ? ? ? ? ? ? return -1;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? /*
> + ? ? ? ?* clear mii interrupt bit
> + ? ? ? ?*/
> + ? ? ? writel(FEC_IEVENT_MII, &fec->eth->ievent);
> +
> + ? ? ? /*
> + ? ? ? ?* it's now safe to read the PHY's register
> + ? ? ? ?*/
> + ? ? ? *retVal = readl(&fec->eth->mii_data);
> + ? ? ? debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
> + ? ? ? ? ? ? ? ? ? ? ? regAddr, *retVal);
> + ? ? ? return 0;
> +}
> +
> +static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
> + ? ? ? ? ? ? ? uint16_t data)
> +{
> + ? ? ? struct eth_device *edev = eth_get_dev_by_name(dev);
> + ? ? ? struct fec_priv *fec = (struct fec_priv *)edev->priv;
> +
> + ? ? ? uint32_t reg; ? ? ? ? ? /* convenient holder for the PHY register */
> + ? ? ? uint32_t phy; ? ? ? ? ? /* convenient holder for the PHY */
> + ? ? ? uint32_t start;
> +
> + ? ? ? reg = regAddr << FEC_MII_DATA_RA_SHIFT;
> + ? ? ? phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
> +
> + ? ? ? writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
> + ? ? ? ? ? ? ? FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
> +
> + ? ? ? /*
> + ? ? ? ?* wait for the MII interrupt
> + ? ? ? ?*/
> + ? ? ? start = get_timer_masked();
> + ? ? ? while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
> + ? ? ? ? ? ? ? if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
> + ? ? ? ? ? ? ? ? ? ? ? printf("Write MDIO failed...\n");
> + ? ? ? ? ? ? ? ? ? ? ? return -1;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? /*
> + ? ? ? ?* clear MII interrupt bit
> + ? ? ? ?*/
> + ? ? ? writel(FEC_IEVENT_MII, &fec->eth->ievent);
> + ? ? ? debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
> + ? ? ? ? ? ? ? ? ? ? ? regAddr, data);
> +
> + ? ? ? return 0;
> +}
> +
> +static int miiphy_restart_aneg(struct eth_device *dev)
> +{
> + ? ? ? /*
> + ? ? ? ?* Wake up from sleep if necessary
> + ? ? ? ?* Reset PHY, then delay 300ns
> + ? ? ? ?*/
> + ? ? ? miiphy_write(dev->name, 0, PHY_MIPGSR, 0x00FF);
> + ? ? ? miiphy_write(dev->name, 0, PHY_BMCR, PHY_BMCR_RESET);
> + ? ? ? udelay(1000);
> +
> + ? ? ? /*
> + ? ? ? ?* Set the auto-negotiation advertisement register bits
> + ? ? ? ?*/
> + ? ? ? miiphy_write(dev->name, 0, PHY_ANAR, 0x1e0);
> + ? ? ? miiphy_write(dev->name, 0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
> +
> + ? ? ? return 0;
> +}
> +
> +static int miiphy_wait_aneg(struct eth_device *dev)
> +{
> + ? ? ? uint32_t start;
> + ? ? ? uint16_t status;
> +
> + ? ? ? /*
> + ? ? ? ?* Wait for AN completion
> + ? ? ? ?*/
> + ? ? ? start = get_timer_masked(); /* get_time_ns(); */
> + ? ? ? do {
> + ? ? ? ? ? ? ? if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
> + ? ? ? ? ? ? ? ? ? ? ? printf("%s: Autonegotiation timeout\n", dev->name);
> + ? ? ? ? ? ? ? ? ? ? ? return -1;
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? if (miiphy_read(dev->name, 0, PHY_BMSR, &status)) {
> + ? ? ? ? ? ? ? ? ? ? ? printf("%s: Autonegotiation failed. status: 0x%04x\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dev->name, status);
> + ? ? ? ? ? ? ? ? ? ? ? return -1;
> + ? ? ? ? ? ? ? }
> + ? ? ? } while (!(status & PHY_BMSR_LS));
> +
> + ? ? ? return 0;
> +}
> +static int fec_rx_task_enable(struct fec_priv *fec)
> +{
> + ? ? ? writel(1 << 24, &fec->eth->r_des_active);
> + ? ? ? return 0;
> +}
> +
> +static int fec_rx_task_disable(struct fec_priv *fec)
> +{
> + ? ? ? return 0;
> +}
> +
> +static int fec_tx_task_enable(struct fec_priv *fec)
> +{
> + ? ? ? writel(1 << 24, &fec->eth->x_des_active);
> + ? ? ? return 0;
> +}
> +
> +static int fec_tx_task_disable(struct fec_priv *fec)
> +{
> + ? ? ? return 0;
> +}
> +
> +/**
> + * Initialize receive task's buffer descriptors
> + * @param[in] fec all we know about the device yet
> + * @param[in] count receive buffer count to be allocated
> + * @param[in] size size of each receive buffer
> + * @return 0 on success
> + *
> + * For this task we need additional memory for the data buffers. And each
> + * data buffer requires some alignment. Thy must be aligned to a specific
> + * boundary each (DB_DATA_ALIGNMENT).
> + */
> +static int fec_rbd_init(struct fec_priv *fec, int count, int size, int once)
> +{
> + ? ? ? int ix;
> + ? ? ? uint32_t p = 0;
> +
> + ? ? ? if (!once) {
> + ? ? ? ? ? ? ? /* reserve data memory and consider alignment */
> + ? ? ? ? ? ? ? p = (uint32_t)malloc(size * count + DB_DATA_ALIGNMENT);
> + ? ? ? ? ? ? ? memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
> + ? ? ? ? ? ? ? p += DB_DATA_ALIGNMENT-1;
> + ? ? ? ? ? ? ? p &= ~(DB_DATA_ALIGNMENT-1);
> + ? ? ? }
> +
> + ? ? ? for (ix = 0; ix < count; ix++) {
> + ? ? ? ? ? ? ? if (!once) {
> + ? ? ? ? ? ? ? ? ? ? ? writel(p, &fec->rbd_base[ix].data_pointer);
> + ? ? ? ? ? ? ? ? ? ? ? p += size;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
> + ? ? ? ? ? ? ? writew(0, &fec->rbd_base[ix].data_length);
> + ? ? ? }
> + ? ? ? /*
> + ? ? ? ?* mark the last RBD to close the ring
> + ? ? ? ?*/
> + ? ? ? writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
> + ? ? ? fec->rbd_index = 0;
> +
> + ? ? ? return 0;
> +}
> +
> +/**
> + * Initialize transmit task's buffer descriptors
> + * @param[in] fec all we know about the device yet
> + *
> + * Transmit buffers are created externally. We only have to init the BDs here.\n
> + * Note: There is a race condition in the hardware. When only one BD is in
> + * use it must be marked with the WRAP bit to use it for every transmitt.
> + * This bit in combination with the READY bit results into double transmit
> + * of each data buffer. It seems the state machine checks READY earlier then
> + * resetting it after the first transfer.
> + * Using two BDs solves this issue.
> + */
> +static void fec_tbd_init(struct fec_priv *fec)
> +{
> + ? ? ? writew(0x0000, &fec->tbd_base[0].status);
> + ? ? ? writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
> + ? ? ? fec->tbd_index = 0;
> +}
> +
> +/**
> + * Mark the given read buffer descriptor as free
> + * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
> + * @param[in] pRbd buffer descriptor to mark free again
> + */
> +static void fec_rbd_clean(int last, struct fec_bd *pRbd)
> +{
> + ? ? ? /*
> + ? ? ? ?* Reset buffer descriptor as empty
> + ? ? ? ?*/
> + ? ? ? if (last)
> + ? ? ? ? ? ? ? writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
> + ? ? ? else
> + ? ? ? ? ? ? ? writew(FEC_RBD_EMPTY, &pRbd->status);
> + ? ? ? /*
> + ? ? ? ?* no data in it
> + ? ? ? ?*/
> + ? ? ? writew(0, &pRbd->data_length);
> +}
> +
> +static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
> +{
> + ? ? ? struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
> + ? ? ? int i;
> +
> + ? ? ? for (i = 0; i < 6; i++)
> + ? ? ? ? ? ? ? mac[6-1-i] = readl(&iim->IIM_BANK_AREA0[IIM0_MAC + i]);
> +
> + ? ? ? return is_valid_ether_addr(mac);
> +}
> +
> +static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
> +{
> + ? ? ? struct fec_priv *fec = (struct fec_priv *)dev->priv;
> +
> + ? ? ? writel(0, &fec->eth->iaddr1);
> + ? ? ? writel(0, &fec->eth->iaddr2);
> + ? ? ? writel(0, &fec->eth->gaddr1);
> + ? ? ? writel(0, &fec->eth->gaddr2);
> +
> + ? ? ? /*
> + ? ? ? ?* Set physical address
> + ? ? ? ?*/
> + ? ? ? writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
> + ? ? ? ? ? ? ? ? ? ? ? &fec->eth->paddr1);
> + ? ? ? writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
> +
> + ? ? ? return 0;
> +}
> +
> +/**
> + * Start the FEC engine
> + * @param[in] dev Our device to handle
> + */
> +static int fec_open(struct eth_device *edev)
> +{
> + ? ? ? struct fec_priv *fec = (struct fec_priv *)edev->priv;
> +
> + ? ? ? debug("fec_open: fec_open(dev)\n");
> + ? ? ? /* full-duplex, heartbeat disabled */
> + ? ? ? writel(1 << 2, &fec->eth->x_cntrl);
> + ? ? ? fec->rbd_index = 0;
> +
> + ? ? ? /*
> + ? ? ? ?* Enable FEC-Lite controller
> + ? ? ? ?*/
> + ? ? ? writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
> +
> + ? ? ? miiphy_wait_aneg(edev);
> + ? ? ? miiphy_speed(edev->name, 0);
> + ? ? ? miiphy_duplex(edev->name, 0);
> +
> + ? ? ? /*
> + ? ? ? ?* Enable SmartDMA receive task
> + ? ? ? ?*/
> + ? ? ? fec_rx_task_enable(fec);
> +
> + ? ? ? udelay(100000);
> + ? ? ? return 0;
> +}
> +
> +static int fec_init(struct eth_device *dev, bd_t* bd)
> +{
> + ? ? ? static int once;
> + ? ? ? uint32_t base;
> + ? ? ? struct fec_priv *fec = (struct fec_priv *)dev->priv;
> +
> + ? ? ? if (!once) {
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* reserve memory for both buffer descriptor chains at once
> + ? ? ? ? ? ? ? ?* Datasheet forces the startaddress of each chain is 16 byte
> + ? ? ? ? ? ? ? ?* aligned
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? base = (uint32_t)malloc((2 + FEC_RBD_NUM) *
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sizeof(struct fec_bd) + DB_ALIGNMENT);
> + ? ? ? ? ? ? ? memset((void *)base, 0, (2 + FEC_RBD_NUM) *
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sizeof(struct fec_bd) + DB_ALIGNMENT);
> + ? ? ? ? ? ? ? base += (DB_ALIGNMENT-1);
> + ? ? ? ? ? ? ? base &= ~(DB_ALIGNMENT-1);
> +
> + ? ? ? ? ? ? ? fec->rbd_base = (struct fec_bd *)base;
> +
> + ? ? ? ? ? ? ? base += FEC_RBD_NUM * sizeof(struct fec_bd);
> +
> + ? ? ? ? ? ? ? fec->tbd_base = (struct fec_bd *)base;
> + ? ? ? }
> +
> + ? ? ? /*
> + ? ? ? ?* Set interrupt mask register
> + ? ? ? ?*/
> + ? ? ? writel(0x00000000, &fec->eth->imask);
> +
> + ? ? ? /*
> + ? ? ? ?* Clear FEC-Lite interrupt event register(IEVENT)
> + ? ? ? ?*/
> + ? ? ? writel(0xffffffff, &fec->eth->ievent);
> +
> +
> + ? ? ? /*
> + ? ? ? ?* Set FEC-Lite receive control register(R_CNTRL):
> + ? ? ? ?*/
> + ? ? ? if (fec->xcv_type == SEVENWIRE) {
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* Frame length=1518; 7-wire mode
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */
> + ? ? ? } else {
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* Frame length=1518; MII mode;
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
> + ? ? ? ? ? ? ? ?* and do not drop the Preamble.
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &fec->eth->mii_speed);
> + ? ? ? ? ? ? ? debug("fec_init: mii_speed %#lx\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
> + ? ? ? }
> + ? ? ? /*
> + ? ? ? ?* Set Opcode/Pause Duration Register
> + ? ? ? ?*/
> + ? ? ? writel(0x00010020, &fec->eth->op_pause); ? ? ? ?/* FIXME 0xffff0020; */
> + ? ? ? writel(0x2, &fec->eth->x_wmrk);
> + ? ? ? /*
> + ? ? ? ?* Set multicast address filter
> + ? ? ? ?*/
> + ? ? ? writel(0x00000000, &fec->eth->gaddr1);
> + ? ? ? writel(0x00000000, &fec->eth->gaddr2);
> +
> +
> + ? ? ? /* clear MIB RAM */
> + ? ? ? long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
> + ? ? ? while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
> + ? ? ? ? ? ? ? *mib_ptr++ = 0;
> +
> + ? ? ? /* FIFO receive start register */
> + ? ? ? writel(0x520, &fec->eth->r_fstart);
> +
> + ? ? ? /* size and address of each buffer */
> + ? ? ? writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
> + ? ? ? writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
> + ? ? ? writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
> +
> + ? ? ? /*
> + ? ? ? ?* Initialize RxBD/TxBD rings
> + ? ? ? ?*/
> + ? ? ? fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE, once);
> + ? ? ? fec_tbd_init(fec);
> +
> +
> + ? ? ? if (fec->xcv_type != SEVENWIRE)
> + ? ? ? ? ? ? ? miiphy_restart_aneg(dev);
> +
> + ? ? ? once = 1; ? ? ? /* malloc done now (and once) */
> +
> + ? ? ? fec_open(dev);
> + ? ? ? return 0;
> +}
> +
> +/**
> + * Halt the FEC engine
> + * @param[in] dev Our device to handle
> + */
> +static void fec_halt(struct eth_device *dev)
> +{
> + ? ? ? struct fec_priv *fec = &gfec;
> + ? ? ? int counter = 0xffff;
> +
> + ? ? ? /*
> + ? ? ? ?* issue graceful stop command to the FEC transmitter if necessary
> + ? ? ? ?*/
> + ? ? ? writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
> + ? ? ? ? ? ? ? ? ? ? ? &fec->eth->x_cntrl);
> +
> + ? ? ? debug("eth_halt: wait for stop regs\n");
> + ? ? ? /*
> + ? ? ? ?* wait for graceful stop to register
> + ? ? ? ?*/
> + ? ? ? while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
> + ? ? ? ? ? ? ? ; ? ? ? /* FIXME ensure time */
> +
> + ? ? ? /*
> + ? ? ? ?* Disable SmartDMA tasks
> + ? ? ? ?*/
> + ? ? ? fec_tx_task_disable(fec);
> + ? ? ? fec_rx_task_disable(fec);
> +
> + ? ? ? /*
> + ? ? ? ?* Disable the Ethernet Controller
> + ? ? ? ?* Note: this will also reset the BD index counter!
> + ? ? ? ?*/
> + ? ? ? writel(0, &fec->eth->ecntrl);
> + ? ? ? fec->rbd_index = 0;
> + ? ? ? fec->tbd_index = 0;
> + ? ? ? debug("eth_halt: done\n");
> +}
> +
> +/**
> + * Transmit one frame
> + * @param[in] dev Our ethernet device to handle
> + * @param[in] packet Pointer to the data to be transmitted
> + * @param[in] length Data count in bytes
> + * @return 0 on success
> + */
> +static int fec_send(struct eth_device *dev, volatile void* packet, int length)
> +{
> + ? ? ? unsigned int status;
> +
> + ? ? ? /*
> + ? ? ? ?* This routine transmits one frame. ?This routine only accepts
> + ? ? ? ?* 6-byte Ethernet addresses.
> + ? ? ? ?*/
> + ? ? ? struct fec_priv *fec = (struct fec_priv *)dev->priv;
> +
> + ? ? ? /*
> + ? ? ? ?* Check for valid length of data.
> + ? ? ? ?*/
> + ? ? ? if ((length > 1500) || (length <= 0)) {
> + ? ? ? ? ? ? ? printf("Payload (%d) to large!\n", length);
> + ? ? ? ? ? ? ? return -1;
> + ? ? ? }
> +
> + ? ? ? /*
> + ? ? ? ?* Setup the transmit buffer
> + ? ? ? ?* Note: We are always using the first buffer for transmission,
> + ? ? ? ?* the second will be empty and only used to stop the DMA engine
> + ? ? ? ?*/
> + ? ? ? writew(length, &fec->tbd_base[fec->tbd_index].data_length);
> + ? ? ? writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
> + ? ? ? /*
> + ? ? ? ?* update BD's status now
> + ? ? ? ?* This block:
> + ? ? ? ?* - is always the last in a chain (means no chain)
> + ? ? ? ?* - should transmitt the CRC
> + ? ? ? ?* - might be the last BD in the list, so the address counter should
> + ? ? ? ?* ? wrap (-> keep the WRAP flag)
> + ? ? ? ?*/
> + ? ? ? status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
> + ? ? ? status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
> + ? ? ? writew(status, &fec->tbd_base[fec->tbd_index].status);
> +
> + ? ? ? /*
> + ? ? ? ?* Enable SmartDMA transmit task
> + ? ? ? ?*/
> + ? ? ? fec_tx_task_enable(fec);
> +
> + ? ? ? /*
> + ? ? ? ?* wait until frame is sent .
> + ? ? ? ?*/
> + ? ? ? while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
> + ? ? ? ? ? ? ? /* FIXME: Timeout */
> + ? ? ? }
> + ? ? ? debug("fec_send: status 0x%x index %d\n",
> + ? ? ? ? ? ? ? ? ? ? ? readw(&fec->tbd_base[fec->tbd_index].status),
> + ? ? ? ? ? ? ? ? ? ? ? fec->tbd_index);
> + ? ? ? /* for next transmission use the other buffer */
> + ? ? ? if (fec->tbd_index)
> + ? ? ? ? ? ? ? fec->tbd_index = 0;
> + ? ? ? else
> + ? ? ? ? ? ? ? fec->tbd_index = 1;
> +
> + ? ? ? return 0;
> +}
> +
> +/**
> + * Pull one frame from the card
> + * @param[in] dev Our ethernet device to handle
> + * @return Length of packet read
> + */
> +static int fec_recv(struct eth_device *dev)
> +{
> + ? ? ? struct fec_priv *fec = (struct fec_priv *)dev->priv;
> + ? ? ? struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
> + ? ? ? unsigned long ievent;
> + ? ? ? int frame_length, len = 0;
> + ? ? ? struct nbuf *frame;
> + ? ? ? uint16_t bd_status;
> + ? ? ? uchar buff[FEC_MAX_PKT_SIZE];
> +
> + ? ? ? /*
> + ? ? ? ?* Check if any critical events have happened
> + ? ? ? ?*/
> + ? ? ? ievent = readl(&fec->eth->ievent);
> + ? ? ? writel(ievent, &fec->eth->ievent);
> + ? ? ? debug("fec_recv: ievent 0x%x\n", ievent);
> + ? ? ? if (ievent & FEC_IEVENT_BABR) {
> + ? ? ? ? ? ? ? fec_halt(dev);
> + ? ? ? ? ? ? ? fec_init(dev, fec->bd);
> + ? ? ? ? ? ? ? printf("some error: 0x%08lx\n", ievent);
> + ? ? ? ? ? ? ? return 0;
> + ? ? ? }
> + ? ? ? if (ievent & FEC_IEVENT_HBERR) {
> + ? ? ? ? ? ? ? /* Heartbeat error */
> + ? ? ? ? ? ? ? writel(0x00000001 | readl(&fec->eth->x_cntrl),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &fec->eth->x_cntrl);
> + ? ? ? }
> + ? ? ? if (ievent & FEC_IEVENT_GRA) {
> + ? ? ? ? ? ? ? /* Graceful stop complete */
> + ? ? ? ? ? ? ? if (readl(&fec->eth->x_cntrl) & 0x00000001) {
> + ? ? ? ? ? ? ? ? ? ? ? fec_halt(dev);
> + ? ? ? ? ? ? ? ? ? ? ? writel(~0x00000001 & readl(&fec->eth->x_cntrl),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &fec->eth->x_cntrl);
> + ? ? ? ? ? ? ? ? ? ? ? fec_init(dev, fec->bd);
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? /*
> + ? ? ? ?* ensure reading the right buffer status
> + ? ? ? ?*/
> + ? ? ? bd_status = readw(&rbd->status);
> + ? ? ? debug("fec_recv: status 0x%x\n", bd_status);
> +
> + ? ? ? if (!(bd_status & FEC_RBD_EMPTY)) {
> + ? ? ? ? ? ? ? if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
> + ? ? ? ? ? ? ? ? ? ? ? ((readw(&rbd->data_length) - 4) > 14)) {
> + ? ? ? ? ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ? ? ? ? ?* Get buffer address and size
> + ? ? ? ? ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? ? ? ? ? frame = (struct nbuf *)readl(&rbd->data_pointer);
> + ? ? ? ? ? ? ? ? ? ? ? frame_length = readw(&rbd->data_length) - 4;
> + ? ? ? ? ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ? ? ? ? ?* ?Fill the buffer and pass it to upper layers
> + ? ? ? ? ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? ? ? ? ? memcpy(buff, frame->data, frame_length);
> + ? ? ? ? ? ? ? ? ? ? ? NetReceive(buff, frame_length);
> + ? ? ? ? ? ? ? ? ? ? ? len = frame_length;
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? if (bd_status & FEC_RBD_ERR)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? printf("error frame: 0x%08lx 0x%08x\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (ulong)rbd->data_pointer,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bd_status);
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* free the current buffer, restart the engine
> + ? ? ? ? ? ? ? ?* and move forward to the next buffer
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
> + ? ? ? ? ? ? ? fec_rx_task_enable(fec);
> + ? ? ? ? ? ? ? fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
> + ? ? ? }
> + ? ? ? debug("fec_recv: stop\n");
> +
> + ? ? ? return len;
> +}
> +
> +static int fec_probe(bd_t *bd)
> +{
> + ? ? ? struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
> + ? ? ? struct eth_device *edev;
> + ? ? ? struct fec_priv *fec = &gfec;
> + ? ? ? unsigned char ethaddr_str[20];
> + ? ? ? unsigned char ethaddr[6];
> + ? ? ? char *tmp = getenv("ethaddr");
> + ? ? ? char *end;
> +
> + ? ? ? /* enable FEC clock */
> + ? ? ? writel(readl(&pll->PCCR1) | PCCR1_HCLK_FEC, &pll->PCCR1);
> + ? ? ? writel(readl(&pll->PCCR0) | PCCR0_FEC_EN, &pll->PCCR0);
> +
> + ? ? ? /* create and fill edev struct */
> + ? ? ? edev = (struct eth_device *)malloc(sizeof(struct eth_device));
> + ? ? ? edev->priv = fec;
> + ? ? ? edev->init = fec_init;
> + ? ? ? edev->send = fec_send;
> + ? ? ? edev->recv = fec_recv;
> + ? ? ? edev->halt = fec_halt;
> +
> + ? ? ? fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
> + ? ? ? fec->bd = bd;
> +
> + ? ? ? /* Reset chip. */
> + ? ? ? writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
> + ? ? ? while (readl(&fec->eth->ecntrl) & 1)
> + ? ? ? ? ? ? ? udelay(10);
> +
> + ? ? ? fec->xcv_type = MII100;
> +
> + ? ? ? sprintf(edev->name, "FEC ETHERNET");
> +
> + ? ? ? miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
> +
> + ? ? ? eth_register(edev);
> +
> + ? ? ? if ((NULL != tmp) && (12 <= strlen(tmp))) {
> + ? ? ? ? ? ? ? int i;
> + ? ? ? ? ? ? ? /* convert MAC from string to int */
> + ? ? ? ? ? ? ? for (i = 0; i < 6; i++) {
> + ? ? ? ? ? ? ? ? ? ? ? ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
> + ? ? ? ? ? ? ? ? ? ? ? if (tmp)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tmp = (*end) ? end + 1 : end;
> + ? ? ? ? ? ? ? }
> + ? ? ? } else if (fec_get_hwaddr(edev, ethaddr) == 0) {
> + ? ? ? ? ? ? ? printf("got MAC address from EEPROM: %pM\n", ethaddr);
> + ? ? ? ? ? ? ? setenv("ethaddr", (char *)ethaddr_str);
> + ? ? ? }
> + ? ? ? memcpy(edev->enetaddr, ethaddr, 6);
> + ? ? ? fec_set_hwaddr(edev, ethaddr);
> +
> + ? ? ? return 0;
> +}
> +
> +int fecimx27_initialize(bd_t *bd)
> +{
> + ? ? ? int lout = 1;
> + ? ? ? static int once;
> +
> + ? ? ? if (!once) {
> + ? ? ? ? ? ? ? debug("eth_init: fec_probe(bd)\n");
> + ? ? ? ? ? ? ? lout = fec_probe(bd);
> + ? ? ? ? ? ? ? once = 1;
> + ? ? ? }
> + ? ? ? return lout;
> +}
> +
> diff --git a/drivers/net/fec_imx27.h b/drivers/net/fec_imx27.h
> new file mode 100644
> index 0000000..926c0d7
> --- /dev/null
> +++ b/drivers/net/fec_imx27.h
> @@ -0,0 +1,302 @@
> +/*
> + * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
> + * (C) Copyright 2008 Armadeus Systems, nc
> + * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
> + * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
> + *
> + * (C) Copyright 2003
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * This file is based on mpc4200fec.h
> + * (C) Copyright Motorola, Inc., 2000
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + */
> +
> +
> +#ifndef __IMX27_FEC_H
> +#define __IMX27_FEC_H
> +
> +/**
> + * Layout description of the FEC
> + */
> +struct ethernet_regs {
> +
> +/* [10:2]addr = 00 */
> +
> +/* ?Control and status Registers (offset 000-1FF) */
> +
> + ? ? ? uint32_t RES0[1]; ? ? ? ? ? ? ? /* MBAR_ETH + 0x000 */
> + ? ? ? uint32_t ievent; ? ? ? ? ? ? ? ?/* MBAR_ETH + 0x004 */
> + ? ? ? uint32_t imask; ? ? ? ? ? ? ? ? /* MBAR_ETH + 0x008 */
> +
> + ? ? ? uint32_t RES1[1]; ? ? ? ? ? ? ? /* MBAR_ETH + 0x00C */
> + ? ? ? uint32_t r_des_active; ? ? ? ? ?/* MBAR_ETH + 0x010 */
> + ? ? ? uint32_t x_des_active; ? ? ? ? ?/* MBAR_ETH + 0x014 */
> + ? ? ? uint32_t RES2[3]; ? ? ? ? ? ? ? /* MBAR_ETH + 0x018-20 */
> + ? ? ? uint32_t ecntrl; ? ? ? ? ? ? ? ?/* MBAR_ETH + 0x024 */
> +
> + ? ? ? uint32_t RES3[6]; ? ? ? ? ? ? ? /* MBAR_ETH + 0x028-03C */
> + ? ? ? uint32_t mii_data; ? ? ? ? ? ? ?/* MBAR_ETH + 0x040 */
> + ? ? ? uint32_t mii_speed; ? ? ? ? ? ? /* MBAR_ETH + 0x044 */
> + ? ? ? uint32_t RES4[7]; ? ? ? ? ? ? ? /* MBAR_ETH + 0x048-60 */
> + ? ? ? uint32_t mib_control; ? ? ? ? ? /* MBAR_ETH + 0x064 */
> +
> + ? ? ? uint32_t RES5[7]; ? ? ? ? ? ? ? /* MBAR_ETH + 0x068-80 */
> + ? ? ? uint32_t r_cntrl; ? ? ? ? ? ? ? /* MBAR_ETH + 0x084 */
> + ? ? ? uint32_t RES6[15]; ? ? ? ? ? ? ?/* MBAR_ETH + 0x088-C0 */
> + ? ? ? uint32_t x_cntrl; ? ? ? ? ? ? ? /* MBAR_ETH + 0x0C4 */
> + ? ? ? uint32_t RES7[7]; ? ? ? ? ? ? ? /* MBAR_ETH + 0x0C8-E0 */
> + ? ? ? uint32_t paddr1; ? ? ? ? ? ? ? ?/* MBAR_ETH + 0x0E4 */
> + ? ? ? uint32_t paddr2; ? ? ? ? ? ? ? ?/* MBAR_ETH + 0x0E8 */
> + ? ? ? uint32_t op_pause; ? ? ? ? ? ? ?/* MBAR_ETH + 0x0EC */
> +
> + ? ? ? uint32_t RES8[10]; ? ? ? ? ? ? ?/* MBAR_ETH + 0x0F0-114 */
> + ? ? ? uint32_t iaddr1; ? ? ? ? ? ? ? ?/* MBAR_ETH + 0x118 */
> + ? ? ? uint32_t iaddr2; ? ? ? ? ? ? ? ?/* MBAR_ETH + 0x11C */
> + ? ? ? uint32_t gaddr1; ? ? ? ? ? ? ? ?/* MBAR_ETH + 0x120 */
> + ? ? ? uint32_t gaddr2; ? ? ? ? ? ? ? ?/* MBAR_ETH + 0x124 */
> + ? ? ? uint32_t RES9[7]; ? ? ? ? ? ? ? /* MBAR_ETH + 0x128-140 */
> +
> + ? ? ? uint32_t x_wmrk; ? ? ? ? ? ? ? ?/* MBAR_ETH + 0x144 */
> + ? ? ? uint32_t RES10[1]; ? ? ? ? ? ? ?/* MBAR_ETH + 0x148 */
> + ? ? ? uint32_t r_bound; ? ? ? ? ? ? ? /* MBAR_ETH + 0x14C */
> + ? ? ? uint32_t r_fstart; ? ? ? ? ? ? ?/* MBAR_ETH + 0x150 */
> + ? ? ? uint32_t RES11[11]; ? ? ? ? ? ? /* MBAR_ETH + 0x154-17C */
> + ? ? ? uint32_t erdsr; ? ? ? ? ? ? ? ? /* MBAR_ETH + 0x180 */
> + ? ? ? uint32_t etdsr; ? ? ? ? ? ? ? ? /* MBAR_ETH + 0x184 */
> + ? ? ? uint32_t emrbr; ? ? ? ? ? ? ? ? /* MBAR_ETH + 0x188 */
> + ? ? ? uint32_t RES12[29]; ? ? ? ? ? ? /* MBAR_ETH + 0x18C-1FC */
> +
> +/* ?MIB COUNTERS (Offset 200-2FF) */
> +
> + ? ? ? uint32_t rmon_t_drop; ? ? ? ? ? /* MBAR_ETH + 0x200 */
> + ? ? ? uint32_t rmon_t_packets; ? ? ? ?/* MBAR_ETH + 0x204 */
> + ? ? ? uint32_t rmon_t_bc_pkt; ? ? ? ? /* MBAR_ETH + 0x208 */
> + ? ? ? uint32_t rmon_t_mc_pkt; ? ? ? ? /* MBAR_ETH + 0x20C */
> + ? ? ? uint32_t rmon_t_crc_align; ? ? ?/* MBAR_ETH + 0x210 */
> + ? ? ? uint32_t rmon_t_undersize; ? ? ?/* MBAR_ETH + 0x214 */
> + ? ? ? uint32_t rmon_t_oversize; ? ? ? /* MBAR_ETH + 0x218 */
> + ? ? ? uint32_t rmon_t_frag; ? ? ? ? ? /* MBAR_ETH + 0x21C */
> + ? ? ? uint32_t rmon_t_jab; ? ? ? ? ? ?/* MBAR_ETH + 0x220 */
> + ? ? ? uint32_t rmon_t_col; ? ? ? ? ? ?/* MBAR_ETH + 0x224 */
> + ? ? ? uint32_t rmon_t_p64; ? ? ? ? ? ?/* MBAR_ETH + 0x228 */
> + ? ? ? uint32_t rmon_t_p65to127; ? ? ? /* MBAR_ETH + 0x22C */
> + ? ? ? uint32_t rmon_t_p128to255; ? ? ?/* MBAR_ETH + 0x230 */
> + ? ? ? uint32_t rmon_t_p256to511; ? ? ?/* MBAR_ETH + 0x234 */
> + ? ? ? uint32_t rmon_t_p512to1023; ? ? /* MBAR_ETH + 0x238 */
> + ? ? ? uint32_t rmon_t_p1024to2047; ? ?/* MBAR_ETH + 0x23C */
> + ? ? ? uint32_t rmon_t_p_gte2048; ? ? ?/* MBAR_ETH + 0x240 */
> + ? ? ? uint32_t rmon_t_octets; ? ? ? ? /* MBAR_ETH + 0x244 */
> + ? ? ? uint32_t ieee_t_drop; ? ? ? ? ? /* MBAR_ETH + 0x248 */
> + ? ? ? uint32_t ieee_t_frame_ok; ? ? ? /* MBAR_ETH + 0x24C */
> + ? ? ? uint32_t ieee_t_1col; ? ? ? ? ? /* MBAR_ETH + 0x250 */
> + ? ? ? uint32_t ieee_t_mcol; ? ? ? ? ? /* MBAR_ETH + 0x254 */
> + ? ? ? uint32_t ieee_t_def; ? ? ? ? ? ?/* MBAR_ETH + 0x258 */
> + ? ? ? uint32_t ieee_t_lcol; ? ? ? ? ? /* MBAR_ETH + 0x25C */
> + ? ? ? uint32_t ieee_t_excol; ? ? ? ? ?/* MBAR_ETH + 0x260 */
> + ? ? ? uint32_t ieee_t_macerr; ? ? ? ? /* MBAR_ETH + 0x264 */
> + ? ? ? uint32_t ieee_t_cserr; ? ? ? ? ?/* MBAR_ETH + 0x268 */
> + ? ? ? uint32_t ieee_t_sqe; ? ? ? ? ? ?/* MBAR_ETH + 0x26C */
> + ? ? ? uint32_t t_fdxfc; ? ? ? ? ? ? ? /* MBAR_ETH + 0x270 */
> + ? ? ? uint32_t ieee_t_octets_ok; ? ? ?/* MBAR_ETH + 0x274 */
> +
> + ? ? ? uint32_t RES13[2]; ? ? ? ? ? ? ?/* MBAR_ETH + 0x278-27C */
> + ? ? ? uint32_t rmon_r_drop; ? ? ? ? ? /* MBAR_ETH + 0x280 */
> + ? ? ? uint32_t rmon_r_packets; ? ? ? ?/* MBAR_ETH + 0x284 */
> + ? ? ? uint32_t rmon_r_bc_pkt; ? ? ? ? /* MBAR_ETH + 0x288 */
> + ? ? ? uint32_t rmon_r_mc_pkt; ? ? ? ? /* MBAR_ETH + 0x28C */
> + ? ? ? uint32_t rmon_r_crc_align; ? ? ?/* MBAR_ETH + 0x290 */
> + ? ? ? uint32_t rmon_r_undersize; ? ? ?/* MBAR_ETH + 0x294 */
> + ? ? ? uint32_t rmon_r_oversize; ? ? ? /* MBAR_ETH + 0x298 */
> + ? ? ? uint32_t rmon_r_frag; ? ? ? ? ? /* MBAR_ETH + 0x29C */
> + ? ? ? uint32_t rmon_r_jab; ? ? ? ? ? ?/* MBAR_ETH + 0x2A0 */
> +
> + ? ? ? uint32_t rmon_r_resvd_0; ? ? ? ?/* MBAR_ETH + 0x2A4 */
> +
> + ? ? ? uint32_t rmon_r_p64; ? ? ? ? ? ?/* MBAR_ETH + 0x2A8 */
> + ? ? ? uint32_t rmon_r_p65to127; ? ? ? /* MBAR_ETH + 0x2AC */
> + ? ? ? uint32_t rmon_r_p128to255; ? ? ?/* MBAR_ETH + 0x2B0 */
> + ? ? ? uint32_t rmon_r_p256to511; ? ? ?/* MBAR_ETH + 0x2B4 */
> + ? ? ? uint32_t rmon_r_p512to1023; ? ? /* MBAR_ETH + 0x2B8 */
> + ? ? ? uint32_t rmon_r_p1024to2047; ? ?/* MBAR_ETH + 0x2BC */
> + ? ? ? uint32_t rmon_r_p_gte2048; ? ? ?/* MBAR_ETH + 0x2C0 */
> + ? ? ? uint32_t rmon_r_octets; ? ? ? ? /* MBAR_ETH + 0x2C4 */
> + ? ? ? uint32_t ieee_r_drop; ? ? ? ? ? /* MBAR_ETH + 0x2C8 */
> + ? ? ? uint32_t ieee_r_frame_ok; ? ? ? /* MBAR_ETH + 0x2CC */
> + ? ? ? uint32_t ieee_r_crc; ? ? ? ? ? ?/* MBAR_ETH + 0x2D0 */
> + ? ? ? uint32_t ieee_r_align; ? ? ? ? ?/* MBAR_ETH + 0x2D4 */
> + ? ? ? uint32_t r_macerr; ? ? ? ? ? ? ?/* MBAR_ETH + 0x2D8 */
> + ? ? ? uint32_t r_fdxfc; ? ? ? ? ? ? ? /* MBAR_ETH + 0x2DC */
> + ? ? ? uint32_t ieee_r_octets_ok; ? ? ?/* MBAR_ETH + 0x2E0 */
> +
> + ? ? ? uint32_t RES14[6]; ? ? ? ? ? ? ?/* MBAR_ETH + 0x2E4-2FC */
> +
> + ? ? ? uint32_t RES15[64]; ? ? ? ? ? ? /* MBAR_ETH + 0x300-3FF */
> +};
> +
> +#define FEC_IEVENT_HBERR ? ? ? ? ? ? ? 0x80000000
> +#define FEC_IEVENT_BABR ? ? ? ? ? ? ? ? ? ? ? ?0x40000000
> +#define FEC_IEVENT_BABT ? ? ? ? ? ? ? ? ? ? ? ?0x20000000
> +#define FEC_IEVENT_GRA ? ? ? ? ? ? ? ? 0x10000000
> +#define FEC_IEVENT_TXF ? ? ? ? ? ? ? ? 0x08000000
> +#define FEC_IEVENT_TXB ? ? ? ? ? ? ? ? 0x04000000
> +#define FEC_IEVENT_RXF ? ? ? ? ? ? ? ? 0x02000000
> +#define FEC_IEVENT_RXB ? ? ? ? ? ? ? ? 0x01000000
> +#define FEC_IEVENT_MII ? ? ? ? ? ? ? ? 0x00800000
> +#define FEC_IEVENT_EBERR ? ? ? ? ? ? ? 0x00400000
> +#define FEC_IEVENT_LC ? ? ? ? ? ? ? ? ?0x00200000
> +#define FEC_IEVENT_RL ? ? ? ? ? ? ? ? ?0x00100000
> +#define FEC_IEVENT_UN ? ? ? ? ? ? ? ? ?0x00080000
> +
> +#define FEC_IMASK_HBERR ? ? ? ? ? ? ? ? ? ? ? ?0x80000000
> +#define FEC_IMASK_BABR ? ? ? ? ? ? ? ? 0x40000000
> +#define FEC_IMASKT_BABT ? ? ? ? ? ? ? ? ? ? ? ?0x20000000
> +#define FEC_IMASK_GRA ? ? ? ? ? ? ? ? ?0x10000000
> +#define FEC_IMASKT_TXF ? ? ? ? ? ? ? ? 0x08000000
> +#define FEC_IMASK_TXB ? ? ? ? ? ? ? ? ?0x04000000
> +#define FEC_IMASKT_RXF ? ? ? ? ? ? ? ? 0x02000000
> +#define FEC_IMASK_RXB ? ? ? ? ? ? ? ? ?0x01000000
> +#define FEC_IMASK_MII ? ? ? ? ? ? ? ? ?0x00800000
> +#define FEC_IMASK_EBERR ? ? ? ? ? ? ? ? ? ? ? ?0x00400000
> +#define FEC_IMASK_LC ? ? ? ? ? ? ? ? ? 0x00200000
> +#define FEC_IMASKT_RL ? ? ? ? ? ? ? ? ?0x00100000
> +#define FEC_IMASK_UN ? ? ? ? ? ? ? ? ? 0x00080000
> +
> +
> +#define FEC_RCNTRL_MAX_FL_SHIFT ? ? ? ? ? ? ? ?16
> +#define FEC_RCNTRL_LOOP ? ? ? ? ? ? ? ? ? ? ? ?0x00000001
> +#define FEC_RCNTRL_DRT ? ? ? ? ? ? ? ? 0x00000002
> +#define FEC_RCNTRL_MII_MODE ? ? ? ? ? ?0x00000004
> +#define FEC_RCNTRL_PROM ? ? ? ? ? ? ? ? ? ? ? ?0x00000008
> +#define FEC_RCNTRL_BC_REJ ? ? ? ? ? ? ?0x00000010
> +#define FEC_RCNTRL_FCE ? ? ? ? ? ? ? ? 0x00000020
> +
> +#define FEC_TCNTRL_GTS ? ? ? ? ? ? ? ? 0x00000001
> +#define FEC_TCNTRL_HBC ? ? ? ? ? ? ? ? 0x00000002
> +#define FEC_TCNTRL_FDEN ? ? ? ? ? ? ? ? ? ? ? ?0x00000004
> +#define FEC_TCNTRL_TFC_PAUSE ? ? ? ? ? 0x00000008
> +#define FEC_TCNTRL_RFC_PAUSE ? ? ? ? ? 0x00000010
> +
> +#define FEC_ECNTRL_RESET ? ? ? ? ? ? ? 0x00000001 ? ? ?/* reset the FEC */
> +#define FEC_ECNTRL_ETHER_EN ? ? ? ? ? ?0x00000002 ? ? ?/* enable the FEC */
> +
> +/**
> + * @brief Descriptor buffer alignment
> + *
> + * i.MX27 requires a 16 byte alignment (but for the first element only)
> + */
> +#define DB_ALIGNMENT ? ? ? ? ? 16
> +
> +/**
> + * @brief Data buffer alignment
> + *
> + * i.MX27 requires a four byte alignment for transmit and 16 bits
> + * alignment for receive so take 16
> + * Note: Valid for member data_pointer in struct buffer_descriptor
> + */
> +#define DB_DATA_ALIGNMENT ? ? ?16
> +
> +/**
> + * @brief Receive & Transmit Buffer Descriptor definitions
> + *
> + * Note: The first BD must be aligned (see DB_ALIGNMENT)
> + */
> +struct fec_bd {
> + ? ? ? uint16_t data_length; ? ? ? ? ? /* payload's length in bytes */
> + ? ? ? uint16_t status; ? ? ? ? ? ? ? ?/* BD's staus (see datasheet) */
> + ? ? ? uint32_t data_pointer; ? ? ? ? ?/* payload's buffer address */
> +};
> +
> +/**
> + * Supported phy types on this platform
> + */
> +enum xceiver_type {
> + ? ? ? SEVENWIRE, ? ? ?/* 7-wire ? ? ? */
> + ? ? ? MII10, ? ? ? ? ?/* MII 10Mbps ? */
> + ? ? ? MII100 ? ? ? ? ?/* MII 100Mbps ?*/
> +};
> +
> +/**
> + * @brief i.MX27-FEC private structure
> + */
> +struct fec_priv {
> + ? ? ? struct ethernet_regs *eth; ? ? ?/* pointer to register'S base */
> + ? ? ? enum xceiver_type xcv_type; ? ? /* transceiver type */
> + ? ? ? struct fec_bd *rbd_base; ? ? ? ?/* RBD ring */
> + ? ? ? int rbd_index; ? ? ? ? ? ? ? ? ?/* next receive BD to read */
> + ? ? ? struct fec_bd *tbd_base; ? ? ? ?/* TBD ring */
> + ? ? ? int tbd_index; ? ? ? ? ? ? ? ? ?/* next transmit BD to write */
> + ? ? ? bd_t *bd;
> +};
> +
> +/**
> + * @brief Numbers of buffer descriptors for receiving
> + *
> + * The number defines the stocked memory buffers for the receiving task.
> + * Larger values makes no sense in this limited environment.
> + */
> +#define FEC_RBD_NUM ? ? ? ? ? ?64
> +
> +/**
> + * @brief Define the ethernet packet size limit in memory
> + *
> + * Note: Do not shrink this number. This will force the FEC to spread larger
> + * frames in more than one BD. This is nothing to worry about, but the current
> + * driver can't handle it.
> + */
> +#define FEC_MAX_PKT_SIZE ? ? ? 1536
> +
> +/* Receive BD status bits */
> +#define FEC_RBD_EMPTY ?0x8000 ?/* Receive BD status: Buffer is empty */
> +#define FEC_RBD_WRAP ? 0x2000 ?/* Receive BD status: Last BD in ring */
> +/* Receive BD status: Buffer is last in frame (useless here!) */
> +#define FEC_RBD_LAST ? 0x0800
> +#define FEC_RBD_MISS ? 0x0100 ?/* Receive BD status: Miss bit for prom mode */
> +/* Receive BD status: The received frame is broadcast frame */
> +#define FEC_RBD_BC ? ? 0x0080
> +/* Receive BD status: The received frame is multicast frame */
> +#define FEC_RBD_MC ? ? 0x0040
> +#define FEC_RBD_LG ? ? 0x0020 ?/* Receive BD status: Frame length violation */
> +#define FEC_RBD_NO ? ? 0x0010 ?/* Receive BD status: Nonoctet align frame */
> +#define FEC_RBD_CR ? ? 0x0004 ?/* Receive BD status: CRC error */
> +#define FEC_RBD_OV ? ? 0x0002 ?/* Receive BD status: Receive FIFO overrun */
> +#define FEC_RBD_TR ? ? 0x0001 ?/* Receive BD status: Frame is truncated */
> +#define FEC_RBD_ERR ? ?(FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
> + ? ? ? ? ? ? ? ? ? ? ? FEC_RBD_OV | FEC_RBD_TR)
> +
> +/* Transmit BD status bits */
> +#define FEC_TBD_READY ?0x8000 ?/* Tansmit BD status: Buffer is ready */
> +#define FEC_TBD_WRAP ? 0x2000 ?/* Tansmit BD status: Mark as last BD in ring */
> +#define FEC_TBD_LAST ? 0x0800 ?/* Tansmit BD status: Buffer is last in frame */
> +#define FEC_TBD_TC ? ? 0x0400 ?/* Tansmit BD status: Transmit the CRC */
> +#define FEC_TBD_ABC ? ?0x0200 ?/* Tansmit BD status: Append bad CRC */
> +
> +/* MII-related definitios */
> +#define FEC_MII_DATA_ST ? ? ? ? ? ? ? ?0x40000000 ? ? ?/* Start of frame delimiter */
> +#define FEC_MII_DATA_OP_RD ? ? 0x20000000 ? ? ?/* Perform a read operation */
> +#define FEC_MII_DATA_OP_WR ? ? 0x10000000 ? ? ?/* Perform a write operation */
> +#define FEC_MII_DATA_PA_MSK ? ?0x0f800000 ? ? ?/* PHY Address field mask */
> +#define FEC_MII_DATA_RA_MSK ? ?0x007c0000 ? ? ?/* PHY Register field mask */
> +#define FEC_MII_DATA_TA ? ? ? ? ? ? ? ?0x00020000 ? ? ?/* Turnaround */
> +#define FEC_MII_DATA_DATAMSK ? 0x0000ffff ? ? ?/* PHY data field */
> +
> +#define FEC_MII_DATA_RA_SHIFT ?18 ? ? ?/* MII Register address bits */
> +#define FEC_MII_DATA_PA_SHIFT ?23 ? ? ?/* MII PHY address bits */
> +
> +#endif /* __IMX27_FEC_H */
> diff --git a/include/netdev.h b/include/netdev.h
> index 63cf730..2d999ad 100644
> --- a/include/netdev.h
> +++ b/include/netdev.h
> @@ -49,6 +49,7 @@ int e1000_initialize(bd_t *bis);
> ?int eepro100_initialize(bd_t *bis);
> ?int eth_3com_initialize (bd_t * bis);
> ?int fec_initialize (bd_t *bis);
> +int fecimx27_initialize (bd_t *bis);
> ?int greth_initialize(bd_t *bis);
> ?void gt6426x_eth_initialize(bd_t *bis);
> ?int inca_switch_initialize(bd_t *bis);
> --
> 1.6.0.6
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-06-15 14:01 ` Johan
@ 2009-06-15 19:59 ` Eric Lammerts
2009-06-16 7:12 ` Johan
2009-06-23 17:37 ` [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC Ethernet " Bill Cook
0 siblings, 2 replies; 42+ messages in thread
From: Eric Lammerts @ 2009-06-15 19:59 UTC (permalink / raw)
To: u-boot
On 06/15/09 10:01, Johan wrote:
> I have trouble using your patch together with our LogicPD iMX27
> Litekit. Seems like the FEC driver does not work well. Here is some
> output from when I try to load files with tftp
<snip>
> Loading: #####T #####################T #########################T ############T#
> #########################T ########################################
> ##T ####################################T #########T T #########
> Retry count exceeded; starting again
<snip>
> I have downloaded the imx27lite head from the u-boot testing branch. I
> have also tried to patch the u-boot-2009.06-rc3 branch with your
> patches, but it does not seem to be any different. Do you have any
> ideas what might be wrong?
Did you have working ethernet before (with a different bootloader or in
Linux)? Do you have the breakout board installed? I have the same board
(but maybe an older revision; about a year old) and with the breakout
board mounted my ethernet would behave the same way as yours. They routed
the MII signals all the way to the headers on the breakout board, and
that causes signal integrity problems. It could be that they fixed it on
later revisions though (not sure).
I'm using u-boot-v2, so I don't know anything about the u-boot fec driver.
Eric
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-06-15 19:59 ` Eric Lammerts
@ 2009-06-16 7:12 ` Johan
2009-06-17 22:19 ` Ilya Yanok
2009-06-19 23:59 ` Wolfgang Denk
2009-06-23 17:37 ` [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC Ethernet " Bill Cook
1 sibling, 2 replies; 42+ messages in thread
From: Johan @ 2009-06-16 7:12 UTC (permalink / raw)
To: u-boot
Seems like that was the trick. After removing the breakout board it
works much better.
I still got some problems which I don't know if its software related.
Sometimes when I power on the board the ethernet LEDs does not turn
green and the network does not work. If I power cycle the board a
number of times the LEDs turn green I can can use the network. Do you
know if that might be hw related or may it be something with the
initialization?
I'll try to test U-boot v2 as you are using and see if it works better.
/Johan
2009/6/15 Eric Lammerts <u-boot@lists.lammerts.org>:
> On 06/15/09 10:01, Johan wrote:
>> I have trouble using your patch together with our LogicPD iMX27
>> Litekit. Seems like the FEC driver does not work well. Here is some
>> output from when I try to load files with tftp
>
> <snip>
>> Loading: #####T #####################T #########################T ############T#
>> ? ? ? ? ?#########################T ########################################
>> ? ? ? ? ?##T ####################################T #########T T #########
>> Retry count exceeded; starting again
>
> <snip>
>> I have downloaded the imx27lite head from the u-boot testing branch. I
>> have also tried to patch the u-boot-2009.06-rc3 branch with your
>> patches, but it does not seem to be any different. Do you have any
>> ideas what might be wrong?
>
> Did you have working ethernet before (with a different bootloader or in
> Linux)? Do you have the breakout board installed? I have the same board
> (but maybe an older revision; about a year old) and with the breakout
> board mounted my ethernet would behave the same way as yours. They routed
> the MII signals all the way to the headers on the breakout board, and
> that causes signal integrity problems. It could be that they fixed it on
> later revisions though (not sure).
>
> I'm using u-boot-v2, so I don't know anything about the u-boot fec driver.
>
> Eric
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-06-16 7:12 ` Johan
@ 2009-06-17 22:19 ` Ilya Yanok
2009-06-19 23:59 ` Wolfgang Denk
1 sibling, 0 replies; 42+ messages in thread
From: Ilya Yanok @ 2009-06-17 22:19 UTC (permalink / raw)
To: u-boot
Hi Johan,
> Seems like that was the trick. After removing the breakout board it
> works much better.
>
> I still got some problems which I don't know if its software related.
> Sometimes when I power on the board the ethernet LEDs does not turn
> green and the network does not work. If I power cycle the board a
> number of times the LEDs turn green I can can use the network. Do you
> know if that might be hw related or may it be something with the
> initialization?
>
> I'll try to test U-boot v2 as you are using and see if it works better.
>
Our customer reported the same problem but we can't reproduce it on our
hardware... Could you please tell me if U-Boot v2 works for you well?
Regards, Ilya.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27
2009-06-16 7:12 ` Johan
2009-06-17 22:19 ` Ilya Yanok
@ 2009-06-19 23:59 ` Wolfgang Denk
1 sibling, 0 replies; 42+ messages in thread
From: Wolfgang Denk @ 2009-06-19 23:59 UTC (permalink / raw)
To: u-boot
Dear Johan,
In message <de9b121e0906160012q5975b23cnd320908aee6cd4ab@mail.gmail.com> you wrote:
> Seems like that was the trick. After removing the breakout board it
> works much better.
>
> I still got some problems which I don't know if its software related.
> Sometimes when I power on the board the ethernet LEDs does not turn
> green and the network does not work. If I power cycle the board a
> number of times the LEDs turn green I can can use the network. Do you
> know if that might be hw related or may it be something with the
> initialization?
This is most likely a hardware problem. Please contach Logic for
information about the required changes on the board.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"May the forces of evil become confused on the way to your house."
- George Carlin
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC Ethernet controller on i.MX27
2009-06-15 19:59 ` Eric Lammerts
2009-06-16 7:12 ` Johan
@ 2009-06-23 17:37 ` Bill Cook
1 sibling, 0 replies; 42+ messages in thread
From: Bill Cook @ 2009-06-23 17:37 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Eric Lammerts [mailto:u-boot at lists.lammerts.org]
> Sent: Monday, June 15, 2009 3:59 PM
> To: Johan
> Cc: u-boot at lists.denx.de; Ilya Yanok
> Subject: Re: [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet
> controller on i.MX27
>
>
> On 06/15/09 10:01, Johan wrote:
> > I have trouble using your patch together with our LogicPD iMX27
> > Litekit. Seems like the FEC driver does not work well. Here is some
> > output from when I try to load files with tftp
>
> <snip>
> > Loading: #####T #####################T #########################T
> ############T#
> > #########################T ########################################
> > ##T ####################################T #########T T #########
> > Retry count exceeded; starting again
>
> <snip>
> > I have downloaded the imx27lite head from the u-boot testing branch. I
> > have also tried to patch the u-boot-2009.06-rc3 branch with your
> > patches, but it does not seem to be any different. Do you have any
> > ideas what might be wrong?
>
> Did you have working ethernet before (with a different bootloader or in
> Linux)? Do you have the breakout board installed? I have the same board
> (but maybe an older revision; about a year old) and with the breakout
> board mounted my ethernet would behave the same way as yours. They routed
> the MII signals all the way to the headers on the breakout board, and
> that causes signal integrity problems. It could be that they fixed it on
> later revisions though (not sure).
>
> I'm using u-boot-v2, so I don't know anything about the u-boot fec driver.
>
> Eric
>
I'm trying to debug ethernet problems on a custom iMX27 board with
same LAN chip as the logicPD liteKit. I don't claim to be an expert,
but it seems that in the fec driver posted by Ilya, the phy address
for MII access is hard coded to a 0, whereas on the board it defaults
to 0x1f. When I turned on DEBUG in fec_imx27.c, the MII reads always
return all 1's. The phy works, but maybe by good fortune, not intent.
Bill Cook
cook at isgchips.com
Imaging Solutions Group Inc;
http://www.isgcameras.com
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-05-19 23:55 [U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
` (2 preceding siblings ...)
2009-05-19 23:55 ` [U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27 Ilya Yanok
@ 2009-05-19 23:55 ` Ilya Yanok
2009-05-28 23:06 ` Wolfgang Denk
2009-05-19 23:55 ` [U-Boot] [PATCH 5/7] mxc-mmc: sdhc host driver for MX2 and MX3 proccessor Ilya Yanok
` (3 subsequent siblings)
7 siblings, 1 reply; 42+ messages in thread
From: Ilya Yanok @ 2009-05-19 23:55 UTC (permalink / raw)
To: u-boot
Driver for NFC NAND controller found on Freescale's MX2 and MX3
processors. Ported from Linux. Tested only with i.MX27 but should
works with other MX2 and MX3 processors too.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/mxc_nand.c | 923 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 924 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/mxc_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 471cd6b..24de947 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
new file mode 100644
index 0000000..fe488c5
--- /dev/null
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -0,0 +1,923 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Sascha Hauer, kernel at pengutronix.de
+ * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#ifdef CONFIG_MX27
+#include <asm/arch/imx-regs.h>
+#endif
+
+#define DRIVER_NAME "mxc_nand"
+
+struct nfc_regs {
+/* NFC RAM BUFFER Main area 0 */
+ uint8_t MAIN_AREA0[0x200];
+ uint8_t MAIN_AREA1[0x200];
+ uint8_t MAIN_AREA2[0x200];
+ uint8_t MAIN_AREA3[0x200];
+/* SPARE BUFFER Spare area 0 */
+ uint8_t SPARE_AREA0[0x10];
+ uint8_t SPARE_AREA1[0x10];
+ uint8_t SPARE_AREA2[0x10];
+ uint8_t SPARE_AREA3[0x10];
+ uint8_t pad[0x5c0];
+/* NFC registers */
+ uint16_t NFC_BUF_SIZE;
+ uint16_t reserved;
+ uint16_t NFC_BUF_ADDR;
+ uint16_t NFC_FLASH_ADDR;
+ uint16_t NFC_FLASH_CMD;
+ uint16_t NFC_CONFIG;
+ uint16_t NFC_ECC_STATUS_RESULT;
+ uint16_t NFC_RSLTMAIN_AREA;
+ uint16_t NFC_RSLTSPARE_AREA;
+ uint16_t NFC_WRPROT;
+ uint16_t NFC_UNLOCKSTART_BLKADDR;
+ uint16_t NFC_UNLOCKEND_BLKADDR;
+ uint16_t NFC_NF_WRPRST;
+ uint16_t NFC_CONFIG1;
+ uint16_t NFC_CONFIG2;
+};
+
+/*
+ * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
+ * for Command operation
+ */
+#define NFC_CMD 0x1
+
+/*
+ * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
+ * for Address operation
+ */
+#define NFC_ADDR 0x2
+
+/*
+ * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
+ * for Input operation
+ */
+#define NFC_INPUT 0x4
+
+/*
+ * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
+ * for Data Output operation
+ */
+#define NFC_OUTPUT 0x8
+
+/*
+ * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
+ * for Read ID operation
+ */
+#define NFC_ID 0x10
+
+/*
+ * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
+ * for Read Status operation
+ */
+#define NFC_STATUS 0x20
+
+/*
+ * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
+ * Status operation
+ */
+#define NFC_INT 0x8000
+
+#define NFC_SP_EN (1 << 2)
+#define NFC_ECC_EN (1 << 3)
+#define NFC_BIG (1 << 5)
+#define NFC_RST (1 << 6)
+#define NFC_CE (1 << 7)
+#define NFC_ONE_CYCLE (1 << 8)
+
+typedef enum {false, true} bool;
+
+struct mxc_nand_host {
+ struct mtd_info mtd;
+ struct nand_chip *nand;
+
+ struct nfc_regs __iomem *regs;
+ int spare_only;
+ int status_request;
+ int pagesize_2k;
+ int clk_act;
+ uint16_t col_addr;
+};
+
+static struct mxc_nand_host mxc_host;
+static struct mxc_nand_host *host = &mxc_host;
+
+/* Define delays in microsec for NAND device operations */
+#define TROP_US_DELAY 2000
+/* Macros to get byte and bit positions of ECC */
+#define COLPOS(x) ((x) >> 3)
+#define BITPOS(x) ((x) & 0xf)
+
+/* Define single bit Error positions in Main & Spare area */
+#define MAIN_SINGLEBIT_ERROR 0x4
+#define SPARE_SINGLEBIT_ERROR 0x1
+
+/* OOB placement block for use with hardware ecc generation */
+static struct nand_ecclayout nand_hw_eccoob_8 = {
+ .eccbytes = 5,
+ .eccpos = {6, 7, 8, 9, 10},
+ .oobfree = {{0, 5}, {11, 5}, }
+};
+
+static struct nand_ecclayout nand_hw_eccoob_16 = {
+ .eccbytes = 5,
+ .eccpos = {6, 7, 8, 9, 10},
+ .oobfree = {{0, 6}, {12, 4}, }
+};
+
+static void *mxc_nand_memcpy(void *dest, void *source, size_t size)
+{
+ uint32_t *s = source, *d = dest;
+
+ size >>= 2;
+ while (size--)
+ *d++ = *s++;
+ return dest;
+}
+
+/*
+ * This function polls the NANDFC to wait for the basic operation to
+ * complete by checking the INT bit of config2 register.
+ */
+static void wait_op_done(struct mxc_nand_host *host, int max_retries,
+ uint16_t param)
+{
+ uint32_t tmp;
+
+ while (max_retries-- > 0) {
+ if (readw(&host->regs->NFC_CONFIG2) & NFC_INT) {
+ tmp = readw(&host->regs->NFC_CONFIG2);
+ tmp &= ~NFC_INT;
+ writew(tmp, &host->regs->NFC_CONFIG2);
+ break;
+ }
+ udelay(1);
+ }
+ if (max_retries <= 0)
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
+ __func__, param);
+}
+
+/*
+ * This function issues the specified command to the NAND device and
+ * waits for completion.
+ */
+static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
+{
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
+
+ writew(cmd, &host->regs->NFC_FLASH_CMD);
+ writew(NFC_CMD, &host->regs->NFC_CONFIG2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, cmd);
+}
+
+/*
+ * This function sends an address (or partial address) to the
+ * NAND device. The address is used to select the source/destination for
+ * a NAND command.
+ */
+static void send_addr(struct mxc_nand_host *host, uint16_t addr)
+{
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
+
+ writew(addr, &host->regs->NFC_FLASH_ADDR);
+ writew(NFC_ADDR, &host->regs->NFC_CONFIG2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, addr);
+}
+
+/*
+ * This function requests the NANDFC to initate the transfer
+ * of data currently in the NANDFC RAM buffer to the NAND device.
+ */
+static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
+ int spare_only)
+{
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
+
+ /* NANDFC buffer 0 is used for page read/write */
+ writew(buf_id, &host->regs->NFC_BUF_ADDR);
+
+ /* Configure spare or page+spare access */
+ if (!host->pagesize_2k) {
+ uint16_t config1 = readw(&host->regs->NFC_CONFIG1);
+ if (spare_only)
+ config1 |= NFC_SP_EN;
+ else
+ config1 &= ~(NFC_SP_EN);
+ writew(config1, &host->regs->NFC_CONFIG1);
+ }
+
+ writew(NFC_INPUT, &host->regs->NFC_CONFIG2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, spare_only);
+}
+
+/*
+ * Requests NANDFC to initated the transfer of data from the
+ * NAND device into in the NANDFC ram buffer.
+ */
+static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
+ int spare_only)
+{
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
+
+ /* NANDFC buffer 0 is used for page read/write */
+ writew(buf_id, &host->regs->NFC_BUF_ADDR);
+
+ /* Configure spare or page+spare access */
+ if (!host->pagesize_2k) {
+ uint32_t config1 = readw(&host->regs->NFC_CONFIG1);
+ if (spare_only)
+ config1 |= NFC_SP_EN;
+ else
+ config1 &= ~NFC_SP_EN;
+ writew(config1, &host->regs->NFC_CONFIG1);
+ }
+
+ writew(NFC_OUTPUT, &host->regs->NFC_CONFIG2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, spare_only);
+}
+
+/* Request the NANDFC to perform a read of the NAND device ID. */
+static void send_read_id(struct mxc_nand_host *host)
+{
+ struct nand_chip *this = host->nand;
+ uint16_t tmp;
+
+ /* NANDFC buffer 0 is used for device ID output */
+ writew(0x0, &host->regs->NFC_BUF_ADDR);
+
+ /* Read ID into main buffer */
+ tmp = readw(&host->regs->NFC_CONFIG1);
+ tmp &= ~NFC_SP_EN;
+ writew(tmp, &host->regs->NFC_CONFIG1);
+
+ writew(NFC_ID, &host->regs->NFC_CONFIG2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, 0);
+
+ if (this->options & NAND_BUSWIDTH_16) {
+ void __iomem *main_buf = host->regs->MAIN_AREA0;
+ /* compress the ID info */
+ writeb(readb(main_buf + 2), main_buf + 1);
+ writeb(readb(main_buf + 4), main_buf + 2);
+ writeb(readb(main_buf + 6), main_buf + 3);
+ writeb(readb(main_buf + 8), main_buf + 4);
+ writeb(readb(main_buf + 10), main_buf + 5);
+ }
+}
+
+/*
+ * This function requests the NANDFC to perform a read of the
+ * NAND device status and returns the current status.
+ */
+static uint16_t get_dev_status(struct mxc_nand_host *host)
+{
+ void __iomem *main_buf = host->regs->MAIN_AREA1;
+ uint32_t store;
+ uint16_t ret, tmp;
+ /* Issue status request to NAND device */
+
+ /* store the main area1 first word, later do recovery */
+ store = readl(main_buf);
+ /*
+ * NANDFC buffer 1 is used for device status to prevent
+ * corruption of read/write buffer on status requests.
+ */
+ writew(1, &host->regs->NFC_BUF_ADDR);
+
+ /* Read status into main buffer */
+ tmp = readw(&host->regs->NFC_CONFIG1);
+ tmp &= ~NFC_SP_EN;
+ writew(tmp, &host->regs->NFC_CONFIG1);
+
+ writew(NFC_STATUS, &host->regs->NFC_CONFIG2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, 0);
+
+ /*
+ * Status is placed in first word of main buffer
+ * get status, then recovery area 1 data
+ */
+ ret = readw(main_buf);
+ writel(store, main_buf);
+
+ return ret;
+}
+
+/* This functions is used by upper layer to checks if device is ready */
+static int mxc_nand_dev_ready(struct mtd_info *mtd)
+{
+ /*
+ * NFC handles R/B internally. Therefore, this function
+ * always returns status as ready.
+ */
+ return 1;
+}
+
+#ifdef CONFIG_MXC_NAND_HWECC
+static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ /*
+ * If HW ECC is enabled, we turn it on during init. There is
+ * no need to enable again here.
+ */
+}
+
+static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
+ u_char *read_ecc, u_char *calc_ecc)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+
+ /*
+ * 1-Bit errors are automatically corrected in HW. No need for
+ * additional correction. 2-Bit errors cannot be corrected by
+ * HW ECC, so we need to return failure
+ */
+ uint16_t ecc_status = readw(&host->regs->NFC_ECC_STATUS_RESULT);
+
+ if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
+ MTDDEBUG(MTD_DEBUG_LEVEL0,
+ "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+ u_char *ecc_code)
+{
+ return 0;
+}
+#endif
+
+static u_char mxc_nand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ uint8_t ret = 0;
+ uint16_t col, rd_word;
+ uint16_t __iomem *main_buf =
+ (uint16_t __iomem *)host->regs->MAIN_AREA0;
+ uint16_t __iomem *spare_buf =
+ (uint16_t __iomem *)host->regs->SPARE_AREA0;
+
+ /* Check for status request */
+ if (host->status_request)
+ return get_dev_status(host) & 0xFF;
+
+ /* Get column for 16-bit access */
+ col = host->col_addr >> 1;
+
+ /* If we are accessing the spare region */
+ if (host->spare_only)
+ rd_word = readw(&spare_buf[col]);
+ else
+ rd_word = readw(&main_buf[col]);
+
+ /* Pick upper/lower byte of word from RAM buffer */
+ if (host->col_addr & 0x1)
+ ret = (rd_word >> 8) & 0xFF;
+ else
+ ret = rd_word & 0xFF;
+
+ /* Update saved column address */
+ host->col_addr++;
+
+ return ret;
+}
+
+static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ uint16_t col, rd_word, ret;
+ uint16_t __iomem *p;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "mxc_nand_read_word(col = %d)\n", host->col_addr);
+
+ col = host->col_addr;
+ /* Adjust saved column address */
+ if (col < mtd->writesize && host->spare_only)
+ col += mtd->writesize;
+
+ if (col < mtd->writesize)
+ p = (uint16_t __iomem *)(host->regs->MAIN_AREA0 + (col >> 1));
+ else
+ p = (uint16_t __iomem *)(host->regs->SPARE_AREA0 +
+ ((col - mtd->writesize) >> 1));
+
+ if (col & 1) {
+ rd_word = readw(p);
+ ret = (rd_word >> 8) & 0xff;
+ rd_word = readw(&p[1]);
+ ret |= (rd_word << 8) & 0xff00;
+
+ } else
+ ret = readw(p);
+
+ /* Update saved column address */
+ host->col_addr = col + 2;
+
+ return ret;
+}
+
+/*
+ * Write data of length len to buffer buf. The data to be
+ * written on NAND Flash is first copied to RAMbuffer. After the Data Input
+ * Operation by the NFC, the data is written to NAND Flash
+ */
+static void mxc_nand_write_buf(struct mtd_info *mtd,
+ const u_char *buf, int len)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ int n, col, i = 0;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
+ len);
+
+ col = host->col_addr;
+
+ /* Adjust saved column address */
+ if (col < mtd->writesize && host->spare_only)
+ col += mtd->writesize;
+
+ n = mtd->writesize + mtd->oobsize - col;
+ n = min(len, n);
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
+
+ while (n) {
+ void __iomem *p;
+
+ if (col < mtd->writesize)
+ p = host->regs->MAIN_AREA0 + (col & ~3);
+ else
+ p = host->regs->SPARE_AREA0 -
+ mtd->writesize + (col & ~3);
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
+ __LINE__, p);
+
+ if (((col | (int)&buf[i]) & 3) || n < 16) {
+ uint32_t data = 0;
+
+ if (col & 3 || n < 4)
+ data = readl(p);
+
+ switch (col & 3) {
+ case 0:
+ if (n) {
+ data = (data & 0xffffff00) |
+ (buf[i++] << 0);
+ n--;
+ col++;
+ }
+ case 1:
+ if (n) {
+ data = (data & 0xffff00ff) |
+ (buf[i++] << 8);
+ n--;
+ col++;
+ }
+ case 2:
+ if (n) {
+ data = (data & 0xff00ffff) |
+ (buf[i++] << 16);
+ n--;
+ col++;
+ }
+ case 3:
+ if (n) {
+ data = (data & 0x00ffffff) |
+ (buf[i++] << 24);
+ n--;
+ col++;
+ }
+ }
+
+ writel(data, p);
+ } else {
+ int m = mtd->writesize - col;
+
+ if (col >= mtd->writesize)
+ m += mtd->oobsize;
+
+ m = min(n, m) & ~3;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
+ __func__, __LINE__, n, m, i, col);
+
+ mxc_nand_memcpy(p, (void *)&buf[i], m);
+ col += m;
+ i += m;
+ n -= m;
+ }
+ }
+ /* Update saved column address */
+ host->col_addr = col;
+}
+
+/*
+ * Read the data buffer from the NAND Flash. To read the data from NAND
+ * Flash first the data output cycle is initiated by the NFC, which copies
+ * the data to RAMbuffer. This data of length len is then copied to buffer buf.
+ */
+static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ int n, col, i = 0;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
+
+ col = host->col_addr;
+
+ /* Adjust saved column address */
+ if (col < mtd->writesize && host->spare_only)
+ col += mtd->writesize;
+
+ n = mtd->writesize + mtd->oobsize - col;
+ n = min(len, n);
+
+ while (n) {
+ void __iomem *p;
+
+ if (col < mtd->writesize)
+ p = host->regs->MAIN_AREA0 + (col & ~3);
+ else
+ p = host->regs->SPARE_AREA0 -
+ mtd->writesize + (col & ~3);
+
+ if (((col | (int)&buf[i]) & 3) || n < 16) {
+ uint32_t data;
+
+ data = readl(p);
+ switch (col & 3) {
+ case 0:
+ if (n) {
+ buf[i++] = (uint8_t) (data);
+ n--;
+ col++;
+ }
+ case 1:
+ if (n) {
+ buf[i++] = (uint8_t) (data >> 8);
+ n--;
+ col++;
+ }
+ case 2:
+ if (n) {
+ buf[i++] = (uint8_t) (data >> 16);
+ n--;
+ col++;
+ }
+ case 3:
+ if (n) {
+ buf[i++] = (uint8_t) (data >> 24);
+ n--;
+ col++;
+ }
+ }
+ } else {
+ int m = mtd->writesize - col;
+
+ if (col >= mtd->writesize)
+ m += mtd->oobsize;
+
+ m = min(n, m) & ~3;
+ mxc_nand_memcpy(&buf[i], p, m);
+
+ col += m;
+ i += m;
+ n -= m;
+ }
+ }
+ /* Update saved column address */
+ host->col_addr = col;
+
+}
+
+/*
+ * Used by the upper layer to verify the data in NAND Flash
+ * with the data in the buf.
+ */
+static int mxc_nand_verify_buf(struct mtd_info *mtd,
+ const u_char *buf, int len)
+{
+ return -EFAULT;
+}
+
+/*
+ * This function is used by upper layer for select and
+ * deselect of the NAND chip
+ */
+static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+
+#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
+ if (chip > 0) {
+ MTDDEBUG(MTD_DEBUG_LEVEL0,
+ "ERROR: Illegal chip select (chip = %d)\n", chip);
+ return;
+ }
+
+ if (chip == -1) {
+ writew(readw(&host->regs->NFC_CONFIG1) & ~NFC_CE,
+ &host->regs->NFC_CONFIG1);
+ return;
+ }
+
+ writew(readw(&host->regs->NFC_CONFIG1) | NFC_CE,
+ &host->regs->NFC_CONFIG1);
+#endif
+
+ switch (chip) {
+ case -1:
+ /* TODO: Disable the NFC clock */
+ if (host->clk_act)
+ host->clk_act = 0;
+ break;
+ case 0:
+ /* TODO: Enable the NFC clock */
+ if (!host->clk_act)
+ host->clk_act = 1;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*
+ * Used by the upper layer to write command to NAND Flash for
+ * different operations to be carried out on NAND Flash
+ */
+static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
+ int column, int page_addr)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
+ command, column, page_addr);
+
+ /* Reset command state information */
+ host->status_request = false;
+
+ /* Command pre-processing step */
+ switch (command) {
+
+ case NAND_CMD_STATUS:
+ host->col_addr = 0;
+ host->status_request = true;
+ break;
+
+ case NAND_CMD_READ0:
+ host->col_addr = column;
+ host->spare_only = false;
+ break;
+
+ case NAND_CMD_READOOB:
+ host->col_addr = column;
+ host->spare_only = true;
+ if (host->pagesize_2k)
+ command = NAND_CMD_READ0; /* only READ0 is valid */
+ break;
+
+ case NAND_CMD_SEQIN:
+ if (column >= mtd->writesize) {
+ /*
+ * FIXME: before send SEQIN command for write OOB,
+ * We must read one page out.
+ * For K9F1GXX has no READ1 command to set current HW
+ * pointer to spare area, we must write the whole page
+ * including OOB together.
+ */
+ if (host->pagesize_2k)
+ /* call ourself to read a page */
+ mxc_nand_command(mtd, NAND_CMD_READ0, 0,
+ page_addr);
+
+ host->col_addr = column - mtd->writesize;
+ host->spare_only = true;
+
+ /* Set program pointer to spare region */
+ if (!host->pagesize_2k)
+ send_cmd(host, NAND_CMD_READOOB);
+ } else {
+ host->spare_only = false;
+ host->col_addr = column;
+
+ /* Set program pointer to page start */
+ if (!host->pagesize_2k)
+ send_cmd(host, NAND_CMD_READ0);
+ }
+ break;
+
+ case NAND_CMD_PAGEPROG:
+ send_prog_page(host, 0, host->spare_only);
+
+ if (host->pagesize_2k) {
+ /* data in 4 areas datas */
+ send_prog_page(host, 1, host->spare_only);
+ send_prog_page(host, 2, host->spare_only);
+ send_prog_page(host, 3, host->spare_only);
+ }
+
+ break;
+ }
+
+ /* Write out the command to the device. */
+ send_cmd(host, command);
+
+ /* Write out column address, if necessary */
+ if (column != -1) {
+ /*
+ * MXC NANDFC can only perform full page+spare or
+ * spare-only read/write. When the upper layers
+ * layers perform a read/write buf operation,
+ * we will used the saved column adress to index into
+ * the full page.
+ */
+ send_addr(host, 0);
+ if (host->pagesize_2k)
+ /* another col addr cycle for 2k page */
+ send_addr(host, 0);
+ }
+
+ /* Write out page address, if necessary */
+ if (page_addr != -1) {
+ /* paddr_0 - p_addr_7 */
+ send_addr(host, (page_addr & 0xff));
+
+ if (host->pagesize_2k) {
+ send_addr(host, (page_addr >> 8) & 0xFF);
+ if (mtd->size >= 0x40000000)
+ send_addr(host, (page_addr >> 16) & 0xff);
+ } else {
+ /* One more address cycle for higher density devices */
+ if (mtd->size >= 0x4000000) {
+ /* paddr_8 - paddr_15 */
+ send_addr(host, (page_addr >> 8) & 0xff);
+ send_addr(host, (page_addr >> 16) & 0xff);
+ } else
+ /* paddr_8 - paddr_15 */
+ send_addr(host, (page_addr >> 8) & 0xff);
+ }
+ }
+
+ /* Command post-processing step */
+ switch (command) {
+
+ case NAND_CMD_RESET:
+ break;
+
+ case NAND_CMD_READOOB:
+ case NAND_CMD_READ0:
+ if (host->pagesize_2k) {
+ /* send read confirm command */
+ send_cmd(host, NAND_CMD_READSTART);
+ /* read for each AREA */
+ send_read_page(host, 0, host->spare_only);
+ send_read_page(host, 1, host->spare_only);
+ send_read_page(host, 2, host->spare_only);
+ send_read_page(host, 3, host->spare_only);
+ } else
+ send_read_page(host, 0, host->spare_only);
+ break;
+
+ case NAND_CMD_READID:
+ send_read_id(host);
+ break;
+
+ case NAND_CMD_PAGEPROG:
+ break;
+
+ case NAND_CMD_STATUS:
+ break;
+
+ case NAND_CMD_ERASE2:
+ break;
+ }
+}
+
+int board_nand_init(struct nand_chip *this)
+{
+ struct system_control_regs *sc_regs =
+ (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+ struct mtd_info *mtd;
+ uint16_t tmp;
+ int err = 0;
+
+ /* structures must be linked */
+ mtd = &host->mtd;
+ mtd->priv = this;
+ host->nand = this;
+
+ /* 50 us command delay time */
+ this->chip_delay = 5;
+
+ this->priv = host;
+ this->dev_ready = mxc_nand_dev_ready;
+ this->cmdfunc = mxc_nand_command;
+ this->select_chip = mxc_nand_select_chip;
+ this->read_byte = mxc_nand_read_byte;
+ this->read_word = mxc_nand_read_word;
+ this->write_buf = mxc_nand_write_buf;
+ this->read_buf = mxc_nand_read_buf;
+ this->verify_buf = mxc_nand_verify_buf;
+
+ host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+ host->clk_act = 1;
+
+#ifdef CONFIG_MXC_NAND_HWECC
+ this->ecc.calculate = mxc_nand_calculate_ecc;
+ this->ecc.hwctl = mxc_nand_enable_hwecc;
+ this->ecc.correct = mxc_nand_correct_data;
+ this->ecc.mode = NAND_ECC_HW;
+ this->ecc.size = 512;
+ this->ecc.bytes = 3;
+ this->ecc.layout = &nand_hw_eccoob_8;
+ tmp = readw(&host->regs->NFC_CONFIG1);
+ tmp |= NFC_ECC_EN;
+ writew(tmp, &host->regs->NFC_CONFIG1);
+#else
+ this->ecc.size = 512;
+ this->ecc.bytes = 3;
+ this->ecc.layout = &nand_hw_eccoob_8;
+ this->ecc.mode = NAND_ECC_SOFT;
+ tmp = readw(&host->regs->NFC_CONFIG1);
+ tmp &= ~NFC_ECC_EN;
+ writew(tmp, &host->regs->NFC_CONFIG1);
+#endif
+
+ /* Reset NAND */
+ this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+ /*
+ * preset operation
+ * Unlock the internal RAM Buffer
+ */
+ writew(0x2, &host->regs->NFC_CONFIG);
+
+ /* Blocks to be unlocked */
+ writew(0x0, &host->regs->NFC_UNLOCKSTART_BLKADDR);
+ writew(0x4000, &host->regs->NFC_UNLOCKEND_BLKADDR);
+
+ /* Unlock Block Command for given address range */
+ writew(0x4, &host->regs->NFC_WRPROT);
+
+ /* NAND bus width determines access funtions used by upper layer */
+ if (readl(&sc_regs->FMCR) & NF_16BIT_SEL) {
+ this->options |= NAND_BUSWIDTH_16;
+ this->ecc.layout = &nand_hw_eccoob_16;
+ }
+
+ host->pagesize_2k = 0;
+
+ return err;
+}
+
--
1.6.0.6
^ permalink raw reply related [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-05-19 23:55 ` [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3 Ilya Yanok
@ 2009-05-28 23:06 ` Wolfgang Denk
2009-05-29 6:22 ` Magnus Lilja
0 siblings, 1 reply; 42+ messages in thread
From: Wolfgang Denk @ 2009-05-28 23:06 UTC (permalink / raw)
To: u-boot
Dear Ilya Yanok,
In message <1242777361-6717-5-git-send-email-yanok@emcraft.com> you wrote:
> Driver for NFC NAND controller found on Freescale's MX2 and MX3
> processors. Ported from Linux. Tested only with i.MX27 but should
> works with other MX2 and MX3 processors too.
...
> +static void *mxc_nand_memcpy(void *dest, void *source, size_t size)
> +{
> + uint32_t *s = source, *d = dest;
> +
> + size >>= 2;
> + while (size--)
> + *d++ = *s++;
> + return dest;
> +}
Why do we need this "special" function here? Why cannot we use plain
standard memcpy() instead?
> + if (col < mtd->writesize)
> + p = (uint16_t __iomem *)(host->regs->MAIN_AREA0 + (col >> 1));
> + else
> + p = (uint16_t __iomem *)(host->regs->SPARE_AREA0 +
> + ((col - mtd->writesize) >> 1));
Braces,please.
...
> + if (col < mtd->writesize)
> + p = host->regs->MAIN_AREA0 + (col & ~3);
> + else
> + p = host->regs->SPARE_AREA0 -
> + mtd->writesize + (col & ~3);
Braces, please.
[please check globally, I will not send more of these comments.]
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If all you have is a hammer, everything looks like a nail.
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-05-28 23:06 ` Wolfgang Denk
@ 2009-05-29 6:22 ` Magnus Lilja
2009-05-29 8:40 ` Wolfgang Denk
0 siblings, 1 reply; 42+ messages in thread
From: Magnus Lilja @ 2009-05-29 6:22 UTC (permalink / raw)
To: u-boot
Dear Wolfgang,
2009/5/29 Wolfgang Denk <wd@denx.de>:
> Dear Ilya Yanok,
>
> In message <1242777361-6717-5-git-send-email-yanok@emcraft.com> you wrote:
>> Driver for NFC NAND controller found on Freescale's MX2 and MX3
>> processors. Ported from Linux. Tested only with i.MX27 but should
>> works with other MX2 and MX3 processors too.
>
> ...
>> +static void *mxc_nand_memcpy(void *dest, void *source, size_t size)
>> +{
>> + ? ? uint32_t *s = source, *d = dest;
>> +
>> + ? ? size >>= 2;
>> + ? ? while (size--)
>> + ? ? ? ? ? ? *d++ = *s++;
>> + ? ? return dest;
>> +}
>
> Why do we need this "special" function here? Why cannot we use plain
> standard memcpy() instead?
Because the nand flash controller can only handle 32 bit read/write
operations, any other size will cause an abort (or something like
that).
/Magnus
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-05-29 6:22 ` Magnus Lilja
@ 2009-05-29 8:40 ` Wolfgang Denk
0 siblings, 0 replies; 42+ messages in thread
From: Wolfgang Denk @ 2009-05-29 8:40 UTC (permalink / raw)
To: u-boot
Dear Magnus,
In message <59b21cf20905282322s60c91890w73eeb443c25a0963@mail.gmail.com> you wrote:
>
> >> +static void *mxc_nand_memcpy(void *dest, void *source, size_t size)
> >> +{
> >> + uint32_t *s = source, *d = dest;
> >> +
> >> + size >>= 2;
> >> + while (size--)
> >> + *d++ = *s++;
> >> + return dest;
> >> +}
> >
> > Why do we need this "special" function here? Why cannot we use plain
> > standard memcpy() instead?
>
> Because the nand flash controller can only handle 32 bit read/write
> operations, any other size will cause an abort (or something like
> that).
I see. I would find it helpful if this was mentioned in a comment;
eventually it should also be reflected in the function name. How about
memcpy32() or memcpy_aligned32() or similar?
While we are at alignment - what happens if the parameters "source"
and "dest" are not 32 bit aligned?
Maybe we should even move this function into common code?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If you're not part of the solution, you're part of the problem.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 5/7] mxc-mmc: sdhc host driver for MX2 and MX3 proccessor
2009-05-19 23:55 [U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
` (3 preceding siblings ...)
2009-05-19 23:55 ` [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3 Ilya Yanok
@ 2009-05-19 23:55 ` Ilya Yanok
2009-05-19 23:56 ` [U-Boot] [PATCH 6/7] arm: add support for CONFIG_GENERIC_MMC Ilya Yanok
` (2 subsequent siblings)
7 siblings, 0 replies; 42+ messages in thread
From: Ilya Yanok @ 2009-05-19 23:55 UTC (permalink / raw)
To: u-boot
This is a port of Linux driver for SDHC host controller hardware
found on Freescale's MX2 and MX3 processors. Uses new generic MMC
framework (CONFIG_GENERIC_MMC).
One need to merge with u-boot-mmc tree to get the fixes for this driver
to work correctly.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
cpu/arm926ejs/mx27/generic.c | 16 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/mxcmmc.c | 523 ++++++++++++++++++++++++++++++++++++
include/asm-arm/arch-mx27/mxcmmc.h | 25 ++
4 files changed, 565 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/mxcmmc.c
create mode 100644 include/asm-arm/arch-mx27/mxcmmc.h
diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
index e820d94..12326b6 100644
--- a/cpu/arm926ejs/mx27/generic.c
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -23,6 +23,9 @@
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
+#ifdef CONFIG_MXC_MMC
+#include <asm/arch/mxcmmc.h>
+#endif
/*
* get the system pll clock in Hz
@@ -169,6 +172,19 @@ int cpu_eth_init(bd_t *bis)
#endif
}
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_MXC_MMC
+ return mxc_mmc_init(bis);
+#else
+ return 0;
+#endif
+}
+
void imx_gpio_mode(int gpio_mode)
{
struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1b0af12..6fa04b8 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
COBJS := $(COBJS-y)
diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c
new file mode 100644
index 0000000..95663b4
--- /dev/null
+++ b/drivers/mmc/mxcmmc.c
@@ -0,0 +1,523 @@
+/*
+ * This is a driver for the SDHC controller found in Freescale MX2/MX3
+ * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
+ * Unlike the hardware found on MX1, this hardware just works and does
+ * not need all the quirks found in imxmmc.c, hence the seperate driver.
+ *
+ * Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>
+ * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
+ *
+ * derived from pxamci.c by Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <mmc.h>
+#include <part.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#ifdef CONFIG_MX27
+#include <asm/arch/clock.h>
+#endif
+
+#define DRIVER_NAME "mxc-mmc"
+
+struct mxcmci_regs {
+ u32 MMC_REG_STR_STP_CLK;
+ u32 MMC_REG_STATUS;
+ u32 MMC_REG_CLK_RATE;
+ u32 MMC_REG_CMD_DAT_CONT;
+ u32 MMC_REG_RES_TO;
+ u32 MMC_REG_READ_TO;
+ u32 MMC_REG_BLK_LEN;
+ u32 MMC_REG_NOB;
+ u32 MMC_REG_REV_NO;
+ u32 MMC_REG_INT_CNTR;
+ u32 MMC_REG_CMD;
+ u32 MMC_REG_ARG;
+ u32 pad;
+ u32 MMC_REG_RES_FIFO;
+ u32 MMC_REG_BUFFER_ACCESS;
+};
+
+#define STR_STP_CLK_RESET (1 << 3)
+#define STR_STP_CLK_START_CLK (1 << 1)
+#define STR_STP_CLK_STOP_CLK (1 << 0)
+
+#define STATUS_CARD_INSERTION (1 << 31)
+#define STATUS_CARD_REMOVAL (1 << 30)
+#define STATUS_YBUF_EMPTY (1 << 29)
+#define STATUS_XBUF_EMPTY (1 << 28)
+#define STATUS_YBUF_FULL (1 << 27)
+#define STATUS_XBUF_FULL (1 << 26)
+#define STATUS_BUF_UND_RUN (1 << 25)
+#define STATUS_BUF_OVFL (1 << 24)
+#define STATUS_SDIO_INT_ACTIVE (1 << 14)
+#define STATUS_END_CMD_RESP (1 << 13)
+#define STATUS_WRITE_OP_DONE (1 << 12)
+#define STATUS_DATA_TRANS_DONE (1 << 11)
+#define STATUS_READ_OP_DONE (1 << 11)
+#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
+#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
+#define STATUS_BUF_READ_RDY (1 << 7)
+#define STATUS_BUF_WRITE_RDY (1 << 6)
+#define STATUS_RESP_CRC_ERR (1 << 5)
+#define STATUS_CRC_READ_ERR (1 << 3)
+#define STATUS_CRC_WRITE_ERR (1 << 2)
+#define STATUS_TIME_OUT_RESP (1 << 1)
+#define STATUS_TIME_OUT_READ (1 << 0)
+#define STATUS_ERR_MASK 0x2f
+
+#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
+#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
+#define CMD_DAT_CONT_START_READWAIT (1 << 10)
+#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
+#define CMD_DAT_CONT_INIT (1 << 7)
+#define CMD_DAT_CONT_WRITE (1 << 4)
+#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
+#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
+#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
+#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
+
+#define INT_SDIO_INT_WKP_EN (1 << 18)
+#define INT_CARD_INSERTION_WKP_EN (1 << 17)
+#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
+#define INT_CARD_INSERTION_EN (1 << 15)
+#define INT_CARD_REMOVAL_EN (1 << 14)
+#define INT_SDIO_IRQ_EN (1 << 13)
+#define INT_DAT0_EN (1 << 12)
+#define INT_BUF_READ_EN (1 << 4)
+#define INT_BUF_WRITE_EN (1 << 3)
+#define INT_END_CMD_RES_EN (1 << 2)
+#define INT_WRITE_OP_DONE_EN (1 << 1)
+#define INT_READ_OP_EN (1 << 0)
+
+struct mxcmci_host {
+ struct mmc *mmc;
+ struct mxcmci_regs *base;
+ int irq;
+ int detect_irq;
+ int dma;
+ int do_dma;
+ unsigned int power_mode;
+
+ struct mmc_cmd *cmd;
+ struct mmc_data *data;
+
+ unsigned int dma_nents;
+ unsigned int datasize;
+ unsigned int dma_dir;
+
+ u16 rev_no;
+ unsigned int cmdat;
+
+ int clock;
+};
+
+static struct mxcmci_host mxcmci_host;
+static struct mxcmci_host *host = &mxcmci_host;
+
+static inline int mxcmci_use_dma(struct mxcmci_host *host)
+{
+ return host->do_dma;
+}
+
+static void mxcmci_softreset(struct mxcmci_host *host)
+{
+ int i;
+
+ /* reset sequence */
+ writew(STR_STP_CLK_RESET, &host->base->MMC_REG_STR_STP_CLK);
+ writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
+ &host->base->MMC_REG_STR_STP_CLK);
+
+ for (i = 0; i < 8; i++)
+ writew(STR_STP_CLK_START_CLK, &host->base->MMC_REG_STR_STP_CLK);
+
+ writew(0xff, &host->base->MMC_REG_RES_TO);
+}
+
+static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
+{
+ unsigned int nob = data->blocks;
+ unsigned int blksz = data->blocksize;
+ unsigned int datasize = nob * blksz;
+
+ host->data = data;
+
+ writew(nob, &host->base->MMC_REG_NOB);
+ writew(blksz, &host->base->MMC_REG_BLK_LEN);
+ host->datasize = datasize;
+}
+
+static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd,
+ unsigned int cmdat)
+{
+ if (host->cmd != NULL)
+ printf("mxcmci: error!\n");
+ host->cmd = cmd;
+
+ switch (cmd->resp_type) {
+ case MMC_RSP_R1: /* short CRC, OPCODE */
+ case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
+ cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
+ break;
+ case MMC_RSP_R2: /* long 136 bit + CRC */
+ cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
+ break;
+ case MMC_RSP_R3: /* short */
+ cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
+ break;
+ case MMC_RSP_NONE:
+ break;
+ default:
+ printf("mxcmci: unhandled response type 0x%x\n",
+ cmd->resp_type);
+ return -EINVAL;
+ }
+
+ writew(cmd->cmdidx, &host->base->MMC_REG_CMD);
+ writel(cmd->cmdarg, &host->base->MMC_REG_ARG);
+ writew(cmdat, &host->base->MMC_REG_CMD_DAT_CONT);
+
+ return 0;
+}
+
+static void mxcmci_finish_request(struct mxcmci_host *host,
+ struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ host->cmd = NULL;
+ host->data = NULL;
+}
+
+static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
+{
+ int data_error = 0;
+
+ if (stat & STATUS_ERR_MASK) {
+ printf("request failed. status: 0x%08x\n",
+ stat);
+ if (stat & STATUS_CRC_READ_ERR) {
+ data_error = -EILSEQ;
+ } else if (stat & STATUS_CRC_WRITE_ERR) {
+ u32 err_code = (stat >> 9) & 0x3;
+ if (err_code == 2) /* No CRC response */
+ data_error = TIMEOUT;
+ else
+ data_error = -EILSEQ;
+ } else if (stat & STATUS_TIME_OUT_READ) {
+ data_error = TIMEOUT;
+ } else {
+ data_error = -EIO;
+ }
+ }
+
+ host->data = NULL;
+
+ return data_error;
+}
+
+static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
+{
+ struct mmc_cmd *cmd = host->cmd;
+ int i;
+ u32 a, b, c;
+ u32 *resp = (u32 *)cmd->response;
+
+ if (!cmd)
+ return 0;
+
+ if (stat & STATUS_TIME_OUT_RESP) {
+ printf("CMD TIMEOUT\n");
+ return TIMEOUT;
+ } else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
+ printf("cmd crc error\n");
+ return -EILSEQ;
+ }
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ if (cmd->resp_type & MMC_RSP_136) {
+ for (i = 0; i < 4; i++) {
+ a = readw(&host->base->MMC_REG_RES_FIFO);
+ b = readw(&host->base->MMC_REG_RES_FIFO);
+ resp[i] = a << 16 | b;
+ }
+ } else {
+ a = readw(&host->base->MMC_REG_RES_FIFO);
+ b = readw(&host->base->MMC_REG_RES_FIFO);
+ c = readw(&host->base->MMC_REG_RES_FIFO);
+ resp[0] = a << 24 | b << 8 | c >> 8;
+ }
+ }
+ return 0;
+}
+
+static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
+{
+ u32 stat;
+ unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;
+
+ do {
+ stat = readl(&host->base->MMC_REG_STATUS);
+ if (stat & STATUS_ERR_MASK)
+ return stat;
+ if (timeout < get_ticks())
+ return STATUS_TIME_OUT_READ;
+ if (stat & mask)
+ return 0;
+ } while (1);
+}
+
+static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
+{
+ unsigned int stat;
+ u32 *buf = _buf;
+
+ while (bytes > 3) {
+ stat = mxcmci_poll_status(host,
+ STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
+ if (stat)
+ return stat;
+ *buf++ = readl(&host->base->MMC_REG_BUFFER_ACCESS);
+ bytes -= 4;
+ }
+
+ if (bytes) {
+ u8 *b = (u8 *)buf;
+ u32 tmp;
+
+ stat = mxcmci_poll_status(host,
+ STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
+ if (stat)
+ return stat;
+ tmp = readl(&host->base->MMC_REG_BUFFER_ACCESS);
+ memcpy(b, &tmp, bytes);
+ }
+
+ return 0;
+}
+
+static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes)
+{
+ unsigned int stat;
+ const u32 *buf = _buf;
+
+ while (bytes > 3) {
+ stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
+ if (stat)
+ return stat;
+ writel(*buf++, &host->base->MMC_REG_BUFFER_ACCESS);
+ bytes -= 4;
+ }
+
+ if (bytes) {
+ const u8 *b = (u8 *)buf;
+ u32 tmp;
+
+ stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
+ if (stat)
+ return stat;
+
+ memcpy(&tmp, b, bytes);
+ writel(tmp, &host->base->MMC_REG_BUFFER_ACCESS);
+ }
+
+ stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
+ if (stat)
+ return stat;
+
+ return 0;
+}
+
+static int mxcmci_transfer_data(struct mxcmci_host *host)
+{
+ struct mmc_data *data = host->data;
+ int stat;
+ unsigned long length;
+
+ length = data->blocks * data->blocksize;
+ host->datasize = 0;
+
+ if (data->flags & MMC_DATA_READ) {
+ stat = mxcmci_pull(host, data->dest, length);
+ if (stat)
+ return stat;
+ host->datasize += length;
+ } else {
+ stat = mxcmci_push(host, (const void *)(data->src), length);
+ if (stat)
+ return stat;
+ host->datasize += length;
+ stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
+ if (stat)
+ return stat;
+ }
+ return 0;
+}
+
+static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
+{
+ int datastat;
+ int ret;
+
+ ret = mxcmci_read_response(host, stat);
+
+ if (ret) {
+ mxcmci_finish_request(host, host->cmd, host->data);
+ return ret;
+ }
+
+ if (!host->data) {
+ mxcmci_finish_request(host, host->cmd, host->data);
+ return 0;
+ }
+
+ datastat = mxcmci_transfer_data(host);
+ ret = mxcmci_finish_data(host, datastat);
+ mxcmci_finish_request(host, host->cmd, host->data);
+ return ret;
+}
+
+static int mxcmci_request(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mxcmci_host *host = mmc->priv;
+ unsigned int cmdat = host->cmdat;
+ u32 stat;
+ int ret;
+
+ host->cmdat &= ~CMD_DAT_CONT_INIT;
+ if (data) {
+ mxcmci_setup_data(host, data);
+
+ cmdat |= CMD_DAT_CONT_DATA_ENABLE;
+
+ if (data->flags & MMC_DATA_WRITE)
+ cmdat |= CMD_DAT_CONT_WRITE;
+ }
+
+ if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
+ mxcmci_finish_request(host, cmd, data);
+ return ret;
+ }
+
+ do {
+ stat = readl(&host->base->MMC_REG_STATUS);
+ writel(stat, &host->base->MMC_REG_STATUS);
+ } while (!(stat & STATUS_END_CMD_RESP));
+
+ return mxcmci_cmd_done(host, stat);
+}
+
+static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
+{
+ unsigned int divider;
+ int prescaler = 0;
+ unsigned long clk_in = imx_get_perclk2();
+
+ while (prescaler <= 0x800) {
+ for (divider = 1; divider <= 0xF; divider++) {
+ int x;
+
+ x = (clk_in / (divider + 1));
+
+ if (prescaler)
+ x /= (prescaler * 2);
+
+ if (x <= clk_ios)
+ break;
+ }
+ if (divider < 0x10)
+ break;
+
+ if (prescaler == 0)
+ prescaler = 1;
+ else
+ prescaler <<= 1;
+ }
+
+ writew((prescaler << 4) | divider, &host->base->MMC_REG_CLK_RATE);
+}
+
+static void mxcmci_set_ios(struct mmc *mmc)
+{
+ struct mxcmci_host *host = mmc->priv;
+ if (mmc->bus_width == 4)
+ host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
+ else
+ host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
+
+ if (mmc->clock) {
+ mxcmci_set_clk_rate(host, mmc->clock);
+ writew(STR_STP_CLK_START_CLK, &host->base->MMC_REG_STR_STP_CLK);
+ } else {
+ writew(STR_STP_CLK_STOP_CLK, &host->base->MMC_REG_STR_STP_CLK);
+ }
+
+ host->clock = mmc->clock;
+}
+
+static int mxcmci_init(struct mmc *mmc)
+{
+ struct mxcmci_host *host = mmc->priv;
+
+ mxcmci_softreset(host);
+
+ host->rev_no = readw(&host->base->MMC_REG_REV_NO);
+ if (host->rev_no != 0x400) {
+ printf("wrong rev.no. 0x%08x. aborting.\n",
+ host->rev_no);
+ return -ENODEV;
+ }
+
+ /* recommended in data sheet */
+ writew(0x2db4, &host->base->MMC_REG_READ_TO);
+
+ writel(0, &host->base->MMC_REG_INT_CNTR);
+
+ return 0;
+}
+
+static int mxcmci_initialize(bd_t *bis)
+{
+ struct mmc *mmc = NULL;
+
+ mmc = malloc(sizeof(struct mmc));
+
+ if (!mmc)
+ return -ENOMEM;
+
+ sprintf(mmc->name, "MXC MCI");
+ mmc->send_cmd = mxcmci_request;
+ mmc->set_ios = mxcmci_set_ios;
+ mmc->init = mxcmci_init;
+ mmc->host_caps = MMC_MODE_4BIT;
+
+ host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
+ mmc->priv = host;
+ host->mmc = mmc;
+
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->f_min = imx_get_perclk2() >> 7;
+ mmc->f_max = imx_get_perclk2() >> 1;
+
+ mmc_register(mmc);
+
+ return 0;
+}
+
+int mxc_mmc_init(bd_t *bis)
+{
+ return mxcmci_initialize(bis);
+}
+
diff --git a/include/asm-arm/arch-mx27/mxcmmc.h b/include/asm-arm/arch-mx27/mxcmmc.h
new file mode 100644
index 0000000..4c83cc7
--- /dev/null
+++ b/include/asm-arm/arch-mx27/mxcmmc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef ASM_ARCH_MXCMMC_H
+#define ASM_ARCH_MXCMMC_H
+
+int mxc_mmc_init(bd_t *bis);
+
+#endif
--
1.6.0.6
^ permalink raw reply related [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 6/7] arm: add support for CONFIG_GENERIC_MMC
2009-05-19 23:55 [U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
` (4 preceding siblings ...)
2009-05-19 23:55 ` [U-Boot] [PATCH 5/7] mxc-mmc: sdhc host driver for MX2 and MX3 proccessor Ilya Yanok
@ 2009-05-19 23:56 ` Ilya Yanok
2009-05-23 0:27 ` Jean-Christophe PLAGNIOL-VILLARD
2009-05-19 23:56 ` [U-Boot] [PATCH 7/7] imx27lite: add support for imx27lite board from LogicPD Ilya Yanok
2009-05-19 23:58 ` [U-Boot] [PATCH 0/7][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
7 siblings, 1 reply; 42+ messages in thread
From: Ilya Yanok @ 2009-05-19 23:56 UTC (permalink / raw)
To: u-boot
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
lib_arm/board.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/lib_arm/board.c b/lib_arm/board.c
index 5d05d9b..268532f 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -48,6 +48,7 @@
#include <serial.h>
#include <nand.h>
#include <onenand_uboot.h>
+#include <mmc.h>
#ifdef CONFIG_DRIVER_SMC91111
#include "../drivers/net/smc91111.h"
@@ -439,6 +440,12 @@ extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
#ifdef BOARD_LATE_INIT
board_late_init ();
#endif
+
+#ifdef CONFIG_GENERIC_MMC
+ puts ("MMC: ");
+ mmc_initialize (gd->bd);
+#endif
+
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
--
1.6.0.6
^ permalink raw reply related [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 6/7] arm: add support for CONFIG_GENERIC_MMC
2009-05-19 23:56 ` [U-Boot] [PATCH 6/7] arm: add support for CONFIG_GENERIC_MMC Ilya Yanok
@ 2009-05-23 0:27 ` Jean-Christophe PLAGNIOL-VILLARD
2009-05-28 15:56 ` Andy Fleming
0 siblings, 1 reply; 42+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-05-23 0:27 UTC (permalink / raw)
To: u-boot
On 03:56 Wed 20 May , Ilya Yanok wrote:
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---
> lib_arm/board.c | 7 +++++++
> 1 files changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a/lib_arm/board.c b/lib_arm/board.c
> index 5d05d9b..268532f 100644
> --- a/lib_arm/board.c
> +++ b/lib_arm/board.c
> @@ -48,6 +48,7 @@
> #include <serial.h>
> #include <nand.h>
> #include <onenand_uboot.h>
> +#include <mmc.h>
>
> #ifdef CONFIG_DRIVER_SMC91111
> #include "../drivers/net/smc91111.h"
> @@ -439,6 +440,12 @@ extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
> #ifdef BOARD_LATE_INIT
> board_late_init ();
> #endif
> +
> +#ifdef CONFIG_GENERIC_MMC
> + puts ("MMC: ");
> + mmc_initialize (gd->bd);
> +#endif
do you use a embedded mmc?
otherwise I'll prefer to not init the mmc at the board init but on need
Best Regards,
J.
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 6/7] arm: add support for CONFIG_GENERIC_MMC
2009-05-23 0:27 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2009-05-28 15:56 ` Andy Fleming
2009-06-02 23:09 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 1 reply; 42+ messages in thread
From: Andy Fleming @ 2009-05-28 15:56 UTC (permalink / raw)
To: u-boot
On Fri, May 22, 2009 at 7:27 PM, Jean-Christophe PLAGNIOL-VILLARD <
plagnioj@jcrosoft.com> wrote:
> On 03:56 Wed 20 May , Ilya Yanok wrote:
> > Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> > ---
> > lib_arm/board.c | 7 +++++++
> > 1 files changed, 7 insertions(+), 0 deletions(-)
> >
> > diff --git a/lib_arm/board.c b/lib_arm/board.c
> > index 5d05d9b..268532f 100644
> > --- a/lib_arm/board.c
> > +++ b/lib_arm/board.c
> > @@ -48,6 +48,7 @@
> > #include <serial.h>
> > #include <nand.h>
> > #include <onenand_uboot.h>
> > +#include <mmc.h>
> >
> > #ifdef CONFIG_DRIVER_SMC91111
> > #include "../drivers/net/smc91111.h"
> > @@ -439,6 +440,12 @@ extern void davinci_eth_set_mac_addr (const u_int8_t
> *addr);
> > #ifdef BOARD_LATE_INIT
> > board_late_init ();
> > #endif
> > +
> > +#ifdef CONFIG_GENERIC_MMC
> > + puts ("MMC: ");
> > + mmc_initialize (gd->bd);
> > +#endif
> do you use a embedded mmc?
> otherwise I'll prefer to not init the mmc at the board init but on need
This is the same way ethernet is initialized. mmc_initialize should not
perform any SD/MMC transactions, but should set up the driver, and register
with the MMC subsystem. Without doing this, there's no way to address the
MMC device from the command line...
Andy
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 6/7] arm: add support for CONFIG_GENERIC_MMC
2009-05-28 15:56 ` Andy Fleming
@ 2009-06-02 23:09 ` Jean-Christophe PLAGNIOL-VILLARD
0 siblings, 0 replies; 42+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-06-02 23:09 UTC (permalink / raw)
To: u-boot
On 10:56 Thu 28 May , Andy Fleming wrote:
> On Fri, May 22, 2009 at 7:27 PM, Jean-Christophe PLAGNIOL-VILLARD
> <plagnioj@jcrosoft.com> wrote:
>
> On 03:56 Wed 20 May , Ilya Yanok wrote:
> > Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> > ---
> > lib_arm/board.c | 7 +++++++
> > 1 files changed, 7 insertions(+), 0 deletions(-)
> >
> > diff --git a/lib_arm/board.c b/lib_arm/board.c
> > index 5d05d9b..268532f 100644
> > --- a/lib_arm/board.c
> > +++ b/lib_arm/board.c
> > @@ -48,6 +48,7 @@
> > #include <serial.h>
> > #include <nand.h>
> > #include <onenand_uboot.h>
> > +#include <mmc.h>
> >
> > #ifdef CONFIG_DRIVER_SMC91111
> > #include "../drivers/net/smc91111.h"
> > @@ -439,6 +440,12 @@ extern void davinci_eth_set_mac_addr (const
> u_int8_t *addr);
> > #ifdef BOARD_LATE_INIT
> > board_late_init ();
> > #endif
> > +
> > +#ifdef CONFIG_GENERIC_MMC
> > + puts ("MMC: ");
> > + mmc_initialize (gd->bd);
> > +#endif
> do you use a embedded mmc?
> otherwise I'll prefer to not init the mmc at the board init but on need
>
> This is the same way ethernet is initialized. mmc_initialize should not
> perform any SD/MMC transactions, but should set up the driver, and
> register with the MMC subsystem. Without doing this, there's no way to
> address the MMC device from the command line...
ok
Best Regards,
J.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 7/7] imx27lite: add support for imx27lite board from LogicPD
2009-05-19 23:55 [U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
` (5 preceding siblings ...)
2009-05-19 23:56 ` [U-Boot] [PATCH 6/7] arm: add support for CONFIG_GENERIC_MMC Ilya Yanok
@ 2009-05-19 23:56 ` Ilya Yanok
2009-05-28 22:27 ` Wolfgang Denk
2009-05-19 23:58 ` [U-Boot] [PATCH 0/7][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
7 siblings, 1 reply; 42+ messages in thread
From: Ilya Yanok @ 2009-05-19 23:56 UTC (permalink / raw)
To: u-boot
This patch adds support for i.MX27-LITEKIT development board from
LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
flash, FEC ethernet controller integrated into i.MX27.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
MAKEALL | 1 +
Makefile | 3 +
board/logicpd/imx27lite/Makefile | 51 +++++++
board/logicpd/imx27lite/config.mk | 1 +
board/logicpd/imx27lite/imx27lite.c | 97 +++++++++++++
board/logicpd/imx27lite/lowlevel_init.S | 223 +++++++++++++++++++++++++++++++
board/logicpd/imx27lite/u-boot.lds | 56 ++++++++
include/configs/imx27lite.h | 193 ++++++++++++++++++++++++++
8 files changed, 625 insertions(+), 0 deletions(-)
create mode 100644 board/logicpd/imx27lite/Makefile
create mode 100644 board/logicpd/imx27lite/config.mk
create mode 100644 board/logicpd/imx27lite/imx27lite.c
create mode 100644 board/logicpd/imx27lite/lowlevel_init.S
create mode 100644 board/logicpd/imx27lite/u-boot.lds
create mode 100644 include/configs/imx27lite.h
diff --git a/MAKEALL b/MAKEALL
index 57dd425..2aaec13 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -504,6 +504,7 @@ LIST_ARM9=" \
cp926ejs \
cp946es \
cp966 \
+ imx27lite \
lpd7a400 \
mx1ads \
mx1fs2 \
diff --git a/Makefile b/Makefile
index 24e6410..cd02a36 100644
--- a/Makefile
+++ b/Makefile
@@ -2790,6 +2790,9 @@ davinci_sffsdr_config : unconfig
davinci_sonata_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
+imx27lite_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
+
lpd7a400_config \
lpd7a404_config: unconfig
@$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x
diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile
new file mode 100644
index 0000000..c404cef
--- /dev/null
+++ b/board/logicpd/imx27lite/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := imx27lite.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
diff --git a/board/logicpd/imx27lite/config.mk b/board/logicpd/imx27lite/config.mk
new file mode 100644
index 0000000..a2e7768
--- /dev/null
+++ b/board/logicpd/imx27lite/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xA7F00000
diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c
new file mode 100644
index 0000000..7c2658c
--- /dev/null
+++ b/board/logicpd/imx27lite/imx27lite.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int imx27lite_devices_init(void)
+{
+ int i;
+ unsigned int mode[] = {
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC | GPIO_PUEN,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_CLR,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mode); i++)
+ imx_gpio_mode(mode[i]);
+
+ return 0;
+}
+
+int board_init (void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ imx27lite_devices_init();
+
+ return 0;
+}
+
+int dram_init (void)
+{
+
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 1 )
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("LogicPD imx27lite\n");
+ return 0;
+}
diff --git a/board/logicpd/imx27lite/lowlevel_init.S b/board/logicpd/imx27lite/lowlevel_init.S
new file mode 100644
index 0000000..ba02ad4
--- /dev/null
+++ b/board/logicpd/imx27lite/lowlevel_init.S
@@ -0,0 +1,223 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
+ * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+#define SDRAM_ESDCFG_REGISTER_VAL(cas) \
+ (ESDCFG_TRC(10) | \
+ ESDCFG_TRCD(3) | \
+ ESDCFG_TCAS(cas) | \
+ ESDCFG_TRRD(1) | \
+ ESDCFG_TRAS(5) | \
+ ESDCFG_TWR | \
+ ESDCFG_TMRD(2) | \
+ ESDCFG_TRP(2) | \
+ ESDCFG_TXP(3))
+
+#define SDRAM_ESDCTL_REGISTER_VAL \
+ (ESDCTL_PRCT(0) | \
+ ESDCTL_BL | \
+ ESDCTL_PWDT(0) | \
+ ESDCTL_SREFR(3) | \
+ ESDCTL_DSIZ_32 | \
+ ESDCTL_COL10 | \
+ ESDCTL_ROW13 | \
+ ESDCTL_SDE)
+
+#define SDRAM_ALL_VAL 0xf00
+
+#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
+#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
+
+#define MPCTL0_VAL 0x1ef15d5
+
+#define SPCTL0_VAL 0x043a1c09
+
+#define CSCR_VAL 0x33f08107
+
+#define PCDR0_VAL 0x120470c3
+#define PCDR1_VAL 0x03030303
+#define PCCR0_VAL 0xffffffff
+#define PCCR1_VAL 0xfffffffc
+
+#define AIPI1_PSR0_VAL 0x20040304
+#define AIPI1_PSR1_VAL 0xdffbfcfb
+#define AIPI2_PSR0_VAL 0x07ffc200
+#define AIPI2_PSR1_VAL 0xffffffff
+
+#define writel(reg, val) \
+ ldr r0, =reg; \
+ ldr r1, =val; \
+ str r1, [r0];
+
+SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
+SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
+SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
+SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
+SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
+ ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
+ ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
+ ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
+
+ .macro init_aipi
+ /*
+ * setup AIPI1 and AIPI2
+ */
+ writel(AIPI1_PSR0, AIPI1_PSR0_VAL)
+ writel(AIPI1_PSR1, AIPI1_PSR1_VAL)
+ writel(AIPI2_PSR0, AIPI2_PSR0_VAL)
+ writel(AIPI2_PSR1, AIPI2_PSR1_VAL)
+
+ .endm /* init_aipi */
+
+ .macro init_clock
+ ldr r0, =CSCR
+ /* disable MPLL/SPLL first */
+ ldr r1, [r0]
+ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
+ str r1, [r0]
+
+ writel(MPCTL0, MPCTL0_VAL)
+ writel(SPCTL0, SPCTL0_VAL)
+
+ writel(CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
+
+ /*
+ * add some delay here
+ */
+ mov r1, #0x1000
+1: subs r1, r1, #0x1
+ bne 1b
+
+ /* peripheral clock divider */
+ writel(PCDR0, PCDR0_VAL)
+ writel(PCDR1, PCDR1_VAL)
+
+ /* Configure PCCR0 and PCCR1 */
+ writel(PCCR0, PCCR0_VAL)
+ writel(PCCR1, PCCR1_VAL)
+
+ .endm /* init_clock */
+
+ .macro sdram_init
+ ldr r0, SOC_ESDCTL_BASE_W
+ mov r2, #PHYS_SDRAM_1
+
+ /* Do initial reset */
+ mov r1, #ESDMISC_MDDR_DL_RST
+ str r1, [r0, #ESDMISC_ROF]
+
+ /* Hold for more than 200ns */
+ ldr r1, =0x10000
+1:
+ subs r1, r1, #0x1
+ bne 1b
+
+ /* Activate LPDDR iface */
+ mov r1, #ESDMISC_MDDREN
+ str r1, [r0, #ESDMISC_ROF]
+
+ /* Check The chip version TO1 or TO2 */
+ ldr r1, SOC_SI_ID_REG_W
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+ /* add Latency on CAS only for TO2 */
+ ldreq r1, SDRAM_ESDCFG_T2_W
+ ldrne r1, SDRAM_ESDCFG_T1_W
+ str r1, [r0, #ESDCFG0_ROF]
+
+ /* Run initialization sequence */
+ ldr r1, SDRAM_PRECHARGE_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_AUTOREF_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_LOADMODE_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+ ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+ add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r1, [r3]
+
+ ldr r1, SDRAM_NORMAL_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+
+#if (CONFIG_NR_DRAM_BANKS > 1)
+ /* 2nd sdram */
+ mov r2, #PHYS_SDRAM_2
+
+ /* Check The chip version TO1 or TO2 */
+ ldr r1, SOC_SI_ID_REG_W
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+ /* add Latency on CAS only for TO2 */
+ ldreq r1, SDRAM_ESDCFG_T2_W
+ ldrne r1, SDRAM_ESDCFG_T1_W
+ str r1, [r0, #ESDCFG1_ROF]
+
+ /* Run initialization sequence */
+ ldr r1, SDRAM_PRECHARGE_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_AUTOREF_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_LOADMODE_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+ ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+ add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r1, [r3]
+
+ ldr r1, SDRAM_NORMAL_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+#endif /* CONFIG_NR_DRAM_BANKS > 1 */
+
+ .endm /* sdram_init */
+
+ .globl board_init_lowlevel
+ board_init_lowlevel:
+ .globl lowlevel_init
+ lowlevel_init:
+
+ mov r10, lr
+
+ init_aipi
+
+ init_clock
+
+ sdram_init
+
+ mov pc,r10
diff --git a/board/logicpd/imx27lite/u-boot.lds b/board/logicpd/imx27lite/u-boot.lds
new file mode 100644
index 0000000..f66f20e
--- /dev/null
+++ b/board/logicpd/imx27lite/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm926ejs/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
+
diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h
new file mode 100644
index 0000000..d71ac4b
--- /dev/null
+++ b/include/configs/imx27lite.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_MX27
+#define CONFIG_IMX27LITE
+#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*=============*/
+/* Memory Info */
+/*=============*/
+/* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024)
+/* reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+/* memtest start address */
+#define CONFIG_SYS_MEMTEST_START 0xA0000000
+#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
+
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX27_UART1
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */
+/* end of flash */
+#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000)
+/* CS2 Base address */
+#define PHYS_FLASH_1 0xc0000000
+/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+/* Flash size 2MB */
+#define PHYS_FLASH_SIZE 0x200000
+#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
+ CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_IMX27
+#define CONFIG_MII
+#define CONFIG_NET_MULTI
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0xd8000000
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
+#define CONFIG_DOS_PARTITION
+
+/*
+ * JFFS2 partitions
+ */
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:256k(U-Boot),-(user),64k(env1)," \
+ "64k(env2);mxc_nand.0:-(nand)"
+
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addmisc=setenv bootargs ${bootargs}\0" \
+ "u-boot=imx27/u-boot.bin\0" \
+ "kernel_addr_r=a0800000\0" \
+ "hostname=imx27\0" \
+ "bootfile=imx27/uImage\0" \
+ "rootpath=/opt/eldk-4.2-arm/arm\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm\0" \
+ "bootcmd=run net_nfs\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};cp.b ${fileaddr} " \
+ xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "upd=run load update\0" \
+
+#endif /* __CONFIG_H */
--
1.6.0.6
^ permalink raw reply related [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 7/7] imx27lite: add support for imx27lite board from LogicPD
2009-05-19 23:56 ` [U-Boot] [PATCH 7/7] imx27lite: add support for imx27lite board from LogicPD Ilya Yanok
@ 2009-05-28 22:27 ` Wolfgang Denk
0 siblings, 0 replies; 42+ messages in thread
From: Wolfgang Denk @ 2009-05-28 22:27 UTC (permalink / raw)
To: u-boot
Dear Ilya,
In message <1242777361-6717-8-git-send-email-yanok@emcraft.com> you wrote:
> This patch adds support for i.MX27-LITEKIT development board from
> LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
> flash, FEC ethernet controller integrated into i.MX27.
>
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---
> MAKEALL | 1 +
> Makefile | 3 +
> board/logicpd/imx27lite/Makefile | 51 +++++++
> board/logicpd/imx27lite/config.mk | 1 +
> board/logicpd/imx27lite/imx27lite.c | 97 +++++++++++++
> board/logicpd/imx27lite/lowlevel_init.S | 223 +++++++++++++++++++++++++++++++
> board/logicpd/imx27lite/u-boot.lds | 56 ++++++++
> include/configs/imx27lite.h | 193 ++++++++++++++++++++++++++
> 8 files changed, 625 insertions(+), 0 deletions(-)
> create mode 100644 board/logicpd/imx27lite/Makefile
> create mode 100644 board/logicpd/imx27lite/config.mk
> create mode 100644 board/logicpd/imx27lite/imx27lite.c
> create mode 100644 board/logicpd/imx27lite/lowlevel_init.S
> create mode 100644 board/logicpd/imx27lite/u-boot.lds
> create mode 100644 include/configs/imx27lite.h
Entry into the MAINTAINERS file missing.
> diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h
> new file mode 100644
> index 0000000..d71ac4b
> --- /dev/null
> +++ b/include/configs/imx27lite.h
...
> +/*
> + * JFFS2 partitions
> + */
These are generic MTD partitions, not restricted to JFFS2.
> +#define CONFIG_CMD_MTDPARTS
> +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
> +#define MTDPARTS_DEFAULT \
> + "mtdparts=physmap-flash.0:256k(U-Boot),-(user),64k(env1)," \
> + "64k(env2);mxc_nand.0:-(nand)"
It seems this has never been tested. I get:
=> mtdparts
mtdparts variable not set, see 'help mtdparts'
no partitions defined
defaults:
mtdids : nor0=physmap-flash.0,nand0=mxc_nand.0
mtdparts: mtdparts=physmap-flash.0:256k(U-Boot),-(user),64k(env1),64k(env2);mxc_nand.0:-(nand)
=> mtdparts default
no partitions allowed after a fill-up partition
Please fix.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The Buddha, the Godhead, resides quite as comfortably in the circuits
of a digital computer or the gears of a cycle transmission as he does
at the top of a mountain or in the petals of a flower.
- R. Pirsig, "Zen and the Art of Motorcycle Maintenance"
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 0/7][v2] Support for LogicPD i.MX27-LITEKIT development board
2009-05-19 23:55 [U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board Ilya Yanok
` (6 preceding siblings ...)
2009-05-19 23:56 ` [U-Boot] [PATCH 7/7] imx27lite: add support for imx27lite board from LogicPD Ilya Yanok
@ 2009-05-19 23:58 ` Ilya Yanok
7 siblings, 0 replies; 42+ messages in thread
From: Ilya Yanok @ 2009-05-19 23:58 UTC (permalink / raw)
To: u-boot
Sorry, guys,
I've copied the wrong subject line. It should be [PATCH 0/7][v2]...
Hope this won't cause misunderstandings...
Regards, Ilya.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-06-08 0:12 [U-Boot] [PATCH 0/7][v3] " Ilya Yanok
@ 2009-06-08 0:12 ` Ilya Yanok
2009-06-20 13:22 ` Jean-Christophe PLAGNIOL-VILLARD
2009-06-22 23:43 ` Scott Wood
0 siblings, 2 replies; 42+ messages in thread
From: Ilya Yanok @ 2009-06-08 0:12 UTC (permalink / raw)
To: u-boot
Driver for NFC NAND controller found on Freescale's MX2 and MX3
processors. Ported from Linux. Tested only with i.MX27 but should
works with other MX2 and MX3 processors too.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/mxc_nand.c | 932 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 933 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/mxc_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 471cd6b..24de947 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
new file mode 100644
index 0000000..dc833a0
--- /dev/null
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -0,0 +1,932 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Sascha Hauer, kernel at pengutronix.de
+ * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#ifdef CONFIG_MX27
+#include <asm/arch/imx-regs.h>
+#endif
+
+#define DRIVER_NAME "mxc_nand"
+
+struct nfc_regs {
+/* NFC RAM BUFFER Main area 0 */
+ uint8_t main_area0[0x200];
+ uint8_t main_area1[0x200];
+ uint8_t main_area2[0x200];
+ uint8_t main_area3[0x200];
+/* SPARE BUFFER Spare area 0 */
+ uint8_t spare_area0[0x10];
+ uint8_t spare_area1[0x10];
+ uint8_t spare_area2[0x10];
+ uint8_t spare_area3[0x10];
+ uint8_t pad[0x5c0];
+/* NFC registers */
+ uint16_t nfc_buf_size;
+ uint16_t reserved;
+ uint16_t nfc_buf_addr;
+ uint16_t nfc_flash_addr;
+ uint16_t nfc_flash_cmd;
+ uint16_t nfc_config;
+ uint16_t nfc_ecc_status_result;
+ uint16_t nfc_rsltmain_area;
+ uint16_t nfc_rsltspare_area;
+ uint16_t nfc_wrprot;
+ uint16_t nfc_unlockstart_blkaddr;
+ uint16_t nfc_unlockend_blkaddr;
+ uint16_t nfc_nf_wrprst;
+ uint16_t nfc_config1;
+ uint16_t nfc_config2;
+};
+
+/*
+ * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
+ * for Command operation
+ */
+#define NFC_CMD 0x1
+
+/*
+ * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
+ * for Address operation
+ */
+#define NFC_ADDR 0x2
+
+/*
+ * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
+ * for Input operation
+ */
+#define NFC_INPUT 0x4
+
+/*
+ * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
+ * for Data Output operation
+ */
+#define NFC_OUTPUT 0x8
+
+/*
+ * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
+ * for Read ID operation
+ */
+#define NFC_ID 0x10
+
+/*
+ * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
+ * for Read Status operation
+ */
+#define NFC_STATUS 0x20
+
+/*
+ * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
+ * Status operation
+ */
+#define NFC_INT 0x8000
+
+#define NFC_SP_EN (1 << 2)
+#define NFC_ECC_EN (1 << 3)
+#define NFC_BIG (1 << 5)
+#define NFC_RST (1 << 6)
+#define NFC_CE (1 << 7)
+#define NFC_ONE_CYCLE (1 << 8)
+
+typedef enum {false, true} bool;
+
+struct mxc_nand_host {
+ struct mtd_info mtd;
+ struct nand_chip *nand;
+
+ struct nfc_regs __iomem *regs;
+ int spare_only;
+ int status_request;
+ int pagesize_2k;
+ int clk_act;
+ uint16_t col_addr;
+};
+
+static struct mxc_nand_host mxc_host;
+static struct mxc_nand_host *host = &mxc_host;
+
+/* Define delays in microsec for NAND device operations */
+#define TROP_US_DELAY 2000
+/* Macros to get byte and bit positions of ECC */
+#define COLPOS(x) ((x) >> 3)
+#define BITPOS(x) ((x) & 0xf)
+
+/* Define single bit Error positions in Main & Spare area */
+#define MAIN_SINGLEBIT_ERROR 0x4
+#define SPARE_SINGLEBIT_ERROR 0x1
+
+/* OOB placement block for use with hardware ecc generation */
+static struct nand_ecclayout nand_hw_eccoob_8 = {
+ .eccbytes = 5,
+ .eccpos = {6, 7, 8, 9, 10},
+ .oobfree = {{0, 5}, {11, 5}, }
+};
+
+static struct nand_ecclayout nand_hw_eccoob_16 = {
+ .eccbytes = 5,
+ .eccpos = {6, 7, 8, 9, 10},
+ .oobfree = {{0, 6}, {12, 4}, }
+};
+
+static void *mxc_nand_memcpy32(void *dest, void *source, size_t size)
+{
+ uint32_t *s = source, *d = dest;
+
+ size >>= 2;
+ while (size--)
+ *d++ = *s++;
+ return dest;
+}
+
+/*
+ * This function polls the NANDFC to wait for the basic operation to
+ * complete by checking the INT bit of config2 register.
+ */
+static void wait_op_done(struct mxc_nand_host *host, int max_retries,
+ uint16_t param)
+{
+ uint32_t tmp;
+
+ while (max_retries-- > 0) {
+ if (readw(&host->regs->nfc_config2) & NFC_INT) {
+ tmp = readw(&host->regs->nfc_config2);
+ tmp &= ~NFC_INT;
+ writew(tmp, &host->regs->nfc_config2);
+ break;
+ }
+ udelay(1);
+ }
+ if (max_retries <= 0) {
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
+ __func__, param);
+ }
+}
+
+/*
+ * This function issues the specified command to the NAND device and
+ * waits for completion.
+ */
+static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
+{
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
+
+ writew(cmd, &host->regs->nfc_flash_cmd);
+ writew(NFC_CMD, &host->regs->nfc_config2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, cmd);
+}
+
+/*
+ * This function sends an address (or partial address) to the
+ * NAND device. The address is used to select the source/destination for
+ * a NAND command.
+ */
+static void send_addr(struct mxc_nand_host *host, uint16_t addr)
+{
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
+
+ writew(addr, &host->regs->nfc_flash_addr);
+ writew(NFC_ADDR, &host->regs->nfc_config2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, addr);
+}
+
+/*
+ * This function requests the NANDFC to initate the transfer
+ * of data currently in the NANDFC RAM buffer to the NAND device.
+ */
+static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
+ int spare_only)
+{
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
+
+ /* NANDFC buffer 0 is used for page read/write */
+ writew(buf_id, &host->regs->nfc_buf_addr);
+
+ /* Configure spare or page+spare access */
+ if (!host->pagesize_2k) {
+ uint16_t config1 = readw(&host->regs->nfc_config1);
+ if (spare_only)
+ config1 |= NFC_SP_EN;
+ else
+ config1 &= ~(NFC_SP_EN);
+ writew(config1, &host->regs->nfc_config1);
+ }
+
+ writew(NFC_INPUT, &host->regs->nfc_config2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, spare_only);
+}
+
+/*
+ * Requests NANDFC to initated the transfer of data from the
+ * NAND device into in the NANDFC ram buffer.
+ */
+static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
+ int spare_only)
+{
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
+
+ /* NANDFC buffer 0 is used for page read/write */
+ writew(buf_id, &host->regs->nfc_buf_addr);
+
+ /* Configure spare or page+spare access */
+ if (!host->pagesize_2k) {
+ uint32_t config1 = readw(&host->regs->nfc_config1);
+ if (spare_only)
+ config1 |= NFC_SP_EN;
+ else
+ config1 &= ~NFC_SP_EN;
+ writew(config1, &host->regs->nfc_config1);
+ }
+
+ writew(NFC_OUTPUT, &host->regs->nfc_config2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, spare_only);
+}
+
+/* Request the NANDFC to perform a read of the NAND device ID. */
+static void send_read_id(struct mxc_nand_host *host)
+{
+ struct nand_chip *this = host->nand;
+ uint16_t tmp;
+
+ /* NANDFC buffer 0 is used for device ID output */
+ writew(0x0, &host->regs->nfc_buf_addr);
+
+ /* Read ID into main buffer */
+ tmp = readw(&host->regs->nfc_config1);
+ tmp &= ~NFC_SP_EN;
+ writew(tmp, &host->regs->nfc_config1);
+
+ writew(NFC_ID, &host->regs->nfc_config2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, 0);
+
+ if (this->options & NAND_BUSWIDTH_16) {
+ void __iomem *main_buf = host->regs->main_area0;
+ /* compress the ID info */
+ writeb(readb(main_buf + 2), main_buf + 1);
+ writeb(readb(main_buf + 4), main_buf + 2);
+ writeb(readb(main_buf + 6), main_buf + 3);
+ writeb(readb(main_buf + 8), main_buf + 4);
+ writeb(readb(main_buf + 10), main_buf + 5);
+ }
+}
+
+/*
+ * This function requests the NANDFC to perform a read of the
+ * NAND device status and returns the current status.
+ */
+static uint16_t get_dev_status(struct mxc_nand_host *host)
+{
+ void __iomem *main_buf = host->regs->main_area1;
+ uint32_t store;
+ uint16_t ret, tmp;
+ /* Issue status request to NAND device */
+
+ /* store the main area1 first word, later do recovery */
+ store = readl(main_buf);
+ /*
+ * NANDFC buffer 1 is used for device status to prevent
+ * corruption of read/write buffer on status requests.
+ */
+ writew(1, &host->regs->nfc_buf_addr);
+
+ /* Read status into main buffer */
+ tmp = readw(&host->regs->nfc_config1);
+ tmp &= ~NFC_SP_EN;
+ writew(tmp, &host->regs->nfc_config1);
+
+ writew(NFC_STATUS, &host->regs->nfc_config2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, TROP_US_DELAY, 0);
+
+ /*
+ * Status is placed in first word of main buffer
+ * get status, then recovery area 1 data
+ */
+ ret = readw(main_buf);
+ writel(store, main_buf);
+
+ return ret;
+}
+
+/* This functions is used by upper layer to checks if device is ready */
+static int mxc_nand_dev_ready(struct mtd_info *mtd)
+{
+ /*
+ * NFC handles R/B internally. Therefore, this function
+ * always returns status as ready.
+ */
+ return 1;
+}
+
+#ifdef CONFIG_MXC_NAND_HWECC
+static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ /*
+ * If HW ECC is enabled, we turn it on during init. There is
+ * no need to enable again here.
+ */
+}
+
+static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
+ u_char *read_ecc, u_char *calc_ecc)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+
+ /*
+ * 1-Bit errors are automatically corrected in HW. No need for
+ * additional correction. 2-Bit errors cannot be corrected by
+ * HW ECC, so we need to return failure
+ */
+ uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
+
+ if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
+ MTDDEBUG(MTD_DEBUG_LEVEL0,
+ "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+ u_char *ecc_code)
+{
+ return 0;
+}
+#endif
+
+static u_char mxc_nand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ uint8_t ret = 0;
+ uint16_t col, rd_word;
+ uint16_t __iomem *main_buf =
+ (uint16_t __iomem *)host->regs->main_area0;
+ uint16_t __iomem *spare_buf =
+ (uint16_t __iomem *)host->regs->spare_area0;
+
+ /* Check for status request */
+ if (host->status_request)
+ return get_dev_status(host) & 0xFF;
+
+ /* Get column for 16-bit access */
+ col = host->col_addr >> 1;
+
+ /* If we are accessing the spare region */
+ if (host->spare_only)
+ rd_word = readw(&spare_buf[col]);
+ else
+ rd_word = readw(&main_buf[col]);
+
+ /* Pick upper/lower byte of word from RAM buffer */
+ if (host->col_addr & 0x1)
+ ret = (rd_word >> 8) & 0xFF;
+ else
+ ret = rd_word & 0xFF;
+
+ /* Update saved column address */
+ host->col_addr++;
+
+ return ret;
+}
+
+static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ uint16_t col, rd_word, ret;
+ uint16_t __iomem *p;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "mxc_nand_read_word(col = %d)\n", host->col_addr);
+
+ col = host->col_addr;
+ /* Adjust saved column address */
+ if (col < mtd->writesize && host->spare_only)
+ col += mtd->writesize;
+
+ if (col < mtd->writesize) {
+ p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
+ } else {
+ p = (uint16_t __iomem *)(host->regs->spare_area0 +
+ ((col - mtd->writesize) >> 1));
+ }
+
+ if (col & 1) {
+ rd_word = readw(p);
+ ret = (rd_word >> 8) & 0xff;
+ rd_word = readw(&p[1]);
+ ret |= (rd_word << 8) & 0xff00;
+
+ } else {
+ ret = readw(p);
+ }
+
+ /* Update saved column address */
+ host->col_addr = col + 2;
+
+ return ret;
+}
+
+/*
+ * Write data of length len to buffer buf. The data to be
+ * written on NAND Flash is first copied to RAMbuffer. After the Data Input
+ * Operation by the NFC, the data is written to NAND Flash
+ */
+static void mxc_nand_write_buf(struct mtd_info *mtd,
+ const u_char *buf, int len)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ int n, col, i = 0;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
+ len);
+
+ col = host->col_addr;
+
+ /* Adjust saved column address */
+ if (col < mtd->writesize && host->spare_only)
+ col += mtd->writesize;
+
+ n = mtd->writesize + mtd->oobsize - col;
+ n = min(len, n);
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
+
+ while (n) {
+ void __iomem *p;
+
+ if (col < mtd->writesize) {
+ p = host->regs->main_area0 + (col & ~3);
+ } else {
+ p = host->regs->spare_area0 -
+ mtd->writesize + (col & ~3);
+ }
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
+ __LINE__, p);
+
+ if (((col | (int)&buf[i]) & 3) || n < 16) {
+ uint32_t data = 0;
+
+ if (col & 3 || n < 4)
+ data = readl(p);
+
+ switch (col & 3) {
+ case 0:
+ if (n) {
+ data = (data & 0xffffff00) |
+ (buf[i++] << 0);
+ n--;
+ col++;
+ }
+ case 1:
+ if (n) {
+ data = (data & 0xffff00ff) |
+ (buf[i++] << 8);
+ n--;
+ col++;
+ }
+ case 2:
+ if (n) {
+ data = (data & 0xff00ffff) |
+ (buf[i++] << 16);
+ n--;
+ col++;
+ }
+ case 3:
+ if (n) {
+ data = (data & 0x00ffffff) |
+ (buf[i++] << 24);
+ n--;
+ col++;
+ }
+ }
+
+ writel(data, p);
+ } else {
+ int m = mtd->writesize - col;
+
+ if (col >= mtd->writesize)
+ m += mtd->oobsize;
+
+ m = min(n, m) & ~3;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
+ __func__, __LINE__, n, m, i, col);
+
+ mxc_nand_memcpy32(p, (void *)&buf[i], m);
+ col += m;
+ i += m;
+ n -= m;
+ }
+ }
+ /* Update saved column address */
+ host->col_addr = col;
+}
+
+/*
+ * Read the data buffer from the NAND Flash. To read the data from NAND
+ * Flash first the data output cycle is initiated by the NFC, which copies
+ * the data to RAMbuffer. This data of length len is then copied to buffer buf.
+ */
+static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ int n, col, i = 0;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
+
+ col = host->col_addr;
+
+ /* Adjust saved column address */
+ if (col < mtd->writesize && host->spare_only)
+ col += mtd->writesize;
+
+ n = mtd->writesize + mtd->oobsize - col;
+ n = min(len, n);
+
+ while (n) {
+ void __iomem *p;
+
+ if (col < mtd->writesize) {
+ p = host->regs->main_area0 + (col & ~3);
+ } else {
+ p = host->regs->spare_area0 -
+ mtd->writesize + (col & ~3);
+ }
+
+ if (((col | (int)&buf[i]) & 3) || n < 16) {
+ uint32_t data;
+
+ data = readl(p);
+ switch (col & 3) {
+ case 0:
+ if (n) {
+ buf[i++] = (uint8_t) (data);
+ n--;
+ col++;
+ }
+ case 1:
+ if (n) {
+ buf[i++] = (uint8_t) (data >> 8);
+ n--;
+ col++;
+ }
+ case 2:
+ if (n) {
+ buf[i++] = (uint8_t) (data >> 16);
+ n--;
+ col++;
+ }
+ case 3:
+ if (n) {
+ buf[i++] = (uint8_t) (data >> 24);
+ n--;
+ col++;
+ }
+ }
+ } else {
+ int m = mtd->writesize - col;
+
+ if (col >= mtd->writesize)
+ m += mtd->oobsize;
+
+ m = min(n, m) & ~3;
+ mxc_nand_memcpy32(&buf[i], p, m);
+
+ col += m;
+ i += m;
+ n -= m;
+ }
+ }
+ /* Update saved column address */
+ host->col_addr = col;
+
+}
+
+/*
+ * Used by the upper layer to verify the data in NAND Flash
+ * with the data in the buf.
+ */
+static int mxc_nand_verify_buf(struct mtd_info *mtd,
+ const u_char *buf, int len)
+{
+ return -EFAULT;
+}
+
+/*
+ * This function is used by upper layer for select and
+ * deselect of the NAND chip
+ */
+static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+
+#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
+ if (chip > 0) {
+ MTDDEBUG(MTD_DEBUG_LEVEL0,
+ "ERROR: Illegal chip select (chip = %d)\n", chip);
+ return;
+ }
+
+ if (chip == -1) {
+ writew(readw(&host->regs->nfc_config1) & ~NFC_CE,
+ &host->regs->nfc_config1);
+ return;
+ }
+
+ writew(readw(&host->regs->nfc_config1) | NFC_CE,
+ &host->regs->nfc_config1);
+#endif
+
+ switch (chip) {
+ case -1:
+ /* TODO: Disable the NFC clock */
+ if (host->clk_act)
+ host->clk_act = 0;
+ break;
+ case 0:
+ /* TODO: Enable the NFC clock */
+ if (!host->clk_act)
+ host->clk_act = 1;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*
+ * Used by the upper layer to write command to NAND Flash for
+ * different operations to be carried out on NAND Flash
+ */
+static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
+ int column, int page_addr)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3,
+ "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
+ command, column, page_addr);
+
+ /* Reset command state information */
+ host->status_request = false;
+
+ /* Command pre-processing step */
+ switch (command) {
+
+ case NAND_CMD_STATUS:
+ host->col_addr = 0;
+ host->status_request = true;
+ break;
+
+ case NAND_CMD_READ0:
+ host->col_addr = column;
+ host->spare_only = false;
+ break;
+
+ case NAND_CMD_READOOB:
+ host->col_addr = column;
+ host->spare_only = true;
+ if (host->pagesize_2k)
+ command = NAND_CMD_READ0; /* only READ0 is valid */
+ break;
+
+ case NAND_CMD_SEQIN:
+ if (column >= mtd->writesize) {
+ /*
+ * FIXME: before send SEQIN command for write OOB,
+ * We must read one page out.
+ * For K9F1GXX has no READ1 command to set current HW
+ * pointer to spare area, we must write the whole page
+ * including OOB together.
+ */
+ if (host->pagesize_2k) {
+ /* call ourself to read a page */
+ mxc_nand_command(mtd, NAND_CMD_READ0, 0,
+ page_addr);
+ }
+
+ host->col_addr = column - mtd->writesize;
+ host->spare_only = true;
+
+ /* Set program pointer to spare region */
+ if (!host->pagesize_2k)
+ send_cmd(host, NAND_CMD_READOOB);
+ } else {
+ host->spare_only = false;
+ host->col_addr = column;
+
+ /* Set program pointer to page start */
+ if (!host->pagesize_2k)
+ send_cmd(host, NAND_CMD_READ0);
+ }
+ break;
+
+ case NAND_CMD_PAGEPROG:
+ send_prog_page(host, 0, host->spare_only);
+
+ if (host->pagesize_2k) {
+ /* data in 4 areas datas */
+ send_prog_page(host, 1, host->spare_only);
+ send_prog_page(host, 2, host->spare_only);
+ send_prog_page(host, 3, host->spare_only);
+ }
+
+ break;
+ }
+
+ /* Write out the command to the device. */
+ send_cmd(host, command);
+
+ /* Write out column address, if necessary */
+ if (column != -1) {
+ /*
+ * MXC NANDFC can only perform full page+spare or
+ * spare-only read/write. When the upper layers
+ * layers perform a read/write buf operation,
+ * we will used the saved column adress to index into
+ * the full page.
+ */
+ send_addr(host, 0);
+ if (host->pagesize_2k)
+ /* another col addr cycle for 2k page */
+ send_addr(host, 0);
+ }
+
+ /* Write out page address, if necessary */
+ if (page_addr != -1) {
+ /* paddr_0 - p_addr_7 */
+ send_addr(host, (page_addr & 0xff));
+
+ if (host->pagesize_2k) {
+ send_addr(host, (page_addr >> 8) & 0xFF);
+ if (mtd->size >= 0x40000000)
+ send_addr(host, (page_addr >> 16) & 0xff);
+ } else {
+ /* One more address cycle for higher density devices */
+ if (mtd->size >= 0x4000000) {
+ /* paddr_8 - paddr_15 */
+ send_addr(host, (page_addr >> 8) & 0xff);
+ send_addr(host, (page_addr >> 16) & 0xff);
+ } else {
+ /* paddr_8 - paddr_15 */
+ send_addr(host, (page_addr >> 8) & 0xff);
+ }
+ }
+ }
+
+ /* Command post-processing step */
+ switch (command) {
+
+ case NAND_CMD_RESET:
+ break;
+
+ case NAND_CMD_READOOB:
+ case NAND_CMD_READ0:
+ if (host->pagesize_2k) {
+ /* send read confirm command */
+ send_cmd(host, NAND_CMD_READSTART);
+ /* read for each AREA */
+ send_read_page(host, 0, host->spare_only);
+ send_read_page(host, 1, host->spare_only);
+ send_read_page(host, 2, host->spare_only);
+ send_read_page(host, 3, host->spare_only);
+ } else {
+ send_read_page(host, 0, host->spare_only);
+ }
+ break;
+
+ case NAND_CMD_READID:
+ host->col_addr = 0;
+ send_read_id(host);
+ break;
+
+ case NAND_CMD_PAGEPROG:
+ break;
+
+ case NAND_CMD_STATUS:
+ break;
+
+ case NAND_CMD_ERASE2:
+ break;
+ }
+}
+
+int board_nand_init(struct nand_chip *this)
+{
+ struct system_control_regs *sc_regs =
+ (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+ struct mtd_info *mtd;
+ uint16_t tmp;
+ int err = 0;
+
+ /* structures must be linked */
+ mtd = &host->mtd;
+ mtd->priv = this;
+ host->nand = this;
+
+ /* 50 us command delay time */
+ this->chip_delay = 5;
+
+ this->priv = host;
+ this->dev_ready = mxc_nand_dev_ready;
+ this->cmdfunc = mxc_nand_command;
+ this->select_chip = mxc_nand_select_chip;
+ this->read_byte = mxc_nand_read_byte;
+ this->read_word = mxc_nand_read_word;
+ this->write_buf = mxc_nand_write_buf;
+ this->read_buf = mxc_nand_read_buf;
+ this->verify_buf = mxc_nand_verify_buf;
+
+ host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+ host->clk_act = 1;
+
+#ifdef CONFIG_MXC_NAND_HWECC
+ this->ecc.calculate = mxc_nand_calculate_ecc;
+ this->ecc.hwctl = mxc_nand_enable_hwecc;
+ this->ecc.correct = mxc_nand_correct_data;
+ this->ecc.mode = NAND_ECC_HW;
+ this->ecc.size = 512;
+ this->ecc.bytes = 3;
+ this->ecc.layout = &nand_hw_eccoob_8;
+ tmp = readw(&host->regs->nfc_config1);
+ tmp |= NFC_ECC_EN;
+ writew(tmp, &host->regs->nfc_config1);
+#else
+ this->ecc.size = 512;
+ this->ecc.bytes = 3;
+ this->ecc.layout = &nand_hw_eccoob_8;
+ this->ecc.mode = NAND_ECC_SOFT;
+ tmp = readw(&host->regs->nfc_config1);
+ tmp &= ~NFC_ECC_EN;
+ writew(tmp, &host->regs->nfc_config1);
+#endif
+
+ /* Reset NAND */
+ this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+ /*
+ * preset operation
+ * Unlock the internal RAM Buffer
+ */
+ writew(0x2, &host->regs->nfc_config);
+
+ /* Blocks to be unlocked */
+ writew(0x0, &host->regs->nfc_unlockstart_blkaddr);
+ writew(0x4000, &host->regs->nfc_unlockend_blkaddr);
+
+ /* Unlock Block Command for given address range */
+ writew(0x4, &host->regs->nfc_wrprot);
+
+ /* NAND bus width determines access funtions used by upper layer */
+ if (readl(&sc_regs->fmcr) & NF_16BIT_SEL) {
+ this->options |= NAND_BUSWIDTH_16;
+ this->ecc.layout = &nand_hw_eccoob_16;
+ }
+
+ host->pagesize_2k = 0;
+
+ return err;
+}
+
--
1.6.0.6
^ permalink raw reply related [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-06-08 0:12 ` [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3 Ilya Yanok
@ 2009-06-20 13:22 ` Jean-Christophe PLAGNIOL-VILLARD
2009-06-22 23:43 ` Scott Wood
1 sibling, 0 replies; 42+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-06-20 13:22 UTC (permalink / raw)
To: u-boot
On 04:12 Mon 08 Jun , Ilya Yanok wrote:
> Driver for NFC NAND controller found on Freescale's MX2 and MX3
> processors. Ported from Linux. Tested only with i.MX27 but should
> works with other MX2 and MX3 processors too.
>
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/mxc_nand.c | 932 +++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 933 insertions(+), 0 deletions(-)
> create mode 100644 drivers/mtd/nand/mxc_nand.c
Scott could you take a look on it?
Best Regards,
J.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-06-08 0:12 ` [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3 Ilya Yanok
2009-06-20 13:22 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2009-06-22 23:43 ` Scott Wood
2009-06-23 20:03 ` Magnus Lilja
2009-07-17 10:48 ` Ilya Yanok
1 sibling, 2 replies; 42+ messages in thread
From: Scott Wood @ 2009-06-22 23:43 UTC (permalink / raw)
To: u-boot
On Mon, Jun 08, 2009 at 04:12:48AM +0400, Ilya Yanok wrote:
> Driver for NFC NAND controller found on Freescale's MX2 and MX3
> processors. Ported from Linux. Tested only with i.MX27 but should
> works with other MX2 and MX3 processors too.
>
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Please look at drivers/mtd/nand/mpc5121_nfc.c, which AFAICT is very
similar hardware, and see if anything can be factored out into common
code, and try to keep the rest looking the same except where the hardware
actually differs.
> +static struct nand_ecclayout nand_hw_eccoob_16 = {
> + .eccbytes = 5,
> + .eccpos = {6, 7, 8, 9, 10},
> + .oobfree = {{0, 6}, {12, 4}, }
> +};
This implies the bad block marker is one byte at offset 11 (it's all
that's left), but I don't see any override of the bad block pattern.
> +static void *mxc_nand_memcpy32(void *dest, void *source, size_t size)
> +{
> + uint32_t *s = source, *d = dest;
> +
> + size >>= 2;
> + while (size--)
> + *d++ = *s++;
> + return dest;
> +}
This should probably be using I/O accessors (possibly raw) -- and should
take uint32_t *, not void *.
> +/*
> + * This function requests the NANDFC to perform a read of the
> + * NAND device status and returns the current status.
> + */
> +static uint16_t get_dev_status(struct mxc_nand_host *host)
> +{
> + void __iomem *main_buf = host->regs->main_area1;
> + uint32_t store;
> + uint16_t ret, tmp;
> + /* Issue status request to NAND device */
> +
> + /* store the main area1 first word, later do recovery */
> + store = readl(main_buf);
> + /*
> + * NANDFC buffer 1 is used for device status to prevent
> + * corruption of read/write buffer on status requests.
> + */
> + writew(1, &host->regs->nfc_buf_addr);
But it looks like buffer 1 is used for data with large page flash.
Other drivers don't seem to have any problem with status reads clobbering
the buffer...
> +/* This functions is used by upper layer to checks if device is ready */
> +static int mxc_nand_dev_ready(struct mtd_info *mtd)
"This functions is"? I'd say this comment is pretty redundant with respect
to the function name anyway...
> +static u_char mxc_nand_read_byte(struct mtd_info *mtd)
> +{
> + struct nand_chip *nand_chip = mtd->priv;
> + struct mxc_nand_host *host = nand_chip->priv;
> + uint8_t ret = 0;
> + uint16_t col, rd_word;
> + uint16_t __iomem *main_buf =
> + (uint16_t __iomem *)host->regs->main_area0;
> + uint16_t __iomem *spare_buf =
> + (uint16_t __iomem *)host->regs->spare_area0;
According to Magnus Lilja, "the nand flash controller can only handle 32
bit read/write operations, any other size will cause an abort (or
something like that)". But now we're accessing it as 16-bit?
> +static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
> +{
> + struct nand_chip *nand_chip = mtd->priv;
> + struct mxc_nand_host *host = nand_chip->priv;
> + uint16_t col, rd_word, ret;
> + uint16_t __iomem *p;
> +
> + MTDDEBUG(MTD_DEBUG_LEVEL3,
> + "mxc_nand_read_word(col = %d)\n", host->col_addr);
> +
> + col = host->col_addr;
> + /* Adjust saved column address */
> + if (col < mtd->writesize && host->spare_only)
> + col += mtd->writesize;
> +
> + if (col < mtd->writesize) {
> + p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
> + } else {
> + p = (uint16_t __iomem *)(host->regs->spare_area0 +
> + ((col - mtd->writesize) >> 1));
> + }
> +
> + if (col & 1) {
> + rd_word = readw(p);
> + ret = (rd_word >> 8) & 0xff;
> + rd_word = readw(&p[1]);
> + ret |= (rd_word << 8) & 0xff00;
> +
col should never be odd if you're reading words.
> +/*
> + * Write data of length len to buffer buf. The data to be
> + * written on NAND Flash is first copied to RAMbuffer. After the Data Input
> + * Operation by the NFC, the data is written to NAND Flash
> + */
> +static void mxc_nand_write_buf(struct mtd_info *mtd,
> + const u_char *buf, int len)
> +{
> + struct nand_chip *nand_chip = mtd->priv;
> + struct mxc_nand_host *host = nand_chip->priv;
> + int n, col, i = 0;
> +
> + MTDDEBUG(MTD_DEBUG_LEVEL3,
> + "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
> + len);
> +
> + col = host->col_addr;
> +
> + /* Adjust saved column address */
> + if (col < mtd->writesize && host->spare_only)
> + col += mtd->writesize;
> +
> + n = mtd->writesize + mtd->oobsize - col;
> + n = min(len, n);
> +
> + MTDDEBUG(MTD_DEBUG_LEVEL3,
> + "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
> +
> + while (n) {
Safer to do while (n > 0), especially when the code is this complex.
> + void __iomem *p;
> +
> + if (col < mtd->writesize) {
> + p = host->regs->main_area0 + (col & ~3);
> + } else {
> + p = host->regs->spare_area0 -
> + mtd->writesize + (col & ~3);
> + }
> +
> + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
> + __LINE__, p);
> +
> + if (((col | (int)&buf[i]) & 3) || n < 16) {
Do not cast pointers to "int". Use "uintptr_t" or "unsigned long" if you
must.
Why < 16 and not < 4?
> + uint32_t data = 0;
> +
> + if (col & 3 || n < 4)
> + data = readl(p);
If that condition doesn't hold, the data we use is zero?
> +
> + switch (col & 3) {
> + case 0:
> + if (n) {
> + data = (data & 0xffffff00) |
> + (buf[i++] << 0);
> + n--;
> + col++;
> + }
> + case 1:
> + if (n) {
> + data = (data & 0xffff00ff) |
> + (buf[i++] << 8);
> + n--;
> + col++;
> + }
> + case 2:
> + if (n) {
> + data = (data & 0xff00ffff) |
> + (buf[i++] << 16);
> + n--;
> + col++;
> + }
> + case 3:
> + if (n) {
> + data = (data & 0x00ffffff) |
> + (buf[i++] << 24);
> + n--;
> + col++;
> + }
> + }
> + writel(data, p);
Might I suggest this?
union {
uint32_t word;
uint8_t bytes[4];
} nfc_word;
nfc_word.word = readl(p);
nfc_word.bytes[col & 3] = buf[i++];
n--;
col++;
writel(nfc_word.word, p);
As a side benefit, you lose the endian dependency.
> + mxc_nand_memcpy32(p, (void *)&buf[i], m);
Unnecessary cast.
> + /* Update saved column address */
> + host->col_addr = col;
> +
> +}
No blank lines before the brace at the end of a block.
> +
> +/*
> + * Used by the upper layer to verify the data in NAND Flash
> + * with the data in the buf.
> + */
> +static int mxc_nand_verify_buf(struct mtd_info *mtd,
> + const u_char *buf, int len)
> +{
> + return -EFAULT;
> +}
Umm...
> + case NAND_CMD_SEQIN:
> + if (column >= mtd->writesize) {
> + /*
> + * FIXME: before send SEQIN command for write OOB,
> + * We must read one page out.
> + * For K9F1GXX has no READ1 command to set current HW
> + * pointer to spare area, we must write the whole page
> + * including OOB together.
> + */
> + if (host->pagesize_2k) {
> + /* call ourself to read a page */
> + mxc_nand_command(mtd, NAND_CMD_READ0, 0,
> + page_addr);
> + }
Should this be #ifdef HWECC? And update the comment to indicate the
actual problem, which is the unusual hardware ECC implementation. I
don't see what the lack of a "READ1" command has to do with it.
And is this actually a FIXME if it's already being done?
> +#ifdef CONFIG_MXC_NAND_HWECC
> + this->ecc.calculate = mxc_nand_calculate_ecc;
> + this->ecc.hwctl = mxc_nand_enable_hwecc;
> + this->ecc.correct = mxc_nand_correct_data;
> + this->ecc.mode = NAND_ECC_HW;
> + this->ecc.size = 512;
> + this->ecc.bytes = 3;
> + this->ecc.layout = &nand_hw_eccoob_8;
> + tmp = readw(&host->regs->nfc_config1);
> + tmp |= NFC_ECC_EN;
> + writew(tmp, &host->regs->nfc_config1);
> +#else
> + this->ecc.size = 512;
> + this->ecc.bytes = 3;
> + this->ecc.layout = &nand_hw_eccoob_8;
> + this->ecc.mode = NAND_ECC_SOFT;
> + tmp = readw(&host->regs->nfc_config1);
> + tmp &= ~NFC_ECC_EN;
> + writew(tmp, &host->regs->nfc_config1);
> +#endif
Soft ECC only supports 256-byte ECC blocks (anything you set here to the
contrary will just be overwritten), and you'll need a layout that
accommodates that with enough ECC bytes.
Alternatively, you can implement 512-byte soft ECC if you don't want to
waste those 3 extra OOB bytes. :-)
> + host->pagesize_2k = 0;
So large page is currently unsupported?
-Scott
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-06-22 23:43 ` Scott Wood
@ 2009-06-23 20:03 ` Magnus Lilja
2009-07-03 19:03 ` Paul Thomas
2009-07-17 10:48 ` Ilya Yanok
1 sibling, 1 reply; 42+ messages in thread
From: Magnus Lilja @ 2009-06-23 20:03 UTC (permalink / raw)
To: u-boot
Hi
2009/6/23 Scott Wood <scottwood@freescale.com>:
> On Mon, Jun 08, 2009 at 04:12:48AM +0400, Ilya Yanok wrote:
>> Driver for NFC NAND controller found on Freescale's MX2 and MX3
>> processors. Ported from Linux. Tested only with i.MX27 but should
>> works with other MX2 and MX3 processors too.
>>
>> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
>> +static u_char mxc_nand_read_byte(struct mtd_info *mtd)
>> +{
>> + ? ? struct nand_chip *nand_chip = mtd->priv;
>> + ? ? struct mxc_nand_host *host = nand_chip->priv;
>> + ? ? uint8_t ret = 0;
>> + ? ? uint16_t col, rd_word;
>> + ? ? uint16_t __iomem *main_buf =
>> + ? ? ? ? ? ? (uint16_t __iomem *)host->regs->main_area0;
>> + ? ? uint16_t __iomem *spare_buf =
>> + ? ? ? ? ? ? (uint16_t __iomem *)host->regs->spare_area0;
>
> According to Magnus Lilja, "the nand flash controller can only handle 32
> bit read/write operations, any other size will cause an abort (or
> something like that)". ?But now we're accessing it as 16-bit?
I'm not sure if the controller allows 16 bit accesses or not, don't
remember if I've tried that. 8 bit accesses don't work. Also, I don't
know if it's the controller itself that can't cope with 8 bit accesses
or if it's the bus interface to the NFC block in i.MX31.
Regards, Magnus
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-06-23 20:03 ` Magnus Lilja
@ 2009-07-03 19:03 ` Paul Thomas
2009-07-03 19:11 ` Paul Thomas
0 siblings, 1 reply; 42+ messages in thread
From: Paul Thomas @ 2009-07-03 19:03 UTC (permalink / raw)
To: u-boot
Hello,
I'm using the imx27lite-v2 branch for our opensource imx27 board. Right now
I'm trying to get the nand to work. I'm using a Micron 2Gb x8 part (p/n
MT29F2G08ABDHC). When I do "nand info" I get "Device 0: NAND 256MiB 1,8V
8-bit, sector size 128 KiB" which is correct. mtdparts returns:
device nand0 <mxc_nand.0>, # parts = 4
#: name size offset mask_flags
0: IPL-SPL 0x00040000 0x00000000 0
1: kernel 0x00200000 0x00040000 0
2: rootfs 0x00b00000 0x00240000 0
3: userfs 0x0f2c0000 0x00d40000 0
active partition: nand0,0 - (IPL-SPL) 0x00040000 @ 0x00000000
defaults:
mtdids : nor0=physmap-flash.0,nand0=mxc_nand.0
mtdparts: mtdparts=mxc_nand.0:256k(IPL-SPL),2m(kernel),11m(rootfs),-(userfs)
But when I do other commands like fsinfo or ls I get "read_nand_cached:
error reading nand off 0x2000 size 8192 bytes" errors.
My questions are: should the current driver support this chip? Do I need to
do anything else to prepare the mtd partitions? Is there a low level test I
could run on the NAND?
thanks,
Paul
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-07-03 19:03 ` Paul Thomas
@ 2009-07-03 19:11 ` Paul Thomas
0 siblings, 0 replies; 42+ messages in thread
From: Paul Thomas @ 2009-07-03 19:11 UTC (permalink / raw)
To: u-boot
On Fri, Jul 3, 2009 at 12:03 PM, Paul Thomas <pthomas8589@gmail.com> wrote:
> Hello,
>
> I'm using the imx27lite-v2 branch for our opensource imx27 board. Right now
> I'm trying to get the nand to work. I'm using a Micron 2Gb x8 part (p/n
> MT29F2G08ABDHC). When I do "nand info" I get "Device 0: NAND 256MiB 1,8V
> 8-bit, sector size 128 KiB" which is correct. mtdparts returns:
>
> device nand0 <mxc_nand.0>, # parts = 4
> #: name size offset mask_flags
> 0: IPL-SPL 0x00040000 0x00000000 0
> 1: kernel 0x00200000 0x00040000 0
> 2: rootfs 0x00b00000 0x00240000 0
> 3: userfs 0x0f2c0000 0x00d40000 0
>
> active partition: nand0,0 - (IPL-SPL) 0x00040000 @ 0x00000000
>
> defaults:
> mtdids : nor0=physmap-flash.0,nand0=mxc_nand.0
> mtdparts:
> mtdparts=mxc_nand.0:256k(IPL-SPL),2m(kernel),11m(rootfs),-(userfs)
>
>
> But when I do other commands like fsinfo or ls I get "read_nand_cached:
> error reading nand off 0x2000 size 8192 bytes" errors.
>
> My questions are: should the current driver support this chip? Do I need to
> do anything else to prepare the mtd partitions? Is there a low level test I
> could run on the NAND?
>
> thanks,
> Paul
>
Also "nand bad" reports that all the blocks are bad, and if I do "nand
scrub" it says "Erasing at 0xffe0000 -- 100% complete.
OK", but "nand bad" still returns that all the blocks are bad.
thanks,
Paul
^ permalink raw reply [flat|nested] 42+ messages in thread
* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-06-22 23:43 ` Scott Wood
2009-06-23 20:03 ` Magnus Lilja
@ 2009-07-17 10:48 ` Ilya Yanok
2009-07-17 16:00 ` Scott Wood
1 sibling, 1 reply; 42+ messages in thread
From: Ilya Yanok @ 2009-07-17 10:48 UTC (permalink / raw)
To: u-boot
Hi Scott,
please review the updated patch (will be posted as a follow-up).
Scott Wood wrote:
> Please look at drivers/mtd/nand/mpc5121_nfc.c, which AFAICT is very
> similar hardware, and see if anything can be factored out into common
> code, and try to keep the rest looking the same except where the hardware
> actually differs.
>
Hmm... For now we just can't spend enough effort for this...
>> +static struct nand_ecclayout nand_hw_eccoob_16 = {
>> + .eccbytes = 5,
>> + .eccpos = {6, 7, 8, 9, 10},
>> + .oobfree = {{0, 6}, {12, 4}, }
>> +};
>>
>
> This implies the bad block marker is one byte at offset 11 (it's all
> that's left), but I don't see any override of the bad block pattern.
>
This is surely a bug. Fixed.
>> +static void *mxc_nand_memcpy32(void *dest, void *source, size_t size)
>> +{
>> + uint32_t *s = source, *d = dest;
>> +
>> + size >>= 2;
>> + while (size--)
>> + *d++ = *s++;
>> + return dest;
>> +}
>>
>
> This should probably be using I/O accessors (possibly raw) -- and should
> take uint32_t *, not void *.
>
Fixed.
>> +/*
>> + * This function requests the NANDFC to perform a read of the
>> + * NAND device status and returns the current status.
>> + */
>> +static uint16_t get_dev_status(struct mxc_nand_host *host)
>> +{
>> + void __iomem *main_buf = host->regs->main_area1;
>> + uint32_t store;
>> + uint16_t ret, tmp;
>> + /* Issue status request to NAND device */
>> +
>> + /* store the main area1 first word, later do recovery */
>> + store = readl(main_buf);
>> + /*
>> + * NANDFC buffer 1 is used for device status to prevent
>> + * corruption of read/write buffer on status requests.
>> + */
>> + writew(1, &host->regs->nfc_buf_addr);
>>
>
> But it looks like buffer 1 is used for data with large page flash.
>
Well, we save first word of the buffer and then recover it.
> Other drivers don't seem to have any problem with status reads clobbering
> the buffer...
>
>
>> +/* This functions is used by upper layer to checks if device is ready */
>> +static int mxc_nand_dev_ready(struct mtd_info *mtd)
>>
>
> "This functions is"? I'd say this comment is pretty redundant with respect
> to the function name anyway...
>
Fixed.
>> +static u_char mxc_nand_read_byte(struct mtd_info *mtd)
>> +{
>> + struct nand_chip *nand_chip = mtd->priv;
>> + struct mxc_nand_host *host = nand_chip->priv;
>> + uint8_t ret = 0;
>> + uint16_t col, rd_word;
>> + uint16_t __iomem *main_buf =
>> + (uint16_t __iomem *)host->regs->main_area0;
>> + uint16_t __iomem *spare_buf =
>> + (uint16_t __iomem *)host->regs->spare_area0;
>>
>
> According to Magnus Lilja, "the nand flash controller can only handle 32
> bit read/write operations, any other size will cause an abort (or
> something like that)". But now we're accessing it as 16-bit?
>
16-bit accesses work quite well. Problem was with 8-bit accesses.
>> +static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
>> +{
>> + struct nand_chip *nand_chip = mtd->priv;
>> + struct mxc_nand_host *host = nand_chip->priv;
>> + uint16_t col, rd_word, ret;
>> + uint16_t __iomem *p;
>> +
>> + MTDDEBUG(MTD_DEBUG_LEVEL3,
>> + "mxc_nand_read_word(col = %d)\n", host->col_addr);
>> +
>> + col = host->col_addr;
>> + /* Adjust saved column address */
>> + if (col < mtd->writesize && host->spare_only)
>> + col += mtd->writesize;
>> +
>> + if (col < mtd->writesize) {
>> + p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
>> + } else {
>> + p = (uint16_t __iomem *)(host->regs->spare_area0 +
>> + ((col - mtd->writesize) >> 1));
>> + }
>> +
>> + if (col & 1) {
>> + rd_word = readw(p);
>> + ret = (rd_word >> 8) & 0xff;
>> + rd_word = readw(&p[1]);
>> + ret |= (rd_word << 8) & 0xff00;
>> +
>>
>
> col should never be odd if you're reading words.
>
It can be odd if previously we've read a byte.
>> +/*
>> + * Write data of length len to buffer buf. The data to be
>> + * written on NAND Flash is first copied to RAMbuffer. After the Data Input
>> + * Operation by the NFC, the data is written to NAND Flash
>> + */
>> +static void mxc_nand_write_buf(struct mtd_info *mtd,
>> + const u_char *buf, int len)
>> +{
>> + struct nand_chip *nand_chip = mtd->priv;
>> + struct mxc_nand_host *host = nand_chip->priv;
>> + int n, col, i = 0;
>> +
>> + MTDDEBUG(MTD_DEBUG_LEVEL3,
>> + "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
>> + len);
>> +
>> + col = host->col_addr;
>> +
>> + /* Adjust saved column address */
>> + if (col < mtd->writesize && host->spare_only)
>> + col += mtd->writesize;
>> +
>> + n = mtd->writesize + mtd->oobsize - col;
>> + n = min(len, n);
>> +
>> + MTDDEBUG(MTD_DEBUG_LEVEL3,
>> + "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
>> +
>> + while (n) {
>>
>
> Safer to do while (n > 0), especially when the code is this complex.
>
Fixed.
>> + void __iomem *p;
>> +
>> + if (col < mtd->writesize) {
>> + p = host->regs->main_area0 + (col & ~3);
>> + } else {
>> + p = host->regs->spare_area0 -
>> + mtd->writesize + (col & ~3);
>> + }
>> +
>> + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
>> + __LINE__, p);
>> +
>> + if (((col | (int)&buf[i]) & 3) || n < 16) {
>>
>
> Do not cast pointers to "int". Use "uintptr_t" or "unsigned long" if you
> must.
>
> Why < 16 and not < 4?
>
Fixed.
>> + uint32_t data = 0;
>> +
>> + if (col & 3 || n < 4)
>> + data = readl(p);
>>
>
> If that condition doesn't hold, the data we use is zero?
>
If that condition doesn't hold we are going to rewrite a whole 32-bit
word so there is no need to read it's old content. But I've changed that
piece of code as you suggested anyway.
>> +
>> + switch (col & 3) {
>> + case 0:
>> + if (n) {
>> + data = (data & 0xffffff00) |
>> + (buf[i++] << 0);
>> + n--;
>> + col++;
>> + }
>> + case 1:
>> + if (n) {
>> + data = (data & 0xffff00ff) |
>> + (buf[i++] << 8);
>> + n--;
>> + col++;
>> + }
>> + case 2:
>> + if (n) {
>> + data = (data & 0xff00ffff) |
>> + (buf[i++] << 16);
>> + n--;
>> + col++;
>> + }
>> + case 3:
>> + if (n) {
>> + data = (data & 0x00ffffff) |
>> + (buf[i++] << 24);
>> + n--;
>> + col++;
>> + }
>> + }
>> + writel(data, p);
>>
>
> Might I suggest this?
>
> union {
> uint32_t word;
> uint8_t bytes[4];
> } nfc_word;
>
> nfc_word.word = readl(p);
> nfc_word.bytes[col & 3] = buf[i++];
> n--;
> col++;
>
> writel(nfc_word.word, p);
>
> As a side benefit, you lose the endian dependency.
>
Thanks! I've used your code.
>> + mxc_nand_memcpy32(p, (void *)&buf[i], m);
>>
>
> Unnecessary cast.
>
Fixed.
>> + /* Update saved column address */
>> + host->col_addr = col;
>> +
>> +}
>>
>
> No blank lines before the brace at the end of a block.
>
Fixed.
>> +
>> +/*
>> + * Used by the upper layer to verify the data in NAND Flash
>> + * with the data in the buf.
>> + */
>> +static int mxc_nand_verify_buf(struct mtd_info *mtd,
>> + const u_char *buf, int len)
>> +{
>> + return -EFAULT;
>> +}
>>
>
> Umm...
>
I've added verify_buf function.
>> + case NAND_CMD_SEQIN:
>> + if (column >= mtd->writesize) {
>> + /*
>> + * FIXME: before send SEQIN command for write OOB,
>> + * We must read one page out.
>> + * For K9F1GXX has no READ1 command to set current HW
>> + * pointer to spare area, we must write the whole page
>> + * including OOB together.
>> + */
>> + if (host->pagesize_2k) {
>> + /* call ourself to read a page */
>> + mxc_nand_command(mtd, NAND_CMD_READ0, 0,
>> + page_addr);
>> + }
>>
>
> Should this be #ifdef HWECC? And update the comment to indicate the
> actual problem, which is the unusual hardware ECC implementation. I
> don't see what the lack of a "READ1" command has to do with it.
>
I've updated the comment.
> And is this actually a FIXME if it's already being done?
>
>
>> +#ifdef CONFIG_MXC_NAND_HWECC
>> + this->ecc.calculate = mxc_nand_calculate_ecc;
>> + this->ecc.hwctl = mxc_nand_enable_hwecc;
>> + this->ecc.correct = mxc_nand_correct_data;
>> + this->ecc.mode = NAND_ECC_HW;
>> + this->ecc.size = 512;
>> + this->ecc.bytes = 3;
>> + this->ecc.layout = &nand_hw_eccoob_8;
>> + tmp = readw(&host->regs->nfc_config1);
>> + tmp |= NFC_ECC_EN;
>> + writew(tmp, &host->regs->nfc_config1);
>> +#else
>> + this->ecc.size = 512;
>> + this->ecc.bytes = 3;
>> + this->ecc.layout = &nand_hw_eccoob_8;
>> + this->ecc.mode = NAND_ECC_SOFT;
>> + tmp = readw(&host->regs->nfc_config1);
>> + tmp &= ~NFC_ECC_EN;
>> + writew(tmp, &host->regs->nfc_config1);
>> +#endif
>>
>
> Soft ECC only supports 256-byte ECC blocks (anything you set here to the
> contrary will just be overwritten), and you'll need a layout that
> accommodates that with enough ECC bytes.
>
> Alternatively, you can implement 512-byte soft ECC if you don't want to
> waste those 3 extra OOB bytes. :-)
>
>
>> + host->pagesize_2k = 0;
>>
>
> So large page is currently unsupported?
>
Linux driver was fixed recently and now it claims to support 2K page
size... I've added all needed fixes but I can understand how this driver
should detect the pagesize... Linux driver calls nand_scan_ident()
itself for this... Do you think I can calls nand_scan_ident() from my
board_nand_init() function?
Regards, Ilya.
^ permalink raw reply [flat|nested] 42+ messages in thread* [U-Boot] [PATCH 4/7] mxc_nand: add nand driver for MX2/MX3
2009-07-17 10:48 ` Ilya Yanok
@ 2009-07-17 16:00 ` Scott Wood
0 siblings, 0 replies; 42+ messages in thread
From: Scott Wood @ 2009-07-17 16:00 UTC (permalink / raw)
To: u-boot
On Fri, Jul 17, 2009 at 02:48:38PM +0400, Ilya Yanok wrote:
> Scott Wood wrote:
> > Please look at drivers/mtd/nand/mpc5121_nfc.c, which AFAICT is very
> > similar hardware, and see if anything can be factored out into common
> > code, and try to keep the rest looking the same except where the hardware
> > actually differs.
> >
>
> Hmm... For now we just can't spend enough effort for this...
Understood -- but I have to grumble about it regardless. :-)
> >> +/*
> >> + * This function requests the NANDFC to perform a read of the
> >> + * NAND device status and returns the current status.
> >> + */
> >> +static uint16_t get_dev_status(struct mxc_nand_host *host)
> >> +{
> >> + void __iomem *main_buf = host->regs->main_area1;
> >> + uint32_t store;
> >> + uint16_t ret, tmp;
> >> + /* Issue status request to NAND device */
> >> +
> >> + /* store the main area1 first word, later do recovery */
> >> + store = readl(main_buf);
> >> + /*
> >> + * NANDFC buffer 1 is used for device status to prevent
> >> + * corruption of read/write buffer on status requests.
> >> + */
> >> + writew(1, &host->regs->nfc_buf_addr);
> >>
> >
> > But it looks like buffer 1 is used for data with large page flash.
> >
>
> Well, we save first word of the buffer and then recover it.
So then there's no longer any special reason to use buffer 1 for status,
and that comment is misleading...
> > Other drivers don't seem to have any problem with status reads clobbering
> > the buffer...
What's different about this hardware in that regard? I'm wondering if
you're being more tolerant than you need to be of status requests coming
in at odd times.
> > According to Magnus Lilja, "the nand flash controller can only handle 32
> > bit read/write operations, any other size will cause an abort (or
> > something like that)". But now we're accessing it as 16-bit?
> >
>
> 16-bit accesses work quite well. Problem was with 8-bit accesses.
OK. But in that case I'd think it would have been simpler to use 16-bit
accesses rather than 32-bit when emulating byte accesses in
read_buf()/write_buf().
> > col should never be odd if you're reading words.
> >
>
> It can be odd if previously we've read a byte.
I don't think that accesses will ever be mixed in that way -- correct me
if I'm wrong.
In fact, I only see one use of read_word, which is to read the bad block
marker.
> >> + host->pagesize_2k = 0;
> >>
> >
> > So large page is currently unsupported?
> >
>
> Linux driver was fixed recently and now it claims to support 2K page
> size... I've added all needed fixes but I can understand how this driver
> should detect the pagesize... Linux driver calls nand_scan_ident()
> itself for this... Do you think I can calls nand_scan_ident() from my
> board_nand_init() function?
No, at the moment you should probably just hard code it in the board
config file. I need to find some time to rework the NAND init mechanism
to be driven more from platform code so that it can split up
nand_scan_ident() and nand_scan_tail().
-Scott
^ permalink raw reply [flat|nested] 42+ messages in thread