[PATCH 0/3 v2] x86: adapt CPU topology detection for AMD Magny-Cours

[PATCH 0/3 v2] x86: adapt CPU topology detection for AMD Magny-Cours

[Andreas Herrmann]

Hi,

Second attempt to fix CPU topology representation for multi-node
processors.

Using topology information from /sys/devices/system/cpu/cpu*/topology
you can identify

 phys_package by physical_package_id
 core         by core_id + physical_package_id

Corresponding sibling information is

  Level        | Set of CPUs
 --------------|---------------
  phys_package | core_siblings
  core         | thread_siblings
  thread       | one CPU

Example:

  cpu19: physical_package_id        : 1
  cpu19: core_id                    : 7
  cpu19: thread_siblings            : 00080000
  cpu19: thread_siblings_list       : 19
  cpu19: core_siblings              : 00fff000
  cpu19: core_siblings_list         : 12-23

I am adding cpu_node_id, cpu_node_siblings, cpu_node_siblings_list
to get the complete hierarchy. Now you can identify

 phys_package by physical_package_id
 cpu_node     by physical_package_id + cpu_node_id
 core         by physical_package_id + cpu_node_id + core_id

In contrast to first patch set I don't change the meaning of
core_siblings. Thus we have following sets of CPUs on a socket

  Level        | Set of CPUs
 --------------|---------------
  phys_package | core_siblings
  cpu_node     | cpu_node_siblings
  core         | thread_siblings
  thread       | one CPU

Example:

  cpu19: physical_package_id        : 1
  cpu19: core_id                    : 1
  cpu19: thread_siblings            : 00080000
  cpu19: thread_siblings_list       : 19
  cpu19: cpu_node_id                : 0
  cpu19: cpu_node_siblings          : 00fc0000
  cpu19: cpu_node_siblings_list     : 18-23
  cpu19: core_siblings              : 00fff000
  cpu19: core_siblings_list         : 12-23

The cpu_node level information is stored in struct cpuinfo_x86.cpu_node_id
and in cpu_node_map. It can be accessed using topology_cpu_node_id(cpu)
and topology_cpu_node_cpumask(cpu).

Note:
 A cpu_node is a functional unit. In case of AMD Magny-Cours it
 contains a number of cores, configuration registers, memory
 controler, ... A cpu_node is _not_ necessarily a NUMA node.

 If you doubt this. Think of node interleaving where strictly speaking
 you have no NUMA but spread memory accesses across all nodes
 (depending on some bits of the memory address).  The NUMA node
 topology is provided via ACPI tables (e.g. SRAT, SLIT). The contents
 of such tables might vary with different BIOS settings - the CPU
 topology is constant.

Patches are against tip/master.
Please apply.


Thanks,
Andreas

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[PATCH 1/3] x86: provide CPU topology information for multi-node processors

[Andreas Herrmann]

This support can be switched off/on using a new config option
MULTI_NODE_CPU. If the option is set the CPU topology information is
extended with cpu_node information. This includes a cpu_node_id,
cpu_node_siblings and cpu_node_siblings_list.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/Kconfig                 |    9 +++++++++
 arch/x86/include/asm/processor.h |    4 ++++
 arch/x86/include/asm/smp.h       |    8 ++++++++
 arch/x86/include/asm/topology.h  |    5 +++++
 arch/x86/kernel/cpu/common.c     |    4 ++++
 arch/x86/kernel/cpu/proc.c       |    3 +++
 arch/x86/kernel/smpboot.c        |   14 ++++++++++++++
 drivers/base/topology.c          |   14 ++++++++++++++
 8 files changed, 61 insertions(+), 0 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index ddc207f..af86631 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -710,6 +710,15 @@ config SCHED_MC
 	  making when dealing with multi-core CPU chips at a cost of slightly
 	  increased overhead in some places. If unsure say N here.
 
+config MULTI_NODE_CPU
+	def_bool y
+	prompt "Multi-node processor support"
+	depends on SMP
+	---help---
+	  Multi-node processor support allows proper representation of
+	  CPU topology for processors having multiple-nodes per socket.
+	  If unsure say N here.
+
 source "kernel/Kconfig.preempt"
 
 config X86_UP_APIC
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index c776826..7a791b7 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -106,6 +106,10 @@ struct cpuinfo_x86 {
 	u16			booted_cores;
 	/* Physical processor id: */
 	u16			phys_proc_id;
+#ifdef CONFIG_MULTI_NODE_CPU
+	/* Node id in case of multi-node processor: */
+	u16			cpu_node_id;
+#endif
 	/* Core id: */
 	u16			cpu_core_id;
 	/* Index into per_cpu list: */
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index 6a84ed1..03f9d85 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -31,6 +31,14 @@ static inline struct cpumask *cpu_sibling_mask(int cpu)
 	return per_cpu(cpu_sibling_map, cpu);
 }
 
+#ifdef CONFIG_MULTI_NODE_CPU
+DECLARE_PER_CPU(cpumask_var_t, cpu_node_map);
+static inline struct cpumask *cpu_node_mask(int cpu)
+{
+	return per_cpu(cpu_node_map, cpu);
+}
+#endif
+
 static inline struct cpumask *cpu_core_mask(int cpu)
 {
 	return per_cpu(cpu_core_map, cpu);
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index 066ef59..e04d2a4 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -190,6 +190,11 @@ extern const struct cpumask *cpu_coregroup_mask(int cpu);
 #define topology_core_id(cpu)			(cpu_data(cpu).cpu_core_id)
 #define topology_core_cpumask(cpu)		(per_cpu(cpu_core_map, cpu))
 #define topology_thread_cpumask(cpu)		(per_cpu(cpu_sibling_map, cpu))
+#ifdef CONFIG_MULTI_NODE_CPU
+#define topology_cpu_node_id(cpu)		(cpu_data(cpu).cpu_node_id)
+#define topology_cpu_node_cpumask(cpu)		(per_cpu(cpu_node_map, cpu))
+#define arch_provides_multi_node_cpu_topology	yes
+#endif
 
 /* indicates that pointers to the topology cpumask_t maps are valid */
 #define arch_provides_topology_pointers		yes
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 3ffdcfa..d80e05e 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -478,6 +478,10 @@ out:
 	if ((c->x86_max_cores * smp_num_siblings) > 1) {
 		printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
 		       c->phys_proc_id);
+#ifdef CONFIG_MULTI_NODE_CPU
+		printk(KERN_INFO  "CPU: Processor Node ID: %d\n",
+		       c->cpu_node_id);
+#endif
 		printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
 		       c->cpu_core_id);
 	}
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index d5e3039..ebb34e9 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -15,6 +15,9 @@ static void show_cpuinfo_core(struct seq_file *m, struct cpuinfo_x86 *c,
 		seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
 		seq_printf(m, "siblings\t: %d\n",
 			   cpumask_weight(cpu_core_mask(cpu)));
+#ifdef CONFIG_MULTI_NODE_CPU
+		seq_printf(m, "node id\t\t: %d\n", c->cpu_node_id);
+#endif
 		seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
 		seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
 		seq_printf(m, "apicid\t\t: %d\n", c->apicid);
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index d2e8de9..6041fca 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -108,6 +108,10 @@ EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
 
+/* representing node silbings on multi-node CPU */
+DEFINE_PER_CPU(cpumask_var_t, cpu_node_map);
+EXPORT_PER_CPU_SYMBOL(cpu_node_map);
+
 /* Per CPU bogomips and other parameters */
 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 EXPORT_PER_CPU_SYMBOL(cpu_info);
@@ -401,6 +405,13 @@ void __cpuinit set_cpu_sibling_map(int cpu)
 			cpumask_set_cpu(i, c->llc_shared_map);
 			cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map);
 		}
+#ifdef CONFIG_MULTI_NODE_CPU
+		if ((c->phys_proc_id == cpu_data(i).phys_proc_id) &&
+		    (c->cpu_node_id == cpu_data(i).cpu_node_id)) {
+			cpumask_set_cpu(i, cpu_node_mask(cpu));
+			cpumask_set_cpu(cpu, cpu_node_mask(i));
+		}
+#endif
 		if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
 			cpumask_set_cpu(i, cpu_core_mask(cpu));
 			cpumask_set_cpu(cpu, cpu_core_mask(i));
@@ -1220,6 +1231,9 @@ static void remove_siblinginfo(int cpu)
 	c->phys_proc_id = 0;
 	c->cpu_core_id = 0;
 	cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
+#ifdef CONFIG_MULTI_NODE_CPU
+	c->cpu_node_id = 0;
+#endif
 }
 
 static void __ref remove_cpu_from_maps(int cpu)
diff --git a/drivers/base/topology.c b/drivers/base/topology.c
index bf6b132..9196632 100644
--- a/drivers/base/topology.c
+++ b/drivers/base/topology.c
@@ -114,11 +114,25 @@ define_siblings_show_func(core_cpumask);
 define_one_ro_named(core_siblings, show_core_cpumask);
 define_one_ro_named(core_siblings_list, show_core_cpumask_list);
 
+#ifdef arch_provides_multi_node_cpu_topology
+define_id_show_func(cpu_node_id);
+define_one_ro(cpu_node_id);
+define_siblings_show_func(cpu_node_cpumask);
+define_one_ro_named(cpu_node_siblings, show_cpu_node_cpumask);
+define_one_ro_named(cpu_node_siblings_list, show_cpu_node_cpumask_list);
+#endif
+
+
 static struct attribute *default_attrs[] = {
 	&attr_physical_package_id.attr,
 	&attr_core_id.attr,
 	&attr_thread_siblings.attr,
 	&attr_thread_siblings_list.attr,
+#ifdef arch_provides_multi_node_cpu_topology
+	&attr_cpu_node_id.attr,
+	&attr_cpu_node_siblings.attr,
+	&attr_cpu_node_siblings_list.attr,
+#endif
 	&attr_core_siblings.attr,
 	&attr_core_siblings_list.attr,
 	NULL
-- 
1.6.3.1

[PATCH 2/3] x86: add topology detection for AMD multi-node processors

[Andreas Herrmann]

This adapts CPU topology detection for AMD Magny-Cours.

Here is example output from two cores on same package but different
internal cpu_nodes:

/sys/devices/system/cpu/cpu5:
  physical_package_id        : 0
  core_id                    : 5
  thread_siblings            : 00000020
  thread_siblings_list       : 5
  cpu_node_id                : 0
  cpu_node_siblings          : 0000003f
  cpu_node_siblings_list     : 0-5
  core_siblings              : 00000fff
  core_siblings_list         : 0-11
/sys/devices/system/cpu/cpu6:
  physical_package_id        : 0
  core_id                    : 0
  thread_siblings            : 00000040
  thread_siblings_list       : 6
  cpu_node_id                : 1
  cpu_node_siblings          : 00000fc0
  cpu_node_siblings_list     : 6-11
  core_siblings              : 00000fff
  core_siblings_list         : 0-11

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 arch/x86/kernel/cpu/amd.c         |   63 +++++++++++++++++++++++++++++++++++++
 2 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 13cc6a5..7abe596 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -94,6 +94,7 @@
 #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_NONSTOP_TSC	(3*32+24) /* TSC does not stop in C states */
 #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
+#define X86_FEATURE_AMD_DCM     (3*32+26) /* multi-node processor */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 728b375..53ac4b5 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -6,6 +6,7 @@
 #include <asm/processor.h>
 #include <asm/apic.h>
 #include <asm/cpu.h>
+#include <asm/pci-direct.h>
 
 #ifdef CONFIG_X86_64
 # include <asm/numa_64.h>
@@ -250,6 +251,58 @@ static int __cpuinit nearby_node(int apicid)
 #endif
 
 /*
+ * Fixup core topology information for AMD multi-node processors.
+ * Assumption 1: Number of cores in each internal node is the same.
+ * Assumption 2: Mixed systems with both single-node and dual-node
+ *               processors are not supported.
+ */
+static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_MULTI_NODE_CPU
+	u32 t, cpn;
+	u8 n;
+
+	/* fixup topology information only once for a core */
+	if (cpu_has(c, X86_FEATURE_AMD_DCM))
+		return;
+
+	/* check for multi-node processor on boot cpu */
+	t = read_pci_config(0, 24, 3, 0xe8);
+	if (!(t & (1 << 29)))
+		return;
+
+	set_cpu_cap(c, X86_FEATURE_AMD_DCM);
+
+	/* cores per node: each internal node has half the number of cores */
+	cpn = c->x86_max_cores >> 1;
+
+	/* even-numbered NB_id of this dual-node processor */
+	n = c->phys_proc_id << 1;
+
+	/*
+	 * determine internal node id and assign cores fifty-fifty to
+	 * each node of the dual-node processor
+	 */
+	t = read_pci_config(0, 24 + n, 3, 0xe8);
+	n = (t>>30) & 0x3;
+	if (n == 0) {
+		if (c->cpu_core_id < cpn)
+			c->cpu_node_id = 0;
+		else
+			c->cpu_node_id = 1;
+	} else {
+		if (c->cpu_core_id < cpn)
+			c->cpu_node_id = 1;
+		else
+			c->cpu_node_id = 0;
+	}
+
+	 /* fixup core id to be in range from 0 to cpn */
+	c->cpu_core_id = c->cpu_core_id % cpn;
+#endif
+}
+
+/*
  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
  * Assumes number of cores is a power of two.
  */
@@ -264,6 +317,9 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
 	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
 	/* Convert the initial APIC ID into the socket ID */
 	c->phys_proc_id = c->initial_apicid >> bits;
+	/* fixup topology information on multi-node processors */
+	if ((c->x86 == 0x10) && (c->x86_model == 9))
+		amd_fixup_dcm(c);
 #endif
 }
 
@@ -274,7 +330,14 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 	int node;
 	unsigned apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
 
+#ifdef CONFIG_MULTI_NODE_CPU
+	if (cpu_has(c, X86_FEATURE_AMD_DCM))
+		node = (c->phys_proc_id << 1) + c->cpu_node_id;
+	else
+		node = c->phys_proc_id;
+#else
 	node = c->phys_proc_id;
+#endif
 	if (apicid_to_node[apicid] != NUMA_NO_NODE)
 		node = apicid_to_node[apicid];
 	if (!node_online(node)) {
-- 
1.6.3.1

[PATCH 3/3] x86: cacheinfo: fixup L3 cache information for AMD multi-node processors

[Andreas Herrmann]

L3 cache size, associativity and shared_cpu information need to be
adapted to show information for an internal node instead of the
entire physical package.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |   22 +++++++++++++++++-----
 1 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 789efe2..dbafe2b 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -241,7 +241,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
 	case 0:
 		if (!l1->val)
 			return;
-		assoc = l1->assoc;
+		assoc = assocs[l1->assoc];
 		line_size = l1->line_size;
 		lines_per_tag = l1->lines_per_tag;
 		size_in_kb = l1->size_in_kb;
@@ -249,7 +249,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
 	case 2:
 		if (!l2.val)
 			return;
-		assoc = l2.assoc;
+		assoc = assocs[l2.assoc];
 		line_size = l2.line_size;
 		lines_per_tag = l2.lines_per_tag;
 		/* cpu_data has errata corrections for K7 applied */
@@ -258,10 +258,14 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
 	case 3:
 		if (!l3.val)
 			return;
-		assoc = l3.assoc;
+		assoc = assocs[l3.assoc];
 		line_size = l3.line_size;
 		lines_per_tag = l3.lines_per_tag;
 		size_in_kb = l3.size_encoded * 512;
+		if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
+			size_in_kb = size_in_kb >> 1;
+			assoc = assoc >> 1;
+		}
 		break;
 	default:
 		return;
@@ -278,10 +282,10 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
 	eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
 
 
-	if (assoc == 0xf)
+	if (assoc == 0xffff)
 		eax->split.is_fully_associative = 1;
 	ebx->split.coherency_line_size = line_size - 1;
-	ebx->split.ways_of_associativity = assocs[assoc] - 1;
+	ebx->split.ways_of_associativity = assoc - 1;
 	ebx->split.physical_line_partition = lines_per_tag - 1;
 	ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
 		(ebx->split.ways_of_associativity + 1) - 1;
@@ -598,7 +602,15 @@ static void __cpuinit get_cpu_leaves(void *_retval)
 				cache_remove_shared_cpu_map(cpu, i);
 			break;
 		}
+#ifdef CONFIG_MULTI_NODE_CPU
+		if (boot_cpu_has(X86_FEATURE_AMD_DCM))
+			cpumask_copy(to_cpumask(this_leaf->shared_cpu_map),
+				     topology_cpu_node_cpumask(cpu));
+		else
+			cache_shared_cpu_map_setup(cpu, j);
+#else
 		cache_shared_cpu_map_setup(cpu, j);
+#endif
 	}
 }
 
-- 
1.6.3.1

Re: [PATCH 1/3] x86: provide CPU topology information for multi-node processors

[Bert Wesarg]

On Fri, May 29, 2009 at 20:42, Andreas Herrmann
<andreas.herrmann3@amd.com> wrote:
> This support can be switched off/on using a new config option
> MULTI_NODE_CPU. If the option is set the CPU topology information is
> extended with cpu_node information. This includes a cpu_node_id,
> cpu_node_siblings and cpu_node_siblings_list.
I think this would be a step back after commit
c50cbb05a05cf1f9ca3592272eff053c847727d8. Which exported default
topology information, in case the architecture does not provide these
information.

Regards,
Bert
>
> Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>

Re: [PATCH 1/3] x86: provide CPU topology information for multi-node processors

[Andreas Herrmann]

On Tue, Jun 02, 2009 at 05:05:07PM +0200, Bert Wesarg wrote:
> On Fri, May 29, 2009 at 20:42, Andreas Herrmann
> <andreas.herrmann3@amd.com> wrote:
> > This support can be switched off/on using a new config option
> > MULTI_NODE_CPU. If the option is set the CPU topology information is
> > extended with cpu_node information. This includes a cpu_node_id,
> > cpu_node_siblings and cpu_node_siblings_list.

> I think this would be a step back after commit
> c50cbb05a05cf1f9ca3592272eff053c847727d8. Which exported default
> topology information, in case the architecture does not provide these
> information.

I am fine with exporting default topology information for all
architectures.

I just wanted to avoid pollution of sysfs with useless information
when this information is not provided on an architecture.

Further thoughts -- e.g. concerning the MULTI_NODE_CPU config option?

If I provide defaults for cpu_node_id, cpu_node_siblings etc. the
config option becomes rather useless and I'll remove it.


Regards,
Andreas

Re: [PATCH 1/3] x86: provide CPU topology information for multi-node processors

[Bert Wesarg]

On Tue, Jun 2, 2009 at 17:58, Andreas Herrmann
<andreas.herrmann3@amd.com> wrote:
> On Tue, Jun 02, 2009 at 05:05:07PM +0200, Bert Wesarg wrote:
>> On Fri, May 29, 2009 at 20:42, Andreas Herrmann
>> <andreas.herrmann3@amd.com> wrote:
>> > This support can be switched off/on using a new config option
>> > MULTI_NODE_CPU. If the option is set the CPU topology information is
>> > extended with cpu_node information. This includes a cpu_node_id,
>> > cpu_node_siblings and cpu_node_siblings_list.
>
>> I think this would be a step back after commit
>> c50cbb05a05cf1f9ca3592272eff053c847727d8. Which exported default
>> topology information, in case the architecture does not provide these
>> information.
>
> I am fine with exporting default topology information for all
> architectures.
>
> I just wanted to avoid pollution of sysfs with useless information
> when this information is not provided on an architecture.
>
> Further thoughts -- e.g. concerning the MULTI_NODE_CPU config option?
>
> If I provide defaults for cpu_node_id, cpu_node_siblings etc. the
> config option becomes rather useless and I'll remove it.
Exactly ;-)

The interface to the exported API should not depend on config options.
Only the kernel version number should indicate, whether the cpu_node
information is available or not.

Thanks,
Bert
>
>
> Regards,
> Andreas
>
>
>