* [PATCH] sh: sh7724 clock framework rewrite
@ 2009-06-02 10:34 Magnus Damm
2009-06-03 5:04 ` Kuninori Morimoto
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Magnus Damm @ 2009-06-02 10:34 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@igel.co.jp>
This patch contains a rewrite of the sh7724 clock
framework code. The new code makes use of the
recently merged div4, div6 and mstp32 helper code.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
Untested due to lack of hardware.
arch/sh/Kconfig | 2
arch/sh/kernel/cpu/sh4a/Makefile | 2
arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 85 --------------
arch/sh/kernel/cpu/sh4a/clock-sh7724.c | 183 ++++++++++++++++++++++++++++++++
4 files changed, 190 insertions(+), 82 deletions(-)
--- 0006/arch/sh/Kconfig
+++ work/arch/sh/Kconfig 2009-06-02 19:01:47.000000000 +0900
@@ -516,7 +516,7 @@ config SH_CLK_CPG
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
- def_bool y if !CPU_SUBTYPE_SH7785 && !CPU_SUBTYPE_SH7723
+ def_bool y if !CPU_SUBTYPE_SH7785 && !CPU_SUBTYPE_SH7723 && !CPU_SUBTYPE_SH7724
config SH_CLK_MD
int "CPU Mode Pin Setting"
--- 0006/arch/sh/kernel/cpu/sh4a/Makefile
+++ work/arch/sh/kernel/cpu/sh4a/Makefile 2009-06-02 19:01:19.000000000 +0900
@@ -27,7 +27,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7786) := cl
clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
--- 0006/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ work/arch/sh/kernel/cpu/sh4a/clock-sh7722.c 2009-06-02 19:21:14.000000000 +0900
@@ -130,11 +130,7 @@ static void adjust_clocks(int originate,
* is quite simple..
*/
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
-#define STCPLL(frqcr) ((((frqcr >> 24) & 0x3f) + 1) * 2)
-#else
#define STCPLL(frqcr) (((frqcr >> 24) & 0x1f) + 1)
-#endif
/*
* Instead of having two separate multipliers/divisors set, like this:
@@ -145,11 +141,7 @@ static void adjust_clocks(int originate,
* I created the divisors2 array, which is used to calculate rate like
* rate = parent * 2 / divisors2[ divisor ];
*/
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
-static int divisors2[] = { 4, 1, 8, 12, 16, 24, 32, 1, 48, 64, 72, 96, 1, 144 };
-#else
static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
-#endif
static unsigned long master_clk_recalc(struct clk *clk)
{
@@ -171,17 +163,10 @@ static unsigned long module_clk_recalc(s
return clk->parent->rate / STCPLL(frqcr);
}
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
-#define MASTERDIVS { 12, 16, 24, 30, 32, 36, 48 }
-#define STCMASK 0x3f
-#define DIVCALC(div) (div/2-1)
-#define FRQCRKICK 0x80000000
-#else
#define MASTERDIVS { 2, 3, 4, 6, 8, 16 }
#define STCMASK 0x1f
#define DIVCALC(div) (div-1)
#define FRQCRKICK 0x00000000
-#endif
static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
{
@@ -557,8 +542,7 @@ static struct clk sh7722_r_clock = {
.rate = 32768,
};
-#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
- !defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7343)
/*
* these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
* methods of clk_ops determine which register they should access by
@@ -575,10 +559,9 @@ static struct clk sh7722_siu_b_clock = {
.arch_flags = SCLKBCR,
.ops = &sh7722_siu_clk_ops,
};
-#endif /* CONFIG_CPU_SUBTYPE_SH7343, SH7724 */
+#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
-#if defined(CONFIG_CPU_SUBTYPE_SH7722) ||\
- defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722)
static struct clk sh7722_irda_clock = {
.name = "irda_clk",
.arch_flags = IrDACLKCR,
@@ -676,61 +659,6 @@ static struct clk sh7722_mstpcr_clocks[]
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
- /* See Datasheet : Overview -> Block Diagram */
- MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
- MSTPCR("ic0", "cpu_clk", 0, 30, 0),
- MSTPCR("oc0", "cpu_clk", 0, 29, 0),
- MSTPCR("rs0", "bus_clk", 0, 28, 0),
- MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
- MSTPCR("l2c0", "sh_clk", 0, 26, 0),
- MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
- MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
- MSTPCR("dmac0", "bus_clk", 0, 21, 0),
- MSTPCR("sh0", "sh_clk", 0, 20, 0),
- MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
- MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
- MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
- MSTPCR("cmt0", "r_clk", 0, 14, 0),
- MSTPCR("rwdt0", "r_clk", 0, 13, 0),
- MSTPCR("dmac1", "bus_clk", 0, 12, 0),
- MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
- MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
- MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
- MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
- MSTPCR("scif3", "bus_clk", 0, 6, 0),
- MSTPCR("scif4", "bus_clk", 0, 5, 0),
- MSTPCR("scif5", "bus_clk", 0, 4, 0),
- MSTPCR("msiof0", "bus_clk", 0, 2, 0),
- MSTPCR("msiof1", "bus_clk", 0, 1, 0),
- MSTPCR("keysc0", "r_clk", 1, 12, 0),
- MSTPCR("rtc0", "r_clk", 1, 11, 0),
- MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
- MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
- MSTPCR("mmc0", "bus_clk", 2, 29, 0),
- MSTPCR("eth0", "bus_clk", 2, 28, 0),
- MSTPCR("atapi0", "bus_clk", 2, 26, 0),
- MSTPCR("tpu0", "bus_clk", 2, 25, 0),
- MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
- MSTPCR("tsif0", "bus_clk", 2, 22, 0),
- MSTPCR("usb1", "bus_clk", 2, 21, 0),
- MSTPCR("usb0", "bus_clk", 2, 20, 0),
- MSTPCR("2dg0", "bus_clk", 2, 19, 0),
- MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
- MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
- MSTPCR("veu1", "bus_clk", 2, 15, CLK_ENABLE_ON_INIT),
- MSTPCR("ceu1", "bus_clk", 2, 13, 0),
- MSTPCR("beu1", "bus_clk", 2, 12, 0),
- MSTPCR("2ddmac0", "sh_clk", 2, 10, 0),
- MSTPCR("spu0", "bus_clk", 2, 9, 0),
- MSTPCR("jpu0", "bus_clk", 2, 6, 0),
- MSTPCR("vou0", "bus_clk", 2, 5, 0),
- MSTPCR("beu0", "bus_clk", 2, 4, 0),
- MSTPCR("ceu0", "bus_clk", 2, 3, 0),
- MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
- MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
- MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
-#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7343)
MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
@@ -802,14 +730,11 @@ static struct clk *sh7722_clocks[] = {
&sh7722_sh_clock,
&sh7722_peripheral_clock,
&sh7722_sdram_clock,
-#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
- !defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7343)
&sh7722_siu_a_clock,
&sh7722_siu_b_clock,
#endif
-/* 7724 should support FSI clock */
-#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
- defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722)
&sh7722_irda_clock,
#endif
&sh7722_video_clock,
--- /dev/null
+++ work/arch/sh/kernel/cpu/sh4a/clock-sh7724.c 2009-06-02 19:18:14.000000000 +0900
@@ -0,0 +1,183 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+ *
+ * SH7724 clock framework support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+
+/* SH7724 registers */
+#define FRQCRA 0xa4150000
+#define FRQCRB 0xa4150004
+#define VCLKCR 0xa4150048
+#define FCLKACR 0xa4150008
+#define FCLKBCR 0xa415000c
+#define IRDACLKCR 0xa4150018
+#define SPUCLKCR 0xa415003c
+#define MSTPCR0 0xa4150030
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+
+/* Fixed 32 KHz root clock for RTC and Power Management purposes */
+static struct clk r_clk = {
+ .name = "rclk",
+ .id = -1,
+ .rate = 32768,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+struct clk extal_clk = {
+ .name = "extal",
+ .id = -1,
+ .rate = 33333333,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+ return clk->parent->rate * (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1);
+}
+
+static struct clk_ops pll_clk_ops = {
+ .recalc = pll_recalc,
+};
+
+static struct clk pll_clk = {
+ .name = "pll_clk",
+ .id = -1,
+ .ops = &pll_clk_ops,
+ .parent = &extal_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+};
+
+struct clk *main_clks[] = {
+ &r_clk,
+ &extal_clk,
+ &pll_clk,
+};
+
+static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
+
+static struct clk_div_mult_table div4_table = {
+ .divisors = divisors,
+ .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
+
+#define DIV4(_str, _reg, _bit, _mask, _flags) \
+ SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+
+struct clk div4_clks[DIV4_NR] = {
+ [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
+ [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
+ [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
+ [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
+ [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
+};
+
+struct clk div6_clks[] = {
+ SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+ SH_CLK_DIV6("fsia_clk", &pll_clk, FCLKACR, 0),
+ SH_CLK_DIV6("fsib_clk", &pll_clk, FCLKBCR, 0),
+ SH_CLK_DIV6("irda_clk", &pll_clk, IRDACLKCR, 0),
+ SH_CLK_DIV6("spu_clk", &pll_clk, SPUCLKCR, 0),
+};
+
+#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
+ SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
+
+static struct clk mstp_clks[] = {
+ MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
+ MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
+ MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
+ MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0),
+ MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
+ MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0),
+ MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
+ MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0),
+ MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
+ MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
+ MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
+ MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
+ MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
+ MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
+ MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
+ MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
+ MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
+ MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
+ MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
+ MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
+ MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
+ MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
+ MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
+ MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
+ MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
+
+ MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0),
+ MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0),
+ MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
+ MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0),
+
+ MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0),
+ MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0),
+ MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0),
+ MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
+ MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
+ MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
+ MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
+ MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1),
+ MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1),
+ MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
+ MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
+ MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1),
+ MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1),
+ MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1),
+ MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1),
+ MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0),
+ MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
+ MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
+ MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
+ MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
+ MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
+ MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
+ MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
+};
+
+int __init arch_clk_init(void)
+{
+ int k, ret = 0;
+
+ for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+ ret = clk_register(main_clks[k]);
+
+ if (!ret)
+ ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+ if (!ret)
+ ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+
+ if (!ret)
+ ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+
+ return ret;
+}
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] sh: sh7724 clock framework rewrite
2009-06-02 10:34 [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
@ 2009-06-03 5:04 ` Kuninori Morimoto
2009-06-03 8:43 ` [PATCH] sh: sh7724 clock framework rewrite V2 Magnus Damm
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Kuninori Morimoto @ 2009-06-03 5:04 UTC (permalink / raw)
To: linux-sh
Dear Magnus
thank you for nice patch.
on new clock-sh7724.c
> +static unsigned long pll_recalc(struct clk *clk)
> +{
> + return clk->parent->rate * (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1);
> +}
sh7724 needs "* 2" here.
please check old clock-sh7722.c
> -#if defined(CONFIG_CPU_SUBTYPE_SH7724)
> -#define STCPLL(frqcr) ((((frqcr >> 24) & 0x3f) + 1) * 2)
> -#else
> #define STCPLL(frqcr) (((frqcr >> 24) & 0x1f) + 1)
> -#endif
If I add "*2" here, It works =).
Best regards
--
Kuninori Morimoto
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] sh: sh7724 clock framework rewrite V2
2009-06-02 10:34 [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
2009-06-03 5:04 ` Kuninori Morimoto
@ 2009-06-03 8:43 ` Magnus Damm
2009-06-04 7:53 ` [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Magnus Damm @ 2009-06-03 8:43 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@igel.co.jp>
This patch contains V2 of the sh7724 clock framework
rewrite. The new code makes use of the recently merged
div4, div6 and mstp32 helper code. Both extal and fll are
supported as input clocks to the pll. The div6 clocks are
fed through a divide-by-3 block.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
Untested. Thanks to Morimoto-san for feedback.
arch/sh/Kconfig | 2
arch/sh/kernel/cpu/sh4a/Makefile | 2
arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 57 --------
arch/sh/kernel/cpu/sh4a/clock-sh7723.c | 222 ++++++++++++++++++++++++++++++++
4 files changed, 225 insertions(+), 58 deletions(-)
--- 0010/arch/sh/Kconfig
+++ work/arch/sh/Kconfig 2009-06-03 17:01:02.000000000 +0900
@@ -516,7 +516,7 @@ config SH_CLK_CPG
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
- def_bool y if !CPU_SUBTYPE_SH7785 && !CPU_SUBTYPE_SH7723
+ def_bool y if !CPU_SUBTYPE_SH7785 && !CPU_SUBTYPE_SH7723 && !CPU_SUBTYPE_SH7724
config SH_CLK_MD
int "CPU Mode Pin Setting"
--- 0010/arch/sh/kernel/cpu/sh4a/Makefile
+++ work/arch/sh/kernel/cpu/sh4a/Makefile 2009-06-03 17:01:02.000000000 +0900
@@ -27,7 +27,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7786) := cl
clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
--- 0010/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ work/arch/sh/kernel/cpu/sh4a/clock-sh7722.c 2009-06-03 17:01:02.000000000 +0900
@@ -130,11 +130,7 @@ static void adjust_clocks(int originate,
* is quite simple..
*/
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
-#define STCPLL(frqcr) ((((frqcr >> 24) & 0x3f) + 1) * 2)
-#else
#define STCPLL(frqcr) (((frqcr >> 24) & 0x1f) + 1)
-#endif
/*
* Instead of having two separate multipliers/divisors set, like this:
@@ -145,11 +141,7 @@ static void adjust_clocks(int originate,
* I created the divisors2 array, which is used to calculate rate like
* rate = parent * 2 / divisors2[ divisor ];
*/
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
-static int divisors2[] = { 4, 1, 8, 12, 16, 24, 32, 1, 48, 64, 72, 96, 1, 144 };
-#else
static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
-#endif
static unsigned long master_clk_recalc(struct clk *clk)
{
@@ -171,17 +163,10 @@ static unsigned long module_clk_recalc(s
return clk->parent->rate / STCPLL(frqcr);
}
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
-#define MASTERDIVS { 12, 16, 24, 30, 32, 36, 48 }
-#define STCMASK 0x3f
-#define DIVCALC(div) (div/2-1)
-#define FRQCRKICK 0x80000000
-#else
#define MASTERDIVS { 2, 3, 4, 6, 8, 16 }
#define STCMASK 0x1f
#define DIVCALC(div) (div-1)
#define FRQCRKICK 0x00000000
-#endif
static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
{
@@ -557,8 +542,7 @@ static struct clk sh7722_r_clock = {
.rate = 32768,
};
-#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
- !defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7343)
/*
* these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
* methods of clk_ops determine which register they should access by
@@ -575,10 +559,9 @@ static struct clk sh7722_siu_b_clock = {
.arch_flags = SCLKBCR,
.ops = &sh7722_siu_clk_ops,
};
-#endif /* CONFIG_CPU_SUBTYPE_SH7343, SH7724 */
+#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
-#if defined(CONFIG_CPU_SUBTYPE_SH7722) ||\
- defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722)
static struct clk sh7722_irda_clock = {
.name = "irda_clk",
.arch_flags = IrDACLKCR,
@@ -676,61 +659,6 @@ static struct clk sh7722_mstpcr_clocks[]
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
- /* See Datasheet : Overview -> Block Diagram */
- MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
- MSTPCR("ic0", "cpu_clk", 0, 30, 0),
- MSTPCR("oc0", "cpu_clk", 0, 29, 0),
- MSTPCR("rs0", "bus_clk", 0, 28, 0),
- MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
- MSTPCR("l2c0", "sh_clk", 0, 26, 0),
- MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
- MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
- MSTPCR("dmac0", "bus_clk", 0, 21, 0),
- MSTPCR("sh0", "sh_clk", 0, 20, 0),
- MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
- MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
- MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
- MSTPCR("cmt0", "r_clk", 0, 14, 0),
- MSTPCR("rwdt0", "r_clk", 0, 13, 0),
- MSTPCR("dmac1", "bus_clk", 0, 12, 0),
- MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
- MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
- MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
- MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
- MSTPCR("scif3", "bus_clk", 0, 6, 0),
- MSTPCR("scif4", "bus_clk", 0, 5, 0),
- MSTPCR("scif5", "bus_clk", 0, 4, 0),
- MSTPCR("msiof0", "bus_clk", 0, 2, 0),
- MSTPCR("msiof1", "bus_clk", 0, 1, 0),
- MSTPCR("keysc0", "r_clk", 1, 12, 0),
- MSTPCR("rtc0", "r_clk", 1, 11, 0),
- MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
- MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
- MSTPCR("mmc0", "bus_clk", 2, 29, 0),
- MSTPCR("eth0", "bus_clk", 2, 28, 0),
- MSTPCR("atapi0", "bus_clk", 2, 26, 0),
- MSTPCR("tpu0", "bus_clk", 2, 25, 0),
- MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
- MSTPCR("tsif0", "bus_clk", 2, 22, 0),
- MSTPCR("usb1", "bus_clk", 2, 21, 0),
- MSTPCR("usb0", "bus_clk", 2, 20, 0),
- MSTPCR("2dg0", "bus_clk", 2, 19, 0),
- MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
- MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
- MSTPCR("veu1", "bus_clk", 2, 15, CLK_ENABLE_ON_INIT),
- MSTPCR("ceu1", "bus_clk", 2, 13, 0),
- MSTPCR("beu1", "bus_clk", 2, 12, 0),
- MSTPCR("2ddmac0", "sh_clk", 2, 10, 0),
- MSTPCR("spu0", "bus_clk", 2, 9, 0),
- MSTPCR("jpu0", "bus_clk", 2, 6, 0),
- MSTPCR("vou0", "bus_clk", 2, 5, 0),
- MSTPCR("beu0", "bus_clk", 2, 4, 0),
- MSTPCR("ceu0", "bus_clk", 2, 3, 0),
- MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
- MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
- MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
-#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7343)
MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
@@ -802,14 +730,11 @@ static struct clk *sh7722_clocks[] = {
&sh7722_sh_clock,
&sh7722_peripheral_clock,
&sh7722_sdram_clock,
-#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
- !defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7343)
&sh7722_siu_a_clock,
&sh7722_siu_b_clock,
#endif
-/* 7724 should support FSI clock */
-#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
- defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722)
&sh7722_irda_clock,
#endif
&sh7722_video_clock,
--- /dev/null
+++ work/arch/sh/kernel/cpu/sh4a/clock-sh7724.c 2009-06-03 17:01:02.000000000 +0900
@@ -0,0 +1,242 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+ *
+ * SH7724 clock framework support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+
+/* SH7724 registers */
+#define FRQCRA 0xa4150000
+#define FRQCRB 0xa4150004
+#define VCLKCR 0xa4150048
+#define FCLKACR 0xa4150008
+#define FCLKBCR 0xa415000c
+#define IRDACLKCR 0xa4150018
+#define PLLCR 0xa4150024
+#define MSTPCR0 0xa4150030
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+#define SPUCLKCR 0xa415003c
+#define FLLFRQ 0xa4150050
+#define LSTATS 0xa4150060
+
+/* Fixed 32 KHz root clock for RTC and Power Management purposes */
+static struct clk r_clk = {
+ .name = "rclk",
+ .id = -1,
+ .rate = 32768,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+struct clk extal_clk = {
+ .name = "extal",
+ .id = -1,
+ .rate = 33333333,
+};
+
+/* The fll multiplies the 32khz r_clk, may be used instead of extal */
+static unsigned long fll_recalc(struct clk *clk)
+{
+ unsigned long mult = 0;
+ unsigned long div = 1;
+
+ if (__raw_readl(PLLCR) & 0x1000)
+ mult = __raw_readl(FLLFRQ) & 0x3ff;
+
+ if (__raw_readl(FLLFRQ) & 0x4000)
+ div = 2;
+
+ return (clk->parent->rate * mult) / div;
+}
+
+static struct clk_ops fll_clk_ops = {
+ .recalc = fll_recalc,
+};
+
+static struct clk fll_clk = {
+ .name = "fll_clk",
+ .id = -1,
+ .ops = &fll_clk_ops,
+ .parent = &r_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+ unsigned long mult = 1;
+
+ if (__raw_readl(PLLCR) & 0x4000)
+ mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
+
+ return clk->parent->rate * mult;
+}
+
+static struct clk_ops pll_clk_ops = {
+ .recalc = pll_recalc,
+};
+
+static struct clk pll_clk = {
+ .name = "pll_clk",
+ .id = -1,
+ .ops = &pll_clk_ops,
+ .flags = CLK_ENABLE_ON_INIT,
+};
+
+/* A fixed divide-by-3 block use by the div6 clocks */
+static unsigned long div3_recalc(struct clk *clk)
+{
+ return clk->parent->rate / 3;
+}
+
+static struct clk_ops div3_clk_ops = {
+ .recalc = div3_recalc,
+};
+
+static struct clk div3_clk = {
+ .name = "div3_clk",
+ .id = -1,
+ .ops = &div3_clk_ops,
+ .parent = &pll_clk,
+};
+
+struct clk *main_clks[] = {
+ &r_clk,
+ &extal_clk,
+ &fll_clk,
+ &pll_clk,
+ &div3_clk,
+};
+
+static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
+
+static struct clk_div_mult_table div4_table = {
+ .divisors = divisors,
+ .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
+
+#define DIV4(_str, _reg, _bit, _mask, _flags) \
+ SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+
+struct clk div4_clks[DIV4_NR] = {
+ [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
+ [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
+ [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
+ [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
+ [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
+};
+
+struct clk div6_clks[] = {
+ SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
+ SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
+ SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
+ SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
+ SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
+};
+
+#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
+ SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
+
+static struct clk mstp_clks[] = {
+ MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
+ MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
+ MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
+ MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0),
+ MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
+ MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0),
+ MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
+ MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0),
+ MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
+ MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
+ MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
+ MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
+ MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
+ MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
+ MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
+ MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
+ MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
+ MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
+ MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
+ MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
+ MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
+ MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
+ MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
+ MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
+ MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
+
+ MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0),
+ MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0),
+ MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
+ MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0),
+
+ MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0),
+ MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0),
+ MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0),
+ MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
+ MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
+ MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
+ MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
+ MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1),
+ MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1),
+ MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
+ MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
+ MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1),
+ MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1),
+ MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1),
+ MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1),
+ MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0),
+ MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
+ MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
+ MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
+ MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
+ MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
+ MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
+ MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
+};
+
+int __init arch_clk_init(void)
+{
+ int k, ret = 0;
+
+ /* autodetect extal or fll configuration */
+ if (__raw_readl(PLLCR) & 0x1000)
+ pll_clk.parent = &fll_clk;
+ else
+ pll_clk.parent = &extal_clk;
+
+ for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+ ret = clk_register(main_clks[k]);
+
+ if (!ret)
+ ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+ if (!ret)
+ ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+
+ if (!ret)
+ ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+
+ return ret;
+}
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] sh: sh7724 clock framework rewrite
2009-06-02 10:34 [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
2009-06-03 5:04 ` Kuninori Morimoto
2009-06-03 8:43 ` [PATCH] sh: sh7724 clock framework rewrite V2 Magnus Damm
@ 2009-06-04 7:53 ` Magnus Damm
2009-06-04 8:08 ` Kuninori Morimoto
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Magnus Damm @ 2009-06-04 7:53 UTC (permalink / raw)
To: linux-sh
Hi Morimoto-san,
Thanks for checking the patch!
On Wed, Jun 3, 2009 at 2:04 PM, Kuninori Morimoto
<morimoto.kuninori@renesas.com> wrote:
> on new clock-sh7724.c
>
>> +static unsigned long pll_recalc(struct clk *clk)
>> +{
>> + return clk->parent->rate * (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1);
>> +}
>
> sh7724 needs "* 2" here.
> please check old clock-sh7722.c
Yes, you are correct. Thanks for finding this problem.
I've fixed this in V2 that I posted yesterday. Let me know if you find
any other issues.
Thanks,
/ magnus
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] sh: sh7724 clock framework rewrite
2009-06-02 10:34 [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
` (2 preceding siblings ...)
2009-06-04 7:53 ` [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
@ 2009-06-04 8:08 ` Kuninori Morimoto
2009-06-08 10:03 ` [PATCH] sh: sh7724 clock framework rewrite V2 Kuninori Morimoto
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Kuninori Morimoto @ 2009-06-04 8:08 UTC (permalink / raw)
To: linux-sh
Hi Magnus
> > sh7724 needs "* 2" here.
> > please check old clock-sh7722.c
>
> Yes, you are correct. Thanks for finding this problem.
no problem.
> I've fixed this in V2 that I posted yesterday. Let me know if you find
> any other issues.
OK. I will try this patch next week.
Best regards
--
Kuninori Morimoto
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] sh: sh7724 clock framework rewrite V2
2009-06-02 10:34 [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
` (3 preceding siblings ...)
2009-06-04 8:08 ` Kuninori Morimoto
@ 2009-06-08 10:03 ` Kuninori Morimoto
2009-06-09 8:04 ` Magnus Damm
2009-06-10 11:31 ` [PATCH] sh: sh7724 clock framework rewrite V3 Magnus Damm
6 siblings, 0 replies; 8+ messages in thread
From: Kuninori Morimoto @ 2009-06-08 10:03 UTC (permalink / raw)
To: linux-sh
Hi Magnus
I checked this patch. and it works.
But I found bug
> This patch contains V2 of the sh7724 clock framework
> rewrite. The new code makes use of the recently merged
> div4, div6 and mstp32 helper code. Both extal and fll are
> supported as input clocks to the pll. The div6 clocks are
> fed through a divide-by-3 block.
> - MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
(snip)
> + MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
I wonder your manual is old one.
old manual is very bad, and it say lie sometimes.
correct MSTP010 is "tmu1" here
Best regards
--
Kuninori Morimoto
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] sh: sh7724 clock framework rewrite V2
2009-06-02 10:34 [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
` (4 preceding siblings ...)
2009-06-08 10:03 ` [PATCH] sh: sh7724 clock framework rewrite V2 Kuninori Morimoto
@ 2009-06-09 8:04 ` Magnus Damm
2009-06-10 11:31 ` [PATCH] sh: sh7724 clock framework rewrite V3 Magnus Damm
6 siblings, 0 replies; 8+ messages in thread
From: Magnus Damm @ 2009-06-09 8:04 UTC (permalink / raw)
To: linux-sh
Hi Morimoto-san,
Thanks for checking the patch.
On Mon, Jun 8, 2009 at 7:03 PM, Kuninori
Morimoto<morimoto.kuninori@renesas.com> wrote:
>> This patch contains V2 of the sh7724 clock framework
>> rewrite. The new code makes use of the recently merged
>> div4, div6 and mstp32 helper code. Both extal and fll are
>> supported as input clocks to the pll. The div6 clocks are
>> fed through a divide-by-3 block.
>
>> - MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
> (snip)
>> + MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
Yeah, you are correct.
> I wonder your manual is old one.
> old manual is very bad, and it say lie sometimes.
>
> correct MSTP010 is "tmu1" here
I used the Japanese version of Rev 0.10 for this code, but it contains
"tmu1" for MSTP010.
So this must be my typo. Sorry about that.
I'll repost V3 in the near future. Thank you!
/ magnus
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] sh: sh7724 clock framework rewrite V3
2009-06-02 10:34 [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
` (5 preceding siblings ...)
2009-06-09 8:04 ` Magnus Damm
@ 2009-06-10 11:31 ` Magnus Damm
6 siblings, 0 replies; 8+ messages in thread
From: Magnus Damm @ 2009-06-10 11:31 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@igel.co.jp>
This patch contains V3 of the sh7724 clock framework
rewrite. The new code makes use of the recently merged
div4, div6 and mstp32 helper code. Both extal and fll are
supported as input clocks to the pll. The div6 clocks are
fed through a divide-by-3 block.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
---
Apply V3 in the same order as V2 and V1 - after the sh7723 patch.
Changes since V2:
- Fixed MSTP010 from "flctl0" to "tmu1", thanks Morimoto-san!
arch/sh/Kconfig | 2
arch/sh/kernel/cpu/sh4a/Makefile | 2
arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 85 -----------
arch/sh/kernel/cpu/sh4a/clock-sh7724.c | 242 ++++++++++++++++++++++++++++++++
4 files changed, 249 insertions(+), 82 deletions(-)
--- 0010/arch/sh/Kconfig
+++ work/arch/sh/Kconfig 2009-06-03 17:02:09.000000000 +0900
@@ -516,7 +516,7 @@ config SH_CLK_CPG
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
- def_bool y if !CPU_SUBTYPE_SH7785 && !CPU_SUBTYPE_SH7723
+ def_bool y if !CPU_SUBTYPE_SH7785 && !CPU_SUBTYPE_SH7723 && !CPU_SUBTYPE_SH7724
config SH_CLK_MD
int "CPU Mode Pin Setting"
--- 0010/arch/sh/kernel/cpu/sh4a/Makefile
+++ work/arch/sh/kernel/cpu/sh4a/Makefile 2009-06-03 17:02:09.000000000 +0900
@@ -27,7 +27,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7786) := cl
clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
--- 0010/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ work/arch/sh/kernel/cpu/sh4a/clock-sh7722.c 2009-06-03 17:02:09.000000000 +0900
@@ -130,11 +130,7 @@ static void adjust_clocks(int originate,
* is quite simple..
*/
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
-#define STCPLL(frqcr) ((((frqcr >> 24) & 0x3f) + 1) * 2)
-#else
#define STCPLL(frqcr) (((frqcr >> 24) & 0x1f) + 1)
-#endif
/*
* Instead of having two separate multipliers/divisors set, like this:
@@ -145,11 +141,7 @@ static void adjust_clocks(int originate,
* I created the divisors2 array, which is used to calculate rate like
* rate = parent * 2 / divisors2[ divisor ];
*/
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
-static int divisors2[] = { 4, 1, 8, 12, 16, 24, 32, 1, 48, 64, 72, 96, 1, 144 };
-#else
static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
-#endif
static unsigned long master_clk_recalc(struct clk *clk)
{
@@ -171,17 +163,10 @@ static unsigned long module_clk_recalc(s
return clk->parent->rate / STCPLL(frqcr);
}
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
-#define MASTERDIVS { 12, 16, 24, 30, 32, 36, 48 }
-#define STCMASK 0x3f
-#define DIVCALC(div) (div/2-1)
-#define FRQCRKICK 0x80000000
-#else
#define MASTERDIVS { 2, 3, 4, 6, 8, 16 }
#define STCMASK 0x1f
#define DIVCALC(div) (div-1)
#define FRQCRKICK 0x00000000
-#endif
static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
{
@@ -557,8 +542,7 @@ static struct clk sh7722_r_clock = {
.rate = 32768,
};
-#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
- !defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7343)
/*
* these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
* methods of clk_ops determine which register they should access by
@@ -575,10 +559,9 @@ static struct clk sh7722_siu_b_clock = {
.arch_flags = SCLKBCR,
.ops = &sh7722_siu_clk_ops,
};
-#endif /* CONFIG_CPU_SUBTYPE_SH7343, SH7724 */
+#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
-#if defined(CONFIG_CPU_SUBTYPE_SH7722) ||\
- defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722)
static struct clk sh7722_irda_clock = {
.name = "irda_clk",
.arch_flags = IrDACLKCR,
@@ -676,61 +659,6 @@ static struct clk sh7722_mstpcr_clocks[]
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7724)
- /* See Datasheet : Overview -> Block Diagram */
- MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
- MSTPCR("ic0", "cpu_clk", 0, 30, 0),
- MSTPCR("oc0", "cpu_clk", 0, 29, 0),
- MSTPCR("rs0", "bus_clk", 0, 28, 0),
- MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
- MSTPCR("l2c0", "sh_clk", 0, 26, 0),
- MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
- MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
- MSTPCR("dmac0", "bus_clk", 0, 21, 0),
- MSTPCR("sh0", "sh_clk", 0, 20, 0),
- MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
- MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
- MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
- MSTPCR("cmt0", "r_clk", 0, 14, 0),
- MSTPCR("rwdt0", "r_clk", 0, 13, 0),
- MSTPCR("dmac1", "bus_clk", 0, 12, 0),
- MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
- MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
- MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
- MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
- MSTPCR("scif3", "bus_clk", 0, 6, 0),
- MSTPCR("scif4", "bus_clk", 0, 5, 0),
- MSTPCR("scif5", "bus_clk", 0, 4, 0),
- MSTPCR("msiof0", "bus_clk", 0, 2, 0),
- MSTPCR("msiof1", "bus_clk", 0, 1, 0),
- MSTPCR("keysc0", "r_clk", 1, 12, 0),
- MSTPCR("rtc0", "r_clk", 1, 11, 0),
- MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
- MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
- MSTPCR("mmc0", "bus_clk", 2, 29, 0),
- MSTPCR("eth0", "bus_clk", 2, 28, 0),
- MSTPCR("atapi0", "bus_clk", 2, 26, 0),
- MSTPCR("tpu0", "bus_clk", 2, 25, 0),
- MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
- MSTPCR("tsif0", "bus_clk", 2, 22, 0),
- MSTPCR("usb1", "bus_clk", 2, 21, 0),
- MSTPCR("usb0", "bus_clk", 2, 20, 0),
- MSTPCR("2dg0", "bus_clk", 2, 19, 0),
- MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
- MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
- MSTPCR("veu1", "bus_clk", 2, 15, CLK_ENABLE_ON_INIT),
- MSTPCR("ceu1", "bus_clk", 2, 13, 0),
- MSTPCR("beu1", "bus_clk", 2, 12, 0),
- MSTPCR("2ddmac0", "sh_clk", 2, 10, 0),
- MSTPCR("spu0", "bus_clk", 2, 9, 0),
- MSTPCR("jpu0", "bus_clk", 2, 6, 0),
- MSTPCR("vou0", "bus_clk", 2, 5, 0),
- MSTPCR("beu0", "bus_clk", 2, 4, 0),
- MSTPCR("ceu0", "bus_clk", 2, 3, 0),
- MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
- MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
- MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
-#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7343)
MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
@@ -802,14 +730,11 @@ static struct clk *sh7722_clocks[] = {
&sh7722_sh_clock,
&sh7722_peripheral_clock,
&sh7722_sdram_clock,
-#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
- !defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7343)
&sh7722_siu_a_clock,
&sh7722_siu_b_clock,
#endif
-/* 7724 should support FSI clock */
-#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
- defined(CONFIG_CPU_SUBTYPE_SH7724)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722)
&sh7722_irda_clock,
#endif
&sh7722_video_clock,
--- /dev/null
+++ work/arch/sh/kernel/cpu/sh4a/clock-sh7724.c 2009-06-10 19:53:34.000000000 +0900
@@ -0,0 +1,242 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+ *
+ * SH7724 clock framework support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+
+/* SH7724 registers */
+#define FRQCRA 0xa4150000
+#define FRQCRB 0xa4150004
+#define VCLKCR 0xa4150048
+#define FCLKACR 0xa4150008
+#define FCLKBCR 0xa415000c
+#define IRDACLKCR 0xa4150018
+#define PLLCR 0xa4150024
+#define MSTPCR0 0xa4150030
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+#define SPUCLKCR 0xa415003c
+#define FLLFRQ 0xa4150050
+#define LSTATS 0xa4150060
+
+/* Fixed 32 KHz root clock for RTC and Power Management purposes */
+static struct clk r_clk = {
+ .name = "rclk",
+ .id = -1,
+ .rate = 32768,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+struct clk extal_clk = {
+ .name = "extal",
+ .id = -1,
+ .rate = 33333333,
+};
+
+/* The fll multiplies the 32khz r_clk, may be used instead of extal */
+static unsigned long fll_recalc(struct clk *clk)
+{
+ unsigned long mult = 0;
+ unsigned long div = 1;
+
+ if (__raw_readl(PLLCR) & 0x1000)
+ mult = __raw_readl(FLLFRQ) & 0x3ff;
+
+ if (__raw_readl(FLLFRQ) & 0x4000)
+ div = 2;
+
+ return (clk->parent->rate * mult) / div;
+}
+
+static struct clk_ops fll_clk_ops = {
+ .recalc = fll_recalc,
+};
+
+static struct clk fll_clk = {
+ .name = "fll_clk",
+ .id = -1,
+ .ops = &fll_clk_ops,
+ .parent = &r_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+ unsigned long mult = 1;
+
+ if (__raw_readl(PLLCR) & 0x4000)
+ mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
+
+ return clk->parent->rate * mult;
+}
+
+static struct clk_ops pll_clk_ops = {
+ .recalc = pll_recalc,
+};
+
+static struct clk pll_clk = {
+ .name = "pll_clk",
+ .id = -1,
+ .ops = &pll_clk_ops,
+ .flags = CLK_ENABLE_ON_INIT,
+};
+
+/* A fixed divide-by-3 block use by the div6 clocks */
+static unsigned long div3_recalc(struct clk *clk)
+{
+ return clk->parent->rate / 3;
+}
+
+static struct clk_ops div3_clk_ops = {
+ .recalc = div3_recalc,
+};
+
+static struct clk div3_clk = {
+ .name = "div3_clk",
+ .id = -1,
+ .ops = &div3_clk_ops,
+ .parent = &pll_clk,
+};
+
+struct clk *main_clks[] = {
+ &r_clk,
+ &extal_clk,
+ &fll_clk,
+ &pll_clk,
+ &div3_clk,
+};
+
+static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
+
+static struct clk_div_mult_table div4_table = {
+ .divisors = divisors,
+ .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
+
+#define DIV4(_str, _reg, _bit, _mask, _flags) \
+ SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+
+struct clk div4_clks[DIV4_NR] = {
+ [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
+ [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
+ [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
+ [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
+ [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
+};
+
+struct clk div6_clks[] = {
+ SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
+ SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
+ SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
+ SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
+ SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
+};
+
+#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
+ SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
+
+static struct clk mstp_clks[] = {
+ MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
+ MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
+ MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
+ MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0),
+ MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
+ MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0),
+ MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
+ MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0),
+ MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
+ MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
+ MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
+ MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
+ MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
+ MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
+ MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
+ MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
+ MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
+ MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
+ MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
+ MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
+ MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
+ MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
+ MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
+ MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
+ MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
+
+ MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0),
+ MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0),
+ MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
+ MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0),
+
+ MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0),
+ MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0),
+ MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0),
+ MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
+ MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
+ MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
+ MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
+ MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1),
+ MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1),
+ MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
+ MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
+ MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1),
+ MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1),
+ MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1),
+ MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1),
+ MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0),
+ MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
+ MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
+ MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
+ MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
+ MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
+ MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
+ MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
+};
+
+int __init arch_clk_init(void)
+{
+ int k, ret = 0;
+
+ /* autodetect extal or fll configuration */
+ if (__raw_readl(PLLCR) & 0x1000)
+ pll_clk.parent = &fll_clk;
+ else
+ pll_clk.parent = &extal_clk;
+
+ for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+ ret = clk_register(main_clks[k]);
+
+ if (!ret)
+ ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+ if (!ret)
+ ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+
+ if (!ret)
+ ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+
+ return ret;
+}
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2009-06-10 11:31 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-06-02 10:34 [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
2009-06-03 5:04 ` Kuninori Morimoto
2009-06-03 8:43 ` [PATCH] sh: sh7724 clock framework rewrite V2 Magnus Damm
2009-06-04 7:53 ` [PATCH] sh: sh7724 clock framework rewrite Magnus Damm
2009-06-04 8:08 ` Kuninori Morimoto
2009-06-08 10:03 ` [PATCH] sh: sh7724 clock framework rewrite V2 Kuninori Morimoto
2009-06-09 8:04 ` Magnus Damm
2009-06-10 11:31 ` [PATCH] sh: sh7724 clock framework rewrite V3 Magnus Damm
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