[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Prafulla Wadaskar]

This patch adds a NAND driver for the Marvell Kirkwood SoC's.

Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Change log:
v2: updated as per feedback for v1 (cosmetic change)

 drivers/mtd/nand/Makefile        |    1 +
 drivers/mtd/nand/kirkwood_nand.c |   81 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 82 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/kirkwood_nand.c

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 471cd6b..766c3f0 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
 COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
 COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c
 COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
new file mode 100644
index 0000000..9cdbe20
--- /dev/null
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/kirkwood.h>
+#include <nand.h>
+
+/* NAND Flash Soc registers */
+struct kwnandf_registers {
+	u32 rd_params;	/* 0x10418 */
+	u32 wr_param;	/* 0x1041c */
+	u8  pad[0x10470 - 0x1041c - 4];
+	u32 ctrl;	/* 0x10470 */
+};
+
+static struct kwnandf_registers *nf_reg =
+	(struct kwnandf_registers *)KW_NANDF_BASE;
+
+/*
+ * hardware specific access to control-lines/bits
+ */
+#define NAND_ACTCEBOOT_BIT		0x02
+
+static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+			      unsigned int ctrl)
+{
+	struct nand_chip *nc = mtd->priv;
+	u32 offs;
+
+	if (cmd == NAND_CMD_NONE)
+		return;
+
+	if (ctrl & NAND_CLE)
+		offs = (1 << 0);	/* Commands with A[1:0] == 01 */
+	else if (ctrl & NAND_ALE)
+		offs = (1 << 1);	/* Addresses with A[1:0] == 10 */
+	else
+		return;
+
+	writeb(cmd, nc->IO_ADDR_W + offs);
+}
+
+void kw_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+	u32 data;
+
+	data = readl(&nf_reg->ctrl);
+	data |= NAND_ACTCEBOOT_BIT;
+	writel(data, &nf_reg->ctrl);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = kw_nand_hwcontrol;
+	nand->chip_delay = 30;
+	nand->select_chip = kw_nand_select_chip;
+	return 0;
+}
-- 
1.5.3.3

[U-Boot] [PATCH v3 2/3] net: Add Marvell Kirkwood gigabit ethernet driver

[Prafulla Wadaskar]

This patch adds a egiga driver for the Marvell Kirkwood SoC's.

Contributors:
Yotam Admon <yotam@marvell.com>
Michael Blostein <michaelbl at marvell.com

Reviewed-by: Ronen Shitrit <rshitrit@marvell.com>
Acked-by: Stefan Rose <sr@denx.de>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Change log:
v2: updated all print messages to provide helpful info

v3: No link dectection bug fixed

 drivers/net/Makefile         |    1 +
 drivers/net/kirkwood_egiga.c |  665 ++++++++++++++++++++++++++++++++++++++++++
 drivers/net/kirkwood_egiga.h |  561 +++++++++++++++++++++++++++++++++++
 include/netdev.h             |    1 +
 4 files changed, 1228 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/kirkwood_egiga.c
 create mode 100644 drivers/net/kirkwood_egiga.h

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a360a50..f0c5654 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_ENC28J60) += enc28j60.o
 COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
 COBJS-$(CONFIG_GRETH) += greth.o
 COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
+COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
 COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
 COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o
 COBJS-$(CONFIG_MACB) += macb.o
diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c
new file mode 100644
index 0000000..455476a
--- /dev/null
+++ b/drivers/net/kirkwood_egiga.c
@@ -0,0 +1,665 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh at galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <asm/errno.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <asm/arch/kirkwood.h>
+#include "kirkwood_egiga.h"
+
+/*
+ * smi_reg_read - miiphy_read callback function.
+ *
+ * Returns 16bit phy register value, or 0xffff on error
+ */
+static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+	struct kwgbe_registers *regs = dkwgbe->regs;
+	u32 smi_reg;
+	volatile u32 timeout;
+
+	/* Phyadr read request */
+	if (phy_adr == 0xEE && reg_ofs == 0xEE) {
+		*data = (u16) (KWGBEREG_RD(regs->phyadr) & 0x00ff);
+		return 0;
+	}
+	/* check parameters */
+	if (phy_adr > 0x1f) {
+		printf("Err..(%s) Invalid PHY address %d\n",
+			__FUNCTION__, phy_adr);
+		return -EFAULT;
+	}
+	if (reg_ofs > 0x1f) {
+		printf("Err..(%s) Invalid register offset %d\n",
+		       __FUNCTION__, reg_ofs);
+		return -EFAULT;
+	}
+
+	timeout = KWGBE_PHY_SMI_TIMEOUT;
+	/* wait till the SMI is not busy */
+	do {
+		/* read smi register */
+		smi_reg = KWGBEREG_RD(regs->smi);
+		if (timeout-- == 0) {
+			printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
+			return -EFAULT;
+		}
+	} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+
+	/* fill the phy address and regiser offset and read opcode */
+	smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
+		| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
+		| KWGBE_PHY_SMI_OPCODE_READ;
+
+	/* write the smi register */
+	KWGBEREG_WR(regs->smi, smi_reg);
+
+	/*wait till read value is ready */
+	timeout = KWGBE_PHY_SMI_TIMEOUT;
+	do {
+		/* read smi register */
+		smi_reg = KWGBEREG_RD(regs->smi);
+		if (timeout-- == 0) {
+			printf("Err..(%s) SMI read ready timeout\n",
+			       __FUNCTION__);
+			return -EFAULT;
+		}
+	} while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
+
+	/* Wait for the data to update in the SMI register */
+	for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
+
+	*data = (u16) (KWGBEREG_RD(regs->smi) & KWGBE_PHY_SMI_DATA_MASK);
+
+	debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
+	      reg_ofs, *data);
+
+	return 0;
+}
+
+/*
+ * smi_reg_write - imiiphy_write callback function.
+ *
+ * Returns 0 if write succeed, -EINVAL on bad parameters
+ * -ETIME on timeout
+ */
+static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+	struct kwgbe_registers *regs = dkwgbe->regs;
+	u32 smi_reg;
+	volatile u32 timeout;
+
+	/* Phyadr write request*/
+	if (phy_adr == 0xEE && reg_ofs == 0xEE) {
+		KWGBEREG_WR(regs->phyadr, data);
+		return 0;
+	}
+
+	/* check parameters */
+	if (phy_adr > 0x1f) {
+		printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
+		return -EINVAL;
+	}
+	if (reg_ofs > 0x1f) {
+		printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	/* wait till the SMI is not busy */
+	timeout = KWGBE_PHY_SMI_TIMEOUT;
+	do {
+		/* read smi register */
+		smi_reg = KWGBEREG_RD(regs->smi);
+		if (timeout-- == 0) {
+			printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
+			return -ETIME;
+		}
+	} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+
+	/* fill the phy addr and reg offset and write opcode and data */
+	smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
+	smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
+		| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
+	smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
+
+	/* write the smi register */
+	KWGBEREG_WR(regs->smi, smi_reg);
+
+	return 0;
+}
+
+/* Stop and checks all queues */
+static void stop_queue(u32 * qreg)
+{
+	u32 reg_data;
+
+	reg_data = readl(qreg);
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		writel((reg_data << 8), qreg);
+
+		/* Wait for all queue activity to terminate. */
+		do {
+			/*
+			 * Check port cause register that all queues
+			 * are stopped
+			 */
+			reg_data = readl(qreg);
+		}
+		while (reg_data & 0xFF);
+	}
+}
+
+/*
+ * set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * This function configures the address decode parameters for the Gigabit
+ * Ethernet Controller according the given parameters struct.
+ *
+ * @regs	Register struct pointer.
+ * @param	Address decode parameter struct.
+ */
+static void set_access_control(struct kwgbe_registers *regs,
+			       struct kwgbe_winparam *param)
+{
+	u32 access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = KWGBEREG_RD(regs->epap);
+	/* clear window permission */
+	access_prot_reg &= (~(3 << (param->win * 2)));
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	KWGBEREG_WR(regs->epap, access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	KWGBEREG_WR(regs->barsz[param->win].size,
+		    (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	KWGBEREG_WR(regs->barsz[param->win].bar,
+		    (param->target | param->attrib | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
+	else
+		KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
+}
+
+static void set_dram_access(struct kwgbe_registers *regs)
+{
+	struct kwgbe_winparam win_param;
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* Set access parameters for DRAM bank i */
+		win_param.win = i;	/* Use Ethernet window i */
+		/* Window target - DDR */
+		win_param.target = KWGBE_TARGET_DRAM;
+		/* Enable full access */
+		win_param.access_ctrl = EWIN_ACCESS_FULL;
+		win_param.high_addr = 0;
+		/* Get bank base */
+		win_param.base_addr = kw_sdram_bar(i);
+		win_param.size = kw_sdram_bs(i);	/* Get bank size */
+		if (win_param.size == 0)
+			win_param.enable = 0;
+		else
+			win_param.enable = 1;	/* Enable the access */
+
+		/* Enable DRAM bank */
+		switch (i) {
+		case 0:
+			win_param.attrib = EBAR_DRAM_CS0;
+			break;
+		case 1:
+			win_param.attrib = EBAR_DRAM_CS1;
+			break;
+		case 2:
+			win_param.attrib = EBAR_DRAM_CS2;
+			break;
+		case 3:
+			win_param.attrib = EBAR_DRAM_CS3;
+			break;
+		default:
+			/* invalide bank, disable access */
+			win_param.enable = 0;
+			win_param.attrib = 0;
+			break;
+		}
+#ifdef CONFIG_SYS_COHERENT_CACHE
+		win_param.attrib |= EBAR_DRAM_CACHE_COHERENCY_WB;
+#endif
+		/* Set the access control for address window(EPAPR) RD/WR */
+		set_access_control(regs, &win_param);
+	}
+}
+
+/*
+ * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+ *
+ * Go through all the DA filter tables (Unicast, Special Multicast & Other
+ * Multicast) and set each entry to 0.
+ */
+static void port_init_mac_tables(struct kwgbe_registers *regs)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index < 4; ++table_index)
+		KWGBEREG_WR(regs->dfut[table_index], 0);
+
+	for (table_index = 0; table_index < 64; ++table_index) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		KWGBEREG_WR(regs->dfsmt[table_index], 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		KWGBEREG_WR(regs->dfomt[table_index], 0);
+	}
+}
+
+/*
+ * port_uc_addr - This function Set the port unicast address table
+ *
+ * This function locates the proper entry in the Unicast table for the
+ * specified MAC nibble and sets its properties according to function
+ * parameters.
+ * This function add/removes MAC addresses from the port unicast address
+ * table.
+ *
+ * @uc_nibble	Unicast MAC Address last nibble.
+ * @option      0 = Add, 1 = remove address.
+ *
+ * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
+ */
+static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
+			int option)
+{
+	u32 unicast_reg;
+	u32 tbl_offset;
+	u32 reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	/* Register offset from unicast table base */
+	tbl_offset = (uc_nibble / 4);
+	/* Entry offset within the above register */
+	reg_offset = uc_nibble % 4;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/*
+		 * Clear accepts frame bit at specified unicast
+		 * DA table entry
+		 */
+		unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+		unicast_reg &= (0xFF << (8 * reg_offset));
+		KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+		break;
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+		unicast_reg &= (0xFF << (8 * reg_offset));
+		unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
+		KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+		break;
+	default:
+		return 0;
+	}
+	return 1;
+}
+
+/*
+ * port_uc_addr_set - This function Set the port Unicast address.
+ */
+static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
+{
+	u32 mac_h;
+	u32 mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
+		(p_addr[3] << 0);
+
+	KWGBEREG_WR(regs->macal, mac_l);
+	KWGBEREG_WR(regs->macah, mac_h);
+
+	/* Accept frames of this address */
+	port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
+}
+
+/*
+ * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ */
+static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
+{
+	volatile struct kwgbe_rxdesc *p_rx_desc;
+	int i;
+
+	/* initialize the Rx descriptors ring */
+	p_rx_desc = dkwgbe->p_rxdesc;
+	for (i = 0; i < RINGSZ; i++) {
+		p_rx_desc->cmd_sts =
+			KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+		p_rx_desc->buf_size = PKTSIZE_ALIGN;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
+		if (i == (RINGSZ - 1))
+			p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
+		else {
+			p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
+				((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
+			p_rx_desc = p_rx_desc->nxtdesc_p;
+		}
+		D_CACHE_FLUSH_LINE(p_rx_desc, 0);
+	}
+
+	dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
+}
+
+static int kwgbe_init(struct eth_device *dev)
+{
+	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+	struct kwgbe_registers *regs = dkwgbe->regs;
+
+	/* setup RX rings */
+	kwgbe_init_rx_desc_ring(dkwgbe);
+
+	/* Clear the ethernet port interrupts */
+	KWGBEREG_WR(regs->ic, 0);
+	KWGBEREG_WR(regs->ice, 0);
+	/* Unmask RX buffer and TX end interrupt */
+	KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
+	/* Unmask phy and link status changes interrupts */
+	KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
+
+	set_dram_access(regs);
+	port_init_mac_tables(regs);
+	port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+
+	/* Assign port configuration and command. */
+	KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
+	KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
+	KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
+	KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+
+	/* Assign port SDMA configuration */
+	KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
+	KWGBEREG_WR(regs->tqx[0].qxttbc, 0x3fffffff);
+	KWGBEREG_WR(regs->tqx[0].tqxtbc, 0x03fffcff);
+	/* Turn off the port/RXUQ bandwidth limitation */
+	KWGBEREG_WR(regs->pmtu, 0x0);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	KWGBEREG_WR(regs->psc0,
+		    (0x5 << 17) | (KWGBEREG_RD(regs->psc0) & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+	KWGBEREG_WR(regs->pmtu, 0);
+
+	/* Assignment of Rx CRDB of given RXUQ */
+	KWGBEREG_WR(regs->rxcdp[RXUQ].rxcdp, (u32) dkwgbe->p_rxdesc_curr);
+	/* Enable port Rx. */
+	KWGBEREG_WR(regs->rqc, (1 << RXUQ));
+
+#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
+	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+	u16 phyadr;
+	miiphy_read(dev->name, 0xEE, 0xEE, &phyadr);
+	if (!miiphy_link(dev->name, phyadr)) {
+		printf("%s: No link on %s\n", __FUNCTION__, dev->name);
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+static int kwgbe_halt(struct eth_device *dev)
+{
+	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+	struct kwgbe_registers *regs = dkwgbe->regs;
+
+	/* Disable all gigE address decoder */
+	KWGBEREG_WR(regs->bare, 0x3f);
+
+	stop_queue(&regs->tqc);
+	stop_queue(&regs->rqc);
+
+	/* Enable port in the Configuration Register */
+	KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+	/* Set port of active in the Configuration Register */
+	KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
+#ifdef CONFIG_SYS_MII_MODE
+	/* Set MMI interface up */
+	KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
+#endif
+	/* Disable ethernet port interrupts */
+	KWGBEREG_WR(regs->ic, 0);
+	KWGBEREG_WR(regs->ice, 0);
+	/* Mask RX buffer and TX end interrupt */
+	KWGBEREG_WR(regs->pim, 0);
+	/* Mask phy and link status changes interrupts */
+	KWGBEREG_WR(regs->peim, 0);
+
+	return 0;
+}
+
+static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
+		      int datasize)
+{
+	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+	struct kwgbe_registers *regs = dkwgbe->regs;
+	struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
+
+	if ((u32) dataptr & 0x07) {
+		printf("Err..(%s) xmit dataptr not 64bit aligned\n",
+		       __FUNCTION__);
+		return -1;
+	}
+	p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
+	p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
+	p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
+	p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
+	p_txdesc->buf_ptr = (u8 *) dataptr;
+	p_txdesc->byte_cnt = datasize;
+
+	/* Flush CPU pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Apply send command using zeroth RXUQ */
+	KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
+	KWGBEREG_WR(regs->tqc, (1 << TXUQ));
+
+	/*
+	 * wait for packet xmit completion
+	 */
+	while (p_txdesc->cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
+		/* return fail if error is detected */
+		if (p_txdesc->cmd_sts & 0x06) {
+			printf("Err..(%s) in xmit packet\n", __FUNCTION__);
+			return -1;
+		}
+	};
+	return 0;
+}
+
+static int kwgbe_recv(struct eth_device *dev)
+{
+	volatile struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+	volatile struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
+
+	/* wait untill rx packet available */
+	while (p_rxdesc_curr->cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) ;
+	D_CACHE_FLUSH_LINE((u32) p_rxdesc_curr, 0);
+
+	if (p_rxdesc_curr->byte_cnt != 0) {
+		debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
+		      __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
+		      (u32) p_rxdesc_curr->buf_ptr,
+		      (u32) p_rxdesc_curr->cmd_sts);
+	}
+
+	/*
+	 * In case received a packet without first/last bits on
+	 * OR the error summary bit is on,
+	 * the packets needs to be dropeed.
+	 */
+	if ((p_rxdesc_curr->cmd_sts &
+	     (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
+	    != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
+
+		printf("Err..(%s) Dropping packet spread on"
+			" multiple descriptors\n", __FUNCTION__);
+
+	} else if (p_rxdesc_curr->cmd_sts & KWGBE_ERROR_SUMMARY) {
+
+		printf("Err..(%s) Dropping packet with errors\n",
+			__FUNCTION__);
+
+	} else {
+		/* !!! call higher layer processing */
+		debug("%s: Sending Received packet to"
+			" upper layer (NetReceive)\n", __FUNCTION__);
+
+		/* let the upper layer handle the packet */
+		NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
+			   (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
+	}
+	/*
+	 * free these descriptors and point next in the ring
+	 */
+	p_rxdesc_curr->cmd_sts =
+		KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+	p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
+	p_rxdesc_curr->byte_cnt = 0x0000;
+
+	dkwgbe->p_rxdesc_curr = p_rxdesc_curr->nxtdesc_p;
+	return 0;
+}
+
+int kirkwood_egiga_initialize(bd_t * bis)
+{
+	struct kwgbe_device *dkwgbe;
+	struct eth_device *dev;
+	int devnum;
+	char *s, buf[64];
+	u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
+
+	for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
+		/*skip if port is configured not to use */
+		if (used_ports[devnum] == 0)
+			continue;
+
+		if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
+			goto error1;
+
+		memset(dkwgbe, 0, sizeof(struct kwgbe_device));
+
+		if (!(dkwgbe->p_rxdesc =
+		      (struct kwgbe_rxdesc *)memalign(PKTALIGN,
+						      KW_RXQ_DESC_ALIGNED_SIZE
+						      * RINGSZ + 1)))
+			goto error2;
+
+		if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
+							* PKTSIZE_ALIGN + 1)))
+			goto error3;
+
+		if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
+		      memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
+			free(dkwgbe->p_rxbuf);
+		      error3:
+			free(dkwgbe->p_rxdesc);
+		      error2:
+			free(dkwgbe);
+		      error1:
+			printf("Err.. %s Failed to allocate memory\n",
+			       __FUNCTION__);
+			return -1;
+		}
+
+		dev = &dkwgbe->dev;
+
+		/* must be less than NAMESIZE (16) */
+		sprintf(dev->name, "egiga%d", devnum);
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			dkwgbe->regs = (void *)KW_EGIGA0_BASE;
+			s = "ethaddr";
+			break;
+		case 1:
+			dkwgbe->regs = (void *)KW_EGIGA1_BASE;
+			s = "eth1addr";
+			break;
+		default:	/* this should never happen */
+			printf("Err..(%s) Invalid device number %d\n",
+			       __FUNCTION__, devnum);
+			return -1;
+		}
+
+		while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
+			/* Generate Ramdom MAC addresses if not set */
+			sprintf(buf, "00:50:43:%02x:%02x:%02x",
+				get_random_hex(), get_random_hex(),
+				get_random_hex());
+			setenv(s, buf);
+		}
+
+		dev->init = (void *)kwgbe_init;
+		dev->halt = (void *)kwgbe_halt;
+		dev->send = (void *)kwgbe_send;
+		dev->recv = (void *)kwgbe_recv;
+
+		eth_register(dev);
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+		miiphy_register(dev->name, smi_reg_read, smi_reg_write);
+		/* Set phy address of the port */
+		miiphy_write(dev->name, 0xEE, 0xEE, PHY_BASE_ADR + devnum);
+#endif
+	}
+	return 0;
+}
diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/kirkwood_egiga.h
new file mode 100644
index 0000000..1d818f9
--- /dev/null
+++ b/drivers/net/kirkwood_egiga.h
@@ -0,0 +1,561 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh at galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EGIGA_H__
+#define __EGIGA_H__
+
+#define MAX_KWGBE_DEVS	2	/*controller has two ports */
+
+/* In case SRAM is cache coherent or non-cacheable */
+#ifndef CONFIG_SYS_COHERENT_CACHE
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#define CPU_PIPE_FLUSH	{ __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop");}
+#else
+#error "Cache coherent macros to be defined.."
+#endif
+
+/* PHY_BASE_ADR is board specific and can be configured */
+#if defined (CONFIG_PHY_BASE_ADR)
+#define PHY_BASE_ADR		CONFIG_PHY_BASE_ADR
+#else
+#define PHY_BASE_ADR		0x08	/* default phy base addr */
+#endif
+
+/* Constants */
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#define RXUQ	0 /* Used Rx queue */
+#define TXUQ	0 /* Used Rx queue */
+
+#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
+#define KWGBEREG_WR(adr, val)		writel(val, &adr)
+#define KWGBEREG_RD(adr)		readl(&adr)
+#define KWGBEREG_BITS_RESET(adr, val)	writel(readl(&adr) & ~(val), &adr)
+#define KWGBEREG_BITS_SET(adr, val)	writel(readl(&adr) | val, &adr)
+
+/* Default port configuration value */
+#define PRT_CFG_VAL			( \
+	KWGBE_UCAST_MOD_NRML		| \
+	KWGBE_DFLT_RX_Q0		| \
+	KWGBE_DFLT_RX_ARPQ0		| \
+	KWGBE_RX_BC_IF_NOT_IP_OR_ARP	| \
+	KWGBE_RX_BC_IF_IP		| \
+	KWGBE_RX_BC_IF_ARP		| \
+	KWGBE_CPTR_TCP_FRMS_DIS		| \
+	KWGBE_CPTR_UDP_FRMS_DIS		| \
+	KWGBE_DFLT_RX_TCPQ0		| \
+	KWGBE_DFLT_RX_UDPQ0		| \
+	KWGBE_DFLT_RX_BPDU_Q_0)
+
+/* Default port extend configuration value */
+#define PORT_CFG_EXTEND_VALUE		\
+	KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL	| \
+	KWGBE_PARTITION_DIS		| \
+	KWGBE_TX_CRC_GENERATION_EN
+
+/* Default sdma control value */
+#ifndef CONFIG_SYS_COHERENT_CACHE
+#define PORT_SDMA_CFG_VALUE		( \
+	KWGBE_RX_BURST_SIZE_16_64BIT	| \
+	KWGBE_BLM_RX_NO_SWAP		| \
+	KWGBE_BLM_TX_NO_SWAP		| \
+	GT_KWGBE_IPG_INT_RX(0)		| \
+	KWGBE_TX_BURST_SIZE_16_64BIT)
+#else
+#define PORT_SDMA_CFG_VALUE		( \
+	KWGBE_RX_BURST_SIZE_4_64BIT	| \
+	GT_KWGBE_IPG_INT_RX(0)		| \
+	KWGBE_TX_BURST_SIZE_4_64BIT)
+#endif
+
+#define GT_KWGBE_IPG_INT_RX(value)	((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE_TMP		( \
+	KWGBE_FORCE_LINK_PASS			| \
+	KWGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	KWGBE_ADV_NO_FLOW_CTRL			| \
+	KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	KWGBE_FORCE_BP_MODE_NO_JAM		| \
+	(1 << 9)				| \
+	KWGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	KWGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	KWGBE_DTE_ADV_0				| \
+	KWGBE_MIIPHY_MAC_MODE			| \
+	KWGBE_AUTO_NEG_NO_CHANGE		| \
+	KWGBE_MAX_RX_PACKET_1552BYTE		| \
+	KWGBE_CLR_EXT_LOOPBACK			| \
+	KWGBE_SET_FULL_DUPLEX_MODE		| \
+	KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX | \
+	KWGBE_SET_MII_SPEED_TO_100)
+
+/* Speed will be configured to 10_100MBPS for MII mode of operation */
+#ifdef CONFIG_SYS_MII_MODE
+#define PORT_SERIAL_CONTROL_VALUE	( \
+	PORT_SERIAL_CONTROL_VALUE_TMP	| \
+	KWGBE_SET_GMII_SPEED_TO_10_100)
+#else
+#define PORT_SERIAL_CONTROL_VALUE	( \
+	PORT_SERIAL_CONTROL_VALUE_TMP	| \
+	KWGBE_SET_GMII_SPEED_TO_1000)
+#endif
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	0x24	/* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE	0x_fFFF	/* PMTBS reg (default) */
+#define PORT_TOKEN_RATE		1023	/* PTTBRC reg (default) */
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR		0
+#define REJECT_MAC_ADDR		1
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define KW_RXQ_DESC_ALIGNED_SIZE	\
+	(((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET		0x2
+
+/* Port serial status reg (PSR) */
+#define KWGBE_INTERFACE_GMII_MII	0
+#define KWGBE_INTERFACE_PCM		1
+#define KWGBE_LINK_IS_DOWN		0
+#define KWGBE_LINK_IS_UP		(1 << 1)
+#define KWGBE_PORT_AT_HALF_DUPLEX	0
+#define KWGBE_PORT_AT_FULL_DUPLEX	(1 << 2)
+#define KWGBE_RX_FLOW_CTRL_DISD		0
+#define KWGBE_RX_FLOW_CTRL_ENBALED	(1 << 3)
+#define KWGBE_GMII_SPEED_100_10		0
+#define KWGBE_GMII_SPEED_1000		(1 << 4)
+#define KWGBE_MII_SPEED_10		0
+#define KWGBE_MII_SPEED_100		(1 << 5)
+#define KWGBE_NO_TX			0
+#define KWGBE_TX_IN_PROGRESS		(1 << 7)
+#define KWGBE_BYPASS_NO_ACTIVE		0
+#define KWGBE_BYPASS_ACTIVE		(1 << 8)
+#define KWGBE_PORT_NOT_AT_PARTN_STT	0
+#define KWGBE_PORT_AT_PARTN_STT		(1 << 9)
+#define KWGBE_PORT_TX_FIFO_NOT_EMPTY	0
+#define KWGBE_PORT_TX_FIFO_EMPTY	(1 << 10)
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define KWGBE_UCAST_MOD_NRML		0
+#define KWGBE_UNICAST_PROMISCUOUS_MODE	1
+#define KWGBE_DFLT_RX_Q0		0
+#define KWGBE_DFLT_RX_Q1		(1 << 1)
+#define KWGBE_DFLT_RX_Q2		(1 << 2)
+#define KWGBE_DFLT_RX_Q3		((1 << 2) | (1 << 1))
+#define KWGBE_DFLT_RX_Q4		(1 << 3)
+#define KWGBE_DFLT_RX_Q5		((1 << 3) | (1 << 1))
+#define KWGBE_DFLT_RX_Q6		((1 << 3) | (1 << 2))
+#define KWGBE_DFLT_RX_Q7		((1 << 3) | (1 << 2) | (1 << 1))
+#define KWGBE_DFLT_RX_ARPQ0		0
+#define KWGBE_DFLT_RX_ARPQ1		(1 << 4)
+#define KWGBE_DFLT_RX_ARPQ2		(1 << 5)
+#define KWGBE_DFLT_RX_ARPQ3		((1 << 5) | (1 << 4))
+#define KWGBE_DFLT_RX_ARPQ4		(1 << 6)
+#define KWGBE_DFLT_RX_ARPQ5		((1 << 6) | (1 << 4))
+#define KWGBE_DFLT_RX_ARPQ6		((1 << 6) | (1 << 5))
+#define KWGBE_DFLT_RX_ARPQ7		((1 << 6) | (1 << 5) | (1 << 4))
+#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP	0
+#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
+#define KWGBE_RX_BC_IF_IP		0
+#define KWGBE_REJECT_BC_IF_IP		(1 << 8)
+#define KWGBE_RX_BC_IF_ARP		0
+#define KWGBE_REJECT_BC_IF_ARP		(1 << 9)
+#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY	(1 << 12)
+#define KWGBE_CPTR_TCP_FRMS_DIS		0
+#define KWGBE_CPTR_TCP_FRMS_EN		(1 << 14)
+#define KWGBE_CPTR_UDP_FRMS_DIS		0
+#define KWGBE_CPTR_UDP_FRMS_EN		(1 << 15)
+#define KWGBE_DFLT_RX_TCPQ0		0
+#define KWGBE_DFLT_RX_TCPQ1		(1 << 16)
+#define KWGBE_DFLT_RX_TCPQ2		(1 << 17)
+#define KWGBE_DFLT_RX_TCPQ3		((1 << 17) | (1 << 16))
+#define KWGBE_DFLT_RX_TCPQ4		(1 << 18)
+#define KWGBE_DFLT_RX_TCPQ5		((1 << 18) | (1 << 16))
+#define KWGBE_DFLT_RX_TCPQ6		((1 << 18) | (1 << 17))
+#define KWGBE_DFLT_RX_TCPQ7		((1 << 18) | (1 << 17) | (1 << 16))
+#define KWGBE_DFLT_RX_UDPQ0		0
+#define KWGBE_DFLT_RX_UDPQ1		(1 << 19)
+#define KWGBE_DFLT_RX_UDPQ2		(1 << 20)
+#define KWGBE_DFLT_RX_UDPQ3		((1 << 20) | (1 << 19))
+#define KWGBE_DFLT_RX_UDPQ4		(1 << 21)
+#define KWGBE_DFLT_RX_UDPQ5		((1 << 21) | (1 << 19))
+#define KWGBE_DFLT_RX_UDPQ6		((1 << 21) | (1 << 20))
+#define KWGBE_DFLT_RX_UDPQ7		((1 << 21) | (1 << 20) | (1 << 19))
+#define KWGBE_DFLT_RX_BPDU_Q_0		 0
+#define KWGBE_DFLT_RX_BPDU_Q_1		(1 << 22)
+#define KWGBE_DFLT_RX_BPDU_Q_2		(1 << 23)
+#define KWGBE_DFLT_RX_BPDU_Q_3		((1 << 23) | (1 << 22))
+#define KWGBE_DFLT_RX_BPDU_Q_4		(1 << 24)
+#define KWGBE_DFLT_RX_BPDU_Q_5		((1 << 24) | (1 << 22))
+#define KWGBE_DFLT_RX_BPDU_Q_6		((1 << 24) | (1 << 23))
+#define KWGBE_DFLT_RX_BPDU_Q_7		((1 << 24) | (1 << 23) | (1 << 22))
+#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE	(1 << 25)
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define KWGBE_CLASSIFY_EN			1
+#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL	0
+#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7	(1 << 1)
+#define KWGBE_PARTITION_DIS			0
+#define KWGBE_PARTITION_EN			(1 << 2)
+#define KWGBE_TX_CRC_GENERATION_EN		0
+#define KWGBE_TX_CRC_GENERATION_DIS		(1 << 3)
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define KWGBE_RIFB				1
+#define KWGBE_RX_BURST_SIZE_1_64BIT		0
+#define KWGBE_RX_BURST_SIZE_2_64BIT		(1 << 1)
+#define KWGBE_RX_BURST_SIZE_4_64BIT		(1 << 2)
+#define KWGBE_RX_BURST_SIZE_8_64BIT		((1 << 2) | (1 << 1))
+#define KWGBE_RX_BURST_SIZE_16_64BIT		(1 << 3)
+#define KWGBE_BLM_RX_NO_SWAP			(1 << 4)
+#define KWGBE_BLM_RX_BYTE_SWAP			0
+#define KWGBE_BLM_TX_NO_SWAP			(1 << 5)
+#define KWGBE_BLM_TX_BYTE_SWAP			0
+#define KWGBE_DESCRIPTORS_BYTE_SWAP		(1 << 6)
+#define KWGBE_DESCRIPTORS_NO_SWAP		0
+#define KWGBE_TX_BURST_SIZE_1_64BIT		0
+#define KWGBE_TX_BURST_SIZE_2_64BIT		(1 << 22)
+#define KWGBE_TX_BURST_SIZE_4_64BIT		(1 << 23)
+#define KWGBE_TX_BURST_SIZE_8_64BIT		((1 << 23) | (1 << 22))
+#define KWGBE_TX_BURST_SIZE_16_64BIT		(1 << 24)
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define KWGBE_SERIAL_PORT_DIS			0
+#define KWGBE_SERIAL_PORT_EN			1
+#define KWGBE_FORCE_LINK_PASS			(1 << 1)
+#define KWGBE_DO_NOT_FORCE_LINK_PASS		0
+#define KWGBE_EN_AUTO_NEG_FOR_DUPLX		0
+#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX		(1 << 2)
+#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL		0
+#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	(1 << 3)
+#define KWGBE_ADV_NO_FLOW_CTRL			0
+#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL		(1 << 4)
+#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	0
+#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS	(1 << 5)
+#define KWGBE_FORCE_BP_MODE_NO_JAM		0
+#define KWGBE_FORCE_BP_MODE_JAM_TX		(1 << 7)
+#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR	(1 << 8)
+#define KWGBE_FORCE_LINK_FAIL			0
+#define KWGBE_DO_NOT_FORCE_LINK_FAIL		(1 << 10)
+#define KWGBE_DIS_AUTO_NEG_SPEED_GMII		(1 << 13)
+#define KWGBE_EN_AUTO_NEG_SPEED_GMII		0
+#define KWGBE_DTE_ADV_0				0
+#define KWGBE_DTE_ADV_1				(1 << 14)
+#define KWGBE_MIIPHY_MAC_MODE			0
+#define KWGBE_MIIPHY_PHY_MODE			(1 << 15)
+#define KWGBE_AUTO_NEG_NO_CHANGE		0
+#define KWGBE_RESTART_AUTO_NEG			(1 << 16)
+#define KWGBE_MAX_RX_PACKET_1518BYTE		0
+#define KWGBE_MAX_RX_PACKET_1522BYTE		(1 << 17)
+#define KWGBE_MAX_RX_PACKET_1552BYTE		(1 << 18)
+#define KWGBE_MAX_RX_PACKET_9022BYTE		((1 << 18) | (1 << 17))
+#define KWGBE_MAX_RX_PACKET_9192BYTE		(1 << 19)
+#define KWGBE_MAX_RX_PACKET_9700BYTE		((1 << 19) | (1 << 17))
+#define KWGBE_SET_EXT_LOOPBACK			(1 << 20)
+#define KWGBE_CLR_EXT_LOOPBACK			0
+#define KWGBE_SET_FULL_DUPLEX_MODE		(1 << 21)
+#define KWGBE_SET_HALF_DUPLEX_MODE		0
+#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	(1 << 22)
+#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+#define KWGBE_SET_GMII_SPEED_TO_10_100		0
+#define KWGBE_SET_GMII_SPEED_TO_1000		(1 << 23)
+#define KWGBE_SET_MII_SPEED_TO_10		0
+#define KWGBE_SET_MII_SPEED_TO_100		(1 << 24)
+
+/* SMI register fields (KWGBE_SMI_REG) */
+#define KWGBE_PHY_SMI_TIMEOUT		10000
+#define KWGBE_PHY_SMI_DATA_OFFS		0	/* Data */
+#define KWGBE_PHY_SMI_DATA_MASK		(0xffff << KWGBE_PHY_SMI_DATA_OFFS)
+#define KWGBE_PHY_SMI_DEV_ADDR_OFFS	16	/* PHY device address */
+#define KWGBE_PHY_SMI_DEV_ADDR_MASK	(0x1f << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
+#define KWGBE_SMI_REG_ADDR_OFFS		21	/* PHY device reg addr */
+#define KWGBE_SMI_REG_ADDR_MASK		(0x1f << KWGBE_SMI_REG_ADDR_OFFS)
+#define KWGBE_PHY_SMI_OPCODE_OFFS	26	/* Write/Read opcode */
+#define KWGBE_PHY_SMI_OPCODE_MASK	(3 << KWGBE_PHY_SMI_OPCODE_OFFS)
+#define KWGBE_PHY_SMI_OPCODE_WRITE	(0 << KWGBE_PHY_SMI_OPCODE_OFFS)
+#define KWGBE_PHY_SMI_OPCODE_READ	(1 << KWGBE_PHY_SMI_OPCODE_OFFS)
+#define KWGBE_PHY_SMI_READ_VALID_MASK	(1 << 27)	/* Read Valid */
+#define KWGBE_PHY_SMI_BUSY_MASK		(1 << 28)	/* Busy */
+
+/* SDMA command status fields macros */
+/* Tx & Rx descriptors status */
+#define KWGBE_ERROR_SUMMARY		1
+
+/* Tx & Rx descriptors command */
+#define KWGBE_BUFFER_OWNED_BY_DMA	(1 << 31)
+
+/* Tx descriptors status */
+#define KWGBE_LC_ERROR			0
+#define KWGBE_UR_ERROR			(1 << 1)
+#define KWGBE_RL_ERROR			(1 << 2)
+#define KWGBE_LLC_SNAP_FORMAT		(1 << 9)
+
+/* Rx descriptors status */
+#define KWGBE_CRC_ERROR			0
+#define KWGBE_OVERRUN_ERROR		(1 << 1)
+#define KWGBE_MAX_FRAME_LENGTH_ERROR	(1 << 2)
+#define KWGBE_RESOURCE_ERROR		((1 << 2) | (1 << 1))
+#define KWGBE_VLAN_TAGGED		(1 << 19)
+#define KWGBE_BPDU_FRAME		(1 << 20)
+#define KWGBE_TCP_FRAME_OVER_IP_V_4	0
+#define KWGBE_UDP_FRAME_OVER_IP_V_4	(1 << 21)
+#define KWGBE_OTHER_FRAME_TYPE		(1 << 22)
+#define KWGBE_LAYER_2_IS_KWGBE_V_2	(1 << 23)
+#define KWGBE_FRAME_TYPE_IP_V_4		(1 << 24)
+#define KWGBE_FRAME_HEADER_OK		(1 << 25)
+#define KWGBE_RX_LAST_DESC		(1 << 26)
+#define KWGBE_RX_FIRST_DESC		(1 << 27)
+#define KWGBE_UNKNOWN_DESTINATION_ADDR	(1 << 28)
+#define KWGBE_RX_EN_INTERRUPT		(1 << 29)
+#define KWGBE_LAYER_4_CHECKSUM_OK	(1 << 30)
+
+/* Rx descriptors byte count */
+#define KWGBE_FRAME_FRAGMENTED		(1 << 2)
+
+/* Tx descriptors command */
+#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC	(1 << 10)
+#define KWGBE_FRAME_SET_TO_VLAN			(1 << 15)
+#define KWGBE_TCP_FRAME				0
+#define KWGBE_UDP_FRAME				(1 << 16)
+#define KWGBE_GEN_TCP_UDP_CHECKSUM		(1 << 17)
+#define KWGBE_GEN_IP_V_4_CHECKSUM		(1 << 18)
+#define KWGBE_ZERO_PADDING			(1 << 19)
+#define KWGBE_TX_LAST_DESC			(1 << 20)
+#define KWGBE_TX_FIRST_DESC			(1 << 21)
+#define KWGBE_GEN_CRC				(1 << 22)
+#define KWGBE_TX_EN_INTERRUPT			(1 << 23)
+#define KWGBE_AUTO_MODE				(1 << 30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM			0x00000000
+#define EBAR_TARGET_DEVICE			0x00000001
+#define EBAR_TARGET_CBS				0x00000002
+#define EBAR_TARGET_PCI0			0x00000003
+#define EBAR_TARGET_PCI1			0x00000004
+#define EBAR_TARGET_CUNIT			0x00000005
+#define EBAR_TARGET_AUNIT			0x00000006
+#define EBAR_TARGET_GUNIT			0x00000007
+
+/* Window attrib */
+#define EBAR_DRAM_CS0				0x00000E00
+#define EBAR_DRAM_CS1				0x00000D00
+#define EBAR_DRAM_CS2				0x00000B00
+#define EBAR_DRAM_CS3				0x00000700
+
+/* DRAM Target interface */
+#define EBAR_DRAM_NO_CACHE_COHERENCY		0x00000000
+#define EBAR_DRAM_CACHE_COHERENCY_WT		0x00001000
+#define EBAR_DRAM_CACHE_COHERENCY_WB		0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_DEVICE_DEVCS0			0x00001E00
+#define EBAR_DEVICE_DEVCS1			0x00001D00
+#define EBAR_DEVICE_DEVCS2			0x00001B00
+#define EBAR_DEVICE_DEVCS3			0x00001700
+#define EBAR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_PCI_BYTE_SWAP			0x00000000
+#define EBAR_PCI_NO_SWAP			0x00000100
+#define EBAR_PCI_BYTE_WORD_SWAP			0x00000200
+#define EBAR_PCI_WORD_SWAP			0x00000300
+#define EBAR_PCI_NO_SNOOP_NOT_ASSERT		0x00000000
+#define EBAR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_PCI_IO_SPACE			0x00000000
+#define EBAR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_PCI_REQ64_SIZE			0x00001000
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	1
+#define EWIN_ACCESS_FULL	((1 << 1) | 1)
+
+/* structures represents Controller registers */
+struct kwgbe_barsz {
+	u32 bar;
+	u32 size;
+};
+
+struct kwgbe_rxcdp {
+	struct kwgbe_rxdesc *rxcdp;
+	u32 rxcdp_pad[3];
+};
+
+struct kwgbe_tqx {
+	u32 qxttbc;
+	u32 tqxtbc;
+	u32 tqxac;
+	u32 tqxpad;
+};
+
+struct kwgbe_registers {
+	u32 phyadr;
+	u32 smi;
+	u32 euda;
+	u32 eudid;
+	u8 pad1[0x080 - 0x00c - 4];
+	u32 euic;
+	u32 euim;
+	u8 pad2[0x094 - 0x084 - 4];
+	u32 euea;
+	u32 euiae;
+	u8 pad3[0x0b0 - 0x098 - 4];
+	u32 euc;
+	u8 pad3a[0x200 - 0x0b0 - 4];
+	struct kwgbe_barsz barsz[6];
+	u8 pad4[0x280 - 0x22c - 4];
+	u32 ha_remap[4];
+	u32 bare;
+	u32 epap;
+	u8 pad5[0x400 - 0x294 - 4];
+	u32 pxc;
+	u32 pxcx;
+	u32 mii_ser_params;
+	u8 pad6[0x410 - 0x408 - 4];
+	u32 evlane;
+	u32 macal;
+	u32 macah;
+	u32 sdc;
+	u32 dscp[7];
+	u32 psc0;
+	u32 vpt2p;
+	u32 ps0;
+	u32 tqc;
+	u32 psc1;
+	u32 ps1;
+	u32 mrvl_header;
+	u8 pad7[0x460 - 0x454 - 4];
+	u32 ic;
+	u32 ice;
+	u32 pim;
+	u32 peim;
+	u8 pad8[0x474 - 0x46c - 4];
+	u32 pxtfut;
+	u32 pad9;
+	u32 pxmfs;
+	u32 pad10;
+	u32 pxdfc;
+	u32 pxofc;
+	u8 pad11[0x494 - 0x488 - 4];
+	u32 peuiae;
+	u8 pad12[0x4bc - 0x494 - 4];
+	u32 eth_type_prio;
+	u8 pad13[0x4dc - 0x4bc - 4];
+	u32 tqfpc;
+	u32 pttbrc;
+	u32 tqc1;
+	u32 pmtu;
+	u32 pmtbs;
+	u8 pad14[0x60c - 0x4ec - 4];
+	struct kwgbe_rxcdp rxcdp[7];
+	u32 rxcdp7;
+	u32 rqc;
+	struct kwgbe_txdesc *tcsdp;
+	u8 pad15[0x6c0 - 0x684 - 4];
+	struct kwgbe_txdesc *tcqdp[8];
+	u8 pad16[0x700 - 0x6dc - 4];
+	struct kwgbe_tqx tqx[8];
+	u32 pttbc;
+	u8 pad17[0x7a8 - 0x780 - 4];
+	u32 tqxipg0;
+	u32 pad18[3];
+	u32 tqxipg1;
+	u8 pad19[0x7c0 - 0x7b8 - 4];
+	u32 hitkninlopkt;
+	u32 hitkninasyncpkt;
+	u32 lotkninasyncpkt;
+	u32 pad20;
+	u32 ts;
+	u8 pad21[0x3000 - 0x27d0 - 4];
+	u32 pad20_1[32];	/* mib counter registes */
+	u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
+	u32 dfsmt[64];
+	u32 dfomt[64];
+	u32 dfut[4];
+	u8 pad23[0xe20c0 - 0x7360c - 4];
+	u32 pmbus_top_arbiter;
+};
+
+/* structures/enums needed by driver */
+enum kwgbe_adrwin {
+	KWGBE_WIN0,
+	KWGBE_WIN1,
+	KWGBE_WIN2,
+	KWGBE_WIN3,
+	KWGBE_WIN4,
+	KWGBE_WIN5
+};
+
+enum kwgbe_target {
+	KWGBE_TARGET_DRAM,
+	KWGBE_TARGET_DEV,
+	KWGBE_TARGET_CBS,
+	KWGBE_TARGET_PCI0,
+	KWGBE_TARGET_PCI1
+};
+
+struct kwgbe_winparam {
+	enum kwgbe_adrwin win;	/* Window number */
+	enum kwgbe_target target;	/* System targets */
+	u16 attrib;		/* BAR attrib. See above macros */
+	u32 base_addr;		/* Window base address in u32 form */
+	u32 high_addr;		/* Window high address in u32 form */
+	u32 size;		/* Size in MBytes. Must be % 64Kbyte. */
+	int enable;		/* Enable/disable access to the window. */
+	u16 access_ctrl;	/*Access ctrl register. see above macros */
+};
+
+struct kwgbe_rxdesc {
+	u32 cmd_sts;		/* Descriptor command status */
+	u16 buf_size;		/* Buffer size */
+	u16 byte_cnt;		/* Descriptor buffer byte count */
+	u8 *buf_ptr;		/* Descriptor buffer pointer */
+	struct kwgbe_rxdesc *nxtdesc_p;	/* Next descriptor pointer */
+};
+
+struct kwgbe_txdesc {
+	u32 cmd_sts;		/* Descriptor command status */
+	u16 l4i_chk;		/* CPU provided TCP Checksum */
+	u16 byte_cnt;		/* Descriptor buffer byte count */
+	u8 *buf_ptr;		/* Descriptor buffer ptr */
+	struct kwgbe_txdesc *nxtdesc_p;	/* Next descriptor ptr */
+};
+
+/* port device data struct */
+struct kwgbe_device {
+	struct eth_device dev;
+	struct kwgbe_registers *regs;
+	struct kwgbe_txdesc *p_txdesc;
+	struct kwgbe_rxdesc *p_rxdesc;
+	struct kwgbe_rxdesc *p_rxdesc_curr;
+	u8 *p_rxbuf;
+};
+
+#endif /* __EGIGA_H__ */
diff --git a/include/netdev.h b/include/netdev.h
index 63cf730..b73aa8e 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -52,6 +52,7 @@ int fec_initialize (bd_t *bis);
 int greth_initialize(bd_t *bis);
 void gt6426x_eth_initialize(bd_t *bis);
 int inca_switch_initialize(bd_t *bis);
+int kirkwood_egiga_initialize(bd_t *bis);
 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int mcdmafec_initialize(bd_t *bis);
 int mcffec_initialize(bd_t *bis);
-- 
1.5.3.3

[U-Boot] [PATCH v4 3/3] Marvell Sheevaplug Board support

[Prafulla Wadaskar]

Reference:
http://plugcomputer.org/
http://openplug.org/plugwiki/index.php/Das_U-boot_plug_support

This patch is tested for-
1. Boot from DRAM/NAND flash
2. File transfer using tftp
3. NAND flash read/write/erase
4. Linux kernel and RFS Boot from NAND

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Change log:
v2: updated as per feedback for v1

v3: updated as per feedback for v2

v4: removed PHY driver dependency, coded in sheevaplug.c

 MAINTAINERS                           |    4 +
 MAKEALL                               |    1 +
 Makefile                              |    4 +-
 board/Marvell/sheevaplug/Makefile     |   51 +++++++++
 board/Marvell/sheevaplug/config.mk    |   25 +++++
 board/Marvell/sheevaplug/sheevaplug.c |  155 ++++++++++++++++++++++++++
 board/Marvell/sheevaplug/sheevaplug.h |   41 +++++++
 include/configs/sheevaplug.h          |  191 +++++++++++++++++++++++++++++++++
 8 files changed, 471 insertions(+), 1 deletions(-)
 create mode 100644 board/Marvell/sheevaplug/Makefile
 create mode 100644 board/Marvell/sheevaplug/config.mk
 create mode 100644 board/Marvell/sheevaplug/sheevaplug.c
 create mode 100644 board/Marvell/sheevaplug/sheevaplug.h
 create mode 100644 include/configs/sheevaplug.h

diff --git a/MAINTAINERS b/MAINTAINERS
index bf076b9..2474481 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -655,6 +655,10 @@ Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
 
 	SFFSDR		ARM926EJS
 
+Prafulla Wadaskar <prafulla@marvell.com>
+
+	sheevaplug	ARM926EJS (Kirkwood SoC)
+
 Richard Woodruff <r-woodruff2@ti.com>
 
 	omap2420h4	ARM1136EJS
diff --git a/MAKEALL b/MAKEALL
index c98d03a..4a7ccee 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -516,6 +516,7 @@ LIST_ARM9="			\
 	omap730p2		\
 	sbc2410x		\
 	scb9328			\
+	sheevaplug		\
 	smdk2400		\
 	smdk2410		\
 	trab			\
diff --git a/Makefile b/Makefile
index 81a5cd0..527e383 100644
--- a/Makefile
+++ b/Makefile
@@ -2879,6 +2879,9 @@ sbc2410x_config: unconfig
 scb9328_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx
 
+sheevaplug_config: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
+
 smdk2400_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t smdk2400 samsung s3c24x0
 
@@ -3107,7 +3110,6 @@ omap2420h4_config	: unconfig
 qong_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 qong davedenx mx31
 
-
 #########################################################################
 ## ARM1176 Systems
 #########################################################################
diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile
new file mode 100644
index 0000000..e378b5b
--- /dev/null
+++ b/board/Marvell/sheevaplug/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= sheevaplug.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/sheevaplug/config.mk b/board/Marvell/sheevaplug/config.mk
new file mode 100644
index 0000000..a4ea769
--- /dev/null
+++ b/board/Marvell/sheevaplug/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00600000
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
new file mode 100644
index 0000000..547126a
--- /dev/null
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "sheevaplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
+			SHEEVAPLUG_OE_VAL_HIGH,
+			SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_UART0_RTS,
+		MPP9_UART0_CTS,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config);
+
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h
new file mode 100644
index 0000000..3ed5b7f
--- /dev/null
+++ b/board/Marvell/sheevaplug/sheevaplug.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __SHEEVAPLUG_H
+#define __SHEEVAPLUG_H
+
+#define SHEEVAPLUG_OE_LOW		(~(0))
+#define SHEEVAPLUG_OE_HIGH		(~(0))
+#define SHEEVAPLUG_OE_VAL_LOW		(1 << 29)	/* USB_PWEN low */
+#define SHEEVAPLUG_OE_VAL_HIGH		(1 << 17)	/* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __SHEEVAPLUG_H */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
new file mode 100644
index 0000000..0c7545a
--- /dev/null
+++ b/include/configs/sheevaplug.h
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_SHEEVAPLUG_H
+#define _CONFIG_SHEEVAPLUG_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-Sheevaplug"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL		1
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_SHEEVAPLUG	/* Machine type */
+
+#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ		1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define	CONFIG_SYS_PROMPT	"Marvell>> "	/* Command Prompt */
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+
+/*
+ * Flash configuration
+ */
+#ifndef CONFIG_CMD_FLASH
+#define CONFIG_SYS_NO_FLASH		1	/* Declare no flash (NOR/SPI) */
+#endif
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* KW_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x40000
+#define CONFIG_ENV_OFFSET		0x40000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS		"orion_nand:512k(uboot),"	\
+	"3m at 1m(kernel),1m at 4m(psm),13m at 5m(rootfs) rw\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"	\
+	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS	\
+	"x_bootcmd_kernel=nand read 0x100000 0x6400000 0x300000\0" \
+	"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
+#define CONFIG_ARCH_CPU_INIT	/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT	/* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO	/* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS	4
+#define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
+#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_NET_MULTI	/* specify more that one ports available */
+#define	CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1,0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+
+#endif /* _CONFIG_SHEEVAPLUG_H */
-- 
1.5.3.3

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Jean-Christophe PLAGNIOL-VILLARD]

On 17:34 Mon 08 Jun     , Prafulla Wadaskar wrote:
> This patch adds a NAND driver for the Marvell Kirkwood SoC's.
> 
> Acked-by: Stefan Roese <sr@denx.de>
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Change log:
> v2: updated as per feedback for v1 (cosmetic change)
Scott what is status for you?

Best Regards,
J.

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Prafulla Wadaskar]

 

> -----Original Message-----
> From: Jean-Christophe PLAGNIOL-VILLARD [mailto:plagnioj at jcrosoft.com] 
> Sent: Saturday, June 13, 2009 7:32 PM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Manas Saksena; Ronen Shitrit; 
> Nicolas Pitre; Ashish Karkare; Prabhanjan Sarnaik; Lennert 
> Buijtenhek; Scott Wood
> Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add 
> Marvell Kirkwood NAND driver
> 
> On 17:34 Mon 08 Jun     , Prafulla Wadaskar wrote:
> > This patch adds a NAND driver for the Marvell Kirkwood SoC's.
> > 
> > Acked-by: Stefan Roese <sr@denx.de>
> > Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> > ---
> > Change log:
> > v2: updated as per feedback for v1 (cosmetic change)
> Scott what is status for you?
Hi Scott,
I have re-posted this driver twice.. Any updates on this?

Regards..
Prafulla . . 

> 
> Best Regards,
> J.
> 

[U-Boot] [PATCH v4 3/3] Marvell Sheevaplug Board support

[Prafulla Wadaskar]

> -----Original Message-----
> From: Prafulla Wadaskar [mailto:prafulla at marvell.com] 
> Sent: Monday, June 08, 2009 5:35 PM
> To: u-boot at lists.denx.de
> Cc: Nicolas Pitre; Manas Saksena; Lennert Buijtenhek; 
> Prabhanjan Sarnaik; Ronen Shitrit; Ashish Karkare; Prafulla Wadaskar
> Subject: [PATCH v4 3/3] Marvell Sheevaplug Board support
> 
> Reference:
> http://plugcomputer.org/
> http://openplug.org/plugwiki/index.php/Das_U-boot_plug_support
> 
> This patch is tested for-
> 1. Boot from DRAM/NAND flash
> 2. File transfer using tftp
> 3. NAND flash read/write/erase
> 4. Linux kernel and RFS Boot from NAND
> 
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Change log:
> v2: updated as per feedback for v1
> 
> v3: updated as per feedback for v2
> 
> v4: removed PHY driver dependency, coded in sheevaplug.c

Hi Jean,

Network driver dependency (2/3) in this patch series is accepted by Ben
Anther dependency (1/3), the nand driver is all done, waiting for reply from scott.
Since this is arm board- who will be custodian to accept this patch? are you? :-)

Regards..
Prafulla . . 

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Scott Wood]

Prafulla Wadaskar wrote:
>> Scott what is status for you?
> Hi Scott,
> I have re-posted this driver twice.. Any updates on this?

Sorry, I was out the previous week and have been busy catching up this past 
week.  I'll try to get to the stack of pending NAND stuff soon.

-Scott

[U-Boot] [PATCH v4 3/3] Marvell Sheevaplug Board support

[Jean-Christophe PLAGNIOL-VILLARD]

On 02:32 Fri 19 Jun     , Prafulla Wadaskar wrote:
> 
> > -----Original Message-----
> > From: Prafulla Wadaskar [mailto:prafulla at marvell.com] 
> > Sent: Monday, June 08, 2009 5:35 PM
> > To: u-boot at lists.denx.de
> > Cc: Nicolas Pitre; Manas Saksena; Lennert Buijtenhek; 
> > Prabhanjan Sarnaik; Ronen Shitrit; Ashish Karkare; Prafulla Wadaskar
> > Subject: [PATCH v4 3/3] Marvell Sheevaplug Board support
> > 
> > Reference:
> > http://plugcomputer.org/
> > http://openplug.org/plugwiki/index.php/Das_U-boot_plug_support
> > 
> > This patch is tested for-
> > 1. Boot from DRAM/NAND flash
> > 2. File transfer using tftp
> > 3. NAND flash read/write/erase
> > 4. Linux kernel and RFS Boot from NAND
> > 
> > Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> > ---
> > Change log:
> > v2: updated as per feedback for v1
> > 
> > v3: updated as per feedback for v2
> > 
> > v4: removed PHY driver dependency, coded in sheevaplug.c
> 
> Hi Jean,
> 
> Network driver dependency (2/3) in this patch series is accepted by Ben
> Anther dependency (1/3), the nand driver is all done, waiting for reply from scott.
> Since this is arm board- who will be custodian to accept this patch? are you? :-)
the board I the others as you point Ben and Scott

Best Regards,
J.

[U-Boot] [PATCH v4 3/3] Marvell Sheevaplug Board support

[Prafulla Wadaskar]

Hi Jean,

I observed that your arm/master is newly rebased, most of my patches are available here, where as Basic Kirkwood support is available on arm/next branch.

I have applied Basic Kirkwood patches from next to master branch and tried to build it there. At the end I get build error saying EABI version mismatch.
In this regard, may you please suggest me what additional patches I should pick from next branch to resolve this problem? (I saw certain work in this direction by you)

Or shall I continue working on arm/next?

Regards..
Prafulla . .
  

> -----Original Message-----
> From: u-boot-bounces at lists.denx.de 
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Prafulla Wadaskar
> Sent: Friday, June 19, 2009 3:03 PM
> To: Jean-Christophe PLAGNIOL-VILLARD; u-boot at lists.denx.de
> Cc: Manas Saksena; Ronen Shitrit; Nicolas Pitre; Ashish 
> Karkare; Prabhanjan Sarnaik; Lennert Buijtenhek
> Subject: Re: [U-Boot] [PATCH v4 3/3] Marvell Sheevaplug Board support
> 
> 
> > -----Original Message-----
> > From: Prafulla Wadaskar [mailto:prafulla at marvell.com]
> > Sent: Monday, June 08, 2009 5:35 PM
> > To: u-boot at lists.denx.de
> > Cc: Nicolas Pitre; Manas Saksena; Lennert Buijtenhek; Prabhanjan 
> > Sarnaik; Ronen Shitrit; Ashish Karkare; Prafulla Wadaskar
> > Subject: [PATCH v4 3/3] Marvell Sheevaplug Board support
> > 
> > Reference:
> > http://plugcomputer.org/
> > http://openplug.org/plugwiki/index.php/Das_U-boot_plug_support
> > 
> > This patch is tested for-
> > 1. Boot from DRAM/NAND flash
> > 2. File transfer using tftp
> > 3. NAND flash read/write/erase
> > 4. Linux kernel and RFS Boot from NAND
> > 
> > Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> > ---
> > Change log:
> > v2: updated as per feedback for v1
> > 
> > v3: updated as per feedback for v2
> > 
> > v4: removed PHY driver dependency, coded in sheevaplug.c
> 
> Hi Jean,
> 
> Network driver dependency (2/3) in this patch series is 
> accepted by Ben Anther dependency (1/3), the nand driver is 
> all done, waiting for reply from scott.
> Since this is arm board- who will be custodian to accept this 
> patch? are you? :-)
> 
> Regards..
> Prafulla . . 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
> 

[U-Boot] [PATCH v4 3/3] Marvell Sheevaplug Board support

[Jean-Christophe PLAGNIOL-VILLARD]

On 04:43 Mon 22 Jun     , Prafulla Wadaskar wrote:
> Hi Jean,
> 
> I observed that your arm/master is newly rebased, most of my patches are available here, where as Basic Kirkwood support is available on arm/next branch.
> 
> I have applied Basic Kirkwood patches from next to master branch and tried to build it there. At the end I get build error saying EABI version mismatch.
> In this regard, may you please suggest me what additional patches I should pick from next branch to resolve this problem? (I saw certain work in this direction by you)
you need to pick this 2 patch fron the testing branch

http://git.denx.de/?p=u-boot/u-boot-arm.git;a=commit;h=5b30fe639c3ca0141d78820be74ce26120056116
http://git.denx.de/?p=u-boot/u-boot-arm.git;a=commit;h=009130ac00f4679516c6bb5a20f9a97eec98e6bc
> 
> Or shall I continue working on arm/next?
or continue to work on the next I will keep them sync about arm part

Best Regards,
J.

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Jean-Christophe PLAGNIOL-VILLARD]

> > > > > +#include <common.h>
> > > > > +#include <asm/io.h>
> > > > > +#include <asm/arch/kirkwood.h>
> > > > > +#include <nand.h>
> > > > 
> > > > I don't see kirkwood.h in upstream, so I guess this 
> > should go via an 
> > > > arch tree.
> > > Hi Jean,
> > > Similar to spi driver, can you please pull this driver too?
> > > I am posting the new spin for suggested modification
> > > 
> > please fix the year and I will
> Hi Jean
> I have already posted v3 for this, but I could not find this in your today's pull request
> Ref: http://lists.denx.de/pipermail/u-boot/2009-June/055110.html
> Can you please apply this one?
I've not seen it but I'll send other pull requests for this release :)

Best Regards,
J.

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Prafulla Wadaskar]

 

> -----Original Message-----
> From: Jean-Christophe PLAGNIOL-VILLARD [mailto:plagnioj at jcrosoft.com] 
> Sent: Saturday, June 27, 2009 8:53 PM
> To: Prafulla Wadaskar
> Cc: Scott Wood; u-boot at lists.denx.de; Ashish Karkare; 
> Prabhanjan Sarnaik; Ronen Shitrit
> Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add 
> Marvell Kirkwood NAND driver
> 
> On 00:32 Fri 26 Jun     , Prafulla Wadaskar wrote:
> >  
> > 
> > > -----Original Message-----
> > > From: Scott Wood [mailto:scottwood at freescale.com]
> > > Sent: Tuesday, June 23, 2009 3:35 AM
> > > To: Prafulla Wadaskar
> > > Cc: u-boot at lists.denx.de; Ashish Karkare; Prabhanjan 
> Sarnaik; Ronen 
> > > Shitrit
> > > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell 
> > > Kirkwood NAND driver
> > > 
> > > On Sun, Jun 14, 2009 at 10:32:47PM +0530, Prafulla Wadaskar wrote:
> > > > diff --git a/drivers/mtd/nand/kirkwood_nand.c
> > > > b/drivers/mtd/nand/kirkwood_nand.c
> > > > new file mode 100644
> > > > index 0000000..9cdbe20
> > > > --- /dev/null
> > > > +++ b/drivers/mtd/nand/kirkwood_nand.c
> > > > @@ -0,0 +1,81 @@
> > > > +/*
> > > > + * Copyright (C) Marvell International Ltd. and its affiliates
> > > 
> > > No year?
> > > 
> > > > +#include <common.h>
> > > > +#include <asm/io.h>
> > > > +#include <asm/arch/kirkwood.h>
> > > > +#include <nand.h>
> > > 
> > > I don't see kirkwood.h in upstream, so I guess this 
> should go via an 
> > > arch tree.
> > Hi Jean,
> > Similar to spi driver, can you please pull this driver too?
> > I am posting the new spin for suggested modification
> > 
> please fix the year and I will
Hi Jean
I have already posted v3 for this, but I could not find this in your today's pull request
Ref: http://lists.denx.de/pipermail/u-boot/2009-June/055110.html
Can you please apply this one?

Regards..
Prafulla . .

> 
> Best Regards,
> J.
> 

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Jean-Christophe PLAGNIOL-VILLARD]

On 00:32 Fri 26 Jun     , Prafulla Wadaskar wrote:
>  
> 
> > -----Original Message-----
> > From: Scott Wood [mailto:scottwood at freescale.com] 
> > Sent: Tuesday, June 23, 2009 3:35 AM
> > To: Prafulla Wadaskar
> > Cc: u-boot at lists.denx.de; Ashish Karkare; Prabhanjan Sarnaik; 
> > Ronen Shitrit
> > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add 
> > Marvell Kirkwood NAND driver
> > 
> > On Sun, Jun 14, 2009 at 10:32:47PM +0530, Prafulla Wadaskar wrote:
> > > diff --git a/drivers/mtd/nand/kirkwood_nand.c 
> > > b/drivers/mtd/nand/kirkwood_nand.c
> > > new file mode 100644
> > > index 0000000..9cdbe20
> > > --- /dev/null
> > > +++ b/drivers/mtd/nand/kirkwood_nand.c
> > > @@ -0,0 +1,81 @@
> > > +/*
> > > + * Copyright (C) Marvell International Ltd. and its affiliates
> > 
> > No year?
> > 
> > > +#include <common.h>
> > > +#include <asm/io.h>
> > > +#include <asm/arch/kirkwood.h>
> > > +#include <nand.h>
> > 
> > I don't see kirkwood.h in upstream, so I guess this should go 
> > via an arch tree.
> Hi Jean,
> Similar to spi driver, can you please pull this driver too?
> I am posting the new spin for suggested modification
> 
please fix the year and I will

Best Regards,
J.

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Prafulla Wadaskar]

 

> -----Original Message-----
> From: Scott Wood [mailto:scottwood at freescale.com] 
> Sent: Tuesday, June 23, 2009 3:35 AM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Ashish Karkare; Prabhanjan Sarnaik; 
> Ronen Shitrit
> Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add 
> Marvell Kirkwood NAND driver
> 
> On Sun, Jun 14, 2009 at 10:32:47PM +0530, Prafulla Wadaskar wrote:
> > diff --git a/drivers/mtd/nand/kirkwood_nand.c 
> > b/drivers/mtd/nand/kirkwood_nand.c
> > new file mode 100644
> > index 0000000..9cdbe20
> > --- /dev/null
> > +++ b/drivers/mtd/nand/kirkwood_nand.c
> > @@ -0,0 +1,81 @@
> > +/*
> > + * Copyright (C) Marvell International Ltd. and its affiliates
> 
> No year?
> 
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/kirkwood.h>
> > +#include <nand.h>
> 
> I don't see kirkwood.h in upstream, so I guess this should go 
> via an arch tree.
Hi Jean,
Similar to spi driver, can you please pull this driver too?
I am posting the new spin for suggested modification

Regards..
Prafulla . .
 
> 
> Acked-by: Scott Wood <scottwood@freescale.com>
> 
> -Scott
> 

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Dieter Kiermaier]

Am Dienstag 23 Juni 2009 14:06:46 schrieb Prafulla Wadaskar:
> > -----Original Message-----
> > From: Dieter Kiermaier [mailto:dk-arm-linux at gmx.de]
> > Sent: Tuesday, June 23, 2009 4:53 PM
> > To: Prafulla Wadaskar
> > Cc: Jean-Christophe PLAGNIOL-VILLARD; u-boot at lists.denx.de;
> > Scott Wood; Ashish Karkare; Prabhanjan Sarnaik; Ronen Shitrit
> > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add
> > Marvell Kirkwood NAND driver
> >
> > Am Dienstag 23 Juni 2009 12:38:05 schrieb Prafulla Wadaskar:
> > > > -----Original Message-----
> > > > From: Dieter Kiermaier [mailto:dk-arm-linux at gmx.de]
> > > > Sent: Tuesday, June 23, 2009 2:18 PM
> > > > To: Jean-Christophe PLAGNIOL-VILLARD
> > > > Cc: Prafulla Wadaskar; u-boot at lists.denx.de; Scott Wood; Ashish
> > > > Karkare; Prabhanjan Sarnaik; Ronen Shitrit
> > > > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell
> > > > Kirkwood NAND driver
> > > >
> > > > Am Dienstag 23 Juni 2009 10:35:31 schrieb Jean-Christophe
> > > >
> > > > PLAGNIOL-VILLARD:
> > > > > > > I2C lowest priority (as per need)
> > > > > >
> > > > > > Can I do something to push I2C priority?
> > >
> > > Any way this driver will be arround TWSI controller
> >
> > interface by h/w
> >
> > > Again if you are using different pins then may not be
> >
> > helpful for you
> >
> > I2C by hardware is ok because the pins are not multiplexed
> > with other important functions as its the case for SPI.
> > And also I2C isn't _so_ important to bring up the first board
> > revision :)
> >
> > > > > If the I/O is shared with gpio you can use bitbanging with few
> > > > > hours
> > > >
> > > > I think this would be the best to start - due to the fact that I
> > > > need bitbanging for FPGA flashing, too.
> > >
> > > This is a good Idea, start your development with accessing GPIO
> > > registers directly
> >
> > I start working on gpio stuff now and sending my patches to
> > you. Maybe it is helpful for others, too,
>
> You are most welcomed as one of kirkwood developer for u-boot community
> Post your patches to mailing list so that everyone can review and provide
> you feedback, follow u-boot development guidelines, go through u-boot
> development documentation..
>
> Best of luck :-)
>
Thanks to all - it's time to give something back to the community :)
And sure - I will send the patches as well to the list!

Dieter

> Regards..
> Prafulla . .
>
> > Dieter
> >
> > > Regards..
> > > Prafulla . . .

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Prafulla Wadaskar]

 

> -----Original Message-----
> From: Dieter Kiermaier [mailto:dk-arm-linux at gmx.de] 
> Sent: Tuesday, June 23, 2009 4:53 PM
> To: Prafulla Wadaskar
> Cc: Jean-Christophe PLAGNIOL-VILLARD; u-boot at lists.denx.de; 
> Scott Wood; Ashish Karkare; Prabhanjan Sarnaik; Ronen Shitrit
> Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add 
> Marvell Kirkwood NAND driver
> 
> Am Dienstag 23 Juni 2009 12:38:05 schrieb Prafulla Wadaskar:
> > > -----Original Message-----
> > > From: Dieter Kiermaier [mailto:dk-arm-linux at gmx.de]
> > > Sent: Tuesday, June 23, 2009 2:18 PM
> > > To: Jean-Christophe PLAGNIOL-VILLARD
> > > Cc: Prafulla Wadaskar; u-boot at lists.denx.de; Scott Wood; Ashish 
> > > Karkare; Prabhanjan Sarnaik; Ronen Shitrit
> > > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell 
> > > Kirkwood NAND driver
> > >
> > > Am Dienstag 23 Juni 2009 10:35:31 schrieb Jean-Christophe
> > >
> > > PLAGNIOL-VILLARD:
> > > > > > I2C lowest priority (as per need)
> > > > >
> > > > > Can I do something to push I2C priority?
> >
> > Any way this driver will be arround TWSI controller 
> interface by h/w 
> > Again if you are using different pins then may not be 
> helpful for you
> >
> I2C by hardware is ok because the pins are not multiplexed 
> with other important functions as its the case for SPI.
> And also I2C isn't _so_ important to bring up the first board 
> revision :)
> 
> > > > If the I/O is shared with gpio you can use bitbanging with few 
> > > > hours
> > >
> > > I think this would be the best to start - due to the fact that I 
> > > need bitbanging for FPGA flashing, too.
> >
> > This is a good Idea, start your development with accessing GPIO 
> > registers directly
> I start working on gpio stuff now and sending my patches to 
> you. Maybe it is helpful for others, too,

You are most welcomed as one of kirkwood developer for u-boot community
Post your patches to mailing list so that everyone can review and provide you feedback, follow u-boot development guidelines, go through u-boot development documentation..

Best of luck :-)

Regards..
Prafulla . .

> 
> Dieter
> >
> > Regards..
> > Prafulla . . .
> 
> 
> 

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Stefan Roese]

On Tuesday 23 June 2009 13:23:18 Dieter Kiermaier wrote:
> > > I think this would be the best to start - due to the fact
> > > that I need bitbanging for FPGA flashing, too.
> >
> > This is a good Idea, start your development with accessing GPIO registers
> > directly
>
> I start working on gpio stuff now and sending my patches to you. Maybe it
> is helpful for others, too,

Please send your patches not only to Prafulla but to the list as well.

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Dieter Kiermaier]

Am Dienstag 23 Juni 2009 12:38:05 schrieb Prafulla Wadaskar:
> > -----Original Message-----
> > From: Dieter Kiermaier [mailto:dk-arm-linux at gmx.de]
> > Sent: Tuesday, June 23, 2009 2:18 PM
> > To: Jean-Christophe PLAGNIOL-VILLARD
> > Cc: Prafulla Wadaskar; u-boot at lists.denx.de; Scott Wood;
> > Ashish Karkare; Prabhanjan Sarnaik; Ronen Shitrit
> > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add
> > Marvell Kirkwood NAND driver
> >
> > Am Dienstag 23 Juni 2009 10:35:31 schrieb Jean-Christophe
> >
> > PLAGNIOL-VILLARD:
> > > > > I2C lowest priority (as per need)
> > > >
> > > > Can I do something to push I2C priority?
>
> Any way this driver will be arround TWSI controller interface by h/w
> Again if you are using different pins then may not be helpful for you
>
I2C by hardware is ok because the pins are not multiplexed with other 
important functions as its the case for SPI.
And also I2C isn't _so_ important to bring up the first board revision :)

> > > If the I/O is shared with gpio you can use bitbanging with few hours
> >
> > I think this would be the best to start - due to the fact
> > that I need bitbanging for FPGA flashing, too.
>
> This is a good Idea, start your development with accessing GPIO registers
> directly
I start working on gpio stuff now and sending my patches to you. Maybe it is 
helpful for others, too,

Dieter
>
> Regards..
> Prafulla . . .

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Prafulla Wadaskar]

 

> -----Original Message-----
> From: Dieter Kiermaier [mailto:dk-arm-linux at gmx.de] 
> Sent: Tuesday, June 23, 2009 2:18 PM
> To: Jean-Christophe PLAGNIOL-VILLARD
> Cc: Prafulla Wadaskar; u-boot at lists.denx.de; Scott Wood; 
> Ashish Karkare; Prabhanjan Sarnaik; Ronen Shitrit
> Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add 
> Marvell Kirkwood NAND driver
> 
> Am Dienstag 23 Juni 2009 10:35:31 schrieb Jean-Christophe 
> PLAGNIOL-VILLARD:
> 
> > > > I2C lowest priority (as per need)
> > >
> > > Can I do something to push I2C priority?
Any way this driver will be arround TWSI controller interface by h/w
Again if you are using different pins then may not be helpful for you

> >
> > If the I/O is shared with gpio you can use bitbanging with few hours
> 
> I think this would be the best to start - due to the fact 
> that I need bitbanging for FPGA flashing, too.
This is a good Idea, start your development with accessing GPIO registers directly

Regards..
Prafulla . . .

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Dieter Kiermaier]

Am Dienstag 23 Juni 2009 10:35:31 schrieb Jean-Christophe PLAGNIOL-VILLARD:

> > > I2C lowest priority (as per need)
> >
> > Can I do something to push I2C priority?
>
> If the I/O is shared with gpio you can use bitbanging with few hours

I think this would be the best to start - due to the fact that I need 
bitbanging for FPGA flashing, too.

>
> Best Regards,
> J.

@Prafulla:
in kirkwood/cpu.c
there are 2 functions:
kw_config_gpio()
kw_config_mpp()

If I implement additional functions like
kw_gpio_direction(int gpio, enum direction)
kw_gpio_set(int gpio, int value)
int value kw_gpio_get(int gpio)

If the functions are implemented in cpu.c are they accessible from cmd_xxx.c 
functions?

Would this be ok to get it mainline or should there be an special driver for 
gpio access?

Sorry for my newbie questions :)


Dieter

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Jean-Christophe PLAGNIOL-VILLARD]

> 
> > I2C lowest priority (as per need)
> Can I do something to push I2C priority?
If the I/O is shared with gpio you can use bitbanging with few hours

Best Regards,
J.

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Dieter Kiermaier]

Am Dienstag 23 Juni 2009 10:01:28 schrieb Prafulla Wadaskar:
> > -----Original Message-----
> > From: Dieter Kiermaier [mailto:dk-arm-linux at gmx.de]
> > Sent: Tuesday, June 23, 2009 1:23 PM
> > To: u-boot at lists.denx.de
> > Cc: Prafulla Wadaskar; Scott Wood; Jean-Christophe
> > PLAGNIOL-VILLARD; Ashish Karkare; Prabhanjan Sarnaik; Ronen Shitrit
> > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add
> > Marvell Kirkwood NAND driver
> >
> > Prafulla,
> >
> > > > -----Original Message-----
> > > > From: Scott Wood [mailto:scottwood at freescale.com]
> > > > Sent: Tuesday, June 23, 2009 3:35 AM
> > > > To: Prafulla Wadaskar
> > > > Cc: u-boot at lists.denx.de; Ashish Karkare; Prabhanjan
> >
> > Sarnaik; Ronen
> >
> > > > Shitrit
> > > > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell
> > > > Kirkwood NAND driver
> > > >
> > > > On Sun, Jun 14, 2009 at 10:32:47PM +0530, Prafulla Wadaskar wrote:
> > > > > diff --git a/drivers/mtd/nand/kirkwood_nand.c
> > > > > b/drivers/mtd/nand/kirkwood_nand.c
> > > > > new file mode 100644
> > > > > index 0000000..9cdbe20
> > > > > --- /dev/null
> > > > > +++ b/drivers/mtd/nand/kirkwood_nand.c
> > > > > @@ -0,0 +1,81 @@
> > > > > +/*
> > > > > + * Copyright (C) Marvell International Ltd. and its affiliates
> > > >
> > > > No year?
> > >
> > > I will correct this.
> > >
> > > > > +#include <common.h>
> > > > > +#include <asm/io.h>
> > > > > +#include <asm/arch/kirkwood.h>
> > > > > +#include <nand.h>
> > > >
> > > > I don't see kirkwood.h in upstream, so I guess this
> >
> > should go via an
> >
> > > > arch tree.
> > >
> > > Kirkwood support is available in arm/next, I hope it will be pulled
> > > soon
> > >
> > > :-) Any way this is dependency for this driver but is this blocker?
> > >
> > > I have two options-
> > > 1. remove dependency from this patch or 2. get Basic
> >
> > Kirkwood support
> >
> > > up streamed There are some other drivers in pipeline i.e.
> >
> > i2c,spi,usb
> >
> > > that needs Basic Kirkwood support. So I wish to go for
> >
> > second option
> >
> > > Hi Jean, Can you pls help to resolve this dependency?
> >
> > Could you give me a rough time schedule for these new drivers?
> > Do we talk from a view weeks or months?
>
> SPI is ready to use (available on git.marvell.com)
> USB will be ready latest by ~10thJuly2009
Thats fine - you made me a birthday present :)

> I2C lowest priority (as per need)
Can I do something to push I2C priority?

>
> > I have to start writing my board support functions and it
> > would be helpful to decide on which u-boot I want to start
> > (1.1.4 marvell or marvell git).
>
> Please use marvell git, 1.1.4 is now outdated and not recommended for new
> development

Thats my opinion, too.
Thanks,
Dieter

>
> Regards..
> Prafulla . .
>
> > Thanks,
> > Dieter
> >
> > > Please let me know your feedback on this issue ASAP so that I can
> > > release next spin
> > >
> > > Regards..
> > > Prafulla . .
> > > _______________________________________________
> > > U-Boot mailing list
> > > U-Boot at lists.denx.de
> > > http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Prafulla Wadaskar]

 

> -----Original Message-----
> From: Dieter Kiermaier [mailto:dk-arm-linux at gmx.de] 
> Sent: Tuesday, June 23, 2009 1:23 PM
> To: u-boot at lists.denx.de
> Cc: Prafulla Wadaskar; Scott Wood; Jean-Christophe 
> PLAGNIOL-VILLARD; Ashish Karkare; Prabhanjan Sarnaik; Ronen Shitrit
> Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add 
> Marvell Kirkwood NAND driver
> 
> Prafulla,
> 
> > > -----Original Message-----
> > > From: Scott Wood [mailto:scottwood at freescale.com]
> > > Sent: Tuesday, June 23, 2009 3:35 AM
> > > To: Prafulla Wadaskar
> > > Cc: u-boot at lists.denx.de; Ashish Karkare; Prabhanjan 
> Sarnaik; Ronen 
> > > Shitrit
> > > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell 
> > > Kirkwood NAND driver
> > >
> > > On Sun, Jun 14, 2009 at 10:32:47PM +0530, Prafulla Wadaskar wrote:
> > > > diff --git a/drivers/mtd/nand/kirkwood_nand.c
> > > > b/drivers/mtd/nand/kirkwood_nand.c
> > > > new file mode 100644
> > > > index 0000000..9cdbe20
> > > > --- /dev/null
> > > > +++ b/drivers/mtd/nand/kirkwood_nand.c
> > > > @@ -0,0 +1,81 @@
> > > > +/*
> > > > + * Copyright (C) Marvell International Ltd. and its affiliates
> > >
> > > No year?
> >
> > I will correct this.
> >
> > > > +#include <common.h>
> > > > +#include <asm/io.h>
> > > > +#include <asm/arch/kirkwood.h>
> > > > +#include <nand.h>
> > >
> > > I don't see kirkwood.h in upstream, so I guess this 
> should go via an 
> > > arch tree.
> >
> > Kirkwood support is available in arm/next, I hope it will be pulled 
> > soon
> > :-) Any way this is dependency for this driver but is this blocker?
> >
> > I have two options-
> > 1. remove dependency from this patch or 2. get Basic 
> Kirkwood support 
> > up streamed There are some other drivers in pipeline i.e. 
> i2c,spi,usb 
> > that needs Basic Kirkwood support. So I wish to go for 
> second option 
> > Hi Jean, Can you pls help to resolve this dependency?
> >
> 
> Could you give me a rough time schedule for these new drivers?
> Do we talk from a view weeks or months?
SPI is ready to use (available on git.marvell.com)
USB will be ready latest by ~10thJuly2009
I2C lowest priority (as per need)

> 
> I have to start writing my board support functions and it 
> would be helpful to decide on which u-boot I want to start 
> (1.1.4 marvell or marvell git).
Please use marvell git, 1.1.4 is now outdated and not recommended for new development

Regards..
Prafulla . .
> 
> Thanks,
> Dieter
> 
> > Please let me know your feedback on this issue ASAP so that I can 
> > release next spin
> >
> > Regards..
> > Prafulla . .
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> 
> 
> 

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Dieter Kiermaier]

Prafulla,

> > -----Original Message-----
> > From: Scott Wood [mailto:scottwood at freescale.com]
> > Sent: Tuesday, June 23, 2009 3:35 AM
> > To: Prafulla Wadaskar
> > Cc: u-boot at lists.denx.de; Ashish Karkare; Prabhanjan Sarnaik;
> > Ronen Shitrit
> > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add
> > Marvell Kirkwood NAND driver
> >
> > On Sun, Jun 14, 2009 at 10:32:47PM +0530, Prafulla Wadaskar wrote:
> > > diff --git a/drivers/mtd/nand/kirkwood_nand.c
> > > b/drivers/mtd/nand/kirkwood_nand.c
> > > new file mode 100644
> > > index 0000000..9cdbe20
> > > --- /dev/null
> > > +++ b/drivers/mtd/nand/kirkwood_nand.c
> > > @@ -0,0 +1,81 @@
> > > +/*
> > > + * Copyright (C) Marvell International Ltd. and its affiliates
> >
> > No year?
>
> I will correct this.
>
> > > +#include <common.h>
> > > +#include <asm/io.h>
> > > +#include <asm/arch/kirkwood.h>
> > > +#include <nand.h>
> >
> > I don't see kirkwood.h in upstream, so I guess this should go
> > via an arch tree.
>
> Kirkwood support is available in arm/next, I hope it will be pulled soon
> :-) Any way this is dependency for this driver but is this blocker?
>
> I have two options-
> 1. remove dependency from this patch or
> 2. get Basic Kirkwood support up streamed
> There are some other drivers in pipeline i.e. i2c,spi,usb that needs Basic
> Kirkwood support. So I wish to go for second option Hi Jean,
> Can you pls help to resolve this dependency?
>

Could you give me a rough time schedule for these new drivers?
Do we talk from a view weeks or months?

I have to start writing my board support functions and it would be helpful to 
decide on which u-boot I want to start (1.1.4 marvell or marvell git).

Thanks,
Dieter

> Please let me know your feedback on this issue ASAP so that I can release
> next spin
>
> Regards..
> Prafulla . .
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Jean-Christophe PLAGNIOL-VILLARD]

On 23:08 Mon 22 Jun     , Prafulla Wadaskar wrote:
>  
> 
> > -----Original Message-----
> > From: Scott Wood [mailto:scottwood at freescale.com] 
> > Sent: Tuesday, June 23, 2009 3:35 AM
> > To: Prafulla Wadaskar
> > Cc: u-boot at lists.denx.de; Ashish Karkare; Prabhanjan Sarnaik; 
> > Ronen Shitrit
> > Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add 
> > Marvell Kirkwood NAND driver
> > 
> > On Sun, Jun 14, 2009 at 10:32:47PM +0530, Prafulla Wadaskar wrote:
> > > diff --git a/drivers/mtd/nand/kirkwood_nand.c 
> > > b/drivers/mtd/nand/kirkwood_nand.c
> > > new file mode 100644
> > > index 0000000..9cdbe20
> > > --- /dev/null
> > > +++ b/drivers/mtd/nand/kirkwood_nand.c
> > > @@ -0,0 +1,81 @@
> > > +/*
> > > + * Copyright (C) Marvell International Ltd. and its affiliates
> > 
> > No year?
> I will correct this.
> 
> > 
> > > +#include <common.h>
> > > +#include <asm/io.h>
> > > +#include <asm/arch/kirkwood.h>
> > > +#include <nand.h>
> > 
> > I don't see kirkwood.h in upstream, so I guess this should go 
> > via an arch tree.
> 
> Kirkwood support is available in arm/next, I hope it will be pulled soon :-)
> Any way this is dependency for this driver but is this blocker?
> 
> I have two options-
> 1. remove dependency from this patch or
> 2. get Basic Kirkwood support up streamed
> There are some other drivers in pipeline i.e. i2c,spi,usb that needs Basic Kirkwood support. So I wish to go for second option
> Hi Jean,
> Can you pls help to resolve this dependency?
Wolfgang is in vacancy so we will have to wait until he will came back
the will be present in the arm tree until and then I will send him a pull
request

Best Regards,
J.

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Prafulla Wadaskar]

 

> -----Original Message-----
> From: Scott Wood [mailto:scottwood at freescale.com] 
> Sent: Tuesday, June 23, 2009 3:35 AM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Ashish Karkare; Prabhanjan Sarnaik; 
> Ronen Shitrit
> Subject: Re: [U-Boot] [PATCH v2 1/3][repost] nand: Add 
> Marvell Kirkwood NAND driver
> 
> On Sun, Jun 14, 2009 at 10:32:47PM +0530, Prafulla Wadaskar wrote:
> > diff --git a/drivers/mtd/nand/kirkwood_nand.c 
> > b/drivers/mtd/nand/kirkwood_nand.c
> > new file mode 100644
> > index 0000000..9cdbe20
> > --- /dev/null
> > +++ b/drivers/mtd/nand/kirkwood_nand.c
> > @@ -0,0 +1,81 @@
> > +/*
> > + * Copyright (C) Marvell International Ltd. and its affiliates
> 
> No year?
I will correct this.

> 
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/kirkwood.h>
> > +#include <nand.h>
> 
> I don't see kirkwood.h in upstream, so I guess this should go 
> via an arch tree.

Kirkwood support is available in arm/next, I hope it will be pulled soon :-)
Any way this is dependency for this driver but is this blocker?

I have two options-
1. remove dependency from this patch or
2. get Basic Kirkwood support up streamed
There are some other drivers in pipeline i.e. i2c,spi,usb that needs Basic Kirkwood support. So I wish to go for second option
Hi Jean,
Can you pls help to resolve this dependency?

Please let me know your feedback on this issue ASAP so that I can release next spin

Regards..
Prafulla . .

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Scott Wood]

On Sun, Jun 14, 2009 at 10:32:47PM +0530, Prafulla Wadaskar wrote:
> diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
> new file mode 100644
> index 0000000..9cdbe20
> --- /dev/null
> +++ b/drivers/mtd/nand/kirkwood_nand.c
> @@ -0,0 +1,81 @@
> +/*
> + * Copyright (C) Marvell International Ltd. and its affiliates

No year?

> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/kirkwood.h>
> +#include <nand.h>

I don't see kirkwood.h in upstream, so I guess this should go via an arch
tree.

Acked-by: Scott Wood <scottwood@freescale.com>

-Scott

[U-Boot] [PATCH v2 1/3][repost] nand: Add Marvell Kirkwood NAND driver

[Prafulla Wadaskar]

This patch adds a NAND driver for the Marvell Kirkwood SoC's.

Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Change log:
v2: updated as per feedback for v1 (cosmetic change)

 drivers/mtd/nand/Makefile        |    1 +
 drivers/mtd/nand/kirkwood_nand.c |   81 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 82 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/kirkwood_nand.c

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 471cd6b..766c3f0 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
 COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
 COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c
 COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
new file mode 100644
index 0000000..9cdbe20
--- /dev/null
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/kirkwood.h>
+#include <nand.h>
+
+/* NAND Flash Soc registers */
+struct kwnandf_registers {
+	u32 rd_params;	/* 0x10418 */
+	u32 wr_param;	/* 0x1041c */
+	u8  pad[0x10470 - 0x1041c - 4];
+	u32 ctrl;	/* 0x10470 */
+};
+
+static struct kwnandf_registers *nf_reg =
+	(struct kwnandf_registers *)KW_NANDF_BASE;
+
+/*
+ * hardware specific access to control-lines/bits
+ */
+#define NAND_ACTCEBOOT_BIT		0x02
+
+static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+			      unsigned int ctrl)
+{
+	struct nand_chip *nc = mtd->priv;
+	u32 offs;
+
+	if (cmd == NAND_CMD_NONE)
+		return;
+
+	if (ctrl & NAND_CLE)
+		offs = (1 << 0);	/* Commands with A[1:0] == 01 */
+	else if (ctrl & NAND_ALE)
+		offs = (1 << 1);	/* Addresses with A[1:0] == 10 */
+	else
+		return;
+
+	writeb(cmd, nc->IO_ADDR_W + offs);
+}
+
+void kw_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+	u32 data;
+
+	data = readl(&nf_reg->ctrl);
+	data |= NAND_ACTCEBOOT_BIT;
+	writel(data, &nf_reg->ctrl);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = kw_nand_hwcontrol;
+	nand->chip_delay = 30;
+	nand->select_chip = kw_nand_select_chip;
+	return 0;
+}
-- 
1.5.3.4