* [U-Boot] [PATCH] ppc4xx: Fix "chip_config" command for AMCC Arches
@ 2009-08-17 15:14 Stefan Roese
2009-08-18 7:21 ` Stefan Roese
0 siblings, 1 reply; 2+ messages in thread
From: Stefan Roese @ 2009-08-17 15:14 UTC (permalink / raw)
To: u-boot
This patch fixes the "chip_config" command for I2C bootstrap EEPROM
configuration. First it changes the I2C bootstrap EEPROM address to
0x54 as this is used on Arches (instead of 0x52 on Canyonlands/
Glacier). Additionally, the NAND bootstrap settings are removed
for Arches since Arches doesn't support NAND-booting.
Signed-off-by: Stefan Roese <sr@denx.de>
---
board/amcc/canyonlands/chip_config.c | 34 ++++++++++++++++++----------------
include/configs/canyonlands.h | 4 ++++
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/board/amcc/canyonlands/chip_config.c b/board/amcc/canyonlands/chip_config.c
index e46f4d8..5ad78b8 100644
--- a/board/amcc/canyonlands/chip_config.c
+++ b/board/amcc/canyonlands/chip_config.c
@@ -34,45 +34,46 @@ struct ppc4xx_config ppc4xx_config_val[] = {
}
},
{
- "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100",
{
- 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
- "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100",
{
- 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
- "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88",
{
- 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
- 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
+#if !defined(CONFIG_ARCHES)
{
- "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
{
- 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
{
- "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
{
- 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
{
- "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
{
- 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
- 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
{
@@ -82,6 +83,7 @@ struct ppc4xx_config ppc4xx_config_val[] = {
0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}
},
+#endif
};
int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 217a8ee..3dddccf 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -331,7 +331,11 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* I2C bootstrap EEPROM */
+#if defined(CONFIG_ARCHES)
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
+#else
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
+#endif
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
--
1.6.3.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH] ppc4xx: Fix "chip_config" command for AMCC Arches
2009-08-17 15:14 [U-Boot] [PATCH] ppc4xx: Fix "chip_config" command for AMCC Arches Stefan Roese
@ 2009-08-18 7:21 ` Stefan Roese
0 siblings, 0 replies; 2+ messages in thread
From: Stefan Roese @ 2009-08-18 7:21 UTC (permalink / raw)
To: u-boot
On Monday 17 August 2009 17:14:28 Stefan Roese wrote:
> This patch fixes the "chip_config" command for I2C bootstrap EEPROM
> configuration. First it changes the I2C bootstrap EEPROM address to
> 0x54 as this is used on Arches (instead of 0x52 on Canyonlands/
> Glacier). Additionally, the NAND bootstrap settings are removed
> for Arches since Arches doesn't support NAND-booting.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
Applied to u-boot-ppc4xx. Thanks.
Cheers,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
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