* [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs
@ 2009-12-22 1:49 David VomLehn
2010-01-26 14:26 ` Ralf Baechle
2010-01-30 15:10 ` Maxime Bizon
0 siblings, 2 replies; 6+ messages in thread
From: David VomLehn @ 2009-12-22 1:49 UTC (permalink / raw)
To: linux-mips; +Cc: ralf
The MIPS processor is limited to 64 external interrupt sources. Using a
greater number without IRQ sharing requires reading platform-specific
registers. On such platforms, reading the IntCtl register to determine
which interrupt corresponds to a timer interrupt will not work.
On MIPSR2 systems there is a solution--the TI bit in the Cause register,
specifically indicates that a timer interrupt has occured. This patch
uses that bit to detect interrupts for MIPSR2 processors, which may be
expected to work regardless of how the timer interrupt may be routed
in the hardware.
Signed-off-by: David VomLehn (dvomlehn@cisco.com)
---
arch/mips/include/asm/irq.h | 1 +
arch/mips/include/asm/mipsregs.h | 12 ++++++++++++
arch/mips/kernel/cevt-r4k.c | 2 +-
arch/mips/kernel/traps.c | 6 ++++--
4 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 0696036..dea4aed 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -135,6 +135,7 @@ extern void free_irqno(unsigned int irq);
#define CP0_LEGACY_COMPARE_IRQ 7
extern int cp0_compare_irq;
+extern int cp0_compare_irq_shift;
extern int cp0_perfcount_irq;
#endif /* _ASM_IRQ_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index a581d60..f4ab313 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -406,6 +406,16 @@
#define ST0_XX 0x80000000 /* MIPS IV naming */
/*
+ * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
+ *
+ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
+ */
+#define INTCTLB_IPPCI 26
+#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
+#define INTCTLB_IPTI 29
+#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
+
+/*
* Bitfields and bit numbers in the coprocessor 0 cause register.
*
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
@@ -434,6 +444,8 @@
#define CAUSEF_IV (_ULCAST_(1) << 23)
#define CAUSEB_CE 28
#define CAUSEF_CE (_ULCAST_(3) << 28)
+#define CAUSEB_TI 30
+#define CAUSEF_TI (_ULCAST_(1) << 30)
#define CAUSEB_BD 31
#define CAUSEF_BD (_ULCAST_(1) << 31)
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index b469ad0..0b2450c 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -97,7 +97,7 @@ void mips_event_handler(struct clock_event_device *dev)
*/
static int c0_compare_int_pending(void)
{
- return (read_c0_cause() >> cp0_compare_irq) & 0x100;
+ return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
}
/*
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 308e434..338dfe8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1403,6 +1403,7 @@ extern void flush_tlb_handlers(void);
* Timer interrupt
*/
int cp0_compare_irq;
+int cp0_compare_irq_shift;
/*
* Performance counter IRQ or -1 if shared with timer
@@ -1493,8 +1494,9 @@ void __cpuinit per_cpu_trap_init(void)
* o read IntCtl.IPPCI to determine the performance counter interrupt
*/
if (cpu_has_mips_r2) {
- cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
- cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
+ cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
+ cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
+ cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
} else {
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs
2009-12-22 1:49 [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs David VomLehn
@ 2010-01-26 14:26 ` Ralf Baechle
2010-01-26 18:36 ` David VomLehn
2010-01-30 15:10 ` Maxime Bizon
1 sibling, 1 reply; 6+ messages in thread
From: Ralf Baechle @ 2010-01-26 14:26 UTC (permalink / raw)
To: David VomLehn; +Cc: linux-mips
On Mon, Dec 21, 2009 at 05:49:22PM -0800, David VomLehn wrote:
> The MIPS processor is limited to 64 external interrupt sources. Using a
> greater number without IRQ sharing requires reading platform-specific
> registers. On such platforms, reading the IntCtl register to determine
> which interrupt corresponds to a timer interrupt will not work.
>
> On MIPSR2 systems there is a solution--the TI bit in the Cause register,
> specifically indicates that a timer interrupt has occured. This patch
> uses that bit to detect interrupts for MIPSR2 processors, which may be
> expected to work regardless of how the timer interrupt may be routed
> in the hardware.
I think this isn't relevant for any currently in-tree supported platforms (?)
so I've queued this for 2.6.34.
Thanks,
Ralf
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs
2010-01-26 14:26 ` Ralf Baechle
@ 2010-01-26 18:36 ` David VomLehn
2010-01-26 23:20 ` Ralf Baechle
0 siblings, 1 reply; 6+ messages in thread
From: David VomLehn @ 2010-01-26 18:36 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips
On Tue, Jan 26, 2010 at 08:26:14AM -0600, Ralf Baechle wrote:
> On Mon, Dec 21, 2009 at 05:49:22PM -0800, David VomLehn wrote:
>
> > The MIPS processor is limited to 64 external interrupt sources. Using a
> > greater number without IRQ sharing requires reading platform-specific
> > registers. On such platforms, reading the IntCtl register to determine
> > which interrupt corresponds to a timer interrupt will not work.
> >
> > On MIPSR2 systems there is a solution--the TI bit in the Cause register,
> > specifically indicates that a timer interrupt has occured. This patch
> > uses that bit to detect interrupts for MIPSR2 processors, which may be
> > expected to work regardless of how the timer interrupt may be routed
> > in the hardware.
>
> I think this isn't relevant for any currently in-tree supported platforms (?)
> so I've queued this for 2.6.34.
>
> Thanks,
>
> Ralf
It's required for the PowerTV platform, but the release that includes it
is at your discretion.
--
David VL
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs
2010-01-26 18:36 ` David VomLehn
@ 2010-01-26 23:20 ` Ralf Baechle
0 siblings, 0 replies; 6+ messages in thread
From: Ralf Baechle @ 2010-01-26 23:20 UTC (permalink / raw)
To: David VomLehn; +Cc: linux-mips
On Tue, Jan 26, 2010 at 10:36:06AM -0800, David VomLehn wrote:
> > I think this isn't relevant for any currently in-tree supported platforms (?)
> > so I've queued this for 2.6.34.
> >
> > Thanks,
> >
> > Ralf
>
> It's required for the PowerTV platform, but the release that includes it
> is at your discretion.
Should have guessed so. Will pull it into 2.6.33 then.
Ralf
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs
2009-12-22 1:49 [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs David VomLehn
2010-01-26 14:26 ` Ralf Baechle
@ 2010-01-30 15:10 ` Maxime Bizon
2010-02-01 8:47 ` Wu Zhangjin
1 sibling, 1 reply; 6+ messages in thread
From: Maxime Bizon @ 2010-01-30 15:10 UTC (permalink / raw)
To: David VomLehn; +Cc: linux-mips, ralf
On Mon, 2009-12-21 at 17:49 -0800, David VomLehn wrote:
Hi,
> if (cpu_has_mips_r2) {
> - cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
> - cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
> + cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
> + cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
> + cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
This patch breaks at least bcm63xx, because cp0_compare_irq_shift is not
initialized when cpu_has_mips_r2 is false.
Regards,
--
Maxime
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs
2010-01-30 15:10 ` Maxime Bizon
@ 2010-02-01 8:47 ` Wu Zhangjin
0 siblings, 0 replies; 6+ messages in thread
From: Wu Zhangjin @ 2010-02-01 8:47 UTC (permalink / raw)
To: mbizon; +Cc: David VomLehn, linux-mips, ralf
On Sat, 2010-01-30 at 16:10 +0100, Maxime Bizon wrote:
> On Mon, 2009-12-21 at 17:49 -0800, David VomLehn wrote:
>
> Hi,
>
> > if (cpu_has_mips_r2) {
> > - cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
> > - cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
> > + cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
> > + cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
> > + cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
>
> This patch breaks at least bcm63xx, because cp0_compare_irq_shift is not
> initialized when cpu_has_mips_r2 is false.
Yes, that patch have broken the CEVT_R4K support in the archs whose
cpu_has_mips_r2 is false.
I will send a piece of patch to fix it.
Thanks & Regards,
Wu Zhangjin
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2010-02-01 8:58 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-12-22 1:49 [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs David VomLehn
2010-01-26 14:26 ` Ralf Baechle
2010-01-26 18:36 ` David VomLehn
2010-01-26 23:20 ` Ralf Baechle
2010-01-30 15:10 ` Maxime Bizon
2010-02-01 8:47 ` Wu Zhangjin
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