* [U-Boot] [PATCH] add new board pm9g45
@ 2010-03-16 12:57 Asen Dimov
2010-03-16 19:00 ` Wolfgang Denk
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Asen Dimov @ 2010-03-16 12:57 UTC (permalink / raw)
To: u-boot
Hello everyone,
here is the new board PM9G45 from Ronetix GmbH,
based on at91sam9g45 MCU. It has 128MB DDR2 SDRAM, 256MB NAND,
could be with or without DataFlash.
The board is made as SODIMM200 module.
For more info www.ronatix.at or info at ronetix.at.
Regards,
Asen
Signed-off-by: Asen Dimov <dimov@ronetix.at>
---
MAKEALL | 1 +
Makefile | 4 +
board/ronetix/pm9g45/Makefile | 54 +++
.../at91sam9m10g45ek => ronetix/pm9g45}/config.mk | 0
board/ronetix/pm9g45/pm9g45.c | 365 ++++++++++++++++++++
include/configs/pm9g45.h | 246 +++++++++++++
6 files changed, 670 insertions(+), 0 deletions(-)
create mode 100644 board/ronetix/pm9g45/Makefile
copy board/{atmel/at91sam9m10g45ek => ronetix/pm9g45}/config.mk (100%)
create mode 100644 board/ronetix/pm9g45/pm9g45.c
create mode 100644 include/configs/pm9g45.h
diff --git a/MAKEALL b/MAKEALL
index beacb5f..ad591d5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -673,6 +673,7 @@ LIST_at91=" \
otc570 \
pm9261 \
pm9263 \
+ pm9g45 \
SBC35_A9G20 \
TNY_A9260 \
TNY_A9G20 \
diff --git a/Makefile b/Makefile
index d801e25..438580a 100644
--- a/Makefile
+++ b/Makefile
@@ -2882,6 +2882,10 @@ otc570_config : unconfig
pm9263_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
+pm9g45_config : unconfig
+ @mkdir -p $(obj)include
+ @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
+
SBC35_A9G20_NANDFLASH_config \
SBC35_A9G20_EEPROM_config \
SBC35_A9G20_config : unconfig
diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile
new file mode 100644
index 0000000..dd5b02e
--- /dev/null
+++ b/board/ronetix/pm9g45/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += pm9g45.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atmel/at91sam9m10g45ek/config.mk b/board/ronetix/pm9g45/config.mk
similarity index 100%
copy from board/atmel/at91sam9m10g45ek/config.mk
copy to board/ronetix/pm9g45/config.mk
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
new file mode 100644
index 0000000..d11f40f
--- /dev/null
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -0,0 +1,365 @@
+/*
+ * (C) Copyright 2005-2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+#endif
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_HAS_DATAFLASH
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "DataFlash"},
+};
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static void pm9g45_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_DBW_8 |
+ AT91_SMC_TDF_(3));
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
+
+#ifdef CONFIG_SYS_NAND_READY_PIN
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+#endif
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9g45_macb_hw_init(void)
+{
+ unsigned long rstc;
+
+ /*
+ * PD2 enables the 50MHz oscillator for Ethernet PHY
+ * 1 - enable
+ * 0 - disable
+ */
+ at91_set_gpio_output(AT91_PIN_PD2, 1);
+ at91_set_gpio_value(AT91_PIN_PD2, 1); /* 1- enable, 0 - disable */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA15) => PHY normal mode (not Test mode)
+ * ERX0 (PA12) => PHY ADDR0
+ * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA15),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+ writel(pin_to_mask(AT91_PIN_PA12) |
+ pin_to_mask(AT91_PIN_PA13),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA15),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+ writel(pin_to_mask(AT91_PIN_PA12) |
+ pin_to_mask(AT91_PIN_PA13),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+/*
+ * LCD name TX09D50VM1CCA
+ */
+vidinfo_t panel_info = {
+ vl_col: 240,
+ vl_row: 320,
+ vl_clk: 4965000,
+ vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
+ ATMEL_LCDC_INVFRAME_NORMAL,
+ vl_bpix: 3,
+ vl_tft: 1,
+ vl_hsync_len: 5,
+ vl_left_margin: 1,
+ vl_right_margin:33,
+ vl_vsync_len: 1,
+ vl_upper_margin:1,
+ vl_lower_margin:0,
+ mmio: AT91SAM9G45_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+ at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
+}
+
+static void pm9g45_lcd_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
+ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
+ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
+ at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
+ at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
+
+ at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
+ at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
+ at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
+ at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
+ at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
+ at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
+ at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
+ at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
+ at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
+ at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
+ at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
+ at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
+ at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
+ at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
+ at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
+ at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
+ at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
+ at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
+ at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
+ at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
+ at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
+ at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
+ at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
+ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
+
+ gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size, dataflash_size;
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2010 Ronetix GmbH\n");
+ lcd_printf ("support at ronetix.at\n");
+ lcd_printf ("%s CPU at %s MHz\n",
+ CONFIG_SYS_AT91_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+
+#ifdef CONFIG_HAS_DATAFLASH
+ dataflash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
+ dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
+ dataflash_info[i].Device.pages_size;
+#endif
+
+ lcd_printf ("%ld MB DDR2 SDRAM\n%ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20);
+
+#ifdef CONFIG_HAS_DATAFLASH
+ lcd_printf ("%ld MB DataFlash\n",
+ dataflash_size >> 20);
+#endif
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ at91_sys_write(AT91_PMC_PCER,
+ (1 << AT91SAM9G45_ID_PIOA) |
+ (1 << AT91SAM9G45_ID_PIOB) |
+ (1 << AT91SAM9G45_ID_PIOC) |
+ (1 << AT91SAM9G45_ID_PIODE));
+
+ /* arch number of AT91SAM9M10G45EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ pm9g45_nand_hw_init();
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+ pm9g45_macb_hw_init();
+#endif
+
+#ifdef CONFIG_LCD
+ pm9g45_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x01);
+#endif
+ return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch(slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 0);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 0);
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch(slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 1);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 1);
+ break;
+ }
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
new file mode 100644
index 0000000..b8300b9
--- /dev/null
+++ b/include/configs/pm9g45.h
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2005-2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the PM9G45 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AT91_LEGACY
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
+#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO 1
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+#define CONFIG_ATMEL_SPI 1
+
+#define CONFIG_SYS_USE_NANDFLASH 1
+
+/*
+ * Hardware on board which could be removed
+ */
+#undef CONFIG_HAS_DATAFLASH
+
+/* LCD */
+#define CONFIG_LCD 1
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_LCD_LOGO 1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO 1
+#define CONFIG_LCD_INFO_BELOW_LOGO 1
+#define CONFIG_SYS_WHITE_ON_BLACK 1
+#define CONFIG_ATMEL_LCD 1
+#define CONFIG_ATMEL_LCD_RGB565 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
+#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+#define CONFIG_CMD_JFFS2 1
+#define CONFIG_JFFS2_CMDLINE 1
+#define CONFIG_JFFS2_NAND 1
+#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
+#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x70000000
+#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+
+/* DataFlash */
+#ifdef CONFIG_ATMEL_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_SPI_FLASH_ATMEL 1
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+#endif
+
+/* NOR flash, not available */
+#define CONFIG_SYS_NO_FLASH 1
+#undef CONFIG_CMD_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MAX_CHIPS 1
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE*/
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
+
+#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400)
+#define CONFIG_ENV_OFFSET 0x4200
+#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x4200
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=atmel_nand:-(root) "\
+ "rw rootfstype=jffs2"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
+#define CONFIG_BOOTARGS "fbcon=rotate:3 " \
+ "root=/dev/mtdblock4 " \
+ "mtdparts=atmel_nand:128k(bootstrap)ro," \
+ "256k(uboot)ro,1664k(env)," \
+ "2M(linux)ro,-(root) rw " \
+ "rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
--
1.5.5.6
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] add new board pm9g45
2010-03-16 12:57 [U-Boot] [PATCH] add new board pm9g45 Asen Dimov
@ 2010-03-16 19:00 ` Wolfgang Denk
2010-03-17 20:06 ` RONETIX - Asen Dimov
2010-03-18 6:41 ` Maxim Podbereznyi
2010-03-20 19:10 ` Tom
2 siblings, 1 reply; 10+ messages in thread
From: Wolfgang Denk @ 2010-03-16 19:00 UTC (permalink / raw)
To: u-boot
Dear Asen Dimov,
In message <1268744233-2497-1-git-send-email-dimov@ronetix.at> you wrote:
> Hello everyone,
>
> here is the new board PM9G45 from Ronetix GmbH,
> based on at91sam9g45 MCU. It has 128MB DDR2 SDRAM, 256MB NAND,
> could be with or without DataFlash.
> The board is made as SODIMM200 module.
> For more info www.ronatix.at or info at ronetix.at.
>
> Regards,
> Asen
You sent a similar patch les than one hour before this one.
None of your patches includes any indication what they are - if you
are resubmitting a patch, you are suppoosed to mark it as "[PATCH
v2]" or "[PATCH v3]" or similar in the Subject: line.
> Signed-off-by: Asen Dimov <dimov@ronetix.at>
> ---
> MAKEALL | 1 +
...
Also, you are supposed to include a descripotion of what has been
changed compared to the previous version(s) of the patch here, below
the "---" line.
At fist glance, the two patches look identical to me. Do you expect
me to scan through some 1500+ lines of patches to check which lines
or characters might have changed?
Also, a commit message including "Hello everyone," and "Regards, Asen"
is not exactly useful. Please omit this in patches.
> ---
> MAKEALL | 1 +
> Makefile | 4 +
> board/ronetix/pm9g45/Makefile | 54 +++
> .../at91sam9m10g45ek => ronetix/pm9g45}/config.mk | 0
> board/ronetix/pm9g45/pm9g45.c | 365 ++++++++++++++++++++
> include/configs/pm9g45.h | 246 +++++++++++++
> 6 files changed, 670 insertions(+), 0 deletions(-)
> create mode 100644 board/ronetix/pm9g45/Makefile
> copy board/{atmel/at91sam9m10g45ek => ronetix/pm9g45}/config.mk (100%)
> create mode 100644 board/ronetix/pm9g45/pm9g45.c
> create mode 100644 include/configs/pm9g45.h
MAINTAINERS entry is missing.
> diff --git a/board/atmel/at91sam9m10g45ek/config.mk b/board/ronetix/pm9g45/config.mk
> similarity index 100%
> copy from board/atmel/at91sam9m10g45ek/config.mk
> copy to board/ronetix/pm9g45/config.mk
> diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
> new file mode 100644
> index 0000000..d11f40f
> --- /dev/null
> +++ b/board/ronetix/pm9g45/pm9g45.c
> @@ -0,0 +1,365 @@
> +/*
> + * (C) Copyright 2005-2010
> + * Ilko Iliev <iliev@ronetix.at>
> + * Asen Dimov <dimov@ronetix.at>
> + * Ronetix GmbH <www.ronetix.at>
2005- ? Is this really correct?
> + writel(pin_to_mask(AT91_PIN_PA15),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
> + writel(pin_to_mask(AT91_PIN_PA12) |
> + pin_to_mask(AT91_PIN_PA13),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
> +
> + /* Re-enable pull-up */
> + writel(pin_to_mask(AT91_PIN_PA15),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
> + writel(pin_to_mask(AT91_PIN_PA12) |
> + pin_to_mask(AT91_PIN_PA13),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
The use of base address plus offset is deprecated. Please use C
strucxts to desribe the register layout.
> +#ifdef CONFIG_LCD
> +/*
> + * LCD name TX09D50VM1CCA
> + */
> +vidinfo_t panel_info = {
> + vl_col: 240,
> + vl_row: 320,
> + vl_clk: 4965000,
> + vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
> + ATMEL_LCDC_INVFRAME_NORMAL,
> + vl_bpix: 3,
> + vl_tft: 1,
> + vl_hsync_len: 5,
> + vl_left_margin: 1,
> + vl_right_margin:33,
> + vl_vsync_len: 1,
> + vl_upper_margin:1,
> + vl_lower_margin:0,
> + mmio: AT91SAM9G45_LCDC_BASE,
> +};
This information should not be board-specific. The panel information
is generic and should moved to a separate header file that is not part
of the board code.
...
> +}
> +
> +#ifdef CONFIG_LCD_INFO
> +#include <nand.h>
> +#include <version.h>
Please move #includes to the top of the file.
> +#ifdef CONFIG_HAS_DATAFLASH
> + dataflash_size = 0;
> + for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
> + dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
> + dataflash_info[i].Device.pages_size;
> +#endif
Line too long. Please check and fix globally. Also, multiline
statements require curly braces.
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> + switch(slave->cs) {
> + case 1:
> + at91_set_gpio_output(AT91_PIN_PB18, 0);
> + break;
> + case 0:
> + default:
> + at91_set_gpio_output(AT91_PIN_PB3, 0);
> + break;
> + }
> +}
> +
> +void spi_cs_deactivate(struct spi_slave *slave)
> +{
> + switch(slave->cs) {
> + case 1:
> + at91_set_gpio_output(AT91_PIN_PB18, 1);
> + break;
> + case 0:
> + default:
> + at91_set_gpio_output(AT91_PIN_PB3, 1);
> + break;
> + }
> +}
Incorrect indentation. Please fix globally.
...
> +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
^^^^^^^^^^^^^^^^^^^^^^^^
...
> +#define CONFIG_AT91_GPIO 1
> +#define CONFIG_ATMEL_USART 1
> +#undef CONFIG_USART0
^^^^^^^^^^^^^^^^^^^^^^^
> +#undef CONFIG_USART1
^^^^^^^^^^^^^^^^^^^^^^^
> +#undef CONFIG_USART2
^^^^^^^^^^^^^^^^^^^^^^^
Please do not undef what is not #defined anyway.
> +#include <config_cmd_default.h>
> +#undef CONFIG_CMD_BDI
> +#undef CONFIG_CMD_FPGA
> +#undef CONFIG_CMD_IMI
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_AUTOSCRIPT
AUTOSCRIP has been deprecated long ago.
Is there any good reason for disabling pretty useful commands like
bdinfo, iminfo or imls ? It does not appear to me as if the memory
footprint was critical to you.
> +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
> +#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
Again: lines too long. Please fix everywhere.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Brontosaurus Principle: Organizations can grow faster than their
brains can manage them in relation to their environment and to their
own physiology: when this occurs, they are an endangered species.
- Thomas K. Connellan
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] add new board pm9g45
2010-03-16 19:00 ` Wolfgang Denk
@ 2010-03-17 20:06 ` RONETIX - Asen Dimov
2010-03-17 23:00 ` Wolfgang Denk
0 siblings, 1 reply; 10+ messages in thread
From: RONETIX - Asen Dimov @ 2010-03-17 20:06 UTC (permalink / raw)
To: u-boot
Hello Wolfgang,
in the message <20100316190012.84CA75086C@gemini.denx.de> form
16.03.2010 at 09:00 PM
>> +#ifdef CONFIG_LCD
>> +/*
>> + * LCD name TX09D50VM1CCA
>> + */
>> +vidinfo_t panel_info = {
>> + vl_col: 240,
>> + vl_row: 320,
>> + vl_clk: 4965000,
>> + vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
>> + ATMEL_LCDC_INVFRAME_NORMAL,
>> + vl_bpix: 3,
>> + vl_tft: 1,
>> + vl_hsync_len: 5,
>> + vl_left_margin: 1,
>> + vl_right_margin:33,
>> + vl_vsync_len: 1,
>> + vl_upper_margin:1,
>> + vl_lower_margin:0,
>> + mmio: AT91SAM9G45_LCDC_BASE,
>> +};
>>
>
> This information should not be board-specific. The panel information
> is generic and should moved to a separate header file that is not part
> of the board code.
>
>
>
In the boards (at91sam9263ek and at91sam9m10g45ek, and some more
at91sam9 based boards) I am looking at, the panel_info is in the board
specific code.
There are some lcd.c files with panel_info structures:
drivers/video/mx3fb.c, cpu/pxa/pxafb.c and cpu/mpc8xx/lcd.c .
Where should be the proper place for panel_info which is somehow
architecture dependent?
Regards,
Asen
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] add new board pm9g45
2010-03-17 20:06 ` RONETIX - Asen Dimov
@ 2010-03-17 23:00 ` Wolfgang Denk
0 siblings, 0 replies; 10+ messages in thread
From: Wolfgang Denk @ 2010-03-17 23:00 UTC (permalink / raw)
To: u-boot
Dear RONETIX - Asen Dimov,
In message <4BA1363B.7010002@ronetix.at> you wrote:
>
> > This information should not be board-specific. The panel information
> > is generic and should moved to a separate header file that is not part
> > of the board code.
> >
> >
> In the boards (at91sam9263ek and at91sam9m10g45ek, and some more
> at91sam9 based boards) I am looking at, the panel_info is in the board
> specific code.
Indeed. Patches to clean this up are welcome.
> There are some lcd.c files with panel_info structures:
> drivers/video/mx3fb.c, cpu/pxa/pxafb.c and cpu/mpc8xx/lcd.c .
>
> Where should be the proper place for panel_info which is somehow
> architecture dependent?
I'm not an expert in this area. In Linux there has been discussion to
put this type of information into the device tree. Either in the form
of (new, to be defined) specific bindings, or as EDID data.
I wonder if we could / should do something similar here?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Man is the best computer we can put aboard a spacecraft ... and the
only one that can be mass produced with unskilled labor.
-- Wernher von Braun
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] add new board pm9g45
2010-03-16 12:57 [U-Boot] [PATCH] add new board pm9g45 Asen Dimov
2010-03-16 19:00 ` Wolfgang Denk
@ 2010-03-18 6:41 ` Maxim Podbereznyi
2010-03-21 18:57 ` Wolfgang Denk
2010-03-20 19:10 ` Tom
2 siblings, 1 reply; 10+ messages in thread
From: Maxim Podbereznyi @ 2010-03-18 6:41 UTC (permalink / raw)
To: u-boot
Russian company MENTOREL released at91sam9G45 based SODIMM module a couple
of months ago. Module is named GEM45 and I guess it is more integrated as it
has the following features:
- 128M DDR2 main memory
- 64M DDR2 second memory for frame buffer or smt else
- 128/256M NAND
- 64/128M NOR (option)
- 4/8M Dataflash (option)
- Ethernet 10/100 Mbps
- Globally unique MAC-address compliant with EUI-48? and EUI-64?
- many usual I/F: USB, LCD, SPI, I2C, AC97 etc
2010/3/16 Asen Dimov <dimov@ronetix.at>
> Hello everyone,
>
> here is the new board PM9G45 from Ronetix GmbH,
> based on at91sam9g45 MCU. It has 128MB DDR2 SDRAM, 256MB NAND,
> could be with or without DataFlash.
> The board is made as SODIMM200 module.
> For more info www.ronatix.at or info at ronetix.at.
>
> Regards,
> Asen
>
> Signed-off-by: Asen Dimov <dimov@ronetix.at>
> ---
> MAKEALL | 1 +
> Makefile | 4 +
> board/ronetix/pm9g45/Makefile | 54 +++
> .../at91sam9m10g45ek => ronetix/pm9g45}/config.mk | 0
> board/ronetix/pm9g45/pm9g45.c | 365
> ++++++++++++++++++++
> include/configs/pm9g45.h | 246 +++++++++++++
> 6 files changed, 670 insertions(+), 0 deletions(-)
> create mode 100644 board/ronetix/pm9g45/Makefile
> copy board/{atmel/at91sam9m10g45ek => ronetix/pm9g45}/config.mk (100%)
> create mode 100644 board/ronetix/pm9g45/pm9g45.c
> create mode 100644 include/configs/pm9g45.h
>
> diff --git a/MAKEALL b/MAKEALL
> index beacb5f..ad591d5 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -673,6 +673,7 @@ LIST_at91=" \
> otc570 \
> pm9261 \
> pm9263 \
> + pm9g45 \
> SBC35_A9G20 \
> TNY_A9260 \
> TNY_A9G20 \
> diff --git a/Makefile b/Makefile
> index d801e25..438580a 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -2882,6 +2882,10 @@ otc570_config : unconfig
> pm9263_config : unconfig
> @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
>
> +pm9g45_config : unconfig
> + @mkdir -p $(obj)include
> + @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
> +
> SBC35_A9G20_NANDFLASH_config \
> SBC35_A9G20_EEPROM_config \
> SBC35_A9G20_config : unconfig
> diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile
> new file mode 100644
> index 0000000..dd5b02e
> --- /dev/null
> +++ b/board/ronetix/pm9g45/Makefile
> @@ -0,0 +1,54 @@
> +#
> +# (C) Copyright 2003-2008
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# (C) Copyright 2008
> +# Stelian Pop <stelian.pop@leadtechdesign.com>
> +# Lead Tech Design <www.leadtechdesign.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).a
> +
> +COBJS-y += pm9g45.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS-y))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
> +
> +clean:
> + rm -f $(SOBJS) $(OBJS)
> +
> +distclean: clean
> + rm -f $(LIB) core *.bak $(obj).depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/atmel/at91sam9m10g45ek/config.mkb/board/ronetix/pm9g45/
> config.mk
> similarity index 100%
> copy from board/atmel/at91sam9m10g45ek/config.mk
> copy to board/ronetix/pm9g45/config.mk
> diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
> new file mode 100644
> index 0000000..d11f40f
> --- /dev/null
> +++ b/board/ronetix/pm9g45/pm9g45.c
> @@ -0,0 +1,365 @@
> +/*
> + * (C) Copyright 2005-2010
> + * Ilko Iliev <iliev@ronetix.at>
> + * Asen Dimov <dimov@ronetix.at>
> + * Ronetix GmbH <www.ronetix.at>
> + *
> + * (C) Copyright 2007-2008
> + * Stelian Pop <stelian.pop@leadtechdesign.com>
> + * Lead Tech Design <www.leadtechdesign.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/sizes.h>
> +#include <asm/arch/at91sam9g45.h>
> +#include <asm/arch/at91sam9_matrix.h>
> +#include <asm/arch/at91sam9_smc.h>
> +#include <asm/arch/at91_common.h>
> +#include <asm/arch/at91_pmc.h>
> +#include <asm/arch/at91_rstc.h>
> +#include <asm/arch/clk.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/io.h>
> +#include <asm/arch/hardware.h>
> +#include <lcd.h>
> +#include <atmel_lcdc.h>
> +#ifdef CONFIG_HAS_DATAFLASH
> +#include <dataflash.h>
> +#endif
> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
> +#include <net.h>
> +#endif
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> ------------------------------------------------------------------------- */
> +/*
> + * Miscelaneous platform dependent initialisations
> + */
> +
> +#ifdef CONFIG_HAS_DATAFLASH
> +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
> +
> +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
> + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress,
> CS */
> +};
> +
> +/*define the area offsets*/
> +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
> + {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "DataFlash"},
> +};
> +#endif
> +
> +#ifdef CONFIG_CMD_NAND
> +static void pm9g45_nand_hw_init(void)
> +{
> + unsigned long csa;
> +
> + /* Enable CS3 */
> + csa = at91_sys_read(AT91_MATRIX_EBICSA);
> + at91_sys_write(AT91_MATRIX_EBICSA,
> + csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
> +
> + /* Configure SMC CS3 for NAND/SmartMedia */
> + at91_sys_write(AT91_SMC_SETUP(3),
> + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
> + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
> + at91_sys_write(AT91_SMC_PULSE(3),
> + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
> + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
> + at91_sys_write(AT91_SMC_CYCLE(3),
> + AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
> + at91_sys_write(AT91_SMC_MODE(3),
> + AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
> + AT91_SMC_EXNWMODE_DISABLE |
> + AT91_SMC_DBW_8 |
> + AT91_SMC_TDF_(3));
> +
> + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
> +
> +#ifdef CONFIG_SYS_NAND_READY_PIN
> + /* Configure RDY/BSY */
> + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
> +#endif
> +
> + /* Enable NandFlash */
> + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
> +}
> +#endif
> +
> +#ifdef CONFIG_MACB
> +static void pm9g45_macb_hw_init(void)
> +{
> + unsigned long rstc;
> +
> + /*
> + * PD2 enables the 50MHz oscillator for Ethernet PHY
> + * 1 - enable
> + * 0 - disable
> + */
> + at91_set_gpio_output(AT91_PIN_PD2, 1);
> + at91_set_gpio_value(AT91_PIN_PD2, 1); /* 1- enable, 0 - disable */
> +
> + /* Enable clock */
> + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
> +
> + /*
> + * Disable pull-up on:
> + * RXDV (PA15) => PHY normal mode (not Test mode)
> + * ERX0 (PA12) => PHY ADDR0
> + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
> + *
> + * PHY has internal pull-down
> + */
> + writel(pin_to_mask(AT91_PIN_PA15),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
> + writel(pin_to_mask(AT91_PIN_PA12) |
> + pin_to_mask(AT91_PIN_PA13),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
> +
> + /* Re-enable pull-up */
> + writel(pin_to_mask(AT91_PIN_PA15),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
> + writel(pin_to_mask(AT91_PIN_PA12) |
> + pin_to_mask(AT91_PIN_PA13),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
> +
> + at91_macb_hw_init();
> +}
> +#endif
> +
> +#ifdef CONFIG_LCD
> +/*
> + * LCD name TX09D50VM1CCA
> + */
> +vidinfo_t panel_info = {
> + vl_col: 240,
> + vl_row: 320,
> + vl_clk: 4965000,
> + vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
> + ATMEL_LCDC_INVFRAME_NORMAL,
> + vl_bpix: 3,
> + vl_tft: 1,
> + vl_hsync_len: 5,
> + vl_left_margin: 1,
> + vl_right_margin:33,
> + vl_vsync_len: 1,
> + vl_upper_margin:1,
> + vl_lower_margin:0,
> + mmio: AT91SAM9G45_LCDC_BASE,
> +};
> +
> +void lcd_enable(void)
> +{
> + at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
> +}
> +
> +void lcd_disable(void)
> +{
> + at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
> +}
> +
> +static void pm9g45_lcd_hw_init(void)
> +{
> + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
> + at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
> + at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
> + at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
> + at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
> +
> + at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
> + at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
> + at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
> + at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
> + at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
> + at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
> + at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
> + at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
> + at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
> + at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
> + at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
> + at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
> + at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
> + at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
> + at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
> + at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
> + at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
> + at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
> + at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
> + at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
> + at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
> + at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
> + at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
> + at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
> +
> + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
> +
> + gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
> +}
> +
> +#ifdef CONFIG_LCD_INFO
> +#include <nand.h>
> +#include <version.h>
> +
> +void lcd_show_board_info(void)
> +{
> + ulong dram_size, nand_size, dataflash_size;
> + int i;
> + char temp[32];
> +
> + lcd_printf ("%s\n", U_BOOT_VERSION);
> + lcd_printf ("(C) 2010 Ronetix GmbH\n");
> + lcd_printf ("support at ronetix.at\n");
> + lcd_printf ("%s CPU at %s MHz\n",
> + CONFIG_SYS_AT91_CPU_NAME,
> + strmhz(temp, get_cpu_clk_rate()));
> +
> + dram_size = 0;
> + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
> + dram_size += gd->bd->bi_dram[i].size;
> +
> + nand_size = 0;
> + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
> + nand_size += nand_info[i].size;
> +
> +#ifdef CONFIG_HAS_DATAFLASH
> + dataflash_size = 0;
> + for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
> + dataflash_size += (unsigned int)
> dataflash_info[i].Device.pages_number *
> + dataflash_info[i].Device.pages_size;
> +#endif
> +
> + lcd_printf ("%ld MB DDR2 SDRAM\n%ld MB NAND\n",
> + dram_size >> 20,
> + nand_size >> 20);
> +
> +#ifdef CONFIG_HAS_DATAFLASH
> + lcd_printf ("%ld MB DataFlash\n",
> + dataflash_size >> 20);
> +#endif
> +}
> +#endif /* CONFIG_LCD_INFO */
> +#endif
> +
> +int board_init(void)
> +{
> + /* Enable Ctrlc */
> + console_init_f();
> +
> + at91_sys_write(AT91_PMC_PCER,
> + (1 << AT91SAM9G45_ID_PIOA) |
> + (1 << AT91SAM9G45_ID_PIOB) |
> + (1 << AT91SAM9G45_ID_PIOC) |
> + (1 << AT91SAM9G45_ID_PIODE));
> +
> + /* arch number of AT91SAM9M10G45EK-Board */
> + gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
> + /* adress of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + at91_serial_hw_init();
> +#ifdef CONFIG_CMD_NAND
> + pm9g45_nand_hw_init();
> +#endif
> +
> +#ifdef CONFIG_HAS_DATAFLASH
> + at91_spi0_hw_init(1 << 0);
> +#endif
> +
> +#ifdef CONFIG_ATMEL_SPI
> + at91_spi0_hw_init(1 << 4);
> +#endif
> +
> +#ifdef CONFIG_MACB
> + pm9g45_macb_hw_init();
> +#endif
> +
> +#ifdef CONFIG_LCD
> + pm9g45_lcd_hw_init();
> +#endif
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM;
> + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
> + return 0;
> +}
> +
> +#ifdef CONFIG_RESET_PHY_R
> +void reset_phy(void)
> +{
> +#ifdef CONFIG_MACB
> + /*
> + * Initialize ethernet HW addr prior to starting Linux,
> + * needed for nfsroot
> + */
> + eth_init(gd->bd);
> +#endif
> +}
> +#endif
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = 0;
> +#ifdef CONFIG_MACB
> + rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x01);
> +#endif
> + return rc;
> +}
> +
> +/* SPI chip select control */
> +#ifdef CONFIG_ATMEL_SPI
> +#include <spi.h>
> +
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> + return bus == 0 && cs < 2;
> +}
> +
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> + switch(slave->cs) {
> + case 1:
> + at91_set_gpio_output(AT91_PIN_PB18, 0);
> + break;
> + case 0:
> + default:
> + at91_set_gpio_output(AT91_PIN_PB3, 0);
> + break;
> + }
> +}
> +
> +void spi_cs_deactivate(struct spi_slave *slave)
> +{
> + switch(slave->cs) {
> + case 1:
> + at91_set_gpio_output(AT91_PIN_PB18, 1);
> + break;
> + case 0:
> + default:
> + at91_set_gpio_output(AT91_PIN_PB3, 1);
> + break;
> + }
> +}
> +#endif /* CONFIG_ATMEL_SPI */
> diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
> new file mode 100644
> index 0000000..b8300b9
> --- /dev/null
> +++ b/include/configs/pm9g45.h
> @@ -0,0 +1,246 @@
> +/*
> + * (C) Copyright 2005-2010
> + * Ilko Iliev <iliev@ronetix.at>
> + * Asen Dimov <dimov@ronetix.at>
> + * Ronetix GmbH <www.ronetix.at>
> + *
> + * (C) Copyright 2007-2008
> + * Stelian Pop <stelian.pop@leadtechdesign.com>
> + * Lead Tech Design <www.leadtechdesign.com>
> + *
> + * Configuation settings for the PM9G45 board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_AT91_LEGACY
> +
> +/* ARM asynchronous clock */
> +#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz
> crystal */
> +#define CONFIG_SYS_HZ 1000
> +
> +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
> +#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
> +#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/
> +#define CONFIG_ARCH_CPU_INIT
> +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
> +
> +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS 1
> +#define CONFIG_INITRD_TAG 1
> +
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_SKIP_RELOCATE_UBOOT
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_AT91_GPIO 1
> +#define CONFIG_ATMEL_USART 1
> +#undef CONFIG_USART0
> +#undef CONFIG_USART1
> +#undef CONFIG_USART2
> +#define CONFIG_USART3 1 /* USART 3 is DBGU */
> +#define CONFIG_ATMEL_SPI 1
> +
> +#define CONFIG_SYS_USE_NANDFLASH 1
> +
> +/*
> + * Hardware on board which could be removed
> + */
> +#undef CONFIG_HAS_DATAFLASH
> +
> +/* LCD */
> +#define CONFIG_LCD 1
> +#define LCD_BPP LCD_COLOR8
> +#define CONFIG_LCD_LOGO 1
> +#undef LCD_TEST_PATTERN
> +#define CONFIG_LCD_INFO 1
> +#define CONFIG_LCD_INFO_BELOW_LOGO 1
> +#define CONFIG_SYS_WHITE_ON_BLACK 1
> +#define CONFIG_ATMEL_LCD 1
> +#define CONFIG_ATMEL_LCD_RGB565 1
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
> +
> +/* LED */
> +#define CONFIG_AT91_LED
> +#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the
> user1 led */
> +#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the
> user2 led */
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +/*
> + * BOOTP options
> + */
> +#define CONFIG_BOOTP_BOOTFILESIZE 1
> +#define CONFIG_BOOTP_BOOTPATH 1
> +#define CONFIG_BOOTP_GATEWAY 1
> +#define CONFIG_BOOTP_HOSTNAME 1
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +#undef CONFIG_CMD_BDI
> +#undef CONFIG_CMD_FPGA
> +#undef CONFIG_CMD_IMI
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_AUTOSCRIPT
> +#undef CONFIG_CMD_LOADS
> +
> +#define CONFIG_CMD_PING 1
> +#define CONFIG_CMD_DHCP 1
> +#define CONFIG_CMD_NAND 1
> +#define CONFIG_CMD_USB 1
> +
> +#define CONFIG_CMD_JFFS2 1
> +#define CONFIG_JFFS2_CMDLINE 1
> +#define CONFIG_JFFS2_NAND 1
> +#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives
> on */
> +#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition
> */
> +#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition
> size*/
> +
> +/* SDRAM */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM 0x70000000
> +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs
> */
> +
> +/* DataFlash */
> +#ifdef CONFIG_ATMEL_SPI
> +#define CONFIG_CMD_SF
> +#define CONFIG_CMD_SPI
> +#define CONFIG_SPI_FLASH 1
> +#define CONFIG_SPI_FLASH_ATMEL 1
> +#endif
> +#ifdef CONFIG_HAS_DATAFLASH
> +#define CONFIG_ATMEL_DATAFLASH_SPI
> +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
> +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
> +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
> +#define AT91_SPI_CLK 15000000
> +#define DATAFLASH_TCSS (0x1a << 16)
> +#define DATAFLASH_TCHS (0x1 << 24)
> +#endif
> +
> +/* NOR flash, not available */
> +#define CONFIG_SYS_NO_FLASH 1
> +#undef CONFIG_CMD_FLASH
> +
> +/* NAND flash */
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_NAND_MAX_CHIPS 1
> +#define CONFIG_NAND_ATMEL
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x40000000
> +#define CONFIG_SYS_NAND_DBW_8 1
> +/* our ALE is AD21 */
> +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
> +/* our CLE is AD22 */
> +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
> +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
> +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3
> +
> +#endif
> +
> +/* Ethernet */
> +#define CONFIG_MACB 1
> +#define CONFIG_RMII 1
> +#define CONFIG_NET_MULTI 1
> +#define CONFIG_NET_RETRY_COUNT 20
> +#define CONFIG_RESET_PHY_R 1
> +
> +/* USB */
> +#define CONFIG_USB_ATMEL
> +#define CONFIG_USB_OHCI_NEW 1
> +#define CONFIG_DOS_PARTITION 1
> +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
> +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /*
> AT91SAM9G45_UHP_OHCI_BASE*/
> +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
> +#define CONFIG_USB_STORAGE 1
> +
> +/* board specific(not enough SRAM) */
> +#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
> +
> +#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load
> address */
> +
> +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> +#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
> +
> +#ifdef CONFIG_SYS_USE_DATAFLASH
> +
> +/* bootstrap + u-boot + env + linux in dataflash on CS0 */
> +#define CONFIG_ENV_IS_IN_SPI_FLASH 1
> +#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400)
> +#define CONFIG_ENV_OFFSET 0x4200
> +#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET)
> +#define CONFIG_ENV_SIZE 0x4200
> +#define CONFIG_ENV_SECT_SIZE 0x10000
> +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000;
> bootm"
> +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
> + "root=/dev/mtdblock0 " \
> + "mtdparts=atmel_nand:-(root) "\
> + "rw rootfstype=jffs2"
> +
> +#else /* CONFIG_SYS_USE_NANDFLASH */
> +
> +/* bootstrap + u-boot + env + linux in nandflash */
> +#define CONFIG_ENV_IS_IN_NAND 1
> +#define CONFIG_ENV_OFFSET 0x60000
> +#define CONFIG_ENV_OFFSET_REDUND 0x80000
> +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector
> = 128 kB */
> +#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000;
> bootm"
> +#define CONFIG_BOOTARGS "fbcon=rotate:3 " \
> + "root=/dev/mtdblock4 " \
> + "mtdparts=atmel_nand:128k(bootstrap)ro," \
> + "256k(uboot)ro,1664k(env)," \
> + "2M(linux)ro,-(root) rw " \
> + "rootfstype=jffs2"
> +
> +#endif
> +
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600
> }
> +
> +#define CONFIG_SYS_PROMPT "U-Boot> "
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +
> sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_LONGHELP 1
> +#define CONFIG_CMDLINE_EDITING 1
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE +
> 128*1024, 0x1000)
> +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial
> data */
> +
> +#define CONFIG_STACKSIZE (32*1024) /* regular stack */
> +
> +#ifdef CONFIG_USE_IRQ
> +#error CONFIG_USE_IRQ not supported
> +#endif
> +
> +#endif
> --
> 1.5.5.6
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] add new board pm9g45
2010-03-16 12:57 [U-Boot] [PATCH] add new board pm9g45 Asen Dimov
2010-03-16 19:00 ` Wolfgang Denk
2010-03-18 6:41 ` Maxim Podbereznyi
@ 2010-03-20 19:10 ` Tom
2010-03-21 19:56 ` Wolfgang Denk
2010-03-30 11:55 ` RONETIX - Asen Dimov
2 siblings, 2 replies; 10+ messages in thread
From: Tom @ 2010-03-20 19:10 UTC (permalink / raw)
To: u-boot
Asen Dimov wrote:
> Hello everyone,
>
> here is the new board PM9G45 from Ronetix GmbH,
> based on at91sam9g45 MCU. It has 128MB DDR2 SDRAM, 256MB NAND,
> could be with or without DataFlash.
> The board is made as SODIMM200 module.
> For more info www.ronatix.at or info at ronetix.at.
>
> Regards,
> Asen
There are some errors on building with MAKEALL arm
These must be fixed
regressions from pm9g45.ERR
cpu.c:26:2: warning: #warning Your board is using legacy SoC access. Please update!
pm9g45.c: In function 'pm9g45_macb_hw_init':
pm9g45.c:112: warning: unused variable 'rstc'
pm9g45.c: In function 'lcd_show_board_info':
pm9g45.c:225: warning: unused variable 'dataflash_size'
Because this is a new board, it should follow the new at91 Soc access.
See doc/README.at91-soc
I also recommend running the linux kernel's checkpatch.pl program to
find formatting problems.
>
> Signed-off-by: Asen Dimov <dimov@ronetix.at>
> ---
> MAKEALL | 1 +
> Makefile | 4 +
> board/ronetix/pm9g45/Makefile | 54 +++
> .../at91sam9m10g45ek => ronetix/pm9g45}/config.mk | 0
> board/ronetix/pm9g45/pm9g45.c | 365 ++++++++++++++++++++
> include/configs/pm9g45.h | 246 +++++++++++++
> 6 files changed, 670 insertions(+), 0 deletions(-)
> create mode 100644 board/ronetix/pm9g45/Makefile
> copy board/{atmel/at91sam9m10g45ek => ronetix/pm9g45}/config.mk (100%)
> create mode 100644 board/ronetix/pm9g45/pm9g45.c
> create mode 100644 include/configs/pm9g45.h
>
> diff --git a/MAKEALL b/MAKEALL
> index beacb5f..ad591d5 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -673,6 +673,7 @@ LIST_at91=" \
> otc570 \
> pm9261 \
> pm9263 \
> + pm9g45 \
> SBC35_A9G20 \
> TNY_A9260 \
> TNY_A9G20 \
> diff --git a/Makefile b/Makefile
> index d801e25..438580a 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -2882,6 +2882,10 @@ otc570_config : unconfig
> pm9263_config : unconfig
> @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
>
> +pm9g45_config : unconfig
> + @mkdir -p $(obj)include
> + @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
> +
> SBC35_A9G20_NANDFLASH_config \
> SBC35_A9G20_EEPROM_config \
> SBC35_A9G20_config : unconfig
> diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile
> new file mode 100644
> index 0000000..dd5b02e
> --- /dev/null
> +++ b/board/ronetix/pm9g45/Makefile
> @@ -0,0 +1,54 @@
> +#
> +# (C) Copyright 2003-2008
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# (C) Copyright 2008
> +# Stelian Pop <stelian.pop@leadtechdesign.com>
> +# Lead Tech Design <www.leadtechdesign.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).a
> +
> +COBJS-y += pm9g45.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS-y))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
> +
> +clean:
> + rm -f $(SOBJS) $(OBJS)
> +
> +distclean: clean
> + rm -f $(LIB) core *.bak $(obj).depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/atmel/at91sam9m10g45ek/config.mk b/board/ronetix/pm9g45/config.mk
> similarity index 100%
> copy from board/atmel/at91sam9m10g45ek/config.mk
> copy to board/ronetix/pm9g45/config.mk
> diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
> new file mode 100644
> index 0000000..d11f40f
> --- /dev/null
> +++ b/board/ronetix/pm9g45/pm9g45.c
> @@ -0,0 +1,365 @@
> +/*
> + * (C) Copyright 2005-2010
> + * Ilko Iliev <iliev@ronetix.at>
> + * Asen Dimov <dimov@ronetix.at>
> + * Ronetix GmbH <www.ronetix.at>
> + *
> + * (C) Copyright 2007-2008
> + * Stelian Pop <stelian.pop@leadtechdesign.com>
> + * Lead Tech Design <www.leadtechdesign.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/sizes.h>
> +#include <asm/arch/at91sam9g45.h>
> +#include <asm/arch/at91sam9_matrix.h>
> +#include <asm/arch/at91sam9_smc.h>
> +#include <asm/arch/at91_common.h>
> +#include <asm/arch/at91_pmc.h>
> +#include <asm/arch/at91_rstc.h>
> +#include <asm/arch/clk.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/io.h>
> +#include <asm/arch/hardware.h>
> +#include <lcd.h>
> +#include <atmel_lcdc.h>
> +#ifdef CONFIG_HAS_DATAFLASH
> +#include <dataflash.h>
> +#endif
> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
> +#include <net.h>
> +#endif
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* ------------------------------------------------------------------------- */
This line is not needed
> +/*
> + * Miscelaneous platform dependent initialisations
> + */
> +
> +#ifdef CONFIG_HAS_DATAFLASH
> +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
> +
> +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
> + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
> +};
> +
> +/*define the area offsets*/
Space needed 'sets*/'
> +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
> + {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "DataFlash"},
> +};
> +#endif
> +
> +#ifdef CONFIG_CMD_NAND
> +static void pm9g45_nand_hw_init(void)
> +{
> + unsigned long csa;
> +
> + /* Enable CS3 */
> + csa = at91_sys_read(AT91_MATRIX_EBICSA);
> + at91_sys_write(AT91_MATRIX_EBICSA,
> + csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
> +
> + /* Configure SMC CS3 for NAND/SmartMedia */
> + at91_sys_write(AT91_SMC_SETUP(3),
> + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
> + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
> + at91_sys_write(AT91_SMC_PULSE(3),
> + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
> + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
> + at91_sys_write(AT91_SMC_CYCLE(3),
> + AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
> + at91_sys_write(AT91_SMC_MODE(3),
> + AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
> + AT91_SMC_EXNWMODE_DISABLE |
> + AT91_SMC_DBW_8 |
> + AT91_SMC_TDF_(3));
> +
> + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
> +
> +#ifdef CONFIG_SYS_NAND_READY_PIN
> + /* Configure RDY/BSY */
> + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
> +#endif
GPIO is one of the areas that uses the new at91 soc access
In git, look for this commit
'add a new AT91 GPIO driver'
> +
> + /* Enable NandFlash */
> + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
> +}
> +#endif
> +
> +#ifdef CONFIG_MACB
> +static void pm9g45_macb_hw_init(void)
> +{
> + unsigned long rstc;
> +
> + /*
> + * PD2 enables the 50MHz oscillator for Ethernet PHY
> + * 1 - enable
> + * 0 - disable
> + */
> + at91_set_gpio_output(AT91_PIN_PD2, 1);
> + at91_set_gpio_value(AT91_PIN_PD2, 1); /* 1- enable, 0 - disable */
> +
> + /* Enable clock */
> + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
> +
> + /*
> + * Disable pull-up on:
> + * RXDV (PA15) => PHY normal mode (not Test mode)
> + * ERX0 (PA12) => PHY ADDR0
> + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
> + *
> + * PHY has internal pull-down
> + */
> + writel(pin_to_mask(AT91_PIN_PA15),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
> + writel(pin_to_mask(AT91_PIN_PA12) |
> + pin_to_mask(AT91_PIN_PA13),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
> +
> + /* Re-enable pull-up */
> + writel(pin_to_mask(AT91_PIN_PA15),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
> + writel(pin_to_mask(AT91_PIN_PA12) |
> + pin_to_mask(AT91_PIN_PA13),
> + pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
> +
> + at91_macb_hw_init();
> +}
> +#endif
> +
> +#ifdef CONFIG_LCD
Move the LCD code to its own file
board/ronetix/pm9g45/lcd.c
> +/*
> + * LCD name TX09D50VM1CCA
> + */
> +vidinfo_t panel_info = {
> + vl_col: 240,
> + vl_row: 320,
> + vl_clk: 4965000,
> + vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
> + ATMEL_LCDC_INVFRAME_NORMAL,
> + vl_bpix: 3,
> + vl_tft: 1,
> + vl_hsync_len: 5,
> + vl_left_margin: 1,
> + vl_right_margin:33,
> + vl_vsync_len: 1,
> + vl_upper_margin:1,
> + vl_lower_margin:0,
> + mmio: AT91SAM9G45_LCDC_BASE,
> +};
The pannel information, if common with other boards
should be defined in an h-file and shared. If there
is no overlap, defining in c-file is fine
> +
> +void lcd_enable(void)
> +{
> + at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
> +}
> +
at91_set_A_periph is another function that changed with the new
soc access.
> +void lcd_disable(void)
> +{
> + at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
> +}
> +
> +static void pm9g45_lcd_hw_init(void)
> +{
> + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
> + at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
> + at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
> + at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
> + at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
> +
> + at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
> + at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
> + at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
> + at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
> + at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
> + at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
> + at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
> + at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
> + at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
> + at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
> + at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
> + at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
> + at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
> + at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
> + at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
> + at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
> + at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
> + at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
> + at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
> + at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
> + at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
> + at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
> + at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
> + at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
> +
> + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
> +
> + gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
> +}
> +
> +#ifdef CONFIG_LCD_INFO
> +#include <nand.h>
> +#include <version.h>
> +
> +void lcd_show_board_info(void)
> +{
> + ulong dram_size, nand_size, dataflash_size;
> + int i;
> + char temp[32];
> +
> + lcd_printf ("%s\n", U_BOOT_VERSION);
> + lcd_printf ("(C) 2010 Ronetix GmbH\n");
> + lcd_printf ("support at ronetix.at\n");
> + lcd_printf ("%s CPU at %s MHz\n",
> + CONFIG_SYS_AT91_CPU_NAME,
> + strmhz(temp, get_cpu_clk_rate()));
> +
> + dram_size = 0;
> + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
> + dram_size += gd->bd->bi_dram[i].size;
> +
> + nand_size = 0;
> + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
> + nand_size += nand_info[i].size;
> +
> +#ifdef CONFIG_HAS_DATAFLASH
> + dataflash_size = 0;
> + for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
> + dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
> + dataflash_info[i].Device.pages_size;
> +#endif
Trailing tab.
Remove
> +
> + lcd_printf ("%ld MB DDR2 SDRAM\n%ld MB NAND\n",
> + dram_size >> 20,
> + nand_size >> 20);
> +
> +#ifdef CONFIG_HAS_DATAFLASH
This and the above CONFIG_HAS_DATAFLASH should be combined for readablity
Move above #if-def here.
> + lcd_printf ("%ld MB DataFlash\n",
> + dataflash_size >> 20);
> +#endif
Trailing tab
Remove
> +}
> +#endif /* CONFIG_LCD_INFO */
> +#endif
> +
> +int board_init(void)
> +{
> + /* Enable Ctrlc */
> + console_init_f();
> +
> + at91_sys_write(AT91_PMC_PCER,
> + (1 << AT91SAM9G45_ID_PIOA) |
> + (1 << AT91SAM9G45_ID_PIOB) |
> + (1 << AT91SAM9G45_ID_PIOC) |
> + (1 << AT91SAM9G45_ID_PIODE));
Remove some of these tab's to a lines align with first line
of the statement better
> +
> + /* arch number of AT91SAM9M10G45EK-Board */
> + gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
> + /* adress of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
> +
> + at91_serial_hw_init();
> +#ifdef CONFIG_CMD_NAND
> + pm9g45_nand_hw_init();
> +#endif
> +
> +#ifdef CONFIG_HAS_DATAFLASH
> + at91_spi0_hw_init(1 << 0);
> +#endif
> +
1 << 0 ??
Change this value and one below to a logical
#if-def value
> +#ifdef CONFIG_ATMEL_SPI
> + at91_spi0_hw_init(1 << 4);
> +#endif
> +
> +#ifdef CONFIG_MACB
> + pm9g45_macb_hw_init();
> +#endif
> +
> +#ifdef CONFIG_LCD
> + pm9g45_lcd_hw_init();
> +#endif
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM;
> + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
> + return 0;
> +}
> +
> +#ifdef CONFIG_RESET_PHY_R
> +void reset_phy(void)
> +{
> +#ifdef CONFIG_MACB
> + /*
> + * Initialize ethernet HW addr prior to starting Linux,
> + * needed for nfsroot
> + */
> + eth_init(gd->bd);
> +#endif
> +}
> +#endif
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = 0;
> +#ifdef CONFIG_MACB
> + rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x01);
> +#endif
> + return rc;
> +}
> +
> +/* SPI chip select control */
> +#ifdef CONFIG_ATMEL_SPI
> +#include <spi.h>
> +
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> + return bus == 0 && cs < 2;
enclose the return statement in ()'s to make it
clear that a conditional is being returned.
> +}
> +
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> + switch(slave->cs) {
> + case 1:
> + at91_set_gpio_output(AT91_PIN_PB18, 0);
> + break;
> + case 0:
> + default:
> + at91_set_gpio_output(AT91_PIN_PB3, 0);
> + break;
> + }
Only 2 conditions in switch is overkill.
Consider changing this to a if-else statement.
> +}
> +
> +void spi_cs_deactivate(struct spi_slave *slave)
> +{
> + switch(slave->cs) {
> + case 1:
> + at91_set_gpio_output(AT91_PIN_PB18, 1);
> + break;
> + case 0:
> + default:
> + at91_set_gpio_output(AT91_PIN_PB3, 1);
> + break;
Similar consider changing to if-else
> + }
> +}
> +#endif /* CONFIG_ATMEL_SPI */
> diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
> new file mode 100644
> index 0000000..b8300b9
> --- /dev/null
> +++ b/include/configs/pm9g45.h
> @@ -0,0 +1,246 @@
> +/*
> + * (C) Copyright 2005-2010
> + * Ilko Iliev <iliev@ronetix.at>
> + * Asen Dimov <dimov@ronetix.at>
> + * Ronetix GmbH <www.ronetix.at>
> + *
> + * (C) Copyright 2007-2008
> + * Stelian Pop <stelian.pop@leadtechdesign.com>
> + * Lead Tech Design <www.leadtechdesign.com>
> + *
> + * Configuation settings for the PM9G45 board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_AT91_LEGACY
> +
> +/* ARM asynchronous clock */
> +#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
> +#define CONFIG_SYS_HZ 1000
Move the clock values below the cpu/soc/board values
> +
> +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
> +#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
> +#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/
To here
> +#define CONFIG_ARCH_CPU_INIT
> +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
> +
> +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS 1
> +#define CONFIG_INITRD_TAG 1
> +
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_SKIP_RELOCATE_UBOOT
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_AT91_GPIO 1
> +#define CONFIG_ATMEL_USART 1
> +#undef CONFIG_USART0
> +#undef CONFIG_USART1
> +#undef CONFIG_USART2
> +#define CONFIG_USART3 1 /* USART 3 is DBGU */
> +#define CONFIG_ATMEL_SPI 1
> +
> +#define CONFIG_SYS_USE_NANDFLASH 1
> +
> +/*
> + * Hardware on board which could be removed
> + */
> +#undef CONFIG_HAS_DATAFLASH
> +
> +/* LCD */
> +#define CONFIG_LCD 1
> +#define LCD_BPP LCD_COLOR8
> +#define CONFIG_LCD_LOGO 1
> +#undef LCD_TEST_PATTERN
> +#define CONFIG_LCD_INFO 1
> +#define CONFIG_LCD_INFO_BELOW_LOGO 1
> +#define CONFIG_SYS_WHITE_ON_BLACK 1
> +#define CONFIG_ATMEL_LCD 1
> +#define CONFIG_ATMEL_LCD_RGB565 1
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
> +
> +/* LED */
> +#define CONFIG_AT91_LED
> +#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
> +#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +/*
> + * BOOTP options
> + */
> +#define CONFIG_BOOTP_BOOTFILESIZE 1
> +#define CONFIG_BOOTP_BOOTPATH 1
> +#define CONFIG_BOOTP_GATEWAY 1
> +#define CONFIG_BOOTP_HOSTNAME 1
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +#undef CONFIG_CMD_BDI
> +#undef CONFIG_CMD_FPGA
> +#undef CONFIG_CMD_IMI
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_AUTOSCRIPT
> +#undef CONFIG_CMD_LOADS
> +
> +#define CONFIG_CMD_PING 1
> +#define CONFIG_CMD_DHCP 1
> +#define CONFIG_CMD_NAND 1
> +#define CONFIG_CMD_USB 1
> +
> +#define CONFIG_CMD_JFFS2 1
> +#define CONFIG_JFFS2_CMDLINE 1
> +#define CONFIG_JFFS2_NAND 1
> +#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
> +#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
> +#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
Need a space 'size*/'
Likely also need to move the comment
> +
> +/* SDRAM */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM 0x70000000
> +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
> +
> +/* DataFlash */
> +#ifdef CONFIG_ATMEL_SPI
> +#define CONFIG_CMD_SF
> +#define CONFIG_CMD_SPI
> +#define CONFIG_SPI_FLASH 1
> +#define CONFIG_SPI_FLASH_ATMEL 1
> +#endif
> +#ifdef CONFIG_HAS_DATAFLASH
> +#define CONFIG_ATMEL_DATAFLASH_SPI
> +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
> +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
> +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
> +#define AT91_SPI_CLK 15000000
> +#define DATAFLASH_TCSS (0x1a << 16)
> +#define DATAFLASH_TCHS (0x1 << 24)
> +#endif
> +
> +/* NOR flash, not available */
> +#define CONFIG_SYS_NO_FLASH 1
> +#undef CONFIG_CMD_FLASH
> +
> +/* NAND flash */
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_NAND_MAX_CHIPS 1
> +#define CONFIG_NAND_ATMEL
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x40000000
> +#define CONFIG_SYS_NAND_DBW_8 1
> +/* our ALE is AD21 */
> +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
> +/* our CLE is AD22 */
> +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
> +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
> +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3
> +
> +#endif
> +
> +/* Ethernet */
> +#define CONFIG_MACB 1
> +#define CONFIG_RMII 1
> +#define CONFIG_NET_MULTI 1
> +#define CONFIG_NET_RETRY_COUNT 20
> +#define CONFIG_RESET_PHY_R 1
> +
> +/* USB */
> +#define CONFIG_USB_ATMEL
> +#define CONFIG_USB_OHCI_NEW 1
> +#define CONFIG_DOS_PARTITION 1
> +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
> +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE*/
> +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
> +#define CONFIG_USB_STORAGE 1
> +
> +/* board specific(not enough SRAM) */
> +#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
> +
> +#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load address */
> +
> +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> +#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
> +
> +#ifdef CONFIG_SYS_USE_DATAFLASH
> +
> +/* bootstrap + u-boot + env + linux in dataflash on CS0 */
> +#define CONFIG_ENV_IS_IN_SPI_FLASH 1
> +#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400)
> +#define CONFIG_ENV_OFFSET 0x4200
> +#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET)
> +#define CONFIG_ENV_SIZE 0x4200
> +#define CONFIG_ENV_SECT_SIZE 0x10000
> +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm"
> +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
> + "root=/dev/mtdblock0 " \
> + "mtdparts=atmel_nand:-(root) "\
> + "rw rootfstype=jffs2"
> +
> +#else /* CONFIG_SYS_USE_NANDFLASH */
> +
> +/* bootstrap + u-boot + env + linux in nandflash */
> +#define CONFIG_ENV_IS_IN_NAND 1
> +#define CONFIG_ENV_OFFSET 0x60000
> +#define CONFIG_ENV_OFFSET_REDUND 0x80000
> +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
> +#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
> +#define CONFIG_BOOTARGS "fbcon=rotate:3 " \
> + "root=/dev/mtdblock4 " \
> + "mtdparts=atmel_nand:128k(bootstrap)ro," \
> + "256k(uboot)ro,1664k(env)," \
> + "2M(linux)ro,-(root) rw " \
> + "rootfstype=jffs2"
> +
> +#endif
> +
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
> +
> +#define CONFIG_SYS_PROMPT "U-Boot> "
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_LONGHELP 1
> +#define CONFIG_CMDLINE_EDITING 1
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
> +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
> +
> +#define CONFIG_STACKSIZE (32*1024) /* regular stack */
> +
> +#ifdef CONFIG_USE_IRQ
> +#error CONFIG_USE_IRQ not supported
> +#endif
Explicitly undef-ed CONFIG_USB_IRQ above
Could remove this.
> +
> +#endif
Tom
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] add new board pm9g45
2010-03-18 6:41 ` Maxim Podbereznyi
@ 2010-03-21 18:57 ` Wolfgang Denk
0 siblings, 0 replies; 10+ messages in thread
From: Wolfgang Denk @ 2010-03-21 18:57 UTC (permalink / raw)
To: u-boot
Dear Maxim Podbereznyi,
In message <e0656fd71003172341t27279a66i25e739cf25cfa046@mail.gmail.com> you wrote:
>
> Russian company MENTOREL released at91sam9G45 based SODIMM module a couple
> of months ago. Module is named ...
Except for the cheap commercial plug - did you intend to contribute
anything to the review of the patch in question here?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"There is nothing so deadly as not to hold up to people the
opportunity to do great and wonderful things, if we wish to stimulate
them in an active way."
- Dr. Harold Urey, Nobel Laureate in chemistry
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] add new board pm9g45
2010-03-20 19:10 ` Tom
@ 2010-03-21 19:56 ` Wolfgang Denk
2010-03-30 11:55 ` RONETIX - Asen Dimov
1 sibling, 0 replies; 10+ messages in thread
From: Wolfgang Denk @ 2010-03-21 19:56 UTC (permalink / raw)
To: u-boot
Dear Tom,
In message <4BA51DAD.5020200@windriver.com> you wrote:
> Asen Dimov wrote:
> > Hello everyone,
> >
> > here is the new board PM9G45 from Ronetix GmbH,
> > based on at91sam9g45 MCU. It has 128MB DDR2 SDRAM, 256MB NAND,
> > could be with or without DataFlash.
> > The board is made as SODIMM200 module.
> > For more info www.ronatix.at or info at ronetix.at.
> >
> > Regards,
> > Asen
>
> There are some errors on building with MAKEALL arm
> These must be fixed
Could you please make sure to include threading information (i. e.
appropriate "References:" and "In-reply-to:" mail headers)?
It would be nice if we could see which message your postings refer
to.
Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Philosophy: A route of many roads leading from nowhere to nothing.
- Ambrose Bierce
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] add new board pm9g45
2010-03-20 19:10 ` Tom
2010-03-21 19:56 ` Wolfgang Denk
@ 2010-03-30 11:55 ` RONETIX - Asen Dimov
1 sibling, 0 replies; 10+ messages in thread
From: RONETIX - Asen Dimov @ 2010-03-30 11:55 UTC (permalink / raw)
To: u-boot
Hello Tom,
In respond of the message <4BA51DAD.5020200@windriver.com> you wrote:
there is a second version of the this patch in e-mail with message-id
<1268928021-31632-1-git-send-email-dimov@ronetix.at> and subject
<[U-Boot][PATCH v2] add new board pm9g45> from 18.03.2010.
Regards,
Asen
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] add new board pm9g45
@ 2010-03-16 12:02 Asen Dimov
0 siblings, 0 replies; 10+ messages in thread
From: Asen Dimov @ 2010-03-16 12:02 UTC (permalink / raw)
To: u-boot
Board PM9G45 from Ronetix GmbH. Based on at91sam9g45 MCU.
It has 128MB DDR2 SDRAM, 256MB NAND, could be with or without
DataFlash. The board is made as SODIMM200 module.
For more info www.ronatix.at or info at ronetix.at.
Signed-off-by: Asen Dimov <dimov@ronetix.at>
---
MAKEALL | 1 +
Makefile | 4 +
board/ronetix/pm9g45/Makefile | 54 +++
.../at91sam9m10g45ek => ronetix/pm9g45}/config.mk | 0
board/ronetix/pm9g45/pm9g45.c | 365 ++++++++++++++++++++
include/configs/pm9g45.h | 246 +++++++++++++
6 files changed, 670 insertions(+), 0 deletions(-)
create mode 100644 board/ronetix/pm9g45/Makefile
copy board/{atmel/at91sam9m10g45ek => ronetix/pm9g45}/config.mk (100%)
create mode 100644 board/ronetix/pm9g45/pm9g45.c
create mode 100644 include/configs/pm9g45.h
diff --git a/MAKEALL b/MAKEALL
index beacb5f..ad591d5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -673,6 +673,7 @@ LIST_at91=" \
otc570 \
pm9261 \
pm9263 \
+ pm9g45 \
SBC35_A9G20 \
TNY_A9260 \
TNY_A9G20 \
diff --git a/Makefile b/Makefile
index d801e25..438580a 100644
--- a/Makefile
+++ b/Makefile
@@ -2882,6 +2882,10 @@ otc570_config : unconfig
pm9263_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
+pm9g45_config : unconfig
+ @mkdir -p $(obj)include
+ @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
+
SBC35_A9G20_NANDFLASH_config \
SBC35_A9G20_EEPROM_config \
SBC35_A9G20_config : unconfig
diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile
new file mode 100644
index 0000000..dd5b02e
--- /dev/null
+++ b/board/ronetix/pm9g45/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += pm9g45.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atmel/at91sam9m10g45ek/config.mk b/board/ronetix/pm9g45/config.mk
similarity index 100%
copy from board/atmel/at91sam9m10g45ek/config.mk
copy to board/ronetix/pm9g45/config.mk
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
new file mode 100644
index 0000000..d11f40f
--- /dev/null
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -0,0 +1,365 @@
+/*
+ * (C) Copyright 2005-2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+#endif
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_HAS_DATAFLASH
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "DataFlash"},
+};
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static void pm9g45_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ at91_sys_write(AT91_MATRIX_EBICSA,
+ csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+ AT91_SMC_DBW_8 |
+ AT91_SMC_TDF_(3));
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
+
+#ifdef CONFIG_SYS_NAND_READY_PIN
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+#endif
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9g45_macb_hw_init(void)
+{
+ unsigned long rstc;
+
+ /*
+ * PD2 enables the 50MHz oscillator for Ethernet PHY
+ * 1 - enable
+ * 0 - disable
+ */
+ at91_set_gpio_output(AT91_PIN_PD2, 1);
+ at91_set_gpio_value(AT91_PIN_PD2, 1); /* 1- enable, 0 - disable */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA15) => PHY normal mode (not Test mode)
+ * ERX0 (PA12) => PHY ADDR0
+ * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA15),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+ writel(pin_to_mask(AT91_PIN_PA12) |
+ pin_to_mask(AT91_PIN_PA13),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA15),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+ writel(pin_to_mask(AT91_PIN_PA12) |
+ pin_to_mask(AT91_PIN_PA13),
+ pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+/*
+ * LCD name TX09D50VM1CCA
+ */
+vidinfo_t panel_info = {
+ vl_col: 240,
+ vl_row: 320,
+ vl_clk: 4965000,
+ vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
+ ATMEL_LCDC_INVFRAME_NORMAL,
+ vl_bpix: 3,
+ vl_tft: 1,
+ vl_hsync_len: 5,
+ vl_left_margin: 1,
+ vl_right_margin:33,
+ vl_vsync_len: 1,
+ vl_upper_margin:1,
+ vl_lower_margin:0,
+ mmio: AT91SAM9G45_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+ at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
+}
+
+static void pm9g45_lcd_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
+ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
+ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
+ at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
+ at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
+
+ at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
+ at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
+ at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
+ at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
+ at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
+ at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
+ at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
+ at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
+ at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
+ at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
+ at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
+ at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
+ at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
+ at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
+ at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
+ at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
+ at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
+ at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
+ at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
+ at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
+ at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
+ at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
+ at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
+ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
+
+ gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size, dataflash_size;
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2010 Ronetix GmbH\n");
+ lcd_printf ("support at ronetix.at\n");
+ lcd_printf ("%s CPU at %s MHz\n",
+ CONFIG_SYS_AT91_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+
+#ifdef CONFIG_HAS_DATAFLASH
+ dataflash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
+ dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
+ dataflash_info[i].Device.pages_size;
+#endif
+
+ lcd_printf ("%ld MB DDR2 SDRAM\n%ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20);
+
+#ifdef CONFIG_HAS_DATAFLASH
+ lcd_printf ("%ld MB DataFlash\n",
+ dataflash_size >> 20);
+#endif
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ at91_sys_write(AT91_PMC_PCER,
+ (1 << AT91SAM9G45_ID_PIOA) |
+ (1 << AT91SAM9G45_ID_PIOB) |
+ (1 << AT91SAM9G45_ID_PIOC) |
+ (1 << AT91SAM9G45_ID_PIODE));
+
+ /* arch number of AT91SAM9M10G45EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ pm9g45_nand_hw_init();
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+ pm9g45_macb_hw_init();
+#endif
+
+#ifdef CONFIG_LCD
+ pm9g45_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x01);
+#endif
+ return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch(slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 0);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 0);
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch(slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 1);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 1);
+ break;
+ }
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
new file mode 100644
index 0000000..b8300b9
--- /dev/null
+++ b/include/configs/pm9g45.h
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2005-2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the PM9G45 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AT91_LEGACY
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
+#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO 1
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+#define CONFIG_ATMEL_SPI 1
+
+#define CONFIG_SYS_USE_NANDFLASH 1
+
+/*
+ * Hardware on board which could be removed
+ */
+#undef CONFIG_HAS_DATAFLASH
+
+/* LCD */
+#define CONFIG_LCD 1
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_LCD_LOGO 1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO 1
+#define CONFIG_LCD_INFO_BELOW_LOGO 1
+#define CONFIG_SYS_WHITE_ON_BLACK 1
+#define CONFIG_ATMEL_LCD 1
+#define CONFIG_ATMEL_LCD_RGB565 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
+#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+#define CONFIG_CMD_JFFS2 1
+#define CONFIG_JFFS2_CMDLINE 1
+#define CONFIG_JFFS2_NAND 1
+#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
+#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x70000000
+#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+
+/* DataFlash */
+#ifdef CONFIG_ATMEL_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH 1
+#define CONFIG_SPI_FLASH_ATMEL 1
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+#endif
+
+/* NOR flash, not available */
+#define CONFIG_SYS_NO_FLASH 1
+#undef CONFIG_CMD_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MAX_CHIPS 1
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE*/
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
+
+#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400)
+#define CONFIG_ENV_OFFSET 0x4200
+#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x4200
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 " \
+ "mtdparts=atmel_nand:-(root) "\
+ "rw rootfstype=jffs2"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
+#define CONFIG_BOOTARGS "fbcon=rotate:3 " \
+ "root=/dev/mtdblock4 " \
+ "mtdparts=atmel_nand:128k(bootstrap)ro," \
+ "256k(uboot)ro,1664k(env)," \
+ "2M(linux)ro,-(root) rw " \
+ "rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
--
1.5.5.6
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2010-03-30 11:55 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-03-16 12:57 [U-Boot] [PATCH] add new board pm9g45 Asen Dimov
2010-03-16 19:00 ` Wolfgang Denk
2010-03-17 20:06 ` RONETIX - Asen Dimov
2010-03-17 23:00 ` Wolfgang Denk
2010-03-18 6:41 ` Maxim Podbereznyi
2010-03-21 18:57 ` Wolfgang Denk
2010-03-20 19:10 ` Tom
2010-03-21 19:56 ` Wolfgang Denk
2010-03-30 11:55 ` RONETIX - Asen Dimov
-- strict thread matches above, loose matches on Subject: below --
2010-03-16 12:02 Asen Dimov
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