* [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac
@ 2010-03-29 12:24 Mikhail Kshevetskiy
2010-03-30 21:15 ` Wolfgang Denk
2010-04-09 21:50 ` [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac Wolfgang Denk
0 siblings, 2 replies; 9+ messages in thread
From: Mikhail Kshevetskiy @ 2010-03-29 12:24 UTC (permalink / raw)
To: u-boot
This patch is based on custom u-boot-1.1.2 version produced by voipac
(http://www.voipac.com) and board/trizepsiv files from current u-boot.
Up to now only PXA270 DIMM module with NOR flash is tested.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
---
Makefile | 3 +
board/vpac270/Makefile | 51 +++
board/vpac270/config.mk | 3 +
board/vpac270/lowlevel_init.S | 740 +++++++++++++++++++++++++++++++++++++++++
board/vpac270/vpac270.c | 101 ++++++
include/configs/vpac270.h | 329 ++++++++++++++++++
6 files changed, 1227 insertions(+), 0 deletions(-)
create mode 100644 board/vpac270/Makefile
create mode 100644 board/vpac270/config.mk
create mode 100644 board/vpac270/lowlevel_init.S
create mode 100644 board/vpac270/vpac270.c
create mode 100644 include/configs/vpac270.h
diff --git a/Makefile b/Makefile
index d801e25..188d618 100644
--- a/Makefile
+++ b/Makefile
@@ -3253,6 +3253,9 @@ trizepsiv_config : unconfig
fi;
@$(MKCONFIG) -a trizepsiv arm pxa trizepsiv
+vpac270_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm pxa vpac270
+
wepep250_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa wepep250
diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile
new file mode 100644
index 0000000..500e075
--- /dev/null
+++ b/board/vpac270/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := vpac270.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk
new file mode 100644
index 0000000..4486f6b
--- /dev/null
+++ b/board/vpac270/config.mk
@@ -0,0 +1,3 @@
+TEXT_BASE =0xa1f00000
+# 0xa1700000
+#TEXT_BASE = 0
diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S
new file mode 100644
index 0000000..1df381c
--- /dev/null
+++ b/board/vpac270/lowlevel_init.S
@@ -0,0 +1,740 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0, =GPSR0
+ ldr r1, =CONFIG_SYS_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CONFIG_SYS_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CONFIG_SYS_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR3
+ ldr r1, =CONFIG_SYS_GPSR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CONFIG_SYS_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CONFIG_SYS_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CONFIG_SYS_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR3
+ ldr r1, =CONFIG_SYS_GPCR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CONFIG_SYS_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CONFIG_SYS_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CONFIG_SYS_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR3
+ ldr r1, =CONFIG_SYS_GPDR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CONFIG_SYS_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CONFIG_SYS_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CONFIG_SYS_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CONFIG_SYS_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CONFIG_SYS_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CONFIG_SYS_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_L
+ ldr r1, =CONFIG_SYS_GAFR3_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_U
+ ldr r1, =CONFIG_SYS_GAFR3_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CONFIG_SYS_PSSR_VAL
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ mov r10, lr
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+ at 1:
+@ ldr r2, [r3]
+@ cmp r4, r2
+@ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, [r1, #MSC0_OFFSET]
+ tst r2, #8 /* test bus width */
+ ldr r2, =CONFIG_SYS_MSC0_VAL
+ biceq r2, r2, #8
+ orrne r2, r2, #8
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CONFIG_SYS_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CONFIG_SYS_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CONFIG_SYS_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CONFIG_SYS_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CONFIG_SYS_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CONFIG_SYS_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CONFIG_SYS_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CONFIG_SYS_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CONFIG_SYS_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+@ ldr r2, =CONFIG_SYS_FLYCNFG_VAL
+@ str r2, [r1, #FLYCNFG_OFFSET]
+@ str r2, [r1, #FLYCNFG_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field. */
+
+ ldr r4, [r1, #MDREFR_OFFSET]
+ ldr r2, =0xFFF
+ bic r4, r4, r2
+
+ ldr r3, =CONFIG_SYS_MDREFR_VAL
+ and r3, r3, r2
+
+ orr r4, r4, r3
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+
+ orr r4, r4, #MDREFR_K0RUN
+ orr r4, r4, #MDREFR_K0DB4
+ orr r4, r4, #MDREFR_K0FREE
+ orr r4, r4, #MDREFR_K0DB2
+ orr r4, r4, #MDREFR_K1DB2
+ orr r4, r4, #MDREFR_K2DB2
+ bic r4, r4, #MDREFR_K1FREE
+ bic r4, r4, #MDREFR_K2FREE
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Note: preserve the mdrefr value in r4 */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ ldr r2, =CONFIG_SYS_SXCNFG_VAL
+ str r2, [r1, #SXCNFG_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+ orr r4, r4, #MDREFR_K1RUN
+ orr r4, r4, #MDREFR_K2RUN
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ bic r4, r4, #MDREFR_SLFRSH
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ orr r4, r4, #MDREFR_E1PIN
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ nop
+ nop
+
+#if defined(CONFIG_SYS_MEM_BUF_IMP)
+ /* Step 4a: set memory buffer strengths */
+
+ ldr r3, =CONFIG_SYS_MEM_BUF_IMP
+ and r3, r3, #0x0f
+ /* now, copy those 4 bits to all 8 sub-registers (into r2): */
+ mov r2, r3
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+
+ str r2, [r1, #BSCNTR0_OFFSET]
+ str r2, [r1, #BSCNTR2_OFFSET]
+ str r2, [r1, #BSCNTR3_OFFSET]
+
+ /* BSCNTR1 is special, as it holds SDCAS_DELAY in bits 7:4 */
+ ldr r3, [r1, #BSCNTR1_OFFSET]
+ and r3, r3, #0xf0
+ bic r2, r2, #0xf0
+ orr r2, r3, r2
+ str r2, [r1, #BSCNTR1_OFFSET]
+
+ /* read back to make sure it's done: */
+ ldr r3, [r1, #BSCNTR1_OFFSET]
+#endif
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CONFIG_SYS_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+ bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 ?sec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ ldr r3, =PHYS_SDRAM_1
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+ ldr r3, =PHYS_SDRAM_2
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ mov r4, r3
+ orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
+ orr r3, r3, #(MDCNFG_DE2|MDCNFG_DE3)
+ str r3, [r1, #MDCNFG_OFFSET]
+ mov r0, r3
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CONFIG_SYS_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+ /* enable APD */
+ ldr r3, [r1, #MDREFR_OFFSET]
+ orr r3, r3, #MDREFR_APD
+ str r3, [r1, #MDREFR_OFFSET]
+
+ /* Step 5: Autodetect SDRAM size and bus width */
+
+ ldr r3, =PHYS_SDRAM_1 /* bank0, partition0/1 */
+
+ bl get_bus_width
+
+ /* set detected bank0 bus width */
+
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ orr r2, r2, r0
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* check sdram bank0 present */
+
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+ bic r2, r2, #0x3700
+ bic r2, r2, #0x00ff
+ ldr r4, [r3]
+ cmp r0, r4
+ bne bank0disable
+
+ ldr r0, =0xdeadbeef
+ str r0, [r3] /* a0000000 = deadbeef */
+ ldr r4, [r3]
+ cmp r0, r4
+ bne bank0disable
+
+ /* set column probe offset */
+
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ tst r2, #0x04 /* bank0 16/32bit wide bus ? */
+ mov r4, #0x200
+ addeq r4, r4, r4 /* 0x200 (16bit), 0x400 (32bit) */
+
+ bl get_columns
+
+ /* set detected columns */
+
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ bic r2, r2, #0x18
+ bic r2, r2, #0x4000
+ orr r2, r2, r0
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* set row probe offset */
+
+ tst r2, #0x04 /* bank0 16/32bit wide bus ? */
+ mov r4, #0x800000
+ addeq r4, r4, r4 /* 0x800000 (16bit), 0x1000000 (32bit) */
+
+ bl get_rows
+
+ /* set detected rows */
+
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ bic r2, r2, #0x60
+ orr r2, r2, r0
+
+bank0disable:
+ str r2, [r1, #MDCNFG_OFFSET]
+
+
+ ldr r3, =PHYS_SDRAM_2 /* bank1, partition2/3 */
+
+ bl get_bus_width
+
+ /* set detected bank0 bus width */
+
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ orr r2, r2, r0, LSL#16
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* check sdram bank1 present */
+
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+ bic r2, r2, #0x37000000
+ bic r2, r2, #0x00ff0000
+ ldr r4, [r3]
+ cmp r0, r4
+ bne bank1disable
+
+ ldr r0, =0xdeadbeef
+ str r0, [r3] /* a0000000 = deadbeef */
+ ldr r4, [r3]
+ cmp r0, r4
+ bne bank1disable
+
+ /* set column probe offset */
+
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ tst r2, #0x40000 /* bank1 16/32bit wide bus ? */
+ mov r4, #0x200
+ addeq r4, r4, r4 /* 0x200 (16bit), 0x400 (32bit) */
+
+ bl get_columns
+
+ /* set detected columns */
+
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ bic r2, r2, #0x180000
+ bic r2, r2, #0x40000000
+ orr r2, r2, r0, LSL#16
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* set row probe offset */
+
+ tst r2, #0x40000 /* bank1 16/32bit wide bus ? */
+ mov r4, #0x800000
+ addeq r4, r4, r4 /* 0x800000 (16bit), 0x1000000 (32bit) */
+
+ bl get_rows
+
+ /* set detected rows */
+
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ bic r2, r2, #0x600000
+ orr r2, r2, r0, LSL#16
+
+bank1disable:
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* We are finished with Intel's memory controller initialisation */
+
+
+ at setvoltage:
+@ mov r10, lr
+@ bl initPXAvoltage /* In case the board is rebooting with a */
+@ mov lr, r10 /* low voltage raise it up to a good one. */
+
+wakeup:
+ /* Are we waking from sleep? */
+ mov r1, #0x01
+ ldr r0, =RCSR
+ str r1, [r0]
+ ldr r1, [r0]
+ and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+ str r1, [r0]
+ teq r1, #RCSR_SMR
+
+ bne initirqs
+
+ ldr r0, =PSSR
+ mov r1, #PSSR_PH
+ str r1, [r0]
+
+ /* if so, resume at PSPR */
+ ldr r0, =PSPR
+ ldr r1, [r0]
+ mov pc, r1
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+
+ /* Turn Off on-chip peripheral clocks (except for memory) */
+ /* for re-configuration. */
+ ldr r1, =CKEN
+ ldr r2, =CONFIG_SYS_CKEN
+ str r2, [r1]
+
+ /* ... and write the core clock config register */
+ ldr r2, =CONFIG_SYS_CCCR
+ ldr r1, =CCCR
+ str r2, [r1]
+
+ /* Turn on turbo mode */
+ mrc p14, 0, r2, c6, c0, 0
+ orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
+ mcr p14, 0, r2, c6, c0, 0
+
+ /* Re-write MDREFR */
+ ldr r1, =MEMC_BASE
+ ldr r2, [r1, #MDREFR_OFFSET]
+ str r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+@ ands r2, r2, #1
+@ beq 60b
+#else
+#error "RTC not defined"
+#endif
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+ /* FIXME */
+
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+ mov lr, r10
+ mov pc, lr
+
+ /* Step 5a: Detect bus width 16/32bits */
+
+get_bus_width:
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+ ldr r2, =0xdeadbeef
+ str r2, [r3] /* a0000000 = 0xdeadbeef */
+
+ ldr r0, [r3] /* a0000000 */
+ cmp r0, r2
+ mov r0, #0
+ orrne r0, r0, #0x04
+
+ mov pc, lr
+
+ /* Step 5b: Detect number of columns */
+
+get_columns:
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+
+ add r0, r0, r4
+ str r0, [r3, r0] /* a0000200 (16bit), a0000400 (32bit) */
+
+ add r0, r0, r0
+ str r0, [r3, r0] /* a0000400 (16bit), a0000800 (32bit) */
+
+ add r0, r0, r0
+ str r0, [r3, r0] /* a0000800 (16bit), a0001000 (32bit) */
+
+ add r0, r0, r0
+ str r0, [r3, r0] /* a0001000 (16bit), a0002000 (32bit) */
+
+ ldr r2, =0xdeadbeef
+ str r2, [r3] /* a0000000 = 0xdeadbeef */
+
+ ldr r0, [r3, r4] /* a0000200 (16bit), a0000400 (32bit) */
+ cmp r0, r2
+ mov r0, #0 /* 8 columns, DCAC0 = 0 */
+ beq setcols
+
+ add r4, r4, r4
+ ldr r0, [r3, r4] /* a0000400 (16bit), a0000800 (32bit) */
+ cmp r0, r2
+ mov r0, #8 /* 9 columns, DCAC0 = 1 */
+ beq setcols
+
+ add r4, r4, r4
+ ldr r0, [r3, r4] /* a0000800 (16bit), a0001000 (32bit) */
+ cmp r0, r2
+ mov r0, #0x10 /* 10 columns, DCAC0 = 2 */
+ beq setcols
+
+@ add r4, r4, r4
+@ ldr r0, [r3, r4] /* a0001000 (16bit), a0002000 (32bit) */
+@ cmp r0, r2
+ mov r0, #0x18 /* 11 columns, DCAC0 = 3 */
+@ beq setcols
+
+@ mov r0, #0x4000 /* 12 columns, DCAC0 = 0, DCACX0 = 1 */
+
+setcols:
+ mov pc, lr
+
+ /* Step 5c: Detect number of rows */
+
+get_rows:
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+
+ add r0, r0, r4
+ str r0, [r3, r0] /* a0800000 (16bit), a1000000 (32bit) */
+
+ add r0, r0, r0
+ str r0, [r3, r0] /* a1000000 (16bit), a2000000 (32bit) */
+
+ ldr r2, =0xdeadbeef
+ str r2, [r3] /* a0000000 = 0xdeadbeef */
+
+ ldr r0, [r3, r4] /* a0800000 (16bit), a1000000 (32bit */
+ cmp r0, r2
+ mov r0, #0 /* 11 rows, DRAC0 = 0 */
+ beq setrows
+
+ add r4, r4, r4
+ ldr r0, [r3, r4] /* a1000000 (16bit), a2000000 (32bit) */
+ cmp r0, r2
+ mov r0, #0x20 /* 12 rows, DRAC0 = 1 */
+ beq setrows
+
+ mov r0, #0x40 /* 13 rows, DRAC0 = 2 */
+
+setrows:
+ mov pc, lr
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
new file mode 100644
index 0000000..723e9d8
--- /dev/null
+++ b/board/vpac270/vpac270.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley at applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+#define BOOT_CONSOLE "serial_ffuart"
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ char *console=getenv("boot_console");
+
+ if (console == NULL) console = BOOT_CONSOLE;
+ setenv("stdout", console);
+ setenv("stdin", console);
+ setenv("stderr", console);
+#endif
+
+ return 0;
+}
+
+struct serial_device *default_serial_console (void)
+{
+ return &serial_ffuart_device;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
new file mode 100644
index 0000000..969d6d3
--- /dev/null
+++ b/include/configs/vpac270.h
@@ -0,0 +1,329 @@
+/*
+ * (C) Copyright 2005
+ * Detlef Vollmann, Toradex AG, <dv@vollmann.ch>
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley at applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the VPAC270 module
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+//#define DEBUG 15
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
+#define CONFIG_VPAC270 1 /* on a Colibri module */
+
+//#define BOARD_LATE_INIT 1
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define RTC 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_FFUART 1 /* we use FFUART on Colibri */
+#define CONFIG_BTUART 1 /* we use BTUART on Colibri */
+#define CONFIG_STUART 1 /* we use STUART on Colibri */
+
+#define CONFIG_BAUDRATE 115200
+ /* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_DIAG /* Diagnostics */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_IPADDR 192.168.1.48
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_ETHADDR 00:01:02:03:04:05
+#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
+
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTCOMMAND "FIXME"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS0,115200"
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+//#define CONFIG_INITRD_TAG 1
+//#define CONFIG_SERIAL_TAG 1 /* we transfer the ethernet addr this way */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "u-boot> " /* Monitor Command Prompt */
+
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (64*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+ #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+ #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 bank of DRAM, but we have room for 4 */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
+
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+
+/*
+ * GPIO settings
+ */
+#if 1 /* minimal vpac270 settings, includes FFUART and Ethernet */
+ #define CONFIG_SYS_GPSR3_VAL 0x00000000
+ #define CONFIG_SYS_GPSR2_VAL 0x0000c000 // GPIO78, GPIO79
+ #define CONFIG_SYS_GPSR1_VAL 0x00020000 // GPIO49
+ #define CONFIG_SYS_GPSR0_VAL 0x00000000
+
+ #define CONFIG_SYS_GPCR3_VAL 0x0
+ #define CONFIG_SYS_GPCR2_VAL 0x0
+ #define CONFIG_SYS_GPCR1_VAL 0x0
+ #define CONFIG_SYS_GPCR0_VAL 0x0
+
+ #define CONFIG_SYS_GPDR3_VAL 0x00000000
+ #define CONFIG_SYS_GPDR2_VAL 0x0000c000 // GPIO78, GPIO79
+ #define CONFIG_SYS_GPDR1_VAL 0x00020180 // GPIO39, GPIO40, GPIO49
+ #define CONFIG_SYS_GPDR0_VAL 0x08000000 // GPIO27
+
+ #define CONFIG_SYS_GAFR3_U_VAL 0x00000000
+ #define CONFIG_SYS_GAFR3_L_VAL 0x00000300 // GPIO100=FFCTS
+ #define CONFIG_SYS_GAFR2_U_VAL 0x00000000
+ #define CONFIG_SYS_GAFR2_L_VAL 0xa0000000 // GPIO78=nCS2, GPIO79=nCS3
+ #define CONFIG_SYS_GAFR1_U_VAL 0x00000008 // GPIO49=nPWE
+ #define CONFIG_SYS_GAFR1_L_VAL 0x00029018 // GPIO33=FFDSR, GPIO34=FFRXD, GPIO38=FFRI, GPIO39=FFTXD, GPIO40=FFDTR
+ #define CONFIG_SYS_GAFR0_U_VAL 0x00c00010 // GPIO18=RDY, GPIO27=FFRTS
+ #define CONFIG_SYS_GAFR0_L_VAL 0x00100000 // GPIO10=FFDCD
+
+#else /* maximal vpac270 settings */
+ #define CONFIG_SYS_GPSR3_VAL 0x0161e800 // GPIO97
+ #define CONFIG_SYS_GPSR2_VAL 0x9228c000 // GPIO78-79, GPIO85, GPIO95
+ #define CONFIG_SYS_GPSR1_VAL 0x00cf0000 // GPIO48-51, GPIO54-55
+ #define CONFIG_SYS_GPSR0_VAL 0x01318800
+
+ #define CONFIG_SYS_GPCR3_VAL 0x0
+ #define CONFIG_SYS_GPCR2_VAL 0x0
+ #define CONFIG_SYS_GPCR1_VAL 0x0
+ #define CONFIG_SYS_GPCR0_VAL 0x0
+
+ #define CONFIG_SYS_GPDR3_VAL 0x0161e904 // GPIO98, GPIO104
+ #define CONFIG_SYS_GPDR2_VAL 0x922affff // GPIO64-79, GPIO85, GPIO95
+ #define CONFIG_SYS_GPDR1_VAL 0xfccfa981 // GPIO32, GPIO39-40, GPIO43, GPIO45, GPIO48-51, GPIO54-55, GPIO58-63
+ #define CONFIG_SYS_GPDR0_VAL 0xcbb18800 // GPIO11 GPIO15-16, GPIO20-21, GPIO27, GPIO30-31
+
+ #define CONFIG_SYS_GAFR3_U_VAL 0x00025401 // GPIO112=MMCMD
+ #define CONFIG_SYS_GAFR3_L_VAL 0x54010310 // GPIO98=AC97_SYSCLK, GPIO100=FFCTS, GPIO104=PSKTSEL, GPIO110=MMDAT2
+ #define CONFIG_SYS_GAFR2_U_VAL 0x41090401 // GPIO85=nPCE1, GPIO92=MMDAT0, GPIO95=AC97_RESET
+ #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa // GPIO64-73=LDD6-15, GPIO74=L_FCLK, GPIO75=L_LCLK,
+ // GPIO76=L_PCLK, GPIO77=L_BIAS, GPIO78=nCS2, GPIO79=nCS3
+ #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa // GPIO48=nPOE, GPIO49=nPWE, GPIO50=nPIOR, GPIO51=nPIOW
+ // GPIO54=nPCE2, GPIO55=nPREG, GPIO58-63=LDD0-5
+ #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a // GPIO32=MMCLK, GPIO33=FFDSR, GPIO34=FFRXD, GPIO38=FFRI, GPIO39=FFTXD
+ // GPIO40=FFDTR, GPIO42=BTRXD, GPIO43=BTTXD, GPIO44=BTCTS, GPIO45=BTRTS
+ #define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510 // GPIO18=RDY, GPIO20=SDCS2, GPIO21=SDCS3, GPIO27=FFRTS, GPIO28=AC97_BCLK
+ // GPIO29=AC97_SDATA_IN0, GPIO30=AC97_SDATA_OUT, GPIO31=AC97_SYNC
+ #define CONFIG_SYS_GAFR0_L_VAL 0x00100000 // GPIO10=FFDCD
+#endif
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x00500240 /* CKEN22_MEMC, CKEN20_SRAM, CKEN9_OSTM, CKEN6_FFUART */
+//#define CONFIG_SYS_CCCR 0x02000190 /* 312Mhz */
+#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */
+//#define CONFIG_SYS_CCCR 0x02000210 /* 416 Mhz */
+
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x3ffc95f2
+#define CONFIG_SYS_MSC1_VAL 0x02ccf974
+#define CONFIG_SYS_MSC2_VAL 0x00000000
+#define CONFIG_SYS_MDCNFG_VAL 0x8AD80AD8 // 11 cols, 13 rows, 4 banks, 32 bit
+//#define CONFIG_SYS_MDCNFG_VAL 0x08000AA8 // k4s281633d = 9cols,12rows,4banks
+//#define CONFIG_SYS_MDCNFG_VAL 0x08000AC8 // toradex dimm270 = 9cols,13rows,4banks
+//#define CONFIG_SYS_MDCNFG_VAL 0x88000AD0 // k4s511633f = 10cols,13rows,4banks
+//#define CONFIG_SYS_MDCNFG_VAL 0x88000AD8 // k4s511633f = 11cols,13rows,4banks
+#define CONFIG_SYS_MDREFR_VAL 0x0000001E
+#define CONFIG_SYS_MDMRS_VAL 0x00000000
+
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+#define CONFIG_SYS_MEM_BUF_IMP 0x0f /* factory default for PXA is 5 */
+
+#define BSCNTR0_OFFSET 0x4c
+#define BSCNTR1_OFFSET 0x50
+#define BSCNTR2_OFFSET 0x5c
+#define BSCNTR3_OFFSET 0x60
+
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001C787
+#define CONFIG_SYS_MCATT1_VAL 0x0001C787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430F
+#define CONFIG_SYS_MCIO1_VAL 0x0001430F
+
+/*
+ * Network card settings
+ */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+0x0004)
+
+
+/*
+ * FLASH support selection
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_SYS_FLASH_CFI
+//#define CONFIG_SYS_FLASH_ONENAND
+
+#ifdef CONFIG_SYS_FLASH_CFI
+ /*
+ * CFI flash support and environment organization
+ */
+ #define CONFIG_FLASH_CFI_DRIVER 1
+ #define CONFIG_SYS_FLASH_PROTECTION 1
+ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+ #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+ #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+ #define CONFIG_SYS_MAX_FLASH_SECT 260 /* max number of sectors on one chip */
+ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+ /* Flash environment locations */
+ #define CONFIG_ENV_IS_IN_FLASH 1
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
+ #define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+
+#elif defined(CONFIG_SYS_FLASH_ONENAND)
+ /*
+ * ONENAND flash support
+ */
+ #define CONFIG_FLASH_ONENAND_DRIVER 1
+ #define CONFIG_SYS_FLASH_PROTECTION 1
+ #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_FLASH_BASE
+
+ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+ /* Flash environment locations */
+ #define CONFIG_ENV_IS_IN_FLASH 1
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
+ #define CONFIG_ENV_SIZE (2*1024)
+ #define CONFIG_ENV_SECT_SIZE 0x20000
+#endif
+
+
+#endif /* __CONFIG_H */
--
1.7.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac
2010-03-29 12:24 [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac Mikhail Kshevetskiy
@ 2010-03-30 21:15 ` Wolfgang Denk
2010-04-07 11:46 ` Mikhail Kshevetskiy
2010-04-07 11:49 ` [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac [rev 2] Mikhail Kshevetskiy
2010-04-09 21:50 ` [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac Wolfgang Denk
1 sibling, 2 replies; 9+ messages in thread
From: Wolfgang Denk @ 2010-03-30 21:15 UTC (permalink / raw)
To: u-boot
Dear Mikhail Kshevetskiy,
In message <20100329162420.40f5433b@laska.campus-ws.pu.ru> you wrote:
> This patch is based on custom u-boot-1.1.2 version produced by voipac
> (http://www.voipac.com) and board/trizepsiv files from current u-boot.
>
> Up to now only PXA270 DIMM module with NOR flash is tested.
>
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
> ---
> Makefile | 3 +
> board/vpac270/Makefile | 51 +++
> board/vpac270/config.mk | 3 +
> board/vpac270/lowlevel_init.S | 740 +++++++++++++++++++++++++++++++++++++++++
> board/vpac270/vpac270.c | 101 ++++++
> include/configs/vpac270.h | 329 ++++++++++++++++++
> 6 files changed, 1227 insertions(+), 0 deletions(-)
> create mode 100644 board/vpac270/Makefile
> create mode 100644 board/vpac270/config.mk
> create mode 100644 board/vpac270/lowlevel_init.S
> create mode 100644 board/vpac270/vpac270.c
> create mode 100644 include/configs/vpac270.h
Entries to MAKEALL and MAINTAINERS missing.
> diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk
> new file mode 100644
> index 0000000..4486f6b
> --- /dev/null
> +++ b/board/vpac270/config.mk
> @@ -0,0 +1,3 @@
> +TEXT_BASE =0xa1f00000
> +# 0xa1700000
> +#TEXT_BASE = 0
Please do not add dead code. Remove it.
> diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S
> new file mode 100644
> index 0000000..1df381c
...
> +/* wait for coprocessor write complete */
> + .macro CPWAIT reg
> + mrc p15,0,\reg,c2,c0,0
> + mov \reg,\reg
> + sub pc,pc,#4
> + .endm
Indentation and vertial alignment by TAB only. Please fix globally.
> + /* Set up GPIO pins first ----------------------------------------- */
> +
> + ldr r0, =GPSR0
> + ldr r1, =CONFIG_SYS_GPSR0_VAL
> + str r1, [r0]
One TAB between instruction and arguments should be sufficient.
> + /* ---------------------------------------------------------------- */
> + /* Enable memory interface */
> + /* */
> + /* The sequence below is based on the recommended init steps */
> + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
> + /* Chapter 10. */
> + /* ---------------------------------------------------------------- */
Incorrect multiline comment style. Please fix globally.
...
> + /* MECR: Memory Expansion Card Register */
> + ldr r2, =CONFIG_SYS_MECR_VAL
> + str r2, [r1, #MECR_OFFSET]
> + ldr r2, [r1, #MECR_OFFSET]
Inconsistent indentation - please fix globally.
> + /* MCMEM0: Card Interface slot 0 timing */
> + ldr r2, =CONFIG_SYS_MCMEM0_VAL
> + str r2, [r1, #MCMEM0_OFFSET]
> + ldr r2, [r1, #MCMEM0_OFFSET]
> +
> + /* MCMEM1: Card Interface slot 1 timing */
> + ldr r2, =CONFIG_SYS_MCMEM1_VAL
> + str r2, [r1, #MCMEM1_OFFSET]
> + ldr r2, [r1, #MCMEM1_OFFSET]
> +
> + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
> + ldr r2, =CONFIG_SYS_MCATT0_VAL
> + str r2, [r1, #MCATT0_OFFSET]
> + ldr r2, [r1, #MCATT0_OFFSET]
> +
> + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
> + ldr r2, =CONFIG_SYS_MCATT1_VAL
> + str r2, [r1, #MCATT1_OFFSET]
> + ldr r2, [r1, #MCATT1_OFFSET]
> +
> + /* MCIO0: Card Interface I/O Space Timing, slot 0 */
> + ldr r2, =CONFIG_SYS_MCIO0_VAL
> + str r2, [r1, #MCIO0_OFFSET]
> + ldr r2, [r1, #MCIO0_OFFSET]
> +
> + /* MCIO1: Card Interface I/O Space Timing, slot 1 */
> + ldr r2, =CONFIG_SYS_MCIO1_VAL
> + str r2, [r1, #MCIO1_OFFSET]
> + ldr r2, [r1, #MCIO1_OFFSET]
> +
> + /* ---------------------------------------------------------------- */
> + /* Step 2c: Write FLYCNFG FIXME: what's that??? */
> + /* ---------------------------------------------------------------- */
> +@ ldr r2, =CONFIG_SYS_FLYCNFG_VAL
> +@ str r2, [r1, #FLYCNFG_OFFSET]
> +@ str r2, [r1, #FLYCNFG_OFFSET]
> +
> + /* ---------------------------------------------------------------- */
> + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
> + /* ---------------------------------------------------------------- */
> +
> + /* Before accessing MDREFR we need a valid DRI field, so we set */
> + /* this to power on defaults + DRI field. */
> +
> + ldr r4, [r1, #MDREFR_OFFSET]
> + ldr r2, =0xFFF
> + bic r4, r4, r2
> +
> + ldr r3, =CONFIG_SYS_MDREFR_VAL
> + and r3, r3, r2
> +
> + orr r4, r4, r3
> + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
Hm... I think most of this does not belong into lowlevel_init.S which
really should be kept minimal. Most of this should be rewritten in C.
> diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
> new file mode 100644
> index 0000000..723e9d8
> --- /dev/null
> +++ b/board/vpac270/vpac270.c
...
> +int board_late_init(void)
> +{
> +#if defined(CONFIG_SERIAL_MULTI)
> + char *console=getenv("boot_console");
> +
> + if (console == NULL) console = BOOT_CONSOLE;
Incorrect indentation. Please check and fix globally.
> diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
> new file mode 100644
> index 0000000..969d6d3
> --- /dev/null
> +++ b/include/configs/vpac270.h
...
> +//#define DEBUG 15
No C++ comments please. And don't add dead code.
...
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_BOOTCOMMAND "FIXME"
> +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS0,115200"
Line too long. Please fix globally.
> +#define CONFIG_STACKSIZE (64*1024) /* regular stack */
> +#ifdef CONFIG_USE_IRQ
> + #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
> + #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> +#endif
Indentation by TAB only!
> +/*
> + * GPIO settings
> + */
> +#if 1 /* minimal vpac270 settings, includes FFUART and Ethernet */
...
> +#else /* maximal vpac270 settings */
...
Do not add dead code. Remove the "#if 1" and the whole "else" block.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There's a way out of any cage.
-- Captain Christopher Pike, "The Menagerie" ("The Cage"),
stardate unknown.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac
2010-03-30 21:15 ` Wolfgang Denk
@ 2010-04-07 11:46 ` Mikhail Kshevetskiy
2010-04-09 22:41 ` Wolfgang Denk
2010-04-07 11:49 ` [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac [rev 2] Mikhail Kshevetskiy
1 sibling, 1 reply; 9+ messages in thread
From: Mikhail Kshevetskiy @ 2010-04-07 11:46 UTC (permalink / raw)
To: u-boot
Dear Wolfgang Denk,
Here is my comments to your notices,
the updated patch is in the following letter.
On Tue, 30 Mar 2010 23:15:45 +0200
Wolfgang Denk <wd@denx.de> wrote:
> Dear Mikhail Kshevetskiy,
>
> In message <20100329162420.40f5433b@laska.campus-ws.pu.ru> you wrote:
> > This patch is based on custom u-boot-1.1.2 version produced by voipac
> > (http://www.voipac.com) and board/trizepsiv files from current u-boot.
> >
> > Up to now only PXA270 DIMM module with NOR flash is tested.
> >
> > Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
> > ---
> > Makefile | 3 +
> > board/vpac270/Makefile | 51 +++
> > board/vpac270/config.mk | 3 +
> > board/vpac270/lowlevel_init.S | 740 +++++++++++++++++++++++++++++++++++++++++
> > board/vpac270/vpac270.c | 101 ++++++
> > include/configs/vpac270.h | 329 ++++++++++++++++++
> > 6 files changed, 1227 insertions(+), 0 deletions(-)
> > create mode 100644 board/vpac270/Makefile
> > create mode 100644 board/vpac270/config.mk
> > create mode 100644 board/vpac270/lowlevel_init.S
> > create mode 100644 board/vpac270/vpac270.c
> > create mode 100644 include/configs/vpac270.h
>
> Entries to MAKEALL and MAINTAINERS missing.
fixed
> > diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk
> > new file mode 100644
> > index 0000000..4486f6b
> > --- /dev/null
> > +++ b/board/vpac270/config.mk
> > @@ -0,0 +1,3 @@
> > +TEXT_BASE =0xa1f00000
> > +# 0xa1700000
> > +#TEXT_BASE = 0
>
> Please do not add dead code. Remove it.
fixed
> > diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S
> > new file mode 100644
> > index 0000000..1df381c
> ...
> > +/* wait for coprocessor write complete */
> > + .macro CPWAIT reg
> > + mrc p15,0,\reg,c2,c0,0
> > + mov \reg,\reg
> > + sub pc,pc,#4
> > + .endm
>
> Indentation and vertial alignment by TAB only. Please fix globally.
fixed,
I try to keep lowlevel_init.S as much close to the same file from board/trizeptiv
as it was possible, so initially i keep formatting and comments style from the
upstream version of board/trizeptiv/lowlevel_init.S.
>
> > + /* Set up GPIO pins first ----------------------------------------- */
> > +
> > + ldr r0, =GPSR0
> > + ldr r1, =CONFIG_SYS_GPSR0_VAL
> > + str r1, [r0]
>
> One TAB between instruction and arguments should be sufficient.
same as above
> > + /* ---------------------------------------------------------------- */
> > + /* Enable memory interface */
> > + /* */
> > + /* The sequence below is based on the recommended init steps */
> > + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
> > + /* Chapter 10. */
> > + /* ---------------------------------------------------------------- */
>
> Incorrect multiline comment style. Please fix globally.
same as above
> ...
> > + /* MECR: Memory Expansion Card Register */
> > + ldr r2, =CONFIG_SYS_MECR_VAL
> > + str r2, [r1, #MECR_OFFSET]
> > + ldr r2, [r1, #MECR_OFFSET]
>
> Inconsistent indentation - please fix globally.
same as above
> > + /* MCMEM0: Card Interface slot 0 timing */
> > + ldr r2, =CONFIG_SYS_MCMEM0_VAL
> > + str r2, [r1, #MCMEM0_OFFSET]
> > + ldr r2, [r1, #MCMEM0_OFFSET]
> > +
> > + /* MCMEM1: Card Interface slot 1 timing */
> > + ldr r2, =CONFIG_SYS_MCMEM1_VAL
> > + str r2, [r1, #MCMEM1_OFFSET]
> > + ldr r2, [r1, #MCMEM1_OFFSET]
> > +
> > + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
> > + ldr r2, =CONFIG_SYS_MCATT0_VAL
> > + str r2, [r1, #MCATT0_OFFSET]
> > + ldr r2, [r1, #MCATT0_OFFSET]
> > +
> > + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
> > + ldr r2, =CONFIG_SYS_MCATT1_VAL
> > + str r2, [r1, #MCATT1_OFFSET]
> > + ldr r2, [r1, #MCATT1_OFFSET]
> > +
> > + /* MCIO0: Card Interface I/O Space Timing, slot 0 */
> > + ldr r2, =CONFIG_SYS_MCIO0_VAL
> > + str r2, [r1, #MCIO0_OFFSET]
> > + ldr r2, [r1, #MCIO0_OFFSET]
> > +
> > + /* MCIO1: Card Interface I/O Space Timing, slot 1 */
> > + ldr r2, =CONFIG_SYS_MCIO1_VAL
> > + str r2, [r1, #MCIO1_OFFSET]
> > + ldr r2, [r1, #MCIO1_OFFSET]
> > +
> > + /* ---------------------------------------------------------------- */
> > + /* Step 2c: Write FLYCNFG FIXME: what's that??? */
> > + /* ---------------------------------------------------------------- */
> > +@ ldr r2, =CONFIG_SYS_FLYCNFG_VAL
> > +@ str r2, [r1, #FLYCNFG_OFFSET]
> > +@ str r2, [r1, #FLYCNFG_OFFSET]
> > +
> > + /* ---------------------------------------------------------------- */
> > + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
> > + /* ---------------------------------------------------------------- */
> > +
> > + /* Before accessing MDREFR we need a valid DRI field, so we set */
> > + /* this to power on defaults + DRI field. */
> > +
> > + ldr r4, [r1, #MDREFR_OFFSET]
> > + ldr r2, =0xFFF
> > + bic r4, r4, r2
> > +
> > + ldr r3, =CONFIG_SYS_MDREFR_VAL
> > + and r3, r3, r2
> > +
> > + orr r4, r4, r3
> > + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
>
>
> Hm... I think most of this does not belong into lowlevel_init.S which
> really should be kept minimal. Most of this should be rewritten in C.
the similar or exactly the same peace of code can be found in lowlevel
initialization of almost all arm/pxa boards, so i think it is reasonable to keep
this code in place.
> > diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
> > new file mode 100644
> > index 0000000..723e9d8
> > --- /dev/null
> > +++ b/board/vpac270/vpac270.c
> ...
> > +int board_late_init(void)
> > +{
> > +#if defined(CONFIG_SERIAL_MULTI)
> > + char *console=getenv("boot_console");
> > +
> > + if (console == NULL) console = BOOT_CONSOLE;
>
> Incorrect indentation. Please check and fix globally.
fixed,
The same as early, i try to keep this file similar to
board/trizeptiv/conxs.c file from the upstream.
>
> > diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
> > new file mode 100644
> > index 0000000..969d6d3
> > --- /dev/null
> > +++ b/include/configs/vpac270.h
> ...
> > +//#define DEBUG 15
>
> No C++ comments please. And don't add dead code.
fixed
> ...
> > +#define CONFIG_BOOTDELAY 3
> > +#define CONFIG_BOOTCOMMAND "FIXME"
> > +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS0,115200"
>
> Line too long. Please fix globally.
fixed
> > +#define CONFIG_STACKSIZE (64*1024) /* regular stack */
> > +#ifdef CONFIG_USE_IRQ
> > + #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
> > + #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> > +#endif
>
> Indentation by TAB only!
fixed
> > +/*
> > + * GPIO settings
> > + */
> > +#if 1 /* minimal vpac270 settings, includes FFUART and Ethernet */
> ...
> > +#else /* maximal vpac270 settings */
> ...
>
> Do not add dead code. Remove the "#if 1" and the whole "else" block.
fixed
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac [rev 2]
2010-03-30 21:15 ` Wolfgang Denk
2010-04-07 11:46 ` Mikhail Kshevetskiy
@ 2010-04-07 11:49 ` Mikhail Kshevetskiy
2010-04-09 22:39 ` Wolfgang Denk
1 sibling, 1 reply; 9+ messages in thread
From: Mikhail Kshevetskiy @ 2010-04-07 11:49 UTC (permalink / raw)
To: u-boot
This patch is based on custom u-boot-1.1.2 version produced by voipac
(http://www.voipac.com) and board/trizepsiv files from current u-boot.
Up to now only PXA270 DIMM module with NOR flash is tested.
v2: code style was improved
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
---
MAINTAINERS | 4 +
MAKEALL | 1 +
Makefile | 3 +
board/vpac270/Makefile | 51 +++
board/vpac270/config.mk | 1 +
board/vpac270/lowlevel_init.S | 735 +++++++++++++++++++++++++++++++++++++++++
board/vpac270/vpac270.c | 103 ++++++
include/configs/vpac270.h | 408 +++++++++++++++++++++++
8 files changed, 1306 insertions(+), 0 deletions(-)
create mode 100644 board/vpac270/Makefile
create mode 100644 board/vpac270/config.mk
create mode 100644 board/vpac270/lowlevel_init.S
create mode 100644 board/vpac270/vpac270.c
create mode 100644 include/configs/vpac270.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 80057ce..f84b6f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -525,6 +525,10 @@ Stefano Babic <sbabic@denx.de>
polaris xscale
trizepsiv xscale
+Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
+
+ vpac270 xscale
+
Dirk Behme <dirk.behme@gmail.com>
omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC)
diff --git a/MAKEALL b/MAKEALL
index 5c303f9..78ba2af 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -692,6 +692,7 @@ LIST_pxa=" \
polaris \
pxa255_idp \
trizepsiv \
+ vpac270 \
wepep250 \
xaeniax \
xm250 \
diff --git a/Makefile b/Makefile
index e141cb2..20cceba 100644
--- a/Makefile
+++ b/Makefile
@@ -3250,6 +3250,9 @@ trizepsiv_config : unconfig
fi;
@$(MKCONFIG) -a trizepsiv arm pxa trizepsiv
+vpac270_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm pxa vpac270
+
wepep250_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa wepep250
diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile
new file mode 100644
index 0000000..500e075
--- /dev/null
+++ b/board/vpac270/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := vpac270.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk
new file mode 100644
index 0000000..e798bc3
--- /dev/null
+++ b/board/vpac270/config.mk
@@ -0,0 +1 @@
+TEXT_BASE =0xa1f00000
diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S
new file mode 100644
index 0000000..3e8bb5b
--- /dev/null
+++ b/board/vpac270/lowlevel_init.S
@@ -0,0 +1,735 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+.macro CPWAIT reg
+ mrc p15, 0, \reg, c2, c0, 0
+ mov \reg, \reg
+ sub pc, pc, #4
+.endm
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Set up GPIO pins first ----------------------------------------- */
+ ldr r0, =GPSR0
+ ldr r1, =CONFIG_SYS_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CONFIG_SYS_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CONFIG_SYS_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR3
+ ldr r1, =CONFIG_SYS_GPSR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CONFIG_SYS_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CONFIG_SYS_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CONFIG_SYS_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR3
+ ldr r1, =CONFIG_SYS_GPCR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CONFIG_SYS_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CONFIG_SYS_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CONFIG_SYS_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR3
+ ldr r1, =CONFIG_SYS_GPDR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CONFIG_SYS_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CONFIG_SYS_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CONFIG_SYS_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CONFIG_SYS_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CONFIG_SYS_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CONFIG_SYS_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_L
+ ldr r1, =CONFIG_SYS_GAFR3_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_U
+ ldr r1, =CONFIG_SYS_GAFR3_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CONFIG_SYS_PSSR_VAL
+ str r1, [r0]
+
+ /* ----------------------------------------------------------------
+ * Enable memory interface
+ *
+ * The sequence below is based on the recommended init steps
+ * detailed in the Intel PXA250 Operating Systems Developers Guide,
+ * Chapter 10.
+ * ---------------------------------------------------------------- */
+
+ /* ----------------------------------------------------------------
+ * Step 1: Wait for at least 200 microsedonds to allow internal
+ * clocks to settle. Only necessary after hard reset...
+ * FIXME: can be optimized later
+ * ---------------------------------------------------------------- */
+
+ mov r10, lr
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec,
+ * so 0x300 should be plenty
+ */
+ at 1:
+@ ldr r2, [r3]
+@ cmp r4, r2
+@ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ----------------------------------------------------------------
+ * Step 2a: Initialize Asynchronous static memory controller
+ * ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, [r1, #MSC0_OFFSET]
+ tst r2, #8 /* test bus width */
+ ldr r2, =CONFIG_SYS_MSC0_VAL
+ biceq r2, r2, #8
+ orrne r2, r2, #8
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure
+ * that data latches
+ */
+
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CONFIG_SYS_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CONFIG_SYS_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ----------------------------------------------------------------
+ * Step 2b: Initialize Card Interface
+ * ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CONFIG_SYS_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CONFIG_SYS_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CONFIG_SYS_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CONFIG_SYS_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CONFIG_SYS_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CONFIG_SYS_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CONFIG_SYS_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ----------------------------------------------------------------
+ * Step 2c: Write FLYCNFG FIXME: what's that???
+ * ---------------------------------------------------------------- */
+@ ldr r2, =CONFIG_SYS_FLYCNFG_VAL
+@ str r2, [r1, #FLYCNFG_OFFSET]
+@ str r2, [r1, #FLYCNFG_OFFSET]
+
+ /* ----------------------------------------------------------------
+ * Step 2d: Initialize Timing for Sync Memory (SDCLK0)
+ * ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set
+ * this to power on defaults + DRI field.
+ */
+
+ ldr r4, [r1, #MDREFR_OFFSET]
+ ldr r2, =0xFFF
+ bic r4, r4, r2
+
+ ldr r3, =CONFIG_SYS_MDREFR_VAL
+ and r3, r3, r2
+
+ orr r4, r4, r3
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+
+ orr r4, r4, #MDREFR_K0RUN
+ orr r4, r4, #MDREFR_K0DB4
+ orr r4, r4, #MDREFR_K0FREE
+ orr r4, r4, #MDREFR_K0DB2
+ orr r4, r4, #MDREFR_K1DB2
+ orr r4, r4, #MDREFR_K2DB2
+ bic r4, r4, #MDREFR_K1FREE
+ bic r4, r4, #MDREFR_K2FREE
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Note: preserve the mdrefr value in r4 */
+
+
+ /* ----------------------------------------------------------------
+ * Step 3: Initialize Synchronous Static Memory (Flash/Peripherals)
+ * ----------------------------------------------------------------
+ *
+ * Initialize SXCNFG register. Assert the enable bits
+ *
+ * Write SXMRS to cause an MRS command to all enabled banks of
+ * synchronous static memory. Note that SXLCR need not be written
+ * at this time.
+ */
+
+ ldr r2, =CONFIG_SYS_SXCNFG_VAL
+ str r2, [r1, #SXCNFG_OFFSET]
+
+ /* ----------------------------------------------------------------
+ * Step 4: Initialize SDRAM
+ * ---------------------------------------------------------------- */
+
+ bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+ orr r4, r4, #MDREFR_K1RUN
+ orr r4, r4, #MDREFR_K2RUN
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ bic r4, r4, #MDREFR_SLFRSH
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ orr r4, r4, #MDREFR_E1PIN
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ nop
+ nop
+
+#if defined(CONFIG_SYS_MEM_BUF_IMP)
+ /* Step 4a: set memory buffer strengths */
+ ldr r3, =CONFIG_SYS_MEM_BUF_IMP
+ and r3, r3, #0x0f
+
+ /* now, copy those 4 bits to all 8 sub-registers (into r2): */
+ mov r2, r3
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+ mov r2, r2, LSL #4
+ orr r2, r3, r2
+
+ str r2, [r1, #BSCNTR0_OFFSET]
+ str r2, [r1, #BSCNTR2_OFFSET]
+ str r2, [r1, #BSCNTR3_OFFSET]
+
+ /* BSCNTR1 is special, as it holds SDCAS_DELAY in bits 7:4 */
+ ldr r3, [r1, #BSCNTR1_OFFSET]
+ and r3, r3, #0xf0
+ bic r2, r2, #0xf0
+ orr r2, r3, r2
+ str r2, [r1, #BSCNTR1_OFFSET]
+
+ /* read back to make sure it's done: */
+ ldr r3, [r1, #BSCNTR1_OFFSET]
+#endif
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to
+ * configure but not enable each SDRAM partition pair.
+ */
+ ldr r4, =CONFIG_SYS_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+ bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize,
+ * 100..200 usec.
+ */
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec,
+ * so 0x300 should be plenty
+ */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by
+ * attempting non-burst read or write accesses to disabled
+ * SDRAM, as commonly specified in the power up sequence
+ * documented in SDRAM data sheets. The address(es) used
+ * for this purpose must not be cacheable.
+ */
+ ldr r3, =PHYS_SDRAM_1
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+ ldr r3, =PHYS_SDRAM_2
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+ /* Step 4g: Write MDCNFG with enable bits asserted
+ * (MDCNFG:DEx set to 1).
+ */
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ mov r4, r3
+ orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
+ orr r3, r3, #(MDCNFG_DE2|MDCNFG_DE3)
+ str r3, [r1, #MDCNFG_OFFSET]
+ mov r0, r3
+
+ /* Step 4h: Write MDMRS. */
+ ldr r2, =CONFIG_SYS_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+ /* enable APD */
+ ldr r3, [r1, #MDREFR_OFFSET]
+ orr r3, r3, #MDREFR_APD
+ str r3, [r1, #MDREFR_OFFSET]
+
+ /* Step 5: Autodetect SDRAM size and bus width */
+ ldr r3, =PHYS_SDRAM_1 /* bank0, partition0/1 */
+
+ bl get_bus_width
+
+ /* set detected bank0 bus width */
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ orr r2, r2, r0
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* check sdram bank0 present */
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+ bic r2, r2, #0x3700
+ bic r2, r2, #0x00ff
+ ldr r4, [r3]
+ cmp r0, r4
+ bne bank0disable
+
+ ldr r0, =0xdeadbeef
+ str r0, [r3] /* a0000000 = deadbeef */
+ ldr r4, [r3]
+ cmp r0, r4
+ bne bank0disable
+
+ /* set column probe offset */
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ tst r2, #0x04 /* bank0 16/32bit wide bus ? */
+ mov r4, #0x200
+ addeq r4, r4, r4 /* 0x200 (16bit), 0x400 (32bit) */
+
+ bl get_columns
+
+ /* set detected columns */
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ bic r2, r2, #0x18
+ bic r2, r2, #0x4000
+ orr r2, r2, r0
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* set row probe offset */
+ tst r2, #0x04 /* bank0 16/32bit wide bus ? */
+ mov r4, #0x800000
+ addeq r4, r4, r4 /* 0x800000 (16bit),
+ * 0x1000000 (32bit)
+ */
+
+ bl get_rows
+
+ /* set detected rows */
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ bic r2, r2, #0x60
+ orr r2, r2, r0
+
+bank0disable:
+ str r2, [r1, #MDCNFG_OFFSET]
+ ldr r3, =PHYS_SDRAM_2 /* bank1, partition2/3 */
+
+ bl get_bus_width
+
+ /* set detected bank0 bus width */
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ orr r2, r2, r0, LSL#16
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* check sdram bank1 present */
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+ bic r2, r2, #0x37000000
+ bic r2, r2, #0x00ff0000
+ ldr r4, [r3]
+ cmp r0, r4
+ bne bank1disable
+
+ ldr r0, =0xdeadbeef
+ str r0, [r3] /* a0000000 = deadbeef */
+ ldr r4, [r3]
+ cmp r0, r4
+ bne bank1disable
+
+ /* set column probe offset */
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ tst r2, #0x40000 /* bank1 16/32bit wide bus ? */
+ mov r4, #0x200
+ addeq r4, r4, r4 /* 0x200 (16bit), 0x400 (32bit) */
+
+ bl get_columns
+
+ /* set detected columns */
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ bic r2, r2, #0x180000
+ bic r2, r2, #0x40000000
+ orr r2, r2, r0, LSL#16
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* set row probe offset */
+ tst r2, #0x40000 /* bank1 16/32bit wide bus ? */
+ mov r4, #0x800000
+ addeq r4, r4, r4 /* 0x800000 (16bit),
+ * 0x1000000 (32bit)
+ */
+
+ bl get_rows
+
+ /* set detected rows */
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ bic r2, r2, #0x600000
+ orr r2, r2, r0, LSL#16
+
+bank1disable:
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* We are finished with Intel's memory controller initialisation */
+
+
+ at setvoltage:
+@ mov r10, lr
+@ bl initPXAvoltage /* In case the board is rebooting with a */
+@ mov lr, r10 /* low voltage raise it up to a good one. */
+
+wakeup:
+ /* Are we waking from sleep? */
+ mov r1, #0x01
+ ldr r0, =RCSR
+ str r1, [r0]
+ ldr r1, [r0]
+ and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+ str r1, [r0]
+ teq r1, #RCSR_SMR
+
+ bne initirqs
+
+ ldr r0, =PSSR
+ mov r1, #PSSR_PH
+ str r1, [r0]
+
+ /* if so, resume at PSPR */
+ ldr r0, =PSPR
+ ldr r1, [r0]
+ mov pc, r1
+
+
+ /* ----------------------------------------------------------------
+ * Disable (mask) all interrupts at interrupt controller
+ * ---------------------------------------------------------------- */
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+
+ /* ----------------------------------------------------------------
+ * Clock initialisation
+ * ---------------------------------------------------------------- */
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency
+ * Turn Off on-chip peripheral clocks (except for memory)
+ * for re-configuration.
+ */
+ ldr r1, =CKEN
+ ldr r2, =CONFIG_SYS_CKEN
+ str r2, [r1]
+
+ /* ... and write the core clock config register */
+ ldr r2, =CONFIG_SYS_CCCR
+ ldr r1, =CCCR
+ str r2, [r1]
+
+ /* Turn on turbo mode */
+ mrc p14, 0, r2, c6, c0, 0
+ orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change */
+ mcr p14, 0, r2, c6, c0, 0
+
+ /* Re-write MDREFR */
+ ldr r1, =MEMC_BASE
+ ldr r2, [r1, #MDREFR_OFFSET]
+ str r2, [r1, #MDREFR_OFFSET]
+
+#ifdef RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL
+ /* has settled.
+ */
+60:
+ ldr r2, [r1]
+@ ands r2, r2, #1
+@ beq 60b
+#else
+ #error "RTC not defined"
+#endif
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+ /* FIXME */
+
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0, #0
+ mcr p15, 0, r0, c14, c8, 0 /* ibcr0 */
+ mcr p15, 0, r0, c14, c9, 0 /* ibcr1 */
+ mcr p15, 0, r0, c14, c4, 0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0, #0x80000000
+ mcr p14, 0, r0, c10, c0, 0 /* dcsr */
+#endif
+
+
+ /* ----------------------------------------------------------------
+ * End lowlevel_init
+ * ---------------------------------------------------------------- */
+endlowlevel_init:
+ mov lr, r10
+ mov pc, lr
+
+
+ /* Step 5a: Detect bus width 16/32bits */
+get_bus_width:
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+ ldr r2, =0xdeadbeef
+ str r2, [r3] /* a0000000 = 0xdeadbeef */
+
+ ldr r0, [r3] /* a0000000 */
+ cmp r0, r2
+ mov r0, #0
+ orrne r0, r0, #0x04
+
+ mov pc, lr
+
+
+ /* Step 5b: Detect number of columns */
+get_columns:
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+
+ add r0, r0, r4
+ str r0, [r3, r0] /* a0000200 (16bit), a0000400 (32bit) */
+
+ add r0, r0, r0
+ str r0, [r3, r0] /* a0000400 (16bit), a0000800 (32bit) */
+
+ add r0, r0, r0
+ str r0, [r3, r0] /* a0000800 (16bit), a0001000 (32bit) */
+
+ add r0, r0, r0
+ str r0, [r3, r0] /* a0001000 (16bit), a0002000 (32bit) */
+
+ ldr r2, =0xdeadbeef
+ str r2, [r3] /* a0000000 = 0xdeadbeef */
+
+ ldr r0, [r3, r4] /* a0000200 (16bit), a0000400 (32bit) */
+ cmp r0, r2
+ mov r0, #0 /* 8 columns, DCAC0 = 0 */
+ beq setcols
+
+ add r4, r4, r4
+ ldr r0, [r3, r4] /* a0000400 (16bit), a0000800 (32bit) */
+ cmp r0, r2
+ mov r0, #8 /* 9 columns, DCAC0 = 1 */
+ beq setcols
+
+ add r4, r4, r4
+ ldr r0, [r3, r4] /* a0000800 (16bit), a0001000 (32bit) */
+ cmp r0, r2
+ mov r0, #0x10 /* 10 columns, DCAC0 = 2 */
+ beq setcols
+
+@ add r4, r4, r4
+@ ldr r0, [r3, r4] /* a0001000 (16bit), a0002000 (32bit) */
+@ cmp r0, r2
+ mov r0, #0x18 /* 11 columns, DCAC0 = 3 */
+@ beq setcols
+
+@ mov r0, #0x4000 /* 12 columns, DCAC0 = 0, DCACX0 = 1 */
+
+setcols:
+ mov pc, lr
+
+
+ /* Step 5c: Detect number of rows */
+get_rows:
+ mov r0, #0
+ str r0, [r3] /* a0000000 = 0 */
+
+ add r0, r0, r4
+ str r0, [r3, r0] /* a0800000 (16bit), a1000000 (32bit) */
+
+ add r0, r0, r0
+ str r0, [r3, r0] /* a1000000 (16bit), a2000000 (32bit) */
+
+ ldr r2, =0xdeadbeef
+ str r2, [r3] /* a0000000 = 0xdeadbeef */
+
+ ldr r0, [r3, r4] /* a0800000 (16bit), a1000000 (32bit */
+ cmp r0, r2
+ mov r0, #0 /* 11 rows, DRAC0 = 0 */
+ beq setrows
+
+ add r4, r4, r4
+ ldr r0, [r3, r4] /* a1000000 (16bit), a2000000 (32bit) */
+ cmp r0, r2
+ mov r0, #0x20 /* 12 rows, DRAC0 = 1 */
+ beq setrows
+
+ mov r0, #0x40 /* 13 rows, DRAC0 = 2 */
+
+setrows:
+ mov pc, lr
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
new file mode 100644
index 0000000..5502550
--- /dev/null
+++ b/board/vpac270/vpac270.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley at applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+#define BOOT_CONSOLE "serial_ffuart"
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ char *console = getenv("boot_console");
+
+ if (console == NULL)
+ console = BOOT_CONSOLE;
+
+ setenv("stdin", console);
+ setenv("stdout", console);
+ setenv("stderr", console);
+#endif
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_ffuart_device;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
new file mode 100644
index 0000000..bbf747c
--- /dev/null
+++ b/include/configs/vpac270.h
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2005
+ * Detlef Vollmann, Toradex AG, <dv@vollmann.ch>
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley at applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the VPAC270 module
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
+#define CONFIG_VPAC270 1 /* on a voipac module */
+#define CONFIG_VPAC270_MINIMAL_SETTINGS 1 /* use minimal gpio settings */
+
+#undef BOARD_LATE_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ */
+
+#define RTC 1
+
+
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + 128 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_FFUART 1 /* we use FFUART on voipac */
+#define CONFIG_BTUART 1 /* we use BTUART on voipac */
+#define CONFIG_STUART 1 /* we use STUART on voipac */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200, 230400 }
+
+#define CONFIG_BAUDRATE 115200
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_PING /* ping support */
+#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_DIAG /* Diagnostics */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_IPADDR 192.168.1.48
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_ETHADDR 00:01:02:03:04:05
+#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
+
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTCOMMAND "FIXME"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock2 rootfstype=jffs2"
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "u-boot> "
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4--8 MB in DRAM */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0xa1000000
+
+#define CONFIG_SYS_HZ 1000
+
+/* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+#define CONFIG_SYS_CPUSPEED 0x190
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (64*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+ #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+ #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 bank of DRAM,
+ * but we have room for 4
+ */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
+
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+
+/*
+ * GPIO settings
+ */
+#ifdef CONFIG_VPAC270_MINIMAL_SETTINGS
+ /* minimal vpac270 settings, includes FFUART and Ethernet */
+ #define CONFIG_SYS_GPSR0_VAL 0x00000000
+ #define CONFIG_SYS_GPSR1_VAL 0x00020000 /* GPIO49 */
+ #define CONFIG_SYS_GPSR2_VAL 0x0000c000 /* GPIO78, GPIO79 */
+ #define CONFIG_SYS_GPSR3_VAL 0x00000000
+
+
+ #define CONFIG_SYS_GPCR0_VAL 0x0
+ #define CONFIG_SYS_GPCR1_VAL 0x0
+ #define CONFIG_SYS_GPCR2_VAL 0x0
+ #define CONFIG_SYS_GPCR3_VAL 0x0
+
+
+ /* GPIO27 */
+ #define CONFIG_SYS_GPDR0_VAL 0x08000000
+ /* GPIO39, GPIO40, GPIO49 */
+ #define CONFIG_SYS_GPDR1_VAL 0x00020180
+ /* GPIO78, GPIO79 */
+ #define CONFIG_SYS_GPDR2_VAL 0x0000c000
+ #define CONFIG_SYS_GPDR3_VAL 0x00000000
+
+
+ /* GPIO10=FFDCD */
+ #define CONFIG_SYS_GAFR0_L_VAL 0x00100000
+ /* GPIO18=RDY, GPIO27=FFRTS */
+ #define CONFIG_SYS_GAFR0_U_VAL 0x00c00010
+ /* GPIO33=FFDSR, GPIO34=FFRXD, GPIO38=FFRI, GPIO39=FFTXD,
+ * GPIO40=FFDTR
+ */
+ #define CONFIG_SYS_GAFR1_L_VAL 0x00029018
+ /* GPIO49=nPWE */
+ #define CONFIG_SYS_GAFR1_U_VAL 0x00000008
+ /* GPIO78=nCS2, GPIO79=nCS3 */
+ #define CONFIG_SYS_GAFR2_L_VAL 0xa0000000
+ #define CONFIG_SYS_GAFR2_U_VAL 0x00000000
+ /* GPIO100=FFCTS */
+ #define CONFIG_SYS_GAFR3_L_VAL 0x00000300
+ #define CONFIG_SYS_GAFR3_U_VAL 0x00000000
+#else
+ /* maximal vpac270 settings */
+ #define CONFIG_SYS_GPSR0_VAL 0x01318800
+ /* GPIO48-51, GPIO54-55 */
+ #define CONFIG_SYS_GPSR1_VAL 0x00cf0000
+ /* GPIO78-79, GPIO85, GPIO95 */
+ #define CONFIG_SYS_GPSR2_VAL 0x9228c000
+ /* GPIO97 */
+ #define CONFIG_SYS_GPSR3_VAL 0x0161e800
+
+
+ #define CONFIG_SYS_GPCR0_VAL 0x0
+ #define CONFIG_SYS_GPCR1_VAL 0x0
+ #define CONFIG_SYS_GPCR2_VAL 0x0
+ #define CONFIG_SYS_GPCR3_VAL 0x0
+
+
+ /* GPIO11, GPIO15-16, GPIO20-21, GPIO27, GPIO30-31 */
+ #define CONFIG_SYS_GPDR0_VAL 0xcbb18800
+ /* GPIO32, GPIO39-40, GPIO43, GPIO45, GPIO48-51, GPIO54-55, GPIO58-63 */
+ #define CONFIG_SYS_GPDR1_VAL 0xfccfa981
+ /* GPIO64-79, GPIO85, GPIO95 */
+ #define CONFIG_SYS_GPDR2_VAL 0x922affff
+ /* GPIO98, GPIO104 */
+ #define CONFIG_SYS_GPDR3_VAL 0x0161e904
+
+
+ /* GPIO10=FFDCD */
+ #define CONFIG_SYS_GAFR0_L_VAL 0x00100000
+ /* GPIO18=RDY, GPIO20=SDCS2, GPIO21=SDCS3, GPIO27=FFRTS,
+ * GPIO28=AC97_BCLK, GPIO29=AC97_SDATA_IN0, GPIO30=AC97_SDATA_OUT,
+ * GPIO31=AC97_SYNC
+ */
+ #define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510
+ /* GPIO32=MMCLK, GPIO33=FFDSR, GPIO34=FFRXD, GPIO38=FFRI, GPIO39=FFTXD,
+ * GPIO40=FFDTR, GPIO42=BTRXD, GPIO43=BTTXD, GPIO44=BTCTS, GPIO45=BTRTS
+ */
+ #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
+ /* GPIO48=nPOE, GPIO49=nPWE, GPIO50=nPIOR, GPIO51=nPIOW, GPIO54=nPCE2,
+ * GPIO55=nPREG, GPIO58-63=LDD0-5
+ */
+ #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa
+ /* GPIO64-73=LDD6-15, GPIO74=L_FCLK, GPIO75=L_LCLK, GPIO76=L_PCLK,
+ * GPIO77=L_BIAS, GPIO78=nCS2, GPIO79=nCS3
+ */
+ #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
+ /* GPIO85=nPCE1, GPIO92=MMDAT0, GPIO95=AC97_RESET */
+ #define CONFIG_SYS_GAFR2_U_VAL 0x41090401
+ /* GPIO98=AC97_SYSCLK, GPIO100=FFCTS, GPIO104=PSKTSEL, GPIO110=MMDAT2 */
+ #define CONFIG_SYS_GAFR3_L_VAL 0x54010310
+ /* GPIO112=MMCMD */
+ #define CONFIG_SYS_GAFR3_U_VAL 0x00025401
+#endif
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+
+/*
+ * Clock settings
+ */
+
+/* CKEN22_MEMC, CKEN20_SRAM, CKEN9_OSTM, CKEN6_FFUART */
+#define CONFIG_SYS_CKEN 0x00500240
+/* CPU frequence:
+ * 312 Mhz CCCR = 0x02000190
+ * 416 Mhz CCCR = 0x02000210
+ * 520 Mhz CCCR = 0x02000290
+ */
+#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */
+
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x3ffc95f2
+#define CONFIG_SYS_MSC1_VAL 0x02ccf974
+#define CONFIG_SYS_MSC2_VAL 0x00000000
+
+/* 11 cols, 13 rows, 4 banks, 32 bit */
+#define CONFIG_SYS_MDCNFG_VAL 0x8AD80AD8
+
+#define CONFIG_SYS_MDREFR_VAL 0x0000001E
+#define CONFIG_SYS_MDMRS_VAL 0x00000000
+
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+/* factory default for PXA is 5 */
+#define CONFIG_SYS_MEM_BUF_IMP 0x0f
+
+#define BSCNTR0_OFFSET 0x4c
+#define BSCNTR1_OFFSET 0x50
+#define BSCNTR2_OFFSET 0x5c
+#define BSCNTR3_OFFSET 0x60
+
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001C787
+#define CONFIG_SYS_MCATT1_VAL 0x0001C787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430F
+#define CONFIG_SYS_MCIO1_VAL 0x0001430F
+
+/*
+ * Network card settings
+ */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+0x0004)
+
+
+/*
+ * FLASH support selection
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+/* accroding u-boot.map, the size of u-boot (from the beginning of .text
+ * section till the end of .bss section) in my case is 0x1EEA4 bytes.
+ * The CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN should be aligned
+ * to the flash sector boundary, so the value 0x20000 suit fine.
+ * (use 'flinfo' u-boot command to obtain the flash sector layout)
+ */
+#define CONFIG_SYS_MONITOR_LEN 0x20000
+
+#define CONFIG_SYS_FLASH_CFI
+#undef CONFIG_SYS_FLASH_ONENAND
+
+#ifdef CONFIG_SYS_FLASH_CFI
+ /*
+ * CFI flash support and environment organization
+ */
+ #define CONFIG_FLASH_CFI_DRIVER 1
+ #define CONFIG_SYS_FLASH_PROTECTION 1
+ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+ /* Timeout for Flash Erase */
+ #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
+ /* Timeout for Flash Write */
+ #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
+
+ /* max number of memory banks */
+ #define CONFIG_SYS_MAX_FLASH_BANKS 1
+ /* max number of sectors on one chip */
+ #define CONFIG_SYS_MAX_FLASH_SECT 260
+ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+ /* Flash environment locations */
+ #define CONFIG_ENV_IS_IN_FLASH 1
+
+ /* Addr of Environment Sector */
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+ /* Total Size of Environment */
+ #define CONFIG_ENV_SIZE (4 * 1024)
+ /* Total Size of Environment Sector */
+ #define CONFIG_ENV_SECT_SIZE 0x20000
+
+#elif defined(CONFIG_SYS_FLASH_ONENAND)
+ /*
+ * ONENAND flash support
+ */
+ #define CONFIG_FLASH_ONENAND_DRIVER 1
+ #define CONFIG_SYS_FLASH_PROTECTION 1
+ #define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_FLASH_BASE
+
+ /* max number of memory banks */
+ #define CONFIG_SYS_MAX_FLASH_BANKS 1
+ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+ /* Flash environment locations */
+ #define CONFIG_ENV_IS_IN_FLASH 1
+
+ /* Addr of Environment Sector */
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+ /* Total Size of Environment */
+ #define CONFIG_ENV_SIZE (4 * 1024)
+ /* Total Size of Environment Sector */
+ #define CONFIG_ENV_SECT_SIZE 0x20000
+#endif
+
+
+#endif /* __CONFIG_H */
--
1.7.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac
2010-03-29 12:24 [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac Mikhail Kshevetskiy
2010-03-30 21:15 ` Wolfgang Denk
@ 2010-04-09 21:50 ` Wolfgang Denk
1 sibling, 0 replies; 9+ messages in thread
From: Wolfgang Denk @ 2010-04-09 21:50 UTC (permalink / raw)
To: u-boot
Dear Mikhail Kshevetskiy,
In message <20100329162420.40f5433b@laska.campus-ws.pu.ru> you wrote:
> This patch is based on custom u-boot-1.1.2 version produced by voipac
> (http://www.voipac.com) and board/trizepsiv files from current u-boot.
>
> Up to now only PXA270 DIMM module with NOR flash is tested.
>
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
> ---
> Makefile | 3 +
> board/vpac270/Makefile | 51 +++
> board/vpac270/config.mk | 3 +
> board/vpac270/lowlevel_init.S | 740 +++++++++++++++++++++++++++++++++++++++++
> board/vpac270/vpac270.c | 101 ++++++
> include/configs/vpac270.h | 329 ++++++++++++++++++
> 6 files changed, 1227 insertions(+), 0 deletions(-)
> create mode 100644 board/vpac270/Makefile
> create mode 100644 board/vpac270/config.mk
> create mode 100644 board/vpac270/lowlevel_init.S
> create mode 100644 board/vpac270/vpac270.c
> create mode 100644 include/configs/vpac270.h
Entries to MAKEALL and MAINTAINERS missing.
> --- /dev/null
> +++ b/board/vpac270/config.mk
> @@ -0,0 +1,3 @@
> +TEXT_BASE xa1f00000
> +# 0xa1700000
> +#TEXT_BASE 0
Please do not adde dead code. Please fix globally.
> diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S
> new file mode 100644
> index 0000000..1df381c
> --- /dev/null
> +++ b/board/vpac270/lowlevel_init.S
> @@ -0,0 +1,740 @@
> +/*
> + * This was originally from the Lubbock u-boot port.
> + *
> + * Most of this taken from Redboot hal_platform_setup.h with cleanup
> + *
> + * NOTE: I haven't clean this up considerably, just enough to get it
> + * running. See hal_platform_setup.h for the source. See
> + * board/cradle/lowlevel_init.S for another PXA250 setup that is
> + * much cleaner.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +#include <asm/arch/pxa-regs.h>
> +
> +/* wait for coprocessor write complete */
> + .macro CPWAIT reg
> + mrc p15,0,\reg,c2,c0,0
> + mov \reg,\reg
> + sub pc,pc,#4
> + .endm
Indentation by TAB only. Please fix globally.
> + /* Set up GPIO pins first ----------------------------------------- */
> +
> + ldr r0, GPSR0
> + ldr r1, ONFIG_SYS_GPSR0_VAL
> + str r1, [r0]
One TAB should be enough to separate insn and args.
> +#ifdef NODEBUG
Please don't add dead code, not even like this.
> + /*Disable software and data breakpoints */
> + mov r0,#0
> + mcr p15,0,r0,c14,c8,0 /* ibcr0 */
> + mcr p15,0,r0,c14,c9,0 /* ibcr1 */
> + mcr p15,0,r0,c14,c4,0 /* dbcon */
> +
> + /*Enable all debug functionality */
> + mov r0,#0x80000000
> + mcr p14,0,r0,c10,c0,0 /* dcsr */
> +#endif
> +/* ------------------------------------------------------------------------- */
> +
> +/*
> + * Miscelaneous platform dependent initialisations
> + */
Typos. s/l/ll/, s/sat/zat/
> +int board_init (void)
> +{
> + /* memory and cpu-speed are setup before relocation */
> + /* so we do _nothing_ here */
incorrect multiline comment style.
> +int board_late_init(void)
> +{
> +#if defined(CONFIG_SERIAL_MULTI)
> + char *consolegetenv("boot_console");
> +
> + if (console NULL) console BOOT_CONSOLE;
Incorrect indentation. What the heck is "console BOOT_CONSOLE" ???
> +++ b/include/configs/vpac270.h
> @@ -0,0 +1,329 @@
> +/*
> + * (C) Copyright 2005
> + * Detlef Vollmann, Toradex AG, <dv@vollmann.ch>
> + *
> + * (C) Copyright 2004
> + * Robert Whaley, Applied Data Systems, Inc. rwhaley at applieddata.net
> + *
> + * (C) Copyright 2002
> + * Kyle Harris, Nexus Technologies, Inc. kharris at nexus-tech.net
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
Is it really true that all these people have contributed significant
parts to that file, and at the given dates?
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +//#define DEBUG 15
No C++ comments. Please fix globally.
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + 128*1024)
> +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
Line too long. Please fix globally.
> +#define CONFIG_PXA_SERIAL
> +#define CONFIG_SERIAL_MULTI
> +#define CONFIG_FFUART 1 /* we use FFUART on Colibri */
> +#define CONFIG_BTUART 1 /* we use BTUART on Colibri */
> +#define CONFIG_STUART 1 /* we use STUART on Colibri */
On colibri? Is the comment really correct?
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_SERVERIP 192.168.1.1
> +#define CONFIG_IPADDR 192.168.1.48
> +#define CONFIG_NETMASK 255.255.255.0
> +#define CONFIG_ETHADDR 00:01:02:03:04:05
NAK. Remove this stuff, it makes no sense. Especially not with a
stolen MAC address (00:01:02 belongs to the 3COM CORPORATION).
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
An armed society is a polite society.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac [rev 2]
2010-04-07 11:49 ` [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac [rev 2] Mikhail Kshevetskiy
@ 2010-04-09 22:39 ` Wolfgang Denk
2010-04-14 17:39 ` Marek Vasut
2010-04-27 17:14 ` Marek Vasut
0 siblings, 2 replies; 9+ messages in thread
From: Wolfgang Denk @ 2010-04-09 22:39 UTC (permalink / raw)
To: u-boot
Dear Mikhail Kshevetskiy,
In message <20100407154936.474d591e@laska.campus-ws.pu.ru> you wrote:
> This patch is based on custom u-boot-1.1.2 version produced by voipac
> (http://www.voipac.com) and board/trizepsiv files from current u-boot.
>
> Up to now only PXA270 DIMM module with NOR flash is tested.
>
> v2: code style was improved
>
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
NAK. Please see review comments to previous version.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"No one talks peace unless he's ready to back it up with war."
"He talks of peace if it is the only way to live."
-- Colonel Green and Surak of Vulcan, "The Savage Curtain",
stardate 5906.5.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac
2010-04-07 11:46 ` Mikhail Kshevetskiy
@ 2010-04-09 22:41 ` Wolfgang Denk
0 siblings, 0 replies; 9+ messages in thread
From: Wolfgang Denk @ 2010-04-09 22:41 UTC (permalink / raw)
To: u-boot
Dear Mikhail Kshevetskiy,
In message <20100407154622.316be1f2@laska.campus-ws.pu.ru> you wrote:
>
> Here is my comments to your notices,
> the updated patch is in the following letter.
Thanks.
> I try to keep lowlevel_init.S as much close to the same file from board/trizeptiv
> as it was possible, so initially i keep formatting and comments style from the
> upstream version of board/trizeptiv/lowlevel_init.S.
I see. But a bad example is no reason to keep this style. Please fix.
> the similar or exactly the same peace of code can be found in lowlevel
> initialization of almost all arm/pxa boards, so i think it is reasonable to keep
> this code in place.
The fact that we accepted poor code in the past ist no reason not to
try to improve over time.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Intelligence without character is a dangerous thing." - G. Steinem
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac [rev 2]
2010-04-09 22:39 ` Wolfgang Denk
@ 2010-04-14 17:39 ` Marek Vasut
2010-04-27 17:14 ` Marek Vasut
1 sibling, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2010-04-14 17:39 UTC (permalink / raw)
To: u-boot
Dne So 10. dubna 2010 00:39:41 Wolfgang Denk napsal(a):
> Dear Mikhail Kshevetskiy,
>
> In message <20100407154936.474d591e@laska.campus-ws.pu.ru> you wrote:
> > This patch is based on custom u-boot-1.1.2 version produced by voipac
> > (http://www.voipac.com) and board/trizepsiv files from current u-boot.
> >
> > Up to now only PXA270 DIMM module with NOR flash is tested.
> >
> > v2: code style was improved
> >
> > Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
>
> NAK. Please see review comments to previous version.
>
> Best regards,
>
> Wolfgang Denk
I sent you my not-really-a-patch for vpac270. Hope you can get some ideas. But
please, that patch I sent you doesn't have the review issues addressed, be sure
to fix those.
Thanks!
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac [rev 2]
2010-04-09 22:39 ` Wolfgang Denk
2010-04-14 17:39 ` Marek Vasut
@ 2010-04-27 17:14 ` Marek Vasut
1 sibling, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2010-04-27 17:14 UTC (permalink / raw)
To: u-boot
Dne So 10. dubna 2010 00:39:41 Wolfgang Denk napsal(a):
> Dear Mikhail Kshevetskiy,
>
> In message <20100407154936.474d591e@laska.campus-ws.pu.ru> you wrote:
> > This patch is based on custom u-boot-1.1.2 version produced by voipac
> > (http://www.voipac.com) and board/trizepsiv files from current u-boot.
> >
> > Up to now only PXA270 DIMM module with NOR flash is tested.
> >
> > v2: code style was improved
> >
> > Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
>
> NAK. Please see review comments to previous version.
>
> Best regards,
>
> Wolfgang Denk
Hi,
Mikhail, any updates on this ?
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2010-04-27 17:14 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-03-29 12:24 [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac Mikhail Kshevetskiy
2010-03-30 21:15 ` Wolfgang Denk
2010-04-07 11:46 ` Mikhail Kshevetskiy
2010-04-09 22:41 ` Wolfgang Denk
2010-04-07 11:49 ` [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac [rev 2] Mikhail Kshevetskiy
2010-04-09 22:39 ` Wolfgang Denk
2010-04-14 17:39 ` Marek Vasut
2010-04-27 17:14 ` Marek Vasut
2010-04-09 21:50 ` [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac Wolfgang Denk
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