* [U-Boot] [PATCH 0/2] arm: Adding support for TI OMAP4430 SDP
@ 2010-05-25 6:39 Aneesh V
2010-05-25 6:39 ` [U-Boot] [PATCH 1/2] arm: renaming the cpu arm_cortexa8 to armv7 Aneesh V
0 siblings, 1 reply; 9+ messages in thread
From: Aneesh V @ 2010-05-25 6:39 UTC (permalink / raw)
To: u-boot
The following series implements support for TI OMAP4430 SDP based TI OMAP4430.
TI OMAP4430 is a Cortex-A9 based SOC from TI. OMAP4430 is a refrence board
based on OMAP4430.
The first patch in this series renames the cpu arm_cortexa8 to armv7 so that
the existing cortexa8 code can be shared with cortexa9. Both A8 and A9 are
based on armv7 architecture.
The second patch adds minimal support for OMAP4430 SDP. With this patch
OMAP4430 SDP boots up. Other features such as MMC, ethernet etc will be
added in subsequent patches.
Aneesh V (2):
arm: renaming the cpu arm_cortexa8 to armv7
arm: cortexa9: adding support for TI OMAP4430 SDP
Makefile | 28 ++-
arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c | 0
.../{arm_cortexa8 => armv7}/mx51/lowlevel_init.S | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c | 0
.../cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds | 0
.../arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c | 0
.../{arm_cortexa8 => armv7}/omap3/lowlevel_init.S | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/reset.S | 0
.../cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c | 0
.../arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/timer.c | 0
.../{arm_cortexa8/omap3 => armv7/omap4}/Makefile | 7 +-
.../{arm_cortexa8/s5pc1xx => armv7/omap4}/cache.S | 66 +++--
.../mx51/speed.c => armv7/omap4/lowlevel_init.S} | 40 ++-
arch/arm/cpu/armv7/omap4/omap4.c | 97 +++++++
.../{arm_cortexa8/omap3 => armv7/omap4}/reset.S | 0
.../s5pc1xx/cpu_info.c => armv7/omap4/sys_info.c} | 51 ++--
.../{arm_cortexa8/omap3 => armv7/omap4}/timer.c | 48 ++--
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/start.S | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds | 2 +-
arch/arm/include/asm/arch-omap4/cpu.h | 89 ++++++
arch/arm/include/asm/arch-omap4/omap4.h | 142 ++++++++++
.../reset.S => include/asm/arch-omap4/sys_proto.h} | 38 ++--
.../cpu/arm_cortexa8 => board/ti/sdp4430}/Makefile | 24 +-
.../arm_cortexa8 => board/ti/sdp4430}/config.mk | 25 +-
.../s5pc1xx/reset.S => board/ti/sdp4430/sdp.c | 57 +++--
include/configs/omap4_sdp4430.h | 280 ++++++++++++++++++++
46 files changed, 817 insertions(+), 177 deletions(-)
copy arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile (100%)
copy arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/lowlevel_init.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c (100%)
copy arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds (100%)
copy arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/lowlevel_init.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c (100%)
copy arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/reset.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c (100%)
copy arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8/omap3 => armv7/omap4}/Makefile (93%)
copy arch/arm/cpu/{arm_cortexa8/s5pc1xx => armv7/omap4}/cache.S (73%)
rename arch/arm/cpu/{arm_cortexa8/mx51/speed.c => armv7/omap4/lowlevel_init.S} (63%)
create mode 100644 arch/arm/cpu/armv7/omap4/omap4.c
copy arch/arm/cpu/{arm_cortexa8/omap3 => armv7/omap4}/reset.S (100%)
copy arch/arm/cpu/{arm_cortexa8/s5pc1xx/cpu_info.c => armv7/omap4/sys_info.c} (51%)
rename arch/arm/cpu/{arm_cortexa8/omap3 => armv7/omap4}/timer.c (73%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c (100%)
copy arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/start.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds (97%)
create mode 100644 arch/arm/include/asm/arch-omap4/cpu.h
create mode 100644 arch/arm/include/asm/arch-omap4/omap4.h
rename arch/arm/{cpu/arm_cortexa8/omap3/reset.S => include/asm/arch-omap4/sys_proto.h} (58%)
rename {arch/arm/cpu/arm_cortexa8 => board/ti/sdp4430}/Makefile (79%)
rename {arch/arm/cpu/arm_cortexa8 => board/ti/sdp4430}/config.mk (54%)
rename arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S => board/ti/sdp4430/sdp.c (58%)
create mode 100644 include/configs/omap4_sdp4430.h
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 1/2] arm: renaming the cpu arm_cortexa8 to armv7
2010-05-25 6:39 [U-Boot] [PATCH 0/2] arm: Adding support for TI OMAP4430 SDP Aneesh V
@ 2010-05-25 6:39 ` Aneesh V
2010-05-25 6:39 ` [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP Aneesh V
0 siblings, 1 reply; 9+ messages in thread
From: Aneesh V @ 2010-05-25 6:39 UTC (permalink / raw)
To: u-boot
Renaming the cpu arm_cortexa8 to armv7 so that we can share code between cortexa8
and cortexa9.
Both A8 and A9 belong to the armv7 architecture.
The differences between cortexa8 and cortexa9 do not impact u-boot initialization.
We can have common code for both the CPUs.
Signed-off-by: Aneesh V <aneesh@ti.com>
---
Makefile | 20 ++++++++++----------
arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c | 0
.../{arm_cortexa8 => armv7}/mx51/lowlevel_init.S | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c | 0
.../cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds | 0
.../arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c | 0
.../{arm_cortexa8 => armv7}/omap3/lowlevel_init.S | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/reset.S | 0
.../cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c | 0
.../arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/timer.c | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c | 0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/start.S | 0
arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds | 2 +-
32 files changed, 11 insertions(+), 11 deletions(-)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/lowlevel_init.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/lowlevel_init.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/reset.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/start.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds (97%)
diff --git a/Makefile b/Makefile
index 82cbbf4..0c7c130 100644
--- a/Makefile
+++ b/Makefile
@@ -3156,31 +3156,31 @@ SMN42_config : unconfig
#########################################################################
devkit8000_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
+ @$(MKCONFIG) $(@:_config=) arm armv7 devkit8000 timll omap3
omap3_beagle_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle ti omap3
+ @$(MKCONFIG) $(@:_config=) arm armv7 beagle ti omap3
omap3_overo_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo NULL omap3
+ @$(MKCONFIG) $(@:_config=) arm armv7 overo NULL omap3
omap3_evm_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm ti omap3
+ @$(MKCONFIG) $(@:_config=) arm armv7 evm ti omap3
omap3_pandora_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora NULL omap3
+ @$(MKCONFIG) $(@:_config=) arm armv7 pandora NULL omap3
omap3_sdp3430_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3
+ @$(MKCONFIG) $(@:_config=) arm armv7 sdp3430 ti omap3
omap3_zoom1_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 logicpd omap3
+ @$(MKCONFIG) $(@:_config=) arm armv7 zoom1 logicpd omap3
omap3_zoom2_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
+ @$(MKCONFIG) $(@:_config=) arm armv7 zoom2 logicpd omap3
smdkc100_config: unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
+ @$(MKCONFIG) $(@:_config=) arm armv7 smdkc100 samsung s5pc1xx
#########################################################################
## XScale Systems
@@ -3299,7 +3299,7 @@ mx31pdk_nand_config : unconfig
@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
mx51evk_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51
+ @$(MKCONFIG) $(@:_config=) arm armv7 mx51evk freescale mx51
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
diff --git a/arch/arm/cpu/arm_cortexa8/Makefile b/arch/arm/cpu/armv7/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/Makefile
rename to arch/arm/cpu/armv7/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/config.mk b/arch/arm/cpu/armv7/config.mk
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/config.mk
rename to arch/arm/cpu/armv7/config.mk
diff --git a/arch/arm/cpu/arm_cortexa8/cpu.c b/arch/arm/cpu/armv7/cpu.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/cpu.c
rename to arch/arm/cpu/armv7/cpu.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/Makefile b/arch/arm/cpu/armv7/mx51/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/Makefile
rename to arch/arm/cpu/armv7/mx51/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/clock.c b/arch/arm/cpu/armv7/mx51/clock.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/clock.c
rename to arch/arm/cpu/armv7/mx51/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/iomux.c b/arch/arm/cpu/armv7/mx51/iomux.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/iomux.c
rename to arch/arm/cpu/armv7/mx51/iomux.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S b/arch/arm/cpu/armv7/mx51/lowlevel_init.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
rename to arch/arm/cpu/armv7/mx51/lowlevel_init.S
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/soc.c b/arch/arm/cpu/armv7/mx51/soc.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/soc.c
rename to arch/arm/cpu/armv7/mx51/soc.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/speed.c b/arch/arm/cpu/armv7/mx51/speed.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/speed.c
rename to arch/arm/cpu/armv7/mx51/speed.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/timer.c b/arch/arm/cpu/armv7/mx51/timer.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/timer.c
rename to arch/arm/cpu/armv7/mx51/timer.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx51/u-boot.lds
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
rename to arch/arm/cpu/armv7/mx51/u-boot.lds
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/Makefile
rename to arch/arm/cpu/armv7/omap3/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/board.c
rename to arch/arm/cpu/armv7/omap3/board.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/cache.S
rename to arch/arm/cpu/armv7/omap3/cache.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/clock.c
rename to arch/arm/cpu/armv7/omap3/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/gpio.c b/arch/arm/cpu/armv7/omap3/gpio.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/gpio.c
rename to arch/arm/cpu/armv7/omap3/gpio.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
rename to arch/arm/cpu/armv7/omap3/lowlevel_init.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/mem.c
rename to arch/arm/cpu/armv7/omap3/mem.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/reset.S b/arch/arm/cpu/armv7/omap3/reset.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/reset.S
rename to arch/arm/cpu/armv7/omap3/reset.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
rename to arch/arm/cpu/armv7/omap3/sys_info.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/syslib.c b/arch/arm/cpu/armv7/omap3/syslib.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/syslib.c
rename to arch/arm/cpu/armv7/omap3/syslib.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/timer.c b/arch/arm/cpu/armv7/omap3/timer.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/timer.c
rename to arch/arm/cpu/armv7/omap3/timer.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile
rename to arch/arm/cpu/armv7/s5pc1xx/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S
rename to arch/arm/cpu/armv7/s5pc1xx/cache.S
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c
rename to arch/arm/cpu/armv7/s5pc1xx/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c
rename to arch/arm/cpu/armv7/s5pc1xx/cpu_info.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S
rename to arch/arm/cpu/armv7/s5pc1xx/reset.S
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c
rename to arch/arm/cpu/armv7/s5pc1xx/sromc.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c b/arch/arm/cpu/armv7/s5pc1xx/timer.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c
rename to arch/arm/cpu/armv7/s5pc1xx/timer.c
diff --git a/arch/arm/cpu/arm_cortexa8/start.S b/arch/arm/cpu/armv7/start.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/start.S
rename to arch/arm/cpu/armv7/start.S
diff --git a/arch/arm/cpu/arm_cortexa8/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
similarity index 97%
rename from arch/arm/cpu/arm_cortexa8/u-boot.lds
rename to arch/arm/cpu/armv7/u-boot.lds
index 820e3a1..9e5b5a9 100644
--- a/arch/arm/cpu/arm_cortexa8/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm_cortexa8/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text)
*(.text)
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP
2010-05-25 6:39 ` [U-Boot] [PATCH 1/2] arm: renaming the cpu arm_cortexa8 to armv7 Aneesh V
@ 2010-05-25 6:39 ` Aneesh V
2010-06-04 21:58 ` John Rigby
2010-06-05 19:55 ` Wolfgang Denk
0 siblings, 2 replies; 9+ messages in thread
From: Aneesh V @ 2010-05-25 6:39 UTC (permalink / raw)
To: u-boot
Adding support for OMAP4430 SDP board based on the TI OMAP4430 SOC.
TI OMAP4430 is an SOC based on ARM Cortex-A9 cpu.
OMAP4430 SDP is a reference board based on OMAP4430.
This patch adds minimum support for booting the board.
OMAP4430 SDP does not support XIP. U-boot is loaded to SDRAM with the help of
another small bootloader running from SRAM. U-boot currently relies on this
bootloader for clock, mux, and SDRAM initialization.
This will change when OMAP4430 Configuration Header(CH) is attached
to u-boot. CH is a feature by which ROM code can be made to intialize the
clocks and SDRAM and to copy u-boot directly into SDRAM from a non-XIP device.
More support such as MMC, ethernet etc will be added in subsequent patches.
Signed-off-by: Aneesh V <aneesh@ti.com>
---
Makefile | 8 +-
arch/arm/cpu/armv7/omap4/Makefile | 50 +++++
arch/arm/cpu/armv7/omap4/cache.S | 128 ++++++++++++
arch/arm/cpu/armv7/omap4/lowlevel_init.S | 49 +++++
arch/arm/cpu/armv7/omap4/omap4.c | 97 +++++++++
arch/arm/cpu/armv7/omap4/reset.S | 36 ++++
arch/arm/cpu/armv7/omap4/sys_info.c | 58 ++++++
arch/arm/cpu/armv7/omap4/timer.c | 140 +++++++++++++
arch/arm/include/asm/arch-omap4/cpu.h | 89 +++++++++
arch/arm/include/asm/arch-omap4/omap4.h | 142 ++++++++++++++
arch/arm/include/asm/arch-omap4/sys_proto.h | 36 ++++
board/ti/sdp4430/Makefile | 49 +++++
board/ti/sdp4430/config.mk | 32 +++
board/ti/sdp4430/sdp.c | 56 ++++++
include/configs/omap4_sdp4430.h | 280 +++++++++++++++++++++++++++
15 files changed, 1249 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/armv7/omap4/Makefile
create mode 100644 arch/arm/cpu/armv7/omap4/cache.S
create mode 100644 arch/arm/cpu/armv7/omap4/lowlevel_init.S
create mode 100644 arch/arm/cpu/armv7/omap4/omap4.c
create mode 100644 arch/arm/cpu/armv7/omap4/reset.S
create mode 100644 arch/arm/cpu/armv7/omap4/sys_info.c
create mode 100644 arch/arm/cpu/armv7/omap4/timer.c
create mode 100644 arch/arm/include/asm/arch-omap4/cpu.h
create mode 100644 arch/arm/include/asm/arch-omap4/omap4.h
create mode 100644 arch/arm/include/asm/arch-omap4/sys_proto.h
create mode 100644 board/ti/sdp4430/Makefile
create mode 100644 board/ti/sdp4430/config.mk
create mode 100644 board/ti/sdp4430/sdp.c
create mode 100644 include/configs/omap4_sdp4430.h
diff --git a/Makefile b/Makefile
index 0c7c130..3fb488c 100644
--- a/Makefile
+++ b/Makefile
@@ -3152,7 +3152,7 @@ SMN42_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292
#########################################################################
-## ARM CORTEX Systems
+## ARM v7 Cortex-A8 systems
#########################################################################
devkit8000_config : unconfig
@@ -3183,6 +3183,12 @@ smdkc100_config: unconfig
@$(MKCONFIG) $(@:_config=) arm armv7 smdkc100 samsung s5pc1xx
#########################################################################
+## ARM v7 CORTEX-A9 Systems
+#########################################################################
+omap4_sdp4430_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm armv7 sdp4430 ti omap4
+
+#########################################################################
## XScale Systems
#########################################################################
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
new file mode 100644
index 0000000..824a64c
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+SOBJS := lowlevel_init.o
+SOBJS += reset.o
+
+COBJS += omap4.o
+COBJS += sys_info.o
+COBJS += timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/omap4/cache.S b/arch/arm/cpu/armv7/omap4/cache.S
new file mode 100644
index 0000000..3c78aa9
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/cache.S
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This file is based on and replaces the existing cache.c file
+ * The copyrights for the cache.c file are:
+ *
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * omap4 cache code
+ */
+
+.align 5
+.global invalidate_dcache
+.global l2_cache_enable
+.global l2_cache_disable
+.global invalidate_icache
+/*
+ * invalidate_dcache()
+ *
+ * Invalidate the whole L1 D-cache.
+ *
+ * Corrupted registers: r0-r5, r7, r9-r11
+ *
+ * - mm - mm_struct describing address space
+ */
+invalidate_dcache:
+ stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ ands r3, r0, #0x7000000 @ extract loc from clidr
+ mov r3, r3, lsr #23 @ left align loc bit field
+ beq finished_inval @ if loc is 0, then no need to
+ @ clean
+ mov r10, #0 @ start clean at cache level 0
+inval_loop1:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache
+ @ level
+ mov r1, r0, lsr r2 @ extract cache type bits from
+ @ clidr
+ and r1, r1, #7 @ mask of the bits for current
+ @ cache only
+ cmp r1, #2 @ see what cache we have at
+ @ this level
+ blt skip_inval @ skip if no cache, or just
+ @ i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level
+ @ in cssr
+ mov r2, #0 @ operand for mcr SBZ
+ mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
+ @ sych the new cssr&csidr,
+ @ with armv7 this is 'isb',
+ @ but we compile with armv5
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the
+ @ cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ ldr r4, =0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the
+ @ way size
+ clz r5, r4 @ find bit position of way
+ @ size increment
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the
+ @ index size
+inval_loop2:
+ mov r9, r4 @ create working copy of max
+ @ way size
+inval_loop3:
+ orr r11, r10, r9, lsl r5 @ factor way and cache number
+ @ into r11
+ orr r11, r11, r7, lsl r2 @ factor index number into r11
+ mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
+ subs r9, r9, #1 @ decrement the way
+ bge inval_loop3
+ subs r7, r7, #1 @ decrement the index
+ bge inval_loop2
+skip_inval:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt inval_loop1
+finished_inval:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level
+ @ in cssr
+ dmb @ DMB is sufficient to guarantee the
+ @ ordering of D$ maintenance operations.
+
+ ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
+
+l2_cache_enable:
+ bx r14
+
+l2_cache_disable:
+ bx r14
+
+invalidate_icache:
+ /* ICIALLU - Invalidate the entire Instruction Cache to POU */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0
+ dsb
+ bx lr
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
new file mode 100644
index 0000000..fd2ff38
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -0,0 +1,49 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Initial Code by:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/omap4.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, =LOW_LEVEL_SRAM_STACK
+
+ /*
+ * Save the old lr(passed in ip) and the current lr to stack
+ */
+ push {ip, lr}
+
+ /*
+ * go setup pll, mux, memory
+ */
+ bl s_init
+ pop {ip, pc}
+
diff --git a/arch/arm/cpu/armv7/omap4/omap4.c b/arch/arm/cpu/armv7/omap4/omap4.c
new file mode 100644
index 0000000..a28cbcf
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/omap4.c
@@ -0,0 +1,97 @@
+/*
+ *
+ * Common functions for OMAP4 processor
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ * Aneesh V <aneesh@ti.com> - Created OMAP4 version
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+/* Declare the global data pointer - gd */
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with SRAM stack.
+ */
+void s_init (void)
+{
+ watchdog_init ();
+}
+
+/*
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ */
+void wait_for_command_complete (struct watchdog *wd_base)
+{
+ int pending = 1;
+ do {
+ pending = readl (&wd_base->wwps);
+ } while (pending);
+}
+
+/*
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ */
+void watchdog_init (void)
+{
+ struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
+
+ writel (WD_UNLOCK1, &wd2_base->wspr);
+ wait_for_command_complete (wd2_base);
+ writel (WD_UNLOCK2, &wd2_base->wspr);
+}
+
+/*
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ */
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = 0x80000000;
+ gd->bd->bi_dram[0].size = 512 << 20;
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/*
+ * Print board information
+ */
+int checkboard (void)
+{
+ printf ("%s\n", sysinfo.board_string);
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
diff --git a/arch/arm/cpu/armv7/omap4/reset.S b/arch/arm/cpu/armv7/omap4/reset.S
new file mode 100644
index 0000000..a53c408
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/reset.S
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.global reset_cpu
+reset_cpu:
+ ldr r1, rstctl @ get addr for global reset
+ @ reg
+ mov r3, #0x2 @ full reset pll + mpu
+ str r3, [r1] @ force reset
+ mov r0, r0
+_loop_forever:
+ b _loop_forever
+rstctl:
+ .word PRM_RSTCTRL
diff --git a/arch/arm/cpu/armv7/omap4/sys_info.c b/arch/arm/cpu/armv7/omap4/sys_info.c
new file mode 100644
index 0000000..acfafad
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sys_info.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type (void)
+{
+ return 0;
+}
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev (void)
+{
+ return 0x20;
+}
+
+/*
+ * Print CPU information
+ */
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo (void)
+{
+
+ printf ("CPU : OMAP4430 ES1.0 \n");
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/armv7/omap4/timer.c b/arch/arm/cpu/armv7/omap4/timer.c
new file mode 100644
index 0000000..2c2ec45
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/timer.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Moahmmed Khasim <khasim@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/omap4.h>
+
+static ulong timestamp;
+static ulong lastinc;
+static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Nothing really to do with interrupts, just starts up a counter.
+ * We run the counter with 13MHz, divided by 8, resulting in timer
+ * frequency of 1.625MHz. With 32bit counter register, counter
+ * overflows in ~44min
+ */
+
+/* 13MHz / 8 = 1.625MHz */
+#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
+#define TIMER_LOAD_VAL 0xffffffff
+
+int timer_init (void)
+{
+ /* start the counter ticking up, reload value on overflow */
+ writel (TIMER_LOAD_VAL, &timer_base->tldr);
+ /* enable timer */
+ writel ((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
+ &timer_base->tclr);
+
+ reset_timer_masked (); /* init the timestamp and lastinc value */
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds */
+void __udelay (unsigned long usec)
+{
+ long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+ unsigned long now, last = readl (&timer_base->tcrr);
+
+ while (tmo > 0) {
+ now = readl (&timer_base->tcrr);
+ if (last > now) /* count up timer overflow */
+ tmo -= TIMER_LOAD_VAL - last + now;
+ else
+ tmo -= now - last;
+ last = now;
+ }
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time, capture current incrementer value time */
+ lastinc = readl (&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+ /* current tick value */
+ ulong now = readl (&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+
+ if (now >= lastinc)
+ /* normal mode (non roll) */
+ /* move stamp fordward with absoulte diff ticks */
+ timestamp += (now - lastinc);
+ else /* we have rollover of incrementer */
+ timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
+ - lastinc) + now;
+ lastinc = now;
+ return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks (void)
+{
+ return get_timer (0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
new file mode 100644
index 0000000..637e02c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_OMAP4_H
+#define _CPU_OMAP4_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gptimer {
+ u32 tidr; /* 0x00 r */
+ u8 res[0xc];
+ u32 tiocp_cfg; /* 0x10 rw */
+ u32 tistat; /* 0x14 r */
+ u32 tisr; /* 0x18 rw */
+ u32 tier; /* 0x1c rw */
+ u32 twer; /* 0x20 rw */
+ u32 tclr; /* 0x24 rw */
+ u32 tcrr; /* 0x28 rw */
+ u32 tldr; /* 0x2c rw */
+ u32 ttgr; /* 0x30 rw */
+ u32 twpc; /* 0x34 r */
+ u32 tmar; /* 0x38 rw */
+ u32 tcar1; /* 0x3c r */
+ u32 tcicr; /* 0x40 rw */
+ u32 tcar2; /* 0x44 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+ u8 res1[0x34];
+ u32 wwps; /* 0x34 r */
+ u8 res2[0x10];
+ u32 wspr; /* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+#define SYSCLKDIV_1 (0x1 << 6)
+#define SYSCLKDIV_2 (0x1 << 7)
+
+#define CLKSEL_GPT1 (0x1 << 0)
+
+#define EN_GPT1 (0x1 << 0)
+#define EN_32KSYNC (0x1 << 2)
+
+#define ST_WDT2 (0x1 << 5)
+
+#define RESETDONE (0x1 << 0)
+
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
new file mode 100644
index 0000000..62557f3
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Derived from OMAP3 work by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP4_H_
+#define _OMAP4_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP44XX_L4_CORE_BASE 0x4A000000
+#define OMAP44XX_L4_WKUP_BASE 0x4A300000
+#define OMAP44XX_L4_PER_BASE 0x48000000
+
+/* CONTROL */
+#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
+
+/* UART */
+#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
+
+/* GPMC */
+#define GPMC_BASE 0x50000000
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* GP Timer */
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE 0x4A306000
+#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL PRM_DEVICE_BASE
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+ unsigned char res[0x10];
+ unsigned int s32k_cr; /* 0x10 */
+};
+
+struct gptimer {
+ u32 tidr; /* 0x00 r */
+ u8 res[0xc];
+ u32 tiocp_cfg; /* 0x10 rw */
+ u32 tistat; /* 0x14 r */
+ u32 tisr; /* 0x18 rw */
+ u32 tier; /* 0x1c rw */
+ u32 twer; /* 0x20 rw */
+ u32 tclr; /* 0x24 rw */
+ u32 tcrr; /* 0x28 rw */
+ u32 tldr; /* 0x2c rw */
+ u32 ttgr; /* 0x30 rw */
+ u32 twpc; /* 0x34 r */
+ u32 tmar; /* 0x38 rw */
+ u32 tcar1; /* 0x3c r */
+ u32 tcicr; /* 0x40 rw */
+ u32 tcar2; /* 0x44 r */
+};
+
+struct watchdog {
+ u8 res1[0x34];
+ u32 wwps; /* 0x34 r */
+ u8 res2[0x10];
+ u32 wspr; /* 0x48 rw */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ *@0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE 0x4030D000
+/* Temporary SRAM stack used while low level init is done */
+#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
+
+/*
+ * OMAP4 real hardware:
+ * TODO: Change this to the IDCODE in the hw regsiter
+ */
+#define CPU_OMAP4430_ES10 1
+#define CPU_OMAP4430_ES20 2
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
new file mode 100644
index 0000000..29915ee
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+#include <asm/arch/omap4.h>
+#include <asm/io.h>
+
+struct omap_sysinfo {
+ char *board_string;
+};
+
+void watchdog_init (void);
+u32 get_device_type (void);
+void invalidate_dcache (u32);
+
+extern const struct omap_sysinfo sysinfo;
+
+#endif
diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile
new file mode 100644
index 0000000..2554c7b
--- /dev/null
+++ b/board/ti/sdp4430/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := sdp.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
new file mode 100644
index 0000000..3c0349e
--- /dev/null
+++ b/board/ti/sdp4430/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2006-2009
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# SDRAM Address Space:
+# 8000'0000 - 9fff'ffff (512 MB)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# Let's place u-boot 1MB before the end of SDRAM.
+TEXT_BASE = 0x9ff00000
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
new file mode 100644
index 0000000..6989187
--- /dev/null
+++ b/board/ti/sdp4430/sdp.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP4430 SDP"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init (void)
+{
+ return 0;
+}
+
+int board_eth_init (bd_t *bis)
+{
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure SDP board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r (void)
+{
+ return 0;
+}
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
new file mode 100644
index 0000000..68a0c27
--- /dev/null
+++ b/include/configs/omap4_sdp4430.h
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2006-2009
+ * Texas Instruments Incorporated.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ * Nishanth Menon <nm@ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Configuration settings for the 3430 TI SDP3430 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA9 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP44XX 1 /* which is a 44XX */
+#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_4430SDP 1 /* working with SDP */
+ /*#define CONFIG_FASTBOOT 1*//* Using fastboot interface */
+
+/* Get CPU defs */
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 256k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
+ /* initial data */
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#if 0
+/* Enabled commands */
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#endif
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * MMC boot support
+ */
+#if defined(CONFIG_CMD_MMC)
+#define CONFIG_MMC 1
+#define CONFIG_DOS_PARTITION 1
+#endif
+
+/*
+ * I2C for power management setup
+ */
+#undef CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+
+/*
+ * Enabling relocation of u-boot by default
+ * Relocation can be skipped if u-boot is copied to the TEXT_BASE
+ */
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Environment setup
+ *
+ * Default boot order: mmc bootscript, MMC uImage, NOR image.
+ * Network booting environment must be configured at site.
+ */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS0,115200n8\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=/dev/mmcblk0p2 rw " \
+ "rootfstype=ext3 rootwait\0" \
+ "norargs=setenv bootargs console=${console} " \
+ "root=/dev/mtdblock3 rw " \
+ "rootfstype=jffs2\0" \
+ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from MMC/SD ...; " \
+ "autoscr ${loadaddr}\0" \
+ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from MMC/SD ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "norboot=echo Booting from NOR ...; " \
+ "run norargs; " \
+ "bootm 0x80000\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmcinit; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run norboot; " \
+ "fi; " \
+ "fi; " \
+ "else run norboot; fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/* SDRAM Test range - start at 16 meg boundary -ends at 1Meg -
+ * a basic sanity check ONLY
+ * IF you would like to increase coverage, increase the end address
+ * or run the test with custom options
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (1 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE GPT1_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE 0
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+
+/*
+ * Although we don't have
+ * CFI FLASH driver setup
+ * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
+ *
+ */
+#if 0
+#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH 2
+#define PHYS_FLASH_SIZE (128 << 20)
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
+#endif
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
--
1.6.0.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP
2010-05-25 6:39 ` [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP Aneesh V
@ 2010-06-04 21:58 ` John Rigby
2010-06-08 16:49 ` Steve Sakoman
2010-06-05 19:55 ` Wolfgang Denk
1 sibling, 1 reply; 9+ messages in thread
From: John Rigby @ 2010-06-04 21:58 UTC (permalink / raw)
To: u-boot
Aneesh:
On Tue, May 25, 2010 at 12:39 AM, Aneesh V <aneesh@ti.com> wrote:
> Adding support for OMAP4430 SDP board based on the TI OMAP4430 SOC.
---
arch/arm/cpu/armv7/omap4/reset.S:
Identical to omap3 version. I think they should be shared. Perhaps
have a arch/arm/cpu/armv7/omap directory for shared files.
arch/arm/cpu/armv7/omap4/timer.c:
Apart from the include of asm/arch/omap4.h this file is identical to
the omap3 version. See sharing comment above.
arch/arm/include/asm/arch-omap4/cpu.h:
I think there is opportunity for sharing here as well. Not the whole file
so some refactoring needs to happen.
Thanks,
John
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP
2010-05-25 6:39 ` [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP Aneesh V
2010-06-04 21:58 ` John Rigby
@ 2010-06-05 19:55 ` Wolfgang Denk
2010-06-07 14:44 ` V, Aneesh
1 sibling, 1 reply; 9+ messages in thread
From: Wolfgang Denk @ 2010-06-05 19:55 UTC (permalink / raw)
To: u-boot
Dear Aneesh V,
In message <1274769577-29021-3-git-send-email-aneesh@ti.com> you wrote:
> Adding support for OMAP4430 SDP board based on the TI OMAP4430 SOC.
>
> TI OMAP4430 is an SOC based on ARM Cortex-A9 cpu.
> OMAP4430 SDP is a reference board based on OMAP4430.
>
> This patch adds minimum support for booting the board.
> OMAP4430 SDP does not support XIP. U-boot is loaded to SDRAM with the help of
> another small bootloader running from SRAM. U-boot currently relies on this
> bootloader for clock, mux, and SDRAM initialization.
>
> This will change when OMAP4430 Configuration Header(CH) is attached
> to u-boot. CH is a feature by which ROM code can be made to intialize the
> clocks and SDRAM and to copy u-boot directly into SDRAM from a non-XIP device.
>
> More support such as MMC, ethernet etc will be added in subsequent patches.
>
> Signed-off-by: Aneesh V <aneesh@ti.com>
In addition to John's comments:
> Makefile | 8 +-
> arch/arm/cpu/armv7/omap4/Makefile | 50 +++++
> arch/arm/cpu/armv7/omap4/cache.S | 128 ++++++++++++
> arch/arm/cpu/armv7/omap4/lowlevel_init.S | 49 +++++
> arch/arm/cpu/armv7/omap4/omap4.c | 97 +++++++++
> arch/arm/cpu/armv7/omap4/reset.S | 36 ++++
> arch/arm/cpu/armv7/omap4/sys_info.c | 58 ++++++
> arch/arm/cpu/armv7/omap4/timer.c | 140 +++++++++++++
> arch/arm/include/asm/arch-omap4/cpu.h | 89 +++++++++
> arch/arm/include/asm/arch-omap4/omap4.h | 142 ++++++++++++++
> arch/arm/include/asm/arch-omap4/sys_proto.h | 36 ++++
> board/ti/sdp4430/Makefile | 49 +++++
> board/ti/sdp4430/config.mk | 32 +++
> board/ti/sdp4430/sdp.c | 56 ++++++
> include/configs/omap4_sdp4430.h | 280 +++++++++++++++++++++++++++
> 15 files changed, 1249 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/cpu/armv7/omap4/Makefile
> create mode 100644 arch/arm/cpu/armv7/omap4/cache.S
> create mode 100644 arch/arm/cpu/armv7/omap4/lowlevel_init.S
> create mode 100644 arch/arm/cpu/armv7/omap4/omap4.c
> create mode 100644 arch/arm/cpu/armv7/omap4/reset.S
> create mode 100644 arch/arm/cpu/armv7/omap4/sys_info.c
> create mode 100644 arch/arm/cpu/armv7/omap4/timer.c
> create mode 100644 arch/arm/include/asm/arch-omap4/cpu.h
> create mode 100644 arch/arm/include/asm/arch-omap4/omap4.h
> create mode 100644 arch/arm/include/asm/arch-omap4/sys_proto.h
> create mode 100644 board/ti/sdp4430/Makefile
> create mode 100644 board/ti/sdp4430/config.mk
> create mode 100644 board/ti/sdp4430/sdp.c
> create mode 100644 include/configs/omap4_sdp4430.h
Entries to MAKEALL and MAINTAINERS files missing.
> +int checkboard (void)
> +{
> + printf ("%s\n", sysinfo.board_string);
> + return 0;
> +}
Consider using puts() when you don't need any output formatting.
> +#endif /* CONFIG_DISPLAY_BOARDINFO */
...
> +#ifdef CONFIG_DISPLAY_CPUINFO
These #defines have never been documented. It seems they are being
copied around a lot, but I'm not sure if anybody ever does NOT set
these.
I think we should at least document these - or rather drop them
everywhere. What do you think?
> +{
> +
> + printf ("CPU : OMAP4430 ES1.0 \n");
puts()?
And: no spaces after function names please (fix globally!).
...
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARMCORTEXA9 1 /* This is an ARM V7 CPU core */
> +#define CONFIG_OMAP 1 /* in a TI OMAP core */
> +#define CONFIG_OMAP44XX 1 /* which is a 44XX */
> +#define CONFIG_OMAP4430 1 /* which is in a 4430 */
> +#define CONFIG_4430SDP 1 /* working with SDP */
> + /*#define CONFIG_FASTBOOT 1*//* Using fastboot interface */
Line too long - please check (and fix) globally.
And please don't add dead code like this.
> +#if 0
> +/* Enabled commands */
> +#define CONFIG_CMD_DHCP /* DHCP Support */
> +#define CONFIG_CMD_EXT2 /* EXT2 Support */
> +#define CONFIG_CMD_FAT /* FAT support */
> +#define CONFIG_CMD_I2C /* I2C serial bus support */
> +#define CONFIG_CMD_MMC /* MMC support */
> +#endif
... or like this.
...
> +/* SDRAM Test range - start at 16 meg boundary -ends at 1Meg -
> + * a basic sanity check ONLY
> + * IF you would like to increase coverage, increase the end address
> + * or run the test with custom options
> + */
Incorrect multiline comment style - in addition, the comment ("start
at 16 meg boundary -ends at 1Meg") makes no sense to me.
> +#define CONFIG_SYS_MEMTEST_START 0x80000000
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (1 << 20))
Why would you want to test only such a small fration of your system
RAM?
> +/*
> + * Although we don't have
> + * CFI FLASH driver setup
> + * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
> + *
> + */
Can't parse this!
> +#if 0
No dead code, please.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Real computer scientists don't comment their code. The identifiers
are so long they can't afford the disk space.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP
2010-06-05 19:55 ` Wolfgang Denk
@ 2010-06-07 14:44 ` V, Aneesh
2010-06-07 20:05 ` Wolfgang Denk
0 siblings, 1 reply; 9+ messages in thread
From: V, Aneesh @ 2010-06-07 14:44 UTC (permalink / raw)
To: u-boot
Hello Wolfgang,
Thanks for your comments. We will fix the issues you have pointed out.
> > +#endif /* CONFIG_DISPLAY_BOARDINFO */
> ...
> > +#ifdef CONFIG_DISPLAY_CPUINFO
>
> These #defines have never been documented. It seems they are being
> copied around a lot, but I'm not sure if anybody ever does NOT set
> these.
>
> I think we should at least document these - or rather drop them
> everywhere. What do you think?
>
I'm ok with dropping it everywhere.
> > +{
> > +
> > + printf ("CPU : OMAP4430 ES1.0 \n");
>
> puts()?
>
> And: no spaces after function names please (fix globally!).
But how about this rule mentioned in your wiki:
"All contributions to U-Boot should conform to the Linux kernel coding style; see the file "Documentation/CodingStyle" and the script "scripts/Lindent" in your Linux kernel source directory. In sources originating from U-Boot a style corresponding to "Lindent -pcs" (adding spaces before parameters to function calls) is actually used."
http://www.denx.de/wiki/U-Boot/CodingStyle
In fact, I didn't add spaces initially. They got added when I ran "Lindent -pcs". Is this rule not applicable anymore? Or am I missing something?
Best regards,
Aneesh
> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Sunday, June 06, 2010 1:25 AM
> To: V, Aneesh
> Cc: u-boot at lists.denx.de; olbpdev at list.ti.com - OMAP Linux Baseport
> Development Team (May contain non-TIers)
> Subject: Re: [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI
> OMAP4430 SDP
>
> Dear Aneesh V,
>
> In message <1274769577-29021-3-git-send-email-aneesh@ti.com> you wrote:
> > Adding support for OMAP4430 SDP board based on the TI OMAP4430 SOC.
> >
> > TI OMAP4430 is an SOC based on ARM Cortex-A9 cpu.
> > OMAP4430 SDP is a reference board based on OMAP4430.
> >
> > This patch adds minimum support for booting the board.
> > OMAP4430 SDP does not support XIP. U-boot is loaded to SDRAM with the
> help of
> > another small bootloader running from SRAM. U-boot currently relies on
> this
> > bootloader for clock, mux, and SDRAM initialization.
> >
> > This will change when OMAP4430 Configuration Header(CH) is attached
> > to u-boot. CH is a feature by which ROM code can be made to intialize
> the
> > clocks and SDRAM and to copy u-boot directly into SDRAM from a non-XIP
> device.
> >
> > More support such as MMC, ethernet etc will be added in subsequent
> patches.
> >
> > Signed-off-by: Aneesh V <aneesh@ti.com>
>
> In addition to John's comments:
>
> > Makefile | 8 +-
> > arch/arm/cpu/armv7/omap4/Makefile | 50 +++++
> > arch/arm/cpu/armv7/omap4/cache.S | 128 ++++++++++++
> > arch/arm/cpu/armv7/omap4/lowlevel_init.S | 49 +++++
> > arch/arm/cpu/armv7/omap4/omap4.c | 97 +++++++++
> > arch/arm/cpu/armv7/omap4/reset.S | 36 ++++
> > arch/arm/cpu/armv7/omap4/sys_info.c | 58 ++++++
> > arch/arm/cpu/armv7/omap4/timer.c | 140 +++++++++++++
> > arch/arm/include/asm/arch-omap4/cpu.h | 89 +++++++++
> > arch/arm/include/asm/arch-omap4/omap4.h | 142 ++++++++++++++
> > arch/arm/include/asm/arch-omap4/sys_proto.h | 36 ++++
> > board/ti/sdp4430/Makefile | 49 +++++
> > board/ti/sdp4430/config.mk | 32 +++
> > board/ti/sdp4430/sdp.c | 56 ++++++
> > include/configs/omap4_sdp4430.h | 280
> +++++++++++++++++++++++++++
> > 15 files changed, 1249 insertions(+), 1 deletions(-)
> > create mode 100644 arch/arm/cpu/armv7/omap4/Makefile
> > create mode 100644 arch/arm/cpu/armv7/omap4/cache.S
> > create mode 100644 arch/arm/cpu/armv7/omap4/lowlevel_init.S
> > create mode 100644 arch/arm/cpu/armv7/omap4/omap4.c
> > create mode 100644 arch/arm/cpu/armv7/omap4/reset.S
> > create mode 100644 arch/arm/cpu/armv7/omap4/sys_info.c
> > create mode 100644 arch/arm/cpu/armv7/omap4/timer.c
> > create mode 100644 arch/arm/include/asm/arch-omap4/cpu.h
> > create mode 100644 arch/arm/include/asm/arch-omap4/omap4.h
> > create mode 100644 arch/arm/include/asm/arch-omap4/sys_proto.h
> > create mode 100644 board/ti/sdp4430/Makefile
> > create mode 100644 board/ti/sdp4430/config.mk
> > create mode 100644 board/ti/sdp4430/sdp.c
> > create mode 100644 include/configs/omap4_sdp4430.h
>
> Entries to MAKEALL and MAINTAINERS files missing.
>
> > +int checkboard (void)
> > +{
> > + printf ("%s\n", sysinfo.board_string);
> > + return 0;
> > +}
>
> Consider using puts() when you don't need any output formatting.
>
> > +#endif /* CONFIG_DISPLAY_BOARDINFO */
> ...
> > +#ifdef CONFIG_DISPLAY_CPUINFO
>
> These #defines have never been documented. It seems they are being
> copied around a lot, but I'm not sure if anybody ever does NOT set
> these.
>
> I think we should at least document these - or rather drop them
> everywhere. What do you think?
>
> > +{
> > +
> > + printf ("CPU : OMAP4430 ES1.0 \n");
>
> puts()?
>
> And: no spaces after function names please (fix globally!).
>
> ...
> > +/*
> > + * High Level Configuration Options
> > + */
> > +#define CONFIG_ARMCORTEXA9 1 /* This is an ARM V7 CPU core */
> > +#define CONFIG_OMAP 1 /* in a TI OMAP core */
> > +#define CONFIG_OMAP44XX 1 /* which is a 44XX */
> > +#define CONFIG_OMAP4430 1 /* which is in a 4430 */
> > +#define CONFIG_4430SDP 1 /* working with SDP */
> > + /*#define CONFIG_FASTBOOT 1*//* Using
> fastboot interface */
>
> Line too long - please check (and fix) globally.
>
> And please don't add dead code like this.
>
>
> > +#if 0
> > +/* Enabled commands */
> > +#define CONFIG_CMD_DHCP /* DHCP Support */
> > +#define CONFIG_CMD_EXT2 /* EXT2 Support */
> > +#define CONFIG_CMD_FAT /* FAT support */
> > +#define CONFIG_CMD_I2C /* I2C serial bus support */
> > +#define CONFIG_CMD_MMC /* MMC support */
> > +#endif
>
> ... or like this.
>
> ...
> > +/* SDRAM Test range - start at 16 meg boundary -ends at 1Meg -
> > + * a basic sanity check ONLY
> > + * IF you would like to increase coverage, increase the end address
> > + * or run the test with custom options
> > + */
>
> Incorrect multiline comment style - in addition, the comment ("start
> at 16 meg boundary -ends at 1Meg") makes no sense to me.
>
> > +#define CONFIG_SYS_MEMTEST_START 0x80000000
> > +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (1
> << 20))
>
> Why would you want to test only such a small fration of your system
> RAM?
>
> > +/*
> > + * Although we don't have
> > + * CFI FLASH driver setup
> > + * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
> > + *
> > + */
>
> Can't parse this!
>
> > +#if 0
>
> No dead code, please.
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> Real computer scientists don't comment their code. The identifiers
> are so long they can't afford the disk space.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP
2010-06-07 14:44 ` V, Aneesh
@ 2010-06-07 20:05 ` Wolfgang Denk
0 siblings, 0 replies; 9+ messages in thread
From: Wolfgang Denk @ 2010-06-07 20:05 UTC (permalink / raw)
To: u-boot
Dear "V, Aneesh",
In message <FF55437E1F14DA4BAEB721A458B6701706BD8CC798@dbde02.ent.ti.com> you wrote:
>
> > And: no spaces after function names please (fix globally!).
>
> But how about this rule mentioned in your wiki:
>
> "All contributions to U-Boot should conform to the Linux kernel coding styl
> e; see the file "Documentation/CodingStyle" and the script "scripts/Lindent
> " in your Linux kernel source directory. In sources originating from U-Boot
> a style corresponding to "Lindent -pcs" (adding spaces before parameters t
> o function calls) is actually used."
[Could you please restrict your ine length to some 70 characters or
so? Thanks!]
> http://www.denx.de/wiki/U-Boot/CodingStyle
>
> In fact, I didn't add spaces initially. They got added when I ran "Lindent
> -pcs". Is this rule not applicable anymore? Or am I missing something?
Thais was written some time ago by me, and nobody cared to fix it yet.
Having the spaces was (and is) my ownporeferred style, but I got
overruled by a vast majority...
> > -----Original Message-----
> > From: Wolfgang Denk [mailto:wd at denx.de]
> > Sent: Sunday, June 06, 2010 1:25 AM
> > To: V, Aneesh
> > Cc: u-boot at lists.denx.de; olbpdev at list.ti.com - OMAP Linux Baseport
> > Development Team (May contain non-TIers)
> > Subject: Re: [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI
> > OMAP4430 SDP
> >
> > Dear Aneesh V,
And please don;t top-post / full quote; please see
http://www.netmeister.org/news/learn2quote.html
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A morsel of genuine history is a thing so rare as to be always
valuable. - Thomas Jefferson
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP
2010-06-04 21:58 ` John Rigby
@ 2010-06-08 16:49 ` Steve Sakoman
2010-06-08 18:40 ` John Rigby
0 siblings, 1 reply; 9+ messages in thread
From: Steve Sakoman @ 2010-06-08 16:49 UTC (permalink / raw)
To: u-boot
On Fri, Jun 4, 2010 at 2:58 PM, John Rigby <jcrigby@gmail.com> wrote:
> Aneesh:
>
> On Tue, May 25, 2010 at 12:39 AM, Aneesh V <aneesh@ti.com> wrote:
>> Adding support for OMAP4430 SDP board based on the TI OMAP4430 SOC.
>
> ---
>
> arch/arm/cpu/armv7/omap4/reset.S:
> Identical to omap3 version. ?I think they should be shared. Perhaps
> have a arch/arm/cpu/armv7/omap directory for shared files.
How about we call it omap-common?
Is there a good example of how to handle this shared code? The
existing build system will only build the contents of the omap4
directory and not omap-common. Offhand I don't see any other
architectures that do this, so I thought I would ask before making
something up :-)
Steve
> arch/arm/cpu/armv7/omap4/timer.c:
> Apart from the include of asm/arch/omap4.h this file is identical to
> the omap3 version. ?See sharing comment above.
>
> arch/arm/include/asm/arch-omap4/cpu.h:
> I think there is opportunity for sharing here as well. ?Not the whole file
> so some refactoring needs to happen.
>
> Thanks,
> John
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP
2010-06-08 16:49 ` Steve Sakoman
@ 2010-06-08 18:40 ` John Rigby
0 siblings, 0 replies; 9+ messages in thread
From: John Rigby @ 2010-06-08 18:40 UTC (permalink / raw)
To: u-boot
Looks like mpc85xx and mpc86xx share:
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a
LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.a
LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
endif
ifeq ($(CPU),mpc86xx)
LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.a
LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
endif
So something like
ifeq ($(SOC),omap3)
LIBS += $(CPUDIR)/omap-common/libomap-common.a
endif
ifeq(#(SOC),omap4)
LIBS += $(CPUDIR)/omap-common/libomap-common.a
endif
would work. But it is a bit brute force and not general.
You could also add a config.mk to arch/arm/cpu/armv7/omap[34] that
defines SOC_COMMON as omap-common and then add
ifdef SOC_COMMON
LIBS += $(CPUDIR)/$(SOC_COMMON)/lib$(SOC_COMMON).a
endif
to the root Makefile. This solution seems more clean but a little less
obvious.
On Tue, Jun 8, 2010 at 10:49 AM, Steve Sakoman <sakoman@gmail.com> wrote:
> On Fri, Jun 4, 2010 at 2:58 PM, John Rigby <jcrigby@gmail.com> wrote:
> > Aneesh:
> >
> > On Tue, May 25, 2010 at 12:39 AM, Aneesh V <aneesh@ti.com> wrote:
> >> Adding support for OMAP4430 SDP board based on the TI OMAP4430 SOC.
> >
> > ---
> >
> > arch/arm/cpu/armv7/omap4/reset.S:
> > Identical to omap3 version. I think they should be shared. Perhaps
> > have a arch/arm/cpu/armv7/omap directory for shared files.
>
> How about we call it omap-common?
>
> Is there a good example of how to handle this shared code? The
> existing build system will only build the contents of the omap4
> directory and not omap-common. Offhand I don't see any other
> architectures that do this, so I thought I would ask before making
> something up :-)
>
> Steve
>
> > arch/arm/cpu/armv7/omap4/timer.c:
> > Apart from the include of asm/arch/omap4.h this file is identical to
> > the omap3 version. See sharing comment above.
> >
> > arch/arm/include/asm/arch-omap4/cpu.h:
> > I think there is opportunity for sharing here as well. Not the whole
> file
> > so some refactoring needs to happen.
> >
> > Thanks,
> > John
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> >
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2010-06-08 18:40 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-05-25 6:39 [U-Boot] [PATCH 0/2] arm: Adding support for TI OMAP4430 SDP Aneesh V
2010-05-25 6:39 ` [U-Boot] [PATCH 1/2] arm: renaming the cpu arm_cortexa8 to armv7 Aneesh V
2010-05-25 6:39 ` [U-Boot] [PATCH 2/2] arm: cortexa9: adding support for TI OMAP4430 SDP Aneesh V
2010-06-04 21:58 ` John Rigby
2010-06-08 16:49 ` Steve Sakoman
2010-06-08 18:40 ` John Rigby
2010-06-05 19:55 ` Wolfgang Denk
2010-06-07 14:44 ` V, Aneesh
2010-06-07 20:05 ` Wolfgang Denk
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