[U-Boot] [PATCH 0/2] Support for MPC8308ERDB board

[U-Boot] [PATCH 0/2] Support for MPC8308ERDB board

[Ilya Yanok]

These patches add support for MPC8308 based development board
from Freescale.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>

[U-Boot] [PATCH 1/2] mpc8308: support for Freescale MPC8308 cpu

[Ilya Yanok]

This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also supported. eSDHC, NAND and USB may work but aren't
tested (using ULPI PHY requires additional patch).

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
 arch/powerpc/cpu/mpc83xx/cpu.c         |    1 +
 arch/powerpc/cpu/mpc83xx/speed.c       |    3 ++-
 arch/powerpc/include/asm/immap_83xx.h  |   15 +++++++++++++--
 arch/powerpc/include/asm/mpc8xxx_spi.h |    3 ++-
 include/mpc83xx.h                      |   20 ++++++++++++++++----
 5 files changed, 34 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index d3be909..4ce0a0f 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -55,6 +55,7 @@ int checkcpu(void)
 		char name[15];
 		u32 partid;
 	} cpu_type_list [] = {
+		CPU_TYPE_ENTRY(8308),
 		CPU_TYPE_ENTRY(8311),
 		CPU_TYPE_ENTRY(8313),
 		CPU_TYPE_ENTRY(8314),
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 500eef1..1aef7c4 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -202,7 +202,8 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || \
+	defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308)
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 6b42a73..24796a7 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -73,7 +73,11 @@ typedef struct sysconf83xx {
 	u32 obir;		/* Output Buffer Impedance Register */
 	u8 res8[0xC];
 	u32 pecr1;		/* PCI Express control register 1 */
+#ifdef CONFIG_MPC8308
+	u32 sdhccr;		/* eSDHC Control Registers for MPC8308 */
+#else
 	u32 pecr2;		/* PCI Express control register 2 */
+#endif
 	u8 res9[0xB8];
 } sysconf83xx_t;
 
@@ -589,7 +593,14 @@ typedef struct sdhc83xx {
  * SerDes
  */
 typedef struct serdes83xx {
-	u8 fixme[0x100];
+	u32 srdscr0;
+	u32 srdscr1;
+	u32 srdscr2;
+	u32 srdscr3;
+	u32 srdscr4;
+	u8 res0[0xc];
+	u32 srdsrstctl;
+	u8 res1[0xdc];
 } serdes83xx_t;
 
 /*
@@ -691,7 +702,7 @@ typedef struct immap {
 	u8			res7[0xC0000];
 } immap_t;
 
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 41737d3..b0082af 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -27,9 +27,10 @@
 
 #include <asm/types.h>
 
-#if defined(CONFIG_MPC834x) || \
+#if defined(CONFIG_MPC8308) || \
 	defined(CONFIG_MPC8313) || \
 	defined(CONFIG_MPC8315) || \
+	defined(CONFIG_MPC834x) || \
 	defined(CONFIG_MPC837x)
 
 typedef struct spi8xxx {
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 5214911..7c7ff4f 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -65,6 +65,7 @@
 #define PARTID_NO_E(spridr)		((spridr & 0xFFFE0000) >> 16)
 #define SPR_FAMILY(spridr)		((spridr & 0xFFF00000) >> 20)
 
+#define SPR_8308			0x8100
 #define SPR_831X_FAMILY			0x80B
 #define SPR_8311			0x80B2
 #define SPR_8313			0x80B0
@@ -473,7 +474,7 @@
 #define HRCWL_CE_TO_PLL_1X30		0x0000001E
 #define HRCWL_CE_TO_PLL_1X31		0x0000001F
 
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308)
 #define HRCWL_SVCOD			0x30000000
 #define HRCWL_SVCOD_SHIFT		28
 #define HRCWL_SVCOD_DIV_2		0x00000000
@@ -734,8 +735,8 @@
 #define SCCR_USBDRCM_2			0x00200000
 #define SCCR_USBDRCM_3			0x00300000
 
-#elif defined(CONFIG_MPC8315)
-/* SCCR bits - MPC8315 specific */
+#elif defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308)
+/* SCCR bits - MPC8315/MPC8308 specific */
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
 #define SCCR_TSEC1CM_0			0x00000000
@@ -750,6 +751,15 @@
 #define SCCR_TSEC2CM_2			0x20000000
 #define SCCR_TSEC2CM_3			0x30000000
 
+#if defined(CONFIG_MPC8308)
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+#endif
+
 #define SCCR_USBDRCM			0x00c00000
 #define SCCR_USBDRCM_SHIFT		22
 #define SCCR_USBDRCM_0			0x00000000
@@ -757,6 +767,7 @@
 #define SCCR_USBDRCM_2			0x00800000
 #define SCCR_USBDRCM_3			0x00c00000
 
+#if defined(CONFIG_MPC8315)
 #define SCCR_SATA1CM			0x00003000
 #define SCCR_SATA1CM_SHIFT		12
 #define SCCR_SATACM			0x00003c00
@@ -765,6 +776,7 @@
 #define SCCR_SATACM_1			0x00001400
 #define SCCR_SATACM_2			0x00002800
 #define SCCR_SATACM_3			0x00003c00
+#endif
 
 #define SCCR_TDMCM			0x00000030
 #define SCCR_TDMCM_SHIFT		4
-- 
1.6.2.5

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

This patch provides support for MPC8308ERDB development board from
Freescale with a minimal set of features:
 Dual UART is supported
 NOR flash is supported
 Both TSEC Ethernet controllers are supported
 PCI Express initialization is supported

The following features are enabled in configuration but not fully tested:
 I2C (used to get the board revision)
 I2C-connected RTC
 VSC7385 switch

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
 MAKEALL                                   |    1 +
 Makefile                                  |    3 +
 board/freescale/mpc8308erdb/Makefile      |   52 +++
 board/freescale/mpc8308erdb/config.mk     |    1 +
 board/freescale/mpc8308erdb/mpc8308erdb.c |  154 ++++++++
 board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
 include/configs/MPC8308ERDB.h             |  572 +++++++++++++++++++++++++++++
 7 files changed, 909 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/mpc8308erdb/Makefile
 create mode 100644 board/freescale/mpc8308erdb/config.mk
 create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
 create mode 100644 board/freescale/mpc8308erdb/sdram.c
 create mode 100644 include/configs/MPC8308ERDB.h

diff --git a/MAKEALL b/MAKEALL
index d6d5f5b..04653b7 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -359,6 +359,7 @@ LIST_8260="		\
 LIST_83xx="		\
 	caddy2		\
 	kmeter1		\
+	MPC8308ERDB	\
 	MPC8313ERDB_33	\
 	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
diff --git a/Makefile b/Makefile
index 55bb964..0dc2678 100644
--- a/Makefile
+++ b/Makefile
@@ -2233,6 +2233,9 @@ TASREG_config :		unconfig
 kmeter1_config: unconfig
 	@$(MKCONFIG) kmeter1 powerpc mpc83xx kmeter1 keymile
 
+MPC8308ERDB_config: unconfig
+	@$(MKCONFIG) -a MPC8308ERDB powerpc mpc83xx mpc8308erdb freescale
+
 MPC8313ERDB_33_config \
 MPC8313ERDB_66_config \
 MPC8313ERDB_NAND_33_config \
diff --git a/board/freescale/mpc8308erdb/Makefile b/board/freescale/mpc8308erdb/Makefile
new file mode 100644
index 0000000..e9bfa2b
--- /dev/null
+++ b/board/freescale/mpc8308erdb/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8308erdb/config.mk b/board/freescale/mpc8308erdb/config.mk
new file mode 100644
index 0000000..f768264
--- /dev/null
+++ b/board/freescale/mpc8308erdb/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xFE000000
diff --git a/board/freescale/mpc8308erdb/mpc8308erdb.c b/board/freescale/mpc8308erdb/mpc8308erdb.c
new file mode 100644
index 0000000..09c9875
--- /dev/null
+++ b/board/freescale/mpc8308erdb/mpc8308erdb.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ * Author: Freescale unknown
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;
+
+	return 0;
+}
+
+static u8 read_board_info(void)
+{
+	u8 val8;
+	i2c_set_bus_num(0);
+
+	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+		return val8;
+	else
+		return 0;
+}
+
+int checkboard(void)
+{
+	static const char * const rev_str[] = {
+		"1.0",
+		"<reserved>",
+		"<reserved>",
+		"<reserved>",
+		"<unknown>",
+	};
+	u8 info;
+	int i;
+
+	info = read_board_info();
+	i = (!info) ? 4 : info & 0x03;
+
+	printf("Board: Freescale MPC8308ERDB Rev %s\n", rev_str[i]);
+
+	return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	clk83xx_t *clk = (clk83xx_t *)&immr->clk;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
+				    SCCR_PCIEXP1CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg, 0);
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+	int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;
+	}
+#endif
+
+	return rc;
+}
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);	/* Initialize TSECs first */
+	return pci_eth_init(bis);
+}
+
+
diff --git a/board/freescale/mpc8308erdb/sdram.c b/board/freescale/mpc8308erdb/sdram.c
new file mode 100644
index 0000000..1759763
--- /dev/null
+++ b/board/freescale/mpc8308erdb/sdram.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ * Authors: Nick.Spence at freescale.com
+ *          Wilson.Lo at freescale.com
+ *          scottwood at freescale.com
+ *
+ * This files is  mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void resume_from_sleep(void)
+{
+	u32 magic = *(u32 *)0;
+
+	typedef void (*func_t)(void);
+	func_t resume = *(func_t *)4;
+
+	if (magic == 0xf5153ae5)
+		resume();
+
+	gd->flags &= ~GD_FLG_SILENT;
+	puts("\nResume from sleep failed: bad magic word\n");
+}
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
+		out_be32(&im->ddr.sdram_cfg,
+			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
+	} else {
+		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	}
+
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
diff --git a/include/configs/MPC8308ERDB.h b/include/configs/MPC8308ERDB.h
new file mode 100644
index 0000000..5b7f508
--- /dev/null
+++ b/include/configs/MPC8308ERDB.h
@@ -0,0 +1,572 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
+#define CONFIG_MPC831x		1 /* MPC831x CPU family */
+#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
+#define CONFIG_MPC8308ERDB	1 /* MPC8308ERDB board specific */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is SoC TSEC
+ * TSEC2 is VSC switch
+ */
+#define CONFIG_TSEC1
+#define CONFIG_VSC7385_ENET
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN)
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRH		0x01001003
+#define CFG_SICRL		0x00000040 /* 3.3V, no delay */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| 0x00010000  /* ODT_WR to CSn */ \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE)
+				/* 0x43080000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END		0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */
+
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
+
+#define CONFIG_SYS_BR0_PRELIM	(\
+		CONFIG_SYS_FLASH_BASE	/* Flash Base address */	|\
+		(2 << BR_PS_SHIFT)	/* 16 bit port size */		|\
+		BR_V)			/* valid */
+#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_BR2_PRELIM		0xf0000801 /* VSC7385 Base address */
+#define CONFIG_SYS_OR2_PRELIM		0xfffe09ff /* VSC7385, 128K bytes*/
+/* Access window base@VSC7385 base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
+/* Access window size 128K */
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED	400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0x51}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
+
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#define CONFIG_PCI
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
+					BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+					BATL_CACHEINHIBIT | \
+					BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+					BATL_CACHEINHIBIT | \
+					BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L	0
+#define CONFIG_SYS_IBAT7U	0
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"kernel_addr=FE080000\0"					\
+	"fdt_addr=FE280000\0"						\
+	"ramdisk_addr=FE290000\0"					\
+	"u-boot=mpc8308rdb/u-boot.bin\0"				\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr_r=C00000\0"						\
+	"hostname=mpc8308rdb\0"						\
+	"bootfile=mpc8308rdb/uImage\0"					\
+	"fdtfile=mpc8308rdb/mpc8308erdb.dtb\0"				\
+	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - {fdt_addr_r}\0"		\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
+		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};cp.b ${fileaddr} "			\
+		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
+	"upd=run load update\0"						\
+
+#endif	/* __CONFIG_H */
-- 
1.6.2.5

[U-Boot] [PATCH 1/2] mpc8308: support for Freescale MPC8308 cpu

[Wolfgang Denk]

Dear Ilya Yanok,

In message <1277055168-18596-2-git-send-email-yanok@emcraft.com> you wrote:
> This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
> NOR flash and integrated Ethernet controllers are supported.
> PCI Express is also supported. eSDHC, NAND and USB may work but aren't
> tested (using ULPI PHY requires additional patch).
> 
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
...
> -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
> +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || \
> +	defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308)

Please sort this list.

> -#elif defined(CONFIG_MPC8315)
> +#elif defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308)

Ditto.

> -#elif defined(CONFIG_MPC8315)
> +#elif defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308)

Ditto. ... and so on.

> +#if defined(CONFIG_MPC8308)
> +#define SCCR_SDHCCM			0x0c000000
> +#define SCCR_SDHCCM_SHIFT		26
> +#define SCCR_SDHCCM_0			0x00000000
> +#define SCCR_SDHCCM_1			0x04000000
> +#define SCCR_SDHCCM_2			0x08000000
> +#define SCCR_SDHCCM_3			0x0c000000
> +#endif

Would it make sense to write this as:

And: why do we need the #ifdef? Unused defines should not hurt?

	#define SCCR_SDHCCM_MASK	0x0c000000	/* is it a mask? */
	#define SCCR_SDHCCM_SHIFT	26
	#define SCCR_SDHCCM(arg)	((arg)<<SCCR_SDHCCM_SHIFT)


>  #define SCCR_USBDRCM			0x00c00000
>  #define SCCR_USBDRCM_SHIFT		22
>  #define SCCR_USBDRCM_0			0x00000000
> @@ -757,6 +767,7 @@
>  #define SCCR_USBDRCM_2			0x00800000
>  #define SCCR_USBDRCM_3			0x00c00000

Ah, I see you just follow precedent code. If Kim accepts this, I'm
fine with it, too.

> +#if defined(CONFIG_MPC8315)
>  #define SCCR_SATA1CM			0x00003000
>  #define SCCR_SATA1CM_SHIFT		12
>  #define SCCR_SATACM			0x00003c00
> @@ -765,6 +776,7 @@
>  #define SCCR_SATACM_1			0x00001400
>  #define SCCR_SATACM_2			0x00002800
>  #define SCCR_SATACM_3			0x00003c00
> +#endif

Do we need that #ifdef? Ok, the #defines don't apply to the 8308, but
do they hurt if they are just there, unused?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The world is no nursery.                              - Sigmund Freud

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Wolfgang Denk]

Dear Ilya Yanok,

In message <1277055168-18596-3-git-send-email-yanok@emcraft.com> you wrote:
> This patch provides support for MPC8308ERDB development board from
> Freescale with a minimal set of features:
>  Dual UART is supported
>  NOR flash is supported
>  Both TSEC Ethernet controllers are supported
>  PCI Express initialization is supported
> 
> The following features are enabled in configuration but not fully tested:
>  I2C (used to get the board revision)
>  I2C-connected RTC
>  VSC7385 switch
...

>  MAKEALL                                   |    1 +
>  Makefile                                  |    3 +
>  board/freescale/mpc8308erdb/Makefile      |   52 +++
>  board/freescale/mpc8308erdb/config.mk     |    1 +
>  board/freescale/mpc8308erdb/mpc8308erdb.c |  154 ++++++++
>  board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
>  include/configs/MPC8308ERDB.h             |  572 +++++++++++++++++++++++++++++
>  7 files changed, 909 insertions(+), 0 deletions(-)
>  create mode 100644 board/freescale/mpc8308erdb/Makefile
>  create mode 100644 board/freescale/mpc8308erdb/config.mk
>  create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
>  create mode 100644 board/freescale/mpc8308erdb/sdram.c
>  create mode 100644 include/configs/MPC8308ERDB.h

Entry to MAINTAINERS missing.

> diff --git a/Makefile b/Makefile
> index 55bb964..0dc2678 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -2233,6 +2233,9 @@ TASREG_config :		unconfig
>  kmeter1_config: unconfig
>  	@$(MKCONFIG) kmeter1 powerpc mpc83xx kmeter1 keymile
>  
> +MPC8308ERDB_config: unconfig
> +	@$(MKCONFIG) -a MPC8308ERDB powerpc mpc83xx mpc8308erdb freescale

NAK. Please rebase your code against the "next" branch. We don't
accept any board entries to the top level Makefile any more. Please
add to boards.cfg instead.

> --- /dev/null
> +++ b/board/freescale/mpc8308erdb/mpc8308erdb.c
> @@ -0,0 +1,154 @@
> +/*
> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
> + *
> + * Author: Freescale unknown

Maybe "Initial author" ?

> +int board_early_init_f(void)
> +{
> +	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> +
> +	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
> +		gd->flags |= GD_FLG_SILENT;

What exactly is this good for?

> +/*
> + * Miscellaneous late-boot configurations
> + *
> + * If a VSC7385 microcode image is present, then upload it.
> +*/
> +int misc_init_r(void)
> +{
> +	int rc = 0;

Please drop the variable.

> +#ifdef CONFIG_VSC7385_IMAGE
> +	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
> +		CONFIG_VSC7385_IMAGE_SIZE)) {
> +		puts("Failure uploading VSC7385 microcode.\n");
> +		rc = 1;
	return 1;

> +	}
> +#endif
> +
> +	return rc;

	return 0;

> +int board_eth_init(bd_t *bis)
> +{
> +	cpu_eth_init(bis);	/* Initialize TSECs first */

I think it's wrong to ignore the return code here.

> +	return pci_eth_init(bis);
> +}
> +
> +

Please remove trailing empty lines.


> +/* Fixed sdram init -- doesn't use serial presence detect.
> + *
> + * This is useful for faster booting in configs where the RAM is unlikely
> + * to be changed, or for things like NAND booting where space is tight.
> + */
> +static long fixed_sdram(void)
> +{
> +	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> +	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
> +	u32 msize_log2 = __ilog2(msize);
> +
> +	out_be32(&im->sysconf.ddrlaw[0].bar,
> +			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
> +	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
> +	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
> +
> +	/*
> +	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
> +	 * or the DDR2 controller may fail to initialize correctly.
> +	 */
> +	udelay(50000);
> +
> +	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
> +	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
> +
> +	/* Currently we use only one CS, so disable the other bank. */
> +	out_be32(&im->ddr.cs_config[1], 0);
> +
> +	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
> +	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
> +	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
> +	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
> +	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
> +
> +	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
> +		out_be32(&im->ddr.sdram_cfg,
> +			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
> +	} else {
> +		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
> +	}
> +
> +	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
> +	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
> +	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
> +
> +	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
> +	sync();
> +
> +	/* enable DDR controller */
> +	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
> +	sync();
> +
> +	return msize;

Please test RAM and verify the size using get_mem_size().

> +}
> +
> +phys_size_t initdram(int board_type)
> +{
> +	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> +	u32 msize;
> +
> +	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
> +		return -1;
> +
> +	/* DDR SDRAM */
> +	msize = fixed_sdram();
> +
> +	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
> +		resume_from_sleep();
> +
> +	/* return total bus SDRAM size(bytes)  -- DDR */
> +	return msize;
> +}
> diff --git a/include/configs/MPC8308ERDB.h b/include/configs/MPC8308ERDB.h
> new file mode 100644
> index 0000000..5b7f508
> --- /dev/null
> +++ b/include/configs/MPC8308ERDB.h
> @@ -0,0 +1,572 @@
> +/*
> + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
> + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
> + *
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_E300		1 /* E300 family */
> +#define CONFIG_MPC83xx		1 /* MPC83xx family */
> +#define CONFIG_MPC831x		1 /* MPC831x CPU family */
> +#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
> +#define CONFIG_MPC8308ERDB	1 /* MPC8308ERDB board specific */
> +
> +#define CONFIG_MISC_INIT_R
> +
> +/*
> + * On-board devices
> + *
> + * TSEC1 is SoC TSEC
> + * TSEC2 is VSC switch
> + */
> +#define CONFIG_TSEC1
> +#define CONFIG_VSC7385_ENET
> +
> +/*
> + * System Clock Setup
> + */
> +#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
> +#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
> +
> +/*
> + * Hardware Reset Configuration Word
> + * if CLKIN is 66.66MHz, then
> + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
> + * We choose the A type silicon as default, so the core is 400Mhz.
> + */
> +#define CONFIG_SYS_HRCW_LOW (\
> +	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
> +	HRCWL_DDR_TO_SCB_CLK_2X1 |\
> +	HRCWL_SVCOD_DIV_2 |\
> +	HRCWL_CSB_TO_CLKIN_4X1 |\
> +	HRCWL_CORE_TO_CSB_3X1)
> +/*
> + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
> + * in 8308's HRCWH according to the manual, but original Freescale's
> + * code has them and I've expirienced some problems using the board
> + * with BDI3000 attached when I've tried to set these bits to zero
> + * (UART doesn't work after the 'reset run' command).
> + */
> +#define CONFIG_SYS_HRCW_HIGH (\
> +	HRCWH_PCI_HOST |\
> +	HRCWH_PCI1_ARBITER_ENABLE |\
> +	HRCWH_CORE_ENABLE |\
> +	HRCWH_FROM_0X00000100 |\
> +	HRCWH_BOOTSEQ_DISABLE |\
> +	HRCWH_SW_WATCHDOG_DISABLE |\
> +	HRCWH_ROM_LOC_LOCAL_16BIT |\
> +	HRCWH_RL_EXT_LEGACY |\
> +	HRCWH_TSEC1M_IN_RGMII |\
> +	HRCWH_TSEC2M_IN_RGMII |\
> +	HRCWH_BIG_ENDIAN)


Kim, can you please comment?


> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_PCI

Please sort list.


Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"If you own a machine, you are in turn owned by it,  and  spend  your
time serving it..."    - Marion Zimmer Bradley, _The Forbidden Tower_

[U-Boot] [PATCH 1/2] mpc8308: support for Freescale MPC8308 cpu

[Ilya Yanok]

Dear Wolfgang,

thanks for your review.

On 21.06.2010 11:44, Wolfgang Denk wrote:
>> This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
>> NOR flash and integrated Ethernet controllers are supported.
>> PCI Express is also supported. eSDHC, NAND and USB may work but aren't
>> tested (using ULPI PHY requires additional patch).
>>
>> Signed-off-by: Ilya Yanok<yanok@emcraft.com>
>>      
> ...
>    
>> -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
>> +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || \
>> +	defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308)
>>      
> Please sort this list.
>    

Fixed.

>> +#if defined(CONFIG_MPC8308)
>> +#define SCCR_SDHCCM			0x0c000000
>> +#define SCCR_SDHCCM_SHIFT		26
>> +#define SCCR_SDHCCM_0			0x00000000
>> +#define SCCR_SDHCCM_1			0x04000000
>> +#define SCCR_SDHCCM_2			0x08000000
>> +#define SCCR_SDHCCM_3			0x0c000000
>> +#endif
>>      
> Would it make sense to write this as:
>
> And: why do we need the #ifdef? Unused defines should not hurt?
>
> 	#define SCCR_SDHCCM_MASK	0x0c000000	/* is it a mask? */
> 	#define SCCR_SDHCCM_SHIFT	26
> 	#define SCCR_SDHCCM(arg)	((arg)<<SCCR_SDHCCM_SHIFT)
>
>    

As you already mentioned I'm just following the style used in this file.

>> +#if defined(CONFIG_MPC8315)
>>   #define SCCR_SATA1CM			0x00003000
>>   #define SCCR_SATA1CM_SHIFT		12
>>   #define SCCR_SATACM			0x00003c00
>> @@ -765,6 +776,7 @@
>>   #define SCCR_SATACM_1			0x00001400
>>   #define SCCR_SATACM_2			0x00002800
>>   #define SCCR_SATACM_3			0x00003c00
>> +#endif
>>      
> Do we need that #ifdef? Ok, the #defines don't apply to the 8308, but
> do they hurt if they are just there, unused?
>    

Well, it seems to be safer not to have unused defines so that you can't 
erroneously use some define not applicable for current CPU, but if you 
wish I'll remove these ifdefs.

Regards, Ilya.

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

Dear Wolfgang,

On 21.06.2010 11:44, Wolfgang Denk wrote:
>>   MAKEALL                                   |    1 +
>>   Makefile                                  |    3 +
>>   board/freescale/mpc8308erdb/Makefile      |   52 +++
>>   board/freescale/mpc8308erdb/config.mk     |    1 +
>>   board/freescale/mpc8308erdb/mpc8308erdb.c |  154 ++++++++
>>   board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
>>   include/configs/MPC8308ERDB.h             |  572 +++++++++++++++++++++++++++++
>>   7 files changed, 909 insertions(+), 0 deletions(-)
>>   create mode 100644 board/freescale/mpc8308erdb/Makefile
>>   create mode 100644 board/freescale/mpc8308erdb/config.mk
>>   create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
>>   create mode 100644 board/freescale/mpc8308erdb/sdram.c
>>   create mode 100644 include/configs/MPC8308ERDB.h
>>      
> Entry to MAINTAINERS missing.
>    

Should I add you as a maintainer or myself?

>> diff --git a/Makefile b/Makefile
>> index 55bb964..0dc2678 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -2233,6 +2233,9 @@ TASREG_config :		unconfig
>>   kmeter1_config: unconfig
>>   	@$(MKCONFIG) kmeter1 powerpc mpc83xx kmeter1 keymile
>>
>> +MPC8308ERDB_config: unconfig
>> +	@$(MKCONFIG) -a MPC8308ERDB powerpc mpc83xx mpc8308erdb freescale
>>      
> NAK. Please rebase your code against the "next" branch. We don't
> accept any board entries to the top level Makefile any more. Please
> add to boards.cfg instead.
>    

Done.

>> --- /dev/null
>> +++ b/board/freescale/mpc8308erdb/mpc8308erdb.c
>> @@ -0,0 +1,154 @@
>> +/*
>> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
>> + *
>> + * Author: Freescale unknown
>>      
> Maybe "Initial author" ?
>    

Dropped this line.

>> +int board_early_init_f(void)
>> +{
>> +	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
>> +
>> +	if (in_be32(&im->pmc.pmccr1)&  PMCCR1_POWER_OFF)
>> +		gd->flags |= GD_FLG_SILENT;
>>      
> What exactly is this good for?
>    

That's for making board silent then it comes out of sleep (not printing 
version info, checkcpu() output and so on). Actually I've not tested 
sleep/wakeup functionality but the code looks correct.

>> +/*
>> + * Miscellaneous late-boot configurations
>> + *
>> + * If a VSC7385 microcode image is present, then upload it.
>> +*/
>> +int misc_init_r(void)
>> +{
>> +	int rc = 0;
>>      
> Please drop the variable.
>    

Done.

>> +#ifdef CONFIG_VSC7385_IMAGE
>> +	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
>> +		CONFIG_VSC7385_IMAGE_SIZE)) {
>> +		puts("Failure uploading VSC7385 microcode.\n");
>> +		rc = 1;
>>      
> 	return 1;
>
>    
>> +	}
>> +#endif
>> +
>> +	return rc;
>>      
> 	return 0;
>
>    
>> +int board_eth_init(bd_t *bis)
>> +{
>> +	cpu_eth_init(bis);	/* Initialize TSECs first */
>>      
> I think it's wrong to ignore the return code here.
>    

What makes you think so? What can we do with the return code here? Print 
warning? If we return error from board_eth_init() calling code will call 
cpu_eth_init() again which is useless as we have already called it.

>> +	return pci_eth_init(bis);
>> +}
>> +
>> +
>>      
> Please remove trailing empty lines.
>    

Fixed.

>> +/* Fixed sdram init -- doesn't use serial presence detect.
>> + *
>> + * This is useful for faster booting in configs where the RAM is unlikely
>> + * to be changed, or for things like NAND booting where space is tight.
>> + */
>> +static long fixed_sdram(void)
>> +{
>> +	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
>> +	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
>> +	u32 msize_log2 = __ilog2(msize);
>> +
>> +	out_be32(&im->sysconf.ddrlaw[0].bar,
>> +			CONFIG_SYS_DDR_SDRAM_BASE&  0xfffff000);
>> +	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
>> +	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
>> +
>> +	/*
>> +	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
>> +	 * or the DDR2 controller may fail to initialize correctly.
>> +	 */
>> +	udelay(50000);
>> +
>> +	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1)>>  24);
>> +	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
>> +
>> +	/* Currently we use only one CS, so disable the other bank. */
>> +	out_be32(&im->ddr.cs_config[1], 0);
>> +
>> +	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
>> +	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
>> +	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
>> +	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
>> +	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
>> +
>> +	if (in_be32(&im->pmc.pmccr1)&  PMCCR1_POWER_OFF) {
>> +		out_be32(&im->ddr.sdram_cfg,
>> +			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
>> +	} else {
>> +		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
>> +	}
>> +
>> +	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
>> +	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
>> +	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
>> +
>> +	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
>> +	sync();
>> +
>> +	/* enable DDR controller */
>> +	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
>> +	sync();
>> +
>> +	return msize;
>>      
> Please test RAM and verify the size using get_mem_size().
>    

Done.

>> +
>> +/*
>> + * Hardware Reset Configuration Word
>> + * if CLKIN is 66.66MHz, then
>> + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
>> + * We choose the A type silicon as default, so the core is 400Mhz.
>> + */
>> +#define CONFIG_SYS_HRCW_LOW (\
>> +	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
>> +	HRCWL_DDR_TO_SCB_CLK_2X1 |\
>> +	HRCWL_SVCOD_DIV_2 |\
>> +	HRCWL_CSB_TO_CLKIN_4X1 |\
>> +	HRCWL_CORE_TO_CSB_3X1)
>> +/*
>> + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
>> + * in 8308's HRCWH according to the manual, but original Freescale's
>> + * code has them and I've expirienced some problems using the board
>> + * with BDI3000 attached when I've tried to set these bits to zero
>> + * (UART doesn't work after the 'reset run' command).
>> + */
>> +#define CONFIG_SYS_HRCW_HIGH (\
>> +	HRCWH_PCI_HOST |\
>> +	HRCWH_PCI1_ARBITER_ENABLE |\
>> +	HRCWH_CORE_ENABLE |\
>> +	HRCWH_FROM_0X00000100 |\
>> +	HRCWH_BOOTSEQ_DISABLE |\
>> +	HRCWH_SW_WATCHDOG_DISABLE |\
>> +	HRCWH_ROM_LOC_LOCAL_16BIT |\
>> +	HRCWH_RL_EXT_LEGACY |\
>> +	HRCWH_TSEC1M_IN_RGMII |\
>> +	HRCWH_TSEC2M_IN_RGMII |\
>> +	HRCWH_BIG_ENDIAN)
>>      
>
> Kim, can you please comment?
>
>
>    
>> +#include<config_cmd_default.h>
>> +
>> +#define CONFIG_CMD_PING
>> +#define CONFIG_CMD_DHCP
>> +#define CONFIG_CMD_NET
>> +#define CONFIG_CMD_I2C
>> +#define CONFIG_CMD_MII
>> +#define CONFIG_CMD_DATE
>> +#define CONFIG_CMD_PCI
>>      
> Please sort list.
>    

Fixed.

I'l wait for a while for other comments and then repost the updated patches.

Regards, Ilya.

[U-Boot] [PATCH 1/2] mpc8308: support for Freescale MPC8308 cpu

[Wolfgang Denk]

Dear Ilya,

In message <4C1F4FE0.6050804@emcraft.com> you wrote:
> 
> > Do we need that #ifdef? Ok, the #defines don't apply to the 8308, but
> > do they hurt if they are just there, unused?
> 
> Well, it seems to be safer not to have unused defines so that you can't 
> erroneously use some define not applicable for current CPU, but if you 
> wish I'll remove these ifdefs.

Please remove them.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If you can't beat it or corrupt it, you pretend it was your  idea  in
the first place.                 - Terry Pratchett, _Guards! Guards!_

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Wolfgang Denk]

Dear Ilya Yanok,

In message <4C1F5A54.4050908@emcraft.com> you wrote:
> 
> > Entry to MAINTAINERS missing.
> 
> Should I add you as a maintainer or myself?

You did the actual work...

> >> +int board_eth_init(bd_t *bis)
> >> +{
> >> +	cpu_eth_init(bis);	/* Initialize TSECs first */
> >>      
> > I think it's wrong to ignore the return code here.
> 
> What makes you think so? What can we do with the return code here? Print 
> warning? If we return error from board_eth_init() calling code will call 
> cpu_eth_init() again which is useless as we have already called it.

> >> +	return pci_eth_init(bis);

My understanding is that pci_eth_init() and board_eth_init() return
the number of NIC's found - should that number not include the number
of successfully initialized TSECs?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The use of COBOL cripples the mind; its teaching  should,  therefore,
be regarded as a criminal offence.
          -- Edsger W. Dijkstra, SIGPLAN Notices, Volume 17, Number 5

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ben Warren]

Wolfgang & Ilya,

Sorry for responding to both of you at the same time...

On 6/22/2010 11:14 AM, Wolfgang Denk wrote:
> Dear Ilya Yanok,
>
> In message<4C1F5A54.4050908@emcraft.com>  you wrote:
>    
>>      
>>> Entry to MAINTAINERS missing.
>>>        
>> Should I add you as a maintainer or myself?
>>      
> You did the actual work...
>
>    
>>>> +int board_eth_init(bd_t *bis)
>>>> +{
>>>> +	cpu_eth_init(bis);	/* Initialize TSECs first */
>>>>
>>>>          
>>> I think it's wrong to ignore the return code here.
>>>        
>> What makes you think so? What can we do with the return code here? Print
>> warning? If we return error from board_eth_init() calling code will call
>> cpu_eth_init() again which is useless as we have already called it.
>>      
>    
Yes, print a warning if < 0.  As you've noticed, returning -1 wouldn't 
be good.  I'm not aware of a U-boot policy for handling hardware 
problems other than printf.
>>>> +	return pci_eth_init(bis);
>>>>          
> My understanding is that pci_eth_init() and board_eth_init() return
> the number of NIC's found - should that number not include the number
> of successfully initialized TSECs?
>
>    
Yes, please.  Something like:

int board_eth_init(bd_t *bis)
{
     int rc, num_if = 0;
     if ((rc = cpu_eth_init(bis)) >= 0)
     {
         num_if += rc;
     } else {
         print error message
     }
     if ((rc = pci_eth_init(bis)) >= 0)
     {
         num_if += rc;
     } else {
         print error message
     }
     return num_if;
}

I'm working on changing net/eth.c to be less kludgy, but am having a 
hard time setting up my test bed.  Hopefully in the next few days.

> Best regards,
>
> Wolfgang Denk
>
>    
regards,
Ben

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Kim Phillips]

On Sun, 20 Jun 2010 21:32:48 +0400
Ilya Yanok <yanok@emcraft.com> wrote:

> This patch provides support for MPC8308ERDB development board from
> Freescale with a minimal set of features:
>  Dual UART is supported
>  NOR flash is supported
>  Both TSEC Ethernet controllers are supported
>  PCI Express initialization is supported
> 
> The following features are enabled in configuration but not fully tested:
>  I2C (used to get the board revision)
>  I2C-connected RTC
>  VSC7385 switch
> 
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---

thanks for submitting this, Ilya.

The comments below are in addition to Wolfgang's.

>  MAKEALL                                   |    1 +
>  Makefile                                  |    3 +
>  board/freescale/mpc8308erdb/Makefile      |   52 +++
>  board/freescale/mpc8308erdb/config.mk     |    1 +
>  board/freescale/mpc8308erdb/mpc8308erdb.c |  154 ++++++++
>  board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
>  include/configs/MPC8308ERDB.h             |  572 +++++++++++++++++++++++++++++
>  7 files changed, 909 insertions(+), 0 deletions(-)
>  create mode 100644 board/freescale/mpc8308erdb/Makefile
>  create mode 100644 board/freescale/mpc8308erdb/config.mk
>  create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
>  create mode 100644 board/freescale/mpc8308erdb/sdram.c
>  create mode 100644 include/configs/MPC8308ERDB.h

missing a doc/README.mpc8308erdb file.

>  
> +MPC8308ERDB_config: unconfig
> +	@$(MKCONFIG) -a MPC8308ERDB powerpc mpc83xx mpc8308erdb freescale
> +

patch doesn't apply to WD's next branch:

---
Applying: MPC8308ERDB: minimal support for devboard from Freescale
error: patch failed: Makefile:2233
error: Makefile: patch does not apply
/home/r1aaha/git/u-boot/.git/rebase-apply/patch:112: new blank line at EOF.
+
Patch failed at 0002 MPC8308ERDB: minimal support for devboard from Freescale
When you have resolved this problem run "git am --resolved".
If you would prefer to skip this patch, instead run "git am --skip".
To restore the original branch and stop patching run "git am --abort".
---

please rebase on top of Wolfgang's next branch, and also fix the new
blank line at EOF.

> +#define CONFIG_MPC831x		1 /* MPC831x CPU family */

I don't see the 8308 being a member of the 831x family; e.g., upper
spridr bits are 0x810, which don't match those of 831x: 0x80B.
Please introduce a new CONFIG_MPC830x.

> +/*
> + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
> + * in 8308's HRCWH according to the manual, but original Freescale's
> + * code has them and I've expirienced some problems using the board
> + * with BDI3000 attached when I've tried to set these bits to zero
> + * (UART doesn't work after the 'reset run' command).

is the BDI overriding the RCW in this case?  it's not clear..

> +#define CFG_SICRH		0x01001003
> +#define CFG_SICRL		0x00000040 /* 3.3V, no delay */

the CFG_ prefix is no longer - are these even being used anywhere?

> +#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
> +				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)

| HID0_ENABLE_INSTRUCTION_CACHE?

Thanks,

Kim

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

Hi Wolfgang,

On 22.06.2010 22:14, Wolfgang Denk wrote:
>>> Entry to MAINTAINERS missing.
>>>        
>> Should I add you as a maintainer or myself?
>>      
> You did the actual work...
>    

but I fear I won't be able to maintain it... I don't have much free time 
to spend now...

>>> +	return pci_eth_init(bis);
>>>        
> My understanding is that pci_eth_init() and board_eth_init() return
> the number of NIC's found - should that number not include the number
> of successfully initialized TSECs?
>    

Ok. I get your point. Actually, as for now code in net/eth.c just checks 
board_eth_init() value to be negative or not so there is no difference 
between different non-negative values. But I'll do it like Ben asked.

Regards, Ilya.

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

Hi Ben,

On 22.06.2010 23:10, Ben Warren wrote:
>>>>> +int board_eth_init(bd_t *bis)
>>>>> +{
>>>>> +    cpu_eth_init(bis);    /* Initialize TSECs first */
>>>>>
>>>> I think it's wrong to ignore the return code here.
>>> What makes you think so? What can we do with the return code here? 
>>> Print
>>> warning? If we return error from board_eth_init() calling code will 
>>> call
>>> cpu_eth_init() again which is useless as we have already called it.
>
> Yes, print a warning if < 0.  As you've noticed, returning -1 wouldn't 
> be good.  I'm not aware of a U-boot policy for handling hardware 
> problems other than printf.

Actually I thought that controllers missing in the "NET: " line would be 
enough but I'll add a warning if you ask.

>>>>> +    return pci_eth_init(bis);
>> My understanding is that pci_eth_init() and board_eth_init() return
>> the number of NIC's found - should that number not include the number
>> of successfully initialized TSECs?
>>
> Yes, please.  Something like:
>
> int board_eth_init(bd_t *bis)
> {
>     int rc, num_if = 0;
>     if ((rc = cpu_eth_init(bis)) >= 0)
>     {
>         num_if += rc;
>     } else {
>         print error message
>     }
>     if ((rc = pci_eth_init(bis)) >= 0)
>     {
>         num_if += rc;
>     } else {
>         print error message
>     }
>     return num_if;
> }
>
> I'm working on changing net/eth.c to be less kludgy, but am having a 
> hard time setting up my test bed.  Hopefully in the next few days.

I'll do like you proposed.

Regards, Ilya.

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

Hi Kim,

Thanks for your review.

On 23.06.2010 04:17, Kim Phillips wrote:
>>   MAKEALL                                   |    1 +
>>   Makefile                                  |    3 +
>>   board/freescale/mpc8308erdb/Makefile      |   52 +++
>>   board/freescale/mpc8308erdb/config.mk     |    1 +
>>   board/freescale/mpc8308erdb/mpc8308erdb.c |  154 ++++++++
>>   board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
>>   include/configs/MPC8308ERDB.h             |  572 +++++++++++++++++++++++++++++
>>   7 files changed, 909 insertions(+), 0 deletions(-)
>>   create mode 100644 board/freescale/mpc8308erdb/Makefile
>>   create mode 100644 board/freescale/mpc8308erdb/config.mk
>>   create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
>>   create mode 100644 board/freescale/mpc8308erdb/sdram.c
>>   create mode 100644 include/configs/MPC8308ERDB.h
>>      
> missing a doc/README.mpc8308erdb file.
>    

Hm.. Wolfgang, do we really need this?
Well, I hope I'd be able to reuse most of doc/README.mpc8315erdb...

>>
>> +MPC8308ERDB_config: unconfig
>> +	@$(MKCONFIG) -a MPC8308ERDB powerpc mpc83xx mpc8308erdb freescale
>> +
>>      
> patch doesn't apply to WD's next branch:
>
> ---
> Applying: MPC8308ERDB: minimal support for devboard from Freescale
> error: patch failed: Makefile:2233
> error: Makefile: patch does not apply
> /home/r1aaha/git/u-boot/.git/rebase-apply/patch:112: new blank line at EOF.
> +
> Patch failed at 0002 MPC8308ERDB: minimal support for devboard from Freescale
> When you have resolved this problem run "git am --resolved".
> If you would prefer to skip this patch, instead run "git am --skip".
> To restore the original branch and stop patching run "git am --abort".
> ---
>
> please rebase on top of Wolfgang's next branch, and also fix the new
> blank line at EOF.
>    

Yes, I've already done this.

>> +#define CONFIG_MPC831x		1 /* MPC831x CPU family */
>>      
> I don't see the 8308 being a member of the 831x family; e.g., upper
> spridr bits are 0x810, which don't match those of 831x: 0x80B.
> Please introduce a new CONFIG_MPC830x.
>    

Actually I've noticed this myself... But 8308 has many things common 
with 831x and I'm not sure if there is a family of 830x (I can see only 
8308 on Freescale website).

Well, I'll do as you propose.

>> +/*
>> + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
>> + * in 8308's HRCWH according to the manual, but original Freescale's
>> + * code has them and I've expirienced some problems using the board
>> + * with BDI3000 attached when I've tried to set these bits to zero
>> + * (UART doesn't work after the 'reset run' command).
>>      
> is the BDI overriding the RCW in this case?  it's not clear..
>    

Yes, my default BDI configuration overrides RCW with 0xa0606c00 
0x44060000 (with HRCWH_PCI_HOST and HRCWH_PCI1_ARBITER_ENABLE bits set) 
to be able to program empty flash.
My test sequence is as follows:
0. I had BDI overriding RCW and programmed U-Boot with the same RCW values.
1. I compiled new U-Boot image without HRCWH_PCI* bits and reflashed it 
from U-Boot itself.
2. Then I rebooted the board with the U-Boot 'reset' command. Everything 
works fine.
3. Reseted the board with 'reset run' command from the BDI. Everything 
works well too (recall that BDI is configured to override RCW with old 
value).
4. Then I've changed BDI configuration disabling the RCW override. 
Everything works.
5. But if I configure BDI to override RCW with new value (without 
HRCWH_PCI* bits) I can't see anything on serial console after reset (but 
it looks like U-Boot is started correctly, at least execution address 
looks correct).

>> +#define CFG_SICRH		0x01001003
>> +#define CFG_SICRL		0x00000040 /* 3.3V, no delay */
>>      
> the CFG_ prefix is no longer - are these even being used anywhere?
>    

Ouch... That's my bug. I'll fix it.

>> +#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
>> +				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
>>      
> | HID0_ENABLE_INSTRUCTION_CACHE?
>    

Yes, you are right. I'll add it.

Regards, Ilya.

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Wolfgang Denk]

Dear Ilya Yanok,

In message <4C227CD8.2080002@emcraft.com> you wrote:
> 
> > missing a doc/README.mpc8308erdb file.
> 
> Hm.. Wolfgang, do we really need this?

Only if there is somethign spoecial about this board which is worth
being documented.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There has been an alarming increase in the number of things you  know
nothing about.

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

Dear Kim,

On 23.06.2010 04:17, Kim Phillips wrote:
>> +#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
>> +				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
>>      
> | HID0_ENABLE_INSTRUCTION_CACHE?
>    

I've enabled icache and now the board sometimes resets twice after 
U-Boot 'reset' command:

=> re
Resetting the board.


U-Boot 2010.06-rc3-00020-g093a164 (Jun 24 2010 - 17:45:17) MPC83XX

Reset Status: Software Hard, External/Internal Soft, External/Internal Hard

CPU:   e300c3, MPC8308, Rev: 1.0 at 400 MHz, CSB: 133.333 MHz
Board: Freescale MPC8308ERDB Rev 1.0
I2C:   ready
DRAM:

U-Boot 2010.06-rc3-00020-g093a164 (Jun 24 2010 - 17:45:17) MPC83XX

Reset Status: External/Internal Soft, External/Internal Hard

CPU:   e300c3, MPC8308, Rev: 1.0 at 400 MHz, CSB: 133.333 MHz
Board: Freescale MPC8308ERDB Rev 1.0
I2C:   ready
DRAM:  128 MiB
FLASH: 8 MiB
PCIE0: link
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC1: No support for PHY id ffffffff; assuming generic
eTSEC0, eTSEC1
Hit any key to stop autoboot:  0
=>

(It doesn't always stop at "DRAM:" line but that position is most frequent)
Maybe you have some ideas on this subject?

Regards, Ilya.

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Kim Phillips]

On Thu, 24 Jun 2010 19:59:13 +0400
Ilya Yanok <yanok@emcraft.com> wrote:

> On 23.06.2010 04:17, Kim Phillips wrote:
> >> +#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
> >> +				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
> >>      
> > | HID0_ENABLE_INSTRUCTION_CACHE?
> 
> I've enabled icache and now the board sometimes resets twice after 
> U-Boot 'reset' command:

> (It doesn't always stop at "DRAM:" line but that position is most frequent)
> Maybe you have some ideas on this subject?

hmm, if it's only on soft-resets, can you try adding
HID0_ENABLE_INSTRUCTION_CACHE to CONFIG_SYS_HID0_INIT in addition to
_FINAL?  Some cache state is preserved over a soft-reset...

Thanks,

Kim

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

Hi Kim,

On 24.06.2010 22:00, Kim Phillips wrote:
>> I've enabled icache and now the board sometimes resets twice after
>> U-Boot 'reset' command:
>>      
>    
>> (It doesn't always stop at "DRAM:" line but that position is most frequent)
>> Maybe you have some ideas on this subject?
>>      
> hmm, if it's only on soft-resets, can you try adding
> HID0_ENABLE_INSTRUCTION_CACHE to CONFIG_SYS_HID0_INIT in addition to
> _FINAL?  Some cache state is preserved over a soft-reset...
>    

Thanks for your advice but this doesn't help...

Regards, Ilya.

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Aggrwal Poonam-B10812]

> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
[mailto:u-boot-bounces at lists.denx.de]
> On Behalf Of Ilya Yanok
> Sent: Friday, June 25, 2010 1:07 AM
> To: Phillips Kim-R1AAHA
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for
> devboard from Freescale
> 
> Hi Kim,
> 
> On 24.06.2010 22:00, Kim Phillips wrote:
> >> I've enabled icache and now the board sometimes resets twice after
> >> U-Boot 'reset' command:
> >>
> >
> >> (It doesn't always stop at "DRAM:" line but that position is most
> >> frequent) Maybe you have some ideas on this subject?
> >>
> > hmm, if it's only on soft-resets, can you try adding
> > HID0_ENABLE_INSTRUCTION_CACHE to CONFIG_SYS_HID0_INIT in addition to
> > _FINAL?  Some cache state is preserved over a soft-reset...
> >
> 
> Thanks for your advice but this doesn't help...
>
Just from my experience on few other boards, this could be a DDR
configuration issue.
Can you try to run at lower frequencies?..Or may be playing with DDR
controller timings.

Regards
Poonam
 
> Regards, Ilya.
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/2] mpc8308: support for Freescale MPC8308 cpu

[Ilya Yanok]

This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also supported. eSDHC, NAND and USB may work but aren't
tested (using ULPI PHY requires additional patch).

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
 arch/powerpc/cpu/mpc83xx/cpu.c         |    1 +
 arch/powerpc/cpu/mpc83xx/speed.c       |   23 +++++++++++++++--------
 arch/powerpc/include/asm/global_data.h |    6 ++++--
 arch/powerpc/include/asm/immap_83xx.h  |   15 +++++++++++++--
 arch/powerpc/include/asm/mpc8xxx_spi.h |    3 ++-
 include/mpc83xx.h                      |   27 +++++++++++++++++++--------
 6 files changed, 54 insertions(+), 21 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index d3be909..4ce0a0f 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -55,6 +55,7 @@ int checkcpu(void)
 		char name[15];
 		u32 partid;
 	} cpu_type_list [] = {
+		CPU_TYPE_ENTRY(8308),
 		CPU_TYPE_ENTRY(8311),
 		CPU_TYPE_ENTRY(8313),
 		CPU_TYPE_ENTRY(8314),
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 500eef1..67591ab 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -100,7 +100,8 @@ int get_clocks(void)
 	u32 lcrr;
 
 	u32 csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
@@ -132,7 +133,8 @@ int get_clocks(void)
 	u32 qe_clk;
 	u32 brg_clk;
 #endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
 #endif
@@ -164,7 +166,8 @@ int get_clocks(void)
 
 	sccr = im->clk.sccr;
 
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
 		tsec1_clk = 0;
@@ -202,7 +205,8 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
@@ -319,7 +323,7 @@ int get_clocks(void)
 	i2c1_clk = csb_clk;
 #elif defined(CONFIG_MPC832x)
 	i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC831x)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
 	i2c1_clk = enc_clk;
 #elif defined(CONFIG_FSL_ESDHC)
 	i2c1_clk = sdhc_clk;
@@ -328,7 +332,8 @@ int get_clocks(void)
 	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
 #endif
 
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
 	case 0:
 		pciexp1_clk = 0;
@@ -444,7 +449,8 @@ int get_clocks(void)
 #endif
 
 	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
 	gd->usbdr_clk = usbdr_clk;
@@ -525,7 +531,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_FSL_ESDHC)
 	printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
 #endif
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
 	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
 	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index d3dd44e..c854ce9 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -60,7 +60,8 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC83xx)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
@@ -76,7 +77,8 @@ typedef	struct	global_data {
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 pci_clk;
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
 #endif
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 6b42a73..3a9cdc4 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -73,7 +73,11 @@ typedef struct sysconf83xx {
 	u32 obir;		/* Output Buffer Impedance Register */
 	u8 res8[0xC];
 	u32 pecr1;		/* PCI Express control register 1 */
+#ifdef CONFIG_MPC8308
+	u32 sdhccr;		/* eSDHC Control Registers for MPC8308 */
+#else
 	u32 pecr2;		/* PCI Express control register 2 */
+#endif
 	u8 res9[0xB8];
 } sysconf83xx_t;
 
@@ -589,7 +593,14 @@ typedef struct sdhc83xx {
  * SerDes
  */
 typedef struct serdes83xx {
-	u8 fixme[0x100];
+	u32 srdscr0;
+	u32 srdscr1;
+	u32 srdscr2;
+	u32 srdscr3;
+	u32 srdscr4;
+	u8 res0[0xc];
+	u32 srdsrstctl;
+	u8 res1[0xdc];
 } serdes83xx_t;
 
 /*
@@ -691,7 +702,7 @@ typedef struct immap {
 	u8			res7[0xC0000];
 } immap_t;
 
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 41737d3..b0082af 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -27,9 +27,10 @@
 
 #include <asm/types.h>
 
-#if defined(CONFIG_MPC834x) || \
+#if defined(CONFIG_MPC8308) || \
 	defined(CONFIG_MPC8313) || \
 	defined(CONFIG_MPC8315) || \
+	defined(CONFIG_MPC834x) || \
 	defined(CONFIG_MPC837x)
 
 typedef struct spi8xxx {
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 5214911..ba6cdf1 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -65,6 +65,7 @@
 #define PARTID_NO_E(spridr)		((spridr & 0xFFFE0000) >> 16)
 #define SPR_FAMILY(spridr)		((spridr & 0xFFF00000) >> 20)
 
+#define SPR_8308			0x8100
 #define SPR_831X_FAMILY			0x80B
 #define SPR_8311			0x80B2
 #define SPR_8313			0x80B0
@@ -115,8 +116,9 @@
 #define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
 #define SPCR_TSEC2EP_SHIFT		(31-31)
 
-#elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
-/* SPCR bits - MPC831x and MPC837x specific */
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
+/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
 #define SPCR_TSECDP			0x00003000	/* TSEC data priority */
 #define SPCR_TSECDP_SHIFT		(31-19)
 #define SPCR_TSECBDP			0x00000C00	/* TSEC buffer descriptor priority */
@@ -473,7 +475,7 @@
 #define HRCWL_CE_TO_PLL_1X30		0x0000001E
 #define HRCWL_CE_TO_PLL_1X31		0x0000001F
 
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
 #define HRCWL_SVCOD			0x30000000
 #define HRCWL_SVCOD_SHIFT		28
 #define HRCWL_SVCOD_DIV_2		0x00000000
@@ -541,7 +543,8 @@
 #define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
 #define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
 
-#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 #define HRCWH_ROM_LOC_NAND_SP_8BIT	0x00100000
 #define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
 #define HRCWH_ROM_LOC_NAND_LP_8BIT	0x00500000
@@ -592,7 +595,8 @@
 
 /* RSR - Reset Status Register
  */
-#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 #define RSR_RSTSRC			0xF0000000	/* Reset source */
 #define RSR_RSTSRC_SHIFT		28
 #else
@@ -734,8 +738,8 @@
 #define SCCR_USBDRCM_2			0x00200000
 #define SCCR_USBDRCM_3			0x00300000
 
-#elif defined(CONFIG_MPC8315)
-/* SCCR bits - MPC8315 specific */
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+/* SCCR bits - MPC8315/MPC8308 specific */
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
 #define SCCR_TSEC1CM_0			0x00000000
@@ -750,6 +754,13 @@
 #define SCCR_TSEC2CM_2			0x20000000
 #define SCCR_TSEC2CM_3			0x30000000
 
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
 #define SCCR_USBDRCM			0x00c00000
 #define SCCR_USBDRCM_SHIFT		22
 #define SCCR_USBDRCM_0			0x00000000
-- 
1.6.2.5

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

This patch provides support for MPC8308ERDB development board from
Freescale with a minimal set of features:
 Dual UART is supported
 NOR flash is supported
 Both TSEC Ethernet controllers are supported
 PCI Express initialization is supported

The following features are enabled in configuration but not fully tested:
 I2C (used to get the board revision)
 I2C-connected RTC
 VSC7385 switch

There is one (hopefully) minor issue: on soft reset the board sometimes
resets twice. I've not managed to find the fix for this problem yet.
As a workaround instruction cache can be disabled.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
 MAINTAINERS                               |    4 +
 MAKEALL                                   |    1 +
 board/freescale/mpc8308erdb/Makefile      |   52 +++
 board/freescale/mpc8308erdb/config.mk     |    1 +
 board/freescale/mpc8308erdb/mpc8308erdb.c |  160 ++++++++
 board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
 boards.cfg                                |    1 +
 include/configs/MPC8308ERDB.h             |  577 +++++++++++++++++++++++++++++
 8 files changed, 922 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/mpc8308erdb/Makefile
 create mode 100644 board/freescale/mpc8308erdb/config.mk
 create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
 create mode 100644 board/freescale/mpc8308erdb/sdram.c
 create mode 100644 include/configs/MPC8308ERDB.h

diff --git a/MAINTAINERS b/MAINTAINERS
index d7aec98..5a6c164 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -489,6 +489,10 @@ Stephen Williams <steve@icarus.com>
 
 	JSE		PPC405GPr
 
+Ilya Yanok <yanok@emcraft.com>
+
+	MPC8308ERDB	MPC8308
+
 Roy Zang <tie-fei.zang@freescale.com>
 
 	mpc7448hpc2	MPC7448
diff --git a/MAKEALL b/MAKEALL
index d6d5f5b..04653b7 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -359,6 +359,7 @@ LIST_8260="		\
 LIST_83xx="		\
 	caddy2		\
 	kmeter1		\
+	MPC8308ERDB	\
 	MPC8313ERDB_33	\
 	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
diff --git a/board/freescale/mpc8308erdb/Makefile b/board/freescale/mpc8308erdb/Makefile
new file mode 100644
index 0000000..e9bfa2b
--- /dev/null
+++ b/board/freescale/mpc8308erdb/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8308erdb/config.mk b/board/freescale/mpc8308erdb/config.mk
new file mode 100644
index 0000000..f768264
--- /dev/null
+++ b/board/freescale/mpc8308erdb/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xFE000000
diff --git a/board/freescale/mpc8308erdb/mpc8308erdb.c b/board/freescale/mpc8308erdb/mpc8308erdb.c
new file mode 100644
index 0000000..673d3d6
--- /dev/null
+++ b/board/freescale/mpc8308erdb/mpc8308erdb.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;
+
+	return 0;
+}
+
+static u8 read_board_info(void)
+{
+	u8 val8;
+	i2c_set_bus_num(0);
+
+	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+		return val8;
+	else
+		return 0;
+}
+
+int checkboard(void)
+{
+	static const char * const rev_str[] = {
+		"1.0",
+		"<reserved>",
+		"<reserved>",
+		"<reserved>",
+		"<unknown>",
+	};
+	u8 info;
+	int i;
+
+	info = read_board_info();
+	i = (!info) ? 4 : info & 0x03;
+
+	printf("Board: Freescale MPC8308ERDB Rev %s\n", rev_str[i]);
+
+	return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	clk83xx_t *clk = (clk83xx_t *)&immr->clk;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
+				    SCCR_PCIEXP1CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg, 0);
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		return 1;
+	}
+#endif
+
+	return 0;
+}
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	if ((rv = cpu_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize TSECs.\n");
+
+	if ((rv = pci_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
diff --git a/board/freescale/mpc8308erdb/sdram.c b/board/freescale/mpc8308erdb/sdram.c
new file mode 100644
index 0000000..939c1b8
--- /dev/null
+++ b/board/freescale/mpc8308erdb/sdram.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ * Authors: Nick.Spence at freescale.com
+ *          Wilson.Lo at freescale.com
+ *          scottwood at freescale.com
+ *
+ * This files is  mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void resume_from_sleep(void)
+{
+	u32 magic = *(u32 *)0;
+
+	typedef void (*func_t)(void);
+	func_t resume = *(func_t *)4;
+
+	if (magic == 0xf5153ae5)
+		resume();
+
+	gd->flags &= ~GD_FLG_SILENT;
+	puts("\nResume from sleep failed: bad magic word\n");
+}
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
+		out_be32(&im->ddr.sdram_cfg,
+			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
+	} else {
+		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	}
+
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
diff --git a/boards.cfg b/boards.cfg
index 1a5cfb1..5f2c270 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -132,6 +132,7 @@ ZPC1900		powerpc	mpc8260		zpc1900
 mgcoge		powerpc	mpc8260		-		keymile
 SCM		powerpc	mpc8260		-		siemens
 TQM8272		powerpc	mpc8260		tqm8272		tqc
+MPC8308ERDB	powerpc	mpc83xx		mpc8308erdb	freescale
 kmeter1		powerpc	mpc83xx		kmeter1		keymile
 MVBLM7		powerpc	mpc83xx		mvblm7		matrix_vision
 TQM834x		powerpc	mpc83xx		tqm834x		tqc
diff --git a/include/configs/MPC8308ERDB.h b/include/configs/MPC8308ERDB.h
new file mode 100644
index 0000000..7c143ae
--- /dev/null
+++ b/include/configs/MPC8308ERDB.h
@@ -0,0 +1,577 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
+#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
+#define CONFIG_MPC8308ERDB	1 /* MPC8308ERDB board specific */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is SoC TSEC
+ * TSEC2 is VSC switch
+ */
+#define CONFIG_TSEC1
+#define CONFIG_VSC7385_ENET
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH	0x01801003
+#define CONFIG_SYS_SICRL	0x00000040 /* 3.3V, no delay */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| 0x00010000  /* ODT_WR to CSn */ \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE)
+				/* 0x43080000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END		0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */
+
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
+
+#define CONFIG_SYS_BR0_PRELIM	(\
+		CONFIG_SYS_FLASH_BASE	/* Flash Base address */	|\
+		(2 << BR_PS_SHIFT)	/* 16 bit port size */		|\
+		BR_V)			/* valid */
+#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_BR2_PRELIM		0xf0000801 /* VSC7385 Base address */
+#define CONFIG_SYS_OR2_PRELIM		0xfffe09ff /* VSC7385, 128K bytes*/
+/* Access window base@VSC7385 base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
+/* Access window size 128K */
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED	400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0x51}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
+
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#define CONFIG_PCI
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
+					BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+					BATL_CACHEINHIBIT | \
+					BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+					BATL_CACHEINHIBIT | \
+					BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L	0
+#define CONFIG_SYS_IBAT7U	0
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"kernel_addr=FE080000\0"					\
+	"fdt_addr=FE280000\0"						\
+	"ramdisk_addr=FE290000\0"					\
+	"u-boot=mpc8308rdb/u-boot.bin\0"				\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr_r=C00000\0"						\
+	"hostname=mpc8308rdb\0"						\
+	"bootfile=mpc8308rdb/uImage\0"					\
+	"fdtfile=mpc8308rdb/mpc8308erdb.dtb\0"				\
+	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
+		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};cp.b ${fileaddr} "			\
+		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
+	"upd=run load update\0"						\
+
+#endif	/* __CONFIG_H */
-- 
1.6.2.5

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Kim Phillips]

On Mon, 28 Jun 2010 16:45:29 +0400
Ilya Yanok <yanok@emcraft.com> wrote:

> This patch provides support for MPC8308ERDB development board from

so, according to this document:

http://cache.freescale.com/files/32bit/doc/user_guide/MPC8308RDBUG.pdf

the board name is just 'mpc8308rdb', not 'mpc8308erdb'.  AFAICT, there
is no version of the 8308 that has an 'E'ncryption unit, so the name
should probably be changed.

apologies for not seeing this earlier...

Kim

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

Hi Kim,

On 01.07.2010 04:30, Kim Phillips wrote:
>> This patch provides support for MPC8308ERDB development board from
>>      
> so, according to this document:
>
> http://cache.freescale.com/files/32bit/doc/user_guide/MPC8308RDBUG.pdf
>
> the board name is just 'mpc8308rdb', not 'mpc8308erdb'.  AFAICT, there
> is no version of the 8308 that has an 'E'ncryption unit, so the name
> should probably be changed.
>
> apologies for not seeing this earlier...
>    

Well, actually I saw this myself... but the board is named MPC8308ERDB 
in Freescale BSP so I didn't change this name.
Ok, I'll fix this and repost the patch.

Regards, Ilya.

[U-Boot] [PATCH 2/2] MPC8308RDB: minimal support for devboard from Freescale

[Ilya Yanok]

This patch provides support for MPC8308RDB development board from
Freescale with a minimal set of features:
 Dual UART is supported
 NOR flash is supported
 Both TSEC Ethernet controllers are supported
 PCI Express initialization is supported

The following features are enabled in configuration but not fully tested:
 I2C (used to get the board revision)
 I2C-connected RTC
 VSC7385 switch

There is one (hopefully) minor issue: on soft reset the board sometimes
resets twice. I've not managed to find the fix for this problem yet.
As a workaround instruction cache can be disabled.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
 MAINTAINERS                             |    4 +
 MAKEALL                                 |    1 +
 board/freescale/mpc8308rdb/Makefile     |   52 +++
 board/freescale/mpc8308rdb/config.mk    |    1 +
 board/freescale/mpc8308rdb/mpc8308rdb.c |  160 +++++++++
 board/freescale/mpc8308rdb/sdram.c      |  126 +++++++
 boards.cfg                              |    1 +
 include/configs/MPC8308RDB.h            |  560 +++++++++++++++++++++++++++++++
 8 files changed, 905 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/mpc8308rdb/Makefile
 create mode 100644 board/freescale/mpc8308rdb/config.mk
 create mode 100644 board/freescale/mpc8308rdb/mpc8308rdb.c
 create mode 100644 board/freescale/mpc8308rdb/sdram.c
 create mode 100644 include/configs/MPC8308RDB.h

diff --git a/MAINTAINERS b/MAINTAINERS
index d7aec98..02a7479 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -489,6 +489,10 @@ Stephen Williams <steve@icarus.com>
 
 	JSE		PPC405GPr
 
+Ilya Yanok <yanok@emcraft.com>
+
+	MPC8308RDB	MPC8308
+
 Roy Zang <tie-fei.zang@freescale.com>
 
 	mpc7448hpc2	MPC7448
diff --git a/MAKEALL b/MAKEALL
index d6d5f5b..5f967e9 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -359,6 +359,7 @@ LIST_8260="		\
 LIST_83xx="		\
 	caddy2		\
 	kmeter1		\
+	MPC8308RDB	\
 	MPC8313ERDB_33	\
 	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile
new file mode 100644
index 0000000..e9bfa2b
--- /dev/null
+++ b/board/freescale/mpc8308rdb/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8308rdb/config.mk b/board/freescale/mpc8308rdb/config.mk
new file mode 100644
index 0000000..f768264
--- /dev/null
+++ b/board/freescale/mpc8308rdb/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xFE000000
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
new file mode 100644
index 0000000..a864189
--- /dev/null
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;
+
+	return 0;
+}
+
+static u8 read_board_info(void)
+{
+	u8 val8;
+	i2c_set_bus_num(0);
+
+	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+		return val8;
+	else
+		return 0;
+}
+
+int checkboard(void)
+{
+	static const char * const rev_str[] = {
+		"1.0",
+		"<reserved>",
+		"<reserved>",
+		"<reserved>",
+		"<unknown>",
+	};
+	u8 info;
+	int i;
+
+	info = read_board_info();
+	i = (!info) ? 4 : info & 0x03;
+
+	printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
+
+	return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	clk83xx_t *clk = (clk83xx_t *)&immr->clk;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
+				    SCCR_PCIEXP1CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg, 0);
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		return 1;
+	}
+#endif
+
+	return 0;
+}
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	if ((rv = cpu_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize TSECs.\n");
+
+	if ((rv = pci_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
new file mode 100644
index 0000000..939c1b8
--- /dev/null
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ * Authors: Nick.Spence at freescale.com
+ *          Wilson.Lo at freescale.com
+ *          scottwood at freescale.com
+ *
+ * This files is  mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void resume_from_sleep(void)
+{
+	u32 magic = *(u32 *)0;
+
+	typedef void (*func_t)(void);
+	func_t resume = *(func_t *)4;
+
+	if (magic == 0xf5153ae5)
+		resume();
+
+	gd->flags &= ~GD_FLG_SILENT;
+	puts("\nResume from sleep failed: bad magic word\n");
+}
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
+		out_be32(&im->ddr.sdram_cfg,
+			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
+	} else {
+		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	}
+
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
diff --git a/boards.cfg b/boards.cfg
index 1a5cfb1..169393f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -132,6 +132,7 @@ ZPC1900		powerpc	mpc8260		zpc1900
 mgcoge		powerpc	mpc8260		-		keymile
 SCM		powerpc	mpc8260		-		siemens
 TQM8272		powerpc	mpc8260		tqm8272		tqc
+MPC8308RDB	powerpc	mpc83xx		mpc8308rdb	freescale
 kmeter1		powerpc	mpc83xx		kmeter1		keymile
 MVBLM7		powerpc	mpc83xx		mvblm7		matrix_vision
 TQM834x		powerpc	mpc83xx		tqm834x		tqc
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
new file mode 100644
index 0000000..6cd5da7
--- /dev/null
+++ b/include/configs/MPC8308RDB.h
@@ -0,0 +1,560 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
+#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
+#define CONFIG_MPC8308RDB	1 /* MPC8308RDB board specific */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is SoC TSEC
+ * TSEC2 is VSC switch
+ */
+#define CONFIG_TSEC1
+#define CONFIG_VSC7385_ENET
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH	0x01b7d103
+#define CONFIG_SYS_SICRL	0x00000040 /* 3.3V, no delay */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| 0x00010000  /* ODT_WR to CSn */ \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE)
+				/* 0x43080000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END		0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */
+
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
+
+#define CONFIG_SYS_BR0_PRELIM	(\
+		CONFIG_SYS_FLASH_BASE	/* Flash Base address */	|\
+		(2 << BR_PS_SHIFT)	/* 16 bit port size */		|\
+		BR_V)			/* valid */
+#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_SYS_NAND_BASE		0xE0600000	/* 0xE0600000 */
+#define CONFIG_SYS_BR1_PRELIM	( CONFIG_SYS_NAND_BASE \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8 bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V )		/* valid */
+#define CONFIG_SYS_OR1_PRELIM	( 0xFFFF8000		/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR )
+				/* 0xFFFF8396 */
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_BR2_PRELIM		0xf0000801 /* VSC7385 Base address */
+#define CONFIG_SYS_OR2_PRELIM		0xfffe09ff /* VSC7385, 128K bytes*/
+/* Access window base@VSC7385 base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
+/* Access window size 128K */
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED	400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0x51}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
+
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+/*
+ * Fake PCIE2 definitions: there is no PCIE2 on this board but the code
+ * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this
+ */
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#define CONFIG_PCI
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
+					BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+					BATL_CACHEINHIBIT | \
+					BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"kernel_addr=FE080000\0"					\
+	"fdt_addr=FE280000\0"						\
+	"ramdisk_addr=FE290000\0"					\
+	"u-boot=mpc8308rdb/u-boot.bin\0"				\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr_r=C00000\0"						\
+	"hostname=mpc8308rdb\0"						\
+	"bootfile=mpc8308rdb/uImage\0"					\
+	"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"				\
+	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
+		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};cp.b ${fileaddr} "			\
+		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
+	"upd=run load update\0"						\
+
+#endif	/* __CONFIG_H */
-- 
1.6.2.5

[U-Boot] [PATCH 1/2] mpc8308: support for Freescale MPC8308 cpu

[Kim Phillips]

On Mon, 28 Jun 2010 16:44:33 +0400
Ilya Yanok <yanok@emcraft.com> wrote:

> This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
> NOR flash and integrated Ethernet controllers are supported.
> PCI Express is also supported. eSDHC, NAND and USB may work but aren't
> tested (using ULPI PHY requires additional patch).
> 
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---

Applied.

Thanks,

Kim

[U-Boot] [PATCH 2/2] MPC8308RDB: minimal support for devboard from Freescale

[Kim Phillips]

On Wed, 7 Jul 2010 20:16:13 +0400
Ilya Yanok <yanok@emcraft.com> wrote:

> This patch provides support for MPC8308RDB development board from
> Freescale with a minimal set of features:
>  Dual UART is supported
>  NOR flash is supported
>  Both TSEC Ethernet controllers are supported
>  PCI Express initialization is supported
> 
> The following features are enabled in configuration but not fully tested:
>  I2C (used to get the board revision)
>  I2C-connected RTC
>  VSC7385 switch
> 
> There is one (hopefully) minor issue: on soft reset the board sometimes
> resets twice. I've not managed to find the fix for this problem yet.
> As a workaround instruction cache can be disabled.
> 
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---

Applied, after relocating the boards.cfg entry to maintain the correct
sort order.

Thanks,

Kim

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Kim Phillips]

On Thu, 24 Jun 2010 19:00:54 -0500
Kim Phillips <kim.phillips@freescale.com> wrote:

> On Thu, 24 Jun 2010 23:36:49 +0400
> Ilya Yanok <yanok@emcraft.com> wrote:
> 
> > Hi Kim,
> > 
> > On 24.06.2010 22:00, Kim Phillips wrote:
> > >> I've enabled icache and now the board sometimes resets twice after
> > >> U-Boot 'reset' command:
> > >>      
> > >    
> > >> (It doesn't always stop at "DRAM:" line but that position is most frequent)
> > >> Maybe you have some ideas on this subject?
> > >>      
> > > hmm, if it's only on soft-resets, can you try adding
> > > HID0_ENABLE_INSTRUCTION_CACHE to CONFIG_SYS_HID0_INIT in addition to
> > > _FINAL?  Some cache state is preserved over a soft-reset...
> > >    
> > 
> > Thanks for your advice but this doesn't help...

turning icache on early causes a different pattern of bus accesses when
fetching code, and this might trigger bus accesses that interfere with
code that sets bus configuration registers, such as the acr.  Can you
test this patch please?:

diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 15e2c18..613625d 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -36,6 +36,7 @@ COBJS-y += speed.o
 COBJS-y += interrupts.o
 COBJS-y += spd_sdram.o
 COBJS-y += ecc.o
+COBJS-y += acr.o
 COBJS-$(CONFIG_QE) += qe_io.o
 COBJS-$(CONFIG_FSL_SERDES) += serdes.o
 COBJS-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/cpu/mpc83xx/acr.c b/arch/powerpc/cpu/mpc83xx/acr.c
new file mode 100644
index 0000000..20315fc
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/acr.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void single_cline_write(volatile void *addr, __be32 val)
+{
+	out_be32(addr, val);
+}
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 83cba93..237fa48 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -30,6 +30,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+extern void single_cline_write(volatile void *addr, __be32 val);
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -63,6 +65,7 @@ static void config_qe_ioports(void)
  */
 void cpu_init_f (volatile immap_t * im)
 {
+	__be32 val;
 	__be32 acr_mask =
 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
 		ACR_PIPE_DEP |
@@ -213,7 +216,8 @@ void cpu_init_f (volatile immap_t * im)
 	memset ((void *) gd, 0, sizeof (gd_t));
 
 	/* system performance tweaking */
-	clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
+	val = __raw_readl(&im->arbiter.acr);
+	single_cline_write(&im->arbiter.acr, acr_val & (val & ~acr_mask));
 
 	clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 
diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds
index 0b74a13..f01c462 100644
--- a/arch/powerpc/cpu/mpc83xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds
@@ -51,6 +51,8 @@ SECTIONS
   .text      :
   {
     arch/powerpc/cpu/mpc83xx/start.o	(.text)
+    . = ALIGN(32);
+    arch/powerpc/cpu/mpc83xx/acr.o 	(.text)
     *(.text)
     *(.got1)
     . = ALIGN(16);

Thanks,

Kim

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Wolfgang Denk]

Dear Kim Phillips,

In message <20100719193356.a02add7e.kim.phillips@freescale.com> you wrote:
>
> +++ b/arch/powerpc/cpu/mpc83xx/acr.c
> @@ -0,0 +1,29 @@
> +/*
> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +
> +void single_cline_write(volatile void *addr, __be32 val)
> +{
> +	out_be32(addr, val);
> +}

Oops?? Why do we need a new file, with a new function, does nothing
else but calling another funtion, and that gets used just a single
time?

Drop this wrapper!

> +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
> @@ -30,6 +30,8 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +extern void single_cline_write(volatile void *addr, __be32 val);

[Prototypes should always go to appropriate header files!!]

>  void cpu_init_f (volatile immap_t * im)
>  {
> +	__be32 val;
>  	__be32 acr_mask =
>  #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
>  		ACR_PIPE_DEP |
> @@ -213,7 +216,8 @@ void cpu_init_f (volatile immap_t * im)
>  	memset ((void *) gd, 0, sizeof (gd_t));
>  
>  	/* system performance tweaking */
> -	clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
> +	val = __raw_readl(&im->arbiter.acr);

Do we need __raw_readl()? Why would in_be32() not work?

> +	single_cline_write(&im->arbiter.acr, acr_val & (val & ~acr_mask));

Make this:

	out_be32(&im->arbiter.acr, acr_val & (val & ~acr_mask));


> +    . = ALIGN(32);
> +    arch/powerpc/cpu/mpc83xx/acr.o 	(.text)

Ah! I guess this is worth a comment?  But should we not rather aligh
the in_* and out_* functions then?

What is the exact use case when such alignment might be needed?  Can
you guarantee that it's only with this specific register access, and
only for write accesses?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
... bacteriological warfare ... hard to believe we were once foolish
enough to play around with that.
	-- McCoy, "The Omega Glory", stardate unknown

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

[Ilya Yanok]

  Hi Kim,

20.07.2010 4:33, Kim Phillips wrote:
>>> Thanks for your advice but this doesn't help...
> turning icache on early causes a different pattern of bus accesses when
> fetching code, and this might trigger bus accesses that interfere with
> code that sets bus configuration registers, such as the acr.  Can you
> test this patch please?:

Unfortunately this patch doesn't help too...

Thanks for your efforts!

Regards, Ilya.

[U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale (ICache issue)

[Ilya Yanok]

  Hi Kim,

20.07.2010 4:33, Kim Phillips wrote:
> turning icache on early causes a different pattern of bus accesses when
> fetching code, and this might trigger bus accesses that interfere with
> code that sets bus configuration registers, such as the acr.  Can you
> test this patch please?:

This issue turned to be BDI related (I can't reproduce it with BDI 
detached).

Sorry for inconvenience.

Regards, Ilya.