* [U-Boot] [RFC] Board support patches for the eXMeritus HWW-1U-1A devices
@ 2010-08-30 18:24 Kyle Moffett
2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 1/3] DDR2: Support new JEDEC DDR2 SPD 1.3 spec Kyle Moffett
` (2 more replies)
0 siblings, 3 replies; 19+ messages in thread
From: Kyle Moffett @ 2010-08-30 18:24 UTC (permalink / raw)
To: u-boot
Hello all!
I posted this patch series a few weeks back on the u-boot mailing list and
never got any responses, so I'm resubmitting it again with a couple more
folks on the CC list.
This is my first U-Boot submission, so my apologies if there are any coding
style or conventions issues. Please let me know and I'll get them fixed up
quickly.
In addition, these patches were initially based on v2010.03 and I realize
that upstream may have diverged a bit since then. Please let me know what
GIT tree I should rebase these patches on for future submissions.
The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis with 3
independent TEMPEST zones. Two independent P2020 computers may be found
inside each zone. Complete hardware support is included.
There are a couple preliminary patches to common code, but basically
everything else is limited to our own board-support code.
A GIT tree containing these patches may be found here:
git://opensource.exmeritus.com/hww-1u-1a/u-boot.git master
http://opensource.exmeritus.com/git/hww-1u-1a/u-boot.git/master
I look forward to your comments and criticisms.
Cheers,
Kyle Moffett
--
Overall diffstat below:
MAKEALL | 2 +
Makefile | 4 +
board/exmeritus/hww-1u-1a/Makefile | 54 +++
board/exmeritus/hww-1u-1a/config.mk | 31 ++
board/exmeritus/hww-1u-1a/ddr.c | 136 +++++++
board/exmeritus/hww-1u-1a/gpios.h | 131 ++++++
board/exmeritus/hww-1u-1a/hww-1u-1a.c | 697 +++++++++++++++++++++++++++++++++
board/exmeritus/hww-1u-1a/law.c | 40 ++
board/exmeritus/hww-1u-1a/tlb.c | 93 +++++
common/ddr_spd.c | 4 +-
cpu/mpc85xx/cpu.c | 7 +-
cpu/mpc8xxx/ddr/ddr2_dimm_params.c | 30 +-
drivers/net/e1000.c | 7 +
include/configs/HWW_1U_1A.h | 478 ++++++++++++++++++++++
14 files changed, 1702 insertions(+), 12 deletions(-)
^ permalink raw reply [flat|nested] 19+ messages in thread* [U-Boot] [RFC][PATCH 1/3] DDR2: Support new JEDEC DDR2 SPD 1.3 spec 2010-08-30 18:24 [U-Boot] [RFC] Board support patches for the eXMeritus HWW-1U-1A devices Kyle Moffett @ 2010-08-30 18:24 ` Kyle Moffett 2010-09-03 3:06 ` Peter Tyser 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 2/3] e1000: Intel 82571EB: Don't wait for MNG cycle on unmanaged chips Kyle Moffett 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices Kyle Moffett 2 siblings, 1 reply; 19+ messages in thread From: Kyle Moffett @ 2010-08-30 18:24 UTC (permalink / raw) To: u-boot The new DDR2 SPD spec is backwards-compatible with the old one, but there are DIMMs which are being produced which have new SPD version fields that fail to work with U-boot. To make the code a bit more readable, we add some human-readable SPD_DIMM_TYPE_* constants. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> --- common/ddr_spd.c | 4 ++-- cpu/mpc8xxx/ddr/ddr2_dimm_params.c | 30 ++++++++++++++++++++++-------- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/common/ddr_spd.c b/common/ddr_spd.c index c058e4f..f7a482e 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -18,9 +18,9 @@ spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum) /* * Check SPD revision supported - * Rev 1.2 or less supported by this code + * Rev 1.3 or less supported by this code */ - if (spd_rev > 0x12) { + if (spd_rev > 0x13) { printf("SPD revision %02X not supported by this code\n", spd_rev); return 1; diff --git a/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/cpu/mpc8xxx/ddr/ddr2_dimm_params.c index d9d0fa7..2d40a60 100644 --- a/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ b/cpu/mpc8xxx/ddr/ddr2_dimm_params.c @@ -9,6 +9,17 @@ #include <common.h> #include <asm/fsl_ddr_sdram.h> +/* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ +#define SPD_DIMM_TYPE_UNDEFINED 0x00 +#define SPD_DIMM_TYPE_RDIMM 0x01 +#define SPD_DIMM_TYPE_UDIMM 0x02 +#define SPD_DIMM_TYPE_SO_DIMM 0x04 +#define SPD_DIMM_TYPE_72B_SO_CDIMM 0x06 +#define SPD_DIMM_TYPE_72B_SO_RDIMM 0x07 +#define SPD_DIMM_TYPE_MICRO_DIMM 0x08 +#define SPD_DIMM_TYPE_MINI_RDIMM 0x10 +#define SPD_DIMM_TYPE_MINI_UDIMM 0x20 + #include "ddr.h" /* * Calculate the Density of each Physical Rank. @@ -250,20 +261,23 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, pdimm->primary_sdram_width = spd->primw; pdimm->ec_sdram_width = spd->ecw; - /* FIXME: what about registered SO-DIMM? */ + /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ switch (spd->dimm_type) { - case 0x01: /* RDIMM */ - case 0x10: /* Mini-RDIMM */ - pdimm->registered_dimm = 1; /* register buffered */ + case SPD_DIMM_TYPE_RDIMM: + case SPD_DIMM_TYPE_72B_SO_RDIMM: + case SPD_DIMM_TYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; break; - case 0x02: /* UDIMM */ - case 0x04: /* SO-DIMM */ - case 0x08: /* Micro-DIMM */ - case 0x20: /* Mini-UDIMM */ + case SPD_DIMM_TYPE_UDIMM: + case SPD_DIMM_TYPE_SO_DIMM: + case SPD_DIMM_TYPE_MICRO_DIMM: + case SPD_DIMM_TYPE_MINI_UDIMM: pdimm->registered_dimm = 0; /* unbuffered */ break; + case SPD_DIMM_TYPE_72B_SO_CDIMM: default: printf("unknown dimm_type 0x%02X\n", spd->dimm_type); return 1; -- 1.7.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 1/3] DDR2: Support new JEDEC DDR2 SPD 1.3 spec 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 1/3] DDR2: Support new JEDEC DDR2 SPD 1.3 spec Kyle Moffett @ 2010-09-03 3:06 ` Peter Tyser 2010-09-03 5:10 ` Kyle Moffett 0 siblings, 1 reply; 19+ messages in thread From: Peter Tyser @ 2010-09-03 3:06 UTC (permalink / raw) To: u-boot Hi Kyle, <snip> > +/* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ > +#define SPD_DIMM_TYPE_UNDEFINED 0x00 > +#define SPD_DIMM_TYPE_RDIMM 0x01 > +#define SPD_DIMM_TYPE_UDIMM 0x02 > +#define SPD_DIMM_TYPE_SO_DIMM 0x04 > +#define SPD_DIMM_TYPE_72B_SO_CDIMM 0x06 > +#define SPD_DIMM_TYPE_72B_SO_RDIMM 0x07 > +#define SPD_DIMM_TYPE_MICRO_DIMM 0x08 > +#define SPD_DIMM_TYPE_MINI_RDIMM 0x10 > +#define SPD_DIMM_TYPE_MINI_UDIMM 0x20 These aren't 8xxx-specific, so they should go somewhere common. It looks like many of them are already defined in include/ddr_spd.h; I'd recommend adding new types there. Best, Peter ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 1/3] DDR2: Support new JEDEC DDR2 SPD 1.3 spec 2010-09-03 3:06 ` Peter Tyser @ 2010-09-03 5:10 ` Kyle Moffett 0 siblings, 0 replies; 19+ messages in thread From: Kyle Moffett @ 2010-09-03 5:10 UTC (permalink / raw) To: u-boot On Thu, Sep 2, 2010 at 23:06, Peter Tyser <ptyser@xes-inc.com> wrote: >> +/* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ >> +#define SPD_DIMM_TYPE_UNDEFINED ? ? ? ? ? ? ?0x00 >> +#define SPD_DIMM_TYPE_RDIMM ? ? ? ? ?0x01 >> +#define SPD_DIMM_TYPE_UDIMM ? ? ? ? ?0x02 >> +#define SPD_DIMM_TYPE_SO_DIMM ? ? ? ? ? ? ? ?0x04 >> +#define SPD_DIMM_TYPE_72B_SO_CDIMM ? 0x06 >> +#define SPD_DIMM_TYPE_72B_SO_RDIMM ? 0x07 >> +#define SPD_DIMM_TYPE_MICRO_DIMM ? ? 0x08 >> +#define SPD_DIMM_TYPE_MINI_RDIMM ? ? 0x10 >> +#define SPD_DIMM_TYPE_MINI_UDIMM ? ? 0x20 > > These aren't 8xxx-specific, so they should go somewhere common. ?It > looks like many of them are already defined in include/ddr_spd.h; I'd > recommend adding new types there. Ok, I'll respin this using ddr_spd.h! Thanks for the comments! Cheers, Kyle Moffett ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 2/3] e1000: Intel 82571EB: Don't wait for MNG cycle on unmanaged chips 2010-08-30 18:24 [U-Boot] [RFC] Board support patches for the eXMeritus HWW-1U-1A devices Kyle Moffett 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 1/3] DDR2: Support new JEDEC DDR2 SPD 1.3 spec Kyle Moffett @ 2010-08-30 18:24 ` Kyle Moffett 2010-09-13 4:18 ` Ben Warren 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices Kyle Moffett 2 siblings, 1 reply; 19+ messages in thread From: Kyle Moffett @ 2010-08-30 18:24 UTC (permalink / raw) To: u-boot The Intel 82571EB chipset can be used in an unmanaged configuration as a fast dual-port Gig-E controller. Unfortunately a board consturcted that way would fail to correctly come up because the driver polls for the completion of a management cycle that will never occur. To resolve this problem, we disable the poll and error return on chips whose EEPROMS indicate no management. As a protection against misconfigured chipsets, we still delay for the entire management poll timeout. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> --- Jeff Kirsher <jeffrey.t.kirsher@intel.com> has already accepted a similar patch to the Linux kernel into his e1000e patch queue. drivers/net/e1000.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 2825342..c9677b4 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -4266,6 +4266,13 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) /* Fall Through */ case e1000_82571: case e1000_82572: + /* Don't bother polling the management regs if unmanaged */ + if (!e1000_check_mng_mode(hw)) { + DEBUGOUT("Unmanaged chip... skipping MNG polling\n"); + mdelay(timeout); + return 0; + } + while (timeout) { if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) break; -- 1.7.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 2/3] e1000: Intel 82571EB: Don't wait for MNG cycle on unmanaged chips 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 2/3] e1000: Intel 82571EB: Don't wait for MNG cycle on unmanaged chips Kyle Moffett @ 2010-09-13 4:18 ` Ben Warren 2010-09-13 4:24 ` Kyle Moffett 0 siblings, 1 reply; 19+ messages in thread From: Ben Warren @ 2010-09-13 4:18 UTC (permalink / raw) To: u-boot Hi Kyle, On 8/30/2010 11:24 AM, Kyle Moffett wrote: > The Intel 82571EB chipset can be used in an unmanaged configuration as a > fast dual-port Gig-E controller. Unfortunately a board consturcted that > way would fail to correctly come up because the driver polls for the > completion of a management cycle that will never occur. > > To resolve this problem, we disable the poll and error return on chips > whose EEPROMS indicate no management. As a protection against > misconfigured chipsets, we still delay for the entire management poll > timeout. > > Signed-off-by: Kyle Moffett<Kyle.D.Moffett@boeing.com> > --- > Jeff Kirsher<jeffrey.t.kirsher@intel.com> has already accepted a similar > patch to the Linux kernel into his e1000e patch queue. > > drivers/net/e1000.c | 7 +++++++ > 1 files changed, 7 insertions(+), 0 deletions(-) > > diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c > index 2825342..c9677b4 100644 > --- a/drivers/net/e1000.c > +++ b/drivers/net/e1000.c > @@ -4266,6 +4266,13 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) > /* Fall Through */ > case e1000_82571: > case e1000_82572: > + /* Don't bother polling the management regs if unmanaged */ > + if (!e1000_check_mng_mode(hw)) { > + DEBUGOUT("Unmanaged chip... skipping MNG polling\n"); > + mdelay(timeout); > + return 0; > + } > + > while (timeout) { > if (E1000_READ_REG(hw, EEMNGCTL)& cfg_mask) > break; Applied to net/next after fixing typo in prologue (see if you can find it) regards, Ben ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 2/3] e1000: Intel 82571EB: Don't wait for MNG cycle on unmanaged chips 2010-09-13 4:18 ` Ben Warren @ 2010-09-13 4:24 ` Kyle Moffett 2010-09-13 4:28 ` Ben Warren 0 siblings, 1 reply; 19+ messages in thread From: Kyle Moffett @ 2010-09-13 4:24 UTC (permalink / raw) To: u-boot Ben, I am so sorry... please actually drop this patch. I've been in contact with Intel regarding the equivalent patch for the Linux kernel and it turns out this is just a workaround for a misconfiguration in our EEPROMs. The boards on which I have fixed the EEPROMs do not need this change in order to operate correctly. I am also finishing up a group of patches which allow us to more easily program and manage those EEPROMs from U-Boot which I plan to submit some time in the next few days; I will make sure to put you on the CC list for them. Again, my apologies for the trouble! Cheers, Kyle Moffett ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 2/3] e1000: Intel 82571EB: Don't wait for MNG cycle on unmanaged chips 2010-09-13 4:24 ` Kyle Moffett @ 2010-09-13 4:28 ` Ben Warren 0 siblings, 0 replies; 19+ messages in thread From: Ben Warren @ 2010-09-13 4:28 UTC (permalink / raw) To: u-boot On 9/12/2010 9:24 PM, Kyle Moffett wrote: > Ben, > > I am so sorry... please actually drop this patch. I've been in > contact with Intel regarding the equivalent patch for the Linux kernel > and it turns out this is just a workaround for a misconfiguration in > our EEPROMs. The boards on which I have fixed the EEPROMs do not need > this change in order to operate correctly. > > I am also finishing up a group of patches which allow us to more > easily program and manage those EEPROMs from U-Boot which I plan to > submit some time in the next few days; I will make sure to put you on > the CC list for them. > > Again, my apologies for the trouble! > > Cheers, > Kyle Moffett > OK, no worries. regards, Ben ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices 2010-08-30 18:24 [U-Boot] [RFC] Board support patches for the eXMeritus HWW-1U-1A devices Kyle Moffett 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 1/3] DDR2: Support new JEDEC DDR2 SPD 1.3 spec Kyle Moffett 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 2/3] e1000: Intel 82571EB: Don't wait for MNG cycle on unmanaged chips Kyle Moffett @ 2010-08-30 18:24 ` Kyle Moffett 2010-09-03 4:00 ` Peter Tyser 2 siblings, 1 reply; 19+ messages in thread From: Kyle Moffett @ 2010-08-30 18:24 UTC (permalink / raw) To: u-boot The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis with 3 independent TEMPEST zones. Two independent P2020 computers may be found inside each zone. Complete hardware support is included. High-level hardware overview: * DO-160 certified for passenger aircraft (noncritical) * TEMPEST ceritified for RED/BLACK separation * 3 zones per chassis, 2 computers per zone (total of 6) * Dual-core 1.066GHz P2020 per computer * One 2GB DDR2 SO-RDIMM module per computer (upgradable to 4GB) * Removable 80GB or 160GB Intel X18-M SSD per computer * Front-accessible dual-port E1000E per computer * Front-accessible serial console per computer * Front-accessible USB port per computer * Internal Gigabit crossover within each TEMPEST zone * Internal unidirectional fiber links across TEMPEST zones * Battery-backed DS1339 I2C RTC on each CPU. Combined, each 13lb 1U chassis contains 12GB RAM, 12 cores @ 1.066GHz, 12 front-accessible Gigabit Ethernet ports and 960GB of solid-state storage with a total power consumption of ~200W. Additional notes: * SPD detection is only known to work with the DO-160-certified DIMMs * A U-Boot built with 36-bit address-space seems to work, but I don't yet have a usable 36-bit kernel or DTB, so it's mostly untested. * CPU reset is a little quirky due to hardware misfeature, see the extensive comments in the board_reset_r() function in hww-1u-1a.c Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> --- MAKEALL | 2 + Makefile | 4 + board/exmeritus/hww-1u-1a/Makefile | 54 +++ board/exmeritus/hww-1u-1a/config.mk | 31 ++ board/exmeritus/hww-1u-1a/ddr.c | 136 +++++++ board/exmeritus/hww-1u-1a/gpios.h | 131 ++++++ board/exmeritus/hww-1u-1a/hww-1u-1a.c | 697 +++++++++++++++++++++++++++++++++ board/exmeritus/hww-1u-1a/law.c | 40 ++ board/exmeritus/hww-1u-1a/tlb.c | 93 +++++ cpu/mpc85xx/cpu.c | 7 +- include/configs/HWW_1U_1A.h | 478 ++++++++++++++++++++++ 11 files changed, 1671 insertions(+), 2 deletions(-) create mode 100644 board/exmeritus/hww-1u-1a/Makefile create mode 100644 board/exmeritus/hww-1u-1a/config.mk create mode 100644 board/exmeritus/hww-1u-1a/ddr.c create mode 100644 board/exmeritus/hww-1u-1a/gpios.h create mode 100644 board/exmeritus/hww-1u-1a/hww-1u-1a.c create mode 100644 board/exmeritus/hww-1u-1a/law.c create mode 100644 board/exmeritus/hww-1u-1a/tlb.c create mode 100644 include/configs/HWW_1U_1A.h diff --git a/MAKEALL b/MAKEALL index 5c303f9..bd1a3de 100755 --- a/MAKEALL +++ b/MAKEALL @@ -387,6 +387,8 @@ LIST_83xx=" \ LIST_85xx=" \ ATUM8548 \ + HWW_1U_1A \ + HWW_1U_1A_36BIT \ MPC8536DS \ MPC8536DS_NAND \ MPC8536DS_SDCARD \ diff --git a/Makefile b/Makefile index e141cb2..ad14913 100644 --- a/Makefile +++ b/Makefile @@ -2499,6 +2499,10 @@ P2020DS_36BIT_config \ P2020DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale +HWW_1U_1A_36BIT_config \ +HWW_1U_1A_config: unconfig + @$(MKCONFIG) -t $(@:_config=) HWW_1U_1A ppc mpc85xx hww-1u-1a exmeritus + P1011RDB_config \ P1011RDB_NAND_config \ P1011RDB_SDCARD_config \ diff --git a/board/exmeritus/hww-1u-1a/Makefile b/board/exmeritus/hww-1u-1a/Makefile new file mode 100644 index 0000000..caa6a69 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_DDR_SPD) += ddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/exmeritus/hww-1u-1a/config.mk b/board/exmeritus/hww-1u-1a/config.mk new file mode 100644 index 0000000..878b7b3 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/config.mk @@ -0,0 +1,31 @@ +# +# Copyright 2009-2010 eXMeritus, A Boeing Company +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# p2020ds board +# +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/exmeritus/hww-1u-1a/ddr.c b/board/exmeritus/hww-1u-1a/ddr.c new file mode 100644 index 0000000..b587c87 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/ddr.c @@ -0,0 +1,136 @@ +/* + * Copyright 2009-2010 eXMeritus, A Boeing Company + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +} board_specific_parameters_t; + +/* ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ + + +/* XXX: these values need to be checked for all interleaving modes. */ +/* XXX: No reliable dual-rank 800 MHz setting has been found. It may + * seem reliable, but errors will appear when memory intensive + * program is run. */ +/* XXX: Single rank@800 MHz is OK. */ +const board_specific_parameters_t board_specific_parameters[][20] = { + { + /* memory controller 0 */ + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ +#if 0 + { 0, 333, 2, 6, 7, 3, 0}, + {334, 400, 2, 6, 9, 3, 0}, + {401, 549, 2, 6, 11, 3, 0}, + {550, 680, 2, 1, 10, 5, 0}, + {681, 850, 2, 1, 12, 5, 1}, + { 0, 333, 1, 6, 7, 3, 0}, + {334, 400, 1, 6, 9, 3, 0}, + {401, 549, 1, 6, 11, 3, 0}, + {550, 680, 1, 1, 10, 5, 0}, + {681, 850, 1, 1, 12, 5, 0} +#else + { 0,1000, 2, 4, 4, 2, 0}, + { 0,1000, 1, 4, 4, 2, 0}, +#endif + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const board_specific_parameters_t *pbsp = + &(board_specific_parameters[ctrl_num][0]); + u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / + sizeof(board_specific_parameters[0][0]); + u32 i; + ulong ddr_freq; + + /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i&1) { /* odd CS */ + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 0; + } else { /* even CS */ + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 4; + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { + popts->cs_local_opts[i].odt_rd_cfg = 3; + popts->cs_local_opts[i].odt_wr_cfg = 3; + } + } + } + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm->n_ranks == pbsp->n_ranks) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + } + pbsp++; + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/exmeritus/hww-1u-1a/gpios.h b/board/exmeritus/hww-1u-1a/gpios.h new file mode 100644 index 0000000..5b382a3 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/gpios.h @@ -0,0 +1,131 @@ +/* + * Copyright 2010 eXMeritus, A Boeing Company + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */ +#define GPIO_CPU_ID (1UL << (31 - 8)) +#define GPIO_BLUE_LED (1UL << (31 - 9)) +#define GPIO_DIMM_RESET (1UL << (31 - 10)) +#define GPIO_USB_RESET (1UL << (31 - 11)) +#define GPIO_UNUSED_12 (1UL << (31 - 12)) +#define GPIO_GETH0_RESET (1UL << (31 - 13)) +#define GPIO_RS422_RE (1UL << (31 - 14)) +#define GPIO_RS422_DE (1UL << (31 - 15)) +#define IRQ_I2CINT (1UL << (31 - 20)) +#define IRQ_FANINT (1UL << (31 - 21)) +#define IRQ_DIMM_EVENT (1UL << (31 - 22)) + +/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ +#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0)) +#define GPIO_CPUA_CPU_READY (1UL << (31 - 1)) +#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2)) +#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3)) +#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */ +#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */ +#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */ +#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */ +#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16)) +#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17)) +#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18)) +#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19)) + +/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ +#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0)) +#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1)) +#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2)) +#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3)) +#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4)) +#define GPIO_CPUB_CPU_READY (1UL << (31 - 5)) +#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6)) +#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7)) +#define IRQ_CPUB_SD_1A (1UL << (31 - 16)) +#define IRQ_CPUB_SD_2B (1UL << (31 - 17)) +#define IRQ_CPUB_SD_2A (1UL << (31 - 18)) +#define IRQ_CPUB_SD_1B (1UL << (31 - 19)) + +#define GPIOIRQ_CPUB_INIT_DIR /* Output pins */ \ + ( GPIOIRQ_GLBL_INIT_DIR | GPIO_CPUB_CPU_READY \ + | GPIO_CPUB_DEBUG_LED2 | GPIO_CPUB_DEBUG_LED1 \ + | GPIO_CPUB_RMUX_SEL0A | GPIO_CPUB_RMUX_SEL0B \ + | GPIO_CPUB_RMUX_SEL1A | GPIO_CPUB_RMUX_SEL1B ) + +#define GPIOIRQ_CPUB_INIT_VAL /* Pins to drive high */ \ + ( GPIOIRQ_GLBL_INIT_VAL | GPIO_CPUB_CPU_READY \ + | GPIO_CPUB_RMUX_SEL0A | GPIO_CPUB_RMUX_SEL0B ) + +#define GPIOIRQ_CPUB_BOOT_VAL /* Pins to drive high */ \ + ( GPIOIRQ_GLBL_BOOT_VAL | GPIO_CPUB_CPU_READY \ + | GPIO_CPUB_RMUX_SEL0A | GPIO_CPUB_RMUX_SEL0B ) + +static inline void hww1u1a_gpio_set(unsigned int mask, + unsigned int dir, unsigned int val) +{ + volatile ccsr_gpio_t *gpio; + + /* First mask off the unwanted parts of "dir" and "val" */ + dir &= mask; + val &= mask; + + /* Now read in the values we're supposed to preserve */ + gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + dir |= (in_be32(&gpio->gpdir) & ~mask); + val |= (in_be32(&gpio->gpdat) & ~mask); + + /* Now write out the new values, writing the direction first */ + out_be32(&gpio->gpdir, dir); + asm("sync; isync":::"memory"); + out_be32(&gpio->gpdat, val); +} + +static inline void hww1u1a_gpio_set_in(unsigned int gpios) +{ + hww1u1a_gpio_set(gpios, 0x00000000, 0x00000000); +} + +static inline void hww1u1a_gpio_set_low(unsigned int gpios) +{ + hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0x00000000); +} + +static inline void hww1u1a_gpio_set_high(unsigned int gpios) +{ + hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF); +} + +static inline unsigned int hww1u1a_gpio_get(unsigned int mask) +{ + volatile ccsr_gpio_t *gpio; + unsigned int ret; + + /* Read the requested values */ + gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ret = mask & in_be32(&gpio->gpdat); + + return ret; +} + +static inline unsigned int hww1u1a_is_cpu_a(void) +{ + return !hww1u1a_gpio_get(GPIO_CPU_ID); +} + +static inline unsigned int hww1u1a_is_cpu_b(void) +{ + return !!hww1u1a_gpio_get(GPIO_CPU_ID); +} + diff --git a/board/exmeritus/hww-1u-1a/hww-1u-1a.c b/board/exmeritus/hww-1u-1a/hww-1u-1a.c new file mode 100644 index 0000000..9671549 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/hww-1u-1a.c @@ -0,0 +1,697 @@ +/* + * Copyright 2009-2010 eXMeritus, A Boeing Company + * Copyright 2007-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <tsec.h> +#include <asm/fsl_law.h> +#include <asm/mp.h> +#include <netdev.h> +#include <malloc.h> +#include <i2c.h> + +#include "gpios.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t fixed_sdram(void); + +int checkboard(void) +{ + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + + unsigned int gpio_high = 0; + unsigned int gpio_low = 0; + unsigned int gpio_in = 0; + unsigned int i; + + puts("Board: HWW-1U-1A "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif + + /* + * First just figure out which CPU we're on, then use that to + * configure the lists of other GPIOs to be programmed. + */ + hww1u1a_gpio_set_in(GPIO_CPU_ID); + if (hww1u1a_is_cpu_a()) { + puts("CPU A\n"); + + /* We want to turn on some LEDs */ + gpio_high |= GPIO_CPUA_CPU_READY; + gpio_low |= GPIO_CPUA_DEBUG_LED1; + gpio_low |= GPIO_CPUA_DEBUG_LED2; + + /* Disable the unused transmitters */ + gpio_low |= GPIO_CPUA_TDIS1A; + gpio_high |= GPIO_CPUA_TDIS1B; + gpio_low |= GPIO_CPUA_TDIS2A; + gpio_high |= GPIO_CPUA_TDIS2B; + } else { + puts("CPU B\n"); + + /* We want to turn on some LEDs */ + gpio_high |= GPIO_CPUB_CPU_READY; + gpio_low |= GPIO_CPUB_DEBUG_LED1; + gpio_low |= GPIO_CPUB_DEBUG_LED2; + + /* Enable the appropriate receivers */ + gpio_high |= GPIO_CPUB_RMUX_SEL0A; + gpio_high |= GPIO_CPUB_RMUX_SEL0B; + gpio_low |= GPIO_CPUB_RMUX_SEL1A; + gpio_low |= GPIO_CPUB_RMUX_SEL1B; + } + + /* These GPIOs are common */ + gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT; + gpio_low |= GPIO_RS422_RE; + gpio_high |= GPIO_RS422_DE; + + /* Ok, now go ahead and program all of those in one go */ + hww1u1a_gpio_set( gpio_high|gpio_low|gpio_in, + gpio_high|gpio_low, + gpio_high); + + /* + * If things have been taken out of reset early (for example, by one + * of the BDI3000 debuggers), then we need to put them back in reset + * and delay a while before we continue. + */ +#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET) + if (hww1u1a_gpio_get(GPIO_RESETS)) { + puts("Debugger detected... extra device reset enabled!\n"); + + /* Put stuff into reset and disable the DDR controller */ + hww1u1a_gpio_set_low(GPIO_RESETS); + out_be32(&ddr->sdram_cfg, 0x00000000); + + puts(" Waiting 1 sec for reset..."); + for (i = 0; i < 10; i++) { + udelay(100000); + puts("."); + } + puts("\n"); + } + + /* Now bring everything back out of reset again */ + hww1u1a_gpio_set_high(GPIO_RESETS); + return 0; +} + +/* Create a prompt-like string: "uboot at HOSTNAME% " */ +#define PROMPT_PREFIX "uboot@exm" +#define PROMPT_SUFFIX "% " + +/* This function returns a PS1 prompt based on the serial number */ +static char *hww1u1a_prompt = NULL; +const char *hww1u1a_get_ps1(void) +{ + unsigned long len, i, j; + const char *serialnr; + + /* If our prompt was already set, just use that */ + if (hww1u1a_prompt) + return hww1u1a_prompt; + + /* Use our serial number if present, otherwise "UNPROGRAMMED-[AB]" */ + serialnr = getenv("serial#"); + if (!serialnr || !serialnr[0]) { + if (hww1u1a_is_cpu_a()) + serialnr = "999999-XA"; + else + serialnr = "999999-XB"; + } + + /* + * We will turn the serial number into a hostname by: + * (A) Delete all non-alphanumerics. + * (B) Lowercase all letters + * (C) Prefix "exm" + */ + for (i = 0, len = 0; serialnr[i]; i++) { + if ('0' <= serialnr[i] && serialnr[i] <= '9') + len++; + else if ('a' <= serialnr[i] && serialnr[i] <= 'z') + len++; + else if ('A' <= serialnr[i] && serialnr[i] <= 'Z') + len++; + } + + len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX); /* Includes NUL */ + hww1u1a_prompt = malloc(len); + if (!hww1u1a_prompt) + return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX; + + /* Now actually fill it in */ + i = 0; + + /* Handle the prefix */ + for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++) + hww1u1a_prompt[i++] = PROMPT_PREFIX[j]; + + /* Now the serial# part of the hostname */ + for (j = 0; serialnr[j]; j++) { + if ('0' <= serialnr[j] && serialnr[j] <= '9') + hww1u1a_prompt[i++] = serialnr[j]; + else if ('a' <= serialnr[j] && serialnr[j] <= 'z') + hww1u1a_prompt[i++] = serialnr[j]; + else if ('A' <= serialnr[j] && serialnr[j] <= 'Z') + hww1u1a_prompt[i++] = serialnr[j] + 'a' - 'A'; + } + + /* Finally the suffix */ + for (j = 0; j < sizeof(PROMPT_SUFFIX); j++) + hww1u1a_prompt[i++] = PROMPT_SUFFIX[j]; + + /* This should all have added up, but just in case */ + hww1u1a_prompt[len - 1] = '\0'; + + /* Now we're done */ + return hww1u1a_prompt; +} + + +phys_size_t initdram(int board_type) +{ +#ifndef CONFIG_SPD_EEPROM + /* This is manual (non-SPD) DDR2 SDRAM configuration (2GB ECC) */ + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + phys_size_t dram_size = (2048ULL) << 20; + out_be32(&ddr->cs0_bnds, 0x0000003F); + out_be32(&ddr->cs1_bnds, 0x0040007F); + out_be32(&ddr->cs0_config, 0x80014202); + out_be32(&ddr->cs1_config, 0x80014202); + out_be32(&ddr->timing_cfg_0, 0x00330804); + out_be32(&ddr->timing_cfg_1, 0x6f69f643); + out_be32(&ddr->timing_cfg_2, 0x022068cd); + out_be32(&ddr->timing_cfg_3, 0x00030000); + out_be32(&ddr->sdram_cfg_2, 0x04400010); + out_be32(&ddr->sdram_mode, 0x00440452); + out_be32(&ddr->sdram_mode_2, 0x00000000); + out_be32(&ddr->sdram_md_cntl, 0x00000000); + out_be32(&ddr->sdram_interval, 0x0a280110); + out_be32(&ddr->sdram_data_init, 0xDEADBEEF); + out_be32(&ddr->sdram_clk_cntl, 0x02000000); + out_be32(&ddr->timing_cfg_4, 0x00000000); + out_be32(&ddr->timing_cfg_5, 0x00000000); + out_be32(&ddr->ddr_zq_cntl, 0x00000000); + out_be32(&ddr->ddr_wrlvl_cntl, 0x00000000); + out_be32(&ddr->ip_rev1, 0x00020403); + out_be32(&ddr->ip_rev2, 0x00000100); + out_be32(&ddr->err_int_en, 0x0000000D); + out_be32(&ddr->err_disable, 0x00000000); + out_be32(&ddr->err_sbe, 0x00010000); + out_be32(&ddr->ddr_cdr1, 0x00040000); + out_be32(&ddr->ddr_cdr2, 0x00000000); + out_be32(&ddr->sdram_cfg, 0x73000000); + + /* Allow time for the clocks to stabilize before enabling */ + udelay(500); + out_be32(&ddr->sdram_cfg, 0xF3000000); + + /* Now wait until memory is initialized */ + while (in_be32(&ddr->sdram_cfg_2) & 0x00000010) + udelay(1000); + + /* Finally we set up the local access windows */ + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, dram_size, + LAW_TRGT_IF_DDR) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; +#else + /* We also support "Automagic mode" */ + phys_size_t dram_size = fsl_ddr_sdram(); +#endif + + /* Before we're done we need to set up the TLB entries */ + return setup_ddr_tlbs(dram_size >> 20) << 20; +} + +static struct pci_controller pcie1_hose; +static struct pci_controller pcie2_hose; +static struct pci_controller pcie3_hose; +void pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + + debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + printf(" eTSEC2 is in sgmii mode.\n"); + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + printf(" eTSEC3 is in sgmii mode.\n"); + + puts("\n"); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); + } else { + printf(" PCIE1: disabled\n"); + } + + puts("\n"); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf(" PCIE2 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); + } else { + printf(" PCIE2: disabled\n"); + } + + puts("\n"); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); + printf(" PCIE3 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); + } else { + printf(" PCIE3: disabled\n"); + } + puts("\n"); + +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap bootflash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for FLASH */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[4]; + volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + + SET_STD_TSEC_INFO(tsec_info[0], 1); + SET_STD_TSEC_INFO(tsec_info[1], 2); + SET_STD_TSEC_INFO(tsec_info[2], 3); + if (pgpio->gpdat & GPIO_CPU_ID) + tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB; + else + tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA; + + tsec_eth_init(bis, tsec_info, 3); + return pci_eth_init(bis); +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +} + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} + +/* We don't have any really usable POST memory, so just fake it */ +unsigned long post_word_load (void) +{ + return 0l; +} + +void post_word_store (unsigned long val) +{ + return; +} + +/* + * Unfortunately we have a bit of a problem with our reset line wiring on the + * HWW-1U-1A boards. + * + * Specifically the "CPU A" reset controls all of the PCI devices on the + * IO/backplane card, which means ethernet and SATA controllers for both + * CPU A *and* CPU B. + * + * This is somewhat of a problem if the CPUs are reset independently... CPU B + * might fail to come up because his PCI devices are confused, or CPU B might + * die because CPU A just reset the SATA controller for his root filesystem. + * + * Since in practice the CPUs never need to reboot independently we will go + * ahead and require GPIO cross-communication between them before either one + * will reset. + * + * The communication protocol uses GPIOs 4-7 on the PCA9554 GPIO expander + * found on I2C-2 at address 0x3f. CPU A uses 4,5 as TX and 6,7 as RX; for + * CPU B we use the exact opposite. + * + * The GPIOs initialize as inputs during poweron, and are pulled high; the + * PCA9554 expanders will maintain valid outputs over soft-reset allowing for + * reliable operation. + * + * To avoid duplication, we will assign names to the GPIOs: + * ,---------------------------------------. + * | GPIO4 | GPIO5 | GPIO6 | GPIO7 | + * ,---------|=========|=========|=========|=========| + * | CPU A | tx1 | tx2 | rx1 | rx2 | + * |---------|---------|---------|---------|---------| + * | CPU B | rx1 | rx2 | tx1 | tx2 | + * `-------------------------------------------------' + * + * The state machine for each CPU is below. In simplistic terms, each CPU + * waits until the other has cleared its GPIOs, then cause a tx1 high=>low + * transition. Upon seeing the other CPU do the same, it will perform a + * tx2 high=>low transition and again wait. + * + * Once both CPUs have performed and seen both transitions, they will each + * set tx1 high (to create an "invalid" state) and then reset. + * + * ,--------------. + * | START/ERROR: |<==-. + * ,-==>| tx2 = 1; | || (rx2 == 0) + * || | tx1 = 1; | ==-' + * || `--------------' + * || || + * || || (rx2 == 1) + * || \/ + * || ,--------------. + * || | WAITING: |<==-. + * |\== | tx1 = 0; | || (rx1 == 1) && (rx2 == 1) + * || | | ==-' + * || `--------------' + * || || + * || || (rx1 == 0) && (rx2 == 1) + * || \/ + * || ,--------------. + * || | BOTH_READY: |<==-. + * `-== | tx2 = 0; | || (rx1 == 0) && (rx2 == 1) + * | | ==-' + * `--------------' + * || + * || (rx2 == 0) + * \/ + * ,--------------. + * | RESETTING: | + * | tx1 = 1; | + * | reset(); | + * `--------------' + * + * While in the "BOTH_READY" state a high-to-low rx2 transition must be + * followed within 50ms by activation of the HRESET_REQ signal. That + * state MUST NOT be interrupted by any event other than the observed + * event (rx1 == high) && (rx2 == high). + */ + +#define PCA9554_I2C_ADDR 0x3f +static inline int pca9554_read(u8 reg) +{ + u8 value; + int ret; + + i2c_set_bus_num(1); + ret = i2c_read(PCA9554_I2C_ADDR, reg, 1, &value, 1); + if (ret < 0) + return ret; + return value; +} +static inline int pca9554_write(u8 reg, u8 value) +{ + i2c_set_bus_num(1); + return i2c_write(PCA9554_I2C_ADDR, reg, 1, &value, 1); +} +static inline int pca9554_setmask(u8 reg, u8 value, u8 mask) +{ + int ret = pca9554_read(reg); + if (ret < 0) + return ret; + + return pca9554_write(reg, (ret & ~mask) | (value & mask)); +} + +#define PCA9554_DATA_IN 0x00 +#define PCA9554_DATA_OUT 0x01 +#define PCA9554_INVERT 0x02 +#define PCA9554_IS_INPUT 0x03 + +static inline int pca9554_set_low(u8 gpio) +{ + return pca9554_setmask(PCA9554_DATA_OUT, 0x00, (1U << gpio)); +} + +static inline int pca9554_set_high(u8 gpio) +{ + return pca9554_setmask(PCA9554_DATA_OUT, 0xff, (1U << gpio)); +} + +static inline int pca9554_set_output(u8 gpio) +{ + return pca9554_setmask(PCA9554_IS_INPUT, 0x00, (1U << gpio)); +} + +static inline int pca9554_set_input(u8 gpio) +{ + return pca9554_setmask(PCA9554_DATA_OUT, 0xff, (1U << gpio)); +} + +void board_reset_r(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u8 tx1, tx2, rx1, rx2, rxmask; + int ret; + + /* Our state-machine state */ + enum { + START_ERROR = 0, + WAITING, + BOTH_READY, + } state; + + printf("RESET: Preparing..."); + + /* First clear the "INVERT" setting on all relevant GPIOs */ + if (pca9554_setmask(PCA9554_INVERT, 0x00, 0xf0) < 0) + goto err; + + /* Check what CPU we are and configure accordingly. */ + if (hww1u1a_is_cpu_a()) { + tx1 = 4; tx2 = 5; rx1 = 6; rx2 = 7; + } else { + rx1 = 4; rx2 = 5; tx1 = 6; tx2 = 7; + } + rxmask = (1U << rx1) | (1U << rx2); + + /* Configure both inputs */ + if (pca9554_set_input(rx1) < 0) + goto err; + if (pca9554_set_input(rx2) < 0) + goto err; + + /* Make sure the very first thing we do is set the "tx2" GPIO high */ + if (pca9554_set_high(tx2) < 0) + goto err; + if (pca9554_set_output(tx2) < 0) + goto err; + + /* Now reset our other transmit pin */ + if (pca9554_set_high(tx1) < 0) + goto err; + if (pca9554_set_output(tx1) < 0) + goto err; + + /* Enter the state machine */ + state = START_ERROR; + +poll_state: + ret = pca9554_read(PCA9554_DATA_IN); + switch (state) { + case START_ERROR: + if (ctrlc()) + goto intr; + + if (ret < 0) + goto err; + + /* Wait for (rx2 == high) */ + if (ret & (1U << rx2)) { + /* Success! */ + state = WAITING; + goto enter_state; + } + + goto poll_state; + + case WAITING: + if (ctrlc()) + goto intr; + + if (ret < 0) + goto err; + + /* Wait for (rx1 == low) && (rx2 == high) */ + ret &= rxmask; + if (ret == (1U << rx2)) { + /* Success! */ + state = BOTH_READY; + goto enter_state; + } + if (ret != rxmask) { + /* Oops, error */ + state = START_ERROR; + goto enter_state; + } + + goto poll_state; + + case BOTH_READY: + /* + * Non-interruptable wait for (rx2 == low), however if we + * see (rx1 == high) and (rx2 == high) we should go back + * to START_ERROR. + */ + if (ret < 0) + goto poll_state; + + ret &= rxmask; + if (ret == rxmask) { + /* Oops, error */ + state = START_ERROR; + goto enter_state; + } + if (ret & (1U << rx2)) + goto poll_state; + + /* Success, we have to reset quick now! */ + (void)pca9554_set_high(tx1); + + /* Turn on the "HRESET_REQ" pin (hard-reset request) */ + printf("\nRESET: Hardware reset triggered, waiting...\n"); + out_be32(&gur->rstcr, 0x2); + while (1) + udelay(10000); + } + +enter_state: + switch (state) { + case START_ERROR: + printf("\nRESET: Negotiation error!"); + printf("\nRESET: Starting over..."); + /* Clear both GPIOs high in the right order */ + if (pca9554_set_high(tx2) < 0) + goto err; + if (pca9554_set_high(tx1) < 0) + goto err; + if (ctrlc()) + goto intr; + + goto poll_state; + + case WAITING: + printf("\nRESET: Waiting for peer..."); + /* Set tx1 low */ + if (pca9554_set_low(tx1) < 0) + goto err; + if (ctrlc()) + goto intr; + + goto poll_state; + + case BOTH_READY: + printf("\nRESET: Both ready, point of no return..."); + /* Point of no return: set tx2 low */ + if (pca9554_set_low(tx2) < 0) + goto err; + + goto poll_state; + } + + /* We only get here through gotos */ +err: + printf("\nRESET: I2C communication error!\n"); +intr: + printf("\nRESET: Aborted!\n"); + (void)pca9554_set_high(tx1); + (void)pca9554_set_high(tx2); + return; +} + diff --git a/board/exmeritus/hww-1u-1a/law.c b/board/exmeritus/hww-1u-1a/law.c new file mode 100644 index 0000000..c1dffd9 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/law.c @@ -0,0 +1,40 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/exmeritus/hww-1u-1a/tlb.c b/board/exmeritus/hww-1u-1a/tlb.c new file mode 100644 index 0000000..672e8b9 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/tlb.c @@ -0,0 +1,93 @@ +/* + * Copyright 2009-2010 eXMeritus, A Boeing Company + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd at denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Boot page */ + SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, + CONFIG_BPTR_VIRT_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, + CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - FLASH */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI memory */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, + CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, + CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 0cc6e03..49d963d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -190,8 +190,10 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { -/* Everything after the first generation of PQ3 parts has RSTCR */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ +#if defined(CONFIG_BOARD_RESET_R) + extern void board_reset_r(void); + board_reset_r(); +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) unsigned long val, msr; @@ -207,6 +209,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) val |= 0x70000000; mtspr(DBCR0,val); #else + /* Everything after the first generation of PQ3 parts has RSTCR */ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ udelay(100); diff --git a/include/configs/HWW_1U_1A.h b/include/configs/HWW_1U_1A.h new file mode 100644 index 0000000..9c0706f --- /dev/null +++ b/include/configs/HWW_1U_1A.h @@ -0,0 +1,478 @@ +/* + * Copyright 2009-2010 eXMeritus, A Boeing Company + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * HardwareWall HWW-1U-1A airborne unit configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/************************************************************************ + * High-level system configuration options * + ************************************************************************/ +/*#define DEBUG 1*/ +#define CONFIG_BOOKE 1 /* Power/PowerPC Book-E */ +#define CONFIG_E500 1 /* e500 (Power ISA v2.03 with SPE) */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 family */ +#define CONFIG_FSL_ELBC 1 /* FreeScale Enhanced LocalBus Cntlr */ +#define CONFIG_FSL_LAW 1 /* FreeScale Local Access Window */ +#define CONFIG_P2020 1 /* FreeScale P2020 */ +#define CONFIG_HWW1U1A 1 /* eXMeritus HardwareWall HWW-1U-1A */ +#define CONFIG_MP 1 /* Multiprocessing support */ + +#define CONFIG_L2_CACHE 1 /* L2 cache enabled */ +#define CONFIG_BTB 1 /* Branch predition enabled */ + +#define CONFIG_PANIC_HANG 1 /* No board reset on panic */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r() */ +#define CONFIG_BOARD_RESET_R 1 /* Call board_reset_r() */ + +/* Allow the use of 36-bit physical addresses in "HWW_1U_1A_36BIT" mode */ +#define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_MK_36BIT +# define CONFIG_PHYS_64BIT 1 +# define CONFIG_ADDR_MAP 1 +# define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */ +#endif + +/* This is the U-Boot base address and size */ +#define CONFIG_SYS_MONITOR_BASE 0xeff80000 +#define CONFIG_SYS_MONITOR_LEN 0x00080000 +#if defined(TEXT_BASE) && (TEXT_BASE != CONFIG_SYS_MONITOR_BASE) +# error "TEXT_BASE != CONFIG_SYS_MONITOR_BASE" +#endif + +/* Reserve plenty of RAM for malloc (we have 2GB+) */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* This is where we map our L2 cache so we can use it as RAM */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 +#define CONFIG_SYS_INIT_RAM_END 0x00004000 + +/* This is our temporary global data area just above the stack */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + +/* The stack grows down from the global data area */ +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* Enable IRQs and watchdog with a 1000Hz system decrementer */ +#define CONFIG_CMD_IRQ +#define CONFIG_SYS_HZ 1000 +#if 0 /* FIXME */ +#define CONFIG_WATCHDOG 1 + +/* Enable Power-On-Self-Tests */ +#define CONFIG_POST 1 +#define CONFIG_CMD_DIAG +#endif + + +/************************************************************************ + * Clock crystal configuration: * + * (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR) * + * (2) CCB: Multiplier from SYS_CLK * + * (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock) * + ************************************************************************/ +#undef CONFIG_CLOCKS_IN_MHZ +#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/ +#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/ + + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM + * 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1 + * 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused) + * 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3 + * 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH + * 0xe800_0000 0xefff_ffff 128M Spansion FLASH + * 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0) + * 0xffe0_0000 0xffef_ffff 1M CCSR + * 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller + */ + +/* Virtual Memory Map */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR @ reset */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */ + +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* Physical Memory Map */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000ul +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000ul +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000ul +#define CONFIG_SYS_FLASH_BASE_PHYS 0xe0000000ul +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000ul +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000ul +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000ul +#define CONFIG_SYS_CCSRBAR_PHYS 0xffe00000ul +#endif + +/* Legacy code needs this */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + + +/************************************************************************ + * U-Boot Environment Image: The two sectors immediately below U-Boot * + * form the U-Boot environment (regular and redundant) * + ************************************************************************/ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (one flash sector) */ +#define CONFIG_ENV_SIZE 0x02000 /* 8kB */ +#define CONFIG_ENV_SIZE_REDUND 0x02000 /* 8kB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OVERWRITE 1 + + +/************************************************************************ + * Serial Console Configuration * + ************************************************************************/ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Echo back characters received during a serial download */ +#define CONFIG_LOADS_ECHO 1 + +/* Allow a serial-download to temporarily change baud */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + + +/************************************************************************ + * PCI and PCI-Express Support * + * Memory space is mapped 1-1, but I/O space must start from 0. * + ************************************************************************/ + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* Scan PCI busses */ +#define CONFIG_CMD_PCI /* Enable the "pci" command */ +#define CONFIG_FSL_PCI_INIT 1 /* Common FreeScale PCI initialization */ +#define CONFIG_FSL_PCIE_RESET 1 /* We have PCI-E reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* PCI resources are 64-bit */ +#define CONFIG_PCI_SCAN_SHOW 1 /* Display PCI scan during boot */ + +/* Enable all 3 PCI-E controllers */ +#define CONFIG_PCIE1 1 +#define CONFIG_PCIE2 1 +#define CONFIG_PCIE3 1 + +/* PCI controller addresses */ +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) + +/* PCI bus addresses */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#endif + + +/************************************************************************ + * I2C Bus Support and devices * + ************************************************************************/ + +/* Generic FreeScale hardware I2C support */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_FSL_I2C 1 +#define CONFIG_CMD_I2C +#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* I2C bus configuration */ +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES { \ + { 0, 0x29 } \ +} + +/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x51 +#if 0 +#define CONFIG_CMD_EEPROM +#endif + +/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */ +#define CONFIG_CMD_DATE +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +/* Turn off RTC square-wave output to save battery */ +#define CONFIG_SYS_RTC_DS1337_NOOSC 1 + + +/************************************************************************ + * FreeScale DDR2/3 SDRAM Controller * + ************************************************************************/ +#define CONFIG_FSL_DDR2 1 /* Our SDRAM slot is DDR2 */ +#define CONFIG_DDR_ECC 1 /* Enable ECC by default */ +#define CONFIG_DDR_SPD 1 /* Detect DDR config from SPD EEPROM */ +#define CONFIG_SPD_EEPROM 1 /* ...why 2 config variables for this? */ +#define CONFIG_VERY_BIG_RAM 1 /* Allow 2GB+ of RAM */ +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_CMD_SDRAM + +/* Standard P2020 DDR controller parameters */ +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* Make sure to tell the DDR controller to preinitialze all of RAM */ +#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1 + +/* Enable the U-Boot "memory test" */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x7fffffff + + +/************************************************************************ + * FLASH Memory Configuration (2x 128MB SPANSION FLASH) * + ************************************************************************/ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 + +/* Flash banks (2x 128MB) */ +#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull) +#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull) +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS } + +/* Flash configuration registers */ +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(FLASH0_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(FLASH1_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 + +/* Flash timeouts (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */ + +/* Quiet flash testing */ +#define CONFIG_SYS_FLASH_QUIET_TEST 1 + +/* Don't bother checksumming the flash on boot */ +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* Make program/erase count down from 45/5 (9....8....7....) */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 + +#if 0 +# define CONFIG_CMD_JFFS2 +# define CONFIG_CMD_MTDPARTS +#endif + + +/************************************************************************ + * Ethernet Device Support * + ************************************************************************/ +#define CONFIG_NET_MULTI 1 /* We have multiple devices */ +#define CONFIG_MII 1 /* Enable MII PHY code */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* ??? */ +#define CONFIG_PHY_GIGE 1 /* Support Gigabit PHYs */ +#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */ + +#if 0 +/* All of the ethernet interfaces we should have */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_HAS_ETH4 +#endif + +/* Turn on various helpful networking commands */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING + +/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */ +#define CONFIG_TSEC_ENET 1 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC1_NAME "owt0" +#define CONFIG_TSEC2_NAME "owt1" +#define CONFIG_TSEC3_NAME "peer" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 3 +#define TSEC3_PHY_ADDR_CPUA 4 +#define TSEC3_PHY_ADDR_CPUB 5 +#define TSEC3_PHY_ADDR TSEC3_PHY_ADDR_CPUA + +/* PCI-E dual-port E1000 (external ethernet ports) */ +#define CONFIG_E1000 1 +#define CONFIG_E1000_FALLBACK_MAC { 0x00, 0x05, 0x93, 0x81, 0xff, 0xfe } + + +/************************************************************************ + * USB Thumbdrive Device Support * + ************************************************************************/ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_USB + +/* Partition and Filesystem support */ +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + + +/************************************************************************ + * Command line configuration. * + ************************************************************************/ +#define CONFIG_CMDLINE_EDITING 1 /* Enable command editing */ +#define CONFIG_COMMAND_HISTORY 1 /* Enable command history */ +#define CONFIG_AUTOCOMPLETE 1 /* Enable command completion */ +#define CONFIG_SYS_LONGHELP 1 /* Enable detailed command help */ +#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */ +#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */ +#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */ +#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */ +#define CONFIG_SYS_HUSH_PARSER 1 /* Enable a fancier shell */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Command-line continuation */ + +/* A little extra magic here for the prompt */ +#define CONFIG_SYS_PROMPT hww1u1a_get_ps1() +#ifndef __ASSEMBLY__ +const char *hww1u1a_get_ps1(void); +#endif + +/* Include a bunch of default commands we probably want */ +#include <config_cmd_default.h> + +/* Other helpful shell-like commands */ +#define CONFIG_MD5 +#define CONFIG_SHA1 +#define CONFIG_CMD_MD5SUM +#define CONFIG_CMD_SHA1 +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_SETEXPR + + +/************************************************************************ + * Image manipulation and booting * + ************************************************************************/ + +/* We use the OpenFirmware-esque "Flattened Device Tree" */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMD_ELF +#define CONFIG_SYS_BOOTMAPSZ 0x1000000 /* Maximum kernel memory map */ +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* Maximum kernel size of 16MB */ + +#if 0 +/* FIXME */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#endif + +/* This is the default address for commands with an optional address arg */ +#define CONFIG_LOADADDR 100000 +#define CONFIG_SYS_LOAD_ADDR 0x100000 + +#define CONFIG_BOOTDELAY 20 +#define CONFIG_BOOTCOMMAND "echo Not yet flashed" +#define CONFIG_BOOTARGS "" +#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1" + +/* Extra environment parameters */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "preboot=setenv bootargs \"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \ + "perf_mode=stable\0" \ + "memctl_intlv_ctl=2\0" \ + "flkernel=0xe8020000\0" \ + "flinitramfs=0xe8800000\0" \ + "fldevicetree=0xeff20000\0" \ + "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \ + "flboot=run preboot; run flbootm\0" + +#endif /* __CONFIG_H */ -- 1.7.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices Kyle Moffett @ 2010-09-03 4:00 ` Peter Tyser 2010-09-03 5:50 ` Kyle Moffett 2010-09-07 21:21 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices Moffett, Kyle D 0 siblings, 2 replies; 19+ messages in thread From: Peter Tyser @ 2010-09-03 4:00 UTC (permalink / raw) To: u-boot Hi Kyle, > MAKEALL | 2 + > Makefile | 4 + MAINTAINERS entry is missing. > board/exmeritus/hww-1u-1a/Makefile | 54 +++ > board/exmeritus/hww-1u-1a/config.mk | 31 ++ > board/exmeritus/hww-1u-1a/ddr.c | 136 +++++++ > board/exmeritus/hww-1u-1a/gpios.h | 131 ++++++ > board/exmeritus/hww-1u-1a/hww-1u-1a.c | 697 +++++++++++++++++++++++++++++++++ > board/exmeritus/hww-1u-1a/law.c | 40 ++ > board/exmeritus/hww-1u-1a/tlb.c | 93 +++++ > cpu/mpc85xx/cpu.c | 7 +- > include/configs/HWW_1U_1A.h | 478 ++++++++++++++++++++++ > 11 files changed, 1671 insertions(+), 2 deletions(-) > create mode 100644 board/exmeritus/hww-1u-1a/Makefile > create mode 100644 board/exmeritus/hww-1u-1a/config.mk > create mode 100644 board/exmeritus/hww-1u-1a/ddr.c > create mode 100644 board/exmeritus/hww-1u-1a/gpios.h > create mode 100644 board/exmeritus/hww-1u-1a/hww-1u-1a.c > create mode 100644 board/exmeritus/hww-1u-1a/law.c > create mode 100644 board/exmeritus/hww-1u-1a/tlb.c > create mode 100644 include/configs/HWW_1U_1A.h <snip> > --- a/Makefile > +++ b/Makefile > @@ -2499,6 +2499,10 @@ P2020DS_36BIT_config \ > P2020DS_config: unconfig > @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale > > +HWW_1U_1A_36BIT_config \ > +HWW_1U_1A_config: unconfig > + @$(MKCONFIG) -t $(@:_config=) HWW_1U_1A ppc mpc85xx hww-1u-1a exmeritus > + The new way to add a board is via boards.cfg. You shouldn't need to modify this Makefile. <snip> > +++ b/board/exmeritus/hww-1u-1a/config.mk > @@ -0,0 +1,31 @@ > +# > +# Copyright 2009-2010 eXMeritus, A Boeing Company > +# Copyright 2007-2009 Freescale Semiconductor, Inc. > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +# > +# p2020ds board > +# P2020ds? > +ifndef TEXT_BASE > +TEXT_BASE = 0xeff80000 > +endif > + > +RESET_VECTOR_ADDRESS = 0xeffffffc > diff --git a/board/exmeritus/hww-1u-1a/ddr.c b/board/exmeritus/hww-1u-1a/ddr.c > new file mode 100644 > index 0000000..b587c87 > --- /dev/null > +++ b/board/exmeritus/hww-1u-1a/ddr.c > @@ -0,0 +1,136 @@ > +/* > + * Copyright 2009-2010 eXMeritus, A Boeing Company > + * Copyright 2008-2009 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * Version 2 as published by the Free Software Foundation. > + */ > + > +#include <common.h> > +#include <i2c.h> > + > +#include <asm/fsl_ddr_sdram.h> > +#include <asm/fsl_ddr_dimm_params.h> > + > +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) > +{ > + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); > +} > + > +unsigned int fsl_ddr_get_mem_data_rate(void) > +{ > + return get_ddr_freq(0); > +} > + > +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, > + unsigned int ctrl_num) > +{ > + unsigned int i; > + unsigned int i2c_address = 0; > + > + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { > + if (ctrl_num == 0 && i == 0) > + i2c_address = SPD_EEPROM_ADDRESS1; > + get_spd(&(ctrl_dimms_spd[i]), i2c_address); > + } > +} > + > +typedef struct { > + u32 datarate_mhz_low; > + u32 datarate_mhz_high; > + u32 n_ranks; > + u32 clk_adjust; > + u32 cpo; > + u32 write_data_delay; > + u32 force_2T; > +} board_specific_parameters_t; > + > +/* ranges for parameters: > + * wr_data_delay = 0-6 > + * clk adjust = 0-8 > + * cpo 2-0x1E (30) > + */ > + > + > +/* XXX: these values need to be checked for all interleaving modes. */ > +/* XXX: No reliable dual-rank 800 MHz setting has been found. It may > + * seem reliable, but errors will appear when memory intensive > + * program is run. */ > +/* XXX: Single rank at 800 MHz is OK. */ These comments look like the p2020ds comments. Please remove/update them if they don't apply to your board. > +const board_specific_parameters_t board_specific_parameters[][20] = { > + { > + /* memory controller 0 */ > + /* lo| hi| num| clk| cpo|wrdata|2T */ > + /* mhz| mhz|ranks|adjst| | delay| */ > +#if 0 > + { 0, 333, 2, 6, 7, 3, 0}, > + {334, 400, 2, 6, 9, 3, 0}, > + {401, 549, 2, 6, 11, 3, 0}, > + {550, 680, 2, 1, 10, 5, 0}, > + {681, 850, 2, 1, 12, 5, 1}, > + { 0, 333, 1, 6, 7, 3, 0}, > + {334, 400, 1, 6, 9, 3, 0}, > + {401, 549, 1, 6, 11, 3, 0}, > + {550, 680, 1, 1, 10, 5, 0}, > + {681, 850, 1, 1, 12, 5, 0} > +#else > + { 0,1000, 2, 4, 4, 2, 0}, > + { 0,1000, 1, 4, 4, 2, 0}, > +#endif > + }, > +}; I'd remove the #if 0 above. Dead code is bad. > +void fsl_ddr_board_options(memctl_options_t *popts, > + dimm_params_t *pdimm, > + unsigned int ctrl_num) > +{ > + const board_specific_parameters_t *pbsp = > + &(board_specific_parameters[ctrl_num][0]); > + u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / > + sizeof(board_specific_parameters[0][0]); > + u32 i; > + ulong ddr_freq; > + > + /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in > + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If > + * there are two dimms in the controller, set odt_rd_cfg to 3 and > + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. > + */ > + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { > + if (i&1) { /* odd CS */ > + popts->cs_local_opts[i].odt_rd_cfg = 0; > + popts->cs_local_opts[i].odt_wr_cfg = 0; > + } else { /* even CS */ > + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { > + popts->cs_local_opts[i].odt_rd_cfg = 0; > + popts->cs_local_opts[i].odt_wr_cfg = 4; > + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { > + popts->cs_local_opts[i].odt_rd_cfg = 3; > + popts->cs_local_opts[i].odt_wr_cfg = 3; > + } > + } > + } > + > + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr > + * freqency and n_banks specified in board_specific_parameters table. > + */ > + ddr_freq = get_ddr_freq(0) / 1000000; > + for (i = 0; i < num_params; i++) { > + if (ddr_freq >= pbsp->datarate_mhz_low && > + ddr_freq <= pbsp->datarate_mhz_high && > + pdimm->n_ranks == pbsp->n_ranks) { > + popts->clk_adjust = pbsp->clk_adjust; > + popts->cpo_override = pbsp->cpo; > + popts->write_data_delay = pbsp->write_data_delay; > + popts->twoT_en = pbsp->force_2T; > + } > + pbsp++; > + } > + > + /* > + * Factors to consider for half-strength driver enable: > + * - number of DIMMs installed > + */ > + popts->half_strength_driver_enable = 0; > +} > diff --git a/board/exmeritus/hww-1u-1a/gpios.h b/board/exmeritus/hww-1u-1a/gpios.h > new file mode 100644 > index 0000000..5b382a3 > --- /dev/null > +++ b/board/exmeritus/hww-1u-1a/gpios.h > @@ -0,0 +1,131 @@ > +/* > + * Copyright 2010 eXMeritus, A Boeing Company > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */ > +#define GPIO_CPU_ID (1UL << (31 - 8)) > +#define GPIO_BLUE_LED (1UL << (31 - 9)) > +#define GPIO_DIMM_RESET (1UL << (31 - 10)) > +#define GPIO_USB_RESET (1UL << (31 - 11)) > +#define GPIO_UNUSED_12 (1UL << (31 - 12)) > +#define GPIO_GETH0_RESET (1UL << (31 - 13)) > +#define GPIO_RS422_RE (1UL << (31 - 14)) > +#define GPIO_RS422_DE (1UL << (31 - 15)) > +#define IRQ_I2CINT (1UL << (31 - 20)) > +#define IRQ_FANINT (1UL << (31 - 21)) > +#define IRQ_DIMM_EVENT (1UL << (31 - 22)) > + > +/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ > +#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0)) > +#define GPIO_CPUA_CPU_READY (1UL << (31 - 1)) > +#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2)) > +#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3)) > +#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */ > +#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */ > +#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */ > +#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */ > +#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16)) > +#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17)) > +#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18)) > +#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19)) > + > +/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ > +#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0)) > +#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1)) > +#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2)) > +#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3)) > +#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4)) > +#define GPIO_CPUB_CPU_READY (1UL << (31 - 5)) > +#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6)) > +#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7)) > +#define IRQ_CPUB_SD_1A (1UL << (31 - 16)) > +#define IRQ_CPUB_SD_2B (1UL << (31 - 17)) > +#define IRQ_CPUB_SD_2A (1UL << (31 - 18)) > +#define IRQ_CPUB_SD_1B (1UL << (31 - 19)) > + > +#define GPIOIRQ_CPUB_INIT_DIR /* Output pins */ \ > + ( GPIOIRQ_GLBL_INIT_DIR | GPIO_CPUB_CPU_READY \ > + | GPIO_CPUB_DEBUG_LED2 | GPIO_CPUB_DEBUG_LED1 \ > + | GPIO_CPUB_RMUX_SEL0A | GPIO_CPUB_RMUX_SEL0B \ > + | GPIO_CPUB_RMUX_SEL1A | GPIO_CPUB_RMUX_SEL1B ) > + > +#define GPIOIRQ_CPUB_INIT_VAL /* Pins to drive high */ \ > + ( GPIOIRQ_GLBL_INIT_VAL | GPIO_CPUB_CPU_READY \ > + | GPIO_CPUB_RMUX_SEL0A | GPIO_CPUB_RMUX_SEL0B ) > + > +#define GPIOIRQ_CPUB_BOOT_VAL /* Pins to drive high */ \ > + ( GPIOIRQ_GLBL_BOOT_VAL | GPIO_CPUB_CPU_READY \ > + | GPIO_CPUB_RMUX_SEL0A | GPIO_CPUB_RMUX_SEL0B ) > + > +static inline void hww1u1a_gpio_set(unsigned int mask, > + unsigned int dir, unsigned int val) > +{ > + volatile ccsr_gpio_t *gpio; > + > + /* First mask off the unwanted parts of "dir" and "val" */ > + dir &= mask; > + val &= mask; > + > + /* Now read in the values we're supposed to preserve */ > + gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); > + dir |= (in_be32(&gpio->gpdir) & ~mask); > + val |= (in_be32(&gpio->gpdat) & ~mask); > + > + /* Now write out the new values, writing the direction first */ > + out_be32(&gpio->gpdir, dir); > + asm("sync; isync":::"memory"); > + out_be32(&gpio->gpdat, val); > +} > + > +static inline void hww1u1a_gpio_set_in(unsigned int gpios) > +{ > + hww1u1a_gpio_set(gpios, 0x00000000, 0x00000000); > +} > + > +static inline void hww1u1a_gpio_set_low(unsigned int gpios) > +{ > + hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0x00000000); > +} > + > +static inline void hww1u1a_gpio_set_high(unsigned int gpios) > +{ > + hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF); > +} > + > +static inline unsigned int hww1u1a_gpio_get(unsigned int mask) > +{ > + volatile ccsr_gpio_t *gpio; > + unsigned int ret; > + > + /* Read the requested values */ > + gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); > + ret = mask & in_be32(&gpio->gpdat); > + > + return ret; > +} The GPIO functions above aren't hww1u1a specific. What about adding generic 85xx GPIO functions so others can use them too? > +static inline unsigned int hww1u1a_is_cpu_a(void) > +{ > + return !hww1u1a_gpio_get(GPIO_CPU_ID); > +} > + > +static inline unsigned int hww1u1a_is_cpu_b(void) > +{ > + return !!hww1u1a_gpio_get(GPIO_CPU_ID); > +} > + With only 2 CPUs do you need both the functions above? Eg below you use the logic: if (hww1u1a_is_cpu_a()) stuff else stuff I don't see hww1u1a_is_cpu_b() being used anywhere. > > diff --git a/board/exmeritus/hww-1u-1a/hww-1u-1a.c b/board/exmeritus/hww-1u-1a/hww-1u-1a.c > new file mode 100644 > index 0000000..9671549 > --- /dev/null > +++ b/board/exmeritus/hww-1u-1a/hww-1u-1a.c > @@ -0,0 +1,697 @@ > +/* > + * Copyright 2009-2010 eXMeritus, A Boeing Company > + * Copyright 2007-2009 Freescale Semiconductor, Inc. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <command.h> > +#include <pci.h> > +#include <asm/processor.h> > +#include <asm/mmu.h> > +#include <asm/cache.h> > +#include <asm/immap_85xx.h> > +#include <asm/fsl_pci.h> > +#include <asm/fsl_ddr_sdram.h> > +#include <asm/io.h> > +#include <miiphy.h> > +#include <libfdt.h> > +#include <fdt_support.h> > +#include <tsec.h> > +#include <asm/fsl_law.h> > +#include <asm/mp.h> > +#include <netdev.h> > +#include <malloc.h> > +#include <i2c.h> > + > +#include "gpios.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +phys_size_t fixed_sdram(void); > + > +int checkboard(void) > +{ > + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; > + > + unsigned int gpio_high = 0; > + unsigned int gpio_low = 0; > + unsigned int gpio_in = 0; > + unsigned int i; > + > + puts("Board: HWW-1U-1A "); > +#ifdef CONFIG_PHYS_64BIT > + puts("(36-bit addrmap) "); > +#endif > + > + /* > + * First just figure out which CPU we're on, then use that to > + * configure the lists of other GPIOs to be programmed. > + */ > + hww1u1a_gpio_set_in(GPIO_CPU_ID); > + if (hww1u1a_is_cpu_a()) { > + puts("CPU A\n"); > + > + /* We want to turn on some LEDs */ > + gpio_high |= GPIO_CPUA_CPU_READY; > + gpio_low |= GPIO_CPUA_DEBUG_LED1; > + gpio_low |= GPIO_CPUA_DEBUG_LED2; > + > + /* Disable the unused transmitters */ > + gpio_low |= GPIO_CPUA_TDIS1A; > + gpio_high |= GPIO_CPUA_TDIS1B; > + gpio_low |= GPIO_CPUA_TDIS2A; > + gpio_high |= GPIO_CPUA_TDIS2B; > + } else { > + puts("CPU B\n"); > + > + /* We want to turn on some LEDs */ > + gpio_high |= GPIO_CPUB_CPU_READY; > + gpio_low |= GPIO_CPUB_DEBUG_LED1; > + gpio_low |= GPIO_CPUB_DEBUG_LED2; > + > + /* Enable the appropriate receivers */ > + gpio_high |= GPIO_CPUB_RMUX_SEL0A; > + gpio_high |= GPIO_CPUB_RMUX_SEL0B; > + gpio_low |= GPIO_CPUB_RMUX_SEL1A; > + gpio_low |= GPIO_CPUB_RMUX_SEL1B; > + } > + > + /* These GPIOs are common */ > + gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT; > + gpio_low |= GPIO_RS422_RE; > + gpio_high |= GPIO_RS422_DE; > + > + /* Ok, now go ahead and program all of those in one go */ > + hww1u1a_gpio_set( gpio_high|gpio_low|gpio_in, > + gpio_high|gpio_low, > + gpio_high); The tab above should be removed. > + > + /* > + * If things have been taken out of reset early (for example, by one > + * of the BDI3000 debuggers), then we need to put them back in reset > + * and delay a while before we continue. > + */ > +#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET) > + if (hww1u1a_gpio_get(GPIO_RESETS)) { > + puts("Debugger detected... extra device reset enabled!\n"); > + > + /* Put stuff into reset and disable the DDR controller */ > + hww1u1a_gpio_set_low(GPIO_RESETS); > + out_be32(&ddr->sdram_cfg, 0x00000000); > + > + puts(" Waiting 1 sec for reset..."); > + for (i = 0; i < 10; i++) { > + udelay(100000); > + puts("."); > + } > + puts("\n"); > + } > + > + /* Now bring everything back out of reset again */ > + hww1u1a_gpio_set_high(GPIO_RESETS); > + return 0; > +} > + > +/* Create a prompt-like string: "uboot at HOSTNAME% " */ > +#define PROMPT_PREFIX "uboot at exm" > +#define PROMPT_SUFFIX "% " > + > +/* This function returns a PS1 prompt based on the serial number */ > +static char *hww1u1a_prompt = NULL; > +const char *hww1u1a_get_ps1(void) > +{ > + unsigned long len, i, j; > + const char *serialnr; > + > + /* If our prompt was already set, just use that */ > + if (hww1u1a_prompt) > + return hww1u1a_prompt; > + > + /* Use our serial number if present, otherwise "UNPROGRAMMED-[AB]" */ > + serialnr = getenv("serial#"); > + if (!serialnr || !serialnr[0]) { > + if (hww1u1a_is_cpu_a()) > + serialnr = "999999-XA"; > + else > + serialnr = "999999-XB"; > + } > + > + /* > + * We will turn the serial number into a hostname by: > + * (A) Delete all non-alphanumerics. > + * (B) Lowercase all letters > + * (C) Prefix "exm" > + */ > + for (i = 0, len = 0; serialnr[i]; i++) { > + if ('0' <= serialnr[i] && serialnr[i] <= '9') > + len++; > + else if ('a' <= serialnr[i] && serialnr[i] <= 'z') > + len++; > + else if ('A' <= serialnr[i] && serialnr[i] <= 'Z') > + len++; > + } There are utility functions in include/linux/ctype.h that do the above checks. This, and the similar chunk of code below seems like a lot of effort to get rid of non digits/alpha chars. Is there a reason to not just assume the serial number variable is valid, or include all chars in the prompt? > + len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX); /* Includes NUL */ > + hww1u1a_prompt = malloc(len); > + if (!hww1u1a_prompt) > + return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX; > + > + /* Now actually fill it in */ > + i = 0; > + > + /* Handle the prefix */ > + for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++) > + hww1u1a_prompt[i++] = PROMPT_PREFIX[j]; > + > + /* Now the serial# part of the hostname */ > + for (j = 0; serialnr[j]; j++) { > + if ('0' <= serialnr[j] && serialnr[j] <= '9') > + hww1u1a_prompt[i++] = serialnr[j]; > + else if ('a' <= serialnr[j] && serialnr[j] <= 'z') > + hww1u1a_prompt[i++] = serialnr[j]; > + else if ('A' <= serialnr[j] && serialnr[j] <= 'Z') > + hww1u1a_prompt[i++] = serialnr[j] + 'a' - 'A'; > + } > + > + /* Finally the suffix */ > + for (j = 0; j < sizeof(PROMPT_SUFFIX); j++) > + hww1u1a_prompt[i++] = PROMPT_SUFFIX[j]; > + > + /* This should all have added up, but just in case */ > + hww1u1a_prompt[len - 1] = '\0'; > + > + /* Now we're done */ > + return hww1u1a_prompt; > +} > + > + > +phys_size_t initdram(int board_type) > +{ > +#ifndef CONFIG_SPD_EEPROM > + /* This is manual (non-SPD) DDR2 SDRAM configuration (2GB ECC) */ > + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; > + phys_size_t dram_size = (2048ULL) << 20; > + out_be32(&ddr->cs0_bnds, 0x0000003F); > + out_be32(&ddr->cs1_bnds, 0x0040007F); > + out_be32(&ddr->cs0_config, 0x80014202); > + out_be32(&ddr->cs1_config, 0x80014202); > + out_be32(&ddr->timing_cfg_0, 0x00330804); > + out_be32(&ddr->timing_cfg_1, 0x6f69f643); > + out_be32(&ddr->timing_cfg_2, 0x022068cd); > + out_be32(&ddr->timing_cfg_3, 0x00030000); > + out_be32(&ddr->sdram_cfg_2, 0x04400010); > + out_be32(&ddr->sdram_mode, 0x00440452); > + out_be32(&ddr->sdram_mode_2, 0x00000000); > + out_be32(&ddr->sdram_md_cntl, 0x00000000); > + out_be32(&ddr->sdram_interval, 0x0a280110); > + out_be32(&ddr->sdram_data_init, 0xDEADBEEF); > + out_be32(&ddr->sdram_clk_cntl, 0x02000000); > + out_be32(&ddr->timing_cfg_4, 0x00000000); > + out_be32(&ddr->timing_cfg_5, 0x00000000); > + out_be32(&ddr->ddr_zq_cntl, 0x00000000); > + out_be32(&ddr->ddr_wrlvl_cntl, 0x00000000); > + out_be32(&ddr->ip_rev1, 0x00020403); > + out_be32(&ddr->ip_rev2, 0x00000100); > + out_be32(&ddr->err_int_en, 0x0000000D); > + out_be32(&ddr->err_disable, 0x00000000); > + out_be32(&ddr->err_sbe, 0x00010000); > + out_be32(&ddr->ddr_cdr1, 0x00040000); > + out_be32(&ddr->ddr_cdr2, 0x00000000); > + out_be32(&ddr->sdram_cfg, 0x73000000); > + > + /* Allow time for the clocks to stabilize before enabling */ > + udelay(500); > + out_be32(&ddr->sdram_cfg, 0xF3000000); Get rid of the tab above. > + /* Now wait until memory is initialized */ > + while (in_be32(&ddr->sdram_cfg_2) & 0x00000010) > + udelay(1000); > + > + /* Finally we set up the local access windows */ > + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, dram_size, > + LAW_TRGT_IF_DDR) < 0) { > + printf("ERROR setting Local Access Windows for DDR\n"); > + return 0; > + }; > +#else > + /* We also support "Automagic mode" */ > + phys_size_t dram_size = fsl_ddr_sdram(); > +#endif > + > + /* Before we're done we need to set up the TLB entries */ > + return setup_ddr_tlbs(dram_size >> 20) << 20; > +} > + > +static struct pci_controller pcie1_hose; > +static struct pci_controller pcie2_hose; > +static struct pci_controller pcie3_hose; > +void pci_init_board(void) > +{ > + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); > + struct fsl_pci_info pci_info[3]; > + u32 devdisr, pordevsr, io_sel; > + int first_free_busno = 0; > + int num = 0; > + > + int pcie_ep, pcie_configured; > + > + devdisr = in_be32(&gur->devdisr); > + pordevsr = in_be32(&gur->pordevsr); > + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; > + > + debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); > + > + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) > + printf(" eTSEC2 is in sgmii mode.\n"); > + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) > + printf(" eTSEC3 is in sgmii mode.\n"); > + > + puts("\n"); > + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); > + > + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { > + SET_STD_PCIE_INFO(pci_info[num], 1); > + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); > + printf(" PCIE1 connected as %s (base addr %lx)\n", > + pcie_ep ? "Endpoint" : "Root Complex", > + pci_info[num].regs); > + first_free_busno = fsl_pci_init_port(&pci_info[num++], > + &pcie1_hose, first_free_busno); > + } else { > + printf(" PCIE1: disabled\n"); > + } > + > + puts("\n"); > + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); > + > + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { > + SET_STD_PCIE_INFO(pci_info[num], 2); > + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); > + printf(" PCIE2 connected as %s (base addr %lx)\n", > + pcie_ep ? "Endpoint" : "Root Complex", > + pci_info[num].regs); > + first_free_busno = fsl_pci_init_port(&pci_info[num++], > + &pcie2_hose, first_free_busno); > + } else { > + printf(" PCIE2: disabled\n"); > + } > + > + puts("\n"); > + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); > + > + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { > + SET_STD_PCIE_INFO(pci_info[num], 3); > + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); > + printf(" PCIE3 connected as %s (base addr %lx)\n", > + pcie_ep ? "Endpoint" : "Root Complex", > + pci_info[num].regs); > + first_free_busno = fsl_pci_init_port(&pci_info[num++], > + &pcie3_hose, first_free_busno); > + } else { > + printf(" PCIE3: disabled\n"); > + } > + puts("\n"); > + > +} > + > +int board_early_init_r(void) > +{ > + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; > + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); > + > + /* > + * Remap bootflash region to caching-inhibited > + * so that flash can be erased properly. > + */ > + > + /* Flush d-cache and invalidate i-cache of any FLASH data */ > + flush_dcache(); > + invalidate_icache(); > + > + /* invalidate existing TLB entry for FLASH */ > + disable_tlb(flash_esel); > + > + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, flash_esel, BOOKE_PAGESZ_256M, 1); > + > + return 0; > +} > + > +int board_eth_init(bd_t *bis) > +{ > + struct tsec_info_struct tsec_info[4]; > + volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); > + > + SET_STD_TSEC_INFO(tsec_info[0], 1); > + SET_STD_TSEC_INFO(tsec_info[1], 2); > + SET_STD_TSEC_INFO(tsec_info[2], 3); > + if (pgpio->gpdat & GPIO_CPU_ID) Is the above check the same as the hww1u1a_is_cpu_a() function previously added? > + tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB; > + else > + tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA; > + > + tsec_eth_init(bis, tsec_info, 3); > + return pci_eth_init(bis); > +} > + > +void ft_board_setup(void *blob, bd_t *bd) > +{ > + phys_addr_t base; > + phys_size_t size; > + > + ft_cpu_setup(blob, bd); > + > + base = getenv_bootm_low(); > + size = getenv_bootm_size(); > + > + fdt_fixup_memory(blob, (u64)base, (u64)size); > + > + ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); > + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); > + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); > +} > + > +void board_lmb_reserve(struct lmb *lmb) > +{ > + cpu_mp_lmb_reserve(lmb); > +} > + > +/* We don't have any really usable POST memory, so just fake it */ > +unsigned long post_word_load (void) > +{ > + return 0l; > +} > + > +void post_word_store (unsigned long val) > +{ > + return; > +} Does this work with POSTs? I had thought you'd need to be able to read/write the post word, even if it wasn't saved across reboots. It should be in a #ifdef CONFIG_POST if you do keep it around. > +/* > + * Unfortunately we have a bit of a problem with our reset line wiring on the > + * HWW-1U-1A boards. > + * > + * Specifically the "CPU A" reset controls all of the PCI devices on the > + * IO/backplane card, which means ethernet and SATA controllers for both > + * CPU A *and* CPU B. > + * > + * This is somewhat of a problem if the CPUs are reset independently... CPU B > + * might fail to come up because his PCI devices are confused, or CPU B might > + * die because CPU A just reset the SATA controller for his root filesystem. > + * > + * Since in practice the CPUs never need to reboot independently we will go > + * ahead and require GPIO cross-communication between them before either one > + * will reset. > + * > + * The communication protocol uses GPIOs 4-7 on the PCA9554 GPIO expander > + * found on I2C-2 at address 0x3f. CPU A uses 4,5 as TX and 6,7 as RX; for > + * CPU B we use the exact opposite. > + * > + * The GPIOs initialize as inputs during poweron, and are pulled high; the > + * PCA9554 expanders will maintain valid outputs over soft-reset allowing for > + * reliable operation. > + * > + * To avoid duplication, we will assign names to the GPIOs: > + * ,---------------------------------------. > + * | GPIO4 | GPIO5 | GPIO6 | GPIO7 | > + * ,---------|=========|=========|=========|=========| > + * | CPU A | tx1 | tx2 | rx1 | rx2 | > + * |---------|---------|---------|---------|---------| > + * | CPU B | rx1 | rx2 | tx1 | tx2 | > + * `-------------------------------------------------' > + * > + * The state machine for each CPU is below. In simplistic terms, each CPU > + * waits until the other has cleared its GPIOs, then cause a tx1 high=>low > + * transition. Upon seeing the other CPU do the same, it will perform a > + * tx2 high=>low transition and again wait. > + * > + * Once both CPUs have performed and seen both transitions, they will each > + * set tx1 high (to create an "invalid" state) and then reset. > + * > + * ,--------------. > + * | START/ERROR: |<==-. > + * ,-==>| tx2 = 1; | || (rx2 == 0) > + * || | tx1 = 1; | ==-' > + * || `--------------' > + * || || > + * || || (rx2 == 1) > + * || \/ > + * || ,--------------. > + * || | WAITING: |<==-. > + * |\== | tx1 = 0; | || (rx1 == 1) && (rx2 == 1) > + * || | | ==-' > + * || `--------------' > + * || || > + * || || (rx1 == 0) && (rx2 == 1) > + * || \/ > + * || ,--------------. > + * || | BOTH_READY: |<==-. > + * `-== | tx2 = 0; | || (rx1 == 0) && (rx2 == 1) > + * | | ==-' > + * `--------------' > + * || > + * || (rx2 == 0) > + * \/ > + * ,--------------. > + * | RESETTING: | > + * | tx1 = 1; | > + * | reset(); | > + * `--------------' > + * > + * While in the "BOTH_READY" state a high-to-low rx2 transition must be > + * followed within 50ms by activation of the HRESET_REQ signal. That > + * state MUST NOT be interrupted by any event other than the observed > + * event (rx1 == high) && (rx2 == high). > + */ > + > +#define PCA9554_I2C_ADDR 0x3f > +static inline int pca9554_read(u8 reg) > +{ > + u8 value; > + int ret; > + > + i2c_set_bus_num(1); > + ret = i2c_read(PCA9554_I2C_ADDR, reg, 1, &value, 1); > + if (ret < 0) > + return ret; > + return value; > +} > +static inline int pca9554_write(u8 reg, u8 value) > +{ > + i2c_set_bus_num(1); > + return i2c_write(PCA9554_I2C_ADDR, reg, 1, &value, 1); > +} > +static inline int pca9554_setmask(u8 reg, u8 value, u8 mask) > +{ > + int ret = pca9554_read(reg); > + if (ret < 0) > + return ret; > + > + return pca9554_write(reg, (ret & ~mask) | (value & mask)); > +} > + > +#define PCA9554_DATA_IN 0x00 > +#define PCA9554_DATA_OUT 0x01 > +#define PCA9554_INVERT 0x02 > +#define PCA9554_IS_INPUT 0x03 > + > +static inline int pca9554_set_low(u8 gpio) > +{ > + return pca9554_setmask(PCA9554_DATA_OUT, 0x00, (1U << gpio)); > +} > + > +static inline int pca9554_set_high(u8 gpio) > +{ > + return pca9554_setmask(PCA9554_DATA_OUT, 0xff, (1U << gpio)); > +} > + > +static inline int pca9554_set_output(u8 gpio) > +{ > + return pca9554_setmask(PCA9554_IS_INPUT, 0x00, (1U << gpio)); > +} > + > +static inline int pca9554_set_input(u8 gpio) > +{ > + return pca9554_setmask(PCA9554_DATA_OUT, 0xff, (1U << gpio)); > +} These look very similar to the pca953x driver. It'd be worth investigate using it. > +void board_reset_r(void) > +{ > + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); > + u8 tx1, tx2, rx1, rx2, rxmask; > + int ret; > + > + /* Our state-machine state */ > + enum { > + START_ERROR = 0, > + WAITING, > + BOTH_READY, > + } state; > + > + printf("RESET: Preparing..."); > + > + /* First clear the "INVERT" setting on all relevant GPIOs */ > + if (pca9554_setmask(PCA9554_INVERT, 0x00, 0xf0) < 0) > + goto err; > + > + /* Check what CPU we are and configure accordingly. */ > + if (hww1u1a_is_cpu_a()) { > + tx1 = 4; tx2 = 5; rx1 = 6; rx2 = 7; > + } else { > + rx1 = 4; rx2 = 5; tx1 = 6; tx2 = 7; > + } > + rxmask = (1U << rx1) | (1U << rx2); > + > + /* Configure both inputs */ > + if (pca9554_set_input(rx1) < 0) > + goto err; > + if (pca9554_set_input(rx2) < 0) > + goto err; > + > + /* Make sure the very first thing we do is set the "tx2" GPIO high */ > + if (pca9554_set_high(tx2) < 0) > + goto err; > + if (pca9554_set_output(tx2) < 0) > + goto err; > + > + /* Now reset our other transmit pin */ > + if (pca9554_set_high(tx1) < 0) > + goto err; > + if (pca9554_set_output(tx1) < 0) > + goto err; > + > + /* Enter the state machine */ > + state = START_ERROR; > + > +poll_state: > + ret = pca9554_read(PCA9554_DATA_IN); > + switch (state) { > + case START_ERROR: > + if (ctrlc()) > + goto intr; > + > + if (ret < 0) > + goto err; > + > + /* Wait for (rx2 == high) */ > + if (ret & (1U << rx2)) { > + /* Success! */ > + state = WAITING; > + goto enter_state; > + } > + > + goto poll_state; > + > + case WAITING: > + if (ctrlc()) > + goto intr; > + > + if (ret < 0) > + goto err; > + > + /* Wait for (rx1 == low) && (rx2 == high) */ > + ret &= rxmask; > + if (ret == (1U << rx2)) { > + /* Success! */ > + state = BOTH_READY; > + goto enter_state; > + } > + if (ret != rxmask) { > + /* Oops, error */ > + state = START_ERROR; > + goto enter_state; > + } > + > + goto poll_state; > + > + case BOTH_READY: > + /* > + * Non-interruptable wait for (rx2 == low), however if we > + * see (rx1 == high) and (rx2 == high) we should go back > + * to START_ERROR. > + */ > + if (ret < 0) > + goto poll_state; > + > + ret &= rxmask; > + if (ret == rxmask) { > + /* Oops, error */ > + state = START_ERROR; > + goto enter_state; > + } > + if (ret & (1U << rx2)) > + goto poll_state; > + > + /* Success, we have to reset quick now! */ > + (void)pca9554_set_high(tx1); > + > + /* Turn on the "HRESET_REQ" pin (hard-reset request) */ > + printf("\nRESET: Hardware reset triggered, waiting...\n"); > + out_be32(&gur->rstcr, 0x2); > + while (1) > + udelay(10000); > + } > + > +enter_state: > + switch (state) { > + case START_ERROR: > + printf("\nRESET: Negotiation error!"); > + printf("\nRESET: Starting over..."); > + /* Clear both GPIOs high in the right order */ > + if (pca9554_set_high(tx2) < 0) > + goto err; > + if (pca9554_set_high(tx1) < 0) > + goto err; > + if (ctrlc()) > + goto intr; > + > + goto poll_state; > + > + case WAITING: > + printf("\nRESET: Waiting for peer..."); > + /* Set tx1 low */ > + if (pca9554_set_low(tx1) < 0) > + goto err; > + if (ctrlc()) > + goto intr; > + > + goto poll_state; > + > + case BOTH_READY: > + printf("\nRESET: Both ready, point of no return..."); > + /* Point of no return: set tx2 low */ > + if (pca9554_set_low(tx2) < 0) > + goto err; > + > + goto poll_state; > + } > + > + /* We only get here through gotos */ > +err: > + printf("\nRESET: I2C communication error!\n"); > +intr: > + printf("\nRESET: Aborted!\n"); > + (void)pca9554_set_high(tx1); > + (void)pca9554_set_high(tx2); > + return; > +} > + > diff --git a/board/exmeritus/hww-1u-1a/law.c b/board/exmeritus/hww-1u-1a/law.c > new file mode 100644 > index 0000000..c1dffd9 > --- /dev/null > +++ b/board/exmeritus/hww-1u-1a/law.c > @@ -0,0 +1,40 @@ > +/* > + * Copyright 2008-2009 Freescale Semiconductor, Inc. > + * > + * (C) Copyright 2000 > + * Wolfgang Denk, DENX Software Engineering, wd at denx.de. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/fsl_law.h> > +#include <asm/mmu.h> > + > +struct law_entry law_table[] = { > + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), > + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), > + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), > + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), > + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), > + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), > + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), > +}; > + > +int num_law_entries = ARRAY_SIZE(law_table); > diff --git a/board/exmeritus/hww-1u-1a/tlb.c b/board/exmeritus/hww-1u-1a/tlb.c > new file mode 100644 > index 0000000..672e8b9 > --- /dev/null > +++ b/board/exmeritus/hww-1u-1a/tlb.c > @@ -0,0 +1,93 @@ > +/* > + * Copyright 2009-2010 eXMeritus, A Boeing Company > + * Copyright 2008-2009 Freescale Semiconductor, Inc. > + * > + * (C) Copyright 2000 > + * Wolfgang Denk, DENX Software Engineering, wd at denx.de. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/mmu.h> > + > +struct fsl_e_tlb_entry tlb_table[] = { > + /* TLB 0 - for temp stack in cache */ > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + > + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, > + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, > + MAS3_SX|MAS3_SW|MAS3_SR, 0, > + 0, 0, BOOKE_PAGESZ_4K, 0), > + > + /* TLB 1 */ > + /* *I*** - Boot page */ > + SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, > + CONFIG_BPTR_VIRT_ADDR, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 0, BOOKE_PAGESZ_4K, 1), > + > + /* *I*G* - CCSRBAR */ > + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, > + CONFIG_SYS_CCSRBAR_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 1, BOOKE_PAGESZ_1M, 1), > + > + /* W**G* - FLASH */ > + /* This will be changed to *I*G* after relocation to RAM. */ > + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, > + CONFIG_SYS_FLASH_BASE_PHYS, > + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, > + 0, 2, BOOKE_PAGESZ_256M, 1), > + > + /* *I*G* - PCI memory */ > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, > + CONFIG_SYS_PCIE3_MEM_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 3, BOOKE_PAGESZ_1G, 1), The LAW is only 512 MB. > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, > + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 4, BOOKE_PAGESZ_256M, 1), Is there a reason you don't use CONFIG_SYS_PCIE2_MEM_* here? And the LAW is 512MB above. > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, > + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 5, BOOKE_PAGESZ_256M, 1), > + > + /* *I*G* - PCI I/O */ > + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, > + CONFIG_SYS_PCIE3_IO_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, 6, BOOKE_PAGESZ_256K, 1), > +}; I'd personally get rid of the tabs above. Others may differ. > +int num_tlb_entries = ARRAY_SIZE(tlb_table); > diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c > index 0cc6e03..49d963d 100644 > --- a/cpu/mpc85xx/cpu.c > +++ b/cpu/mpc85xx/cpu.c > @@ -190,8 +190,10 @@ int checkcpu (void) > > int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) > { > -/* Everything after the first generation of PQ3 parts has RSTCR */ > -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ > +#if defined(CONFIG_BOARD_RESET_R) > + extern void board_reset_r(void); > + board_reset_r(); > +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ > defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) > unsigned long val, msr; > > @@ -207,6 +209,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) > val |= 0x70000000; > mtspr(DBCR0,val); > #else > + /* Everything after the first generation of PQ3 parts has RSTCR */ > volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); > out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ > udelay(100); This change is not board-specific, it should go in a separate patch. > diff --git a/include/configs/HWW_1U_1A.h b/include/configs/HWW_1U_1A.h > new file mode 100644 > index 0000000..9c0706f > --- /dev/null > +++ b/include/configs/HWW_1U_1A.h > @@ -0,0 +1,478 @@ > +/* > + * Copyright 2009-2010 eXMeritus, A Boeing Company > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +/* > + * HardwareWall HWW-1U-1A airborne unit configuration file > + */ > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +/************************************************************************ > + * High-level system configuration options * > + ************************************************************************/ > +/*#define DEBUG 1*/ > +#define CONFIG_BOOKE 1 /* Power/PowerPC Book-E */ > +#define CONFIG_E500 1 /* e500 (Power ISA v2.03 with SPE) */ > +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 family */ > +#define CONFIG_FSL_ELBC 1 /* FreeScale Enhanced LocalBus Cntlr */ > +#define CONFIG_FSL_LAW 1 /* FreeScale Local Access Window */ > +#define CONFIG_P2020 1 /* FreeScale P2020 */ > +#define CONFIG_HWW1U1A 1 /* eXMeritus HardwareWall HWW-1U-1A */ > +#define CONFIG_MP 1 /* Multiprocessing support */ > + > +#define CONFIG_L2_CACHE 1 /* L2 cache enabled */ > +#define CONFIG_BTB 1 /* Branch predition enabled */ > + > +#define CONFIG_PANIC_HANG 1 /* No board reset on panic */ > +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r() */ > +#define CONFIG_BOARD_RESET_R 1 /* Call board_reset_r() */ > + > +/* Allow the use of 36-bit physical addresses in "HWW_1U_1A_36BIT" mode */ > +#define CONFIG_ENABLE_36BIT_PHYS 1 > +#ifdef CONFIG_MK_36BIT > +# define CONFIG_PHYS_64BIT 1 > +# define CONFIG_ADDR_MAP 1 > +# define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */ > +#endif > + > +/* This is the U-Boot base address and size */ > +#define CONFIG_SYS_MONITOR_BASE 0xeff80000 > +#define CONFIG_SYS_MONITOR_LEN 0x00080000 > +#if defined(TEXT_BASE) && (TEXT_BASE != CONFIG_SYS_MONITOR_BASE) > +# error "TEXT_BASE != CONFIG_SYS_MONITOR_BASE" > +#endif > + > +/* Reserve plenty of RAM for malloc (we have 2GB+) */ > +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) > + > +/* This is where we map our L2 cache so we can use it as RAM */ > +#define CONFIG_SYS_INIT_RAM_LOCK 1 > +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 > +#define CONFIG_SYS_INIT_RAM_END 0x00004000 > + > +/* This is our temporary global data area just above the stack */ > +#define CONFIG_SYS_GBL_DATA_SIZE 128 > +#define CONFIG_SYS_GBL_DATA_OFFSET \ > + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) > + > +/* The stack grows down from the global data area */ > +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET > + > +/* Enable IRQs and watchdog with a 1000Hz system decrementer */ > +#define CONFIG_CMD_IRQ > +#define CONFIG_SYS_HZ 1000 > +#if 0 /* FIXME */ > +#define CONFIG_WATCHDOG 1 > + > +/* Enable Power-On-Self-Tests */ > +#define CONFIG_POST 1 > +#define CONFIG_CMD_DIAG > +#endif I'd get rid of this #if 0. > + > +/************************************************************************ > + * Clock crystal configuration: * > + * (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR) * > + * (2) CCB: Multiplier from SYS_CLK * > + * (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock) * > + ************************************************************************/ > +#undef CONFIG_CLOCKS_IN_MHZ You shouldn't need the undef above. > +#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/ > +#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/ > + > + > +/* > + * Memory map > + * > + * 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM > + * 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1 > + * 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused) > + * 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3 > + * 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH > + * 0xe800_0000 0xefff_ffff 128M Spansion FLASH > + * 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0) > + * 0xffe0_0000 0xffef_ffff 1M CCSR > + * 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller > + */ > + > +/* Virtual Memory Map */ > +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 > +#define CONFIG_SYS_SDRAM_BASE 0x00000000 > +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 > +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 > +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 > +#define CONFIG_SYS_FLASH_BASE 0xe0000000 > +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR @ reset */ > +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 > +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 > +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 > +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */ > + > +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ > +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ > +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ > +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ > +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ > +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ > + > +/* Physical Memory Map */ > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull > +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull > +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull > +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull > +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull > +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull > +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull > +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull > +#else > +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000ul > +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000ul > +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000ul > +#define CONFIG_SYS_FLASH_BASE_PHYS 0xe0000000ul > +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000ul > +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000ul > +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000ul > +#define CONFIG_SYS_CCSRBAR_PHYS 0xffe00000ul > +#endif > + > +/* Legacy code needs this */ > +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR > + > + > +/************************************************************************ > + * U-Boot Environment Image: The two sectors immediately below U-Boot * > + * form the U-Boot environment (regular and redundant) * > + ************************************************************************/ > +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (one flash sector) */ > +#define CONFIG_ENV_SIZE 0x02000 /* 8kB */ > +#define CONFIG_ENV_SIZE_REDUND 0x02000 /* 8kB */ > +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) > +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) > + > +#define CONFIG_ENV_IS_IN_FLASH 1 > +#define CONFIG_ENV_OVERWRITE 1 > + > + > +/************************************************************************ > + * Serial Console Configuration * > + ************************************************************************/ > +#define CONFIG_CONS_INDEX 1 > +#undef CONFIG_SERIAL_SOFTWARE_FIFO Remove undef if not needed. > +#define CONFIG_SYS_NS16550 > +#define CONFIG_SYS_NS16550_SERIAL > +#define CONFIG_SYS_NS16550_REG_SIZE 1 > +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) > + > +#define CONFIG_BAUDRATE 115200 > +#define CONFIG_SYS_BAUDRATE_TABLE \ > + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} Space before 115200. > + > +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) > +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) > + > +/* Echo back characters received during a serial download */ > +#define CONFIG_LOADS_ECHO 1 > + > +/* Allow a serial-download to temporarily change baud */ > +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 > + > + > +/************************************************************************ > + * PCI and PCI-Express Support * > + * Memory space is mapped 1-1, but I/O space must start from 0. * > + ************************************************************************/ > + > +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ > +#define CONFIG_PCI_PNP 1 /* Scan PCI busses */ > +#define CONFIG_CMD_PCI /* Enable the "pci" command */ > +#define CONFIG_FSL_PCI_INIT 1 /* Common FreeScale PCI initialization */ > +#define CONFIG_FSL_PCIE_RESET 1 /* We have PCI-E reset errata */ > +#define CONFIG_SYS_PCI_64BIT 1 /* PCI resources are 64-bit */ > +#define CONFIG_PCI_SCAN_SHOW 1 /* Display PCI scan during boot */ > + > +/* Enable all 3 PCI-E controllers */ > +#define CONFIG_PCIE1 1 > +#define CONFIG_PCIE2 1 > +#define CONFIG_PCIE3 1 > + > +/* PCI controller addresses */ > +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) > +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) > +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) > + > +/* PCI bus addresses */ > +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 > +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 > +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 > +#ifdef CONFIG_PHYS_64BIT > +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 > +#else > +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 > +#endif > + > + > +/************************************************************************ > + * I2C Bus Support and devices * > + ************************************************************************/ > + > +/* Generic FreeScale hardware I2C support */ > +#define CONFIG_HARD_I2C 1 > +#define CONFIG_FSL_I2C 1 > +#define CONFIG_CMD_I2C > +#define CONFIG_I2C_MULTI_BUS 1 > +#define CONFIG_SYS_I2C_OFFSET 0x3000 > +#define CONFIG_SYS_I2C2_OFFSET 0x3100 > + > +/* I2C bus configuration */ > +#define CONFIG_SYS_I2C_SPEED 400000 > +#define CONFIG_SYS_I2C_SLAVE 0x7F > +#define CONFIG_SYS_I2C_NOPROBES { \ > + { 0, 0x29 } \ > +} It'd be good to document why the devices are no probes. > +/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */ > +#define CONFIG_SYS_SPD_BUS_NUM 0 > +#define SPD_EEPROM_ADDRESS1 0x51 > +#if 0 > +#define CONFIG_CMD_EEPROM > +#endif Remove dead code. Same comment applies for future if 0s. > +/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */ > +#define CONFIG_CMD_DATE > +#define CONFIG_RTC_DS1337 > +#define CONFIG_SYS_RTC_BUS_NUM 0 > +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 > +/* Turn off RTC square-wave output to save battery */ > +#define CONFIG_SYS_RTC_DS1337_NOOSC 1 > + > + > +/************************************************************************ > + * FreeScale DDR2/3 SDRAM Controller * > + ************************************************************************/ > +#define CONFIG_FSL_DDR2 1 /* Our SDRAM slot is DDR2 */ > +#define CONFIG_DDR_ECC 1 /* Enable ECC by default */ > +#define CONFIG_DDR_SPD 1 /* Detect DDR config from SPD EEPROM */ > +#define CONFIG_SPD_EEPROM 1 /* ...why 2 config variables for this? */ > +#define CONFIG_VERY_BIG_RAM 1 /* Allow 2GB+ of RAM */ > +#undef CONFIG_FSL_DDR_INTERACTIVE > +#define CONFIG_CMD_SDRAM > + > +/* Standard P2020 DDR controller parameters */ > +#define CONFIG_NUM_DDR_CONTROLLERS 1 > +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 > +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 > + > +/* Make sure to tell the DDR controller to preinitialze all of RAM */ > +#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF > +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1 > + > +/* Enable the U-Boot "memory test" */ > +#define CONFIG_SYS_MEMTEST_START 0x00000000 > +#define CONFIG_SYS_MEMTEST_END 0x7fffffff > + > + > +/************************************************************************ > + * FLASH Memory Configuration (2x 128MB SPANSION FLASH) * > + ************************************************************************/ > +#define CONFIG_FLASH_CFI_DRIVER > +#define CONFIG_SYS_FLASH_CFI > +#define CONFIG_SYS_FLASH_EMPTY_INFO > +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 > + > +/* Flash banks (2x 128MB) */ > +#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull) > +#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull) > +#define CONFIG_SYS_MAX_FLASH_BANKS 2 > +#define CONFIG_SYS_MAX_FLASH_SECT 1024 > +#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS } > + > +/* Flash configuration registers */ > +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(FLASH0_PHYS) | BR_PS_16 | BR_V) > +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(FLASH1_PHYS) | BR_PS_16 | BR_V) > +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 > +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 There are ORx defines. They should be used to make it clear what the settings above are at a glance. > + > +/* Flash timeouts (in ms) */ > +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */ > +#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */ > + > +/* Quiet flash testing */ > +#define CONFIG_SYS_FLASH_QUIET_TEST 1 > + > +/* Don't bother checksumming the flash on boot */ > +#undef CONFIG_SYS_FLASH_CHECKSUM > + > +/* Make program/erase count down from 45/5 (9....8....7....) */ > +#define CONFIG_FLASH_SHOW_PROGRESS 45 > + > +#if 0 > +# define CONFIG_CMD_JFFS2 > +# define CONFIG_CMD_MTDPARTS > +#endif > + > + > +/************************************************************************ > + * Ethernet Device Support * > + ************************************************************************/ > +#define CONFIG_NET_MULTI 1 /* We have multiple devices */ > +#define CONFIG_MII 1 /* Enable MII PHY code */ > +#define CONFIG_MII_DEFAULT_TSEC 1 /* ??? */ > +#define CONFIG_PHY_GIGE 1 /* Support Gigabit PHYs */ > +#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */ > + > +#if 0 > +/* All of the ethernet interfaces we should have */ > +#define CONFIG_HAS_ETH0 > +#define CONFIG_HAS_ETH1 > +#define CONFIG_HAS_ETH2 > +#define CONFIG_HAS_ETH3 > +#define CONFIG_HAS_ETH4 > +#endif > + > +/* Turn on various helpful networking commands */ > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_MII > +#define CONFIG_CMD_NET > +#define CONFIG_CMD_PING > + > +/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */ > +#define CONFIG_TSEC_ENET 1 > +#define CONFIG_TSEC1 1 > +#define CONFIG_TSEC2 1 > +#define CONFIG_TSEC3 1 > +#define CONFIG_TSEC1_NAME "owt0" > +#define CONFIG_TSEC2_NAME "owt1" > +#define CONFIG_TSEC3_NAME "peer" > +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) > +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) > +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) > +#define TSEC1_PHYIDX 0 > +#define TSEC2_PHYIDX 0 > +#define TSEC3_PHYIDX 0 > +#define TSEC1_PHY_ADDR 2 > +#define TSEC2_PHY_ADDR 3 > +#define TSEC3_PHY_ADDR_CPUA 4 > +#define TSEC3_PHY_ADDR_CPUB 5 > +#define TSEC3_PHY_ADDR TSEC3_PHY_ADDR_CPUA > + > +/* PCI-E dual-port E1000 (external ethernet ports) */ > +#define CONFIG_E1000 1 > +#define CONFIG_E1000_FALLBACK_MAC { 0x00, 0x05, 0x93, 0x81, 0xff, 0xfe } The general U-Boot policy is to not set default MACs. > +/************************************************************************ > + * USB Thumbdrive Device Support * > + ************************************************************************/ > +#define CONFIG_USB_EHCI > +#define CONFIG_USB_EHCI_FSL > +#define CONFIG_USB_STORAGE > +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET > +#define CONFIG_CMD_USB > + > +/* Partition and Filesystem support */ > +#define CONFIG_DOS_PARTITION > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_FAT > + > + > +/************************************************************************ > + * Command line configuration. * > + ************************************************************************/ > +#define CONFIG_CMDLINE_EDITING 1 /* Enable command editing */ > +#define CONFIG_COMMAND_HISTORY 1 /* Enable command history */ > +#define CONFIG_AUTOCOMPLETE 1 /* Enable command completion */ > +#define CONFIG_SYS_LONGHELP 1 /* Enable detailed command help */ > +#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */ > +#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */ > +#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */ > +#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */ > +#define CONFIG_SYS_HUSH_PARSER 1 /* Enable a fancier shell */ > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Command-line continuation */ > + > +/* A little extra magic here for the prompt */ > +#define CONFIG_SYS_PROMPT hww1u1a_get_ps1() > +#ifndef __ASSEMBLY__ > +const char *hww1u1a_get_ps1(void); > +#endif > + > +/* Include a bunch of default commands we probably want */ > +#include <config_cmd_default.h> > + > +/* Other helpful shell-like commands */ > +#define CONFIG_MD5 > +#define CONFIG_SHA1 > +#define CONFIG_CMD_MD5SUM > +#define CONFIG_CMD_SHA1 > +#define CONFIG_CMD_ASKENV > +#define CONFIG_CMD_SETEXPR > + > + > +/************************************************************************ > + * Image manipulation and booting * > + ************************************************************************/ > + > +/* We use the OpenFirmware-esque "Flattened Device Tree" */ > +#define CONFIG_OF_LIBFDT 1 > +#define CONFIG_OF_BOARD_SETUP 1 > +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 > + > +/* > + * For booting Linux, the board info and command line data > + * have to be in the first 16 MB of memory, since this is > + * the maximum mapped by the Linux kernel during initialization. > + */ > +#define CONFIG_CMD_ELF > +#define CONFIG_SYS_BOOTMAPSZ 0x1000000 /* Maximum kernel memory map */ > +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* Maximum kernel size of 16MB */ > + > +#if 0 > +/* FIXME */ > +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ > +#define BOOTFLAG_WARM 0x02 /* Software reboot */ > +#endif > + > +/* This is the default address for commands with an optional address arg */ > +#define CONFIG_LOADADDR 100000 > +#define CONFIG_SYS_LOAD_ADDR 0x100000 > + > +#define CONFIG_BOOTDELAY 20 > +#define CONFIG_BOOTCOMMAND "echo Not yet flashed" > +#define CONFIG_BOOTARGS "" > +#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1" > + > +/* Extra environment parameters */ > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "preboot=setenv bootargs \"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \ > + "perf_mode=stable\0" \ Do you use perf_mode? If not, it should be removed. > + "memctl_intlv_ctl=2\0" \ I'd use the string instead of number to describe the interleaving, eg "bank". > + "flkernel=0xe8020000\0" \ > + "flinitramfs=0xe8800000\0" \ > + "fldevicetree=0xeff20000\0" \ > + "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \ > + "flboot=run preboot; run flbootm\0" Its preferred to use tabs instead of spaces to start new lines above. Best, Peter ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices 2010-09-03 4:00 ` Peter Tyser @ 2010-09-03 5:50 ` Kyle Moffett 2010-09-07 22:09 ` Peter Tyser 2010-09-07 21:21 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices Moffett, Kyle D 1 sibling, 1 reply; 19+ messages in thread From: Kyle Moffett @ 2010-09-03 5:50 UTC (permalink / raw) To: u-boot On Fri, Sep 3, 2010 at 00:00, Peter Tyser <ptyser@xes-inc.com> wrote: > Hi Kyle, Hi! Thanks for the great in-depth review, I really appreciate it! I've included my comments below, and I'll try to respin the patches here soon. I've dropped the second patch (the e1000e one) as it's apparently just a workaround for an as-yet-undiagnosed EEPROM issue with our boards. >> ?MAKEALL ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?2 + >> ?Makefile ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?4 + > > MAINTAINERS entry is missing. Fixed in my next patch, thanks! >> --- a/Makefile >> +++ b/Makefile >> @@ -2499,6 +2499,10 @@ P2020DS_36BIT_config \ >> ?P2020DS_config: ? ? ? ? ? ? ?unconfig >> ? ? ? @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale >> >> +HWW_1U_1A_36BIT_config \ >> +HWW_1U_1A_config: ? ?unconfig >> + ? ? @$(MKCONFIG) -t $(@:_config=) HWW_1U_1A ppc mpc85xx hww-1u-1a exmeritus >> + > > The new way to add a board is via boards.cfg. ?You shouldn't need to > modify this Makefile. Ok, I'll go poke around, thanks for letting me know! >> +++ b/board/exmeritus/hww-1u-1a/config.mk >> +# >> +# p2020ds board >> +# > > P2020ds? Oops, missed a few. I'll go back through and fix the remaining p2020ds references. >> +++ b/board/exmeritus/hww-1u-1a/ddr.c >> +/* XXX: these values need to be checked for all interleaving modes. ?*/ >> +/* XXX: No reliable dual-rank 800 MHz setting has been found. ?It may >> + * ? ? ?seem reliable, but errors will appear when memory intensive >> + * ? ? ?program is run. */ >> +/* XXX: Single rank at 800 MHz is OK. ?*/ > > These comments look like the p2020ds comments. ?Please remove/update > them if they don't apply to your board. Yep, sorry. I'd actually fixed this in a different git tree but lost the change when doing a rebase. >> +const board_specific_parameters_t board_specific_parameters[][20] = { >> + ? ? { >> + ? ? /* ? ? ?memory controller 0 ? ? ? ? ? ? ? ? ? ? */ >> + ? ? /* ? ? ? ?lo| ?hi| ?num| ?clk| cpo|wrdata|2T ? ?*/ >> + ? ? /* ? ? ? mhz| mhz|ranks|adjst| ? ?| delay| ? ? ?*/ >> +#if 0 >> + ? ? ? ? ? ? { ?0, 333, ? ?2, ? ?6, ? 7, ? ?3, ?0}, >> + ? ? ? ? ? ? {334, 400, ? ?2, ? ?6, ? 9, ? ?3, ?0}, >> + ? ? ? ? ? ? {401, 549, ? ?2, ? ?6, ?11, ? ?3, ?0}, >> + ? ? ? ? ? ? {550, 680, ? ?2, ? ?1, ?10, ? ?5, ?0}, >> + ? ? ? ? ? ? {681, 850, ? ?2, ? ?1, ?12, ? ?5, ?1}, >> + ? ? ? ? ? ? { ?0, 333, ? ?1, ? ?6, ? 7, ? ?3, ?0}, >> + ? ? ? ? ? ? {334, 400, ? ?1, ? ?6, ? 9, ? ?3, ?0}, >> + ? ? ? ? ? ? {401, 549, ? ?1, ? ?6, ?11, ? ?3, ?0}, >> + ? ? ? ? ? ? {550, 680, ? ?1, ? ?1, ?10, ? ?5, ?0}, >> + ? ? ? ? ? ? {681, 850, ? ?1, ? ?1, ?12, ? ?5, ?0} >> +#else >> + ? ? ? ? ? ? { ?0,1000, ? ?2, ? ?4, ? 4, ? ?2, ?0}, >> + ? ? ? ? ? ? { ?0,1000, ? ?1, ? ?4, ? 4, ? ?2, ?0}, >> +#endif >> + ? ? }, >> +}; > > I'd remove the #if 0 above. ?Dead code is bad. Same as above, this part came back during a rebase. Will adjust, thanks! >> diff --git a/board/exmeritus/hww-1u-1a/gpios.h b/board/exmeritus/hww-1u-1a/gpios.h >> +static inline void hww1u1a_gpio_set(unsigned int mask, >> + ? ? ? ? ? ? unsigned int dir, unsigned int val) >> +{ >> + ? ? volatile ccsr_gpio_t *gpio; >> + >> + ? ? /* First mask off the unwanted parts of "dir" and "val" */ >> + ? ? dir &= mask; >> + ? ? val &= mask; >> + >> + ? ? /* Now read in the values we're supposed to preserve */ >> + ? ? gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); >> + ? ? dir |= (in_be32(&gpio->gpdir) & ~mask); >> + ? ? val |= (in_be32(&gpio->gpdat) & ~mask); >> + >> + ? ? /* Now write out the new values, writing the direction first */ >> + ? ? out_be32(&gpio->gpdir, dir); >> + ? ? asm("sync; isync":::"memory"); >> + ? ? out_be32(&gpio->gpdat, val); >> +} >> + >> +static inline void hww1u1a_gpio_set_in(unsigned int gpios) >> +{ >> + ? ? hww1u1a_gpio_set(gpios, 0x00000000, 0x00000000); >> +} >> + >> +static inline void hww1u1a_gpio_set_low(unsigned int gpios) >> +{ >> + ? ? hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0x00000000); >> +} >> + >> +static inline void hww1u1a_gpio_set_high(unsigned int gpios) >> +{ >> + ? ? hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF); >> +} >> + >> +static inline unsigned int hww1u1a_gpio_get(unsigned int mask) >> +{ >> + ? ? volatile ccsr_gpio_t *gpio; >> + ? ? unsigned int ret; >> + >> + ? ? /* Read the requested values */ >> + ? ? gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); >> + ? ? ret = mask & in_be32(&gpio->gpdat); >> + >> + ? ? return ret; >> +} > > The GPIO functions above aren't hww1u1a specific. ?What about adding > generic 85xx GPIO functions so others can use them too? I can do that. Do you have any particular place you recommend I put them? >> +static inline unsigned int hww1u1a_is_cpu_a(void) >> +{ >> + ? ? return ?!hww1u1a_gpio_get(GPIO_CPU_ID); >> +} >> + >> +static inline unsigned int hww1u1a_is_cpu_b(void) >> +{ >> + ? ? return !!hww1u1a_gpio_get(GPIO_CPU_ID); >> +} >> + > > With only 2 CPUs do you need both the functions above? ?Eg below you use the logic: > if (hww1u1a_is_cpu_a()) > ? stuff > else > ? stuff > > I don't see hww1u1a_is_cpu_b() being used anywhere. Hmm... yeah, I guess I did remove the only user of hww1u1a_is_cpu_b(). Since it's a static inline (and so consumes no space in the binary if unused) I'm sort of tempted to keep it just for symmetry but it does strike me as redundant. I guess I'll get rid of it. >> +++ b/board/exmeritus/hww-1u-1a/hww-1u-1a.c >> + ? ? /* These GPIOs are common */ >> + ? ? gpio_in ? |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT; >> + ? ? gpio_low ?|= GPIO_RS422_RE; >> + ? ? gpio_high |= GPIO_RS422_DE; >> + >> + ? ? /* Ok, now go ahead and program all of those in one go */ >> + ? ? hww1u1a_gpio_set( ? ? ? gpio_high|gpio_low|gpio_in, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? gpio_high|gpio_low, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? gpio_high); > > The tab above should be removed. It looked easier for me to read when aligned like that, but if it's contrary to coding-style I'll fix it. >> +/* Create a prompt-like string: "uboot at HOSTNAME% " */ >> +#define PROMPT_PREFIX "uboot at exm" >> +#define PROMPT_SUFFIX "% " >> + >> +/* This function returns a PS1 prompt based on the serial number */ >> +static char *hww1u1a_prompt = NULL; >> +const char *hww1u1a_get_ps1(void) >> +{ >> + ? ? unsigned long len, i, j; >> + ? ? const char *serialnr; >> + >> + ? ? /* If our prompt was already set, just use that */ >> + ? ? if (hww1u1a_prompt) >> + ? ? ? ? ? ? return hww1u1a_prompt; >> + >> + ? ? /* Use our serial number if present, otherwise "UNPROGRAMMED-[AB]" */ >> + ? ? serialnr = getenv("serial#"); >> + ? ? if (!serialnr || !serialnr[0]) { >> + ? ? ? ? ? ? if (hww1u1a_is_cpu_a()) >> + ? ? ? ? ? ? ? ? ? ? serialnr = "999999-XA"; >> + ? ? ? ? ? ? else >> + ? ? ? ? ? ? ? ? ? ? serialnr = "999999-XB"; >> + ? ? } >> + >> + ? ? /* >> + ? ? ?* We will turn the serial number into a hostname by: >> + ? ? ?* ? (A) Delete all non-alphanumerics. >> + ? ? ?* ? (B) Lowercase all letters >> + ? ? ?* ? (C) Prefix "exm" >> + ? ? ?*/ >> + ? ? for (i = 0, len = 0; serialnr[i]; i++) { >> + ? ? ? ? ? ? if ('0' <= serialnr[i] && serialnr[i] <= '9') >> + ? ? ? ? ? ? ? ? ? ? len++; >> + ? ? ? ? ? ? else if ('a' <= serialnr[i] && serialnr[i] <= 'z') >> + ? ? ? ? ? ? ? ? ? ? len++; >> + ? ? ? ? ? ? else if ('A' <= serialnr[i] && serialnr[i] <= 'Z') >> + ? ? ? ? ? ? ? ? ? ? len++; >> + ? ? } > > There are utility functions in include/linux/ctype.h that do the above > checks. ?This, and the similar chunk of code below seems like a lot of > effort to get rid of non digits/alpha chars. ?Is there a reason to not > just assume the serial number variable is valid, or include all chars in > the prompt? This is partly compensating for some changes in serial-number format between various generations of prototypes, making them all have the same-format prompt. The rest of it is just me being an overly-defensive programmer. I'll rewrite it to use ctype.h, but the character fiddling is a relatively small amount of code and I'd like to keep it around. >> +int board_eth_init(bd_t *bis) >> +{ >> + ? ? struct tsec_info_struct tsec_info[4]; >> + ? ? volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); >> + >> + ? ? SET_STD_TSEC_INFO(tsec_info[0], 1); >> + ? ? SET_STD_TSEC_INFO(tsec_info[1], 2); >> + ? ? SET_STD_TSEC_INFO(tsec_info[2], 3); >> + ? ? if (pgpio->gpdat & GPIO_CPU_ID) > > Is the above check the same as the hww1u1a_is_cpu_a() function > previously added? Oops, yes it is, will fix. That reminds me of one other question, though. Several variables are different between the CPU A and the CPU B on the board but maintaining 2 nearly-identical device trees is kind of a pain. Is there any good way to manage that? Should I try to poke the device tree file during boot, or is there some kind of macro language I can use in the dts file? (EG: "#ifdef CPU_A", etc) >> +/* We don't have any really usable POST memory, so just fake it */ >> +unsigned long post_word_load (void) >> +{ >> + ? ? return 0l; >> +} >> + >> +void post_word_store (unsigned long val) >> +{ >> + ? ? return; >> +} > > Does this work with POSTs? ?I had thought you'd need to be able to > read/write the post word, even if it wasn't saved across reboots. ?It > should be in a #ifdef CONFIG_POST if you do keep it around. I copied this from another board implementation, but I never got around to testing CONFIG_POST properly. I'll delete this from the current patch and put it back on my TODO list. >> +static inline int pca9554_set_low(u8 gpio) >> +{ >> + ? ? return pca9554_setmask(PCA9554_DATA_OUT, 0x00, (1U << gpio)); >> +} >> + >> +static inline int pca9554_set_high(u8 gpio) >> +{ >> + ? ? return pca9554_setmask(PCA9554_DATA_OUT, 0xff, (1U << gpio)); >> +} >> + >> +static inline int pca9554_set_output(u8 gpio) >> +{ >> + ? ? return pca9554_setmask(PCA9554_IS_INPUT, 0x00, (1U << gpio)); >> +} >> + >> +static inline int pca9554_set_input(u8 gpio) >> +{ >> + ? ? return pca9554_setmask(PCA9554_DATA_OUT, 0xff, (1U << gpio)); >> +} > > These look very similar to the pca953x driver. ?It'd be worth > investigate using it. Heh, that's new... there wasn't one when I first started this board port. I'll go poke around, thanks! >> + ? ? /* *I*G* - PCI memory */ >> + ? ? SET_TLB_ENTRY(1, ? ? ? ?CONFIG_SYS_PCIE3_MEM_VIRT, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? CONFIG_SYS_PCIE3_MEM_PHYS, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0, 3, BOOKE_PAGESZ_1G, 1), > > The LAW is only 512 MB. > >> + ? ? SET_TLB_ENTRY(1, ? ? ? ?CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0, 4, BOOKE_PAGESZ_256M, 1), > > Is there a reason you don't use CONFIG_SYS_PCIE2_MEM_* here? ?And the > LAW is 512MB above. I think I just copied these TLB entries unmodified from the P2020DS eval board... I'll go recheck, but if these are wrong then the p2020ds board is probably wrong too. >> + ? ? SET_TLB_ENTRY(1, ? ? ? ?CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0, 5, BOOKE_PAGESZ_256M, 1), >> + >> + ? ? /* *I*G* - PCI I/O */ >> + ? ? SET_TLB_ENTRY(1, ? ? ? ?CONFIG_SYS_PCIE3_IO_VIRT, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? CONFIG_SYS_PCIE3_IO_PHYS, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0, 6, BOOKE_PAGESZ_256K, 1), >> +}; > > I'd personally get rid of the tabs above. ?Others may differ. I'd prefer to keep them if possible. >> +int num_tlb_entries = ARRAY_SIZE(tlb_table); >> diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c >> index 0cc6e03..49d963d 100644 >> --- a/cpu/mpc85xx/cpu.c >> +++ b/cpu/mpc85xx/cpu.c >> @@ -190,8 +190,10 @@ int checkcpu (void) >> >> ?int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) >> ?{ >> -/* Everything after the first generation of PQ3 parts has RSTCR */ >> -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ >> +#if defined(CONFIG_BOARD_RESET_R) >> + ? ? extern void board_reset_r(void); >> + ? ? board_reset_r(); >> +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ >> ? ? ?defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) >> ? ? ? unsigned long val, msr; >> >> @@ -207,6 +209,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) >> ? ? ? val |= 0x70000000; >> ? ? ? mtspr(DBCR0,val); >> ?#else >> + ? ? /* Everything after the first generation of PQ3 parts has RSTCR */ >> ? ? ? volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); >> ? ? ? out_be32(&gur->rstcr, 0x2); ? ? /* HRESET_REQ */ >> ? ? ? udelay(100); > > This change is not board-specific, it should go in a separate patch. Ah, whoops! I forgot about this one; I'll go break it out. >> +/* Enable IRQs and watchdog with a 1000Hz system decrementer */ >> +#define CONFIG_CMD_IRQ >> +#define CONFIG_SYS_HZ 1000 >> +#if 0 /* FIXME */ >> +#define CONFIG_WATCHDOG 1 >> + >> +/* Enable Power-On-Self-Tests */ >> +#define CONFIG_POST 1 >> +#define CONFIG_CMD_DIAG >> +#endif > > I'd get rid of this #if 0. Yeah, more things to pull out of this patch and put back on the TODO list, thanks! >> + >> +/************************************************************************ >> + * Clock crystal configuration: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?* >> + * ?(1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR) ? ? ? ? ? ? ? ? ? ? ? ?* >> + * ?(2) CCB: Multiplier from SYS_CLK ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * >> + * ?(3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock) ? ? ? ? * >> + ************************************************************************/ >> +#undef CONFIG_CLOCKS_IN_MHZ > > You shouldn't need the undef above. It was copied from P2020DS, I think. I'll go double-check. >> +/* Physical Memory Map */ >> +#ifdef CONFIG_PHYS_64BIT >> +#define CONFIG_SYS_PCIE3_MEM_PHYS ?0xc00000000ull >> +#define CONFIG_SYS_PCIE2_MEM_PHYS ?0xc20000000ull >> +#define CONFIG_SYS_PCIE1_MEM_PHYS ?0xc40000000ull >> +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull >> +#define CONFIG_SYS_PCIE3_IO_PHYS ? 0xfffc00000ull >> +#define CONFIG_SYS_PCIE2_IO_PHYS ? 0xfffc10000ull >> +#define CONFIG_SYS_PCIE1_IO_PHYS ? 0xfffc20000ull >> +#define CONFIG_SYS_CCSRBAR_PHYS ? ?0xfffe00000ull >> +#else >> +#define CONFIG_SYS_PCIE3_MEM_PHYS ?0x80000000ul >> +#define CONFIG_SYS_PCIE2_MEM_PHYS ?0xa0000000ul >> +#define CONFIG_SYS_PCIE1_MEM_PHYS ?0xc0000000ul >> +#define CONFIG_SYS_FLASH_BASE_PHYS 0xe0000000ul >> +#define CONFIG_SYS_PCIE3_IO_PHYS ? 0xffc00000ul >> +#define CONFIG_SYS_PCIE2_IO_PHYS ? 0xffc10000ul >> +#define CONFIG_SYS_PCIE1_IO_PHYS ? 0xffc20000ul >> +#define CONFIG_SYS_CCSRBAR_PHYS ? ?0xffe00000ul >> +#endif One extra question about the physical memory mapping. I'd like to support both 32-bit-phys and 36-bit-phys kernels from a single device-tree and U-boot image by using a non-linear memory mapping, specifically, something like this: 0x000000000 - 0x07fffffff: First 2GB of DDR memory 0x080000000 - 0x0ffffffff: PCI and device IO windows 0x100000000 - 0x17fffffff: Remaining 2GB of DDR memory (only accessible from 36-bit-phys kernel) It looks like U-boot doesn't support a setup like this right now, any idea what kind of changes would be involved to make that happen? >> +/************************************************************************ >> + * Serial Console Configuration ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?* >> + ************************************************************************/ >> +#define CONFIG_CONS_INDEX ? ?1 >> +#undef ? ? ? CONFIG_SERIAL_SOFTWARE_FIFO > > Remove undef if not needed. Ok, thanks. >> +#define CONFIG_SYS_NS16550 >> +#define CONFIG_SYS_NS16550_SERIAL >> +#define CONFIG_SYS_NS16550_REG_SIZE ?1 >> +#define CONFIG_SYS_NS16550_CLK ? ? ? ? ? ? ? get_bus_freq(0) >> + >> +#define CONFIG_BAUDRATE ? ? ?115200 >> +#define CONFIG_SYS_BAUDRATE_TABLE ? ?\ >> + ? ? {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} > > Space before 115200. Fixed! >> +/* I2C bus configuration */ >> +#define CONFIG_SYS_I2C_SPEED 400000 >> +#define CONFIG_SYS_I2C_SLAVE 0x7F >> +#define CONFIG_SYS_I2C_NOPROBES ? ? ?{ ? ? ? \ >> + ? ? { 0, 0x29 } ? ? ? ? ? ? ? ? ? ? \ >> +} > > It'd be good to document why the devices are no probes. Dunno, that was copied from an identical undocumented chunk of the P2020DS board. It's entirely reasonable that it would not apply to our board. I'll go poke at it a bit. >> +/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */ >> +#define CONFIG_SYS_SPD_BUS_NUM 0 >> +#define SPD_EEPROM_ADDRESS1 0x51 >> +#if 0 >> +#define CONFIG_CMD_EEPROM >> +#endif > > Remove dead code. ?Same comment applies for future if 0s. Same as above, things to pull out and put back on TODO list. >> +/* Flash configuration registers */ >> +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(FLASH0_PHYS) | BR_PS_16 | BR_V) >> +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(FLASH1_PHYS) | BR_PS_16 | BR_V) >> +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 >> +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 > > There are ORx defines. ?They should be used to make it clear what the > settings above are at a glance. Ok, I'll have to go look up what those bits mean since I copied them unmodified from the P2020DS board. >> +/* PCI-E dual-port E1000 (external ethernet ports) */ >> +#define CONFIG_E1000 1 >> +#define CONFIG_E1000_FALLBACK_MAC { 0x00, 0x05, 0x93, 0x81, 0xff, 0xfe } > > The general U-Boot policy is to not set default MACs. The e1000e chips on our board need their EEPROMs to be programmed by software during provisioning. At one point I think we needed this in order for the programming to work successfully, but it's possible that no longer applies; I'll go verify it. Regardless, this particular MAC address is one I selected from our suballocation specifically for this purpose. >> +/* Extra environment parameters */ >> +#define CONFIG_EXTRA_ENV_SETTINGS ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\ >> + "preboot=setenv bootargs \"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" ? ? ? \ >> + "perf_mode=stable\0" ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\ > > Do you use perf_mode? ?If not, it should be removed. Not sure, but probably not. I vaguely recall that some piece of generic code was looking at it, but that may just be a leftover from the P2020DS board. >> + "memctl_intlv_ctl=2\0" ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\ > > I'd use the string instead of number to describe the interleaving, eg > "bank". This was copied from P2020DS, but I'll fix. >> + "flkernel=0xe8020000\0" ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \ >> + "flinitramfs=0xe8800000\0" ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\ >> + "fldevicetree=0xeff20000\0" ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \ >> + "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" ? ? ? ? ? ? ? ?\ >> + "flboot=run preboot; run flbootm\0" > > Its preferred to use tabs instead of spaces to start new lines above. Ok. I was mainly trying to make it all fit into my 80 chars terminal :-D. Thanks again for a great review! I'll try to have updated patches out shortly! Cheers, Kyle Moffett ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices 2010-09-03 5:50 ` Kyle Moffett @ 2010-09-07 22:09 ` Peter Tyser 2010-09-07 22:50 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritusHWW-1U-1A devices Moffett, Kyle D 0 siblings, 1 reply; 19+ messages in thread From: Peter Tyser @ 2010-09-07 22:09 UTC (permalink / raw) To: u-boot <snip> > >> diff --git a/board/exmeritus/hww-1u-1a/gpios.h b/board/exmeritus/hww-1u-1a/gpios.h > >> +static inline void hww1u1a_gpio_set(unsigned int mask, > >> + unsigned int dir, unsigned int val) > >> +{ > >> + volatile ccsr_gpio_t *gpio; > >> + > >> + /* First mask off the unwanted parts of "dir" and "val" */ > >> + dir &= mask; > >> + val &= mask; > >> + > >> + /* Now read in the values we're supposed to preserve */ > >> + gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); > >> + dir |= (in_be32(&gpio->gpdir) & ~mask); > >> + val |= (in_be32(&gpio->gpdat) & ~mask); > >> + > >> + /* Now write out the new values, writing the direction first */ > >> + out_be32(&gpio->gpdir, dir); > >> + asm("sync; isync":::"memory"); > >> + out_be32(&gpio->gpdat, val); > >> +} > >> + > >> +static inline void hww1u1a_gpio_set_in(unsigned int gpios) > >> +{ > >> + hww1u1a_gpio_set(gpios, 0x00000000, 0x00000000); > >> +} > >> + > >> +static inline void hww1u1a_gpio_set_low(unsigned int gpios) > >> +{ > >> + hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0x00000000); > >> +} > >> + > >> +static inline void hww1u1a_gpio_set_high(unsigned int gpios) > >> +{ > >> + hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF); > >> +} > >> + > >> +static inline unsigned int hww1u1a_gpio_get(unsigned int mask) > >> +{ > >> + volatile ccsr_gpio_t *gpio; > >> + unsigned int ret; > >> + > >> + /* Read the requested values */ > >> + gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); > >> + ret = mask & in_be32(&gpio->gpdat); > >> + > >> + return ret; > >> +} > > > > The GPIO functions above aren't hww1u1a specific. What about adding > > generic 85xx GPIO functions so others can use them too? > > I can do that. Do you have any particular place you recommend I put them? The 2 places that jump to mind are drivers/gpio, or arch/powerpc/cpu/mpc8xxx. My personal preference would be drivers/gpio. <snip> > >> +++ b/board/exmeritus/hww-1u-1a/hww-1u-1a.c > >> + /* These GPIOs are common */ > >> + gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT; > >> + gpio_low |= GPIO_RS422_RE; > >> + gpio_high |= GPIO_RS422_DE; > >> + > >> + /* Ok, now go ahead and program all of those in one go */ > >> + hww1u1a_gpio_set( gpio_high|gpio_low|gpio_in, > >> + gpio_high|gpio_low, > >> + gpio_high); > > > > The tab above should be removed. > > It looked easier for me to read when aligned like that, but if it's > contrary to coding-style I'll fix it. I believe its contrary to normal coding style, you can read the details at http://www.denx.de/wiki/U-Boot/CodingStyle. Probably not a huge deal either way. > > >> +int board_eth_init(bd_t *bis) > >> +{ > >> + struct tsec_info_struct tsec_info[4]; > >> + volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); > >> + > >> + SET_STD_TSEC_INFO(tsec_info[0], 1); > >> + SET_STD_TSEC_INFO(tsec_info[1], 2); > >> + SET_STD_TSEC_INFO(tsec_info[2], 3); > >> + if (pgpio->gpdat & GPIO_CPU_ID) > > > > Is the above check the same as the hww1u1a_is_cpu_a() function > > previously added? > > Oops, yes it is, will fix. That reminds me of one other question, > though. Several variables are different between the CPU A and the CPU > B on the board but maintaining 2 nearly-identical device trees is kind > of a pain. Is there any good way to manage that? Should I try to > poke the device tree file during boot, or is there some kind of macro > language I can use in the dts file? (EG: "#ifdef CPU_A", etc) There isn't a macro language in the dts file that you can use. Its hard to say if you should tweak the dtb in U-Boot. People's opinions vary: http://www.mail-archive.com/u-boot at lists.denx.de/msg36029.html I'd give modifying the dtb in U-Boot a try, and people will let you know if its outside of the scope of U-Boot's responsibility. <snip> > >> +/* Flash configuration registers */ > >> +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(FLASH0_PHYS) | BR_PS_16 | BR_V) > >> +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(FLASH1_PHYS) | BR_PS_16 | BR_V) > >> +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 > >> +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 > > > > There are ORx defines. They should be used to make it clear what the > > settings above are at a glance. > > Ok, I'll have to go look up what those bits mean since I copied them > unmodified from the P2020DS board. If you are using different localbus devices and/or board clocking from the p2020ds, it'd be good to review the settings as they likely could be improved for your specific setup. > > >> +/* PCI-E dual-port E1000 (external ethernet ports) */ > >> +#define CONFIG_E1000 1 > >> +#define CONFIG_E1000_FALLBACK_MAC { 0x00, 0x05, 0x93, 0x81, 0xff, 0xfe } > > > > The general U-Boot policy is to not set default MACs. > > The e1000e chips on our board need their EEPROMs to be programmed by > software during provisioning. At one point I think we needed this in > order for the programming to work successfully, but it's possible that > no longer applies; I'll go verify it. Regardless, this particular MAC > address is one I selected from our suballocation specifically for this > purpose. The general philosophy is that U-Boot shouldn't include default MAC addresses as inevitably at some point you'll have multiple boards on the network with identical MACs, or customers will corrupt their EEPROM and fall back to the default MAC, etc. Best, Peter ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritusHWW-1U-1A devices 2010-09-07 22:09 ` Peter Tyser @ 2010-09-07 22:50 ` Moffett, Kyle D 2010-09-08 3:43 ` Peter Tyser 0 siblings, 1 reply; 19+ messages in thread From: Moffett, Kyle D @ 2010-09-07 22:50 UTC (permalink / raw) To: u-boot On Sep 07, 2010, at 18:09, Peter Tyser wrote: >>> The GPIO functions above aren't hww1u1a specific. What about adding >>> generic 85xx GPIO functions so others can use them too? >> >> I can do that. Do you have any particular place you recommend I put them? > > The 2 places that jump to mind are drivers/gpio, or > arch/powerpc/cpu/mpc8xxx. My personal preference would be drivers/gpio. Hmm, given that they all seem to inline smaller than a function call would be, I've put them as "static inline" functions in: arch/powerpc/include/asm/mpc85xx_gpio.h Is that OK? >>> Is the above check the same as the hww1u1a_is_cpu_a() function >>> previously added? >> >> Oops, yes it is, will fix. That reminds me of one other question, >> though. Several variables are different between the CPU A and the CPU >> B on the board but maintaining 2 nearly-identical device trees is kind >> of a pain. Is there any good way to manage that? Should I try to >> poke the device tree file during boot, or is there some kind of macro >> language I can use in the dts file? (EG: "#ifdef CPU_A", etc) > > There isn't a macro language in the dts file that you can use. Its hard > to say if you should tweak the dtb in U-Boot. People's opinions vary: > http://www.mail-archive.com/u-boot at lists.denx.de/msg36029.html > > I'd give modifying the dtb in U-Boot a try, and people will let you know > if its outside of the scope of U-Boot's responsibility. Hmm, seems like a lot of extra work to try fiddling with the DTB for very little gain. I think at this point I'll just implement an "is_cpu_a" command and use it from a hush script something like this: if is_cpu_a; then bootm ${flkernel} ${flinitramfs} ${fldevicetree_cpua} else bootm ${flkernel} ${flinitramfs} ${fldevicetree_cpub} fi Does that seem OK? >>>> +/* Flash configuration registers */ >>>> +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(FLASH0_PHYS) | BR_PS_16 | BR_V) >>>> +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(FLASH1_PHYS) | BR_PS_16 | BR_V) >>>> +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 >>>> +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 >>> >>> There are ORx defines. They should be used to make it clear what the >>> settings above are at a glance. >> >> Ok, I'll have to go look up what those bits mean since I copied them >> unmodified from the P2020DS board. > > If you are using different localbus devices and/or board clocking from > the p2020ds, it'd be good to review the settings as they likely could be > improved for your specific setup. The default settings are the most pessimistic configuration parameters for the onboard FLASH. As it is plenty fast for our purposes right now, I'm disinclined to risk breaking this particular piece of code right now. I did rewrite it so it doesn't use magic numbers anymore, but I'm not sure it makes it much more readable :-D. >>>> +/* PCI-E dual-port E1000 (external ethernet ports) */ >>>> +#define CONFIG_E1000 1 >>>> +#define CONFIG_E1000_FALLBACK_MAC { 0x00, 0x05, 0x93, 0x81, 0xff, 0xfe } >>> >>> The general U-Boot policy is to not set default MACs. >> >> The e1000e chips on our board need their EEPROMs to be programmed by >> software during provisioning. At one point I think we needed this in >> order for the programming to work successfully, but it's possible that >> no longer applies; I'll go verify it. Regardless, this particular MAC >> address is one I selected from our suballocation specifically for this >> purpose. > > The general philosophy is that U-Boot shouldn't include default MAC > addresses as inevitably at some point you'll have multiple boards on the > network with identical MACs, or customers will corrupt their EEPROM and > fall back to the default MAC, etc. Well, due to the design of the E1000E hardware, a corrupted EEPROM (as opposed to an unprogrammed EEPROM) usually just causes the whole E1000E chip to drop off the PCI bus... I'm having other functional annoyances with our programming process right now, so I'll drop this part for now and revisit it later once I've got those isolated. Cheers, Kyle Moffett ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritusHWW-1U-1A devices 2010-09-07 22:50 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritusHWW-1U-1A devices Moffett, Kyle D @ 2010-09-08 3:43 ` Peter Tyser 0 siblings, 0 replies; 19+ messages in thread From: Peter Tyser @ 2010-09-08 3:43 UTC (permalink / raw) To: u-boot On Tue, 2010-09-07 at 17:50 -0500, Moffett, Kyle D wrote: > On Sep 07, 2010, at 18:09, Peter Tyser wrote: > >>> The GPIO functions above aren't hww1u1a specific. What about adding > >>> generic 85xx GPIO functions so others can use them too? > >> > >> I can do that. Do you have any particular place you recommend I put them? > > > > The 2 places that jump to mind are drivers/gpio, or > > arch/powerpc/cpu/mpc8xxx. My personal preference would be drivers/gpio. > > Hmm, given that they all seem to inline smaller than a function call would be, I've put them as "static inline" functions in: > arch/powerpc/include/asm/mpc85xx_gpio.h > > Is that OK? I'd recommend throwing it in a C file and using the "standard" gpiolib function names. That way others can easily use it to tie into U-Boot's LED, NAND, I2C, etc drivers. Eg I'd use it for LEDs immediately on a number of my company's boards if it existed. board/altera/nios2-generic/gpio.c is a simple example, arch/blackfin/cpu/gpio.c is a bit more complicated but featureful. > >>> Is the above check the same as the hww1u1a_is_cpu_a() function > >>> previously added? > >> > >> Oops, yes it is, will fix. That reminds me of one other question, > >> though. Several variables are different between the CPU A and the CPU > >> B on the board but maintaining 2 nearly-identical device trees is kind > >> of a pain. Is there any good way to manage that? Should I try to > >> poke the device tree file during boot, or is there some kind of macro > >> language I can use in the dts file? (EG: "#ifdef CPU_A", etc) > > > > There isn't a macro language in the dts file that you can use. Its hard > > to say if you should tweak the dtb in U-Boot. People's opinions vary: > > http://www.mail-archive.com/u-boot at lists.denx.de/msg36029.html > > > > I'd give modifying the dtb in U-Boot a try, and people will let you know > > if its outside of the scope of U-Boot's responsibility. > > Hmm, seems like a lot of extra work to try fiddling with the DTB for very little gain. If done right its not much to tweak the dtb in code for what its worth. > I think at this point I'll just implement an "is_cpu_a" command and use it from a hush script something like this: > > if is_cpu_a; then > bootm ${flkernel} ${flinitramfs} ${fldevicetree_cpua} > else > bootm ${flkernel} ${flinitramfs} ${fldevicetree_cpub} > fi > > Does that seem OK? Sounds good to me. You could always try adding dtb tweaking to U-Boot at a later date if you got sick of maintaining 2 device trees. Best. Peter ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices 2010-09-03 4:00 ` Peter Tyser 2010-09-03 5:50 ` Kyle Moffett @ 2010-09-07 21:21 ` Moffett, Kyle D 2010-09-07 21:40 ` Peter Tyser 1 sibling, 1 reply; 19+ messages in thread From: Moffett, Kyle D @ 2010-09-07 21:21 UTC (permalink / raw) To: u-boot Peter, I've got one more followup question as I work through these updates: On Sep 03, 2010, at 00:00, Peter Tyser wrote: >> --- a/Makefile >> +++ b/Makefile >> @@ -2499,6 +2499,10 @@ P2020DS_36BIT_config \ >> P2020DS_config: unconfig >> @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale >> >> +HWW_1U_1A_36BIT_config \ >> +HWW_1U_1A_config: unconfig >> + @$(MKCONFIG) -t $(@:_config=) HWW_1U_1A ppc mpc85xx hww-1u-1a exmeritus >> + > > The new way to add a board is via boards.cfg. You shouldn't need to > modify this Makefile. Is there some appropriate documentation on how boards.cfg is supposed to work? The latest u-boot.git still seems to have the P2020DS lines that I referenced in "Makefile", and it has no references at all to "P2020DS" in the "boards.cfg" file. Cheers, Kyle Moffett ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices 2010-09-07 21:21 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices Moffett, Kyle D @ 2010-09-07 21:40 ` Peter Tyser 2010-09-07 21:59 ` Wolfgang Denk 2010-09-07 22:21 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritusHWW-1U-1A devices Moffett, Kyle D 0 siblings, 2 replies; 19+ messages in thread From: Peter Tyser @ 2010-09-07 21:40 UTC (permalink / raw) To: u-boot Hi Kyle, > On Sep 03, 2010, at 00:00, Peter Tyser wrote: > >> --- a/Makefile > >> +++ b/Makefile > >> @@ -2499,6 +2499,10 @@ P2020DS_36BIT_config \ > >> P2020DS_config: unconfig > >> @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale > >> > >> +HWW_1U_1A_36BIT_config \ > >> +HWW_1U_1A_config: unconfig > >> + @$(MKCONFIG) -t $(@:_config=) HWW_1U_1A ppc mpc85xx hww-1u-1a exmeritus > >> + > > > > The new way to add a board is via boards.cfg. You shouldn't need to > > modify this Makefile. > > Is there some appropriate documentation on how boards.cfg is supposed to work? Not that I'm aware of. Its a relatively recent change to U-Boot. > The latest u-boot.git still seems to have the P2020DS lines that I referenced in "Makefile", and it has no references at all to "P2020DS" in the "boards.cfg" file. It looks like the top-level Makefile is still required for boards that support multiple configs, eg 'make P2020DS_36BIT' will configure U-Boot to compile a 36-bit addressable U-Boot image while 'make P2020DS' will configure a 32-bit addressable U-Boot image, but they both use the same Makefile rule with some fancy parsing. So I guess if you have a need for both a 32 and 36bit version of U-Boot you'll to modify the Makefile like your original patch did unfortunately. If you don't need to support both U-Boot configs, you can go the route of other similar boards that are only in boards.cfg, eg P4080DS, P1022DS, XPedite5370, etc. Best, Peter ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices 2010-09-07 21:40 ` Peter Tyser @ 2010-09-07 21:59 ` Wolfgang Denk 2010-09-07 22:21 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritusHWW-1U-1A devices Moffett, Kyle D 1 sibling, 0 replies; 19+ messages in thread From: Wolfgang Denk @ 2010-09-07 21:59 UTC (permalink / raw) To: u-boot Dear Peter Tyser, In message <1283895627.26713.466.camel@petert> you wrote: > > It looks like the top-level Makefile is still required for boards that > support multiple configs, eg 'make P2020DS_36BIT' will configure U-Boot > to compile a 36-bit addressable U-Boot image while 'make P2020DS' will > configure a 32-bit addressable U-Boot image, but they both use the same It is just that old, existing entries have not been converted yet, as nobody has submitted patches uet to implement such support in the boards.cfg context. > Makefile rule with some fancy parsing. So I guess if you have a need > for both a 32 and 36bit version of U-Boot you'll to modify the Makefile > like your original patch did unfortunately. If you don't need to We do not allow to add any new entries like thes eany more. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de The more sins you confess, the more books you will sell. ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritusHWW-1U-1A devices 2010-09-07 21:40 ` Peter Tyser 2010-09-07 21:59 ` Wolfgang Denk @ 2010-09-07 22:21 ` Moffett, Kyle D 1 sibling, 0 replies; 19+ messages in thread From: Moffett, Kyle D @ 2010-09-07 22:21 UTC (permalink / raw) To: u-boot On Sep 07, 2010, at 17:40, Peter Tyser wrote: > Hi Kyle, >> The latest u-boot.git still seems to have the P2020DS lines that I referenced in "Makefile", and it has no references at all to "P2020DS" in the "boards.cfg" file. > > It looks like the top-level Makefile is still required for boards that > support multiple configs, eg 'make P2020DS_36BIT' will configure U-Boot > to compile a 36-bit addressable U-Boot image while 'make P2020DS' will > configure a 32-bit addressable U-Boot image, but they both use the same > Makefile rule with some fancy parsing. So I guess if you have a need > for both a 32 and 36bit version of U-Boot you'll to modify the Makefile > like your original patch did unfortunately. If you don't need to > support both U-Boot configs, you can go the route of other similar > boards that are only in boards.cfg, eg P4080DS, P1022DS, XPedite5370, > etc. Hmm... Well I'd like to just have my config always be 36-bit to support up to 4GB of RAM. On the other hand, I also still need to support 32-bit kernels (with only 2GB of usable RAM, obviously). Unfortunately right now I don't see any way of doing both from the same U-Boot image and device tree, as a 36-bit U-Boot maps critical I/O much higher in physical address space. This leads to another question: Is there any way to create a memory hole just like x86_64 systems do? Specifically, I'm thinking about a physical memory-map like this: 0x00000000 - 0x7fffffff [ 2GB] DDR2 Memory 0x80000000 - 0x9fffffff [512MB] PCIE3 Window 0xa0000000 - 0xbfffffff [512MB] PCIE2 Window 0xc0000000 - 0xdfffffff [512MB] PCIE1 Window 0xe0000000 - 0xefffffff [256MB] FLASH (2x128MB) 0xf0000000 - 0xffffffff [256MB] Miscellaneous I/O resources 0x100000000 - 0x17fffffff [ 2GB] DDR2 Memory, inaccessible to 32-bit OS This is basically the same as my current 32-bit memory mapping, but with all memory above 2GB mapped separately further up in the address space. ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC] Board support patches for the eXMeritus HWW-1U-1A devices @ 2010-08-13 16:27 Kyle Moffett 2010-08-13 16:28 ` [U-Boot] [RFC][PATCH 3/3] Add board support " Kyle Moffett 0 siblings, 1 reply; 19+ messages in thread From: Kyle Moffett @ 2010-08-13 16:27 UTC (permalink / raw) To: u-boot Hello all! This is my first U-Boot submission, so my apologies if there are any coding style or conventions issues. Please let me know and I'll get them fixed up shortly. In addition, these patches were based on v2010.03 and I realize that the upstream may have diverged a bit since then. Please let me know what GIT version I should rebase these patches on for future submissions. The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis with 3 independent TEMPEST zones. Two independent P2020 computers may be found inside each zone. Complete hardware support is included. There are a couple preliminary patches to common code, but basically everything else is limited to our own board-support code. I look forward to your comments and criticisms! Cheers, Kyle Moffett -- Overall diffstat below: MAKEALL | 2 + Makefile | 4 + board/exmeritus/hww-1u-1a/Makefile | 54 +++ board/exmeritus/hww-1u-1a/config.mk | 31 ++ board/exmeritus/hww-1u-1a/ddr.c | 136 +++++++ board/exmeritus/hww-1u-1a/gpios.h | 131 ++++++ board/exmeritus/hww-1u-1a/hww-1u-1a.c | 697 +++++++++++++++++++++++++++++++++ board/exmeritus/hww-1u-1a/law.c | 40 ++ board/exmeritus/hww-1u-1a/tlb.c | 93 +++++ common/ddr_spd.c | 4 +- cpu/mpc85xx/cpu.c | 7 +- cpu/mpc8xxx/ddr/ddr2_dimm_params.c | 30 +- drivers/net/e1000.c | 7 + include/configs/HWW_1U_1A.h | 478 ++++++++++++++++++++++ 14 files changed, 1702 insertions(+), 12 deletions(-) ^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices 2010-08-13 16:27 [U-Boot] [RFC] Board support patches for the eXMeritus HWW-1U-1A devices Kyle Moffett @ 2010-08-13 16:28 ` Kyle Moffett 0 siblings, 0 replies; 19+ messages in thread From: Kyle Moffett @ 2010-08-13 16:28 UTC (permalink / raw) To: u-boot The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis with 3 independent TEMPEST zones. Two independent P2020 computers may be found inside each zone. Complete hardware support is included. High-level hardware overview: * DO-160 certified for passenger aircraft (noncritical) * TEMPEST ceritified for RED/BLACK separation * 3 zones per chassis, 2 computers per zone (total of 6) * Dual-core 1.066GHz P2020 per computer * One 2GB DDR2 SO-RDIMM module per computer (upgradable to 4GB) * Removable 80GB or 160GB Intel X18-M SSD per computer * Front-accessible dual-port E1000E per computer * Front-accessible serial console per computer * Front-accessible USB port per computer * Internal Gigabit crossover within each TEMPEST zone * Internal unidirectional fiber links across TEMPEST zones * Battery-backed DS1339 I2C RTC on each CPU. Combined, each 13lb 1U chassis contains 12GB RAM, 12 cores @ 1.066GHz, 12 front-accessible Gigabit Ethernet ports and 960GB of solid-state storage with a total power consumption of ~200W. Additional notes: * SPD detection is only known to work with the DO-160-certified DIMMs * A U-Boot built with 36-bit address-space seems to work, but I don't yet have a usable 36-bit kernel or DTB, so it's mostly untested. * CPU reset is a little quirky due to hardware misfeature, see the extensive comments in the board_reset_r() function in hww-1u-1a.c Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> --- MAKEALL | 2 + Makefile | 4 + board/exmeritus/hww-1u-1a/Makefile | 54 +++ board/exmeritus/hww-1u-1a/config.mk | 31 ++ board/exmeritus/hww-1u-1a/ddr.c | 136 +++++++ board/exmeritus/hww-1u-1a/gpios.h | 131 ++++++ board/exmeritus/hww-1u-1a/hww-1u-1a.c | 697 +++++++++++++++++++++++++++++++++ board/exmeritus/hww-1u-1a/law.c | 40 ++ board/exmeritus/hww-1u-1a/tlb.c | 93 +++++ cpu/mpc85xx/cpu.c | 7 +- include/configs/HWW_1U_1A.h | 478 ++++++++++++++++++++++ 11 files changed, 1671 insertions(+), 2 deletions(-) create mode 100644 board/exmeritus/hww-1u-1a/Makefile create mode 100644 board/exmeritus/hww-1u-1a/config.mk create mode 100644 board/exmeritus/hww-1u-1a/ddr.c create mode 100644 board/exmeritus/hww-1u-1a/gpios.h create mode 100644 board/exmeritus/hww-1u-1a/hww-1u-1a.c create mode 100644 board/exmeritus/hww-1u-1a/law.c create mode 100644 board/exmeritus/hww-1u-1a/tlb.c create mode 100644 include/configs/HWW_1U_1A.h diff --git a/MAKEALL b/MAKEALL index 5c303f9..bd1a3de 100755 --- a/MAKEALL +++ b/MAKEALL @@ -387,6 +387,8 @@ LIST_83xx=" \ LIST_85xx=" \ ATUM8548 \ + HWW-1U-1A \ + HWW-1U-1A_36BIT \ MPC8536DS \ MPC8536DS_NAND \ MPC8536DS_SDCARD \ diff --git a/Makefile b/Makefile index e141cb2..ad14913 100644 --- a/Makefile +++ b/Makefile @@ -2499,6 +2499,10 @@ P2020DS_36BIT_config \ P2020DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale +HWW_1U_1A_36BIT_config \ +HWW_1U_1A_config: unconfig + @$(MKCONFIG) -t $(@:_config=) HWW_1U_1A ppc mpc85xx hww-1u-1a exmeritus + P1011RDB_config \ P1011RDB_NAND_config \ P1011RDB_SDCARD_config \ diff --git a/board/exmeritus/hww-1u-1a/Makefile b/board/exmeritus/hww-1u-1a/Makefile new file mode 100644 index 0000000..caa6a69 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_DDR_SPD) += ddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/exmeritus/hww-1u-1a/config.mk b/board/exmeritus/hww-1u-1a/config.mk new file mode 100644 index 0000000..878b7b3 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/config.mk @@ -0,0 +1,31 @@ +# +# Copyright 2009-2010 eXMeritus, A Boeing Company +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# p2020ds board +# +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/exmeritus/hww-1u-1a/ddr.c b/board/exmeritus/hww-1u-1a/ddr.c new file mode 100644 index 0000000..b587c87 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/ddr.c @@ -0,0 +1,117 @@ +/* + * Copyright 2009-2010 eXMeritus, A Boeing Company + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +} board_specific_parameters_t; + +/* ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ + +const board_specific_parameters_t board_specific_parameters[][20] = { + { + /* memory controller 0 */ + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ + { 0,1000, 2, 4, 4, 2, 0}, + { 0,1000, 1, 4, 4, 2, 0}, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const board_specific_parameters_t *pbsp = + &(board_specific_parameters[ctrl_num][0]); + u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / + sizeof(board_specific_parameters[0][0]); + u32 i; + ulong ddr_freq; + + /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i&1) { /* odd CS */ + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 0; + } else { /* even CS */ + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 4; + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { + popts->cs_local_opts[i].odt_rd_cfg = 3; + popts->cs_local_opts[i].odt_wr_cfg = 3; + } + } + } + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm->n_ranks == pbsp->n_ranks) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + } + pbsp++; + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/exmeritus/hww-1u-1a/gpios.h b/board/exmeritus/hww-1u-1a/gpios.h new file mode 100644 index 0000000..5b382a3 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/gpios.h @@ -0,0 +1,131 @@ +/* + * Copyright 2010 eXMeritus, A Boeing Company + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */ +#define GPIO_CPU_ID (1UL << (31 - 8)) +#define GPIO_BLUE_LED (1UL << (31 - 9)) +#define GPIO_DIMM_RESET (1UL << (31 - 10)) +#define GPIO_USB_RESET (1UL << (31 - 11)) +#define GPIO_UNUSED_12 (1UL << (31 - 12)) +#define GPIO_GETH0_RESET (1UL << (31 - 13)) +#define GPIO_RS422_RE (1UL << (31 - 14)) +#define GPIO_RS422_DE (1UL << (31 - 15)) +#define IRQ_I2CINT (1UL << (31 - 20)) +#define IRQ_FANINT (1UL << (31 - 21)) +#define IRQ_DIMM_EVENT (1UL << (31 - 22)) + +/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ +#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0)) +#define GPIO_CPUA_CPU_READY (1UL << (31 - 1)) +#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2)) +#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3)) +#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */ +#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */ +#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */ +#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */ +#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16)) +#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17)) +#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18)) +#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19)) + +/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ +#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0)) +#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1)) +#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2)) +#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3)) +#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4)) +#define GPIO_CPUB_CPU_READY (1UL << (31 - 5)) +#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6)) +#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7)) +#define IRQ_CPUB_SD_1A (1UL << (31 - 16)) +#define IRQ_CPUB_SD_2B (1UL << (31 - 17)) +#define IRQ_CPUB_SD_2A (1UL << (31 - 18)) +#define IRQ_CPUB_SD_1B (1UL << (31 - 19)) + +#define GPIOIRQ_CPUB_INIT_DIR /* Output pins */ \ + ( GPIOIRQ_GLBL_INIT_DIR | GPIO_CPUB_CPU_READY \ + | GPIO_CPUB_DEBUG_LED2 | GPIO_CPUB_DEBUG_LED1 \ + | GPIO_CPUB_RMUX_SEL0A | GPIO_CPUB_RMUX_SEL0B \ + | GPIO_CPUB_RMUX_SEL1A | GPIO_CPUB_RMUX_SEL1B ) + +#define GPIOIRQ_CPUB_INIT_VAL /* Pins to drive high */ \ + ( GPIOIRQ_GLBL_INIT_VAL | GPIO_CPUB_CPU_READY \ + | GPIO_CPUB_RMUX_SEL0A | GPIO_CPUB_RMUX_SEL0B ) + +#define GPIOIRQ_CPUB_BOOT_VAL /* Pins to drive high */ \ + ( GPIOIRQ_GLBL_BOOT_VAL | GPIO_CPUB_CPU_READY \ + | GPIO_CPUB_RMUX_SEL0A | GPIO_CPUB_RMUX_SEL0B ) + +static inline void hww1u1a_gpio_set(unsigned int mask, + unsigned int dir, unsigned int val) +{ + volatile ccsr_gpio_t *gpio; + + /* First mask off the unwanted parts of "dir" and "val" */ + dir &= mask; + val &= mask; + + /* Now read in the values we're supposed to preserve */ + gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + dir |= (in_be32(&gpio->gpdir) & ~mask); + val |= (in_be32(&gpio->gpdat) & ~mask); + + /* Now write out the new values, writing the direction first */ + out_be32(&gpio->gpdir, dir); + asm("sync; isync":::"memory"); + out_be32(&gpio->gpdat, val); +} + +static inline void hww1u1a_gpio_set_in(unsigned int gpios) +{ + hww1u1a_gpio_set(gpios, 0x00000000, 0x00000000); +} + +static inline void hww1u1a_gpio_set_low(unsigned int gpios) +{ + hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0x00000000); +} + +static inline void hww1u1a_gpio_set_high(unsigned int gpios) +{ + hww1u1a_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF); +} + +static inline unsigned int hww1u1a_gpio_get(unsigned int mask) +{ + volatile ccsr_gpio_t *gpio; + unsigned int ret; + + /* Read the requested values */ + gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ret = mask & in_be32(&gpio->gpdat); + + return ret; +} + +static inline unsigned int hww1u1a_is_cpu_a(void) +{ + return !hww1u1a_gpio_get(GPIO_CPU_ID); +} + +static inline unsigned int hww1u1a_is_cpu_b(void) +{ + return !!hww1u1a_gpio_get(GPIO_CPU_ID); +} + diff --git a/board/exmeritus/hww-1u-1a/hww-1u-1a.c b/board/exmeritus/hww-1u-1a/hww-1u-1a.c new file mode 100644 index 0000000..9671549 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/hww-1u-1a.c @@ -0,0 +1,697 @@ +/* + * Copyright 2009-2010 eXMeritus, A Boeing Company + * Copyright 2007-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <tsec.h> +#include <asm/fsl_law.h> +#include <asm/mp.h> +#include <netdev.h> +#include <malloc.h> +#include <i2c.h> + +#include "gpios.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t fixed_sdram(void); + +int checkboard(void) +{ + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + + unsigned int gpio_high = 0; + unsigned int gpio_low = 0; + unsigned int gpio_in = 0; + unsigned int i; + + puts("Board: HWW-1U-1A "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif + + /* + * First just figure out which CPU we're on, then use that to + * configure the lists of other GPIOs to be programmed. + */ + hww1u1a_gpio_set_in(GPIO_CPU_ID); + if (hww1u1a_is_cpu_a()) { + puts("CPU A\n"); + + /* We want to turn on some LEDs */ + gpio_high |= GPIO_CPUA_CPU_READY; + gpio_low |= GPIO_CPUA_DEBUG_LED1; + gpio_low |= GPIO_CPUA_DEBUG_LED2; + + /* Disable the unused transmitters */ + gpio_low |= GPIO_CPUA_TDIS1A; + gpio_high |= GPIO_CPUA_TDIS1B; + gpio_low |= GPIO_CPUA_TDIS2A; + gpio_high |= GPIO_CPUA_TDIS2B; + } else { + puts("CPU B\n"); + + /* We want to turn on some LEDs */ + gpio_high |= GPIO_CPUB_CPU_READY; + gpio_low |= GPIO_CPUB_DEBUG_LED1; + gpio_low |= GPIO_CPUB_DEBUG_LED2; + + /* Enable the appropriate receivers */ + gpio_high |= GPIO_CPUB_RMUX_SEL0A; + gpio_high |= GPIO_CPUB_RMUX_SEL0B; + gpio_low |= GPIO_CPUB_RMUX_SEL1A; + gpio_low |= GPIO_CPUB_RMUX_SEL1B; + } + + /* These GPIOs are common */ + gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT; + gpio_low |= GPIO_RS422_RE; + gpio_high |= GPIO_RS422_DE; + + /* Ok, now go ahead and program all of those in one go */ + hww1u1a_gpio_set( gpio_high|gpio_low|gpio_in, + gpio_high|gpio_low, + gpio_high); + + /* + * If things have been taken out of reset early (for example, by one + * of the BDI3000 debuggers), then we need to put them back in reset + * and delay a while before we continue. + */ +#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET) + if (hww1u1a_gpio_get(GPIO_RESETS)) { + puts("Debugger detected... extra device reset enabled!\n"); + + /* Put stuff into reset and disable the DDR controller */ + hww1u1a_gpio_set_low(GPIO_RESETS); + out_be32(&ddr->sdram_cfg, 0x00000000); + + puts(" Waiting 1 sec for reset..."); + for (i = 0; i < 10; i++) { + udelay(100000); + puts("."); + } + puts("\n"); + } + + /* Now bring everything back out of reset again */ + hww1u1a_gpio_set_high(GPIO_RESETS); + return 0; +} + +/* Create a prompt-like string: "uboot at HOSTNAME% " */ +#define PROMPT_PREFIX "uboot@exm" +#define PROMPT_SUFFIX "% " + +/* This function returns a PS1 prompt based on the serial number */ +static char *hww1u1a_prompt = NULL; +const char *hww1u1a_get_ps1(void) +{ + unsigned long len, i, j; + const char *serialnr; + + /* If our prompt was already set, just use that */ + if (hww1u1a_prompt) + return hww1u1a_prompt; + + /* Use our serial number if present, otherwise "UNPROGRAMMED-[AB]" */ + serialnr = getenv("serial#"); + if (!serialnr || !serialnr[0]) { + if (hww1u1a_is_cpu_a()) + serialnr = "999999-XA"; + else + serialnr = "999999-XB"; + } + + /* + * We will turn the serial number into a hostname by: + * (A) Delete all non-alphanumerics. + * (B) Lowercase all letters + * (C) Prefix "exm" + */ + for (i = 0, len = 0; serialnr[i]; i++) { + if ('0' <= serialnr[i] && serialnr[i] <= '9') + len++; + else if ('a' <= serialnr[i] && serialnr[i] <= 'z') + len++; + else if ('A' <= serialnr[i] && serialnr[i] <= 'Z') + len++; + } + + len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX); /* Includes NUL */ + hww1u1a_prompt = malloc(len); + if (!hww1u1a_prompt) + return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX; + + /* Now actually fill it in */ + i = 0; + + /* Handle the prefix */ + for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++) + hww1u1a_prompt[i++] = PROMPT_PREFIX[j]; + + /* Now the serial# part of the hostname */ + for (j = 0; serialnr[j]; j++) { + if ('0' <= serialnr[j] && serialnr[j] <= '9') + hww1u1a_prompt[i++] = serialnr[j]; + else if ('a' <= serialnr[j] && serialnr[j] <= 'z') + hww1u1a_prompt[i++] = serialnr[j]; + else if ('A' <= serialnr[j] && serialnr[j] <= 'Z') + hww1u1a_prompt[i++] = serialnr[j] + 'a' - 'A'; + } + + /* Finally the suffix */ + for (j = 0; j < sizeof(PROMPT_SUFFIX); j++) + hww1u1a_prompt[i++] = PROMPT_SUFFIX[j]; + + /* This should all have added up, but just in case */ + hww1u1a_prompt[len - 1] = '\0'; + + /* Now we're done */ + return hww1u1a_prompt; +} + + +phys_size_t initdram(int board_type) +{ +#ifndef CONFIG_SPD_EEPROM + /* This is manual (non-SPD) DDR2 SDRAM configuration (2GB ECC) */ + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + phys_size_t dram_size = (2048ULL) << 20; + out_be32(&ddr->cs0_bnds, 0x0000003F); + out_be32(&ddr->cs1_bnds, 0x0040007F); + out_be32(&ddr->cs0_config, 0x80014202); + out_be32(&ddr->cs1_config, 0x80014202); + out_be32(&ddr->timing_cfg_0, 0x00330804); + out_be32(&ddr->timing_cfg_1, 0x6f69f643); + out_be32(&ddr->timing_cfg_2, 0x022068cd); + out_be32(&ddr->timing_cfg_3, 0x00030000); + out_be32(&ddr->sdram_cfg_2, 0x04400010); + out_be32(&ddr->sdram_mode, 0x00440452); + out_be32(&ddr->sdram_mode_2, 0x00000000); + out_be32(&ddr->sdram_md_cntl, 0x00000000); + out_be32(&ddr->sdram_interval, 0x0a280110); + out_be32(&ddr->sdram_data_init, 0xDEADBEEF); + out_be32(&ddr->sdram_clk_cntl, 0x02000000); + out_be32(&ddr->timing_cfg_4, 0x00000000); + out_be32(&ddr->timing_cfg_5, 0x00000000); + out_be32(&ddr->ddr_zq_cntl, 0x00000000); + out_be32(&ddr->ddr_wrlvl_cntl, 0x00000000); + out_be32(&ddr->ip_rev1, 0x00020403); + out_be32(&ddr->ip_rev2, 0x00000100); + out_be32(&ddr->err_int_en, 0x0000000D); + out_be32(&ddr->err_disable, 0x00000000); + out_be32(&ddr->err_sbe, 0x00010000); + out_be32(&ddr->ddr_cdr1, 0x00040000); + out_be32(&ddr->ddr_cdr2, 0x00000000); + out_be32(&ddr->sdram_cfg, 0x73000000); + + /* Allow time for the clocks to stabilize before enabling */ + udelay(500); + out_be32(&ddr->sdram_cfg, 0xF3000000); + + /* Now wait until memory is initialized */ + while (in_be32(&ddr->sdram_cfg_2) & 0x00000010) + udelay(1000); + + /* Finally we set up the local access windows */ + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, dram_size, + LAW_TRGT_IF_DDR) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; +#else + /* We also support "Automagic mode" */ + phys_size_t dram_size = fsl_ddr_sdram(); +#endif + + /* Before we're done we need to set up the TLB entries */ + return setup_ddr_tlbs(dram_size >> 20) << 20; +} + +static struct pci_controller pcie1_hose; +static struct pci_controller pcie2_hose; +static struct pci_controller pcie3_hose; +void pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + + debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + printf(" eTSEC2 is in sgmii mode.\n"); + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + printf(" eTSEC3 is in sgmii mode.\n"); + + puts("\n"); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); + } else { + printf(" PCIE1: disabled\n"); + } + + puts("\n"); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf(" PCIE2 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); + } else { + printf(" PCIE2: disabled\n"); + } + + puts("\n"); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); + printf(" PCIE3 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); + } else { + printf(" PCIE3: disabled\n"); + } + puts("\n"); + +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap bootflash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for FLASH */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[4]; + volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + + SET_STD_TSEC_INFO(tsec_info[0], 1); + SET_STD_TSEC_INFO(tsec_info[1], 2); + SET_STD_TSEC_INFO(tsec_info[2], 3); + if (pgpio->gpdat & GPIO_CPU_ID) + tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB; + else + tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA; + + tsec_eth_init(bis, tsec_info, 3); + return pci_eth_init(bis); +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +} + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} + +/* We don't have any really usable POST memory, so just fake it */ +unsigned long post_word_load (void) +{ + return 0l; +} + +void post_word_store (unsigned long val) +{ + return; +} + +/* + * Unfortunately we have a bit of a problem with our reset line wiring on the + * HWW-1U-1A boards. + * + * Specifically the "CPU A" reset controls all of the PCI devices on the + * IO/backplane card, which means ethernet and SATA controllers for both + * CPU A *and* CPU B. + * + * This is somewhat of a problem if the CPUs are reset independently... CPU B + * might fail to come up because his PCI devices are confused, or CPU B might + * die because CPU A just reset the SATA controller for his root filesystem. + * + * Since in practice the CPUs never need to reboot independently we will go + * ahead and require GPIO cross-communication between them before either one + * will reset. + * + * The communication protocol uses GPIOs 4-7 on the PCA9554 GPIO expander + * found on I2C-2 at address 0x3f. CPU A uses 4,5 as TX and 6,7 as RX; for + * CPU B we use the exact opposite. + * + * The GPIOs initialize as inputs during poweron, and are pulled high; the + * PCA9554 expanders will maintain valid outputs over soft-reset allowing for + * reliable operation. + * + * To avoid duplication, we will assign names to the GPIOs: + * ,---------------------------------------. + * | GPIO4 | GPIO5 | GPIO6 | GPIO7 | + * ,---------|=========|=========|=========|=========| + * | CPU A | tx1 | tx2 | rx1 | rx2 | + * |---------|---------|---------|---------|---------| + * | CPU B | rx1 | rx2 | tx1 | tx2 | + * `-------------------------------------------------' + * + * The state machine for each CPU is below. In simplistic terms, each CPU + * waits until the other has cleared its GPIOs, then cause a tx1 high=>low + * transition. Upon seeing the other CPU do the same, it will perform a + * tx2 high=>low transition and again wait. + * + * Once both CPUs have performed and seen both transitions, they will each + * set tx1 high (to create an "invalid" state) and then reset. + * + * ,--------------. + * | START/ERROR: |<==-. + * ,-==>| tx2 = 1; | || (rx2 == 0) + * || | tx1 = 1; | ==-' + * || `--------------' + * || || + * || || (rx2 == 1) + * || \/ + * || ,--------------. + * || | WAITING: |<==-. + * |\== | tx1 = 0; | || (rx1 == 1) && (rx2 == 1) + * || | | ==-' + * || `--------------' + * || || + * || || (rx1 == 0) && (rx2 == 1) + * || \/ + * || ,--------------. + * || | BOTH_READY: |<==-. + * `-== | tx2 = 0; | || (rx1 == 0) && (rx2 == 1) + * | | ==-' + * `--------------' + * || + * || (rx2 == 0) + * \/ + * ,--------------. + * | RESETTING: | + * | tx1 = 1; | + * | reset(); | + * `--------------' + * + * While in the "BOTH_READY" state a high-to-low rx2 transition must be + * followed within 50ms by activation of the HRESET_REQ signal. That + * state MUST NOT be interrupted by any event other than the observed + * event (rx1 == high) && (rx2 == high). + */ + +#define PCA9554_I2C_ADDR 0x3f +static inline int pca9554_read(u8 reg) +{ + u8 value; + int ret; + + i2c_set_bus_num(1); + ret = i2c_read(PCA9554_I2C_ADDR, reg, 1, &value, 1); + if (ret < 0) + return ret; + return value; +} +static inline int pca9554_write(u8 reg, u8 value) +{ + i2c_set_bus_num(1); + return i2c_write(PCA9554_I2C_ADDR, reg, 1, &value, 1); +} +static inline int pca9554_setmask(u8 reg, u8 value, u8 mask) +{ + int ret = pca9554_read(reg); + if (ret < 0) + return ret; + + return pca9554_write(reg, (ret & ~mask) | (value & mask)); +} + +#define PCA9554_DATA_IN 0x00 +#define PCA9554_DATA_OUT 0x01 +#define PCA9554_INVERT 0x02 +#define PCA9554_IS_INPUT 0x03 + +static inline int pca9554_set_low(u8 gpio) +{ + return pca9554_setmask(PCA9554_DATA_OUT, 0x00, (1U << gpio)); +} + +static inline int pca9554_set_high(u8 gpio) +{ + return pca9554_setmask(PCA9554_DATA_OUT, 0xff, (1U << gpio)); +} + +static inline int pca9554_set_output(u8 gpio) +{ + return pca9554_setmask(PCA9554_IS_INPUT, 0x00, (1U << gpio)); +} + +static inline int pca9554_set_input(u8 gpio) +{ + return pca9554_setmask(PCA9554_DATA_OUT, 0xff, (1U << gpio)); +} + +void board_reset_r(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u8 tx1, tx2, rx1, rx2, rxmask; + int ret; + + /* Our state-machine state */ + enum { + START_ERROR = 0, + WAITING, + BOTH_READY, + } state; + + printf("RESET: Preparing..."); + + /* First clear the "INVERT" setting on all relevant GPIOs */ + if (pca9554_setmask(PCA9554_INVERT, 0x00, 0xf0) < 0) + goto err; + + /* Check what CPU we are and configure accordingly. */ + if (hww1u1a_is_cpu_a()) { + tx1 = 4; tx2 = 5; rx1 = 6; rx2 = 7; + } else { + rx1 = 4; rx2 = 5; tx1 = 6; tx2 = 7; + } + rxmask = (1U << rx1) | (1U << rx2); + + /* Configure both inputs */ + if (pca9554_set_input(rx1) < 0) + goto err; + if (pca9554_set_input(rx2) < 0) + goto err; + + /* Make sure the very first thing we do is set the "tx2" GPIO high */ + if (pca9554_set_high(tx2) < 0) + goto err; + if (pca9554_set_output(tx2) < 0) + goto err; + + /* Now reset our other transmit pin */ + if (pca9554_set_high(tx1) < 0) + goto err; + if (pca9554_set_output(tx1) < 0) + goto err; + + /* Enter the state machine */ + state = START_ERROR; + +poll_state: + ret = pca9554_read(PCA9554_DATA_IN); + switch (state) { + case START_ERROR: + if (ctrlc()) + goto intr; + + if (ret < 0) + goto err; + + /* Wait for (rx2 == high) */ + if (ret & (1U << rx2)) { + /* Success! */ + state = WAITING; + goto enter_state; + } + + goto poll_state; + + case WAITING: + if (ctrlc()) + goto intr; + + if (ret < 0) + goto err; + + /* Wait for (rx1 == low) && (rx2 == high) */ + ret &= rxmask; + if (ret == (1U << rx2)) { + /* Success! */ + state = BOTH_READY; + goto enter_state; + } + if (ret != rxmask) { + /* Oops, error */ + state = START_ERROR; + goto enter_state; + } + + goto poll_state; + + case BOTH_READY: + /* + * Non-interruptable wait for (rx2 == low), however if we + * see (rx1 == high) and (rx2 == high) we should go back + * to START_ERROR. + */ + if (ret < 0) + goto poll_state; + + ret &= rxmask; + if (ret == rxmask) { + /* Oops, error */ + state = START_ERROR; + goto enter_state; + } + if (ret & (1U << rx2)) + goto poll_state; + + /* Success, we have to reset quick now! */ + (void)pca9554_set_high(tx1); + + /* Turn on the "HRESET_REQ" pin (hard-reset request) */ + printf("\nRESET: Hardware reset triggered, waiting...\n"); + out_be32(&gur->rstcr, 0x2); + while (1) + udelay(10000); + } + +enter_state: + switch (state) { + case START_ERROR: + printf("\nRESET: Negotiation error!"); + printf("\nRESET: Starting over..."); + /* Clear both GPIOs high in the right order */ + if (pca9554_set_high(tx2) < 0) + goto err; + if (pca9554_set_high(tx1) < 0) + goto err; + if (ctrlc()) + goto intr; + + goto poll_state; + + case WAITING: + printf("\nRESET: Waiting for peer..."); + /* Set tx1 low */ + if (pca9554_set_low(tx1) < 0) + goto err; + if (ctrlc()) + goto intr; + + goto poll_state; + + case BOTH_READY: + printf("\nRESET: Both ready, point of no return..."); + /* Point of no return: set tx2 low */ + if (pca9554_set_low(tx2) < 0) + goto err; + + goto poll_state; + } + + /* We only get here through gotos */ +err: + printf("\nRESET: I2C communication error!\n"); +intr: + printf("\nRESET: Aborted!\n"); + (void)pca9554_set_high(tx1); + (void)pca9554_set_high(tx2); + return; +} + diff --git a/board/exmeritus/hww-1u-1a/law.c b/board/exmeritus/hww-1u-1a/law.c new file mode 100644 index 0000000..c1dffd9 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/law.c @@ -0,0 +1,40 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/exmeritus/hww-1u-1a/tlb.c b/board/exmeritus/hww-1u-1a/tlb.c new file mode 100644 index 0000000..672e8b9 --- /dev/null +++ b/board/exmeritus/hww-1u-1a/tlb.c @@ -0,0 +1,93 @@ +/* + * Copyright 2009-2010 eXMeritus, A Boeing Company + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd at denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Boot page */ + SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, + CONFIG_BPTR_VIRT_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, + CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - FLASH */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI memory */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, + CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, + CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 0cc6e03..49d963d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -190,8 +190,10 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { -/* Everything after the first generation of PQ3 parts has RSTCR */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ +#if defined(CONFIG_BOARD_RESET_R) + extern void board_reset_r(void); + board_reset_r(); +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) unsigned long val, msr; @@ -207,6 +209,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) val |= 0x70000000; mtspr(DBCR0,val); #else + /* Everything after the first generation of PQ3 parts has RSTCR */ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ udelay(100); diff --git a/include/configs/HWW_1U_1A.h b/include/configs/HWW_1U_1A.h new file mode 100644 index 0000000..9c0706f --- /dev/null +++ b/include/configs/HWW_1U_1A.h @@ -0,0 +1,478 @@ +/* + * Copyright 2009-2010 eXMeritus, A Boeing Company + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * HardwareWall HWW-1U-1A airborne unit configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/************************************************************************ + * High-level system configuration options * + ************************************************************************/ +/*#define DEBUG 1*/ +#define CONFIG_BOOKE 1 /* Power/PowerPC Book-E */ +#define CONFIG_E500 1 /* e500 (Power ISA v2.03 with SPE) */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 family */ +#define CONFIG_FSL_ELBC 1 /* FreeScale Enhanced LocalBus Cntlr */ +#define CONFIG_FSL_LAW 1 /* FreeScale Local Access Window */ +#define CONFIG_P2020 1 /* FreeScale P2020 */ +#define CONFIG_HWW1U1A 1 /* eXMeritus HardwareWall HWW-1U-1A */ +#define CONFIG_MP 1 /* Multiprocessing support */ + +#define CONFIG_L2_CACHE 1 /* L2 cache enabled */ +#define CONFIG_BTB 1 /* Branch predition enabled */ + +#define CONFIG_PANIC_HANG 1 /* No board reset on panic */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r() */ +#define CONFIG_BOARD_RESET_R 1 /* Call board_reset_r() */ + +/* Allow the use of 36-bit physical addresses in "HWW_1U_1A_36BIT" mode */ +#define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_MK_36BIT +# define CONFIG_PHYS_64BIT 1 +# define CONFIG_ADDR_MAP 1 +# define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */ +#endif + +/* This is the U-Boot base address and size */ +#define CONFIG_SYS_MONITOR_BASE 0xeff80000 +#define CONFIG_SYS_MONITOR_LEN 0x00080000 +#if defined(TEXT_BASE) && (TEXT_BASE != CONFIG_SYS_MONITOR_BASE) +# error "TEXT_BASE != CONFIG_SYS_MONITOR_BASE" +#endif + +/* Reserve plenty of RAM for malloc (we have 2GB+) */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* This is where we map our L2 cache so we can use it as RAM */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 +#define CONFIG_SYS_INIT_RAM_END 0x00004000 + +/* This is our temporary global data area just above the stack */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + +/* The stack grows down from the global data area */ +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* Enable IRQs and watchdog with a 1000Hz system decrementer */ +#define CONFIG_CMD_IRQ +#define CONFIG_SYS_HZ 1000 +#if 0 /* FIXME */ +#define CONFIG_WATCHDOG 1 + +/* Enable Power-On-Self-Tests */ +#define CONFIG_POST 1 +#define CONFIG_CMD_DIAG +#endif + + +/************************************************************************ + * Clock crystal configuration: * + * (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR) * + * (2) CCB: Multiplier from SYS_CLK * + * (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock) * + ************************************************************************/ +#undef CONFIG_CLOCKS_IN_MHZ +#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/ +#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/ + + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM + * 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1 + * 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused) + * 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3 + * 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH + * 0xe800_0000 0xefff_ffff 128M Spansion FLASH + * 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0) + * 0xffe0_0000 0xffef_ffff 1M CCSR + * 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller + */ + +/* Virtual Memory Map */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR @ reset */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */ + +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* Physical Memory Map */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000ul +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000ul +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000ul +#define CONFIG_SYS_FLASH_BASE_PHYS 0xe0000000ul +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000ul +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000ul +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000ul +#define CONFIG_SYS_CCSRBAR_PHYS 0xffe00000ul +#endif + +/* Legacy code needs this */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + + +/************************************************************************ + * U-Boot Environment Image: The two sectors immediately below U-Boot * + * form the U-Boot environment (regular and redundant) * + ************************************************************************/ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (one flash sector) */ +#define CONFIG_ENV_SIZE 0x02000 /* 8kB */ +#define CONFIG_ENV_SIZE_REDUND 0x02000 /* 8kB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OVERWRITE 1 + + +/************************************************************************ + * Serial Console Configuration * + ************************************************************************/ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Echo back characters received during a serial download */ +#define CONFIG_LOADS_ECHO 1 + +/* Allow a serial-download to temporarily change baud */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + + +/************************************************************************ + * PCI and PCI-Express Support * + * Memory space is mapped 1-1, but I/O space must start from 0. * + ************************************************************************/ + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* Scan PCI busses */ +#define CONFIG_CMD_PCI /* Enable the "pci" command */ +#define CONFIG_FSL_PCI_INIT 1 /* Common FreeScale PCI initialization */ +#define CONFIG_FSL_PCIE_RESET 1 /* We have PCI-E reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* PCI resources are 64-bit */ +#define CONFIG_PCI_SCAN_SHOW 1 /* Display PCI scan during boot */ + +/* Enable all 3 PCI-E controllers */ +#define CONFIG_PCIE1 1 +#define CONFIG_PCIE2 1 +#define CONFIG_PCIE3 1 + +/* PCI controller addresses */ +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) + +/* PCI bus addresses */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#endif + + +/************************************************************************ + * I2C Bus Support and devices * + ************************************************************************/ + +/* Generic FreeScale hardware I2C support */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_FSL_I2C 1 +#define CONFIG_CMD_I2C +#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* I2C bus configuration */ +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES { \ + { 0, 0x29 } \ +} + +/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x51 +#if 0 +#define CONFIG_CMD_EEPROM +#endif + +/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */ +#define CONFIG_CMD_DATE +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +/* Turn off RTC square-wave output to save battery */ +#define CONFIG_SYS_RTC_DS1337_NOOSC 1 + + +/************************************************************************ + * FreeScale DDR2/3 SDRAM Controller * + ************************************************************************/ +#define CONFIG_FSL_DDR2 1 /* Our SDRAM slot is DDR2 */ +#define CONFIG_DDR_ECC 1 /* Enable ECC by default */ +#define CONFIG_DDR_SPD 1 /* Detect DDR config from SPD EEPROM */ +#define CONFIG_SPD_EEPROM 1 /* ...why 2 config variables for this? */ +#define CONFIG_VERY_BIG_RAM 1 /* Allow 2GB+ of RAM */ +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_CMD_SDRAM + +/* Standard P2020 DDR controller parameters */ +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* Make sure to tell the DDR controller to preinitialze all of RAM */ +#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1 + +/* Enable the U-Boot "memory test" */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x7fffffff + + +/************************************************************************ + * FLASH Memory Configuration (2x 128MB SPANSION FLASH) * + ************************************************************************/ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 + +/* Flash banks (2x 128MB) */ +#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull) +#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull) +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS } + +/* Flash configuration registers */ +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(FLASH0_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(FLASH1_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 + +/* Flash timeouts (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */ + +/* Quiet flash testing */ +#define CONFIG_SYS_FLASH_QUIET_TEST 1 + +/* Don't bother checksumming the flash on boot */ +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* Make program/erase count down from 45/5 (9....8....7....) */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 + +#if 0 +# define CONFIG_CMD_JFFS2 +# define CONFIG_CMD_MTDPARTS +#endif + + +/************************************************************************ + * Ethernet Device Support * + ************************************************************************/ +#define CONFIG_NET_MULTI 1 /* We have multiple devices */ +#define CONFIG_MII 1 /* Enable MII PHY code */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* ??? */ +#define CONFIG_PHY_GIGE 1 /* Support Gigabit PHYs */ +#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */ + +#if 0 +/* All of the ethernet interfaces we should have */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_HAS_ETH4 +#endif + +/* Turn on various helpful networking commands */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING + +/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */ +#define CONFIG_TSEC_ENET 1 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC1_NAME "owt0" +#define CONFIG_TSEC2_NAME "owt1" +#define CONFIG_TSEC3_NAME "peer" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 3 +#define TSEC3_PHY_ADDR_CPUA 4 +#define TSEC3_PHY_ADDR_CPUB 5 +#define TSEC3_PHY_ADDR TSEC3_PHY_ADDR_CPUA + +/* PCI-E dual-port E1000 (external ethernet ports) */ +#define CONFIG_E1000 1 +#define CONFIG_E1000_FALLBACK_MAC { 0x00, 0x05, 0x93, 0x81, 0xff, 0xfe } + + +/************************************************************************ + * USB Thumbdrive Device Support * + ************************************************************************/ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_USB + +/* Partition and Filesystem support */ +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + + +/************************************************************************ + * Command line configuration. * + ************************************************************************/ +#define CONFIG_CMDLINE_EDITING 1 /* Enable command editing */ +#define CONFIG_COMMAND_HISTORY 1 /* Enable command history */ +#define CONFIG_AUTOCOMPLETE 1 /* Enable command completion */ +#define CONFIG_SYS_LONGHELP 1 /* Enable detailed command help */ +#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */ +#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */ +#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */ +#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */ +#define CONFIG_SYS_HUSH_PARSER 1 /* Enable a fancier shell */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Command-line continuation */ + +/* A little extra magic here for the prompt */ +#define CONFIG_SYS_PROMPT hww1u1a_get_ps1() +#ifndef __ASSEMBLY__ +const char *hww1u1a_get_ps1(void); +#endif + +/* Include a bunch of default commands we probably want */ +#include <config_cmd_default.h> + +/* Other helpful shell-like commands */ +#define CONFIG_MD5 +#define CONFIG_SHA1 +#define CONFIG_CMD_MD5SUM +#define CONFIG_CMD_SHA1 +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_SETEXPR + + +/************************************************************************ + * Image manipulation and booting * + ************************************************************************/ + +/* We use the OpenFirmware-esque "Flattened Device Tree" */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMD_ELF +#define CONFIG_SYS_BOOTMAPSZ 0x1000000 /* Maximum kernel memory map */ +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* Maximum kernel size of 16MB */ + +#if 0 +/* FIXME */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#endif + +/* This is the default address for commands with an optional address arg */ +#define CONFIG_LOADADDR 100000 +#define CONFIG_SYS_LOAD_ADDR 0x100000 + +#define CONFIG_BOOTDELAY 20 +#define CONFIG_BOOTCOMMAND "echo Not yet flashed" +#define CONFIG_BOOTARGS "" +#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1" + +/* Extra environment parameters */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "preboot=setenv bootargs \"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \ + "perf_mode=stable\0" \ + "memctl_intlv_ctl=2\0" \ + "flkernel=0xe8020000\0" \ + "flinitramfs=0xe8800000\0" \ + "fldevicetree=0xeff20000\0" \ + "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \ + "flboot=run preboot; run flbootm\0" + +#endif /* __CONFIG_H */ -- 1.7.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
end of thread, other threads:[~2010-09-13 4:28 UTC | newest] Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2010-08-30 18:24 [U-Boot] [RFC] Board support patches for the eXMeritus HWW-1U-1A devices Kyle Moffett 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 1/3] DDR2: Support new JEDEC DDR2 SPD 1.3 spec Kyle Moffett 2010-09-03 3:06 ` Peter Tyser 2010-09-03 5:10 ` Kyle Moffett 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 2/3] e1000: Intel 82571EB: Don't wait for MNG cycle on unmanaged chips Kyle Moffett 2010-09-13 4:18 ` Ben Warren 2010-09-13 4:24 ` Kyle Moffett 2010-09-13 4:28 ` Ben Warren 2010-08-30 18:24 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices Kyle Moffett 2010-09-03 4:00 ` Peter Tyser 2010-09-03 5:50 ` Kyle Moffett 2010-09-07 22:09 ` Peter Tyser 2010-09-07 22:50 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritusHWW-1U-1A devices Moffett, Kyle D 2010-09-08 3:43 ` Peter Tyser 2010-09-07 21:21 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritus HWW-1U-1A devices Moffett, Kyle D 2010-09-07 21:40 ` Peter Tyser 2010-09-07 21:59 ` Wolfgang Denk 2010-09-07 22:21 ` [U-Boot] [RFC][PATCH 3/3] Add board support for the eXMeritusHWW-1U-1A devices Moffett, Kyle D -- strict thread matches above, loose matches on Subject: below -- 2010-08-13 16:27 [U-Boot] [RFC] Board support patches for the eXMeritus HWW-1U-1A devices Kyle Moffett 2010-08-13 16:28 ` [U-Boot] [RFC][PATCH 3/3] Add board support " Kyle Moffett
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