From: Wolfram Sang <w.sang@pengutronix.de>
To: zhangfei gao <zhangfei.gao@gmail.com>
Cc: Chris Ball <cjb@laptop.org>,
Andrew Morton <akpm@linux-foundation.org>,
linux-mmc@vger.kernel.org,
Anton Vorontsov <cbouatmailru@gmail.com>,
Ben Dooks <ben-linux@fluff.org>,
Matt Fleming <matt@console-pimps.org>,
Haojian Zhuang <haojian.zhuang@gmail.com>,
Eric Miao <eric.y.miao@gmail.com>
Subject: Re: [patch 1/1] sdhci-base-clock-freqency-change-in-spec-3.0
Date: Wed, 15 Sep 2010 12:10:19 +0200 [thread overview]
Message-ID: <20100915101019.GC5985@pengutronix.de> (raw)
In-Reply-To: <AANLkTi=7gXkF+JpOfM+KaWxHPDzT=0SL5oSXDw0hTmJm@mail.gmail.com>
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On Wed, Sep 15, 2010 at 11:35:18AM +0800, zhangfei gao wrote:
> > Is the 8-bit support really according to the standard? I wonder because
> > the bit currently used by sdhci.c is marked as "reserved/new assignment
> > now allowed" in the simplified v2.0 spec.
>
> Attached capacity in sdh 3.0.
> 6-bit base clock frequece is support in 1.0 and 2.0, support 10M to 63M.
> 8-bit is supported in 3.0, and support 10M to 255M.
I meant 8-bit bus width. Which bit in which register selects this?
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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next prev parent reply other threads:[~2010-09-15 10:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-08-20 6:22 [patch 1/1] sdhci-base-clock-freqency-change-in-spec-3.0 zhangfei gao
2010-08-20 6:37 ` zhangfei gao
2010-09-14 13:18 ` Chris Ball
2010-09-14 13:45 ` Wolfram Sang
[not found] ` <AANLkTi=7gXkF+JpOfM+KaWxHPDzT=0SL5oSXDw0hTmJm@mail.gmail.com>
2010-09-15 10:10 ` Wolfram Sang [this message]
2010-09-19 1:56 ` zhangfei gao
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