* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-21 10:35 ` Shawn Guo
0 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-21 10:35 UTC (permalink / raw)
To: linux-mmc, linux-arm-kernel; +Cc: cjb, arnd, w.sang, linux, Shawn Guo
This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
The driver calls into mxs-dma via generic dmaengine api for both pio
and data transfer.
Thanks Chris Ball for the indentation patch.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-mxs/include/mach/mmc.h | 18 +
drivers/mmc/host/Kconfig | 9 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/mxs-mmc.c | 874 ++++++++++++++++++++++++++++++++++
4 files changed, 902 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-mxs/include/mach/mmc.h
create mode 100644 drivers/mmc/host/mxs-mmc.c
diff --git a/arch/arm/mach-mxs/include/mach/mmc.h b/arch/arm/mach-mxs/include/mach/mmc.h
new file mode 100644
index 0000000..211547a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mmc.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MXS_MMC_H__
+#define __MACH_MXS_MMC_H__
+
+struct mxs_mmc_platform_data {
+ int wp_gpio; /* write protect pin */
+ unsigned int flags;
+#define SLOTF_4_BIT_CAPABLE (1 << 0)
+#define SLOTF_8_BIT_CAPABLE (1 << 1)
+};
+#endif /* __MACH_MXS_MMC_H__ */
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index afe8c6f..47ef75d 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -319,6 +319,15 @@ config MMC_MXC
If unsure, say N.
+config MMC_MXS
+ tristate "Freescale MXS Multimedia Card Interface support"
+ depends on ARCH_MXS && MXS_DMA
+ help
+ This selects the Freescale SSP MMC controller found on MXS based
+ platforms like mx23/28.
+
+ If unsure, say N.
+
config MMC_TIFM_SD
tristate "TI Flash Media MMC/SD Interface support (EXPERIMENTAL)"
depends on EXPERIMENTAL && PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index e834fb2..30aa686 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
obj-$(CONFIG_MMC_PXA) += pxamci.o
obj-$(CONFIG_MMC_IMX) += imxmmc.o
obj-$(CONFIG_MMC_MXC) += mxcmmc.o
+obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
obj-$(CONFIG_MMC_SDHCI_PXA) += sdhci-pxa.o
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
new file mode 100644
index 0000000..99d39a6
--- /dev/null
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -0,0 +1,874 @@
+/*
+ * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
+ * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/highmem.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/completion.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sdio.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/mxs.h>
+#include <mach/common.h>
+#include <mach/dma.h>
+#include <mach/mmc.h>
+
+#define DRIVER_NAME "mxs-mmc"
+
+/* card detect polling timeout */
+#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
+
+#define SSP_VERSION_LATEST 4
+#define ssp_is_old() (host->version < SSP_VERSION_LATEST)
+
+/* SSP registers */
+#define HW_SSP_CTRL0 0x000
+#define BM_SSP_CTRL0_RUN (1 << 29)
+#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
+#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
+#define BM_SSP_CTRL0_READ (1 << 25)
+#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
+#define BP_SSP_CTRL0_BUS_WIDTH (22)
+#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
+#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
+#define BM_SSP_CTRL0_GET_RESP (1 << 17)
+#define BM_SSP_CTRL0_ENABLE (1 << 16)
+#define BP_SSP_CTRL0_XFER_COUNT (0)
+#define BM_SSP_CTRL0_XFER_COUNT (0xffff)
+#define HW_SSP_CMD0 0x010
+#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
+#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
+#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
+#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
+#define BP_SSP_CMD0_BLOCK_SIZE (16)
+#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
+#define BP_SSP_CMD0_BLOCK_COUNT (8)
+#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
+#define BP_SSP_CMD0_CMD (0)
+#define BM_SSP_CMD0_CMD (0xff)
+#define HW_SSP_CMD1 0x020
+#define HW_SSP_XFER_SIZE 0x030
+#define HW_SSP_BLOCK_SIZE 0x040
+#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
+#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
+#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
+#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
+#define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070)
+#define BP_SSP_TIMING_TIMEOUT (16)
+#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
+#define BP_SSP_TIMING_CLOCK_DIVIDE (8)
+#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
+#define BP_SSP_TIMING_CLOCK_RATE (0)
+#define BM_SSP_TIMING_CLOCK_RATE (0xff)
+#define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080)
+#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
+#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
+#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
+#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
+#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
+#define BM_SSP_CTRL1_POLARITY (1 << 9)
+#define BP_SSP_CTRL1_WORD_LENGTH (4)
+#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
+#define BP_SSP_CTRL1_SSP_MODE (0)
+#define BM_SSP_CTRL1_SSP_MODE (0xf)
+#define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0)
+#define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0)
+#define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0)
+#define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0)
+#define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100)
+#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
+#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
+#define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130)
+#define BP_SSP_VERSION_MAJOR (24)
+
+#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
+
+#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
+ BM_SSP_CTRL1_RESP_ERR_IRQ | \
+ BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
+ BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
+ BM_SSP_CTRL1_DATA_CRC_IRQ | \
+ BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
+ BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
+ BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
+
+#define SSP_PIO_NUM 3
+
+struct mxs_mmc_host {
+ struct mmc_host *mmc;
+ struct mmc_request *mrq;
+ struct mmc_command *cmd;
+ struct mmc_data *data;
+
+ void __iomem *base;
+ int irq;
+ struct resource *res;
+ struct resource *dma_res;
+ struct clk *clk;
+ unsigned int clk_rate;
+
+ struct dma_chan *dmach;
+ struct mxs_dma_data dma_data;
+ unsigned int dma_dir;
+ u32 ssp_pio_words[SSP_PIO_NUM];
+
+ unsigned int version;
+ unsigned char bus_width;
+ spinlock_t lock;
+ int sdio_irq_en;
+};
+
+static int mxs_mmc_get_ro(struct mmc_host *mmc)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ struct mxs_mmc_platform_data *pdata =
+ mmc_dev(host->mmc)->platform_data;
+
+ if (!pdata)
+ return -EFAULT;
+
+ if (!gpio_is_valid(pdata->wp_gpio))
+ return -EINVAL;
+
+ return gpio_get_value(pdata->wp_gpio);
+}
+
+static int mxs_mmc_get_cd(struct mmc_host *mmc)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+
+ return !(readl(host->base + HW_SSP_STATUS) &
+ BM_SSP_STATUS_CARD_DETECT);
+}
+
+static void mxs_mmc_reset(struct mxs_mmc_host *host)
+{
+ u32 ctrl0, ctrl1;
+
+ mxs_reset_block(host->base);
+
+ ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
+ ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
+ BF_SSP(0x7, CTRL1_WORD_LENGTH) |
+ BM_SSP_CTRL1_DMA_ENABLE |
+ BM_SSP_CTRL1_POLARITY |
+ BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
+ BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
+ BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
+ BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
+ BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
+
+ writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
+ BF_SSP(2, TIMING_CLOCK_DIVIDE) |
+ BF_SSP(0, TIMING_CLOCK_RATE),
+ host->base + HW_SSP_TIMING);
+
+ if (host->sdio_irq_en) {
+ ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+ ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
+ }
+
+ writel(ctrl0, host->base + HW_SSP_CTRL0);
+ writel(ctrl1, host->base + HW_SSP_CTRL1);
+}
+
+static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
+ struct mmc_command *cmd);
+
+static void mxs_mmc_request_done(struct mxs_mmc_host *host)
+{
+ struct mmc_command *cmd = host->cmd;
+ struct mmc_data *data = host->data;
+ struct mmc_request *mrq = host->mrq;
+
+ if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
+ if (mmc_resp_type(cmd) & MMC_RSP_136) {
+ cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0);
+ cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1);
+ cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2);
+ cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3);
+ } else {
+ cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0);
+ }
+ }
+
+ if (data) {
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+ data->sg_len, host->dma_dir);
+ /*
+ * If there was an error on any block, we mark all
+ * data blocks as being in error.
+ */
+ if (!data->error)
+ data->bytes_xfered = data->blocks * data->blksz;
+ else
+ data->bytes_xfered = 0;
+
+ host->data = NULL;
+ if (mrq->stop) {
+ mxs_mmc_start_cmd(host, mrq->stop);
+ return;
+ }
+ }
+
+ host->mrq = NULL;
+ mmc_request_done(host->mmc, mrq);
+}
+
+static void mxs_mmc_dma_irq_callback(void *param)
+{
+ struct mxs_mmc_host *host = param;
+
+ mxs_mmc_request_done(host);
+}
+
+static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
+{
+ struct mxs_mmc_host *host = dev_id;
+ struct mmc_command *cmd = host->cmd;
+ struct mmc_data *data = host->data;
+ u32 stat;
+
+ spin_lock(&host->lock);
+
+ stat = readl(host->base + HW_SSP_CTRL1);
+ writel(stat & MXS_MMC_IRQ_BITS,
+ host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
+
+ if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
+ mmc_signal_sdio_irq(host->mmc);
+
+ spin_unlock(&host->lock);
+
+ if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
+ cmd->error = -ETIMEDOUT;
+ else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
+ cmd->error = -EIO;
+
+ if (data) {
+ if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
+ BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
+ data->error = -ETIMEDOUT;
+ else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
+ data->error = -EILSEQ;
+ else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
+ BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
+ data->error = -EIO;
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
+ struct mxs_mmc_host *host, unsigned int append)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct mmc_data *data = host->data;
+ struct scatterlist * sgl;
+ unsigned int sg_len;
+
+ if (data) {
+ /* data */
+ dma_map_sg(mmc_dev(host->mmc), data->sg,
+ data->sg_len, host->dma_dir);
+ sgl = data->sg;
+ sg_len = data->sg_len;
+ } else {
+ /* pio */
+ sgl = (struct scatterlist *) host->ssp_pio_words;
+ sg_len = SSP_PIO_NUM;
+ }
+
+ desc = host->dmach->device->device_prep_slave_sg(host->dmach,
+ sgl, sg_len, host->dma_dir, append);
+ if (desc) {
+ desc->callback = mxs_mmc_dma_irq_callback;
+ desc->callback_param = host;
+ } else {
+ if (data)
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+ data->sg_len, host->dma_dir);
+ }
+
+ return desc;
+}
+
+static void mxs_mmc_bc(struct mxs_mmc_host *host)
+{
+ struct mmc_command *cmd = host->cmd;
+ struct dma_async_tx_descriptor *desc;
+ u32 ctrl0, cmd0, cmd1;
+
+ ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
+ cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
+ cmd1 = cmd->arg;
+
+ if (host->sdio_irq_en) {
+ ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+ cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
+ }
+
+ host->ssp_pio_words[0] = ctrl0;
+ host->ssp_pio_words[1] = cmd0;
+ host->ssp_pio_words[2] = cmd1;
+ host->dma_dir = DMA_NONE;
+ desc = mxs_mmc_prep_dma(host, 0);
+ if (!desc)
+ goto out;
+
+ dmaengine_submit(desc);
+ return;
+
+out:
+ dev_warn(mmc_dev(host->mmc),
+ "%s: failed to prep dma\n", __func__);
+}
+
+static void mxs_mmc_ac(struct mxs_mmc_host *host)
+{
+ struct mmc_command *cmd = host->cmd;
+ struct dma_async_tx_descriptor *desc;
+ u32 ignore_crc, get_resp, long_resp;
+ u32 ctrl0, cmd0, cmd1;
+
+ ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
+ 0 : BM_SSP_CTRL0_IGNORE_CRC;
+ get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
+ BM_SSP_CTRL0_GET_RESP : 0;
+ long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
+ BM_SSP_CTRL0_LONG_RESP : 0;
+
+ ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
+ cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
+ cmd1 = cmd->arg;
+
+ if (host->sdio_irq_en) {
+ ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+ cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
+ }
+
+ host->ssp_pio_words[0] = ctrl0;
+ host->ssp_pio_words[1] = cmd0;
+ host->ssp_pio_words[2] = cmd1;
+ host->dma_dir = DMA_NONE;
+ desc = mxs_mmc_prep_dma(host, 0);
+ if (!desc)
+ goto out;
+
+ dmaengine_submit(desc);
+ return;
+
+out:
+ dev_warn(mmc_dev(host->mmc),
+ "%s: failed to prep dma\n", __func__);
+}
+
+static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
+{
+ const unsigned int ssp_timeout_mul = 4096;
+ /*
+ * Calculate ticks in ms since ns are large numbers
+ * and might overflow
+ */
+ const unsigned int clock_per_ms = clock_rate / 1000;
+ const unsigned int ms = ns / 1000;
+ const unsigned int ticks = ms * clock_per_ms;
+ const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
+
+ WARN_ON(ssp_ticks == 0);
+ return ssp_ticks;
+}
+
+static void mxs_mmc_adtc(struct mxs_mmc_host *host)
+{
+ struct mmc_command *cmd = host->cmd;
+ struct mmc_data *data = cmd->data;
+ struct dma_async_tx_descriptor *desc;
+ struct scatterlist *sgl = data->sg, *sg;
+ unsigned int sg_len = data->sg_len;
+ int i;
+
+ unsigned short dma_data_dir, timeout;
+ unsigned int data_size = 0, log2_blksz;
+ unsigned int blocks = data->blocks;
+
+ u32 ignore_crc, get_resp, long_resp, read;
+ u32 ctrl0, cmd0, cmd1, val;
+
+ ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
+ 0 : BM_SSP_CTRL0_IGNORE_CRC;
+ get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
+ BM_SSP_CTRL0_GET_RESP : 0;
+ long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
+ BM_SSP_CTRL0_LONG_RESP : 0;
+
+ if (data->flags & MMC_DATA_WRITE) {
+ dma_data_dir = DMA_TO_DEVICE;
+ read = 0;
+ } else {
+ dma_data_dir = DMA_FROM_DEVICE;
+ read = BM_SSP_CTRL0_READ;
+ }
+
+ ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
+ ignore_crc | get_resp | long_resp |
+ BM_SSP_CTRL0_DATA_XFER | read |
+ BM_SSP_CTRL0_WAIT_FOR_IRQ |
+ BM_SSP_CTRL0_ENABLE;
+
+ cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
+
+ /* get logarithm to base 2 of block size for setting register */
+ log2_blksz = ilog2(data->blksz);
+
+ /*
+ * take special care of the case that data size from data->sg
+ * is not equal to blocks x blksz
+ */
+ for_each_sg(sgl, sg, sg_len, i)
+ data_size += sg->length;
+
+ if (data_size != data->blocks * data->blksz)
+ blocks = 1;
+
+ /* xfer count, block size and count need to be set differently */
+ if (ssp_is_old()) {
+ ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
+ cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
+ BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
+ } else {
+ writel(data_size, host->base + HW_SSP_XFER_SIZE);
+ writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
+ BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
+ host->base + HW_SSP_BLOCK_SIZE);
+ }
+
+ if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
+ (cmd->opcode == SD_IO_RW_EXTENDED))
+ cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
+
+ cmd1 = cmd->arg;
+
+ if (host->sdio_irq_en) {
+ ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+ cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
+ }
+
+ /* set the timeout count */
+ timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
+ val = readl(host->base + HW_SSP_TIMING);
+ val &= ~(BM_SSP_TIMING_TIMEOUT);
+ val |= BF_SSP(timeout, TIMING_TIMEOUT);
+ writel(val, host->base + HW_SSP_TIMING);
+
+ /* pio */
+ host->ssp_pio_words[0] = ctrl0;
+ host->ssp_pio_words[1] = cmd0;
+ host->ssp_pio_words[2] = cmd1;
+ host->dma_dir = DMA_NONE;
+ desc = mxs_mmc_prep_dma(host, 0);
+ if (!desc)
+ goto out;
+
+ /* append data sg */
+ WARN_ON(host->data != NULL);
+ host->data = data;
+ host->dma_dir = dma_data_dir;
+ desc = mxs_mmc_prep_dma(host, 1);
+ if (!desc)
+ goto out;
+
+ dmaengine_submit(desc);
+ return;
+out:
+ dev_warn(mmc_dev(host->mmc),
+ "%s: failed to prep dma\n", __func__);
+}
+
+static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
+ struct mmc_command *cmd)
+{
+ host->cmd = cmd;
+
+ switch (mmc_cmd_type(cmd)) {
+ case MMC_CMD_BC:
+ mxs_mmc_bc(host);
+ break;
+ case MMC_CMD_BCR:
+ mxs_mmc_ac(host);
+ break;
+ case MMC_CMD_AC:
+ mxs_mmc_ac(host);
+ break;
+ case MMC_CMD_ADTC:
+ mxs_mmc_adtc(host);
+ break;
+ default:
+ dev_warn(mmc_dev(host->mmc),
+ "%s: unknown MMC command\n", __func__);
+ break;
+ }
+}
+
+static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+
+ WARN_ON(host->mrq != NULL);
+ host->mrq = mrq;
+ mxs_mmc_start_cmd(host, mrq->cmd);
+}
+
+static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
+{
+ unsigned int ssp_rate, bit_rate;
+ u32 div1, div2;
+ u32 val;
+
+ ssp_rate = clk_get_rate(host->clk);
+
+ for (div1 = 2; div1 < 254; div1 += 2) {
+ div2 = ssp_rate / rate / div1;
+ if (div2 < 0x100)
+ break;
+ }
+
+ if (div1 >= 254) {
+ dev_err(mmc_dev(host->mmc),
+ "%s: cannot set clock to %d\n", __func__, rate);
+ return;
+ }
+
+ if (div2 == 0)
+ bit_rate = ssp_rate / div1;
+ else
+ bit_rate = ssp_rate / div1 / div2;
+
+ val = readl(host->base + HW_SSP_TIMING);
+ val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
+ val |= BF_SSP(div1, TIMING_CLOCK_DIVIDE);
+ val |= BF_SSP(div2 - 1, TIMING_CLOCK_RATE);
+ writel(val, host->base + HW_SSP_TIMING);
+
+ host->clk_rate = bit_rate;
+
+ dev_dbg(mmc_dev(host->mmc),
+ "%s: div1 %d, div2 %d, ssp %d, bit %d, rate %d\n",
+ __func__, div1, div2, ssp_rate, bit_rate, rate);
+}
+
+static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+
+ if (ios->bus_width == MMC_BUS_WIDTH_8)
+ host->bus_width = 2;
+ else if (ios->bus_width == MMC_BUS_WIDTH_4)
+ host->bus_width = 1;
+ else
+ host->bus_width = 0;
+
+ if (ios->clock)
+ mxs_mmc_set_clk_rate(host, ios->clock);
+}
+
+static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ host->sdio_irq_en = enable;
+
+ if (enable) {
+ writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
+ host->base + HW_SSP_CTRL0 + MXS_SET_ADDR);
+ writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
+ host->base + HW_SSP_CTRL1 + MXS_SET_ADDR);
+
+ if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ)
+ mmc_signal_sdio_irq(host->mmc);
+
+ } else {
+ writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
+ host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR);
+ writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
+ host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static const struct mmc_host_ops mxs_mmc_ops = {
+ .request = mxs_mmc_request,
+ .get_ro = mxs_mmc_get_ro,
+ .get_cd = mxs_mmc_get_cd,
+ .set_ios = mxs_mmc_set_ios,
+ .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
+};
+
+static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
+{
+ struct mxs_mmc_host *host = param;
+
+ if (!mxs_dma_is_apbh(chan))
+ return false;
+
+ if (chan->chan_id != host->dma_res->start)
+ return false;
+
+ chan->private = &host->dma_data;
+
+ return true;
+}
+
+static int mxs_mmc_probe(struct platform_device *pdev)
+{
+ struct mxs_mmc_host *host;
+ struct mmc_host *mmc;
+ struct resource *iores, *dmares, *r;
+ struct mxs_mmc_platform_data *pdata;
+ int ret = 0, irq_err, irq_dma;
+ dma_cap_mask_t mask;
+
+ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+ irq_err = platform_get_irq(pdev, 0);
+ irq_dma = platform_get_irq(pdev, 1);
+ if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
+ return -EINVAL;
+
+ r = request_mem_region(iores->start, resource_size(iores), pdev->name);
+ if (!r)
+ return -EBUSY;
+
+ mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
+ if (!mmc) {
+ ret = -ENOMEM;
+ goto out_release_mem;
+ }
+
+ host = mmc_priv(mmc);
+ host->base = ioremap(r->start, resource_size(r));
+ if (!host->base) {
+ ret = -ENOMEM;
+ goto out_mmc_free;
+ }
+
+ /* only major verion does matter */
+ host->version = readl(host->base + HW_SSP_VERSION) >>
+ BP_SSP_VERSION_MAJOR;
+
+ host->mmc = mmc;
+ host->res = r;
+ host->dma_res = dmares;
+ host->irq = irq_err;
+ host->sdio_irq_en = 0;
+
+ host->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(host->clk)) {
+ ret = PTR_ERR(host->clk);
+ goto out_iounmap;
+ }
+ clk_enable(host->clk);
+
+ mxs_mmc_reset(host);
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+ host->dma_data.chan_irq = irq_dma;
+ host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
+ if (!host->dmach) {
+ dev_err(mmc_dev(host->mmc),
+ "%s: failed to request dma\n", __func__);
+ goto out_clk_put;
+ }
+
+ /* set mmc core parameters */
+ mmc->ops = &mxs_mmc_ops;
+ mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
+ MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
+
+ pdata = mmc_dev(host->mmc)->platform_data;
+ if (pdata) {
+ if (pdata->flags & SLOTF_8_BIT_CAPABLE)
+ mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
+ if (pdata->flags & SLOTF_4_BIT_CAPABLE)
+ mmc->caps |= MMC_CAP_4_BIT_DATA;
+ }
+
+ mmc->f_min = 400000;
+ mmc->f_max = 288000000;
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->max_segs = 52;
+ mmc->max_blk_size = 1 << 0xf;
+ mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff;
+ mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff;
+ mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
+
+ platform_set_drvdata(pdev, mmc);
+
+ ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host);
+ if (ret)
+ goto out_free_dma;
+
+ spin_lock_init(&host->lock);
+
+ ret = mmc_add_host(mmc);
+ if (ret)
+ goto out_free_irq;
+
+ dev_info(mmc_dev(host->mmc), "initialized\n");
+
+ return 0;
+
+out_free_irq:
+ free_irq(host->irq, host);
+out_free_dma:
+ if (host->dmach)
+ dma_release_channel(host->dmach);
+out_clk_put:
+ clk_disable(host->clk);
+ clk_put(host->clk);
+out_iounmap:
+ iounmap(host->base);
+out_mmc_free:
+ mmc_free_host(mmc);
+out_release_mem:
+ release_mem_region(iores->start, resource_size(iores));
+ return ret;
+}
+
+static int mxs_mmc_remove(struct platform_device *pdev)
+{
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ struct resource *res = host->res;
+
+ mmc_remove_host(mmc);
+
+ free_irq(host->irq, host);
+
+ platform_set_drvdata(pdev, NULL);
+
+ if (host->dmach)
+ dma_release_channel(host->dmach);
+
+ clk_disable(host->clk);
+ clk_put(host->clk);
+
+ iounmap(host->base);
+
+ mmc_free_host(mmc);
+
+ release_mem_region(res->start, resource_size(res));
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxs_mmc_suspend(struct device *dev)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ int ret = 0;
+
+ ret = mmc_suspend_host(mmc);
+
+ clk_disable(host->clk);
+
+ return ret;
+}
+
+static int mxs_mmc_resume(struct device *dev)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ int ret = 0;
+
+ clk_enable(host->clk);
+
+ ret = mmc_resume_host(mmc);
+
+ return ret;
+}
+
+static const struct dev_pm_ops mxs_mmc_pm_ops = {
+ .suspend = mxs_mmc_suspend,
+ .resume = mxs_mmc_resume,
+};
+#endif
+
+static struct platform_driver mxs_mmc_driver = {
+ .probe = mxs_mmc_probe,
+ .remove = mxs_mmc_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+#ifdef CONFIG_PM
+ .pm = &mxs_mmc_pm_ops,
+#endif
+ },
+};
+
+static int __init mxs_mmc_init(void)
+{
+ return platform_driver_register(&mxs_mmc_driver);
+}
+
+static void __exit mxs_mmc_exit(void)
+{
+ platform_driver_unregister(&mxs_mmc_driver);
+}
+
+module_init(mxs_mmc_init);
+module_exit(mxs_mmc_exit);
+
+MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_LICENSE("GPL");
--
1.7.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-21 10:35 ` Shawn Guo
0 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-21 10:35 UTC (permalink / raw)
To: linux-arm-kernel
This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
The driver calls into mxs-dma via generic dmaengine api for both pio
and data transfer.
Thanks Chris Ball for the indentation patch.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-mxs/include/mach/mmc.h | 18 +
drivers/mmc/host/Kconfig | 9 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/mxs-mmc.c | 874 ++++++++++++++++++++++++++++++++++
4 files changed, 902 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-mxs/include/mach/mmc.h
create mode 100644 drivers/mmc/host/mxs-mmc.c
diff --git a/arch/arm/mach-mxs/include/mach/mmc.h b/arch/arm/mach-mxs/include/mach/mmc.h
new file mode 100644
index 0000000..211547a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mmc.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MXS_MMC_H__
+#define __MACH_MXS_MMC_H__
+
+struct mxs_mmc_platform_data {
+ int wp_gpio; /* write protect pin */
+ unsigned int flags;
+#define SLOTF_4_BIT_CAPABLE (1 << 0)
+#define SLOTF_8_BIT_CAPABLE (1 << 1)
+};
+#endif /* __MACH_MXS_MMC_H__ */
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index afe8c6f..47ef75d 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -319,6 +319,15 @@ config MMC_MXC
If unsure, say N.
+config MMC_MXS
+ tristate "Freescale MXS Multimedia Card Interface support"
+ depends on ARCH_MXS && MXS_DMA
+ help
+ This selects the Freescale SSP MMC controller found on MXS based
+ platforms like mx23/28.
+
+ If unsure, say N.
+
config MMC_TIFM_SD
tristate "TI Flash Media MMC/SD Interface support (EXPERIMENTAL)"
depends on EXPERIMENTAL && PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index e834fb2..30aa686 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
obj-$(CONFIG_MMC_PXA) += pxamci.o
obj-$(CONFIG_MMC_IMX) += imxmmc.o
obj-$(CONFIG_MMC_MXC) += mxcmmc.o
+obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
obj-$(CONFIG_MMC_SDHCI_PXA) += sdhci-pxa.o
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
new file mode 100644
index 0000000..99d39a6
--- /dev/null
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -0,0 +1,874 @@
+/*
+ * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
+ * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/highmem.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/completion.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/sdio.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/mxs.h>
+#include <mach/common.h>
+#include <mach/dma.h>
+#include <mach/mmc.h>
+
+#define DRIVER_NAME "mxs-mmc"
+
+/* card detect polling timeout */
+#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
+
+#define SSP_VERSION_LATEST 4
+#define ssp_is_old() (host->version < SSP_VERSION_LATEST)
+
+/* SSP registers */
+#define HW_SSP_CTRL0 0x000
+#define BM_SSP_CTRL0_RUN (1 << 29)
+#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
+#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
+#define BM_SSP_CTRL0_READ (1 << 25)
+#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
+#define BP_SSP_CTRL0_BUS_WIDTH (22)
+#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
+#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
+#define BM_SSP_CTRL0_GET_RESP (1 << 17)
+#define BM_SSP_CTRL0_ENABLE (1 << 16)
+#define BP_SSP_CTRL0_XFER_COUNT (0)
+#define BM_SSP_CTRL0_XFER_COUNT (0xffff)
+#define HW_SSP_CMD0 0x010
+#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
+#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
+#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
+#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
+#define BP_SSP_CMD0_BLOCK_SIZE (16)
+#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
+#define BP_SSP_CMD0_BLOCK_COUNT (8)
+#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
+#define BP_SSP_CMD0_CMD (0)
+#define BM_SSP_CMD0_CMD (0xff)
+#define HW_SSP_CMD1 0x020
+#define HW_SSP_XFER_SIZE 0x030
+#define HW_SSP_BLOCK_SIZE 0x040
+#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
+#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
+#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
+#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
+#define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070)
+#define BP_SSP_TIMING_TIMEOUT (16)
+#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
+#define BP_SSP_TIMING_CLOCK_DIVIDE (8)
+#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
+#define BP_SSP_TIMING_CLOCK_RATE (0)
+#define BM_SSP_TIMING_CLOCK_RATE (0xff)
+#define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080)
+#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
+#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
+#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
+#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
+#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
+#define BM_SSP_CTRL1_POLARITY (1 << 9)
+#define BP_SSP_CTRL1_WORD_LENGTH (4)
+#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
+#define BP_SSP_CTRL1_SSP_MODE (0)
+#define BM_SSP_CTRL1_SSP_MODE (0xf)
+#define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0)
+#define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0)
+#define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0)
+#define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0)
+#define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100)
+#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
+#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
+#define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130)
+#define BP_SSP_VERSION_MAJOR (24)
+
+#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
+
+#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
+ BM_SSP_CTRL1_RESP_ERR_IRQ | \
+ BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
+ BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
+ BM_SSP_CTRL1_DATA_CRC_IRQ | \
+ BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
+ BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
+ BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
+
+#define SSP_PIO_NUM 3
+
+struct mxs_mmc_host {
+ struct mmc_host *mmc;
+ struct mmc_request *mrq;
+ struct mmc_command *cmd;
+ struct mmc_data *data;
+
+ void __iomem *base;
+ int irq;
+ struct resource *res;
+ struct resource *dma_res;
+ struct clk *clk;
+ unsigned int clk_rate;
+
+ struct dma_chan *dmach;
+ struct mxs_dma_data dma_data;
+ unsigned int dma_dir;
+ u32 ssp_pio_words[SSP_PIO_NUM];
+
+ unsigned int version;
+ unsigned char bus_width;
+ spinlock_t lock;
+ int sdio_irq_en;
+};
+
+static int mxs_mmc_get_ro(struct mmc_host *mmc)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ struct mxs_mmc_platform_data *pdata =
+ mmc_dev(host->mmc)->platform_data;
+
+ if (!pdata)
+ return -EFAULT;
+
+ if (!gpio_is_valid(pdata->wp_gpio))
+ return -EINVAL;
+
+ return gpio_get_value(pdata->wp_gpio);
+}
+
+static int mxs_mmc_get_cd(struct mmc_host *mmc)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+
+ return !(readl(host->base + HW_SSP_STATUS) &
+ BM_SSP_STATUS_CARD_DETECT);
+}
+
+static void mxs_mmc_reset(struct mxs_mmc_host *host)
+{
+ u32 ctrl0, ctrl1;
+
+ mxs_reset_block(host->base);
+
+ ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
+ ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
+ BF_SSP(0x7, CTRL1_WORD_LENGTH) |
+ BM_SSP_CTRL1_DMA_ENABLE |
+ BM_SSP_CTRL1_POLARITY |
+ BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
+ BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
+ BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
+ BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
+ BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
+
+ writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
+ BF_SSP(2, TIMING_CLOCK_DIVIDE) |
+ BF_SSP(0, TIMING_CLOCK_RATE),
+ host->base + HW_SSP_TIMING);
+
+ if (host->sdio_irq_en) {
+ ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+ ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
+ }
+
+ writel(ctrl0, host->base + HW_SSP_CTRL0);
+ writel(ctrl1, host->base + HW_SSP_CTRL1);
+}
+
+static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
+ struct mmc_command *cmd);
+
+static void mxs_mmc_request_done(struct mxs_mmc_host *host)
+{
+ struct mmc_command *cmd = host->cmd;
+ struct mmc_data *data = host->data;
+ struct mmc_request *mrq = host->mrq;
+
+ if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
+ if (mmc_resp_type(cmd) & MMC_RSP_136) {
+ cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0);
+ cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1);
+ cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2);
+ cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3);
+ } else {
+ cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0);
+ }
+ }
+
+ if (data) {
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+ data->sg_len, host->dma_dir);
+ /*
+ * If there was an error on any block, we mark all
+ * data blocks as being in error.
+ */
+ if (!data->error)
+ data->bytes_xfered = data->blocks * data->blksz;
+ else
+ data->bytes_xfered = 0;
+
+ host->data = NULL;
+ if (mrq->stop) {
+ mxs_mmc_start_cmd(host, mrq->stop);
+ return;
+ }
+ }
+
+ host->mrq = NULL;
+ mmc_request_done(host->mmc, mrq);
+}
+
+static void mxs_mmc_dma_irq_callback(void *param)
+{
+ struct mxs_mmc_host *host = param;
+
+ mxs_mmc_request_done(host);
+}
+
+static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
+{
+ struct mxs_mmc_host *host = dev_id;
+ struct mmc_command *cmd = host->cmd;
+ struct mmc_data *data = host->data;
+ u32 stat;
+
+ spin_lock(&host->lock);
+
+ stat = readl(host->base + HW_SSP_CTRL1);
+ writel(stat & MXS_MMC_IRQ_BITS,
+ host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
+
+ if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
+ mmc_signal_sdio_irq(host->mmc);
+
+ spin_unlock(&host->lock);
+
+ if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
+ cmd->error = -ETIMEDOUT;
+ else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
+ cmd->error = -EIO;
+
+ if (data) {
+ if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
+ BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
+ data->error = -ETIMEDOUT;
+ else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
+ data->error = -EILSEQ;
+ else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
+ BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
+ data->error = -EIO;
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
+ struct mxs_mmc_host *host, unsigned int append)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct mmc_data *data = host->data;
+ struct scatterlist * sgl;
+ unsigned int sg_len;
+
+ if (data) {
+ /* data */
+ dma_map_sg(mmc_dev(host->mmc), data->sg,
+ data->sg_len, host->dma_dir);
+ sgl = data->sg;
+ sg_len = data->sg_len;
+ } else {
+ /* pio */
+ sgl = (struct scatterlist *) host->ssp_pio_words;
+ sg_len = SSP_PIO_NUM;
+ }
+
+ desc = host->dmach->device->device_prep_slave_sg(host->dmach,
+ sgl, sg_len, host->dma_dir, append);
+ if (desc) {
+ desc->callback = mxs_mmc_dma_irq_callback;
+ desc->callback_param = host;
+ } else {
+ if (data)
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+ data->sg_len, host->dma_dir);
+ }
+
+ return desc;
+}
+
+static void mxs_mmc_bc(struct mxs_mmc_host *host)
+{
+ struct mmc_command *cmd = host->cmd;
+ struct dma_async_tx_descriptor *desc;
+ u32 ctrl0, cmd0, cmd1;
+
+ ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
+ cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
+ cmd1 = cmd->arg;
+
+ if (host->sdio_irq_en) {
+ ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+ cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
+ }
+
+ host->ssp_pio_words[0] = ctrl0;
+ host->ssp_pio_words[1] = cmd0;
+ host->ssp_pio_words[2] = cmd1;
+ host->dma_dir = DMA_NONE;
+ desc = mxs_mmc_prep_dma(host, 0);
+ if (!desc)
+ goto out;
+
+ dmaengine_submit(desc);
+ return;
+
+out:
+ dev_warn(mmc_dev(host->mmc),
+ "%s: failed to prep dma\n", __func__);
+}
+
+static void mxs_mmc_ac(struct mxs_mmc_host *host)
+{
+ struct mmc_command *cmd = host->cmd;
+ struct dma_async_tx_descriptor *desc;
+ u32 ignore_crc, get_resp, long_resp;
+ u32 ctrl0, cmd0, cmd1;
+
+ ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
+ 0 : BM_SSP_CTRL0_IGNORE_CRC;
+ get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
+ BM_SSP_CTRL0_GET_RESP : 0;
+ long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
+ BM_SSP_CTRL0_LONG_RESP : 0;
+
+ ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
+ cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
+ cmd1 = cmd->arg;
+
+ if (host->sdio_irq_en) {
+ ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+ cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
+ }
+
+ host->ssp_pio_words[0] = ctrl0;
+ host->ssp_pio_words[1] = cmd0;
+ host->ssp_pio_words[2] = cmd1;
+ host->dma_dir = DMA_NONE;
+ desc = mxs_mmc_prep_dma(host, 0);
+ if (!desc)
+ goto out;
+
+ dmaengine_submit(desc);
+ return;
+
+out:
+ dev_warn(mmc_dev(host->mmc),
+ "%s: failed to prep dma\n", __func__);
+}
+
+static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
+{
+ const unsigned int ssp_timeout_mul = 4096;
+ /*
+ * Calculate ticks in ms since ns are large numbers
+ * and might overflow
+ */
+ const unsigned int clock_per_ms = clock_rate / 1000;
+ const unsigned int ms = ns / 1000;
+ const unsigned int ticks = ms * clock_per_ms;
+ const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
+
+ WARN_ON(ssp_ticks == 0);
+ return ssp_ticks;
+}
+
+static void mxs_mmc_adtc(struct mxs_mmc_host *host)
+{
+ struct mmc_command *cmd = host->cmd;
+ struct mmc_data *data = cmd->data;
+ struct dma_async_tx_descriptor *desc;
+ struct scatterlist *sgl = data->sg, *sg;
+ unsigned int sg_len = data->sg_len;
+ int i;
+
+ unsigned short dma_data_dir, timeout;
+ unsigned int data_size = 0, log2_blksz;
+ unsigned int blocks = data->blocks;
+
+ u32 ignore_crc, get_resp, long_resp, read;
+ u32 ctrl0, cmd0, cmd1, val;
+
+ ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
+ 0 : BM_SSP_CTRL0_IGNORE_CRC;
+ get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
+ BM_SSP_CTRL0_GET_RESP : 0;
+ long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
+ BM_SSP_CTRL0_LONG_RESP : 0;
+
+ if (data->flags & MMC_DATA_WRITE) {
+ dma_data_dir = DMA_TO_DEVICE;
+ read = 0;
+ } else {
+ dma_data_dir = DMA_FROM_DEVICE;
+ read = BM_SSP_CTRL0_READ;
+ }
+
+ ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
+ ignore_crc | get_resp | long_resp |
+ BM_SSP_CTRL0_DATA_XFER | read |
+ BM_SSP_CTRL0_WAIT_FOR_IRQ |
+ BM_SSP_CTRL0_ENABLE;
+
+ cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
+
+ /* get logarithm to base 2 of block size for setting register */
+ log2_blksz = ilog2(data->blksz);
+
+ /*
+ * take special care of the case that data size from data->sg
+ * is not equal to blocks x blksz
+ */
+ for_each_sg(sgl, sg, sg_len, i)
+ data_size += sg->length;
+
+ if (data_size != data->blocks * data->blksz)
+ blocks = 1;
+
+ /* xfer count, block size and count need to be set differently */
+ if (ssp_is_old()) {
+ ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
+ cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
+ BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
+ } else {
+ writel(data_size, host->base + HW_SSP_XFER_SIZE);
+ writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
+ BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
+ host->base + HW_SSP_BLOCK_SIZE);
+ }
+
+ if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
+ (cmd->opcode == SD_IO_RW_EXTENDED))
+ cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
+
+ cmd1 = cmd->arg;
+
+ if (host->sdio_irq_en) {
+ ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
+ cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
+ }
+
+ /* set the timeout count */
+ timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
+ val = readl(host->base + HW_SSP_TIMING);
+ val &= ~(BM_SSP_TIMING_TIMEOUT);
+ val |= BF_SSP(timeout, TIMING_TIMEOUT);
+ writel(val, host->base + HW_SSP_TIMING);
+
+ /* pio */
+ host->ssp_pio_words[0] = ctrl0;
+ host->ssp_pio_words[1] = cmd0;
+ host->ssp_pio_words[2] = cmd1;
+ host->dma_dir = DMA_NONE;
+ desc = mxs_mmc_prep_dma(host, 0);
+ if (!desc)
+ goto out;
+
+ /* append data sg */
+ WARN_ON(host->data != NULL);
+ host->data = data;
+ host->dma_dir = dma_data_dir;
+ desc = mxs_mmc_prep_dma(host, 1);
+ if (!desc)
+ goto out;
+
+ dmaengine_submit(desc);
+ return;
+out:
+ dev_warn(mmc_dev(host->mmc),
+ "%s: failed to prep dma\n", __func__);
+}
+
+static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
+ struct mmc_command *cmd)
+{
+ host->cmd = cmd;
+
+ switch (mmc_cmd_type(cmd)) {
+ case MMC_CMD_BC:
+ mxs_mmc_bc(host);
+ break;
+ case MMC_CMD_BCR:
+ mxs_mmc_ac(host);
+ break;
+ case MMC_CMD_AC:
+ mxs_mmc_ac(host);
+ break;
+ case MMC_CMD_ADTC:
+ mxs_mmc_adtc(host);
+ break;
+ default:
+ dev_warn(mmc_dev(host->mmc),
+ "%s: unknown MMC command\n", __func__);
+ break;
+ }
+}
+
+static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+
+ WARN_ON(host->mrq != NULL);
+ host->mrq = mrq;
+ mxs_mmc_start_cmd(host, mrq->cmd);
+}
+
+static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
+{
+ unsigned int ssp_rate, bit_rate;
+ u32 div1, div2;
+ u32 val;
+
+ ssp_rate = clk_get_rate(host->clk);
+
+ for (div1 = 2; div1 < 254; div1 += 2) {
+ div2 = ssp_rate / rate / div1;
+ if (div2 < 0x100)
+ break;
+ }
+
+ if (div1 >= 254) {
+ dev_err(mmc_dev(host->mmc),
+ "%s: cannot set clock to %d\n", __func__, rate);
+ return;
+ }
+
+ if (div2 == 0)
+ bit_rate = ssp_rate / div1;
+ else
+ bit_rate = ssp_rate / div1 / div2;
+
+ val = readl(host->base + HW_SSP_TIMING);
+ val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
+ val |= BF_SSP(div1, TIMING_CLOCK_DIVIDE);
+ val |= BF_SSP(div2 - 1, TIMING_CLOCK_RATE);
+ writel(val, host->base + HW_SSP_TIMING);
+
+ host->clk_rate = bit_rate;
+
+ dev_dbg(mmc_dev(host->mmc),
+ "%s: div1 %d, div2 %d, ssp %d, bit %d, rate %d\n",
+ __func__, div1, div2, ssp_rate, bit_rate, rate);
+}
+
+static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+
+ if (ios->bus_width == MMC_BUS_WIDTH_8)
+ host->bus_width = 2;
+ else if (ios->bus_width == MMC_BUS_WIDTH_4)
+ host->bus_width = 1;
+ else
+ host->bus_width = 0;
+
+ if (ios->clock)
+ mxs_mmc_set_clk_rate(host, ios->clock);
+}
+
+static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ host->sdio_irq_en = enable;
+
+ if (enable) {
+ writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
+ host->base + HW_SSP_CTRL0 + MXS_SET_ADDR);
+ writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
+ host->base + HW_SSP_CTRL1 + MXS_SET_ADDR);
+
+ if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ)
+ mmc_signal_sdio_irq(host->mmc);
+
+ } else {
+ writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
+ host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR);
+ writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
+ host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static const struct mmc_host_ops mxs_mmc_ops = {
+ .request = mxs_mmc_request,
+ .get_ro = mxs_mmc_get_ro,
+ .get_cd = mxs_mmc_get_cd,
+ .set_ios = mxs_mmc_set_ios,
+ .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
+};
+
+static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
+{
+ struct mxs_mmc_host *host = param;
+
+ if (!mxs_dma_is_apbh(chan))
+ return false;
+
+ if (chan->chan_id != host->dma_res->start)
+ return false;
+
+ chan->private = &host->dma_data;
+
+ return true;
+}
+
+static int mxs_mmc_probe(struct platform_device *pdev)
+{
+ struct mxs_mmc_host *host;
+ struct mmc_host *mmc;
+ struct resource *iores, *dmares, *r;
+ struct mxs_mmc_platform_data *pdata;
+ int ret = 0, irq_err, irq_dma;
+ dma_cap_mask_t mask;
+
+ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+ irq_err = platform_get_irq(pdev, 0);
+ irq_dma = platform_get_irq(pdev, 1);
+ if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
+ return -EINVAL;
+
+ r = request_mem_region(iores->start, resource_size(iores), pdev->name);
+ if (!r)
+ return -EBUSY;
+
+ mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
+ if (!mmc) {
+ ret = -ENOMEM;
+ goto out_release_mem;
+ }
+
+ host = mmc_priv(mmc);
+ host->base = ioremap(r->start, resource_size(r));
+ if (!host->base) {
+ ret = -ENOMEM;
+ goto out_mmc_free;
+ }
+
+ /* only major verion does matter */
+ host->version = readl(host->base + HW_SSP_VERSION) >>
+ BP_SSP_VERSION_MAJOR;
+
+ host->mmc = mmc;
+ host->res = r;
+ host->dma_res = dmares;
+ host->irq = irq_err;
+ host->sdio_irq_en = 0;
+
+ host->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(host->clk)) {
+ ret = PTR_ERR(host->clk);
+ goto out_iounmap;
+ }
+ clk_enable(host->clk);
+
+ mxs_mmc_reset(host);
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+ host->dma_data.chan_irq = irq_dma;
+ host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
+ if (!host->dmach) {
+ dev_err(mmc_dev(host->mmc),
+ "%s: failed to request dma\n", __func__);
+ goto out_clk_put;
+ }
+
+ /* set mmc core parameters */
+ mmc->ops = &mxs_mmc_ops;
+ mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
+ MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
+
+ pdata = mmc_dev(host->mmc)->platform_data;
+ if (pdata) {
+ if (pdata->flags & SLOTF_8_BIT_CAPABLE)
+ mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
+ if (pdata->flags & SLOTF_4_BIT_CAPABLE)
+ mmc->caps |= MMC_CAP_4_BIT_DATA;
+ }
+
+ mmc->f_min = 400000;
+ mmc->f_max = 288000000;
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->max_segs = 52;
+ mmc->max_blk_size = 1 << 0xf;
+ mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff;
+ mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff;
+ mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
+
+ platform_set_drvdata(pdev, mmc);
+
+ ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host);
+ if (ret)
+ goto out_free_dma;
+
+ spin_lock_init(&host->lock);
+
+ ret = mmc_add_host(mmc);
+ if (ret)
+ goto out_free_irq;
+
+ dev_info(mmc_dev(host->mmc), "initialized\n");
+
+ return 0;
+
+out_free_irq:
+ free_irq(host->irq, host);
+out_free_dma:
+ if (host->dmach)
+ dma_release_channel(host->dmach);
+out_clk_put:
+ clk_disable(host->clk);
+ clk_put(host->clk);
+out_iounmap:
+ iounmap(host->base);
+out_mmc_free:
+ mmc_free_host(mmc);
+out_release_mem:
+ release_mem_region(iores->start, resource_size(iores));
+ return ret;
+}
+
+static int mxs_mmc_remove(struct platform_device *pdev)
+{
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ struct resource *res = host->res;
+
+ mmc_remove_host(mmc);
+
+ free_irq(host->irq, host);
+
+ platform_set_drvdata(pdev, NULL);
+
+ if (host->dmach)
+ dma_release_channel(host->dmach);
+
+ clk_disable(host->clk);
+ clk_put(host->clk);
+
+ iounmap(host->base);
+
+ mmc_free_host(mmc);
+
+ release_mem_region(res->start, resource_size(res));
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxs_mmc_suspend(struct device *dev)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ int ret = 0;
+
+ ret = mmc_suspend_host(mmc);
+
+ clk_disable(host->clk);
+
+ return ret;
+}
+
+static int mxs_mmc_resume(struct device *dev)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+ struct mxs_mmc_host *host = mmc_priv(mmc);
+ int ret = 0;
+
+ clk_enable(host->clk);
+
+ ret = mmc_resume_host(mmc);
+
+ return ret;
+}
+
+static const struct dev_pm_ops mxs_mmc_pm_ops = {
+ .suspend = mxs_mmc_suspend,
+ .resume = mxs_mmc_resume,
+};
+#endif
+
+static struct platform_driver mxs_mmc_driver = {
+ .probe = mxs_mmc_probe,
+ .remove = mxs_mmc_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+#ifdef CONFIG_PM
+ .pm = &mxs_mmc_pm_ops,
+#endif
+ },
+};
+
+static int __init mxs_mmc_init(void)
+{
+ return platform_driver_register(&mxs_mmc_driver);
+}
+
+static void __exit mxs_mmc_exit(void)
+{
+ platform_driver_unregister(&mxs_mmc_driver);
+}
+
+module_init(mxs_mmc_init);
+module_exit(mxs_mmc_exit);
+
+MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_LICENSE("GPL");
--
1.7.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-21 10:35 ` Shawn Guo
@ 2011-02-21 17:40 ` Wolfram Sang
-1 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2011-02-21 17:40 UTC (permalink / raw)
To: Shawn Guo; +Cc: linux-mmc, linux-arm-kernel, cjb, arnd, linux
[-- Attachment #1: Type: text/plain, Size: 821 bytes --]
Shawn,
On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> The driver calls into mxs-dma via generic dmaengine api for both pio
> and data transfer.
>
> Thanks Chris Ball for the indentation patch.
>
> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
What throughput rates do you get on a mx28-regulated slot serving a card
at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
board issue though (or we can fix it later), rest works fine, thus:
Tested-by: Wolfram Sang <w.sang@pengutronix.de>
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-21 17:40 ` Wolfram Sang
0 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2011-02-21 17:40 UTC (permalink / raw)
To: linux-arm-kernel
Shawn,
On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> The driver calls into mxs-dma via generic dmaengine api for both pio
> and data transfer.
>
> Thanks Chris Ball for the indentation patch.
>
> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
What throughput rates do you get on a mx28-regulated slot serving a card
at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
board issue though (or we can fix it later), rest works fine, thus:
Tested-by: Wolfram Sang <w.sang@pengutronix.de>
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
-------------- next part --------------
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-21 17:40 ` Wolfram Sang
@ 2011-02-22 8:09 ` Shawn Guo
-1 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-22 8:09 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-mmc, cjb, linux, linux-arm-kernel, arnd
Hi Wolfram,
On Mon, Feb 21, 2011 at 06:40:16PM +0100, Wolfram Sang wrote:
> Shawn,
>
> On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> > This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> > The driver calls into mxs-dma via generic dmaengine api for both pio
> > and data transfer.
> >
> > Thanks Chris Ball for the indentation patch.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>
> What throughput rates do you get on a mx28-regulated slot serving a card
> at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
To make sure we are on the same page, can you share me the test you
ran? And I can give it a try on my board.
> board issue though (or we can fix it later), rest works fine, thus:
>
> Tested-by: Wolfram Sang <w.sang@pengutronix.de>
>
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-22 8:09 ` Shawn Guo
0 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-22 8:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi Wolfram,
On Mon, Feb 21, 2011 at 06:40:16PM +0100, Wolfram Sang wrote:
> Shawn,
>
> On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> > This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> > The driver calls into mxs-dma via generic dmaengine api for both pio
> > and data transfer.
> >
> > Thanks Chris Ball for the indentation patch.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>
> What throughput rates do you get on a mx28-regulated slot serving a card
> at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
To make sure we are on the same page, can you share me the test you
ran? And I can give it a try on my board.
> board issue though (or we can fix it later), rest works fine, thus:
>
> Tested-by: Wolfram Sang <w.sang@pengutronix.de>
>
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-21 17:40 ` Wolfram Sang
@ 2011-02-22 8:52 ` Shawn Guo
-1 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-22 8:52 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux, cjb, linux-mmc, arnd, linux-arm-kernel
Hi Wolfram,
On Mon, Feb 21, 2011 at 06:40:16PM +0100, Wolfram Sang wrote:
> Shawn,
>
> On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> > This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> > The driver calls into mxs-dma via generic dmaengine api for both pio
> > and data transfer.
> >
> > Thanks Chris Ball for the indentation patch.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>
> What throughput rates do you get on a mx28-regulated slot serving a card
> at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
To make sure we are on the same test, can you share the test case
you ran to get the result? So that I can run it here for the result
on my board.
> board issue though (or we can fix it later), rest works fine, thus:
>
> Tested-by: Wolfram Sang <w.sang@pengutronix.de>
>
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-22 8:52 ` Shawn Guo
0 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-22 8:52 UTC (permalink / raw)
To: linux-arm-kernel
Hi Wolfram,
On Mon, Feb 21, 2011 at 06:40:16PM +0100, Wolfram Sang wrote:
> Shawn,
>
> On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> > This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> > The driver calls into mxs-dma via generic dmaengine api for both pio
> > and data transfer.
> >
> > Thanks Chris Ball for the indentation patch.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>
> What throughput rates do you get on a mx28-regulated slot serving a card
> at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
To make sure we are on the same test, can you share the test case
you ran to get the result? So that I can run it here for the result
on my board.
> board issue though (or we can fix it later), rest works fine, thus:
>
> Tested-by: Wolfram Sang <w.sang@pengutronix.de>
>
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-22 8:52 ` Shawn Guo
@ 2011-02-22 10:33 ` Wolfram Sang
-1 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2011-02-22 10:33 UTC (permalink / raw)
To: Shawn Guo; +Cc: linux-mmc, cjb, linux, linux-arm-kernel, arnd
[-- Attachment #1: Type: text/plain, Size: 906 bytes --]
> > What throughput rates do you get on a mx28-regulated slot serving a card
> > at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
>
> To make sure we are on the same test, can you share the test case
> you ran to get the result? So that I can run it here for the result
> on my board.
# mount -t vfat /dev/mmcblk0p1 /mnt
# dd if=/mnt/test.dat of=/tmp/a bs=1024
# umount /mnt
# ./dd --version
dd (coreutils) 8.5
...
'test.dat' was a 8MB file of random data on a 4GB SDHC card
(extrememory) on a slot powered by the mx28. Operating the card at
50Mhz, dd will report ~55 kb/s. If I add 'rate /= 2;' to the beginning
of set_clk_rate, so it will operate at 25Mhz, I have 8mb/s.
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-22 10:33 ` Wolfram Sang
0 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2011-02-22 10:33 UTC (permalink / raw)
To: linux-arm-kernel
> > What throughput rates do you get on a mx28-regulated slot serving a card
> > at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
>
> To make sure we are on the same test, can you share the test case
> you ran to get the result? So that I can run it here for the result
> on my board.
# mount -t vfat /dev/mmcblk0p1 /mnt
# dd if=/mnt/test.dat of=/tmp/a bs=1024
# umount /mnt
# ./dd --version
dd (coreutils) 8.5
...
'test.dat' was a 8MB file of random data on a 4GB SDHC card
(extrememory) on a slot powered by the mx28. Operating the card at
50Mhz, dd will report ~55 kb/s. If I add 'rate /= 2;' to the beginning
of set_clk_rate, so it will operate at 25Mhz, I have 8mb/s.
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
-------------- next part --------------
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-22 10:33 ` Wolfram Sang
@ 2011-02-22 11:50 ` Shawn Guo
-1 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-22 11:50 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-mmc, cjb, linux, linux-arm-kernel, arnd
On Tue, Feb 22, 2011 at 11:33:49AM +0100, Wolfram Sang wrote:
>
> > > What throughput rates do you get on a mx28-regulated slot serving a card
> > > at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
> >
> > To make sure we are on the same test, can you share the test case
> > you ran to get the result? So that I can run it here for the result
> > on my board.
>
> # mount -t vfat /dev/mmcblk0p1 /mnt
> # dd if=/mnt/test.dat of=/tmp/a bs=1024
> # umount /mnt
> # ./dd --version
> dd (coreutils) 8.5
> ...
>
> 'test.dat' was a 8MB file of random data on a 4GB SDHC card
> (extrememory) on a slot powered by the mx28. Operating the card at
> 50Mhz, dd will report ~55 kb/s. If I add 'rate /= 2;' to the beginning
> of set_clk_rate, so it will operate at 25Mhz, I have 8mb/s.
>
My busybox version of dd does not report the speed. But I tried to
dd 8MB data and saw it's done in 1~2 seconds.
Also here is mmc host driver test performance related result on my
board if you are interested.
mmc0: Test case 23. Best-case read performance...
mmc0: Transfer of 6630 sectors (3315 KiB) took 0.101999209 seconds (33280 kB/s,
32500 KiB/s)
mmc0: Result: OK
mmc0: Test case 24. Best-case write performance...
mmc0: Transfer of 6630 sectors (3315 KiB) took 0.388688317 seconds (8733 kB/s, 8
528 KiB/s)
mmc0: Result: OK
mmc0: Test case 25. Best-case read performance into scattered pages...
mmc0: Transfer of 416 sectors (208 KiB) took 0.006997933 seconds (30436 kB/s, 29
723 KiB/s)
mmc0: Result: OK
mmc0: Test case 26. Best-case write performance from scattered pages...
mmc0: Transfer of 416 sectors (208 KiB) took 0.020431605 seconds (10424 kB/s, 10
180 KiB/s)
mmc0: Result: OK
mmc0: Test case 27. Single read performance by transfer size...
mmc0: Transfer of 1 sectors (0.5 KiB) took 0.000906524 seconds (564 kB/s, 551 Ki
B/s)
mmc0: Transfer of 2 sectors (1 KiB) took 0.000625190 seconds (1637 kB/s, 1599 Ki
B/s)
mmc0: Transfer of 4 sectors (2 KiB) took 0.000687706 seconds (2978 kB/s, 2908 Ki
B/s)
mmc0: Transfer of 8 sectors (4 KiB) took 0.000718959 seconds (5697 kB/s, 5563 Ki
B/s)
mmc0: Transfer of 16 sectors (8 KiB) took 0.000812729 seconds (10079 kB/s, 9843
KiB/s)
mmc0: Transfer of 32 sectors (16 KiB) took 0.001094051 seconds (14975 kB/s, 1462
4 KiB/s)
mmc0: Transfer of 64 sectors (32 KiB) took 0.001625434 seconds (20159 kB/s, 1968
7 KiB/s)
mmc0: Transfer of 128 sectors (64 KiB) took 0.002594421 seconds (25260 kB/s, 246
68 KiB/s)
mmc0: Transfer of 256 sectors (128 KiB) took 0.004563644 seconds (28720 kB/s, 28
047 KiB/s)
mmc0: Transfer of 512 sectors (256 KiB) took 0.008439521 seconds (31061 kB/s, 30
333 KiB/s)
mmc0: Transfer of 1024 sectors (512 KiB) took 0.016253622 seconds (32256 kB/s, 3
1500 KiB/s)
mmc0: Transfer of 2048 sectors (1024 KiB) took 0.031886943 seconds (32884 kB/s,
32113 KiB/s)
mmc0: Transfer of 4096 sectors (2048 KiB) took 0.063176177 seconds (33195 kB/s,
32417 KiB/s)
mmc0: Transfer of 6630 sectors (3315 KiB) took 0.101735514 seconds (33366 kB/s,
32584 KiB/s)
mmc0: Result: OK
mmc0: Test case 28. Single write performance by transfer size...
mmc0: Transfer of 1 sectors (0.5 KiB) took 0.001781476 seconds (287 kB/s, 280 Ki
B/s)
mmc0: Transfer of 2 sectors (1 KiB) took 0.002250249 seconds (455 kB/s, 444 KiB/
s)
mmc0: Transfer of 4 sectors (2 KiB) took 0.002312719 seconds (885 kB/s, 864 KiB/
s)
mmc0: Transfer of 8 sectors (4 KiB) took 0.003437771 seconds (1191 kB/s, 1163 Ki
B/s)
mmc0: Transfer of 16 sectors (8 KiB) took 0.002718920 seconds (3012 kB/s, 2942 K
iB/s)
mmc0: Transfer of 32 sectors (16 KiB) took 0.001500142 seconds (10921 kB/s, 1066
5 KiB/s)
mmc0: Transfer of 64 sectors (32 KiB) took 0.003875336 seconds (8455 kB/s, 8257
KiB/s)
mmc0: Transfer of 128 sectors (64 KiB) took 0.006250472 seconds (10484 kB/s, 102
39 KiB/s)
mmc0: Transfer of 256 sectors (128 KiB) took 0.011563288 seconds (11335 kB/s, 11
069 KiB/s)
mmc0: Transfer of 512 sectors (256 KiB) took 0.022187432 seconds (11814 kB/s, 11
538 KiB/s)
mmc0: Transfer of 1024 sectors (512 KiB) took 0.049155884 seconds (10665 kB/s, 1
0415 KiB/s)
mmc0: Transfer of 2048 sectors (1024 KiB) took 0.085375335 seconds (12281 kB/s,
11994 KiB/s)
mmc0: Transfer of 4096 sectors (2048 KiB) took 0.262563987 seconds (7987 kB/s, 7
800 KiB/s)
mmc0: Transfer of 6630 sectors (3315 KiB) took 0.284787038 seconds (11919 kB/s,
11640 KiB/s)
mmc0: Result: OK
mmc0: Test case 29. Single trim performance by transfer size...
mmc0: Result: UNSUPPORTED (by card)
mmc0: Test case 30. Consecutive read performance by transfer size...
mmc0: Transfer of 8192 x 1 sectors (8192 x 0.5 KiB) took 4.091141441 seconds (10
25 kB/s, 1001 KiB/s)
mmc0: Transfer of 4096 x 2 sectors (4096 x 1 KiB) took 2.490875000 seconds (1683
kB/s, 1644 KiB/s)
mmc0: Transfer of 2048 x 4 sectors (2048 x 2 KiB) took 1.316531250 seconds (3185
kB/s, 3111 KiB/s)
mmc0: Transfer of 1024 x 8 sectors (1024 x 4 KiB) took 0.727437500 seconds (5765
kB/s, 5630 KiB/s)
mmc0: Transfer of 512 x 16 sectors (512 x 8 KiB) took 0.437000000 seconds (9597
kB/s, 9372 KiB/s)
mmc0: Transfer of 256 x 32 sectors (256 x 16 KiB) took 0.283156250 seconds (1481
2 kB/s, 14465 KiB/s)
mmc0: Transfer of 128 x 64 sectors (128 x 32 KiB) took 0.205812500 seconds (2037
9 kB/s, 19901 KiB/s)
mmc0: Transfer of 64 x 128 sectors (64 x 64 KiB) took 0.165750000 seconds (25305
kB/s, 24711 KiB/s)
mmc0: Transfer of 32 x 256 sectors (32 x 128 KiB) took 0.145343750 seconds (2885
7 kB/s, 28181 KiB/s)
mmc0: Transfer of 16 x 512 sectors (16 x 256 KiB) took 0.134968750 seconds (3107
6 kB/s, 30347 KiB/s)
mmc0: Transfer of 8 x 1024 sectors (8 x 512 KiB) took 0.130125000 seconds (32232
kB/s, 31477 KiB/s)
mmc0: Transfer of 4 x 2048 sectors (4 x 1024 KiB) took 0.127531249 seconds (3288
8 kB/s, 32117 KiB/s)
mmc0: Transfer of 2 x 4096 sectors (2 x 2048 KiB) took 0.126343751 seconds (3319
7 kB/s, 32419 KiB/s)
mmc0: Transfer of 1 x 6630 sectors (1 x 3315 KiB) took 0.101687494 seconds (3338
2 kB/s, 32599 KiB/s)
mmc0: Result: OK
mmc0: Test case 31. Consecutive write performance by transfer size...
mmc0: Transfer of 8192 x 1 sectors (8192 x 0.5 KiB) took 14.309562500 seconds (2
93 kB/s, 286 KiB/s)
mmc0: Transfer of 4096 x 2 sectors (4096 x 1 KiB) took 9.871062499 seconds (424
kB/s, 414 KiB/s)
mmc0: Transfer of 2048 x 4 sectors (2048 x 2 KiB) took 4.814593750 seconds (871
kB/s, 850 KiB/s)
mmc0: Transfer of 1024 x 8 sectors (1024 x 4 KiB) took 2.296875000 seconds (1826
kB/s, 1783 KiB/s)
mmc0: Transfer of 512 x 16 sectors (512 x 8 KiB) took 1.072843750 seconds (3909
kB/s, 3817 KiB/s)
mmc0: Transfer of 256 x 32 sectors (256 x 16 KiB) took 0.596312500 seconds (7033
kB/s, 6868 KiB/s)
mmc0: Transfer of 128 x 64 sectors (128 x 32 KiB) took 0.455375000 seconds (9210
kB/s, 8994 KiB/s)
mmc0: Transfer of 64 x 128 sectors (64 x 64 KiB) took 0.402875000 seconds (10410
kB/s, 10166 KiB/s)
mmc0: Transfer of 32 x 256 sectors (32 x 128 KiB) took 0.375531250 seconds (1116
8 kB/s, 10907 KiB/s)
mmc0: Transfer of 16 x 512 sectors (16 x 256 KiB) took 0.362562500 seconds (1156
8 kB/s, 11297 KiB/s)
mmc0: Transfer of 8 x 1024 sectors (8 x 512 KiB) took 0.350500000 seconds (11966
kB/s, 11686 KiB/s)
mmc0: Transfer of 4 x 2048 sectors (4 x 1024 KiB) took 0.351593796 seconds (1192
9 kB/s, 11649 KiB/s)
mmc0: Transfer of 2 x 4096 sectors (2 x 2048 KiB) took 0.346812955 seconds (1209
3 kB/s, 11810 KiB/s)
mmc0: Transfer of 1 x 6630 sectors (1 x 3315 KiB) took 0.280838757 seconds (1208
7 kB/s, 11803 KiB/s)
mmc0: Result: OK
mmc0: Test case 32. Consecutive trim performance by transfer size...
mmc0: Result: UNSUPPORTED (by card)
mmc0: Tests completed.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-22 11:50 ` Shawn Guo
0 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-22 11:50 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Feb 22, 2011 at 11:33:49AM +0100, Wolfram Sang wrote:
>
> > > What throughput rates do you get on a mx28-regulated slot serving a card
> > > at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
> >
> > To make sure we are on the same test, can you share the test case
> > you ran to get the result? So that I can run it here for the result
> > on my board.
>
> # mount -t vfat /dev/mmcblk0p1 /mnt
> # dd if=/mnt/test.dat of=/tmp/a bs=1024
> # umount /mnt
> # ./dd --version
> dd (coreutils) 8.5
> ...
>
> 'test.dat' was a 8MB file of random data on a 4GB SDHC card
> (extrememory) on a slot powered by the mx28. Operating the card at
> 50Mhz, dd will report ~55 kb/s. If I add 'rate /= 2;' to the beginning
> of set_clk_rate, so it will operate at 25Mhz, I have 8mb/s.
>
My busybox version of dd does not report the speed. But I tried to
dd 8MB data and saw it's done in 1~2 seconds.
Also here is mmc host driver test performance related result on my
board if you are interested.
mmc0: Test case 23. Best-case read performance...
mmc0: Transfer of 6630 sectors (3315 KiB) took 0.101999209 seconds (33280 kB/s,
32500 KiB/s)
mmc0: Result: OK
mmc0: Test case 24. Best-case write performance...
mmc0: Transfer of 6630 sectors (3315 KiB) took 0.388688317 seconds (8733 kB/s, 8
528 KiB/s)
mmc0: Result: OK
mmc0: Test case 25. Best-case read performance into scattered pages...
mmc0: Transfer of 416 sectors (208 KiB) took 0.006997933 seconds (30436 kB/s, 29
723 KiB/s)
mmc0: Result: OK
mmc0: Test case 26. Best-case write performance from scattered pages...
mmc0: Transfer of 416 sectors (208 KiB) took 0.020431605 seconds (10424 kB/s, 10
180 KiB/s)
mmc0: Result: OK
mmc0: Test case 27. Single read performance by transfer size...
mmc0: Transfer of 1 sectors (0.5 KiB) took 0.000906524 seconds (564 kB/s, 551 Ki
B/s)
mmc0: Transfer of 2 sectors (1 KiB) took 0.000625190 seconds (1637 kB/s, 1599 Ki
B/s)
mmc0: Transfer of 4 sectors (2 KiB) took 0.000687706 seconds (2978 kB/s, 2908 Ki
B/s)
mmc0: Transfer of 8 sectors (4 KiB) took 0.000718959 seconds (5697 kB/s, 5563 Ki
B/s)
mmc0: Transfer of 16 sectors (8 KiB) took 0.000812729 seconds (10079 kB/s, 9843
KiB/s)
mmc0: Transfer of 32 sectors (16 KiB) took 0.001094051 seconds (14975 kB/s, 1462
4 KiB/s)
mmc0: Transfer of 64 sectors (32 KiB) took 0.001625434 seconds (20159 kB/s, 1968
7 KiB/s)
mmc0: Transfer of 128 sectors (64 KiB) took 0.002594421 seconds (25260 kB/s, 246
68 KiB/s)
mmc0: Transfer of 256 sectors (128 KiB) took 0.004563644 seconds (28720 kB/s, 28
047 KiB/s)
mmc0: Transfer of 512 sectors (256 KiB) took 0.008439521 seconds (31061 kB/s, 30
333 KiB/s)
mmc0: Transfer of 1024 sectors (512 KiB) took 0.016253622 seconds (32256 kB/s, 3
1500 KiB/s)
mmc0: Transfer of 2048 sectors (1024 KiB) took 0.031886943 seconds (32884 kB/s,
32113 KiB/s)
mmc0: Transfer of 4096 sectors (2048 KiB) took 0.063176177 seconds (33195 kB/s,
32417 KiB/s)
mmc0: Transfer of 6630 sectors (3315 KiB) took 0.101735514 seconds (33366 kB/s,
32584 KiB/s)
mmc0: Result: OK
mmc0: Test case 28. Single write performance by transfer size...
mmc0: Transfer of 1 sectors (0.5 KiB) took 0.001781476 seconds (287 kB/s, 280 Ki
B/s)
mmc0: Transfer of 2 sectors (1 KiB) took 0.002250249 seconds (455 kB/s, 444 KiB/
s)
mmc0: Transfer of 4 sectors (2 KiB) took 0.002312719 seconds (885 kB/s, 864 KiB/
s)
mmc0: Transfer of 8 sectors (4 KiB) took 0.003437771 seconds (1191 kB/s, 1163 Ki
B/s)
mmc0: Transfer of 16 sectors (8 KiB) took 0.002718920 seconds (3012 kB/s, 2942 K
iB/s)
mmc0: Transfer of 32 sectors (16 KiB) took 0.001500142 seconds (10921 kB/s, 1066
5 KiB/s)
mmc0: Transfer of 64 sectors (32 KiB) took 0.003875336 seconds (8455 kB/s, 8257
KiB/s)
mmc0: Transfer of 128 sectors (64 KiB) took 0.006250472 seconds (10484 kB/s, 102
39 KiB/s)
mmc0: Transfer of 256 sectors (128 KiB) took 0.011563288 seconds (11335 kB/s, 11
069 KiB/s)
mmc0: Transfer of 512 sectors (256 KiB) took 0.022187432 seconds (11814 kB/s, 11
538 KiB/s)
mmc0: Transfer of 1024 sectors (512 KiB) took 0.049155884 seconds (10665 kB/s, 1
0415 KiB/s)
mmc0: Transfer of 2048 sectors (1024 KiB) took 0.085375335 seconds (12281 kB/s,
11994 KiB/s)
mmc0: Transfer of 4096 sectors (2048 KiB) took 0.262563987 seconds (7987 kB/s, 7
800 KiB/s)
mmc0: Transfer of 6630 sectors (3315 KiB) took 0.284787038 seconds (11919 kB/s,
11640 KiB/s)
mmc0: Result: OK
mmc0: Test case 29. Single trim performance by transfer size...
mmc0: Result: UNSUPPORTED (by card)
mmc0: Test case 30. Consecutive read performance by transfer size...
mmc0: Transfer of 8192 x 1 sectors (8192 x 0.5 KiB) took 4.091141441 seconds (10
25 kB/s, 1001 KiB/s)
mmc0: Transfer of 4096 x 2 sectors (4096 x 1 KiB) took 2.490875000 seconds (1683
kB/s, 1644 KiB/s)
mmc0: Transfer of 2048 x 4 sectors (2048 x 2 KiB) took 1.316531250 seconds (3185
kB/s, 3111 KiB/s)
mmc0: Transfer of 1024 x 8 sectors (1024 x 4 KiB) took 0.727437500 seconds (5765
kB/s, 5630 KiB/s)
mmc0: Transfer of 512 x 16 sectors (512 x 8 KiB) took 0.437000000 seconds (9597
kB/s, 9372 KiB/s)
mmc0: Transfer of 256 x 32 sectors (256 x 16 KiB) took 0.283156250 seconds (1481
2 kB/s, 14465 KiB/s)
mmc0: Transfer of 128 x 64 sectors (128 x 32 KiB) took 0.205812500 seconds (2037
9 kB/s, 19901 KiB/s)
mmc0: Transfer of 64 x 128 sectors (64 x 64 KiB) took 0.165750000 seconds (25305
kB/s, 24711 KiB/s)
mmc0: Transfer of 32 x 256 sectors (32 x 128 KiB) took 0.145343750 seconds (2885
7 kB/s, 28181 KiB/s)
mmc0: Transfer of 16 x 512 sectors (16 x 256 KiB) took 0.134968750 seconds (3107
6 kB/s, 30347 KiB/s)
mmc0: Transfer of 8 x 1024 sectors (8 x 512 KiB) took 0.130125000 seconds (32232
kB/s, 31477 KiB/s)
mmc0: Transfer of 4 x 2048 sectors (4 x 1024 KiB) took 0.127531249 seconds (3288
8 kB/s, 32117 KiB/s)
mmc0: Transfer of 2 x 4096 sectors (2 x 2048 KiB) took 0.126343751 seconds (3319
7 kB/s, 32419 KiB/s)
mmc0: Transfer of 1 x 6630 sectors (1 x 3315 KiB) took 0.101687494 seconds (3338
2 kB/s, 32599 KiB/s)
mmc0: Result: OK
mmc0: Test case 31. Consecutive write performance by transfer size...
mmc0: Transfer of 8192 x 1 sectors (8192 x 0.5 KiB) took 14.309562500 seconds (2
93 kB/s, 286 KiB/s)
mmc0: Transfer of 4096 x 2 sectors (4096 x 1 KiB) took 9.871062499 seconds (424
kB/s, 414 KiB/s)
mmc0: Transfer of 2048 x 4 sectors (2048 x 2 KiB) took 4.814593750 seconds (871
kB/s, 850 KiB/s)
mmc0: Transfer of 1024 x 8 sectors (1024 x 4 KiB) took 2.296875000 seconds (1826
kB/s, 1783 KiB/s)
mmc0: Transfer of 512 x 16 sectors (512 x 8 KiB) took 1.072843750 seconds (3909
kB/s, 3817 KiB/s)
mmc0: Transfer of 256 x 32 sectors (256 x 16 KiB) took 0.596312500 seconds (7033
kB/s, 6868 KiB/s)
mmc0: Transfer of 128 x 64 sectors (128 x 32 KiB) took 0.455375000 seconds (9210
kB/s, 8994 KiB/s)
mmc0: Transfer of 64 x 128 sectors (64 x 64 KiB) took 0.402875000 seconds (10410
kB/s, 10166 KiB/s)
mmc0: Transfer of 32 x 256 sectors (32 x 128 KiB) took 0.375531250 seconds (1116
8 kB/s, 10907 KiB/s)
mmc0: Transfer of 16 x 512 sectors (16 x 256 KiB) took 0.362562500 seconds (1156
8 kB/s, 11297 KiB/s)
mmc0: Transfer of 8 x 1024 sectors (8 x 512 KiB) took 0.350500000 seconds (11966
kB/s, 11686 KiB/s)
mmc0: Transfer of 4 x 2048 sectors (4 x 1024 KiB) took 0.351593796 seconds (1192
9 kB/s, 11649 KiB/s)
mmc0: Transfer of 2 x 4096 sectors (2 x 2048 KiB) took 0.346812955 seconds (1209
3 kB/s, 11810 KiB/s)
mmc0: Transfer of 1 x 6630 sectors (1 x 3315 KiB) took 0.280838757 seconds (1208
7 kB/s, 11803 KiB/s)
mmc0: Result: OK
mmc0: Test case 32. Consecutive trim performance by transfer size...
mmc0: Result: UNSUPPORTED (by card)
mmc0: Tests completed.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-22 11:50 ` Shawn Guo
@ 2011-02-22 11:57 ` Wolfram Sang
-1 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2011-02-22 11:57 UTC (permalink / raw)
To: Shawn Guo; +Cc: linux-mmc, cjb, linux, linux-arm-kernel, arnd
[-- Attachment #1: Type: text/plain, Size: 486 bytes --]
> My busybox version of dd does not report the speed. But I tried to
> dd 8MB data and saw it's done in 1~2 seconds.
>
> Also here is mmc host driver test performance related result on my
> board if you are interested.
OK, looks good. Let's merge the driver then and I will check my board.
Thanks!
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-22 11:57 ` Wolfram Sang
0 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2011-02-22 11:57 UTC (permalink / raw)
To: linux-arm-kernel
> My busybox version of dd does not report the speed. But I tried to
> dd 8MB data and saw it's done in 1~2 seconds.
>
> Also here is mmc host driver test performance related result on my
> board if you are interested.
OK, looks good. Let's merge the driver then and I will check my board.
Thanks!
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
-------------- next part --------------
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-21 10:35 ` Shawn Guo
@ 2011-02-22 15:26 ` Chris Ball
-1 siblings, 0 replies; 22+ messages in thread
From: Chris Ball @ 2011-02-22 15:26 UTC (permalink / raw)
To: Shawn Guo; +Cc: linux-mmc, linux-arm-kernel, arnd, w.sang, linux
Hi Shawn,
On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> The driver calls into mxs-dma via generic dmaengine api for both pio
> and data transfer.
Thanks very much, pushed to mmc-next for .39.
--
Chris Ball <cjb@laptop.org> <http://printf.net/>
One Laptop Per Child
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-22 15:26 ` Chris Ball
0 siblings, 0 replies; 22+ messages in thread
From: Chris Ball @ 2011-02-22 15:26 UTC (permalink / raw)
To: linux-arm-kernel
Hi Shawn,
On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> The driver calls into mxs-dma via generic dmaengine api for both pio
> and data transfer.
Thanks very much, pushed to mmc-next for .39.
--
Chris Ball <cjb@laptop.org> <http://printf.net/>
One Laptop Per Child
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-22 10:33 ` Wolfram Sang
@ 2011-02-22 16:15 ` Arnd Bergmann
-1 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2011-02-22 16:15 UTC (permalink / raw)
To: Wolfram Sang; +Cc: Shawn Guo, linux-mmc, cjb, linux, linux-arm-kernel
On Tuesday 22 February 2011, Wolfram Sang wrote:
> # mount -t vfat /dev/mmcblk0p1 /mnt
> # dd if=/mnt/test.dat of=/tmp/a bs=1024
> # umount /mnt
> # ./dd --version
> dd (coreutils) 8.5
In general, you should try to rule out file system, garbage collection,
partitioning and cache effects.
With coreutils dd, a good command is
dd if=/dev/zero of=/dev/mmcblk0 bs=64K count=64 seek=256 oflag=direct
* Always write multiples of 4 MB to avoid garbage collection
* smaller block sizes may be faster, so writing 64 times 64K may
be better than writing 4 MB once, depending on the card
* don't write to the FAT area, so start writing at 16 MB into the
device.
* use direct I/O to bypass the page cache.
* read from /dev/zero instead of a disk file to avoid measuring the
wrong thing
Arnd
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-22 16:15 ` Arnd Bergmann
0 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2011-02-22 16:15 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday 22 February 2011, Wolfram Sang wrote:
> # mount -t vfat /dev/mmcblk0p1 /mnt
> # dd if=/mnt/test.dat of=/tmp/a bs=1024
> # umount /mnt
> # ./dd --version
> dd (coreutils) 8.5
In general, you should try to rule out file system, garbage collection,
partitioning and cache effects.
With coreutils dd, a good command is
dd if=/dev/zero of=/dev/mmcblk0 bs=64K count=64 seek=256 oflag=direct
* Always write multiples of 4 MB to avoid garbage collection
* smaller block sizes may be faster, so writing 64 times 64K may
be better than writing 4 MB once, depending on the card
* don't write to the FAT area, so start writing at 16 MB into the
device.
* use direct I/O to bypass the page cache.
* read from /dev/zero instead of a disk file to avoid measuring the
wrong thing
Arnd
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-22 16:15 ` Arnd Bergmann
@ 2011-02-22 16:36 ` Wolfram Sang
-1 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2011-02-22 16:36 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: Shawn Guo, linux-mmc, cjb, linux, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 862 bytes --]
On Tue, Feb 22, 2011 at 05:15:07PM +0100, Arnd Bergmann wrote:
> On Tuesday 22 February 2011, Wolfram Sang wrote:
> > # mount -t vfat /dev/mmcblk0p1 /mnt
> > # dd if=/mnt/test.dat of=/tmp/a bs=1024
> > # umount /mnt
> > # ./dd --version
> > dd (coreutils) 8.5
>
> In general, you should try to rule out file system, garbage collection,
> partitioning and cache effects.
Yes, right, I am aware of that (well, most of it ;)). I simplified my
testcase here, because I was sure by previous tests it was only
dependent on the frequency requested by the card. Remember, I wasn't
after maximum values but chasing a difference in read performance of two
magnitudes.
Thanks,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-22 16:36 ` Wolfram Sang
0 siblings, 0 replies; 22+ messages in thread
From: Wolfram Sang @ 2011-02-22 16:36 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Feb 22, 2011 at 05:15:07PM +0100, Arnd Bergmann wrote:
> On Tuesday 22 February 2011, Wolfram Sang wrote:
> > # mount -t vfat /dev/mmcblk0p1 /mnt
> > # dd if=/mnt/test.dat of=/tmp/a bs=1024
> > # umount /mnt
> > # ./dd --version
> > dd (coreutils) 8.5
>
> In general, you should try to rule out file system, garbage collection,
> partitioning and cache effects.
Yes, right, I am aware of that (well, most of it ;)). I simplified my
testcase here, because I was sure by previous tests it was only
dependent on the frequency requested by the card. Remember, I wasn't
after maximum values but chasing a difference in read performance of two
magnitudes.
Thanks,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
-------------- next part --------------
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
2011-02-22 8:09 ` Shawn Guo
@ 2011-02-24 13:48 ` Shawn Guo
-1 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-24 13:48 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-mmc, cjb, linux, linux-arm-kernel, arnd
Please ignore the message which is the one I sent a few days ago
and I thought it did not get through.
On Tue, Feb 22, 2011 at 04:09:06PM +0800, Shawn Guo wrote:
> Hi Wolfram,
>
> On Mon, Feb 21, 2011 at 06:40:16PM +0100, Wolfram Sang wrote:
> > Shawn,
> >
> > On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> > > This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> > > The driver calls into mxs-dma via generic dmaengine api for both pio
> > > and data transfer.
> > >
> > > Thanks Chris Ball for the indentation patch.
> > >
> > > Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > > Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> >
> > What throughput rates do you get on a mx28-regulated slot serving a card
> > at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
>
> To make sure we are on the same page, can you share me the test you
> ran? And I can give it a try on my board.
>
> > board issue though (or we can fix it later), rest works fine, thus:
> >
> > Tested-by: Wolfram Sang <w.sang@pengutronix.de>
> >
>
> --
> Regards,
> Shawn
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28
@ 2011-02-24 13:48 ` Shawn Guo
0 siblings, 0 replies; 22+ messages in thread
From: Shawn Guo @ 2011-02-24 13:48 UTC (permalink / raw)
To: linux-arm-kernel
Please ignore the message which is the one I sent a few days ago
and I thought it did not get through.
On Tue, Feb 22, 2011 at 04:09:06PM +0800, Shawn Guo wrote:
> Hi Wolfram,
>
> On Mon, Feb 21, 2011 at 06:40:16PM +0100, Wolfram Sang wrote:
> > Shawn,
> >
> > On Mon, Feb 21, 2011 at 06:35:28PM +0800, Shawn Guo wrote:
> > > This adds the mmc host driver for Freescale MXS-based SoC i.MX23/28.
> > > The driver calls into mxs-dma via generic dmaengine api for both pio
> > > and data transfer.
> > >
> > > Thanks Chris Ball for the indentation patch.
> > >
> > > Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > > Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> >
> > What throughput rates do you get on a mx28-regulated slot serving a card
> > at 50Mhz? This is poor here (55kb/s) while it is OK at 25Mhz. Could be a
>
> To make sure we are on the same page, can you share me the test you
> ran? And I can give it a try on my board.
>
> > board issue though (or we can fix it later), rest works fine, thus:
> >
> > Tested-by: Wolfram Sang <w.sang@pengutronix.de>
> >
>
> --
> Regards,
> Shawn
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2011-02-24 13:48 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-02-21 10:35 [PATCH v3] mmc: mxs-mmc: add mmc host driver for i.MX23/28 Shawn Guo
2011-02-21 10:35 ` Shawn Guo
2011-02-21 17:40 ` Wolfram Sang
2011-02-21 17:40 ` Wolfram Sang
2011-02-22 8:09 ` Shawn Guo
2011-02-22 8:09 ` Shawn Guo
2011-02-24 13:48 ` Shawn Guo
2011-02-24 13:48 ` Shawn Guo
2011-02-22 8:52 ` Shawn Guo
2011-02-22 8:52 ` Shawn Guo
2011-02-22 10:33 ` Wolfram Sang
2011-02-22 10:33 ` Wolfram Sang
2011-02-22 11:50 ` Shawn Guo
2011-02-22 11:50 ` Shawn Guo
2011-02-22 11:57 ` Wolfram Sang
2011-02-22 11:57 ` Wolfram Sang
2011-02-22 16:15 ` Arnd Bergmann
2011-02-22 16:15 ` Arnd Bergmann
2011-02-22 16:36 ` Wolfram Sang
2011-02-22 16:36 ` Wolfram Sang
2011-02-22 15:26 ` Chris Ball
2011-02-22 15:26 ` Chris Ball
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