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* [PATCH] drm/i915: use i915_enable_rc6 on SNB too
@ 2011-03-30 21:08 Jesse Barnes
  2011-03-30 21:32 ` Ben Widawsky
  0 siblings, 1 reply; 3+ messages in thread
From: Jesse Barnes @ 2011-03-30 21:08 UTC (permalink / raw)
  To: intel-gfx

For debug & testing.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 32b41b4..1268c6a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6842,7 +6842,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
 {
 	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
-	u32 pcu_mbox;
+	u32 pcu_mbox, rc6_mask = 0;
 	int cur_freq, min_freq, max_freq;
 	int i;
 
@@ -6873,9 +6873,12 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
 	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
+	if (i915_enable_rc6)
+		rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
+			GEN6_RC_CTL_RC6_ENABLE;
+
 	I915_WRITE(GEN6_RC_CONTROL,
-		   GEN6_RC_CTL_RC6p_ENABLE |
-		   GEN6_RC_CTL_RC6_ENABLE |
+		   rc6_mask |
 		   GEN6_RC_CTL_EI_MODE(1) |
 		   GEN6_RC_CTL_HW_ENABLE);
 
-- 
1.7.1

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH] drm/i915: use i915_enable_rc6 on SNB too
  2011-03-30 21:08 [PATCH] drm/i915: use i915_enable_rc6 on SNB too Jesse Barnes
@ 2011-03-30 21:32 ` Ben Widawsky
  2011-03-30 21:45   ` Jesse Barnes
  0 siblings, 1 reply; 3+ messages in thread
From: Ben Widawsky @ 2011-03-30 21:32 UTC (permalink / raw)
  To: Jesse Barnes; +Cc: intel-gfx

On Wed, Mar 30, 2011 at 02:08:56PM -0700, Jesse Barnes wrote:
> For debug & testing.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---

>  	I915_WRITE(GEN6_RC_CONTROL,
> -		   GEN6_RC_CTL_RC6p_ENABLE |
> -		   GEN6_RC_CTL_RC6_ENABLE |
> +		   rc6_mask |
>  		   GEN6_RC_CTL_EI_MODE(1) |
>  		   GEN6_RC_CTL_HW_ENABLE);
> 

Do you also need to set GEN6_RC_CTL_RC7_ENABLE if !i915_enable_rc6? I
don't really know how the hardware works, but I had a similar untested
patch except I added that bit in the rc6 disable case.

Otherwise, you can my r-b:
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] drm/i915: use i915_enable_rc6 on SNB too
  2011-03-30 21:32 ` Ben Widawsky
@ 2011-03-30 21:45   ` Jesse Barnes
  0 siblings, 0 replies; 3+ messages in thread
From: Jesse Barnes @ 2011-03-30 21:45 UTC (permalink / raw)
  To: Ben Widawsky; +Cc: intel-gfx

On Wed, 30 Mar 2011 14:32:51 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On Wed, Mar 30, 2011 at 02:08:56PM -0700, Jesse Barnes wrote:
> > For debug & testing.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> 
> >  	I915_WRITE(GEN6_RC_CONTROL,
> > -		   GEN6_RC_CTL_RC6p_ENABLE |
> > -		   GEN6_RC_CTL_RC6_ENABLE |
> > +		   rc6_mask |
> >  		   GEN6_RC_CTL_EI_MODE(1) |
> >  		   GEN6_RC_CTL_HW_ENABLE);
> > 
> 
> Do you also need to set GEN6_RC_CTL_RC7_ENABLE if !i915_enable_rc6? I
> don't really know how the hardware works, but I had a similar untested
> patch except I added that bit in the rc6 disable case.

That seems to control LLC way sharing between GT and the CPU; not sure
if switching to an RC7 message is correct or not if RC6 is disabled
though.

-- 
Jesse Barnes, Intel Open Source Technology Center

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2011-03-30 22:42 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2011-03-30 21:08 [PATCH] drm/i915: use i915_enable_rc6 on SNB too Jesse Barnes
2011-03-30 21:32 ` Ben Widawsky
2011-03-30 21:45   ` Jesse Barnes

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