[Qemu-devel] [PATCH 1/4] [arm] trivial whitespace/indentation fixes

* [Qemu-devel] [PATCH 1/4] [arm] trivial whitespace/indentation fixes
@ 2011-04-13 16:38 Lluís
  2011-04-13 16:38 ` [Qemu-devel] [PATCH 2/4] [arm] move helpers.h to helper.h Lluís
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Lluís @ 2011-04-13 16:38 UTC (permalink / raw)
  To: qemu-devel; +Cc: aurelien

Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
 target-arm/helper.c        |  246 ++++++++++++++++++++++----------------------
 target-arm/iwmmxt_helper.c |   28 +++--
 target-arm/translate.c     |   26 ++---
 3 files changed, 150 insertions(+), 150 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9172fc7..d2e0bf4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -959,7 +959,7 @@ static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
 }
 
 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
-			    int is_user, uint32_t *phys_ptr, int *prot,
+                            int is_user, uint32_t *phys_ptr, int *prot,
                             target_ulong *page_size)
 {
     int code;
@@ -996,13 +996,13 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
         *page_size = 1024 * 1024;
     } else {
         /* Lookup l2 entry.  */
-	if (type == 1) {
-	    /* Coarse pagetable.  */
-	    table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
-	} else {
-	    /* Fine pagetable.  */
-	    table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
-	}
+        if (type == 1) {
+            /* Coarse pagetable.  */
+            table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
+        } else {
+            /* Fine pagetable.  */
+            table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
+        }
         desc = ldl_phys(table);
         switch (desc & 3) {
         case 0: /* Page translation fault.  */
@@ -1019,17 +1019,17 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
             *page_size = 0x1000;
             break;
         case 3: /* 1k page.  */
-	    if (type == 1) {
-		if (arm_feature(env, ARM_FEATURE_XSCALE)) {
-		    phys_addr = (desc & 0xfffff000) | (address & 0xfff);
-		} else {
-		    /* Page translation fault.  */
-		    code = 7;
-		    goto do_fault;
-		}
-	    } else {
-		phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
-	    }
+            if (type == 1) {
+                if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+                    phys_addr = (desc & 0xfffff000) | (address & 0xfff);
+                } else {
+                    /* Page translation fault.  */
+                    code = 7;
+                    goto do_fault;
+                }
+            } else {
+                phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
+            }
             ap = (desc >> 4) & 3;
             *page_size = 0x400;
             break;
@@ -1052,7 +1052,7 @@ do_fault:
 }
 
 static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
-			    int is_user, uint32_t *phys_ptr, int *prot,
+                            int is_user, uint32_t *phys_ptr, int *prot,
                             target_ulong *page_size)
 {
     int code;
@@ -1155,7 +1155,7 @@ do_fault:
 }
 
 static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
-			     int is_user, uint32_t *phys_ptr, int *prot)
+                             int is_user, uint32_t *phys_ptr, int *prot)
 {
     int n;
     uint32_t mask;
@@ -1163,52 +1163,52 @@ static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
 
     *phys_ptr = address;
     for (n = 7; n >= 0; n--) {
-	base = env->cp15.c6_region[n];
-	if ((base & 1) == 0)
-	    continue;
-	mask = 1 << ((base >> 1) & 0x1f);
-	/* Keep this shift separate from the above to avoid an
-	   (undefined) << 32.  */
-	mask = (mask << 1) - 1;
-	if (((base ^ address) & ~mask) == 0)
-	    break;
+        base = env->cp15.c6_region[n];
+        if ((base & 1) == 0)
+            continue;
+        mask = 1 << ((base >> 1) & 0x1f);
+        /* Keep this shift separate from the above to avoid an
+           (undefined) << 32.  */
+        mask = (mask << 1) - 1;
+        if (((base ^ address) & ~mask) == 0)
+            break;
     }
     if (n < 0)
-	return 2;
+        return 2;
 
     if (access_type == 2) {
-	mask = env->cp15.c5_insn;
+        mask = env->cp15.c5_insn;
     } else {
-	mask = env->cp15.c5_data;
+        mask = env->cp15.c5_data;
     }
     mask = (mask >> (n * 4)) & 0xf;
     switch (mask) {
     case 0:
-	return 1;
+        return 1;
     case 1:
-	if (is_user)
-	  return 1;
-	*prot = PAGE_READ | PAGE_WRITE;
-	break;
+        if (is_user)
+          return 1;
+        *prot = PAGE_READ | PAGE_WRITE;
+        break;
     case 2:
-	*prot = PAGE_READ;
-	if (!is_user)
-	    *prot |= PAGE_WRITE;
-	break;
+        *prot = PAGE_READ;
+        if (!is_user)
+            *prot |= PAGE_WRITE;
+        break;
     case 3:
-	*prot = PAGE_READ | PAGE_WRITE;
-	break;
+        *prot = PAGE_READ | PAGE_WRITE;
+        break;
     case 5:
-	if (is_user)
-	    return 1;
-	*prot = PAGE_READ;
-	break;
+        if (is_user)
+            return 1;
+        *prot = PAGE_READ;
+        break;
     case 6:
-	*prot = PAGE_READ;
-	break;
+        *prot = PAGE_READ;
+        break;
     default:
-	/* Bad permission.  */
-	return 1;
+        /* Bad permission.  */
+        return 1;
     }
     *prot |= PAGE_EXEC;
     return 0;
@@ -1231,8 +1231,8 @@ static inline int get_phys_addr(CPUState *env, uint32_t address,
         return 0;
     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
         *page_size = TARGET_PAGE_SIZE;
-	return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
-				 prot);
+        return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
+                                 prot);
     } else if (env->cp15.c1_sys & (1 << 23)) {
         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
                                 prot, page_size);
@@ -1411,22 +1411,22 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
                 goto bad_reg;
             }
         } else {
-	    switch (op2) {
-	    case 0:
-		env->cp15.c2_base0 = val;
-		break;
-	    case 1:
-		env->cp15.c2_base1 = val;
-		break;
-	    case 2:
+            switch (op2) {
+            case 0:
+                env->cp15.c2_base0 = val;
+                break;
+            case 1:
+                env->cp15.c2_base1 = val;
+                break;
+            case 2:
                 val &= 7;
                 env->cp15.c2_control = val;
-		env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
+                env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
                 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
-		break;
-	    default:
-		goto bad_reg;
-	    }
+                break;
+            default:
+                goto bad_reg;
+            }
         }
         break;
     case 3: /* MMU Domain access control / MPU write buffer control.  */
@@ -1555,26 +1555,26 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
             break;
         switch (crm) {
         case 0: /* Cache lockdown.  */
-	    switch (op1) {
-	    case 0: /* L1 cache.  */
-		switch (op2) {
-		case 0:
-		    env->cp15.c9_data = val;
-		    break;
-		case 1:
-		    env->cp15.c9_insn = val;
-		    break;
-		default:
-		    goto bad_reg;
-		}
-		break;
-	    case 1: /* L2 cache.  */
-		/* Ignore writes to L2 lockdown/auxiliary registers.  */
-		break;
-	    default:
-		goto bad_reg;
-	    }
-	    break;
+            switch (op1) {
+            case 0: /* L1 cache.  */
+                switch (op2) {
+                case 0:
+                    env->cp15.c9_data = val;
+                    break;
+                case 1:
+                    env->cp15.c9_insn = val;
+                    break;
+                default:
+                    goto bad_reg;
+                }
+                break;
+            case 1: /* L2 cache.  */
+                /* Ignore writes to L2 lockdown/auxiliary registers.  */
+                break;
+            default:
+                goto bad_reg;
+            }
+            break;
         case 1: /* TCM memory region registers.  */
             /* Not implemented.  */
             goto bad_reg;
@@ -1675,7 +1675,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
                 case 0: /* Device ID.  */
                     return env->cp15.c0_cpuid;
                 case 1: /* Cache Type.  */
-		    return env->cp15.c0_cachetype;
+                    return env->cp15.c0_cachetype;
                 case 2: /* TCM status.  */
                     return 0;
                 case 3: /* TLB type register.  */
@@ -1790,17 +1790,17 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
                 goto bad_reg;
             }
         } else {
-	    switch (op2) {
-	    case 0:
-		return env->cp15.c2_base0;
-	    case 1:
-		return env->cp15.c2_base1;
-	    case 2:
+            switch (op2) {
+            case 0:
+                return env->cp15.c2_base0;
+            case 1:
+                return env->cp15.c2_base1;
+            case 2:
                 return env->cp15.c2_control;
-	    default:
-		goto bad_reg;
-	    }
-	}
+            default:
+                goto bad_reg;
+            }
+        }
     case 3: /* MMU Domain access control / MPU write buffer control.  */
         return env->cp15.c3;
     case 4: /* Reserved.  */
@@ -1836,29 +1836,29 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
         } else {
             if (arm_feature(env, ARM_FEATURE_OMAPCP))
                 op2 = 0;
-	    switch (op2) {
-	    case 0:
-		return env->cp15.c6_data;
-	    case 1:
-		if (arm_feature(env, ARM_FEATURE_V6)) {
-		    /* Watchpoint Fault Adrress.  */
-		    return 0; /* Not implemented.  */
-		} else {
-		    /* Instruction Fault Adrress.  */
-		    /* Arm9 doesn't have an IFAR, but implementing it anyway
-		       shouldn't do any harm.  */
-		    return env->cp15.c6_insn;
-		}
-	    case 2:
-		if (arm_feature(env, ARM_FEATURE_V6)) {
-		    /* Instruction Fault Adrress.  */
-		    return env->cp15.c6_insn;
-		} else {
-		    goto bad_reg;
-		}
-	    default:
-		goto bad_reg;
-	    }
+            switch (op2) {
+            case 0:
+                return env->cp15.c6_data;
+            case 1:
+                if (arm_feature(env, ARM_FEATURE_V6)) {
+                    /* Watchpoint Fault Adrress.  */
+                    return 0; /* Not implemented.  */
+                } else {
+                    /* Instruction Fault Adrress.  */
+                    /* Arm9 doesn't have an IFAR, but implementing it anyway
+                       shouldn't do any harm.  */
+                    return env->cp15.c6_insn;
+                }
+            case 2:
+                if (arm_feature(env, ARM_FEATURE_V6)) {
+                    /* Instruction Fault Adrress.  */
+                    return env->cp15.c6_insn;
+                } else {
+                    goto bad_reg;
+                }
+            default:
+                goto bad_reg;
+            }
         }
     case 7: /* Cache control.  */
         if (crm == 4 && op1 == 0 && op2 == 0) {
@@ -1872,8 +1872,8 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
     case 9: /* Cache lockdown.  */
         switch (op1) {
         case 0: /* L1 cache.  */
-	    if (arm_feature(env, ARM_FEATURE_OMAPCP))
-		return 0;
+            if (arm_feature(env, ARM_FEATURE_OMAPCP))
+                return 0;
             switch (op2) {
             case 0:
                 return env->cp15.c9_data;
diff --git a/target-arm/iwmmxt_helper.c b/target-arm/iwmmxt_helper.c
index 3941f1f..b13ffc7 100644
--- a/target-arm/iwmmxt_helper.c
+++ b/target-arm/iwmmxt_helper.c
@@ -164,13 +164,13 @@ uint64_t HELPER(iwmmxt_macuw)(uint64_t a, uint64_t b)
 #define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3)			\
 uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(uint64_t a, uint64_t b) \
 {								\
-    a =							        \
+    a =                                                         \
         (((a >> SH0) & 0xff) << 0) | (((b >> SH0) & 0xff) << 8) |	\
         (((a >> SH1) & 0xff) << 16) | (((b >> SH1) & 0xff) << 24) |	\
         (((a >> SH2) & 0xff) << 32) | (((b >> SH2) & 0xff) << 40) |	\
         (((a >> SH3) & 0xff) << 48) | (((b >> SH3) & 0xff) << 56);	\
     env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
-        NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |		        \
+        NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |                 \
         NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |		\
         NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |		\
         NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7);		\
@@ -178,10 +178,10 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(uint64_t a, uint64_t b) \
 }								\
 uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(uint64_t a, uint64_t b) \
 {								\
-    a =							        \
+    a =                                                         \
         (((a >> SH0) & 0xffff) << 0) |				\
-        (((b >> SH0) & 0xffff) << 16) |			        \
-        (((a >> SH2) & 0xffff) << 32) |			        \
+        (((b >> SH0) & 0xffff) << 16) |                         \
+        (((a >> SH2) & 0xffff) << 32) |                         \
         (((b >> SH2) & 0xffff) << 48);				\
     env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
         NZBIT8(a >> 0, 0) | NZBIT8(a >> 16, 1) |		\
@@ -190,7 +190,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(uint64_t a, uint64_t b) \
 }								\
 uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(uint64_t a, uint64_t b) \
 {								\
-    a =							        \
+    a =                                                         \
         (((a >> SH0) & 0xffffffff) << 0) |			\
         (((b >> SH0) & 0xffffffff) << 32);			\
     env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
@@ -199,7 +199,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(uint64_t a, uint64_t b) \
 }								\
 uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(uint64_t x)   \
 {								\
-    x =							        \
+    x =                                                         \
         (((x >> SH0) & 0xff) << 0) |				\
         (((x >> SH1) & 0xff) << 16) |				\
         (((x >> SH2) & 0xff) << 32) |				\
@@ -211,7 +211,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(uint64_t x)   \
 }								\
 uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(uint64_t x)   \
 {								\
-    x =							        \
+    x =                                                         \
         (((x >> SH0) & 0xffff) << 0) |				\
         (((x >> SH2) & 0xffff) << 32);				\
     env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
@@ -226,11 +226,11 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(uint64_t x)   \
 }								\
 uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(uint64_t x)   \
 {								\
-    x =							        \
-        ((uint64_t) EXTEND8H((x >> SH0) & 0xff) << 0) |	        \
+    x =                                                         \
+        ((uint64_t) EXTEND8H((x >> SH0) & 0xff) << 0) |         \
         ((uint64_t) EXTEND8H((x >> SH1) & 0xff) << 16) |	\
         ((uint64_t) EXTEND8H((x >> SH2) & 0xff) << 32) |	\
-        ((uint64_t) EXTEND8H((x >> SH3) & 0xff) << 48);	        \
+        ((uint64_t) EXTEND8H((x >> SH3) & 0xff) << 48);         \
     env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
         NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |		\
         NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);		\
@@ -238,7 +238,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(uint64_t x)   \
 }								\
 uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(uint64_t x)   \
 {								\
-    x =							        \
+    x =                                                         \
         ((uint64_t) EXTEND16((x >> SH0) & 0xffff) << 0) |	\
         ((uint64_t) EXTEND16((x >> SH2) & 0xffff) << 32);	\
     env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
@@ -257,13 +257,13 @@ IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)
 #define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O)			\
 uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(uint64_t a, uint64_t b) \
 {								\
-    a =							        \
+    a =                                                         \
         CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) |		\
         CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) |		\
         CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) |		\
         CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff);		\
     env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
-        NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |		        \
+        NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |                 \
         NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |		\
         NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |		\
         NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7);		\
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6190028..cf59d63 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2516,7 +2516,7 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
 
     /* M profile cores use memory mapped registers instead of cp15.  */
     if (arm_feature(env, ARM_FEATURE_M))
-	return 1;
+        return 1;
 
     if ((insn & (1 << 25)) == 0) {
         if (insn & (1 << 20)) {
@@ -6186,21 +6186,21 @@ static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
 
     cpnum = (insn >> 8) & 0xf;
     if (arm_feature(env, ARM_FEATURE_XSCALE)
-	    && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
-	return 1;
+            && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
+        return 1;
 
     switch (cpnum) {
       case 0:
       case 1:
-	if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
-	    return disas_iwmmxt_insn(env, s, insn);
-	} else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
-	    return disas_dsp_insn(env, s, insn);
-	}
-	return 1;
+        if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+            return disas_iwmmxt_insn(env, s, insn);
+        } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+            return disas_dsp_insn(env, s, insn);
+        }
+        return 1;
     case 10:
     case 11:
-	return disas_vfp_insn (env, s, insn);
+        return disas_vfp_insn (env, s, insn);
     case 14:
         /* Coprocessors 7-15 are architecturally reserved by ARM.
            Unfortunately Intel decided to ignore this.  */
@@ -6211,11 +6211,11 @@ static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
         else
             return disas_cp14_write(env, s, insn);
     case 15:
-	return disas_cp15_insn (env, s, insn);
+        return disas_cp15_insn (env, s, insn);
     default:
     board:
-	/* Unknown coprocessor.  See if the board has hooked it.  */
-	return disas_cp_insn (env, s, insn);
+        /* Unknown coprocessor.  See if the board has hooked it.  */
+        return disas_cp_insn (env, s, insn);
     }
 }
 

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