VMA of processes and CPU registers

VMA of processes and CPU registers

[limp]

Hi all,

I know that each user processes has a number of virtual memory areas (VMA)
which consist its (virtual memory) address space. For example cat
/proc/1426/maps will return the (virtual memory) address space of the
process 1426.

What I don't know for sure is if the actual CPU registers contain the
virtual address of a running process or the "translated" by MMU physical
address. 

I think that every access to a VA must be resolved to a corresponding PA so
I guess the CPU registers will deal with the physical addresses rather than
the virtual ones but I wanted to be sure about it.

Thank you all for your help.

John K.

VMA of processes and CPU registers

[Dave Hylands]

Hi John,

On Tue, Apr 19, 2011 at 3:56 PM, limp <johnkyr83@hotmail.com> wrote:
> Hi all,
>
> I know that each user processes has a number of virtual memory areas (VMA)
> which consist its (virtual memory) address space. For example cat
> /proc/1426/maps will return the (virtual memory) address space of the
> process 1426.
>
> What I don't know for sure is if the actual CPU registers contain the
> virtual address of a running process or the "translated" by MMU physical
> address.
>
> I think that every access to a VA must be resolved to a corresponding PA so
> I guess the CPU registers will deal with the physical addresses rather than
> the virtual ones but I wanted to be sure about it.

The CPU registers will contain the virtual addresses. Each and every
time that the CPU tries to access a virtual memory location, then the
address will be translated by the MMU into a physical address.

Generally speaking. the only time you actually deal with physical
addresses is when you're setting up the MMU, and when programming
hardware (like DMA) which accesses memory without going through the
MMU.

-- 
Dave Hylands
Shuswap, BC, Canada
http://www.davehylands.com

VMA of processes and CPU registers

[limp]

Thanks a lot Dace and Vladimir for your replies.

First of all, I forgot to mention that I am talking for x86 architecture.

> The CPU registers will contain the virtual addresses. Each and every
> time that the CPU tries to access a virtual memory location, then the
> address will be translated by the MMU into a physical address.

So, AFAIU the translation to physical memory takes place *only* when the ALU
of the processor has to do some operation which has memory operands (in
this case the CPU needs to deal with the *real* addresses) but not prior to
that.

Now if, for example, EIP has the value of 0xB71B13E8 and I know that on
B70CC000-B71B7000 the libX11.so is linked, then the IP points to the 0xE53E8
(0xB71B13E8 - B70CC000) offset of libX11.so? Is that right?

Thanks again for all the useful help.

John K.


-----Original Message-----
From: Dave Hylands [mailto:dhylands at gmail.com] 
Sent: Wednesday, April 20, 2011 12:20 AM
To: limp
Cc: kernelnewbies at kernelnewbies.org
Subject: Re: VMA of processes and CPU registers

Hi John,

On Tue, Apr 19, 2011 at 3:56 PM, limp <johnkyr83@hotmail.com> wrote:
> Hi all,
>
> I know that each user processes has a number of virtual memory areas (VMA)
> which consist its (virtual memory) address space. For example cat
> /proc/1426/maps will return the (virtual memory) address space of the
> process 1426.
>
> What I don't know for sure is if the actual CPU registers contain the
> virtual address of a running process or the "translated" by MMU physical
> address.
>
> I think that every access to a VA must be resolved to a corresponding PA
so
> I guess the CPU registers will deal with the physical addresses rather
than
> the virtual ones but I wanted to be sure about it.

The CPU registers will contain the virtual addresses. Each and every
time that the CPU tries to access a virtual memory location, then the
address will be translated by the MMU into a physical address.

Generally speaking. the only time you actually deal with physical
addresses is when you're setting up the MMU, and when programming
hardware (like DMA) which accesses memory without going through the
MMU.

-- 
Dave Hylands
Shuswap, BC, Canada
http://www.davehylands.com

VMA of processes and CPU registers

[mindentropy]

On Wednesday 20 Apr 2011 4:31:08 pm limp wrote:
> Thanks a lot Dace and Vladimir for your replies.
> 
> First of all, I forgot to mention that I am talking for x86 architecture.
> 
> > The CPU registers will contain the virtual addresses. Each and every
> > time that the CPU tries to access a virtual memory location, then the
> > address will be translated by the MMU into a physical address.
> 
> So, AFAIU the translation to physical memory takes place *only* when the
> ALU of the processor has to do some operation which has memory operands
> (in this case the CPU needs to deal with the *real* addresses) but not
> prior to that.
> 

The address translation happens in the following way:

Logical Addr-->|Segmentation Unit|-->Linear Addr -->|Paging unit|--> Physical 
Addr.

If the paging unit is not setup then the linear addr is the physical addr.

VMA of processes and CPU registers

[Dave Hylands]

Hi John,

On Wed, Apr 20, 2011 at 4:01 AM, limp <johnkyr83@hotmail.com> wrote:
> Thanks a lot Dace and Vladimir for your replies.
>
> First of all, I forgot to mention that I am talking for x86 architecture.

I think that this is true for all of the architectures I've worked
with (ARM, MIPS, x86). Some architectures (like MIPS) have a
combination of spaces which are linearly mapped between virtual and
physical, and mapped spaces (which go through an MMU). ARM can switch
back and forth by enabling and disabling the MMU, but when running
under linux, the MMU is always on.

>> The CPU registers will contain the virtual addresses. Each and every
>> time that the CPU tries to access a virtual memory location, then the
>> address will be translated by the MMU into a physical address.
>
> So, AFAIU the translation to physical memory takes place *only* when the ALU
> of the processor has to do some operation which has memory operands (in
> this case the CPU needs to deal with the *real* addresses) but not prior to
> that.
>
> Now if, for example, EIP has the value of 0xB71B13E8 and I know that on
> B70CC000-B71B7000 the libX11.so is linked, then the IP points to the 0xE53E8
> (0xB71B13E8 - B70CC000) offset of libX11.so? Is that right?

Correct.

-- 
Dave Hylands
Shuswap, BC, Canada
http://www.davehylands.com

VMA of processes and CPU registers

[mindentropy]

On Wednesday 20 Apr 2011 11:00:17 pm Dave Hylands wrote:
 
> I think that this is true for all of the architectures I've worked
> with (ARM, MIPS, x86). Some architectures (like MIPS) have a
> combination of spaces which are linearly mapped between virtual and
> physical, and mapped spaces (which go through an MMU). 

Is this just identity mapping or does it bypass the paging unit for some 
addresses? Just out of curiosity how do you tell the bypassing info?

VMA of processes and CPU registers

[Dave Hylands]

Hi,

On Wed, Apr 20, 2011 at 11:08 AM, mindentropy <mindentropy@gmail.com> wrote:
> On Wednesday 20 Apr 2011 11:00:17 pm Dave Hylands wrote:
>
>> I think that this is true for all of the architectures I've worked
>> with (ARM, MIPS, x86). Some architectures (like MIPS) have a
>> combination of spaces which are linearly mapped between virtual and
>> physical, and mapped spaces (which go through an MMU).
>
> Is this just identity mapping or does it bypass the paging unit for some
> addresses? Just out of curiosity how do you tell the bypassing info?

On the MIPS core I was working with (which I think was R3000 based),
they use the upper 2 or 3 bits of the address to determine the type of
access.

This page has the details (the table about 1/3 of the way down the web page):
<http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/mips.html>

-- 
Dave Hylands
Shuswap, BC, Canada
http://www.davehylands.com

VMA of processes and CPU registers

[mindentropy]

On Thursday 21 Apr 2011 6:52:29 am Dave Hylands wrote:
> Hi,
> 
> On Wed, Apr 20, 2011 at 11:08 AM, mindentropy <mindentropy@gmail.com> wrote:
> > On Wednesday 20 Apr 2011 11:00:17 pm Dave Hylands wrote:
> >> I think that this is true for all of the architectures I've worked
> >> with (ARM, MIPS, x86). Some architectures (like MIPS) have a
> >> combination of spaces which are linearly mapped between virtual and
> >> physical, and mapped spaces (which go through an MMU).
> > 
> > Is this just identity mapping or does it bypass the paging unit for some
> > addresses? Just out of curiosity how do you tell the bypassing info?
> 
> On the MIPS core I was working with (which I think was R3000 based),
> they use the upper 2 or 3 bits of the address to determine the type of
> access.
> 
> This page has the details (the table about 1/3 of the way down the web
> page):
> <http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/mips.htm
> l>
Thanks for the info. Never knew about this.

VMA of processes and CPU registers

[Prabhu nath]

I understand about Linear virtual address and Physical address. How is the
logical address generated ? Can you please explain.

Thanks,
Prabhu


On Wed, Apr 20, 2011 at 9:33 PM, mindentropy <mindentropy@gmail.com> wrote:

> On Wednesday 20 Apr 2011 4:31:08 pm limp wrote:
> > Thanks a lot Dace and Vladimir for your replies.
> >
> > First of all, I forgot to mention that I am talking for x86 architecture.
> >
> > > The CPU registers will contain the virtual addresses. Each and every
> > > time that the CPU tries to access a virtual memory location, then the
> > > address will be translated by the MMU into a physical address.
> >
> > So, AFAIU the translation to physical memory takes place *only* when the
> > ALU of the processor has to do some operation which has memory operands
> > (in this case the CPU needs to deal with the *real* addresses) but not
> > prior to that.
> >
>
> The address translation happens in the following way:
>
> Logical Addr-->|Segmentation Unit|-->Linear Addr -->|Paging unit|-->
> Physical
> Addr.
>
> If the paging unit is not setup then the linear addr is the physical addr.
>
> _______________________________________________
> Kernelnewbies mailing list
> Kernelnewbies at kernelnewbies.org
> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
>
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VMA of processes and CPU registers

[mindentropy]

On Monday 25 Apr 2011 2:25:10 pm Prabhu nath wrote:
> I understand about Linear virtual address and Physical address. How is the
> logical address generated ? Can you please explain.
> 
> Thanks,
> Prabhu
> 
> On Wed, Apr 20, 2011 at 9:33 PM, mindentropy <mindentropy@gmail.com> wrote:
> > On Wednesday 20 Apr 2011 4:31:08 pm limp wrote:
> > > Thanks a lot Dace and Vladimir for your replies.
> > > 
> > > First of all, I forgot to mention that I am talking for x86
> > > architecture.
> > > 
> > > > The CPU registers will contain the virtual addresses. Each and every
> > > > time that the CPU tries to access a virtual memory location, then the
> > > > address will be translated by the MMU into a physical address.
> > > 
> > > So, AFAIU the translation to physical memory takes place *only* when
> > > the ALU of the processor has to do some operation which has memory
> > > operands (in this case the CPU needs to deal with the *real*
> > > addresses) but not prior to that.
> > 
> > The address translation happens in the following way:
> > 
> > Logical Addr-->|Segmentation Unit|-->Linear Addr -->|Paging unit|-->
> > Physical
> > Addr.
> > 
> > If the paging unit is not setup then the linear addr is the physical
> > addr.
> > 
> > _______________________________________________
> > Kernelnewbies mailing list
> > Kernelnewbies at kernelnewbies.org
> > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies

In the segmented memory model the memory appears as segments. In this model 
the program issues a logical address which comprises of a segment:offset 
address. The offset selects a byte in the segment. The segmentation unit 
converts it to a linear address. If the paging unit is enabled the linear 
address passes through the paging unit for further translation.


Also please do not top post :)

VMA of processes and CPU registers

[Prabhu nath]

My Apologies for top posting. Now in continuation to my previous question.
Is there a method to know whether segmentation unit is enabled or disabled
either from Kernel space or user space.

Thanks,
Prabhu


On Mon, Apr 25, 2011 at 10:08 PM, mindentropy <mindentropy@gmail.com> wrote:

> On Monday 25 Apr 2011 2:25:10 pm Prabhu nath wrote:
> > I understand about Linear virtual address and Physical address. How is
> the
> > logical address generated ? Can you please explain.
> >
> > Thanks,
> > Prabhu
> >
> > On Wed, Apr 20, 2011 at 9:33 PM, mindentropy <mindentropy@gmail.com>
> wrote:
> > > On Wednesday 20 Apr 2011 4:31:08 pm limp wrote:
> > > > Thanks a lot Dace and Vladimir for your replies.
> > > >
> > > > First of all, I forgot to mention that I am talking for x86
> > > > architecture.
> > > >
> > > > > The CPU registers will contain the virtual addresses. Each and
> every
> > > > > time that the CPU tries to access a virtual memory location, then
> the
> > > > > address will be translated by the MMU into a physical address.
> > > >
> > > > So, AFAIU the translation to physical memory takes place *only* when
> > > > the ALU of the processor has to do some operation which has memory
> > > > operands (in this case the CPU needs to deal with the *real*
> > > > addresses) but not prior to that.
> > >
> > > The address translation happens in the following way:
> > >
> > > Logical Addr-->|Segmentation Unit|-->Linear Addr -->|Paging unit|-->
> > > Physical
> > > Addr.
> > >
> > > If the paging unit is not setup then the linear addr is the physical
> > > addr.
> > >
> > > _______________________________________________
> > > Kernelnewbies mailing list
> > > Kernelnewbies at kernelnewbies.org
> > > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
>
> In the segmented memory model the memory appears as segments. In this model
> the program issues a logical address which comprises of a segment:offset
> address. The offset selects a byte in the segment. The segmentation unit
> converts it to a linear address. If the paging unit is enabled the linear
> address passes through the paging unit for further translation.
>
>
> Also please do not top post :)
>
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VMA of processes and CPU registers

[Mulyadi Santosa]

On Wed, Apr 27, 2011 at 11:33, Prabhu nath <gprabhunath@gmail.com> wrote:
> My Apologies for top posting. Now in continuation to my previous question.
> Is there a method to know whether segmentation unit is enabled or disabled
> either from Kernel space or user space.

you mean, protected memory? try to read:
http://en.wikipedia.org/wiki/Protected_mode

-- 
regards,

Mulyadi Santosa
Freelance Linux trainer and consultant

blog: the-hydra.blogspot.com
training: mulyaditraining.blogspot.com

VMA of processes and CPU registers

[mindentropy]

On Wednesday 27 Apr 2011 10:03:47 am Prabhu nath wrote:
> My Apologies for top posting. Now in continuation to my previous question.
> Is there a method to know whether segmentation unit is enabled or disabled
> either from Kernel space or user space.
> 
> Thanks,
> Prabhu
> 

You need to bottom post. Sigh!

As far as I understand the kernel sets up minimal segmentation. All the 
segments start from 0 and all offsets have limits to 0xFFFFF. So the segment 
addresses corresponds to the linear addresses. Even if there is paging enabled 
there is segment translation.  Please feel free to correct me if I have 
misunderstood.