[Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Isaku Yamahata]

This patch series adds basic q35 chipset support for native pci express
support. Some bios related patches are still needed.
For those who want to try it, the following repo is avaiable.
(vgabios doesn't need patches, so use the upstream one)

git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/seabios

Example:
qemu-system-x86_64 ... -M pc_q35 -acpitable 'load_header,data=roms/seabios/src/q35-acpi-dsdt.aml


The motivation is to support newer hardware features because
piix chipset is very old.
Especially I have PCI express in mind and this is the basic infrastructure
for PCI express hot plug and PCI express native direct attach.
I can boot Linux with PCIe MMCONFIG with APIC mode pci interrupt routing.
I haven't tested other OSes.

The patch series consist as following

- Firstly, some PCI patches which introduce helper functions and so on.
- Then, PC initialization related patches which simplifies pc board
  initialization, pc_init1().
- Thirdly, factoring out the logics which are common to the existing
   piix and q35. ie. smram, pam and acpi logic.
- At last introduce q35 chipset emulator which is able to handle
  pci express natively.

Thanks,

Change from v7:
- heavily reorganized and improved.
- factoring out code duplication.
- improved irq routing fully.

Changes from split out piix specific part from pc emulator. V6
- rebased to 731c54f86988d3f28268f184fabfe9b2a32fb5d3
- PCIe MMCONFIG
- pci bridge related fixes
- chipset emulator works.
- IOAPIC patches

Changes from v5:
- rebased 0.11.0-rc0
- changed qemu_system_powerdown_register() to call
  qemu_system_shutdown_request() if qemu_system_shutdown() is called before
  registering.

Changes from v4:
- fix version number.
- rebased anthony's staging tree whose latest change set is
  62969268f876c547ee64da6d60e0f363e0f1df75

Changes from v3:
- move qemu_system_powerdown() in vl.c and more generic
  following the comment by Marcelo Tosatti <mtosatti@redhat.com>
  acpi.c: make qemu_system_powerdown() piix independent.
- define cmos_set_s3_resume_init() and cmos_set_s3_resume() in pc.c
  even if TARGET_I386 isn't defined following th ecommit by
  Paolo Bonzini <bonzini@gnu.org>
  pc.c: remove a global variable, RTCState *rtc_state.
- minor compilation fixes

Changes from v2:
- clean up pc_pci_device_init() not to use unnecessary braces.

Changes from v1:
- make patches full bisectable
- typo s/allocte/allocate/
- some minor fixes
- dropped a merged patch

Isaku Yamahata (26):
  pci: replace the magic, 256, for the maximum of slot
  pci: add opaque argument to pci_map_irq_fn
  pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt
    pin swizzle
  pci: add accessor function to get irq levels
  piix_pci: eliminate PIIX3State::pci_irq_levels
  pci_bridge: add helper function to convert PCIBridge into PCIDevice
  pci/p2pbr: generic pci p2p bridge
  apb_pci: simplify apb_pci.c by using pci_p2pbr
  dec_pci: simplify dec_pci.c by using pci_p2pbr
  ide/ahci/ich: use qdev.reset
  ahci: add ide device initialization helper
  usb/uhci: generalize initialization
  usb/uhci: add ich9 usb uhci id's device
  ide: consolidate drive_get(IF_IDE)
  smbus_eeprom: consolidate smbus eeprom creation
  pc, pc_piix: split out allocating isa irqs
  pc, pc_piix: split out pc nic initialization
  ioapic: move ioapic_init() from pc_piix.c to pc.c
  pc/piix_pci: factor out smram/pam logic
  pc, i440fx: simply i440fx initialization
  acpi, acpi_piix: factor out PM_TMR logic
  acpi, acpi_piix: factor out PM1a EVT logic
  acpi, acpi_piix: factor out PM1_CNT logic
  acpi, acpi_piix: factor out GPE logic
  pci_ids: add intel 82801BA pci-to-pci bridge id and
    PCI_CLASS_SERIAL_SMBUS
  pc q35 based chipset emulator

 Makefile.objs      |    2 +-
 Makefile.target    |    3 +-
 hw/acpi.c          |  197 ++++++++++++
 hw/acpi.h          |   68 ++++
 hw/acpi_ich9.c     |  314 +++++++++++++++++++
 hw/acpi_ich9.h     |   53 ++++
 hw/acpi_piix4.c    |  220 ++++----------
 hw/apb_pci.c       |   67 ++---
 hw/bonito.c        |    2 +-
 hw/dec_pci.c       |   51 +---
 hw/grackle_pci.c   |    2 +-
 hw/gt64xxx.c       |    2 +-
 hw/ide.h           |    6 +
 hw/ide/ahci.c      |   15 +
 hw/ide/core.c      |   14 +
 hw/ide/ich.c       |    9 +-
 hw/mips_fulong2e.c |   18 +-
 hw/mips_malta.c    |   22 +--
 hw/mips_r4k.c      |   10 +-
 hw/pam.c           |  128 ++++++++
 hw/pam.h           |   96 ++++++
 hw/pc.c            |   47 +++-
 hw/pc.h            |    7 +-
 hw/pc_piix.c       |   64 +----
 hw/pc_q35.c        |  359 +++++++++++++++++++++
 hw/pci.c           |   27 ++-
 hw/pci.h           |    6 +-
 hw/pci_bridge.c    |    6 +
 hw/pci_bridge.h    |    1 +
 hw/pci_ids.h       |   17 +
 hw/pci_internals.h |    2 +-
 hw/pci_p2pbr.c     |  151 +++++++++
 hw/pci_p2pbr.h     |   61 ++++
 hw/piix_pci.c      |  117 +++-----
 hw/ppc4xx_pci.c    |    2 +-
 hw/ppc_newworld.c  |   11 +-
 hw/ppc_oldworld.c  |   11 +-
 hw/ppc_prep.c      |   10 +-
 hw/ppce500_pci.c   |    2 +-
 hw/prep_pci.c      |    2 +-
 hw/q35.c           |  877 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/q35.h           |  271 ++++++++++++++++
 hw/q35_smbus.c     |  154 +++++++++
 hw/sh_pci.c        |    2 +-
 hw/smbus.h         |    3 +
 hw/smbus_eeprom.c  |   22 ++-
 hw/sun4u.c         |    9 +-
 hw/unin_pci.c      |    2 +-
 hw/usb-uhci.c      |   93 +++---
 hw/versatile_pci.c |    2 +-
 50 files changed, 3116 insertions(+), 521 deletions(-)
 create mode 100644 hw/acpi_ich9.c
 create mode 100644 hw/acpi_ich9.h
 create mode 100644 hw/pam.c
 create mode 100644 hw/pam.h
 create mode 100644 hw/pc_q35.c
 create mode 100644 hw/pci_p2pbr.c
 create mode 100644 hw/pci_p2pbr.h
 create mode 100644 hw/q35.c
 create mode 100644 hw/q35.h
 create mode 100644 hw/q35_smbus.c

[Qemu-devel] [PATCH 01/26] pci: replace the magic, 256, for the maximum of slot

[Isaku Yamahata]

Introduce symbol PCI_SLOT_MAX for the maximum of slot.
and replace the magic, 256.

Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pci.h           |    1 +
 hw/pci_internals.h |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/hw/pci.h b/hw/pci.h
index 113e556..7d56337 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -16,6 +16,7 @@
 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
+#define PCI_SLOT_MAX            32
 #define PCI_FUNC_MAX            8
 
 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
diff --git a/hw/pci_internals.h b/hw/pci_internals.h
index e3c93a3..efaefcd 100644
--- a/hw/pci_internals.h
+++ b/hw/pci_internals.h
@@ -22,7 +22,7 @@ struct PCIBus {
     pci_hotplug_fn hotplug;
     DeviceState *hotplug_qdev;
     void *irq_opaque;
-    PCIDevice *devices[256];
+    PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
     PCIDevice *parent_dev;
     target_phys_addr_t mem_base;
 
-- 
1.7.1.1

[Qemu-devel] [PATCH 02/26] pci: add opaque argument to pci_map_irq_fn

[Isaku Yamahata]

Pass opaque argument to pci_map_irq_fn like pci_set_irq_fn.
ICH9 irq routing is not static, but configurable by chipset configuration
registers, so the corresponding irq mapping function of pci_map_irq_fn
needs to know the pointer to ich9.

Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/apb_pci.c       |    4 ++--
 hw/bonito.c        |    2 +-
 hw/dec_pci.c       |    2 +-
 hw/grackle_pci.c   |    2 +-
 hw/gt64xxx.c       |    2 +-
 hw/pci.c           |    2 +-
 hw/pci.h           |    2 +-
 hw/piix_pci.c      |    2 +-
 hw/ppc4xx_pci.c    |    2 +-
 hw/ppce500_pci.c   |    2 +-
 hw/prep_pci.c      |    2 +-
 hw/sh_pci.c        |    2 +-
 hw/unin_pci.c      |    2 +-
 hw/versatile_pci.c |    2 +-
 14 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 84e9af7..c56ea9a 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -264,12 +264,12 @@ static CPUReadMemoryFunc * const pci_apb_ioread[] = {
 };
 
 /* The APB host has an IRQ line for each IRQ line of each slot.  */
-static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_apb_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
 }
 
-static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_pbm_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     int bus_offset;
     if (pci_dev->devfn & 1)
diff --git a/hw/bonito.c b/hw/bonito.c
index 65a4a63..94e69f5 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -632,7 +632,7 @@ static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
 }
 
 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
-static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
+static int pci_bonito_map_irq(void *opaque, PCIDevice * pci_dev, int irq_num)
 {
     int slot;
 
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index bf88f2a..3cc4f04 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -45,7 +45,7 @@ typedef struct DECState {
     PCIHostState host_state;
 } DECState;
 
-static int dec_map_irq(PCIDevice *pci_dev, int irq_num)
+static int dec_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     return irq_num;
 }
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index d35701f..4ed1ec6 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -44,7 +44,7 @@ typedef struct GrackleState {
 } GrackleState;
 
 /* Don't know if this matches real hardware, but it agrees with OHW.  */
-static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_grackle_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     return (irq_num + (pci_dev->devfn >> 3)) & 3;
 }
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index c66188f..e6e2828 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -862,7 +862,7 @@ static CPUReadMemoryFunc * const gt64120_read[] = {
     &gt64120_readl,
 };
 
-static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int gt64120_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     int slot;
 
diff --git a/hw/pci.c b/hw/pci.c
index 8d7bfff..5349488 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -117,7 +117,7 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
     PCIBus *bus;
     for (;;) {
         bus = pci_dev->bus;
-        irq_num = bus->map_irq(pci_dev, irq_num);
+        irq_num = bus->map_irq(bus->irq_opaque, pci_dev, irq_num);
         if (bus->set_irq)
             break;
         pci_dev = bus->parent_dev;
diff --git a/hw/pci.h b/hw/pci.h
index 7d56337..1a08139 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -219,7 +219,7 @@ void pci_device_save(PCIDevice *s, QEMUFile *f);
 int pci_device_load(PCIDevice *s, QEMUFile *f);
 
 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
-typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
+typedef int (*pci_map_irq_fn)(void *opaque, PCIDevice *pci_dev, int irq_num);
 
 typedef enum {
     PCI_HOTPLUG_DISABLED,
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 358da58..892c576 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -60,7 +60,7 @@ static void piix3_set_irq(void *opaque, int irq_num, int level);
 /* return the global irq number corresponding to a given device irq
    pin. We could also use the bus number to have a more precise
    mapping. */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+static int pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     int slot_addend;
     slot_addend = (pci_dev->devfn >> 3) - 1;
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index f62f1f9..11ca763 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -267,7 +267,7 @@ static void ppc4xx_pci_reset(void *opaque)
 
 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
  * may need further refactoring for other boards. */
-static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int ppc4xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     int slot = pci_dev->devfn >> 3;
 
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 11edd03..029a3f9 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -187,7 +187,7 @@ static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
     &pci_reg_write4,
 };
 
-static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int mpc85xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     int devno = pci_dev->devfn >> 3, ret = 0;
 
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index f88b825..8287246 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -98,7 +98,7 @@ static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
     &PPC_PCIIO_readl,
 };
 
-static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
+static int prep_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 }
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index e99d8db..f108759 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -93,7 +93,7 @@ static MemOp sh_pci_reg = {
     { NULL, NULL, sh_pci_reg_write },
 };
 
-static int sh_pci_map_irq(PCIDevice *d, int irq_num)
+static int sh_pci_map_irq(void *opaque, PCIDevice *d, int irq_num)
 {
     return (d->devfn >> 3);
 }
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index c57c0a1..1496625 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -44,7 +44,7 @@ typedef struct UNINState {
     ReadWriteHandler data_handler;
 } UNINState;
 
-static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_unin_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
 {
     int retval;
     int devfn = pci_dev->devfn & 0x00FFFFFF;
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 2fed8a0..c002fb2 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -74,7 +74,7 @@ static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
     &pci_vpb_config_readl,
 };
 
-static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
+static int pci_vpb_map_irq(void *opaque, PCIDevice *d, int irq_num)
 {
     return irq_num;
 }
-- 
1.7.1.1

[Qemu-devel] [PATCH 03/26] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle

[Isaku Yamahata]

introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
standardized. PCI bridge swizzle is common logic, by introducing
this function duplicated swizzle logic will be avoided later.

Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pci.c |   18 ++++++++++++++++++
 hw/pci.h |    2 ++
 2 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index 5349488..d6c5e66 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1117,6 +1117,24 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
     pci_change_irq_level(pci_dev, irq_num, change);
 }
 
+/*
+ * PCI-to-PCI bridge specification
+ * 9.1: Interrupt routing. Table 9-1
+ *
+ * the PCI Express Base Specification, Revision 2.1
+ * 2.2.8.1: INTx interrutp signaling - Rules
+ *          the Implementation Note
+ *          Table 2-20
+ */
+/*
+ * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
+ * 0-origin unlike PCI interrupt pin register.
+ */
+int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin)
+{
+    return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
+}
+
 /***********************************************************/
 /* monitor info on PCI */
 
diff --git a/hw/pci.h b/hw/pci.h
index 1a08139..46b3ad3 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -235,6 +235,8 @@ PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                   void *irq_opaque, int nirq);
 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
+/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
+int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin);
 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                          void *irq_opaque, int devfn_min, int nirq);
-- 
1.7.1.1

[Qemu-devel] [PATCH 04/26] pci: add accessor function to get irq levels

[Isaku Yamahata]

Introduce accessor function to know INTx levels.
It will be used later by q35.
Although piix_pci tracks the intx line levels, it can be eliminated
by this helper function.

Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pci.c |    7 +++++++
 hw/pci.h |    1 +
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index d6c5e66..67cb3d7 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -126,6 +126,13 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 }
 
+int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
+{
+    assert(irq_num >= 0);
+    assert(irq_num < bus->nirq);
+    return !!bus->irq_count[irq_num];
+}
+
 /* Update interrupt status bit in config space on interrupt
  * state change. */
 static void pci_update_irq_status(PCIDevice *dev)
diff --git a/hw/pci.h b/hw/pci.h
index 46b3ad3..f523722 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -234,6 +234,7 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                   void *irq_opaque, int nirq);
+int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin);
-- 
1.7.1.1

[Qemu-devel] [PATCH 05/26] piix_pci: eliminate PIIX3State::pci_irq_levels

[Isaku Yamahata]

PIIX3State::pci_irq_levels are redundant which is already tracked by
PCIBus layer. So eliminate them.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/piix_pci.c |   31 +++++++++++++++++++++----------
 1 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 892c576..2d0ad9b 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -39,7 +39,7 @@ typedef PCIHostState I440FXState;
 
 typedef struct PIIX3State {
     PCIDevice dev;
-    int pci_irq_levels[4];
+    int32_t dummy_for_save_load_compat[4];
     qemu_irq *pic;
 } PIIX3State;
 
@@ -162,9 +162,11 @@ static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
     i440fx_update_memory_mappings(d);
     qemu_get_8s(f, &d->smm_enabled);
 
-    if (version_id == 2)
-        for (i = 0; i < 4; i++)
-            d->piix3->pci_irq_levels[i] = qemu_get_be32(f);
+    if (version_id == 2) {
+        for (i = 0; i < 4; i++) {
+            qemu_get_be32(f); /* dummy load for compatibility */
+        }
+    }
 
     return 0;
 }
@@ -256,8 +258,6 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
     int i, pic_irq, pic_level;
     PIIX3State *piix3 = opaque;
 
-    piix3->pci_irq_levels[irq_num] = level;
-
     /* now we change the pic irq level according to the piix irq mappings */
     /* XXX: optimize */
     pic_irq = piix3->dev.config[0x60 + irq_num];
@@ -266,8 +266,9 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
            to it */
         pic_level = 0;
         for (i = 0; i < 4; i++) {
-            if (pic_irq == piix3->dev.config[0x60 + i])
-                pic_level |= piix3->pci_irq_levels[i];
+            if (pic_irq == piix3->dev.config[0x60 + i]) {
+                pic_level |= pci_bus_get_irq_level(piix3->dev.bus, i);
+            }
         }
         qemu_set_irq(piix3->pic[pic_irq], pic_level);
     }
@@ -309,8 +310,17 @@ static void piix3_reset(void *opaque)
     pci_conf[0xab] = 0x00;
     pci_conf[0xac] = 0x00;
     pci_conf[0xae] = 0x00;
+}
 
-    memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
+static void piix3_pre_save(void *opaque)
+{
+    int i;
+    PIIX3State *piix3 = opaque;
+
+    for (i = 0; i < ARRAY_SIZE(piix3->dummy_for_save_load_compat); i++) {
+        piix3->dummy_for_save_load_compat[i] =
+            pci_bus_get_irq_level(piix3->dev.bus, i);
+    }
 }
 
 static const VMStateDescription vmstate_piix3 = {
@@ -318,9 +328,10 @@ static const VMStateDescription vmstate_piix3 = {
     .version_id = 3,
     .minimum_version_id = 2,
     .minimum_version_id_old = 2,
+    .pre_save = piix3_pre_save,
     .fields      = (VMStateField []) {
         VMSTATE_PCI_DEVICE(dev, PIIX3State),
-        VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
+        VMSTATE_INT32_ARRAY_V(dummy_for_save_load_compat, PIIX3State, 4, 3),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
1.7.1.1

[Qemu-devel] [PATCH 06/26] pci_bridge: add helper function to convert PCIBridge into PCIDevice

[Isaku Yamahata]

pci_bridge_to_pci() which converts PCIBridge into PCIDevice which will
be used later by pci_p2pbr.

Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pci_bridge.c |    6 ++++++
 hw/pci_bridge.h |    1 +
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c
index 464d897..00b6b76 100644
--- a/hw/pci_bridge.c
+++ b/hw/pci_bridge.c
@@ -52,6 +52,12 @@ int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
     return pos;
 }
 
+/* Accessor function to get PCI device from pci bridge. */
+PCIDevice *pci_bridge_to_pci(PCIBridge *br)
+{
+    return &br->dev;
+}
+
 /* Accessor function to get parent bridge device from pci bus. */
 PCIDevice *pci_bridge_get_device(PCIBus *bus)
 {
diff --git a/hw/pci_bridge.h b/hw/pci_bridge.h
index 84411a6..c306992 100644
--- a/hw/pci_bridge.h
+++ b/hw/pci_bridge.h
@@ -31,6 +31,7 @@
 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
                           uint16_t svid, uint16_t ssid);
 
+PCIDevice *pci_bridge_to_pci(PCIBridge *br);
 PCIDevice *pci_bridge_get_device(PCIBus *bus);
 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br);
 
-- 
1.7.1.1

[Qemu-devel] [PATCH 07/26] pci/p2pbr: generic pci p2p bridge

[Isaku Yamahata]

Create generic pci p2p bridge device which can be customized
via properties like vendor id/device id and so on.
With this, we can avoid to create many pci p2p bridge which only
differs in those ids.

Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 Makefile.objs  |    2 +-
 hw/pci_p2pbr.c |  151 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/pci_p2pbr.h |   61 +++++++++++++++++++++++
 3 files changed, 213 insertions(+), 1 deletions(-)
 create mode 100644 hw/pci_p2pbr.c
 create mode 100644 hw/pci_p2pbr.h

diff --git a/Makefile.objs b/Makefile.objs
index a52f42f..5cb7010 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -171,7 +171,7 @@ hw-obj-y =
 hw-obj-y += vl.o loader.o
 hw-obj-$(CONFIG_VIRTIO) += virtio.o virtio-console.o
 hw-obj-y += fw_cfg.o
-hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
+hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o pci_p2pbr.o
 hw-obj-$(CONFIG_PCI) += msix.o msi.o
 hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
 hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
diff --git a/hw/pci_p2pbr.c b/hw/pci_p2pbr.c
new file mode 100644
index 0000000..e5b03e2
--- /dev/null
+++ b/hw/pci_p2pbr.c
@@ -0,0 +1,151 @@
+/*
+ * QEMU PCI P2P generic bridge.
+ * In order to avoid create many P2P bridge device which only differs
+ * in vendor id/device id and so on.
+ *
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "pci_bridge.h"
+#include "pci_internals.h"
+#include "pci_p2pbr.h"
+
+typedef struct PCIP2PBridge {
+    struct PCIBridge br;
+
+    /* device specific initialization */
+    pci_p2pbr_init_fn initfn;
+
+    /* properties */
+    uint16_t vendor_id;
+    uint16_t device_id;
+    uint8_t revision_id;
+    uint8_t prog_interface;
+
+    uint8_t ssvid_cap;
+    uint16_t svid;
+    uint16_t ssid;
+} PCIP2PBridge;
+
+static int pci_p2pbr_initfn(PCIDevice *d)
+{
+    PCIBridge *br = DO_UPCAST(PCIBridge, dev, d);
+    PCIP2PBridge *p2pbr = DO_UPCAST(PCIP2PBridge, br, br);
+    uint8_t *config = d->config;
+    int rc;
+
+    rc = pci_bridge_initfn(d);
+    if (rc < 0) {
+        return rc;
+    }
+
+    pci_config_set_vendor_id(config, p2pbr->vendor_id);
+    pci_config_set_device_id(config, p2pbr->device_id);
+    pci_config_set_revision(config, p2pbr->revision_id);
+    pci_config_set_prog_interface(config, p2pbr->prog_interface);
+
+    if (p2pbr->ssvid_cap > 0) {
+        rc = pci_bridge_ssvid_init(d, p2pbr->ssvid_cap,
+                                   p2pbr->svid, p2pbr->ssid);
+        if (rc < 0) {
+            return rc;
+        }
+    }
+
+    if (p2pbr->initfn) {
+        return p2pbr->initfn(d);
+    }
+
+    return 0;
+}
+
+#define PCI_P2P_BRIDGE  "PCI P2P bridge"
+
+static PCIDeviceInfo pci_p2pbr_info = {
+    .qdev.name = PCI_P2P_BRIDGE,
+    .qdev.desc = "PCI PCI-to-PCI bridge",
+    .qdev.size = sizeof(PCIP2PBridge),
+    .qdev.reset = pci_bridge_reset,
+    .qdev.vmsd = &vmstate_pci_device,
+
+    .is_bridge = 1,
+    .init = pci_p2pbr_initfn,
+    .exit = pci_bridge_exitfn,
+    .config_write = pci_bridge_write_config,
+
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_UINT16("vendor_id", PCIP2PBridge, vendor_id, 0),
+        DEFINE_PROP_UINT16("device_id", PCIP2PBridge, device_id, 0),
+        DEFINE_PROP_UINT8("revision_id", PCIP2PBridge, revision_id, 0),
+        DEFINE_PROP_UINT8("prog_interface", PCIP2PBridge, prog_interface, 0),
+
+        DEFINE_PROP_UINT8("ssvid_cap", PCIP2PBridge, ssvid_cap, 0),
+        DEFINE_PROP_UINT16("svid", PCIP2PBridge, svid, 0),
+        DEFINE_PROP_UINT16("ssid", PCIP2PBridge, ssid, 0),
+
+        DEFINE_PROP_END_OF_LIST(),
+    }
+};
+
+static void pci_p2pbr_register(void)
+{
+    pci_qdev_register(&pci_p2pbr_info);
+}
+
+device_init(pci_p2pbr_register);
+
+PCIBridge *pci_p2pbr_create(const PCIP2PBridgeInit *init)
+{
+    PCIDevice *d;
+    PCIBridge *br;
+    PCIP2PBridge *p2pbr;
+
+    d = pci_create_multifunction(init->bus, init->devfn, init->multifunction,
+                                 PCI_P2P_BRIDGE);
+
+    br = DO_UPCAST(PCIBridge, dev, d);
+    pci_bridge_map_irq(br, init->bus_name, init->map_irq);
+
+    p2pbr = DO_UPCAST(PCIP2PBridge, br, br);
+    p2pbr->initfn = init->initfn;
+
+    return br;
+}
+
+void pci_p2pbr_prop_set(PCIBridge *br, const PCIP2PBridgeProp *prop)
+{
+    DeviceState *qdev = &br->dev.qdev;
+
+    qdev_prop_set_uint16(qdev, "vendor_id", prop->vendor_id);
+    qdev_prop_set_uint16(qdev, "device_id", prop->device_id);
+    qdev_prop_set_uint8(qdev, "revision_id", prop->revision_id);
+    qdev_prop_set_uint8(qdev, "prog_interface", prop->prog_interface);
+
+    qdev_prop_set_uint8(qdev, "ssvid_cap", prop->ssvid_cap);
+    qdev_prop_set_uint16(qdev, "svid", prop->svid);
+    qdev_prop_set_uint16(qdev, "ssid", prop->ssid);
+}
+
+/* convenience function to create pci p2p bridge */
+PCIBridge *pci_p2pbr_create_simple(const PCIP2PBridgeInit *init,
+                                   const PCIP2PBridgeProp *prop)
+{
+    PCIBridge *br = pci_p2pbr_create(init);
+    pci_p2pbr_prop_set(br, prop);
+    qdev_init_nofail(&br->dev.qdev);
+    return br;
+}
diff --git a/hw/pci_p2pbr.h b/hw/pci_p2pbr.h
new file mode 100644
index 0000000..ee23ebb
--- /dev/null
+++ b/hw/pci_p2pbr.h
@@ -0,0 +1,61 @@
+/*
+ * QEMU PCI P2P generic bridge.
+ * In order to avoid create many P2P bridge device which only differs
+ * in vendor id/device id and so on.
+ *
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_PCI_P2PBR_H
+#define QEMU_PCI_P2PBR_H
+
+#include "qdev.h"
+
+typedef int (*pci_p2pbr_init_fn)(PCIDevice *d);
+
+typedef struct PCIP2PBridgeInit
+{
+    PCIBus *bus;
+    uint8_t devfn;
+    bool multifunction;
+
+    const char* bus_name;
+    pci_map_irq_fn map_irq;
+
+    pci_p2pbr_init_fn initfn;
+} PCIP2PBridgeInit;
+
+typedef struct PCIP2PBridgeProp
+{
+    uint16_t vendor_id;
+    uint16_t device_id;
+    uint8_t revision_id;
+    uint8_t prog_interface;
+
+    uint8_t ssvid_cap;
+    uint8_t svid;
+    uint8_t ssid;
+} PCIP2PBridgeProp;
+
+/* When setting PCIP2PBridgeProb, zero clear it for future compatibility */
+PCIBridge *pci_p2pbr_create(const PCIP2PBridgeInit *init);
+void pci_p2pbr_prop_set(PCIBridge *br, const PCIP2PBridgeProp *prop);
+
+PCIBridge *pci_p2pbr_create_simple(const PCIP2PBridgeInit *init,
+                                   const PCIP2PBridgeProp *prop);
+
+#endif /* QEMU_PCI_P2PBR_H */
-- 
1.7.1.1

[Qemu-devel] [PATCH 08/26] apb_pci: simplify apb_pci.c by using pci_p2pbr

[Isaku Yamahata]

apply pci_p2pbr for apb_pci.c.

Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/apb_pci.c |   63 ++++++++++++++++++++++++---------------------------------
 1 files changed, 27 insertions(+), 36 deletions(-)

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index c56ea9a..c9f2a6b 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -31,6 +31,7 @@
 #include "pci_host.h"
 #include "pci_bridge.h"
 #include "pci_internals.h"
+#include "pci_p2pbr.h"
 #include "rwhandler.h"
 #include "apb_pci.h"
 #include "sysemu.h"
@@ -297,16 +298,6 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
 
 static int apb_pci_bridge_initfn(PCIDevice *dev)
 {
-    int rc;
-
-    rc = pci_bridge_initfn(dev);
-    if (rc < 0) {
-        return rc;
-    }
-
-    pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_SUN);
-    pci_config_set_device_id(dev->config, PCI_DEVICE_ID_SUN_SIMBA);
-
     /*
      * command register:
      * According to PCI bridge spec, after reset
@@ -321,10 +312,31 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
     pci_set_word(dev->config + PCI_STATUS,
                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                  PCI_STATUS_DEVSEL_MEDIUM);
-    pci_set_byte(dev->config + PCI_REVISION_ID, 0x11);
     return 0;
 }
 
+static PCIBridge *apb_pci_bridge_init(PCIBus *bus,
+                                      uint8_t devfn, const char *bus_name)
+{
+    const PCIP2PBridgeInit init = {
+        .bus = bus,
+        .devfn = devfn,
+        .multifunction = true,
+
+        .bus_name = bus_name,
+        .map_irq = pci_apb_map_irq,
+
+        .initfn = apb_pci_bridge_initfn,
+    };
+    const PCIP2PBridgeProp prop = {
+        .vendor_id = PCI_VENDOR_ID_SUN,
+        .device_id = PCI_DEVICE_ID_SUN_SIMBA,
+        .revision_id = 0x11,
+    };
+
+    return pci_p2pbr_create_simple(&init, &prop);
+}
+
 PCIBus *pci_apb_init(target_phys_addr_t special_base,
                      target_phys_addr_t mem_base,
                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
@@ -333,7 +345,6 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
     SysBusDevice *s;
     APBState *d;
     unsigned int i;
-    PCIDevice *pci_dev;
     PCIBridge *br;
 
     /* Ultrasparc PBM main bus */
@@ -360,20 +371,12 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
     pci_create_simple(d->bus, 0, "pbm");
 
     /* APB secondary busses */
-    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
-                                   "pbm-bridge");
-    br = DO_UPCAST(PCIBridge, dev, pci_dev);
-    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
-                       pci_apb_map_irq);
-    qdev_init_nofail(&pci_dev->qdev);
+    br = apb_pci_bridge_init(d->bus, PCI_DEVFN(1, 0),
+                             "Advanced PCI Bus secondary bridge 1");
     *bus2 = pci_bridge_get_sec_bus(br);
 
-    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
-                                   "pbm-bridge");
-    br = DO_UPCAST(PCIBridge, dev, pci_dev);
-    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
-                       pci_apb_map_irq);
-    qdev_init_nofail(&pci_dev->qdev);
+    br = apb_pci_bridge_init(d->bus, PCI_DEVFN(1, 1),
+                             "Advanced PCI Bus secondary bridge 2");
     *bus3 = pci_bridge_get_sec_bus(br);
 
     return d->bus;
@@ -461,22 +464,10 @@ static SysBusDeviceInfo pbm_host_info = {
     .init = pci_pbm_init_device,
 };
 
-static PCIDeviceInfo pbm_pci_bridge_info = {
-    .qdev.name = "pbm-bridge",
-    .qdev.size = sizeof(PCIBridge),
-    .qdev.vmsd = &vmstate_pci_device,
-    .qdev.reset = pci_bridge_reset,
-    .init = apb_pci_bridge_initfn,
-    .exit = pci_bridge_exitfn,
-    .config_write = pci_bridge_write_config,
-    .is_bridge = 1,
-};
-
 static void pbm_register_devices(void)
 {
     sysbus_register_withprop(&pbm_host_info);
     pci_qdev_register(&pbm_pci_host_info);
-    pci_qdev_register(&pbm_pci_bridge_info);
 }
 
 device_init(pbm_register_devices)
-- 
1.7.1.1

[Qemu-devel] [PATCH 09/26] dec_pci: simplify dec_pci.c by using pci_p2pbr

[Isaku Yamahata]

apply pci_p2pbr for dec_pci.c.

Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/dec_pci.c |   49 ++++++++++++++-----------------------------------
 1 files changed, 14 insertions(+), 35 deletions(-)

diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index 3cc4f04..fbd1363 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -29,6 +29,7 @@
 #include "pci_host.h"
 #include "pci_bridge.h"
 #include "pci_internals.h"
+#include "pci_p2pbr.h"
 
 /* debug DEC */
 //#define DEBUG_DEC
@@ -50,42 +51,21 @@ static int dec_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
     return irq_num;
 }
 
-static int dec_21154_initfn(PCIDevice *dev)
-{
-    int rc;
-
-    rc = pci_bridge_initfn(dev);
-    if (rc < 0) {
-        return rc;
-    }
-
-    pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_DEC);
-    pci_config_set_device_id(dev->config, PCI_DEVICE_ID_DEC_21154);
-    return 0;
-}
-
-static PCIDeviceInfo dec_21154_pci_bridge_info = {
-    .qdev.name = "dec-21154-p2p-bridge",
-    .qdev.desc = "DEC 21154 PCI-PCI bridge",
-    .qdev.size = sizeof(PCIBridge),
-    .qdev.vmsd = &vmstate_pci_device,
-    .qdev.reset = pci_bridge_reset,
-    .init = dec_21154_initfn,
-    .exit = pci_bridge_exitfn,
-    .config_write = pci_bridge_write_config,
-    .is_bridge = 1,
-};
-
 PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
 {
-    PCIDevice *dev;
-    PCIBridge *br;
-
-    dev = pci_create_multifunction(parent_bus, devfn, false,
-                                   "dec-21154-p2p-bridge");
-    br = DO_UPCAST(PCIBridge, dev, dev);
-    pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq);
-    qdev_init_nofail(&dev->qdev);
+    const PCIP2PBridgeInit init = {
+        .bus = parent_bus,
+        .devfn = devfn,
+        .multifunction = false,
+
+        .bus_name = "DEC 21154 PCI-PCI bridge",
+        .map_irq = dec_map_irq,
+    };
+    const PCIP2PBridgeProp prop = {
+        .vendor_id = PCI_VENDOR_ID_DEC,
+        .device_id = PCI_DEVICE_ID_DEC_21154,
+    };
+    PCIBridge *br = pci_p2pbr_create_simple(&init, &prop);
     return pci_bridge_get_sec_bus(br);
 }
 
@@ -127,7 +107,6 @@ static void dec_register_devices(void)
     sysbus_register_dev("dec-21154", sizeof(DECState),
                         pci_dec_21154_init_device);
     pci_qdev_register(&dec_21154_pci_host_info);
-    pci_qdev_register(&dec_21154_pci_bridge_info);
 }
 
 device_init(dec_register_devices)
-- 
1.7.1.1

[Qemu-devel] [PATCH 10/26] ide/ahci/ich: use qdev.reset

[Isaku Yamahata]

use DeviceInfo::reset callback instead of qemu_register_reset().
With this patch, its reset is done before parent pci device's reset.

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/ide/ich.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index f242d7a..e190f24 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -92,8 +92,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
     /* XXX Software should program this register */
     d->card.config[0x90]   = 1 << 6; /* Address Map Register - AHCI mode */
 
-    qemu_register_reset(ahci_reset, d);
-
     /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
     pci_register_bar(&d->card, 5, 0x1000, PCI_BASE_ADDRESS_SPACE_MEMORY,
                      ahci_pci_map);
@@ -115,7 +113,6 @@ static int pci_ich9_uninit(PCIDevice *dev)
         msi_uninit(dev);
     }
 
-    qemu_unregister_reset(ahci_reset, d);
     ahci_uninit(&d->ahci);
 
     return 0;
@@ -128,11 +125,17 @@ static void pci_ich9_write_config(PCIDevice *pci, uint32_t addr,
     msi_write_config(pci, addr, val, len);
 }
 
+static void pci_ich9_resetfn(DeviceState *qdev)
+{
+    ahci_reset(qdev);
+}
+
 static PCIDeviceInfo ich_ahci_info[] = {
     {
         .qdev.name    = "ich9-ahci",
         .qdev.alias   = "ahci",
         .qdev.size    = sizeof(AHCIPCIState),
+        .qdev.reset   = pci_ich9_resetfn,
         .init         = pci_ich9_ahci_init,
         .exit         = pci_ich9_uninit,
         .config_write = pci_ich9_write_config,
-- 
1.7.1.1

[Qemu-devel] [PATCH 11/26] ahci: add ide device initialization helper

[Isaku Yamahata]

Introduce a helper function which initialize ahci port with ide device
It will be used by q35 support later.

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/ide.h      |    3 +++
 hw/ide/ahci.c |   15 +++++++++++++++
 2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/hw/ide.h b/hw/ide.h
index 73fb550..e90f557 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -28,4 +28,7 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
 
 void ide_get_bs(BlockDriverState *bs[], BusState *qbus);
 
+/* ide/ahci.c */
+void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
+
 #endif /* HW_IDE_H */
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 98bdf70..5597885 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -1150,3 +1150,18 @@ void ahci_reset(void *opaque)
         ahci_reset_port(&d->ahci, i);
     }
 }
+
+void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
+{
+    struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev);
+    int i;
+
+    for (i = 0; i < dev->ahci.ports; i++) {
+        /* master device only, ignore slaves */
+        if (hd_table[i * MAX_IDE_DEVS] == NULL) {
+            continue;
+        }
+        ide_create_drive(&dev->ahci.dev[i].port, 0,
+                         hd_table[i * MAX_IDE_DEVS]);
+    }
+}
-- 
1.7.1.1

[Qemu-devel] [PATCH 12/26] usb/uhci: generalize initialization

[Isaku Yamahata]

generalize initialization to make vendir/device id
customizable.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/usb-uhci.c |   87 ++++++++++++++++++++++++++++-----------------------------
 1 files changed, 43 insertions(+), 44 deletions(-)

diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
index b384e1d..2fb2a85 100644
--- a/hw/usb-uhci.c
+++ b/hw/usb-uhci.c
@@ -1115,12 +1115,25 @@ static USBPortOps uhci_port_ops = {
     .wakeup = uhci_wakeup,
 };
 
-static int usb_uhci_common_initfn(UHCIState *s)
+typedef struct UHCIDeviceInfo {
+    PCIDeviceInfo pci;
+    uint16_t vendor_id;
+    uint16_t device_id;
+    uint8_t revision_id;
+} UHCIDeviceInfo;
+
+static int usb_uhci_common_initfn(PCIDevice *dev)
 {
+    UHCIDeviceInfo *uhci_info = DO_UPCAST(UHCIDeviceInfo, pci.qdev,
+                                          dev->qdev.info);
+    UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
     uint8_t *pci_conf = s->dev.config;
     int i;
 
-    pci_conf[PCI_REVISION_ID] = 0x01; // revision number
+    pci_config_set_vendor_id(pci_conf, uhci_info->vendor_id);
+    pci_config_set_device_id(pci_conf, uhci_info->device_id);
+    pci_config_set_revision(pci_conf, uhci_info->revision_id);
+
     pci_conf[PCI_CLASS_PROG] = 0x00;
     pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
     /* TODO: reset value should be 0. */
@@ -1148,34 +1161,10 @@ static int usb_uhci_common_initfn(UHCIState *s)
     return 0;
 }
 
-static int usb_uhci_piix3_initfn(PCIDevice *dev)
-{
-    UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
-    uint8_t *pci_conf = s->dev.config;
-
-    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2);
-    return usb_uhci_common_initfn(s);
-}
-
-static int usb_uhci_piix4_initfn(PCIDevice *dev)
-{
-    UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
-    uint8_t *pci_conf = s->dev.config;
-
-    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2);
-    return usb_uhci_common_initfn(s);
-}
-
 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
 {
     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
     uint8_t *pci_conf = s->dev.config;
-
-    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_UHCI);
-
     /* USB misc control 1/2 */
     pci_set_long(pci_conf + 0x40,0x00001000);
     /* PM capability */
@@ -1183,33 +1172,43 @@ static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
     /* USB legacy support  */
     pci_set_long(pci_conf + 0xc0,0x00002000);
 
-    return usb_uhci_common_initfn(s);
+    return usb_uhci_common_initfn(dev);
 }
 
-static PCIDeviceInfo uhci_info[] = {
+static UHCIDeviceInfo uhci_info[] = {
     {
-        .qdev.name    = "piix3-usb-uhci",
-        .qdev.size    = sizeof(UHCIState),
-        .qdev.vmsd    = &vmstate_uhci,
-        .init         = usb_uhci_piix3_initfn,
-    },{
-        .qdev.name    = "piix4-usb-uhci",
-        .qdev.size    = sizeof(UHCIState),
-        .qdev.vmsd    = &vmstate_uhci,
-        .init         = usb_uhci_piix4_initfn,
+        .pci.qdev.name    = "piix3-usb-uhci",
+        .pci.qdev.size    = sizeof(UHCIState),
+        .pci.qdev.vmsd    = &vmstate_uhci,
+        .pci.init         = usb_uhci_common_initfn,
+        .vendor_id        = PCI_VENDOR_ID_INTEL,
+        .device_id        = PCI_DEVICE_ID_INTEL_82371SB_2,
+        .revision_id      = 0x01,
     },{
-        .qdev.name    = "vt82c686b-usb-uhci",
-        .qdev.size    = sizeof(UHCIState),
-        .qdev.vmsd    = &vmstate_uhci,
-        .init         = usb_uhci_vt82c686b_initfn,
+        .pci.qdev.name    = "piix4-usb-uhci",
+        .pci.qdev.size    = sizeof(UHCIState),
+        .pci.qdev.vmsd    = &vmstate_uhci,
+        .pci.init         = usb_uhci_common_initfn,
+        .vendor_id        = PCI_VENDOR_ID_INTEL,
+        .device_id        = PCI_DEVICE_ID_INTEL_82371AB_2,
+        .revision_id      = 0x01,
     },{
-        /* end of list */
-    }
+        .pci.qdev.name    = "vt82c686b-usb-uhci",
+        .pci.qdev.size    = sizeof(UHCIState),
+        .pci.qdev.vmsd    = &vmstate_uhci,
+        .pci.init         = usb_uhci_vt82c686b_initfn,
+        .vendor_id        = PCI_VENDOR_ID_VIA,
+        .device_id        = PCI_DEVICE_ID_VIA_UHCI,
+        .revision_id      = 0x01,
+    },
 };
 
 static void uhci_register(void)
 {
-    pci_qdev_register_many(uhci_info);
+    int i;
+    for (i = 0; i < ARRAY_SIZE(uhci_info); i++) {
+        pci_qdev_register(&uhci_info[i].pci);
+    }
 }
 device_init(uhci_register);
 
-- 
1.7.1.1

[Qemu-devel] [PATCH 13/26] usb/uhci: add ich9 usb uhci id's device

[Isaku Yamahata]

add uhci device which has ich9 device id.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pci_ids.h  |    2 ++
 hw/usb-uhci.c |    8 ++++++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index ea3418c..9daea23 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -108,3 +108,5 @@
 #define PCI_DEVICE_ID_INTEL_82371AB      0x7111
 #define PCI_DEVICE_ID_INTEL_82371AB_2    0x7112
 #define PCI_DEVICE_ID_INTEL_82371AB_3    0x7113
+
+#define PCI_DEVICE_ID_INTEL_ICH9_UCHI1   0x2934
diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
index 2fb2a85..247f1bf 100644
--- a/hw/usb-uhci.c
+++ b/hw/usb-uhci.c
@@ -1193,6 +1193,14 @@ static UHCIDeviceInfo uhci_info[] = {
         .device_id        = PCI_DEVICE_ID_INTEL_82371AB_2,
         .revision_id      = 0x01,
     },{
+        .pci.qdev.name    = "ich9-usb-uhci1",
+        .pci.qdev.size    = sizeof(UHCIState),
+        .pci.qdev.vmsd    = &vmstate_uhci,
+        .pci.init         = usb_uhci_common_initfn,
+        .vendor_id        = PCI_VENDOR_ID_INTEL,
+        .device_id        = PCI_DEVICE_ID_INTEL_ICH9_UCHI1,
+        .revision_id      = 0x03,
+    },{
         .pci.qdev.name    = "vt82c686b-usb-uhci",
         .pci.qdev.size    = sizeof(UHCIState),
         .pci.qdev.vmsd    = &vmstate_uhci,
-- 
1.7.1.1

[Qemu-devel] [PATCH 14/26] ide: consolidate drive_get(IF_IDE)

[Isaku Yamahata]

factor out ide initialization to call drive_get(IF_IDE)

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/ide.h           |    3 +++
 hw/ide/core.c      |   14 ++++++++++++++
 hw/mips_fulong2e.c |    9 +--------
 hw/mips_malta.c    |   10 +---------
 hw/mips_r4k.c      |   10 +---------
 hw/pc_piix.c       |   13 ++-----------
 hw/ppc_newworld.c  |   11 ++---------
 hw/ppc_oldworld.c  |   11 +++--------
 hw/ppc_prep.c      |   10 +---------
 hw/sun4u.c         |    9 +--------
 10 files changed, 29 insertions(+), 71 deletions(-)

diff --git a/hw/ide.h b/hw/ide.h
index e90f557..66c348b 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -28,6 +28,9 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
 
 void ide_get_bs(BlockDriverState *bs[], BusState *qbus);
 
+/* ide/core.c */
+void ide_drive_get(DriveInfo **hd, int max_bus);
+
 /* ide/ahci.c */
 void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
 
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 9c91a49..afdf126 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -2811,3 +2811,17 @@ const VMStateDescription vmstate_ide_bus = {
         VMSTATE_END_OF_LIST()
     }
 };
+
+void ide_drive_get(DriveInfo **hd, int max_bus)
+{
+    int i;
+
+    if (drive_get_max_bus(IF_IDE) >= max_bus) {
+        fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
+        exit(1);
+    }
+
+    for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
+        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
+    }
+}
diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
index f5ae639..0e90d68 100644
--- a/hw/mips_fulong2e.c
+++ b/hw/mips_fulong2e.c
@@ -338,14 +338,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
     pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
 
     /* South bridge */
-    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
-        fprintf(stderr, "qemu: too many IDE bus\n");
-        exit(1);
-    }
-
-    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
-        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
-    }
+    ide_drive_get(hd, MAX_IDE_BUS);
 
     via_devfn = vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 0));
     if (via_devfn < 0) {
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index d8baa6d..bf0d76d 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -905,15 +905,7 @@ void mips_malta_init (ram_addr_t ram_size,
     pci_bus = gt64120_register(i8259);
 
     /* Southbridge */
-
-    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
-        fprintf(stderr, "qemu: too many IDE bus\n");
-        exit(1);
-    }
-
-    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
-        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
-    }
+    ide_drive_get(hd, MAX_IDE_BUS);
 
     piix4_devfn = piix4_init(pci_bus, 80);
     isa_bus_irqs(i8259);
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 8feb461..2834a46 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -287,15 +287,7 @@ void mips_r4k_init (ram_addr_t ram_size,
     if (nd_table[0].vlan)
         isa_ne2000_init(0x300, 9, &nd_table[0]);
 
-    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
-        fprintf(stderr, "qemu: too many IDE bus\n");
-        exit(1);
-    }
-
-    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
-        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
-    }
-
+    ide_drive_get(hd, MAX_IDE_BUS);
     for(i = 0; i < MAX_IDE_BUS; i++)
         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
                      hd[MAX_IDE_DEVS * i],
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index b3ede89..8ea023d 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -129,18 +129,9 @@ static void pc_init1(ram_addr_t ram_size,
             pci_nic_init_nofail(nd, "e1000", NULL);
     }
 
-    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
-        fprintf(stderr, "qemu: too many IDE bus\n");
-        exit(1);
-    }
-
-    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
-        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
-    }
-
+    ide_drive_get(hd, MAX_IDE_BUS);
     if (pci_enabled) {
-        PCIDevice *dev;
-        dev = pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
+        PCIDevice *dev = pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
         idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
         idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
     } else {
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index b9245f0..86f1cfb 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -325,20 +325,13 @@ static void ppc_core99_init (ram_addr_t ram_size,
     for(i = 0; i < nb_nics; i++)
         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 
-    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
-        fprintf(stderr, "qemu: too many IDE bus\n");
-        exit(1);
-    }
+    ide_drive_get(hd, MAX_IDE_BUS);
     dbdma = DBDMA_init(&dbdma_mem_index);
 
     /* We only emulate 2 out of 3 IDE controllers for now */
     ide_mem_index[0] = -1;
-    hd[0] = drive_get(IF_IDE, 0, 0);
-    hd[1] = drive_get(IF_IDE, 0, 1);
     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]);
-    hd[0] = drive_get(IF_IDE, 1, 0);
-    hd[1] = drive_get(IF_IDE, 1, 1);
-    ide_mem_index[2] = pmac_ide_init(hd, pic[0x0e], dbdma, 0x1a, pic[0x02]);
+    ide_mem_index[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]);
 
     /* cuda also initialize ADB */
     if (machine_arch == ARCH_MAC99_U3) {
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 8a4e088..75a3127 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -236,21 +236,16 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 
 
-    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
-        fprintf(stderr, "qemu: too many IDE bus\n");
-        exit(1);
-    }
+    ide_drive_get(hd, MAX_IDE_BUS);
 
     /* First IDE channel is a MAC IDE on the MacIO bus */
-    hd[0] = drive_get(IF_IDE, 0, 0);
-    hd[1] = drive_get(IF_IDE, 0, 1);
     dbdma = DBDMA_init(&dbdma_mem_index);
     ide_mem_index[0] = -1;
     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 
     /* Second IDE channel is a CMD646 on the PCI bus */
-    hd[0] = drive_get(IF_IDE, 1, 0);
-    hd[1] = drive_get(IF_IDE, 1, 1);
+    hd[0] = hd[MAX_IDE_DEVS];
+    hd[1] = hd[MAX_IDE_DEVS + 1];
     hd[3] = hd[2] = NULL;
     pci_cmd646_ide_init(pci_bus, hd, 0);
 
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index d86a283..16ca49f 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -681,15 +681,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
         }
     }
 
-    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
-        fprintf(stderr, "qemu: too many IDE bus\n");
-        exit(1);
-    }
-
-    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
-        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
-    }
-
+    ide_drive_get(hd, MAX_IDE_BUS);
     for(i = 0; i < MAX_IDE_BUS; i++) {
         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
                      hd[2 * i],
diff --git a/hw/sun4u.c b/hw/sun4u.c
index d282324..55ac182 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -793,14 +793,7 @@ static void sun4uv_init(ram_addr_t RAM_size,
     for(i = 0; i < nb_nics; i++)
         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 
-    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
-        fprintf(stderr, "qemu: too many IDE bus\n");
-        exit(1);
-    }
-    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
-        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
-                          i % MAX_IDE_DEVS);
-    }
+    ide_drive_get(hd, MAX_IDE_BUS);
 
     pci_cmd646_ide_init(pci_bus, hd, 1);
 
-- 
1.7.1.1

[Qemu-devel] [PATCH 15/26] smbus_eeprom: consolidate smbus eeprom creation

[Isaku Yamahata]

consolidate smbus initialization for pc_piix, mips_malta and mips_fulong.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>

Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Huacai Chen <zltjiangshi@gmail.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/mips_fulong2e.c |    9 +--------
 hw/mips_malta.c    |   12 ++----------
 hw/pc_piix.c       |   10 ++--------
 hw/smbus.h         |    3 +++
 hw/smbus_eeprom.c  |   22 ++++++++++++++++++++--
 5 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
index 0e90d68..420fada 100644
--- a/hw/mips_fulong2e.c
+++ b/hw/mips_fulong2e.c
@@ -263,11 +263,9 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
     qemu_irq *cpu_exit_irq;
     int via_devfn;
     PCIBus *pci_bus;
-    uint8_t *eeprom_buf;
     i2c_bus *smbus;
     int i;
     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
-    DeviceState *eeprom;
     CPUState *env;
 
     /* init CPUs */
@@ -353,13 +351,8 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
 
     smbus = vt82c686b_pm_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 4),
                               0xeee1, NULL);
-    eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
-    memcpy(eeprom_buf, eeprom_spd, sizeof(eeprom_spd));
     /* TODO: Populate SPD eeprom data.  */
-    eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
-    qdev_prop_set_uint8(eeprom, "address", 0x50);
-    qdev_prop_set_ptr(eeprom, "data", eeprom_buf);
-    qdev_init_nofail(eeprom);
+    smbus_eeprom_init(smbus, 1, eeprom_spd, sizeof(eeprom_spd));
 
     /* init other devices */
     pit = pit_init(0x40, 0);
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index bf0d76d..ed2a483 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -770,7 +770,6 @@ void mips_malta_init (ram_addr_t ram_size,
     qemu_irq *i8259;
     qemu_irq *cpu_exit_irq;
     int piix4_devfn;
-    uint8_t *eeprom_buf;
     i2c_bus *smbus;
     int i;
     DriveInfo *dinfo;
@@ -913,15 +912,8 @@ void mips_malta_init (ram_addr_t ram_size,
     usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(9),
                           NULL, NULL, 0);
-    eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
-    for (i = 0; i < 8; i++) {
-        /* TODO: Populate SPD eeprom data.  */
-        DeviceState *eeprom;
-        eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
-        qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
-        qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
-        qdev_init_nofail(eeprom);
-    }
+    /* TODO: Populate SPD eeprom data.  */
+    smbus_eeprom_init(smbus, 8, NULL, 0);
     pit = pit_init(0x40, 0);
     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
     DMA_init(0, cpu_exit_irq);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 8ea023d..337f2ec 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -37,6 +37,7 @@
 #include "sysbus.h"
 #include "arch_init.h"
 #include "blockdev.h"
+#include "smbus.h"
 
 #define MAX_IDE_BUS 2
 
@@ -153,7 +154,6 @@ static void pc_init1(ram_addr_t ram_size,
     }
 
     if (pci_enabled && acpi_enabled) {
-        uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
         i2c_bus *smbus;
 
         cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
@@ -162,13 +162,7 @@ static void pc_init1(ram_addr_t ram_size,
         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
                               isa_get_irq(9), *cmos_s3, *smi_irq,
                               kvm_enabled());
-        for (i = 0; i < 8; i++) {
-            DeviceState *eeprom;
-            eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
-            qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
-            qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
-            qdev_init_nofail(eeprom);
-        }
+        smbus_eeprom_init(smbus, 8, NULL, 0);
     }
 
     if (i440fx_state) {
diff --git a/hw/smbus.h b/hw/smbus.h
index 571c52d..a398715 100644
--- a/hw/smbus.h
+++ b/hw/smbus.h
@@ -66,3 +66,6 @@ void smbus_write_word(i2c_bus *bus, uint8_t addr, uint8_t command, uint16_t data
 int smbus_read_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data);
 void smbus_write_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data,
                        int len);
+
+void smbus_eeprom_init(i2c_bus *smbus, int nb_eeprom,
+                       const uint8_t *eeprom_spd, int size);
diff --git a/hw/smbus_eeprom.c b/hw/smbus_eeprom.c
index 52463e0..3634754 100644
--- a/hw/smbus_eeprom.c
+++ b/hw/smbus_eeprom.c
@@ -96,7 +96,7 @@ static uint8_t eeprom_read_data(SMBusDevice *dev, uint8_t cmd, int n)
     return eeprom_receive_byte(dev);
 }
 
-static int smbus_eeprom_init(SMBusDevice *dev)
+static int smbus_eeprom_initfn(SMBusDevice *dev)
 {
     SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *)dev;
 
@@ -111,7 +111,7 @@ static SMBusDeviceInfo smbus_eeprom_info = {
         DEFINE_PROP_PTR("data", SMBusEEPROMDevice, data),
         DEFINE_PROP_END_OF_LIST(),
     },
-    .init = smbus_eeprom_init,
+    .init = smbus_eeprom_initfn,
     .quick_cmd = eeprom_quick_cmd,
     .send_byte = eeprom_send_byte,
     .receive_byte = eeprom_receive_byte,
@@ -125,3 +125,21 @@ static void smbus_eeprom_register_devices(void)
 }
 
 device_init(smbus_eeprom_register_devices)
+
+void smbus_eeprom_init(i2c_bus *smbus, int nb_eeprom,
+                       const uint8_t *eeprom_spd, int eeprom_spd_size)
+{
+    int i;
+    uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
+    if (eeprom_spd_size > 0) {
+        memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size);
+    }
+
+    for (i = 0; i < nb_eeprom; i++) {
+        DeviceState *eeprom;
+        eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
+        qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
+        qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
+        qdev_init_nofail(eeprom);
+    }
+}
-- 
1.7.1.1

[Qemu-devel] [PATCH 16/26] pc, pc_piix: split out allocating isa irqs

[Isaku Yamahata]

Factor out the logic of allocating isa irqs.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pc.c      |   16 ++++++++++++++--
 hw/pc.h      |    2 +-
 hw/pc_piix.c |    8 +-------
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/hw/pc.c b/hw/pc.c
index 4d67d9f..39c7cf0 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1044,9 +1044,21 @@ void pc_memory_init(ram_addr_t ram_size,
     }
 }
 
-qemu_irq *pc_allocate_cpu_irq(void)
+qemu_irq *pc_isa_irq(IsaIrqState **isa_irq_state_p)
 {
-    return qemu_allocate_irqs(pic_irq_request, NULL, 1);
+    qemu_irq *cpu_irq;
+    qemu_irq *i8259;
+    IsaIrqState *isa_irq_state;
+    qemu_irq *isa_irq;
+
+    cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);;
+    i8259 = i8259_init(cpu_irq[0]);
+    isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
+    isa_irq_state->i8259 = i8259;
+    isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
+
+    *isa_irq_state_p = isa_irq_state;
+    return isa_irq;
 }
 
 void pc_vga_init(PCIBus *pci_bus)
diff --git a/hw/pc.h b/hw/pc.h
index feb8a7a..0ee4b89 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -135,7 +135,7 @@ void pc_memory_init(ram_addr_t ram_size,
                     const char *initrd_filename,
                     ram_addr_t *below_4g_mem_size_p,
                     ram_addr_t *above_4g_mem_size_p);
-qemu_irq *pc_allocate_cpu_irq(void);
+qemu_irq *pc_isa_irq(IsaIrqState **isa_irq_state_p);
 void pc_vga_init(PCIBus *pci_bus);
 void pc_basic_device_init(qemu_irq *isa_irq,
                           ISADevice **rtc_state);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 337f2ec..1ac69ff 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -76,9 +76,7 @@ static void pc_init1(ram_addr_t ram_size,
     PCIBus *pci_bus;
     PCII440FXState *i440fx_state;
     int piix3_devfn = -1;
-    qemu_irq *cpu_irq;
     qemu_irq *isa_irq;
-    qemu_irq *i8259;
     qemu_irq *cmos_s3;
     qemu_irq *smi_irq;
     IsaIrqState *isa_irq_state;
@@ -96,14 +94,10 @@ static void pc_init1(ram_addr_t ram_size,
     pc_memory_init(ram_size, kernel_filename, kernel_cmdline, initrd_filename,
                    &below_4g_mem_size, &above_4g_mem_size);
 
-    cpu_irq = pc_allocate_cpu_irq();
-    i8259 = i8259_init(cpu_irq[0]);
-    isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
-    isa_irq_state->i8259 = i8259;
+    isa_irq = pc_isa_irq(&isa_irq_state);
     if (pci_enabled) {
         ioapic_init(isa_irq_state);
     }
-    isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
 
     if (pci_enabled) {
         pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size);
-- 
1.7.1.1

[Qemu-devel] [PATCH 17/26] pc, pc_piix: split out pc nic initialization

[Isaku Yamahata]

Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pc.c      |   15 +++++++++++++++
 hw/pc.h      |    1 +
 hw/pc_piix.c |    9 +--------
 3 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/hw/pc.c b/hw/pc.c
index 39c7cf0..dc771a6 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1167,6 +1167,21 @@ void pc_basic_device_init(qemu_irq *isa_irq,
     fdctrl_init_isa(fd);
 }
 
+void pc_nic_init(PCIBus *pci_bus)
+{
+    int i;
+
+    for(i = 0; i < nb_nics; i++) {
+        NICInfo *nd = &nd_table[i];
+
+        if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
+            pc_init_ne2k_isa(nd);
+        } else {
+            pci_nic_init_nofail(nd, "e1000", NULL);
+        }
+    }
+}
+
 void pc_pci_device_init(PCIBus *pci_bus)
 {
     int max_bus;
diff --git a/hw/pc.h b/hw/pc.h
index 0ee4b89..b70c5f4 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -144,6 +144,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
                   const char *boot_device,
                   BusState *ide0, BusState *ide1,
                   ISADevice *s);
+void pc_nic_init(PCIBus *pci_bus);
 void pc_pci_device_init(PCIBus *pci_bus);
 
 typedef void (*cpu_set_smm_t)(int smm, void *arg);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 1ac69ff..8ee7cab 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -115,14 +115,7 @@ static void pc_init1(ram_addr_t ram_size,
     /* init basic PC hardware */
     pc_basic_device_init(isa_irq, &rtc_state);
 
-    for(i = 0; i < nb_nics; i++) {
-        NICInfo *nd = &nd_table[i];
-
-        if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
-            pc_init_ne2k_isa(nd);
-        else
-            pci_nic_init_nofail(nd, "e1000", NULL);
-    }
+    pc_nic_init(pci_bus);
 
     ide_drive_get(hd, MAX_IDE_BUS);
     if (pci_enabled) {
-- 
1.7.1.1

[Qemu-devel] [PATCH 18/26] ioapic: move ioapic_init() from pc_piix.c to pc.c

[Isaku Yamahata]

ioapic isn't piix specific. And q35 pc will use it.
So move ioapic_init() from pc_piix.c to common place, pc.c.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pc.c      |   16 ++++++++++++++++
 hw/pc.h      |    2 ++
 hw/pc_piix.c |   16 ----------------
 3 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/hw/pc.c b/hw/pc.c
index dc771a6..97d383d 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1192,3 +1192,19 @@ void pc_pci_device_init(PCIBus *pci_bus)
         pci_create_simple(pci_bus, -1, "lsi53c895a");
     }
 }
+
+void ioapic_init(IsaIrqState *isa_irq_state)
+{
+    DeviceState *dev;
+    SysBusDevice *d;
+    unsigned int i;
+
+    dev = qdev_create(NULL, "ioapic");
+    qdev_init_nofail(dev);
+    d = sysbus_from_qdev(dev);
+    sysbus_mmio_map(d, 0, 0xfec00000);
+
+    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
+        isa_irq_state->ioapic[i] = qdev_get_gpio_in(dev, i);
+    }
+}
diff --git a/hw/pc.h b/hw/pc.h
index b70c5f4..598747d 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -150,6 +150,8 @@ void pc_pci_device_init(PCIBus *pci_bus);
 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
 
+void ioapic_init(IsaIrqState *isa_irq_state);
+
 /* acpi.c */
 extern int acpi_enabled;
 extern char *acpi_tables;
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 8ee7cab..f04d58b 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -45,22 +45,6 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
 static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
 static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
 
-static void ioapic_init(IsaIrqState *isa_irq_state)
-{
-    DeviceState *dev;
-    SysBusDevice *d;
-    unsigned int i;
-
-    dev = qdev_create(NULL, "ioapic");
-    qdev_init_nofail(dev);
-    d = sysbus_from_qdev(dev);
-    sysbus_mmio_map(d, 0, 0xfec00000);
-
-    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
-        isa_irq_state->ioapic[i] = qdev_get_gpio_in(dev, i);
-    }
-}
-
 /* PC hardware initialisation */
 static void pc_init1(ram_addr_t ram_size,
                      const char *boot_device,
-- 
1.7.1.1

[Qemu-devel] [PATCH 19/26] pc/piix_pci: factor out smram/pam logic

[Isaku Yamahata]

Factor out smram/pam logic for later use.
Which will be used by q35 too.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 Makefile.target |    2 +-
 hw/pam.c        |  128 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/pam.h        |   96 +++++++++++++++++++++++++++++++++++++++++
 hw/piix_pci.c   |   71 +++++--------------------------
 4 files changed, 236 insertions(+), 61 deletions(-)
 create mode 100644 hw/pam.c
 create mode 100644 hw/pam.h

diff --git a/Makefile.target b/Makefile.target
index f0df98e..d57d250 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -214,7 +214,7 @@ obj-$(CONFIG_KVM) += ivshmem.o
 # Hardware support
 obj-i386-y += vga.o
 obj-i386-y += mc146818rtc.o i8259.o pc.o
-obj-i386-y += cirrus_vga.o apic.o ioapic.o piix_pci.o
+obj-i386-y += cirrus_vga.o apic.o ioapic.o piix_pci.o pam.o
 obj-i386-y += vmport.o
 obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o
 obj-i386-y += debugcon.o multiboot.o
diff --git a/hw/pam.c b/hw/pam.c
new file mode 100644
index 0000000..cd85faf
--- /dev/null
+++ b/hw/pam.c
@@ -0,0 +1,128 @@
+/*
+ * QEMU i440FX/PIIX3 PCI Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Split out from piix_pci.c
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ */
+
+#include "sysemu.h"
+#include "pam.h"
+
+/* XXX: suppress when better memory API. We make the assumption that
+   no device (in particular the VGA) changes the memory mappings in
+   the 0xa0000-0x100000 range */
+void pam_init_memory_mappings(PAM *pam)
+{
+    int i;
+    for(i = 0; i < ARRAY_SIZE(pam->isa_page_descs); i++) {
+        pam->isa_page_descs[i] =
+            cpu_get_physical_page_desc(SMRAM_C_BASE + (i << TARGET_PAGE_BITS));
+    }
+}
+
+static target_phys_addr_t isa_page_descs_get(PAM *pam, uint32_t addr)
+{
+    return pam->isa_page_descs[(addr - SMRAM_C_BASE) >> TARGET_PAGE_BITS];
+}
+
+void smram_update(PAM *pam, uint8_t smram)
+{
+    if ((pam->smm_enabled && (smram & SMRAM_G_SMRAME)) ||
+        (smram & SMRAM_D_OPEN)) {
+        cpu_register_physical_memory(SMRAM_C_BASE, SMRAM_C_SIZE, SMRAM_C_BASE);
+    } else {
+        uint32_t addr;
+        for(addr = SMRAM_C_BASE;
+            addr < SMRAM_C_END; addr += TARGET_PAGE_SIZE) {
+            cpu_register_physical_memory(addr, TARGET_PAGE_SIZE,
+                                         isa_page_descs_get(pam, addr));
+        }
+    }
+}
+
+void smram_set_smm(PAM *pam, int smm, uint8_t smram)
+{
+    uint8_t smm_enabled = (smm != 0);
+    if (pam->smm_enabled != smm_enabled) {
+        pam->smm_enabled = smm_enabled;
+        smram_update(pam, smram);
+    }
+}
+
+static void pam_update_seg(struct PAM *pam,
+                           uint32_t start, uint32_t size, uint8_t attr)
+{
+    uint32_t addr;
+
+#if 0
+    printf("ISA mapping %08"PRIx32"-0x%08"PRIx32": %"PRId32"\n",
+           start, start + size, attr);
+#endif
+    switch(attr) {
+    case PAM_ATTR_WE | PAM_ATTR_RE:
+        /* RAM */
+        cpu_register_physical_memory(start, size, start);
+        break;
+
+    case PAM_ATTR_RE:
+        /* ROM (XXX: not quite correct) */
+        cpu_register_physical_memory(start, size, start | IO_MEM_ROM);
+        break;
+
+    case PAM_ATTR_WE:
+    case 0: /* XXX: should distinguish read/write cases */
+        for(addr = start; addr < start + size; addr += TARGET_PAGE_SIZE) {
+            cpu_register_physical_memory(addr, TARGET_PAGE_SIZE,
+                                         isa_page_descs_get(pam, addr));
+        }
+        break;
+
+    default:
+        abort();
+        break;
+    }
+}
+
+static uint8_t pam_attr(uint8_t val, int hi)
+{
+    return (val >> ((!!hi) * 4)) & PAM_ATTR_MASK;
+}
+
+void pam_update(PAM *pam, int idx, uint8_t val)
+{
+    uint32_t phys_addr;
+
+    assert(0 <= idx && idx <= PAM_IDX_MAX);
+
+    if (idx == 0) {
+        pam_update_seg(pam, PAM_BIOS_BASE, PAM_BIOS_SIZE, pam_attr(val, 1));
+        return;
+    }
+
+    phys_addr = PAM_EXPAN_BASE + PAM_EXPAN_SIZE * (idx - 1) * 2;
+    pam_update_seg(pam, phys_addr, PAM_EXPAN_SIZE, pam_attr(val, 0));
+
+    phys_addr += PAM_EXPAN_SIZE;
+    pam_update_seg(pam, phys_addr, PAM_EXPAN_SIZE, pam_attr(val, 1));
+}
diff --git a/hw/pam.h b/hw/pam.h
new file mode 100644
index 0000000..cb66056
--- /dev/null
+++ b/hw/pam.h
@@ -0,0 +1,96 @@
+#ifndef QEMU_PAM_H
+#define QEMU_PAM_H
+
+/*
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Split out from piix_pci.c
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ *
+ * SMRAM memory area and PAM memory area in Legacy address range for PC.
+ * PAM: Programmable Attribute Map registers
+ *
+ * 0xa0000 - 0xbffff compatible SMRAM
+ *
+ * 0xc0000 - 0xc3fff Expansion area memory segments
+ * 0xc4000 - 0xc7fff
+ * 0xc8000 - 0xcbfff
+ * 0xcc000 - 0xcffff
+ * 0xd0000 - 0xd7fff
+ * 0xd8000 - 0xdbfff
+ * 0xdc000 - 0xdffff
+ * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
+ * 0xe4000 - 0xe7fff
+ * 0xe8000 - 0xebfff
+ * 0xec000 - 0xeffff
+ *
+ * 0xf0000 - 0xfffff System BIOS Area Memory Segments
+ */
+
+#include "qemu-common.h"
+
+#define SMRAM_C_BASE    0xa0000
+#define SMRAM_C_END     0xc0000
+#define SMRAM_C_SIZE    0x20000
+
+
+#define PAM_EXPAN_BASE  0xc0000
+#define PAM_EXPAN_SIZE  0x04000
+
+#define PAM_EXBIOS_BASE 0xe0000
+#define PAM_EXBIOS_SIZE 0x04000
+
+#define PAM_BIOS_BASE   0xf0000
+#define PAM_BIOS_END    0x100000
+#define PAM_BIOS_SIZE   0x10000 /* 16KB */
+
+/* PAM registers: log nibble and high nibble*/
+#define PAM_ATTR_WE     ((uint8_t)2)
+#define PAM_ATTR_RE     ((uint8_t)1)
+#define PAM_ATTR_MASK   ((uint8_t)3)
+
+#define PAM_IDX_MAX     6       /* pam0 - pam6 */
+
+/* SMRAM register */
+#define SMRAM_D_OPEN           ((uint8_t)(1 << 6))
+#define SMRAM_D_CLS            ((uint8_t)(1 << 5))
+#define SMRAM_D_LCK            ((uint8_t)(1 << 4))
+#define SMRAM_G_SMRAME         ((uint8_t)(1 << 3))
+#define SMRAM_C_BASE_SEG_MASK  ((uint8_t)0x7)
+#define SMRAM_C_BASE_SEG       ((uint8_t)0x2)  /* hardwired to b010 */
+
+
+struct PAM {
+    target_phys_addr_t
+    isa_page_descs[(PAM_BIOS_END - SMRAM_C_BASE) >> TARGET_PAGE_BITS];
+    uint8_t smm_enabled;
+};
+
+typedef struct PAM PAM;
+
+void pam_init_memory_mappings(PAM *pam);
+void smram_update(PAM *pam, uint8_t smram);
+void smram_set_smm(PAM *pam, int smm, uint8_t smram);
+void pam_update(PAM *pam, int idx, uint8_t val);
+
+#endif /* QEMU_PAM_H */
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 2d0ad9b..f619162 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -29,6 +29,7 @@
 #include "isa.h"
 #include "sysbus.h"
 #include "range.h"
+#include "pam.h"
 
 /*
  * I440FX chipset data sheet.
@@ -45,8 +46,7 @@ typedef struct PIIX3State {
 
 struct PCII440FXState {
     PCIDevice dev;
-    target_phys_addr_t isa_page_descs[384 / 4];
-    uint8_t smm_enabled;
+    PAM pam;
     PIIX3State *piix3;
 };
 
@@ -67,75 +67,26 @@ static int pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int irq_num)
     return (irq_num + slot_addend) & 3;
 }
 
-static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
-{
-    uint32_t addr;
-
-    //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
-    switch(r) {
-    case 3:
-        /* RAM */
-        cpu_register_physical_memory(start, end - start,
-                                     start);
-        break;
-    case 1:
-        /* ROM (XXX: not quite correct) */
-        cpu_register_physical_memory(start, end - start,
-                                     start | IO_MEM_ROM);
-        break;
-    case 2:
-    case 0:
-        /* XXX: should distinguish read/write cases */
-        for(addr = start; addr < end; addr += 4096) {
-            cpu_register_physical_memory(addr, 4096,
-                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
-        }
-        break;
-    }
-}
-
 static void i440fx_update_memory_mappings(PCII440FXState *d)
 {
-    int i, r;
-    uint32_t smram, addr;
+    int i;
 
-    update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
-    for(i = 0; i < 12; i++) {
-        r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
-        update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
-    }
-    smram = d->dev.config[I440FX_SMRAM];
-    if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
-        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
-    } else {
-        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
-            cpu_register_physical_memory(addr, 4096,
-                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
-        }
+    for (i = 0; i <= PAM_IDX_MAX; i++) {
+        pam_update(&d->pam, i, d->dev.config[I440FX_PAM + i]);
     }
+
+    smram_update(&d->pam, d->dev.config[I440FX_SMRAM]);
 }
 
 static void i440fx_set_smm(int val, void *arg)
 {
     PCII440FXState *d = arg;
-
-    val = (val != 0);
-    if (d->smm_enabled != val) {
-        d->smm_enabled = val;
-        i440fx_update_memory_mappings(d);
-    }
+    smram_set_smm(&d->pam, val, d->dev.config[I440FX_SMRAM]);
 }
 
-
-/* XXX: suppress when better memory API. We make the assumption that
-   no device (in particular the VGA) changes the memory mappings in
-   the 0xa0000-0x100000 range */
 void i440fx_init_memory_mappings(PCII440FXState *d)
 {
-    int i;
-    for(i = 0; i < 96; i++) {
-        d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
-    }
+    pam_init_memory_mappings(&d->pam);
 }
 
 static void i440fx_write_config(PCIDevice *dev,
@@ -160,7 +111,7 @@ static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
     if (ret < 0)
         return ret;
     i440fx_update_memory_mappings(d);
-    qemu_get_8s(f, &d->smm_enabled);
+    qemu_get_8s(f, &d->pam.smm_enabled);
 
     if (version_id == 2) {
         for (i = 0; i < 4; i++) {
@@ -188,7 +139,7 @@ static const VMStateDescription vmstate_i440fx = {
     .post_load = i440fx_post_load,
     .fields      = (VMStateField []) {
         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
-        VMSTATE_UINT8(smm_enabled, PCII440FXState),
+        VMSTATE_UINT8(pam.smm_enabled, PCII440FXState),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
1.7.1.1

[Qemu-devel] [PATCH 20/26] pc, i440fx: simply i440fx initialization

[Isaku Yamahata]

simply i440fx initialization by eliminating
i440fx_init_memory_mappings().

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pc.h       |    2 +-
 hw/pc_piix.c  |    8 +-------
 hw/piix_pci.c |   15 ++++++---------
 3 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/hw/pc.h b/hw/pc.h
index 598747d..d382bb6 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -178,7 +178,7 @@ int pcspk_audio_init(qemu_irq *pic);
 struct PCII440FXState;
 typedef struct PCII440FXState PCII440FXState;
 
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic, ram_addr_t ram_size);
+PCIBus *i440fx_init(int *piix_devfn, qemu_irq *pic, ram_addr_t ram_size);
 void i440fx_init_memory_mappings(PCII440FXState *d);
 
 /* piix4.c */
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index f04d58b..a3697e7 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -58,7 +58,6 @@ static void pc_init1(ram_addr_t ram_size,
     int i;
     ram_addr_t below_4g_mem_size, above_4g_mem_size;
     PCIBus *pci_bus;
-    PCII440FXState *i440fx_state;
     int piix3_devfn = -1;
     qemu_irq *isa_irq;
     qemu_irq *cmos_s3;
@@ -84,10 +83,9 @@ static void pc_init1(ram_addr_t ram_size,
     }
 
     if (pci_enabled) {
-        pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size);
+        pci_bus = i440fx_init(&piix3_devfn, isa_irq, ram_size);
     } else {
         pci_bus = NULL;
-        i440fx_state = NULL;
         isa_bus_new(NULL);
     }
     isa_bus_irqs(isa_irq);
@@ -136,10 +134,6 @@ static void pc_init1(ram_addr_t ram_size,
         smbus_eeprom_init(smbus, 8, NULL, 0);
     }
 
-    if (i440fx_state) {
-        i440fx_init_memory_mappings(i440fx_state);
-    }
-
     if (pci_enabled) {
         pc_pci_device_init(pci_bus);
     }
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index f619162..151353c 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -84,11 +84,6 @@ static void i440fx_set_smm(int val, void *arg)
     smram_set_smm(&d->pam, val, d->dev.config[I440FX_SMRAM]);
 }
 
-void i440fx_init_memory_mappings(PCII440FXState *d)
-{
-    pam_init_memory_mappings(&d->pam);
-}
-
 static void i440fx_write_config(PCIDevice *dev,
                                 uint32_t address, uint32_t val, int len)
 {
@@ -166,15 +161,17 @@ static int i440fx_initfn(PCIDevice *dev)
     d->dev.config[I440FX_SMRAM] = 0x02;
 
     cpu_smm_register(&i440fx_set_smm, d);
+    pam_init_memory_mappings(&d->pam);
     return 0;
 }
 
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
+PCIBus *i440fx_init(int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
 {
     DeviceState *dev;
     PCIBus *b;
     PCIDevice *d;
     I440FXState *s;
+    PCII440FXState *i440fx_state;
     PIIX3State *piix3;
 
     dev = qdev_create(NULL, "i440FX-pcihost");
@@ -184,20 +181,20 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *
     qdev_init_nofail(dev);
 
     d = pci_create_simple(b, 0, "i440FX");
-    *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
+    i440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 
     piix3 = DO_UPCAST(PIIX3State, dev,
                       pci_create_simple_multifunction(b, -1, true, "PIIX3"));
     piix3->pic = pic;
     pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
-    (*pi440fx_state)->piix3 = piix3;
+    i440fx_state->piix3 = piix3;
 
     *piix3_devfn = piix3->dev.devfn;
 
     ram_size = ram_size / 8 / 1024 / 1024;
     if (ram_size > 255)
         ram_size = 255;
-    (*pi440fx_state)->dev.config[0x57]=ram_size;
+    i440fx_state->dev.config[0x57]=ram_size;
 
     return b;
 }
-- 
1.7.1.1

[Qemu-devel] [PATCH 21/26] acpi, acpi_piix: factor out PM_TMR logic

[Isaku Yamahata]

factor out PM_TMR logic. Later This will be used by ich9 acpi.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/acpi.c       |   45 +++++++++++++++++++++++++++++++++++++++++++++
 hw/acpi.h       |   24 ++++++++++++++++++++++++
 hw/acpi_piix4.c |   45 ++++++++++++---------------------------------
 3 files changed, 81 insertions(+), 33 deletions(-)

diff --git a/hw/acpi.c b/hw/acpi.c
index e9bcf18..bd987e0 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -217,3 +217,48 @@ out:
     }
     return -1;
 }
+
+/* ACPI PM_TMR */
+void acpi_pm_tmr_update(ACPIPMTimer *tmr, bool enable)
+{
+    int64_t expire_time;
+
+    /* schedule a timer interruption if needed */
+    if (enable) {
+        expire_time = muldiv64(tmr->overflow_time, get_ticks_per_sec(),
+                               PM_TIMER_FREQUENCY);
+        qemu_mod_timer(tmr->timer, expire_time);
+    } else {
+        qemu_del_timer(tmr->timer);
+    }
+}
+
+void acpi_pm_tmr_calc_overflow_time(ACPIPMTimer *tmr)
+{
+    int64_t d = acpi_pm_tmr_get_clock();
+    tmr->overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
+}
+
+uint32_t acpi_pm_tmr_get(ACPIPMTimer *tmr)
+{
+    uint32_t d = acpi_pm_tmr_get_clock();;
+    return d & 0xffffff;
+}
+
+static void acpi_pm_tmr_timer(void *opaque)
+{
+    ACPIPMTimer *tmr = opaque;
+    tmr->update_sci(tmr);
+}
+
+void acpi_pm_tmr_init(ACPIPMTimer *tmr, acpi_update_sci_fn update_sci)
+{
+    tmr->update_sci = update_sci;
+    tmr->timer = qemu_new_timer(vm_clock, acpi_pm_tmr_timer, tmr);
+}
+
+void acpi_pm_tmr_reset(ACPIPMTimer *tmr)
+{
+    tmr->overflow_time = 0;
+    qemu_del_timer(tmr->timer);
+}
diff --git a/hw/acpi.h b/hw/acpi.h
index 5949958..1f9132f 100644
--- a/hw/acpi.h
+++ b/hw/acpi.h
@@ -74,5 +74,29 @@
 #define ACPI_BITMASK_ARB_DISABLE                0x0001
 
 /* PM_TMR */
+struct ACPIPMTimer;
+typedef struct ACPIPMTimer ACPIPMTimer;
+
+typedef void (*acpi_update_sci_fn)(ACPIPMTimer *tmr);
+
+struct ACPIPMTimer {
+    QEMUTimer *timer;
+    int64_t overflow_time;
+
+    acpi_update_sci_fn update_sci;
+};
+
+void acpi_pm_tmr_update(ACPIPMTimer *tmr, bool enable);
+void acpi_pm_tmr_calc_overflow_time(ACPIPMTimer *tmr);
+uint32_t acpi_pm_tmr_get(ACPIPMTimer *tmr);
+void acpi_pm_tmr_init(ACPIPMTimer *tmr, acpi_update_sci_fn update_sci);
+void acpi_pm_tmr_reset(ACPIPMTimer *tmr);
+
+#include "qemu-timer.h"
+static inline int64_t acpi_pm_tmr_get_clock(void)
+{
+    return muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
+                    get_ticks_per_sec());
+}
 
 #endif /* !QEMU_HW_ACPI_H */
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 5bbc2b5..d5f631a 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -60,8 +60,7 @@ typedef struct PIIX4PMState {
 
     APMState apm;
 
-    QEMUTimer *tmr_timer;
-    int64_t tmr_overflow_time;
+    ACPIPMTimer tmr;
 
     PMSMBus smb;
     uint32_t smb_io_base;
@@ -82,20 +81,10 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
 #define ACPI_ENABLE 0xf1
 #define ACPI_DISABLE 0xf0
 
-static uint32_t get_pmtmr(PIIX4PMState *s)
-{
-    uint32_t d;
-    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
-    return d & 0xffffff;
-}
-
 static int get_pmsts(PIIX4PMState *s)
 {
-    int64_t d;
-
-    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
-                 get_ticks_per_sec());
-    if (d >= s->tmr_overflow_time)
+    int64_t d = acpi_pm_tmr_get_clock();
+    if (d >= s->tmr.overflow_time)
         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
     return s->pmsts;
 }
@@ -103,7 +92,6 @@ static int get_pmsts(PIIX4PMState *s)
 static void pm_update_sci(PIIX4PMState *s)
 {
     int sci_level, pmsts;
-    int64_t expire_time;
 
     pmsts = get_pmsts(s);
     sci_level = (((pmsts & s->pmen) &
@@ -115,19 +103,13 @@ static void pm_update_sci(PIIX4PMState *s)
 
     qemu_set_irq(s->irq, sci_level);
     /* schedule a timer interruption if needed */
-    if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
-        !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
-        expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
-                               PM_TIMER_FREQUENCY);
-        qemu_mod_timer(s->tmr_timer, expire_time);
-    } else {
-        qemu_del_timer(s->tmr_timer);
-    }
+    acpi_pm_tmr_update(&s->tmr, (s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
+                       !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 }
 
-static void pm_tmr_timer(void *opaque)
+static void pm_tmr_timer(ACPIPMTimer *tmr)
 {
-    PIIX4PMState *s = opaque;
+    PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr);
     pm_update_sci(s);
 }
 
@@ -144,14 +126,11 @@ static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
     switch(addr) {
     case 0x00:
         {
-            int64_t d;
             int pmsts;
             pmsts = get_pmsts(s);
             if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
                 /* if TMRSTS is reset, then compute the new overflow time */
-                d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
-                             get_ticks_per_sec());
-                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
+                acpi_pm_tmr_calc_overflow_time(&s->tmr);
             }
             s->pmsts &= ~val;
             pm_update_sci(s);
@@ -210,7 +189,7 @@ static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
         val = s->pmcntrl;
         break;
     case 0x08:
-        val = get_pmtmr(s);
+        val = acpi_pm_tmr_get(&s->tmr);
         break;
     default:
         val = 0;
@@ -315,8 +294,8 @@ static const VMStateDescription vmstate_acpi = {
         VMSTATE_UINT16(pmen, PIIX4PMState),
         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
-        VMSTATE_TIMER(tmr_timer, PIIX4PMState),
-        VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
+        VMSTATE_TIMER(tmr.timer, PIIX4PMState),
+        VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
                        struct pci_status),
@@ -413,7 +392,7 @@ static int piix4_pm_initfn(PCIDevice *dev)
     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 
-    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
+    acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
 
     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 
-- 
1.7.1.1

[Qemu-devel] [PATCH 22/26] acpi, acpi_piix: factor out PM1a EVT logic

[Isaku Yamahata]

factor out ACPI PM1a EVT logic.
Later this will be used by ich9 acpi.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/acpi.c       |   37 +++++++++++++++++++++++++++++++++++++
 hw/acpi.h       |   13 +++++++++++++
 hw/acpi_piix4.c |   52 ++++++++++++++++------------------------------------
 3 files changed, 66 insertions(+), 36 deletions(-)

diff --git a/hw/acpi.c b/hw/acpi.c
index bd987e0..158f30d 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -15,6 +15,7 @@
  * You should have received a copy of the GNU Lesser General Public
  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  */
+#include "sysemu.h"
 #include "hw.h"
 #include "pc.h"
 #include "acpi.h"
@@ -218,6 +219,42 @@ out:
     return -1;
 }
 
+/* ACPI PM1a EVT */
+uint16_t acpi_pm1_evt_get_sts(ACPIPM1EVT *pm1, int64_t overflow_time)
+{
+    int64_t d = acpi_pm_tmr_get_clock();
+    if (d >= overflow_time) {
+        pm1->sts |= ACPI_BITMASK_TIMER_STATUS;
+    }
+    return pm1->sts;
+}
+
+void acpi_pm1_evt_write_sts(ACPIPM1EVT *pm1, ACPIPMTimer *tmr, uint16_t val)
+{
+    uint16_t pm1_sts = acpi_pm1_evt_get_sts(pm1, tmr->overflow_time);
+    if (pm1_sts & val & ACPI_BITMASK_TIMER_STATUS) {
+        /* if TMRSTS is reset, then compute the new overflow time */
+        acpi_pm_tmr_calc_overflow_time(tmr);
+    }
+    pm1->sts &= ~val;
+}
+
+void acpi_pm1_evt_power_down(ACPIPM1EVT *pm1, ACPIPMTimer *tmr)
+{
+    if (!pm1) {
+        qemu_system_shutdown_request();
+    } else if (pm1->en & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
+        pm1->sts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
+        tmr->update_sci(tmr);
+    }
+}
+
+void acpi_pm1_evt_reset(ACPIPM1EVT *pm1)
+{
+    pm1->sts = 0;
+    pm1->en = 0;
+}
+
 /* ACPI PM_TMR */
 void acpi_pm_tmr_update(ACPIPMTimer *tmr, bool enable)
 {
diff --git a/hw/acpi.h b/hw/acpi.h
index 1f9132f..f79939f 100644
--- a/hw/acpi.h
+++ b/hw/acpi.h
@@ -99,4 +99,17 @@ static inline int64_t acpi_pm_tmr_get_clock(void)
                     get_ticks_per_sec());
 }
 
+/* PM1a_EVT: piix and ich9 don't implement PM1b. */
+struct ACPIPM1EVT
+{
+    uint16_t sts;
+    uint16_t en;
+};
+typedef struct ACPIPM1EVT ACPIPM1EVT;
+
+uint16_t acpi_pm1_evt_get_sts(ACPIPM1EVT *pm1, int64_t overflow_time);
+void acpi_pm1_evt_write_sts(ACPIPM1EVT *pm1, ACPIPMTimer *tmr, uint16_t val);
+void acpi_pm1_evt_power_down(ACPIPM1EVT *pm1, ACPIPMTimer *tmr);
+void acpi_pm1_evt_reset(ACPIPM1EVT *pm1);
+
 #endif /* !QEMU_HW_ACPI_H */
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index d5f631a..5b4eef5 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -54,8 +54,7 @@ struct pci_status {
 typedef struct PIIX4PMState {
     PCIDevice dev;
     IORange ioport;
-    uint16_t pmsts;
-    uint16_t pmen;
+    ACPIPM1EVT pm1a;
     uint16_t pmcntrl;
 
     APMState apm;
@@ -81,20 +80,12 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
 #define ACPI_ENABLE 0xf1
 #define ACPI_DISABLE 0xf0
 
-static int get_pmsts(PIIX4PMState *s)
-{
-    int64_t d = acpi_pm_tmr_get_clock();
-    if (d >= s->tmr.overflow_time)
-        s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
-    return s->pmsts;
-}
-
 static void pm_update_sci(PIIX4PMState *s)
 {
     int sci_level, pmsts;
 
-    pmsts = get_pmsts(s);
-    sci_level = (((pmsts & s->pmen) &
+    pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
+    sci_level = (((pmsts & s->pm1a.en) &
                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
@@ -103,7 +94,7 @@ static void pm_update_sci(PIIX4PMState *s)
 
     qemu_set_irq(s->irq, sci_level);
     /* schedule a timer interruption if needed */
-    acpi_pm_tmr_update(&s->tmr, (s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
+    acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 }
 
@@ -125,19 +116,11 @@ static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 
     switch(addr) {
     case 0x00:
-        {
-            int pmsts;
-            pmsts = get_pmsts(s);
-            if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
-                /* if TMRSTS is reset, then compute the new overflow time */
-                acpi_pm_tmr_calc_overflow_time(&s->tmr);
-            }
-            s->pmsts &= ~val;
-            pm_update_sci(s);
-        }
+        acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
+        pm_update_sci(s);
         break;
     case 0x02:
-        s->pmen = val;
+        s->pm1a.en = val;
         pm_update_sci(s);
         break;
     case 0x04:
@@ -154,8 +137,8 @@ static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
                 case 1:
                     /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
                        Pretend that resume was caused by power button */
-                    s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
-                                 ACPI_BITMASK_POWER_BUTTON_STATUS);
+                    s->pm1a.sts |= (ACPI_BITMASK_WAKE_STATUS |
+                                    ACPI_BITMASK_POWER_BUTTON_STATUS);
                     qemu_system_reset_request();
                     if (s->cmos_s3) {
                         qemu_irq_raise(s->cmos_s3);
@@ -180,10 +163,10 @@ static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 
     switch(addr) {
     case 0x00:
-        val = get_pmsts(s);
+        val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
         break;
     case 0x02:
-        val = s->pmen;
+        val = s->pm1a.en;
         break;
     case 0x04:
         val = s->pmcntrl;
@@ -290,8 +273,8 @@ static const VMStateDescription vmstate_acpi = {
     .post_load = vmstate_acpi_post_load,
     .fields      = (VMStateField []) {
         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
-        VMSTATE_UINT16(pmsts, PIIX4PMState),
-        VMSTATE_UINT16(pmen, PIIX4PMState),
+        VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
+        VMSTATE_UINT16(pm1a.en, PIIX4PMState),
         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
         VMSTATE_TIMER(tmr.timer, PIIX4PMState),
@@ -342,13 +325,10 @@ static void piix4_reset(void *opaque)
 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 {
     PIIX4PMState *s = opaque;
+    ACPIPM1EVT *pm1a = s? &s->pm1a: NULL;
+    ACPIPMTimer *tmr = s? &s->tmr: NULL;
 
-    if (!s) {
-        qemu_system_shutdown_request();
-    } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
-        s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
-        pm_update_sci(s);
-    }
+    acpi_pm1_evt_power_down(pm1a, tmr);
 }
 
 static int piix4_pm_initfn(PCIDevice *dev)
-- 
1.7.1.1

[Qemu-devel] [PATCH 23/26] acpi, acpi_piix: factor out PM1_CNT logic

[Isaku Yamahata]

factor out ACPI PM1_CNT logic. This will be used by ich9 acpi.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/acpi.c       |   49 +++++++++++++++++++++++++++++++++++++++++++++++++
 hw/acpi.h       |   14 ++++++++++++++
 hw/acpi_piix4.c |   40 ++++++----------------------------------
 3 files changed, 69 insertions(+), 34 deletions(-)

diff --git a/hw/acpi.c b/hw/acpi.c
index 158f30d..24c878a 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -299,3 +299,52 @@ void acpi_pm_tmr_reset(ACPIPMTimer *tmr)
     tmr->overflow_time = 0;
     qemu_del_timer(tmr->timer);
 }
+
+/* ACPI PM1aCNT */
+void acpi_pm1_cnt_init(ACPIPM1CNT *pm1_cnt, qemu_irq cmos_s3)
+{
+    pm1_cnt->cmos_s3 = cmos_s3;
+}
+
+void acpi_pm1_cnt_write(ACPIPM1EVT *pm1a, ACPIPM1CNT *pm1_cnt, uint16_t val)
+{
+    pm1_cnt->cnt = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
+
+    if (val & ACPI_BITMASK_SLEEP_ENABLE) {
+        /* change suspend type */
+        uint16_t sus_typ = (val >> 10) & 7;
+        switch(sus_typ) {
+        case 0: /* soft power off */
+            qemu_system_shutdown_request();
+            break;
+        case 1:
+            /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
+               Pretend that resume was caused by power button */
+            pm1a->sts |=
+                (ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_POWER_BUTTON_STATUS);
+            qemu_system_reset_request();
+            qemu_irq_raise(pm1_cnt->cmos_s3);
+        default:
+            break;
+        }
+    }
+}
+
+void acpi_pm1_cnt_update(ACPIPM1CNT *pm1_cnt,
+                         bool sci_enable, bool sci_disable)
+{
+    /* ACPI specs 3.0, 4.7.2.5 */
+    if (sci_enable) {
+        pm1_cnt->cnt |= ACPI_BITMASK_SCI_ENABLE;
+    } else if (sci_disable) {
+        pm1_cnt->cnt &= ~ACPI_BITMASK_SCI_ENABLE;
+    }
+}
+
+void acpi_pm1_cnt_reset(ACPIPM1CNT *pm1_cnt)
+{
+    pm1_cnt->cnt = 0;
+    if (pm1_cnt->cmos_s3) {
+        qemu_irq_lower(pm1_cnt->cmos_s3);
+    }
+}
diff --git a/hw/acpi.h b/hw/acpi.h
index f79939f..ab70c00 100644
--- a/hw/acpi.h
+++ b/hw/acpi.h
@@ -112,4 +112,18 @@ void acpi_pm1_evt_write_sts(ACPIPM1EVT *pm1, ACPIPMTimer *tmr, uint16_t val);
 void acpi_pm1_evt_power_down(ACPIPM1EVT *pm1, ACPIPMTimer *tmr);
 void acpi_pm1_evt_reset(ACPIPM1EVT *pm1);
 
+/* PM1a_CNT: piix and ich9 don't implement PM1b CNT. */
+struct ACPIPM1CNT {
+    uint16_t cnt;
+
+    qemu_irq cmos_s3;
+};
+typedef struct ACPIPM1CNT ACPIPM1CNT;
+
+void acpi_pm1_cnt_init(ACPIPM1CNT *pm1_cnt, qemu_irq cmos_s3);
+void acpi_pm1_cnt_write(ACPIPM1EVT *pm1a, ACPIPM1CNT *pm1_cnt, uint16_t val);
+void acpi_pm1_cnt_update(ACPIPM1CNT *pm1_cnt,
+                         bool sci_enable, bool sci_disable);
+void acpi_pm1_cnt_reset(ACPIPM1CNT *pm1_cnt);
+
 #endif /* !QEMU_HW_ACPI_H */
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 5b4eef5..ce86ee3 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -55,7 +55,7 @@ typedef struct PIIX4PMState {
     PCIDevice dev;
     IORange ioport;
     ACPIPM1EVT pm1a;
-    uint16_t pmcntrl;
+    ACPIPM1CNT pm1_cnt;
 
     APMState apm;
 
@@ -65,7 +65,6 @@ typedef struct PIIX4PMState {
     uint32_t smb_io_base;
 
     qemu_irq irq;
-    qemu_irq cmos_s3;
     qemu_irq smi_irq;
     int kvm_enabled;
 
@@ -124,30 +123,7 @@ static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
         pm_update_sci(s);
         break;
     case 0x04:
-        {
-            int sus_typ;
-            s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
-            if (val & ACPI_BITMASK_SLEEP_ENABLE) {
-                /* change suspend type */
-                sus_typ = (val >> 10) & 7;
-                switch(sus_typ) {
-                case 0: /* soft power off */
-                    qemu_system_shutdown_request();
-                    break;
-                case 1:
-                    /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
-                       Pretend that resume was caused by power button */
-                    s->pm1a.sts |= (ACPI_BITMASK_WAKE_STATUS |
-                                    ACPI_BITMASK_POWER_BUTTON_STATUS);
-                    qemu_system_reset_request();
-                    if (s->cmos_s3) {
-                        qemu_irq_raise(s->cmos_s3);
-                    }
-                default:
-                    break;
-                }
-            }
-        }
+        acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
         break;
     default:
         break;
@@ -169,7 +145,7 @@ static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
         val = s->pm1a.en;
         break;
     case 0x04:
-        val = s->pmcntrl;
+        val = s->pm1_cnt.cnt;
         break;
     case 0x08:
         val = acpi_pm_tmr_get(&s->tmr);
@@ -192,11 +168,7 @@ static void apm_ctrl_changed(uint32_t val, void *arg)
     PIIX4PMState *s = arg;
 
     /* ACPI specs 3.0, 4.7.2.5 */
-    if (val == ACPI_ENABLE) {
-        s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
-    } else if (val == ACPI_DISABLE) {
-        s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
-    }
+    acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
 
     if (s->dev.config[0x5b] & (1 << 1)) {
         if (s->smi_irq) {
@@ -275,7 +247,7 @@ static const VMStateDescription vmstate_acpi = {
         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
         VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
         VMSTATE_UINT16(pm1a.en, PIIX4PMState),
-        VMSTATE_UINT16(pmcntrl, PIIX4PMState),
+        VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
         VMSTATE_TIMER(tmr.timer, PIIX4PMState),
         VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
@@ -395,7 +367,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 
     s = DO_UPCAST(PIIX4PMState, dev, dev);
     s->irq = sci_irq;
-    s->cmos_s3 = cmos_s3;
+    acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
     s->smi_irq = smi_irq;
     s->kvm_enabled = kvm_enabled;
 
-- 
1.7.1.1

[Qemu-devel] [PATCH 24/26] acpi, acpi_piix: factor out GPE logic

[Isaku Yamahata]

factor out ACPI GPE logic. Later it will be used by ICH9 ACPI.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/acpi.c       |   66 ++++++++++++++++++++++++++++++++++++++
 hw/acpi.h       |   17 ++++++++++
 hw/acpi_piix4.c |   95 ++++++++++++++----------------------------------------
 3 files changed, 108 insertions(+), 70 deletions(-)

diff --git a/hw/acpi.c b/hw/acpi.c
index 24c878a..315ea25 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -348,3 +348,69 @@ void acpi_pm1_cnt_reset(ACPIPM1CNT *pm1_cnt)
         qemu_irq_lower(pm1_cnt->cmos_s3);
     }
 }
+
+/* ACPI GPE */
+void acpi_gpe_init(ACPIGPE *gpe, uint8_t len)
+{
+    gpe->len = len;
+    gpe->sts = qemu_mallocz(len / 2);
+    gpe->en = qemu_mallocz(len / 2);
+}
+
+void acpi_gpe_blk(ACPIGPE *gpe, uint32_t blk)
+{
+    gpe->blk = blk;
+}
+
+void acpi_gpe_reset(ACPIGPE *gpe)
+{
+    memset(gpe->sts, 0, gpe->len / 2);
+    memset(gpe->en, 0, gpe->len / 2);
+}
+
+static uint8_t *acpi_gpe_ioport_get_ptr(ACPIGPE *gpe, uint32_t addr)
+{
+    uint8_t *cur = NULL;
+
+    if (addr < gpe->len / 2) {
+        cur = gpe->sts + addr;
+    } else if (addr < gpe->len) {
+        cur = gpe->en + addr;
+    } else {
+        abort();
+    }
+
+    return cur;
+}
+
+void acpi_gpe_ioport_writeb(ACPIGPE *gpe, uint32_t addr, uint32_t val)
+{
+    uint8_t *cur;
+
+    addr -= gpe->blk;
+    cur = acpi_gpe_ioport_get_ptr(gpe, addr);
+    if (addr < gpe->len / 2) {
+        /* GPE_STS */
+        *cur = (*cur) & ~val;
+    } else if (addr < gpe->len) {
+        /* GPE_EN */
+        *cur = val;
+    } else {
+        abort();
+    }
+}
+
+uint32_t acpi_gpe_ioport_readb(ACPIGPE *gpe, uint32_t addr)
+{
+    uint8_t *cur;
+    uint32_t val;
+
+    addr -= gpe->blk;
+    cur = acpi_gpe_ioport_get_ptr(gpe, addr);
+    val = 0;
+    if (cur != NULL) {
+        val = *cur;
+    }
+
+    return val;
+}
diff --git a/hw/acpi.h b/hw/acpi.h
index ab70c00..0c666a8 100644
--- a/hw/acpi.h
+++ b/hw/acpi.h
@@ -126,4 +126,21 @@ void acpi_pm1_cnt_update(ACPIPM1CNT *pm1_cnt,
                          bool sci_enable, bool sci_disable);
 void acpi_pm1_cnt_reset(ACPIPM1CNT *pm1_cnt);
 
+/* GPE0 */
+struct ACPIGPE {
+    uint32_t blk;
+    uint8_t len;
+
+    uint8_t *sts;
+    uint8_t *en;
+};
+typedef struct ACPIGPE ACPIGPE;
+
+void acpi_gpe_init(ACPIGPE *gpe, uint8_t len);
+void acpi_gpe_blk(ACPIGPE *gpe, uint32_t blk);
+void acpi_gpe_reset(ACPIGPE *gpe);
+
+void acpi_gpe_ioport_writeb(ACPIGPE *gpe, uint32_t addr, uint32_t val);
+uint32_t acpi_gpe_ioport_readb(ACPIGPE *gpe, uint32_t addr);
+
 #endif /* !QEMU_HW_ACPI_H */
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index ce86ee3..a60eb57 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -35,17 +35,13 @@
 #define ACPI_DBG_IO_ADDR  0xb044
 
 #define GPE_BASE 0xafe0
+#define GPE_LEN 4
 #define PCI_BASE 0xae00
 #define PCI_EJ_BASE 0xae08
 #define PCI_RMV_BASE 0xae0c
 
 #define PIIX4_PCI_HOTPLUG_STATUS 2
 
-struct gpe_regs {
-    uint16_t sts; /* status */
-    uint16_t en;  /* enabled */
-};
-
 struct pci_status {
     uint32_t up;
     uint32_t down;
@@ -69,7 +65,7 @@ typedef struct PIIX4PMState {
     int kvm_enabled;
 
     /* for pci hotplug */
-    struct gpe_regs gpe;
+    ACPIGPE gpe;
     struct pci_status pci0_status;
     uint32_t pci0_hotplug_enable;
 } PIIX4PMState;
@@ -89,7 +85,7 @@ static void pm_update_sci(PIIX4PMState *s)
                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
-        (((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
+        (((s->gpe.sts[0] & s->gpe.en[0]) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
 
     qemu_set_irq(s->irq, sci_level);
     /* schedule a timer interruption if needed */
@@ -213,14 +209,25 @@ static int vmstate_acpi_post_load(void *opaque, int version_id)
     return 0;
 }
 
+#define VMSTATE_GPE_ARRAY(_field, _state)                            \
+ {                                                                   \
+     .name       = (stringify(_field)),                              \
+     .version_id = 0,                                                \
+     .num        = GPE_LEN,                                          \
+     .info       = &vmstate_info_uint16,                             \
+     .size       = sizeof(uint16_t),                                 \
+     .flags      = VMS_ARRAY | VMS_POINTER,                          \
+     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
+ }
+
 static const VMStateDescription vmstate_gpe = {
     .name = "gpe",
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField []) {
-        VMSTATE_UINT16(sts, struct gpe_regs),
-        VMSTATE_UINT16(en, struct gpe_regs),
+        VMSTATE_GPE_ARRAY(sts, ACPIGPE),
+        VMSTATE_GPE_ARRAY(en, ACPIGPE),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -251,7 +258,7 @@ static const VMStateDescription vmstate_acpi = {
         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
         VMSTATE_TIMER(tmr.timer, PIIX4PMState),
         VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
-        VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
+        VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
                        struct pci_status),
         VMSTATE_END_OF_LIST()
@@ -345,6 +352,7 @@ static int piix4_pm_initfn(PCIDevice *dev)
     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 
     acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
+    acpi_gpe_init(&s->gpe, GPE_LEN);
 
     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 
@@ -398,74 +406,20 @@ static void piix4_pm_register(void)
 
 device_init(piix4_pm_register);
 
-static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
-{
-    if (addr & 1)
-        return (val >> 8) & 0xff;
-    return val & 0xff;
-}
-
 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 {
-    uint32_t val = 0;
     PIIX4PMState *s = opaque;
-    struct gpe_regs *g = &s->gpe;
-
-    switch (addr) {
-        case GPE_BASE:
-        case GPE_BASE + 1:
-            val = gpe_read_val(g->sts, addr);
-            break;
-        case GPE_BASE + 2:
-        case GPE_BASE + 3:
-            val = gpe_read_val(g->en, addr);
-            break;
-        default:
-            break;
-    }
+    uint32_t val = acpi_gpe_ioport_readb(&s->gpe, addr);
 
     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
     return val;
 }
 
-static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
-{
-    if (addr & 1)
-        *cur = (*cur & 0xff) | (val << 8);
-    else
-        *cur = (*cur & 0xff00) | (val & 0xff);
-}
-
-static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
-{
-    uint16_t x1, x0 = val & 0xff;
-    int shift = (addr & 1) ? 8 : 0;
-
-    x1 = (*cur >> shift) & 0xff;
-
-    x1 = x1 & ~x0;
-
-    *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
-}
-
 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 {
     PIIX4PMState *s = opaque;
-    struct gpe_regs *g = &s->gpe;
-
-    switch (addr) {
-        case GPE_BASE:
-        case GPE_BASE + 1:
-            gpe_reset_val(&g->sts, addr, val);
-            break;
-        case GPE_BASE + 2:
-        case GPE_BASE + 3:
-            gpe_write_val(&g->en, addr, val);
-            break;
-        default:
-            break;
-    }
 
+    acpi_gpe_ioport_writeb(&s->gpe, addr, val);
     pm_update_sci(s);
 
     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
@@ -548,8 +502,9 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 {
     struct pci_status *pci0_status = &s->pci0_status;
 
-    register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
-    register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, s);
+    register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
+    register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
+    acpi_gpe_blk(&s->gpe, GPE_BASE);
 
     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
@@ -565,13 +520,13 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 
 static void enable_device(PIIX4PMState *s, int slot)
 {
-    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
+    s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
     s->pci0_status.up |= (1 << slot);
 }
 
 static void disable_device(PIIX4PMState *s, int slot)
 {
-    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
+    s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
     s->pci0_status.down |= (1 << slot);
 }
 
-- 
1.7.1.1

[Qemu-devel] [PATCH 25/26] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS

[Isaku Yamahata]

Adds pci id constants which will be used by q35.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pci_ids.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 9daea23..a597a7b 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -30,6 +30,7 @@
 #define PCI_CLASS_SYSTEM_OTHER           0x0880
 
 #define PCI_CLASS_SERIAL_USB             0x0c03
+#define PCI_CLASS_SERIAL_SMBUS           0x0c05
 
 #define PCI_CLASS_BRIDGE_HOST            0x0600
 #define PCI_CLASS_BRIDGE_ISA             0x0601
@@ -101,6 +102,7 @@
 #define PCI_DEVICE_ID_INTEL_82441        0x1237
 #define PCI_DEVICE_ID_INTEL_82801AA_5    0x2415
 #define PCI_DEVICE_ID_INTEL_ESB_9        0x25ab
+#define PCI_DEVICE_ID_INTEL_82801BA_11   0x244e
 #define PCI_DEVICE_ID_INTEL_82371SB_0    0x7000
 #define PCI_DEVICE_ID_INTEL_82371SB_1    0x7010
 #define PCI_DEVICE_ID_INTEL_82371SB_2    0x7020
-- 
1.7.1.1

[Qemu-devel] [PATCH 26/26] pc q35 based chipset emulator

[Isaku Yamahata]

pc q35 based chipset emulator to support pci express natively.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 Makefile.target |    1 +
 hw/acpi_ich9.c  |  314 ++++++++++++++++++++
 hw/acpi_ich9.h  |   53 ++++
 hw/pc_q35.c     |  359 +++++++++++++++++++++++
 hw/pci_ids.h    |   13 +
 hw/q35.c        |  877 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/q35.h        |  271 +++++++++++++++++
 hw/q35_smbus.c  |  154 ++++++++++
 8 files changed, 2042 insertions(+), 0 deletions(-)
 create mode 100644 hw/acpi_ich9.c
 create mode 100644 hw/acpi_ich9.h
 create mode 100644 hw/pc_q35.c
 create mode 100644 hw/q35.c
 create mode 100644 hw/q35.h
 create mode 100644 hw/q35_smbus.c

diff --git a/Makefile.target b/Makefile.target
index d57d250..28da59f 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -219,6 +219,7 @@ obj-i386-y += vmport.o
 obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o
 obj-i386-y += debugcon.o multiboot.o
 obj-i386-y += pc_piix.o kvmclock.o
+obj-i386-y += pc_q35.o q35.o q35_smbus.o acpi_ich9.o
 obj-i386-$(CONFIG_SPICE) += qxl.o qxl-logger.o qxl-render.o
 
 # shared objects
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
new file mode 100644
index 0000000..28db57b
--- /dev/null
+++ b/hw/acpi_ich9.c
@@ -0,0 +1,314 @@
+/*
+ * ACPI implementation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+/*
+ *  Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ *                     VA Linux Systems Japan K.K.
+ *
+ *  This is based on acpi.c.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "pci.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "acpi.h"
+
+#include "q35.h"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define ICH9_DEBUG(fmt, ...)    do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
+#else
+#define ICH9_DEBUG(fmt, ...)    do { } while (0)
+#endif
+
+static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
+                                     uint32_t val);
+static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
+
+static void pm_update_sci(ICH9_LPCPmRegs *pm)
+{
+    int sci_level, pm1a_sts;
+
+    pm1a_sts = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+
+    sci_level = (((pm1a_sts & pm->pm1a.en) &
+                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
+                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
+                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
+                   ACPI_BITMASK_TIMER_ENABLE)) != 0);
+    qemu_set_irq(pm->irq, sci_level);
+
+    /* schedule a timer interruption if needed */
+    acpi_pm_tmr_update(&pm->tmr,
+                       (pm->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
+                       !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
+}
+
+static void ich9_pm_update_sci_fn(ACPIPMTimer *tmr)
+{
+    ICH9_LPCPmRegs *pm = container_of(tmr, ICH9_LPCPmRegs, tmr);
+    pm_update_sci(pm);
+}
+
+static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+    ICH9_LPCPmRegs *pm = opaque;
+
+    switch (addr & ICH9_PMIO_MASK) {
+    case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
+        acpi_gpe_ioport_writeb(&pm->gpe0, addr, val);
+        break;
+    default:
+        break;
+    }
+
+    ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+}
+
+static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
+{
+    ICH9_LPCPmRegs *pm = opaque;
+    uint32_t val = 0;
+
+    switch(addr & ICH9_PMIO_MASK) {
+    case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
+        val = acpi_gpe_ioport_readb(&pm->gpe0, addr);
+        break;
+    default:
+        val = 0;
+        break;
+    }
+    ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+    return val;
+}
+
+static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
+{
+    ICH9_LPCPmRegs *pm = opaque;
+
+    switch(addr & ICH9_PMIO_MASK) {
+    case ICH9_PMIO_PM1_STS:
+        acpi_pm1_evt_write_sts(&pm->pm1a, &pm->tmr, val);
+        pm_update_sci(pm);
+        break;
+    case ICH9_PMIO_PM1_EN:
+        pm->pm1a.en = val;
+        pm_update_sci(pm);
+        break;
+    case ICH9_PMIO_PM1_CNT:
+        acpi_pm1_cnt_write(&pm->pm1a, &pm->pm1_cnt, val);
+        break;
+    default:
+        pm_ioport_write_fallback(opaque, addr, 2, val);
+        break;
+    }
+    ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+}
+
+static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
+{
+    ICH9_LPCPmRegs *pm = opaque;
+    uint32_t val;
+
+    switch(addr & ICH9_PMIO_MASK) {
+    case ICH9_PMIO_PM1_STS:
+        val = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+        break;
+    case ICH9_PMIO_PM1_EN:
+        val = pm->pm1a.en;
+        break;
+    case ICH9_PMIO_PM1_CNT:
+        val = pm->pm1_cnt.cnt;
+        break;
+    default:
+        val = pm_ioport_read_fallback(opaque, addr, 2);
+        break;
+    }
+    ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+    return val;
+}
+
+static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
+{
+    ICH9_LPCPmRegs *pm = opaque;
+
+    switch(addr & ICH9_PMIO_MASK) {
+    case ICH9_PMIO_SMI_EN:
+        pm->smi_en = val;
+        break;
+    default:
+        pm_ioport_write_fallback(opaque, addr, 4, val);
+        break;
+    }
+    ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
+}
+
+static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
+{
+    ICH9_LPCPmRegs *pm = opaque;
+    uint32_t val;
+
+    switch(addr & ICH9_PMIO_MASK) {
+    case ICH9_PMIO_PM1_TMR:
+        val = acpi_pm_tmr_get(&pm->tmr);
+        break;
+    case ICH9_PMIO_SMI_EN:
+        val = pm->smi_en;
+        break;
+
+    default:
+        val = pm_ioport_read_fallback(opaque, addr, 4);
+        break;
+    }
+    ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
+    return val;
+}
+
+static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
+                                     uint32_t val)
+{
+    int subsize = (len == 4)? 2: 1;
+    IOPortWriteFunc *ioport_write =
+        (subsize == 2)? pm_ioport_writew: pm_ioport_writeb;
+
+    int i;
+
+    for (i = 0; i < len; i += subsize) {
+        ioport_write(opaque, addr, val);
+        val >>= 8 * subsize;
+    }
+}
+
+static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
+{
+    int subsize = (len == 4)? 2: 1;
+    IOPortReadFunc *ioport_read =
+        (subsize == 2)? pm_ioport_readw: pm_ioport_readb;
+
+    uint32_t val;
+    int i;
+
+    val = 0;
+    for (i = 0; i < len; i += subsize) {
+        val <<= 8 * subsize;
+        val |= ioport_read(opaque, addr);
+    }
+
+    return val;
+}
+
+void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base)
+{
+    ICH9_DEBUG("to 0x%x\n", pm_io_base);
+
+    assert((pm_io_base & ICH9_PMIO_MASK) == 0);
+
+    if (pm->pm_io_base != 0) {
+        isa_unassign_ioport(pm->pm_io_base, ICH9_PMIO_SIZE);
+    }
+
+    /* don't map at 0 */
+    if (pm_io_base == 0) {
+        return;
+    }
+
+    register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_writeb, pm);
+    register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_readb, pm);
+    register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_writew, pm);
+    register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_readw, pm);
+    register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_writel, pm);
+    register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
+
+    pm->pm_io_base = pm_io_base;
+    acpi_gpe_blk(&pm->gpe0, pm_io_base + ICH9_PMIO_GPE0_STS);
+}
+
+static int ich9_pm_post_load(void *opaque, int version_id)
+{
+    ICH9_LPCPmRegs *pm = opaque;
+    uint32_t pm_io_base = pm->pm_io_base;
+    pm->pm_io_base = 0;
+    ich9_pm_iospace_update(pm, pm_io_base);
+    return 0;
+}
+
+#define VMSTATE_GPE_ARRAY(_field, _state)                            \
+ {                                                                   \
+     .name       = (stringify(_field)),                              \
+     .version_id = 0,                                                \
+     .num        = ICH9_PMIO_GPE0_LEN,                               \
+     .info       = &vmstate_info_uint8,                              \
+     .size       = sizeof(uint8_t),                                  \
+     .flags      = VMS_ARRAY | VMS_POINTER,                          \
+     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
+ }
+
+const VMStateDescription vmstate_ich9_pm = {
+    .name = "ich9_pm",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .post_load = ich9_pm_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT16(pm1a.sts, ICH9_LPCPmRegs),
+        VMSTATE_UINT16(pm1a.en, ICH9_LPCPmRegs),
+        VMSTATE_UINT16(pm1_cnt.cnt, ICH9_LPCPmRegs),
+        VMSTATE_TIMER(tmr.timer, ICH9_LPCPmRegs),
+        VMSTATE_INT64(tmr.overflow_time, ICH9_LPCPmRegs),
+        VMSTATE_GPE_ARRAY(gpe0.sts, ICH9_LPCPmRegs),
+        VMSTATE_GPE_ARRAY(gpe0.en, ICH9_LPCPmRegs),
+        VMSTATE_UINT32(smi_en, ICH9_LPCPmRegs),
+        VMSTATE_UINT32(smi_sts, ICH9_LPCPmRegs),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void pm_reset(void *opaque)
+{
+    ICH9_LPCPmRegs *pm = opaque;
+    ich9_pm_iospace_update(pm, 0);
+
+    acpi_pm1_evt_reset(&pm->pm1a);
+    acpi_pm1_cnt_reset(&pm->pm1_cnt);
+    acpi_pm_tmr_reset(&pm->tmr);
+    acpi_gpe_reset(&pm->gpe0);
+
+    pm_update_sci(pm);
+}
+
+static void pm_powerdown(void *opaque, int irq, int power_failing)
+{
+    ICH9_LPCPmRegs *pm = opaque;
+    ACPIPM1EVT *pm1a = pm? &pm->pm1a: NULL;
+    ACPIPMTimer *tmr = pm? &pm->tmr: NULL;
+
+    acpi_pm1_evt_power_down(pm1a, tmr);
+}
+
+void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
+{
+    acpi_pm_tmr_init(&pm->tmr, ich9_pm_update_sci_fn);
+    acpi_pm1_cnt_init(&pm->pm1_cnt, cmos_s3);
+    acpi_gpe_init(&pm->gpe0, ICH9_PMIO_GPE0_LEN);
+
+    pm->irq = sci_irq;
+    qemu_register_reset(pm_reset, pm);
+    qemu_system_powerdown = *qemu_allocate_irqs(pm_powerdown, pm, 1);
+}
diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
new file mode 100644
index 0000000..f55c0e9
--- /dev/null
+++ b/hw/acpi_ich9.h
@@ -0,0 +1,53 @@
+/*
+ * QEMU GMCH/ICH9 LPC PM Emulation
+ *
+ *  Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ *                     VA Linux Systems Japan K.K.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#ifndef HW_ACPI_ICH9_H
+#define HW_ACPI_ICH9_H
+
+#include "acpi.h"
+
+typedef struct ICH9_LPCPmRegs {
+    ACPIPM1EVT pm1a;
+
+    /*
+     * In ich9 spec says that pm1_cnt register is 32bit width and
+     * that the upper 16bits are reserved and unused.
+     * PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
+     */
+    ACPIPM1CNT pm1_cnt;
+
+    ACPIPMTimer tmr;
+
+    ACPIGPE gpe0;
+
+    uint32_t smi_en;
+    uint32_t smi_sts;
+
+    qemu_irq irq;      /* SCI */
+
+    uint32_t pm_io_base;
+} ICH9_LPCPmRegs;
+
+void ich9_pm_init(ICH9_LPCPmRegs *pm,
+                  qemu_irq sci_irq, qemu_irq cmos_s3_resume);
+void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base);
+extern const VMStateDescription vmstate_ich9_pm;
+
+#endif /* HW_ACPI_ICH9_H */
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
new file mode 100644
index 0000000..84dc221
--- /dev/null
+++ b/hw/pc_q35.c
@@ -0,0 +1,359 @@
+/*
+ * QEMU PC System Emulator
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ *  Q35 chipset based pc system emulator
+ *
+ *  Copyright (c) 2009, 2010
+ *                     Isaku Yamahata <yamahata at valinux co jp>
+ *                     VA Linux Systems Japan K.K.
+ *
+ *  This is based on pc.c, but heavily modified.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+#include "hw.h"
+#include "arch_init.h"
+#include "pc.h"
+#include "fdc.h"
+#include "pci.h"
+#include "pci_bridge.h"
+#include "pci_p2pbr.h"
+#include "ioh3420.h"
+#include "xio3130_upstream.h"
+#include "xio3130_downstream.h"
+#include "block.h"
+#include "blockdev.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "net.h"
+#include "smbus.h"
+#include "boards.h"
+#include "monitor.h"
+#include "fw_cfg.h"
+#include "hpet_emul.h"
+#include "watchdog.h"
+#include "smbios.h"
+#include "ide.h"
+#include "usb-uhci.h"
+
+#include "q35.h"
+
+/* ICH9 AHCI has 6 ports */
+#define MAX_SATA_PORTS     6
+
+#define I21154_REV            0x05
+#define I21154_PI             0x00
+
+static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
+                              bool multifunction)
+{
+    const PCIP2PBridgeInit init = {
+        .bus = bus,
+        .devfn = devfn,
+        .multifunction = multifunction,
+
+        .bus_name = bus_name,
+        .map_irq = pci_swizzle_map_irq_fn,
+    };
+    const PCIP2PBridgeProp prop = {
+        .vendor_id = PCI_VENDOR_ID_DEC,
+        .device_id = PCI_DEVICE_ID_DEC_21154,
+        .revision_id = I21154_REV,
+        .prog_interface = I21154_PI,
+    };
+    return pci_p2pbr_create_simple(&init, &prop);
+}
+
+static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
+{
+    uint8_t dev;
+    uint8_t sec_bus;
+    uint8_t port = 0;
+    uint8_t chassis = 0;
+    uint16_t slot = 0;
+    uint8_t upstream_port;
+    PCIESlot *s;
+    uint8_t fn;
+    PCIESlot *root_port;
+    PCIBus *root_port_bus;
+    char buf[16];
+
+    /* PCI to PCI bridge b6:d[29 - 31]:f0, 6:[1c - 1f].0 with subordinate bus
+       of 7 - 9 on b0:d30:f0, 0.1e.0 = bus */
+#define Q35_P2P_BRDIGE_DEV_BASE         28
+#define Q35_P2P_BRDIGE_DEV_MAX          32
+#define Q35_P2P_BRDIGE_SUBBUS_BASE      (ICH9_D2P_SECONDARY_DEFAULT + 1)
+    for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev < Q35_P2P_BRDIGE_DEV_MAX; dev++) {
+        PCIBridge *br;
+        sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
+
+        snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
+        br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
+    }
+
+    /* PCIe root port b0:d1:f0 in GMCH.
+     * Actually it's vid/did = 0x8086:0x29c1, but we substitute ioh for it.
+     */
+    sec_bus = 32;
+    snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+    s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
+                     buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+
+
+    /* more slots. ICH9 doesn't have those, but many slots are wanted. */
+//#define Q35_MANY_SLOTS
+#undef Q35_MANY_SLOTS
+
+#ifdef Q35_MANY_SLOTS
+#define Q35_NR_ROOTPORT         6
+#define Q35_NR_UPSTREAM         8
+#define Q35_NR_DOWNSTREAM       16
+#else
+#define Q35_NR_ROOTPORT         1
+#define Q35_NR_UPSTREAM         1
+#define Q35_NR_DOWNSTREAM       1
+#endif
+
+    /* PCIe root port b0:d23:f[0-5], 0.17.[0-5] */
+    for (fn = 0; fn < Q35_NR_ROOTPORT; fn++) {
+        sec_bus++;
+        port++;
+        slot++;
+
+        snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+        s = ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
+                         buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+    }
+
+    /* PCIe root port b0:d24:f0 */
+    sec_bus++;
+    port++;
+    slot++;
+    snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+    root_port = ioh3420_init(host_bus, PCI_DEVFN(24, 0), true,
+                             buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+    root_port_bus = pci_bridge_get_sec_bus(&root_port->port.br);
+
+    /* 8 * 16 = 128 slots */
+    upstream_port = 0;
+    for (fn = 0; fn < Q35_NR_UPSTREAM; fn++) {
+        PCIEPort *upstream;
+        PCIBus *upstream_bus;
+        uint16_t downstream_port;
+
+        uint8_t ds_dev_max;
+        uint8_t ds_dev;
+        uint8_t ds_fn_max;
+        uint8_t ds_fn;
+
+        /* PCIe upstream port d0:f[0-7] */
+        sec_bus++;
+        snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+        upstream = xio3130_upstream_init(root_port_bus, PCI_DEVFN(0, fn),
+                                         true, buf, pci_swizzle_map_irq_fn,
+                                         upstream_port);
+
+        upstream_bus = pci_bridge_get_sec_bus(&upstream->br);
+        upstream_port++;
+
+        /* PCIe downstream port */
+        downstream_port = 0;
+        ds_fn_max = MIN(Q35_NR_DOWNSTREAM / PCI_SLOT_MAX, PCI_FUNC_MAX);
+        ds_dev_max = MIN(Q35_NR_DOWNSTREAM / (ds_fn_max + 1), PCI_SLOT_MAX);
+
+        for (ds_dev = 0; ds_dev <= ds_dev_max &&
+                 downstream_port < Q35_NR_DOWNSTREAM; ds_dev++) {
+            for (ds_fn = 0; ds_fn <= ds_fn_max &&
+                     downstream_port < Q35_NR_DOWNSTREAM; ds_fn++) {
+                sec_bus++;
+                slot++;
+                snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+
+                xio3130_downstream_init(upstream_bus, PCI_DEVFN(ds_dev, ds_fn),
+                                        true, buf, pci_swizzle_map_irq_fn,
+                                        downstream_port, chassis, slot);
+                downstream_port++;
+            }
+        }
+    }
+
+    /* PCIe root port b0:d28:f[0-6] in ICH9.
+     * Actually it's vid/did = 0x8086:0x294[02468A], but we substitute ioh
+     * for them.
+     */
+    for (fn = 0; fn < ICH9_PCIE_FUNC_MAX; fn++) {
+        sec_bus++;
+        port++;
+        slot++;
+
+        snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+        s = ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
+                         buf, pci_swizzle_map_irq_fn,
+                         port, chassis, slot);
+    }
+}
+
+static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
+                              DeviceState **gmch_host_p,
+                              PCIBus **host_bus_p, PCIBus **pci_bus_p,
+                              PCIDevice **lpc_p)
+{
+    DeviceState *gmch_host;
+    PCIBus *host_bus;
+    PCIBus *pci_bus;
+
+    PCIDevice *gmch_state;
+    PCIDevice *lpc;
+
+    /* create pci host bus */
+    host_bus = gmch_host_init(&gmch_host, isa_irq, isa_irq_state->ioapic);
+    gmch_state = gmch_init(gmch_host, host_bus);
+
+    /* create conventional pci bus: pcie2pci bridge */
+    pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
+                                                  ICH9_D2P_BRIDGE_FUNC),
+                              ICH9_D2P_SECONDARY_DEFAULT);
+
+    /* create child pci/pcie buses */
+    pc_q35_bridge_init(host_bus, pci_bus);
+
+    /* create ISA bus */
+    lpc = gmch_lpc_init(gmch_host, host_bus);
+
+    *gmch_host_p = gmch_host;
+    *host_bus_p = host_bus;
+    *pci_bus_p = pci_bus;
+    *lpc_p = lpc;
+}
+
+static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
+                             DeviceState *gmch_host,
+                             PCIBus *host_bus, PCIBus *pci_bus,
+                             PCIDevice *lpc)
+{
+    qemu_irq *cmos_s3;
+    PCIDevice *ahci;
+    DriveInfo *hd[MAX_SATA_PORTS * MAX_IDE_DEVS];
+
+    /* connect pm stuff to lpc */
+    cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
+    ich9_lpc_pm_init(gmch_host, lpc, *cmos_s3);
+
+    /* ahci and SATA device */
+    ide_drive_get(hd, MAX_SATA_PORTS);
+    ahci = pci_create_simple_multifunction(host_bus,
+                                           PCI_DEVFN(ICH9_SATA1_DEV,
+                                                     ICH9_SATA1_FUNC),
+                                           true, "ich9-ahci");
+    pci_ahci_ide_create_devs(ahci, hd);
+    idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
+    idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
+
+    if (usb_enabled) {
+        /* Should we create 6 UHCI according to ich9 spec? */
+        pci_create_simple_multifunction(
+            host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
+            true, "ich9-usb-uhci1");
+        /* XXX: EHCI */
+    }
+
+    /* TODO: Populate SPD eeprom data.  */
+    smbus_eeprom_init(ich9_smb_init(host_bus,
+                                    PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
+                                    0xb100),
+                      8, NULL, 0);
+}
+
+/* PC hardware initialisation */
+static void pc_q35_init(ram_addr_t ram_size,
+                        const char *boot_device,
+                        const char *kernel_filename,
+                        const char *kernel_cmdline,
+                        const char *initrd_filename,
+                        const char *cpu_model)
+{
+    ram_addr_t below_4g_mem_size, above_4g_mem_size;
+    DeviceState *gmch_host;
+    PCIBus *host_bus;
+    PCIBus *pci_bus;
+    PCIDevice *lpc;
+    qemu_irq *isa_irq;
+    IsaIrqState *isa_irq_state;
+    BusState *idebus[MAX_SATA_PORTS];
+    ISADevice *rtc_state;
+
+    pc_cpus_init(cpu_model);
+
+    /* allocate ram and load rom/bios */
+    pc_memory_init(ram_size, kernel_filename, kernel_cmdline, initrd_filename,
+                   &below_4g_mem_size, &above_4g_mem_size);
+
+    /* irq lines */
+    isa_irq = pc_isa_irq(&isa_irq_state);
+    ioapic_init(isa_irq_state);
+
+    pc_q35_init_early(isa_irq, isa_irq_state,
+                      &gmch_host, &host_bus, &pci_bus, &lpc);
+    isa_bus_irqs(isa_irq);
+    pc_register_ferr_irq(isa_get_irq(13));
+
+    /* init basic PC hardware */
+    pc_basic_device_init(isa_irq, &rtc_state);
+
+    pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, pci_bus, lpc);
+
+    pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
+                 idebus[0], idebus[1], rtc_state);
+
+    /* the rest devices to which pci devfn is automatically assigned */
+    pc_vga_init(host_bus);
+    audio_init(isa_irq, pci_bus);
+    pc_nic_init(pci_bus);
+    pc_pci_device_init(pci_bus);
+}
+
+static QEMUMachine pc_q35_machine = {
+    .name = "pc_q35",
+    .desc = "Q35 chipset PC",
+    .init = pc_q35_init,
+    .max_cpus = 255,
+};
+
+static void pc_q35_machine_init(void)
+{
+    qemu_register_machine(&pc_q35_machine);
+}
+
+machine_init(pc_q35_machine_init);
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index a597a7b..21cac58 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -35,6 +35,7 @@
 #define PCI_CLASS_BRIDGE_HOST            0x0600
 #define PCI_CLASS_BRIDGE_ISA             0x0601
 #define PCI_CLASS_BRIDGE_PCI             0x0604
+#define  PCI_CLASS_BRDIGE_PCI_INF_SUB    0x01
 #define PCI_CLASS_BRIDGE_OTHER           0x0680
 
 #define PCI_CLASS_COMMUNICATION_OTHER    0x0780
@@ -111,4 +112,16 @@
 #define PCI_DEVICE_ID_INTEL_82371AB_2    0x7112
 #define PCI_DEVICE_ID_INTEL_82371AB_3    0x7113
 
+#define PCI_DEVICE_ID_INTEL_ICH9_0       0x2910
+#define PCI_DEVICE_ID_INTEL_ICH9_1       0x2917
+#define PCI_DEVICE_ID_INTEL_ICH9_2       0x2912
+#define PCI_DEVICE_ID_INTEL_ICH9_3       0x2913
+#define PCI_DEVICE_ID_INTEL_ICH9_4       0x2914
+#define PCI_DEVICE_ID_INTEL_ICH9_5       0x2919
+#define PCI_DEVICE_ID_INTEL_ICH9_6       0x2930
+#define PCI_DEVICE_ID_INTEL_ICH9_7       0x2916
+#define PCI_DEVICE_ID_INTEL_ICH9_8       0x2918
+
 #define PCI_DEVICE_ID_INTEL_ICH9_UCHI1   0x2934
+
+#define PCI_DEVICE_ID_INTEL_Q35_MCH      0x29c0
diff --git a/hw/q35.c b/hw/q35.c
new file mode 100644
index 0000000..0636aa4
--- /dev/null
+++ b/hw/q35.c
@@ -0,0 +1,877 @@
+/*
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * QEMU GMCH/ICH9 PCI Bridge Emulation
+ *
+ *  Copyright (c) 2009, 2010, 2011
+ *                Isaku Yamahata <yamahata at valinux co jp>
+ *                VA Linux Systems Japan K.K.
+ *
+ *  This is based on piix_pci.c, but heavily modified.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include "hw.h"
+#include "range.h"
+#include "isa.h"
+#include "sysbus.h"
+#include "pc.h"
+#include "apm.h"
+#include "apic.h"
+#include "pci.h"
+#include "pcie_host.h"
+#include "pci_bridge.h"
+#include "pci_p2pbr.h"
+#include "q35.h"
+#include "acpi.h"
+#include "acpi_ich9.h"
+#include "pam.h"
+
+
+struct ICH9_LPCState;
+
+typedef struct ICH9_LPCIrqState {
+    struct ICH9_LPCState *lpc;
+    qemu_irq *pic;
+    qemu_irq *ioapic;
+} ICH9_LPCIrqState;
+
+typedef struct GMCH_PCIHost {
+    PCIExpressHost      host;
+
+    PCIDevice    *dev;
+    ICH9_LPCIrqState irq_state;
+} GMCH_PCIHost;
+
+typedef struct GMCH_PCIState {
+    PCIDevice   d;
+    /*
+     * GMCH_PCIHost   *gmch_host;
+     * In order to get GMCH_PCIHost
+     *  PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
+     */
+
+    PAM pam;
+} GMCH_PCIState;
+
+typedef struct ICH9_LPCState {
+    /* ICH9 LPC PCI to ISA bridge */
+    PCIDevice d;
+
+    /* (pci device, intx) -> pirq
+     * In real chipset case, the unused slots are never used
+     * as ICH9 supports only D25-D32 irq routing.
+     * On the other hand in qemu case, any slot/function can be populated
+     * via command line option.
+     * So fallback interrupt routing for any devices in any slots is necessary.
+     */
+    uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
+
+    APMState apm;
+    ICH9_LPCPmRegs pm;
+    uint32_t sci_level; /* track sci level */
+
+    /* 10.1 Chipset Configuration registers(Memory Space)
+       which is pointed by RCBA */
+    uint8_t chip_config[ICH9_CC_SIZE];
+    int rbca_index;
+} ICH9_LPCState;
+
+
+/****************************************************************************
+ * GMCH PCI host
+ */
+/* ich9 irq */
+static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx);
+static void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
+static int ich9_lpc_sci_irq(ICH9_LPCState *lpc);
+
+static GMCH_PCIHost *gmch_pcihost_from_qdev(DeviceState *gmch_host_qdev)
+{
+    SysBusDevice *sysdev = sysbus_from_qdev(gmch_host_qdev);
+    PCIHostState *pci = FROM_SYSBUS(PCIHostState, sysdev);
+    PCIExpressHost *pcie = DO_UPCAST(PCIExpressHost, pci, pci);
+    return DO_UPCAST(GMCH_PCIHost, host, pcie);
+}
+
+static int gmch_pcihost_initfn(SysBusDevice *dev)
+{
+    GMCH_PCIHost *s = gmch_pcihost_from_qdev(&dev->qdev);
+
+    pci_host_conf_register_ioport(GMCH_HOST_BRIDGE_CONFIG_ADDR, &s->host.pci);
+    pci_host_data_register_ioport(GMCH_HOST_BRIDGE_CONFIG_DATA, &s->host.pci);
+
+    if (pcie_host_init(&s->host) < 0) {
+        abort();
+    }
+
+    return 0;
+}
+
+static SysBusDeviceInfo gmch_pcihost_info = {
+    .init         = gmch_pcihost_initfn,
+    .qdev.name    = "gmch-pcihost",
+    .qdev.size    = sizeof(GMCH_PCIHost),
+    .qdev.no_user = 1,
+    .qdev.props = (Property[]) {
+        {
+            .name = "MCFG",
+            .info = &qdev_prop_uint64,
+            .offset = offsetof(GMCH_PCIHost, host.base_addr),
+            .defval = (uint64_t[]){ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT },
+        },
+        DEFINE_PROP_END_OF_LIST(),
+    },
+};
+
+/* host bridge */
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+                       qemu_irq *pic, qemu_irq *ioapic)
+{
+    DeviceState *dev;
+    GMCH_PCIHost *s;
+    PCIBus *b;
+
+    dev = qdev_create(NULL, "gmch-pcihost");
+    s = gmch_pcihost_from_qdev(dev);
+    s->irq_state.pic = pic;
+    s->irq_state.ioapic = ioapic;
+
+    b = pci_bus_new(dev, "pcie.0", 0);
+    pci_bus_irqs(b, ich9_lpc_set_irq, ich9_lpc_map_irq, &s->irq_state,
+                 ICH9_LPC_NB_PIRQS);
+    s->host.pci.bus = b;
+    qdev_init_nofail(dev);
+
+    *gmch_hostp = dev;
+    return b;
+}
+
+
+/****************************************************************************
+ * GMCH
+ */
+static GMCH_PCIState *gmch_from_pci(PCIDevice *gmch_pci)
+{
+    return DO_UPCAST(GMCH_PCIState, d, gmch_pci);
+}
+
+/* PCIE MMCFG */
+static void gmch_update_pciexbar(GMCH_PCIState *gs)
+{
+    PCIDevice* pci_dev = &gs->d;
+    BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
+    DeviceState *qdev = bus->parent;
+    GMCH_PCIHost *s = gmch_pcihost_from_qdev(qdev);
+
+    uint64_t pciexbar;
+    int enable;
+    uint64_t addr;
+    uint64_t addr_mask;
+    uint32_t length;
+
+    pciexbar = pci_get_quad(pci_dev->config + GMCH_HOST_BRIDGE_PCIEXBAR);
+    enable = pciexbar & GMCH_HOST_BRIDGE_PCIEXBAREN;
+
+    addr_mask = GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
+    switch (pciexbar & GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
+    case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
+        length = 256 * 1024 * 1024;
+        break;
+    case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
+        length = 128 * 1024 * 1024;
+        addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
+            GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+        break;
+    case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
+        length = 64 * 1024 * 1024;
+        addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+        break;
+    case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
+    default:
+        enable = 0;
+        length = 0;
+        abort();
+        break;
+    }
+    addr = pciexbar & addr_mask;
+
+    pcie_host_mmcfg_update(&s->host, enable, addr, length);
+}
+
+/* PAM */
+static void gmch_update_pam(GMCH_PCIState *gs)
+{
+    int i;
+    for (i = 0; i <= PAM_IDX_MAX; i++) {
+        pam_update(&gs->pam, i, gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i]);
+    }
+}
+
+/* SMRAM */
+static void gmch_update_smram(GMCH_PCIState *gs)
+{
+    smram_update(&gs->pam, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+}
+
+static void gmch_set_smm(int smm, void *arg)
+{
+    GMCH_PCIState *gs = arg;
+    smram_set_smm(&gs->pam, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+}
+
+static void gmch_write_config(PCIDevice *d,
+                              uint32_t address, uint32_t val, int len)
+{
+    GMCH_PCIState *gs = gmch_from_pci(d);
+
+    /* XXX: implement SMRAM.D_LOCK */
+    pci_default_write_config(d, address, val, len);
+
+    if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PAM0,
+                       GMCH_HOST_BRIDGE_PAM_SIZE)) {
+        gmch_update_pam(gs);
+    }
+
+    if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PCIEXBAR,
+                       GMCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
+        gmch_update_pciexbar(gs);
+    }
+
+    if (ranges_overlap(address, len, GMCH_HOST_BRDIGE_SMRAM,
+                       GMCH_HOST_BRDIGE_SMRAM_SIZE)) {
+        gmch_update_smram(gs);
+    }
+}
+
+static void gmch_update(GMCH_PCIState *gs)
+{
+    gmch_update_pciexbar(gs);
+    gmch_update_pam(gs);
+    gmch_update_smram(gs);
+}
+
+static int gmch_post_load(void *opaque, int version_id)
+{
+    GMCH_PCIState *gs = opaque;
+    gmch_update(gs);
+    return 0;
+}
+
+static const VMStateDescription vmstate_gmch = {
+    .name = "gmch",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .post_load = gmch_post_load,
+    .fields = (VMStateField []) {
+        VMSTATE_PCI_DEVICE(d, GMCH_PCIState),
+        VMSTATE_UINT8(pam.smm_enabled, GMCH_PCIState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void gmch_reset(DeviceState *qdev)
+{
+    PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
+    GMCH_PCIState *gs = gmch_from_pci(d);
+
+    pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
+                 GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
+
+    d->config[GMCH_HOST_BRDIGE_SMRAM] = GMCH_HOST_BRIDGE_SMRAM_DEFAULT;
+
+    gmch_update(gs);
+}
+
+static int gmch_initfn(PCIDevice *d)
+{
+    GMCH_PCIState *gs = gmch_from_pci(d);
+
+    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+    pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_Q35_MCH);
+    pci_config_set_revision(d->config, GMCH_HOST_BRIDGE_REVISION_DEFUALT);
+    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
+
+    cpu_smm_register(&gmch_set_smm, gs);
+    pam_init_memory_mappings(&gs->pam);
+
+    return 0;
+}
+
+static PCIDeviceInfo gmch_info = {
+    .qdev.name    = "gmch",
+    .qdev.desc    = "Host bridge",
+    .qdev.size    = sizeof(GMCH_PCIState),
+    .qdev.vmsd    = &vmstate_gmch,
+    .qdev.no_user = 1,
+    .init         = gmch_initfn,
+    .config_write = gmch_write_config,
+    .qdev.reset   = gmch_reset,
+};
+
+/* host bridge */
+PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
+{
+    GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+    PCIDevice *d;
+
+    d = pci_create_simple_multifunction(b, 0, false, "gmch");
+    s->dev = d;
+
+    return d;
+}
+
+/*****************************************************************************/
+/* ICH9 DMI-to-PCI bridge */
+#define I82801ba_SSVID_OFFSET   0x50
+#define I82801ba_SSVID_SVID     0
+#define I82801ba_SSVID_SSID     0
+
+static PCIBridge *i82801ba11_init(PCIBus *bus, int devfn, const char *bus_name,
+                                  bool multifunction)
+{
+    const PCIP2PBridgeInit init = {
+        .bus = bus,
+        .devfn = devfn,
+        .multifunction = multifunction,
+
+        .bus_name = bus_name,
+        .map_irq = pci_swizzle_map_irq_fn,
+    };
+    const PCIP2PBridgeProp prop = {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .device_id = PCI_DEVICE_ID_INTEL_82801BA_11,
+        .revision_id = ICH9_D2P_A2_REVISION,
+        .prog_interface = PCI_CLASS_BRDIGE_PCI_INF_SUB,
+
+        .ssvid_cap = I82801ba_SSVID_OFFSET,
+        .svid = I82801ba_SSVID_SVID,
+        .ssid = I82801ba_SSVID_SSID,
+    };
+    return pci_p2pbr_create_simple(&init, &prop);
+}
+
+PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)
+{
+    PCIBridge *br;
+    char buf[16];
+
+    snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
+    br = i82801ba11_init(bus, devfn, buf, true);
+    if (br == NULL) {
+        return NULL;
+    }
+    return pci_bridge_get_sec_bus(br);
+}
+
+
+/*****************************************************************************/
+/* ICH9 LPC PCI to ISA bridge */
+
+static void ich9_lpc_reset(DeviceState *qdev);
+
+static ICH9_LPCState *ich9_lpc_from_pci(PCIDevice *lpc_pci)
+{
+    return DO_UPCAST(ICH9_LPCState, d, lpc_pci);
+}
+
+/* chipset configuration register
+ * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
+ * are used.
+ * Although it's not pci configuration space, it's little endian as Intel.
+ */
+
+static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
+{
+    int intx;
+    for (intx = 0; intx < PCI_NUM_PINS; intx++) {
+        irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
+    }
+}
+
+static void ich9_cc_update(ICH9_LPCState *lpc)
+{
+    int slot;
+    int reg_offset;
+    int intx;
+
+    /* D{25 - 31}IR, but D30IR is read only to 0. */
+    for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
+        if (slot != 30) {
+            ich9_cc_update_ir(lpc->irr[slot],
+                              lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
+        }
+    }
+
+    /*
+     * D30: DMI2PCI bridge
+     * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge
+     * are connected to pirq lines. Our choice is PIRQ[E-H].
+     * INT[A-D] are connected to PIRQ[E-H]
+     */
+    for (intx = 0; intx < PCI_NUM_PINS; intx++) {
+        lpc->irr[30][intx] = intx + 4;
+    }
+}
+
+static void ich9_cc_init(ICH9_LPCState *lpc)
+{
+    int slot;
+    int intx;
+
+    /* the default irq routing is arbitrary as long as it matches with
+     * acpi irq routing table.
+     * The one that is incompatible with piix_pci(= bochs) one is
+     * intentionally chosen to let the users know that the different
+     * board is used.
+     *
+     * int[A-D] -> pirq[E-F]
+     * avoid pirq A-D because they are used for pci express port
+     */
+    for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
+        for (intx = 0; intx < PCI_NUM_PINS; intx++) {
+            lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
+        }
+    }
+    ich9_cc_update(lpc);
+}
+
+static void ich9_cc_reset(ICH9_LPCState *lpc)
+{
+    uint8_t *c = lpc->chip_config;
+
+    memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
+
+    pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
+    pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
+    pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
+    pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
+    pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
+    pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
+    pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
+
+    ich9_cc_update(lpc);
+}
+
+static void ich9_cc_addr_len(uint32_t *addr, int *len)
+{
+    *addr &= ICH9_CC_ADDR_MASK;
+    if (*addr + *len >= ICH9_CC_SIZE) {
+        *len = ICH9_CC_SIZE - *addr;
+    }
+}
+
+/* val: little endian */
+static void ich9_cc_write(ICH9_LPCState *lpc, uint32_t addr,
+                          uint32_t val, int len)
+{
+    ich9_cc_addr_len(&addr, &len);
+    memcpy(lpc->chip_config + addr, &val, len);
+}
+
+/* return value: little endian */
+static uint32_t ich9_cc_read(ICH9_LPCState *lpc, uint32_t addr, int len)
+{
+    uint32_t val = 0;
+    ich9_cc_addr_len(&addr, &len);
+    memcpy(&val, lpc->chip_config + addr, len);
+    return val;
+}
+
+#define ICH9_CC_MMIO_WRITE(type, len)                           \
+    static void ich9_cc_mmio_write ## type                      \
+    (void *opaque, target_phys_addr_t addr, uint32_t val)       \
+    {                                                           \
+        ich9_cc_write(opaque, addr, val, len);                  \
+    }
+
+#define ICH9_CC_MMIO_READ(type, len)            \
+    static uint32_t ich9_cc_mmio_read ## type   \
+    (void *opaque, target_phys_addr_t addr)     \
+    {                                           \
+        return ich9_cc_read(opaque, addr, len); \
+    }
+
+ICH9_CC_MMIO_WRITE(b, 1)
+ICH9_CC_MMIO_WRITE(w, 2)
+ICH9_CC_MMIO_WRITE(l, 4)
+
+ICH9_CC_MMIO_READ(b, 1)
+ICH9_CC_MMIO_READ(w, 2)
+ICH9_CC_MMIO_READ(l, 4)
+
+static CPUWriteMemoryFunc * const ich9_cc_mmio_write[] = {
+    ich9_cc_mmio_writeb,
+    ich9_cc_mmio_writew,
+    ich9_cc_mmio_writel,
+};
+
+static CPUReadMemoryFunc * const ich9_cc_mmio_read[] = {
+    ich9_cc_mmio_readb,
+    ich9_cc_mmio_readw,
+    ich9_cc_mmio_readl,
+};
+
+/* IRQ routing */
+/* */
+static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
+{
+    *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
+    *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
+}
+
+static void ich9_lpc_pic_irq(ICH9_LPCState *lpc, int irq_num,
+                             int *pic_irq, int *pic_dis)
+{
+    switch (irq_num) {
+    case 0 ... 3: /* A-D */
+        ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + irq_num],
+                      pic_irq, pic_dis);
+        return;
+    case 4 ... 7: /* E-H */
+        ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (irq_num - 4)],
+                      pic_irq, pic_dis);
+        return;
+    default:
+        break;
+    }
+    abort();
+}
+
+/* pic_irq: i8254 irq 0-15 */
+static void ich9_lpc_update_pic(ICH9_LPCIrqState *irq_state, int pic_irq)
+{
+    GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
+    ICH9_LPCState *lpc = irq_state->lpc;
+    int i, pic_level;
+
+    /* The pic level is the logical OR of all the PCI irqs mapped to it */
+    pic_level = 0;
+    for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
+        int tmp_irq;
+        int tmp_dis;
+        ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
+        if (!tmp_dis && pic_irq == tmp_irq) {
+            pic_level |= pci_bus_get_irq_level(s->host.pci.bus, i);
+        }
+    }
+    if (pic_irq == ich9_lpc_sci_irq(lpc)) {
+        pic_level |= lpc->sci_level;
+    }
+
+    qemu_set_irq(irq_state->pic[pic_irq], pic_level);
+}
+
+/* pirq: pirq[A-H] 0-7*/
+static void ich9_lpc_update_by_pirq(ICH9_LPCIrqState *irq_state, int pirq)
+{
+    ICH9_LPCState *lpc = irq_state->lpc;
+    int pic_irq;
+    int pic_dis;
+
+    ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
+    assert(pic_irq < ICH9_LPC_PIC_NUM_PINS);
+    if (pic_dis) {
+        return;
+    }
+
+    ich9_lpc_update_pic(irq_state, pic_irq);
+}
+
+/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
+static int ich9_pirq_to_gsi(int pirq)
+{
+    return pirq + ICH9_LPC_PIC_NUM_PINS;
+}
+
+static int ich9_gsi_to_pirq(int gsi)
+{
+    return gsi - ICH9_LPC_PIC_NUM_PINS;
+}
+
+static void ich9_lpc_update_apic(ICH9_LPCIrqState *irq_state, int gsi)
+{
+    GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
+    ICH9_LPCState *lpc = irq_state->lpc;
+    int level;
+
+    level = pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
+    if (gsi == ich9_lpc_sci_irq(lpc)) {
+        level |= lpc->sci_level;
+    }
+
+    qemu_set_irq(irq_state->ioapic[gsi], level);
+}
+
+/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
+   a given device irq pin. */
+static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx)
+{
+    ICH9_LPCIrqState *irq_state = opaque;
+    return irq_state->lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
+}
+
+static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
+{
+    ICH9_LPCIrqState *irq_state = opaque;
+
+    assert(0 <= pirq);
+    assert(pirq < ICH9_LPC_NB_PIRQS);
+
+    ich9_lpc_update_apic(irq_state, ich9_pirq_to_gsi(pirq));
+    ich9_lpc_update_by_pirq(irq_state, pirq);
+}
+
+static int ich9_lpc_sci_irq(ICH9_LPCState *lpc)
+{
+    switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
+            ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
+    case ICH9_LPC_ACPI_CTRL_9:
+        return 9;
+    case ICH9_LPC_ACPI_CTRL_10:
+        return 10;
+    case ICH9_LPC_ACPI_CTRL_11:
+        return 11;
+    case ICH9_LPC_ACPI_CTRL_20:
+        return 20;
+    case ICH9_LPC_ACPI_CTRL_21:
+        return 21;
+    default:
+        /* reserved */
+        break;
+    }
+    return -1;
+}
+
+static void ich9_set_sci(void *opaque, int irq_num, int level)
+{
+    ICH9_LPCIrqState *irq_state = opaque;
+    ICH9_LPCState *lpc = irq_state->lpc;
+    int irq;
+
+    assert(irq_num == 0);
+    level = !!level;
+    if (level == lpc->sci_level) {
+        return;
+    }
+    lpc->sci_level = level;
+
+    irq = ich9_lpc_sci_irq(lpc);
+    if (irq < 0) {
+        return;
+    }
+
+    ich9_lpc_update_apic(irq_state, irq);
+    if (irq < ICH9_LPC_PIC_NUM_PINS) {
+        ich9_lpc_update_pic(irq_state, irq);
+    }
+}
+
+void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
+                      qemu_irq cmos_s3)
+{
+    GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+    ICH9_LPCState *lpc = ich9_lpc_from_pci(lpc_pci);
+    qemu_irq *sci_irq;
+
+    sci_irq = qemu_allocate_irqs(ich9_set_sci, &s->irq_state, 1);
+    ich9_pm_init(&lpc->pm, sci_irq[0], cmos_s3);
+
+    ich9_lpc_reset(&lpc->d.qdev);
+}
+
+/* APM */
+static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
+{
+    ICH9_LPCState *lpc = arg;
+
+    /* ACPI specs 3.0, 4.7.2.5 */
+    acpi_pm1_cnt_update(&lpc->pm.pm1_cnt,
+                        val == ICH9_APM_ACPI_ENABLE,
+                        val == ICH9_APM_ACPI_DISABLE);
+
+    /* SMI_EN = PMBASE + 30. SMI control and enable register */
+    if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
+        cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
+    }
+}
+
+/* config:PMBASE */
+static void
+ich9_lpc_pmbase_update(ICH9_LPCState *lpc)
+{
+    uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
+    pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
+
+    ich9_pm_iospace_update(&lpc->pm, pm_io_base);
+}
+
+/* config:RBCA */
+static void ich9_lpc_rcba_update(ICH9_LPCState *lpc, uint32_t rbca_old)
+{
+    uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
+
+    if (rbca_old & ICH9_LPC_RCBA_EN) {
+        cpu_register_physical_memory(rbca_old & ICH9_LPC_RCBA_BA_MASK,
+                                     ICH9_CC_SIZE, IO_MEM_UNASSIGNED);
+    }
+    if (rbca & ICH9_LPC_RCBA_EN) {
+        cpu_register_physical_memory(rbca & ICH9_LPC_RCBA_BA_MASK,
+                                     ICH9_CC_SIZE, lpc->rbca_index);
+    }
+}
+
+static int ich9_lpc_post_load(void *opaque, int version_id)
+{
+    ICH9_LPCState *lpc = opaque;
+
+    ich9_lpc_pmbase_update(lpc);
+    ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */);
+    return 0;
+}
+
+static void ich9_lpc_config_write(PCIDevice *d,
+                                  uint32_t addr, uint32_t val, int len)
+{
+    ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+    uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
+
+    pci_default_write_config(d, addr, val, len);
+    if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) {
+        ich9_lpc_pmbase_update(lpc);
+    }
+    if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
+        ich9_lpc_rcba_update(lpc, rbca_old);
+    }
+}
+
+static void ich9_lpc_reset(DeviceState *qdev)
+{
+    PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
+    ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+    uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
+    int i;
+
+    for (i = 0; i < 4; i++) {
+        pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
+                     ICH9_LPC_PIRQ_ROUT_DEFAULT);
+    }
+    for (i = 0; i < 4; i++) {
+        pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
+                     ICH9_LPC_PIRQ_ROUT_DEFAULT);
+    }
+    pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
+
+    pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
+    pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
+
+    ich9_cc_reset(lpc);
+
+    ich9_lpc_pmbase_update(lpc);
+    ich9_lpc_rcba_update(lpc, rbca_old);
+
+    lpc->sci_level = 0;
+}
+
+static int ich9_lpc_initfn(PCIDevice *d)
+{
+    ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+
+    isa_bus_new(&d->qdev);
+    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+    pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_8); /* ICH9 LPC */
+    pci_config_set_revision(d->config, ICH9_A2_LPC_REVISION);
+    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_ISA);
+
+    pci_set_long(d->wmask + ICH9_LPC_PMBASE,
+                 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
+
+    lpc->rbca_index = cpu_register_io_memory(ich9_cc_mmio_read,
+                                             ich9_cc_mmio_write,
+                                             lpc, DEVICE_LITTLE_ENDIAN);
+
+    ich9_cc_init(lpc);
+    apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc);
+    return 0;
+}
+
+static const VMStateDescription vmstate_ich9_lpc = {
+    .name = "ICH9LPC",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .post_load = ich9_lpc_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(d, ICH9_LPCState),
+        VMSTATE_STRUCT(apm, ICH9_LPCState, 0, vmstate_apm, APMState),
+        VMSTATE_STRUCT(pm, ICH9_LPCState, 0, vmstate_ich9_pm, ICH9_LPCPmRegs),
+        VMSTATE_UINT8_ARRAY(chip_config, ICH9_LPCState, ICH9_CC_SIZE),
+        VMSTATE_UINT32(sci_level, ICH9_LPCState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus)
+{
+    GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+    PCIDevice *d;
+    ICH9_LPCState *lpc;
+
+    d = pci_create_simple_multifunction(bus, PCI_DEVFN(ICH9_LPC_DEV,
+                                                       ICH9_LPC_FUNC),
+                                        true, "ICH9 LPC");
+    lpc = ich9_lpc_from_pci(d);
+    s->irq_state.lpc = lpc;
+    return &lpc->d;
+}
+
+static PCIDeviceInfo ich9_lpc_info = {
+    .qdev.name    = "ICH9 LPC",
+    .qdev.desc    = "ICH9 LPC bridge",
+    .qdev.size    = sizeof(ICH9_LPCState),
+    .qdev.vmsd    = &vmstate_ich9_lpc,
+    .qdev.no_user = 1,
+    .init         = ich9_lpc_initfn,
+    .config_write = ich9_lpc_config_write,
+    .qdev.reset   = ich9_lpc_reset,
+};
+
+static void q35_register(void)
+{
+    sysbus_register_withprop(&gmch_pcihost_info);
+    pci_qdev_register(&gmch_info);
+    pci_qdev_register(&ich9_lpc_info);
+}
+device_init(q35_register);
diff --git a/hw/q35.h b/hw/q35.h
new file mode 100644
index 0000000..c0f5213
--- /dev/null
+++ b/hw/q35.h
@@ -0,0 +1,271 @@
+/*
+ * q35.h
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ *                    VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#ifndef HW_Q35_H
+#define HW_Q35_H
+
+#include "sysbus.h"
+#include "acpi_ich9.h"
+
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+                       qemu_irq *pic, qemu_irq *ioapic);
+
+PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b);
+PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
+PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus);
+void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *pci_lpc,
+                      qemu_irq cmos_s3);
+
+i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
+
+#define Q35_MASK(bit, ms_bit, ls_bit)           ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
+
+/*
+ * gmch part
+ */
+
+/* PCI configuration */
+#define GMCH_HOST_BRIDGE                        "GMCH"
+
+#define GMCH_HOST_BRIDGE_CONFIG_ADDR            0xcf8
+#define GMCH_HOST_BRIDGE_CONFIG_DATA            0xcfc
+
+/* D0:F0 configuration space */
+#define  GMCH_HOST_BRIDGE_REVISION_DEFUALT      0x0
+
+#define GMCH_HOST_BRIDGE_PCIEXBAR               0x60    /* 64bit register */
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_SIZE         8       /* 64bit register */
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT      0xe0000000
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK        Q35_MASK(64, 35, 25)    /* bit 35:28 */
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK     ((uint64_t)(1 << 26))
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK      ((uint64_t)(1 << 25))
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK  ((uint64_t)(0x3 << 1))
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M  ((uint64_t)(0x0 << 1))
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M  ((uint64_t)(0x1 << 1))
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M   ((uint64_t)(0x2 << 1))
+#define  GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD   ((uint64_t)(0x3 << 1))
+#define  GMCH_HOST_BRIDGE_PCIEXBAREN            ((uint64_t)1)
+
+#define GMCH_HOST_BRIDGE_PAM_NB                 7
+#define GMCH_HOST_BRIDGE_PAM_SIZE               7
+#define GMCH_HOST_BRIDGE_PAM0                   0x90
+#define  GMCH_HOST_BRIDGE_PAM_BIOS_AREA         0xf0000
+#define  GMCH_HOST_BRIDGE_PAM_AREA_SIZE         0x10000 /* 16KB */
+#define GMCH_HOST_BRIDGE_PAM1                   0x91
+#define  GMCH_HOST_BRIDGE_PAM_EXPAN_AREA        0xc0000
+#define  GMCH_HOST_BRIDGE_PAM_EXPAN_SIZE        0x04000
+#define GMCH_HOST_BRIDGE_PAM2                   0x92
+#define GMCH_HOST_BRIDGE_PAM3                   0x93
+#define GMCH_HOST_BRIDGE_PAM4                   0x94
+#define  GMCH_HOST_BRIDGE_PAM_EXBIOS_AREA       0xe0000
+#define  GMCH_HOST_BRIDGE_PAM_EXBIOS_SIZE       0x04000
+#define GMCH_HOST_BRIDGE_PAM5                   0x95
+#define GMCH_HOST_BRIDGE_PAM6                   0x96
+#define  GMCH_HOST_BRIDGE_PAM_WE_HI             ((uint8_t)(0x2 << 4))
+#define  GMCH_HOST_BRIDGE_PAM_RE_HI             ((uint8_t)(0x1 << 4))
+#define  GMCH_HOST_BRIDGE_PAM_HI_MASK           ((uint8_t)(0x3 << 4))
+#define  GMCH_HOST_BRIDGE_PAM_WE_LO             ((uint8_t)0x2)
+#define  GMCH_HOST_BRIDGE_PAM_RE_LO             ((uint8_t)0x1)
+#define  GMCH_HOST_BRIDGE_PAM_LO_MASK           ((uint8_t)0x3)
+#define  GMCH_HOST_BRIDGE_PAM_WE                ((uint8_t)0x2)
+#define  GMCH_HOST_BRIDGE_PAM_RE                ((uint8_t)0x1)
+#define  GMCH_HOST_BRIDGE_PAM_MASK              ((uint8_t)0x3)
+
+#define GMCH_HOST_BRDIGE_SMRAM                  0x9d
+#define GMCH_HOST_BRDIGE_SMRAM_SIZE             1
+#define  GMCH_HOST_BRIDGE_SMRAM_DEFAULT         ((uint8_t)0x2)
+#define  GMCH_HOST_BRIDGE_SMRAM_D_OPEN          ((uint8_t)(1 << 6))
+#define  GMCH_HOST_BRIDGE_SMRAM_D_CLS           ((uint8_t)(1 << 5))
+#define  GMCH_HOST_BRIDGE_SMRAM_D_LCK           ((uint8_t)(1 << 4))
+#define  GMCH_HOST_BRIDGE_SMRAM_G_SMRAME        ((uint8_t)(1 << 3))
+#define  GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
+#define  GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG      ((uint8_t)0x2)  /* hardwired to b010 */
+#define   GMCH_HOST_BRIDGE_SMRAM_C_BASE         0xa0000
+#define   GMCH_HOST_BRIDGE_SMRAM_C_END          0xc0000
+#define   GMCH_HOST_BRIDGE_SMRAM_C_SIZE         0x20000
+#define GMCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END  0x100000
+
+#define GMCH_HOST_BRIDGE_ESMRAMC                0x9e
+#define  GMCH_HOST_BRDIGE_ESMRAMC_H_SMRAME      ((uint8_t)(1 << 6))
+#define  GMCH_HOST_BRDIGE_ESMRAMC_E_SMERR       ((uint8_t)(1 << 5))
+#define  GMCH_HOST_BRDIGE_ESMRAMC_SM_CACHE      ((uint8_t)(1 << 4))
+#define  GMCH_HOST_BRDIGE_ESMRAMC_SM_L1         ((uint8_t)(1 << 3))
+#define  GMCH_HOST_BRDIGE_ESMRAMC_SM_L2         ((uint8_t)(1 << 2))
+#define  GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK  ((uint8_t)(0x3 << 1))
+#define   GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB  ((uint8_t)(0x0 << 1))
+#define   GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB  ((uint8_t)(0x1 << 1))
+#define   GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB  ((uint8_t)(0x2 << 1))
+#define  GMCH_HOST_BRDIGE_ESMRAMC_T_EN          ((uint8_t)1)
+
+/* D1:F0 PCIE* port*/
+#define GMCH_PCIE_DEV                           1
+#define GMCH_PCIE_FUNC                          0
+
+/*
+ * ich9 part
+ */
+
+/* ICH9: Chipset Configuration Registers */
+#define ICH9_CC_SIZE                            (16 * 1024)     /* 16KB */
+#define ICH9_CC_ADDR_MASK                       (ICH9_CC_SIZE - 1)
+
+#define ICH9_CC
+#define ICH9_CC_D28IP                           0x310C
+#define  ICH9_CC_D28IP_SHIFT                    4
+#define  ICH9_CC_D28IP_MASK                     0xf
+#define  ICH9_CC_D28IP_DEFAULT                  0x00214321
+#define ICH9_CC_D31IR                           0x3140
+#define ICH9_CC_D30IR                           0x3142
+#define ICH9_CC_D29IR                           0x3144
+#define ICH9_CC_D28IR                           0x3146
+#define ICH9_CC_D27IR                           0x3148
+#define ICH9_CC_D26IR                           0x314C
+#define ICH9_CC_D25IR                           0x3150
+#define  ICH9_CC_DIR_DEFAULT                    0x3210
+#define  ICH9_CC_D30IR_DEFAULT                  0x0
+#define  ICH9_CC_DIR_SHIFT                      4
+#define  ICH9_CC_DIR_MASK                       0x7
+#define ICH9_CC_OIC                             0x31FF
+#define  ICH9_CC_OIC_AEN                        0x1
+
+/* D28:F[0-5] */
+#define ICH9_PCIE_DEV                           28
+#define ICH9_PCIE_FUNC_MAX                      6
+
+
+/* D29:F0 USB UHCI Controller #1 */
+#define ICH9_USB_UHCI1_DEV                      29
+#define ICH9_USB_UHCI1_FUNC                     0
+
+/* D30:F0 DMI-to-PCI brdige */
+#define ICH9_D2P_BRIDGE                         "ICH9 D2P BRIDGE"
+#define ICH9_D2P_BRIDGE_SAVEVM_VERSION          0
+
+#define ICH9_D2P_BRIDGE_DEV                     30
+#define ICH9_D2P_BRIDGE_FUNC                    0
+
+#define ICH9_D2P_SECONDARY_DEFAULT              (256 - 8)
+
+#define ICH9_D2P_A2_REVISION                    0x92
+
+
+/* D31:F1 LPC controller */
+#define ICH9_A2_LPC                             "ICH9 A2 LPC"
+#define ICH9_A2_LPC_SAVEVM_VERSION              0
+
+#define ICH9_LPC_DEV                            31
+#define ICH9_LPC_FUNC                           0
+
+#define ICH9_A2_LPC_REVISION                    0x2
+#define ICH9_LPC_NB_PIRQS                       8       /* PCI A-H */
+
+#define ICH9_LPC_PMBASE                         0x40
+#define  ICH9_LPC_PMBASE_BASE_ADDRESS_MASK      Q35_MASK(32, 15, 7)
+#define  ICH9_LPC_PMBASE_RTE                    0x1
+#define  ICH9_LPC_PMBASE_DEFAULT                0x1
+#define ICH9_LPC_ACPI_CTRL                      0x44
+#define  ICH9_LPC_ACPI_CTRL_ACPI_EN             0x80
+#define  ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK    Q35_MASK(8, 2, 0)
+#define  ICH9_LPC_ACPI_CTRL_9                   0x0
+#define  ICH9_LPC_ACPI_CTRL_10                  0x1
+#define  ICH9_LPC_ACPI_CTRL_11                  0x2
+#define  ICH9_LPC_ACPI_CTRL_20                  0x4
+#define  ICH9_LPC_ACPI_CTRL_21                  0x5
+#define  ICH9_LPC_ACPI_CTRL_DEFAULT             0x0
+
+#define ICH9_LPC_PIRQA_ROUT                     0x60
+#define ICH9_LPC_PIRQB_ROUT                     0x61
+#define ICH9_LPC_PIRQC_ROUT                     0x62
+#define ICH9_LPC_PIRQD_ROUT                     0x63
+
+#define ICH9_LPC_PIRQE_ROUT                     0x68
+#define ICH9_LPC_PIRQF_ROUT                     0x69
+#define ICH9_LPC_PIRQG_ROUT                     0x6a
+#define ICH9_LPC_PIRQH_ROUT                     0x6b
+
+#define  ICH9_LPC_PIRQ_ROUT_IRQEN               0x80
+#define  ICH9_LPC_PIRQ_ROUT_MASK                Q35_MASK(8, 3, 0)
+#define  ICH9_LPC_PIRQ_ROUT_DEFAULT             0x80
+
+#define ICH9_LPC_RCBA                           0xf0
+#define  ICH9_LPC_RCBA_BA_MASK                  Q35_MASK(32, 31, 14)
+#define  ICH9_LPC_RCBA_EN                       0x1
+#define  ICH9_LPC_RCBA_DEFAULT                  0x0
+
+#define ICH9_LPC_PIC_NUM_PINS                   16
+#define ICH9_LPC_IOAPIC_NUM_PINS                24
+
+/* D31:F2 SATA Controller #1 */
+#define ICH9_SATA1_DEV                          31
+#define ICH9_SATA1_FUNC                         2
+
+/* D30:F1 power management I/O registers
+   offset from the address ICH9_LPC_PMBASE */
+
+/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
+#define ICH9_PMIO_SIZE                          128
+#define ICH9_PMIO_MASK                          (ICH9_PMIO_SIZE - 1)
+
+#define ICH9_PMIO_PM1_STS                       0x00
+#define ICH9_PMIO_PM1_EN                        0x02
+#define ICH9_PMIO_PM1_CNT                       0x04
+#define ICH9_PMIO_PM1_TMR                       0x08
+#define ICH9_PMIO_GPE0_STS                      0x20
+#define ICH9_PMIO_GPE0_EN                       0x28
+#define  ICH9_PMIO_GPE0_LEN                     16
+#define ICH9_PMIO_SMI_EN                        0x30
+#define  ICH9_PMIO_SMI_EN_APMC_EN               (1 << 5)
+#define ICH9_PMIO_SMI_STS                       0x34
+
+/* FADT ACPI_ENABLE/ACPI_DISABLE */
+#define ICH9_APM_ACPI_ENABLE                    0x2
+#define ICH9_APM_ACPI_DISABLE                   0x3
+
+
+/* D31:F3 SMBus controller */
+#define ICH9_A2_SMB_REVISION                    0x02
+#define ICH9_SMB_PI                             0x00
+
+#define ICH9_SMB_SMBMBAR0                       0x10
+#define ICH9_SMB_SMBMBAR1                       0x14
+#define  ICH9_SMB_SMBM_BAR                      0
+#define  ICH9_SMB_SMBM_SIZE                     (1 << 8)
+#define ICH9_SMB_SMB_BASE                       0x20
+#define  ICH9_SMB_SMB_BASE_BAR                  4
+#define  ICH9_SMB_SMB_BASE_SIZE                 (1 << 5)
+#define ICH9_SMB_HOSTC                          0x40
+#define  ICH9_SMB_HOSTC_SSRESET                 ((uint8_t)(1 << 3))
+#define  ICH9_SMB_HOSTC_I2C_EN                  ((uint8_t)(1 << 2))
+#define  ICH9_SMB_HOSTC_SMB_SMI_EN              ((uint8_t)(1 << 1))
+#define  ICH9_SMB_HOSTC_HST_EN                  ((uint8_t)(1 << 0))
+
+/* D31:F3 SMBus I/O and memory mapped I/O registers */
+#define ICH9_SMB_DEV                            31
+#define ICH9_SMB_FUNC                           3
+
+#define ICH9_SMB_HST_STS                        0x00
+#define ICH9_SMB_HST_CNT                        0x02
+#define ICH9_SMB_HST_CMD                        0x03
+#define ICH9_SMB_XMIT_SLVA                      0x04
+#define ICH9_SMB_HST_D0                         0x05
+#define ICH9_SMB_HST_D1                         0x06
+#define ICH9_SMB_HOST_BLOCK_DB                  0x07
+
+#endif /* HW_Q35_H */
diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
new file mode 100644
index 0000000..fe445ac
--- /dev/null
+++ b/hw/q35_smbus.c
@@ -0,0 +1,154 @@
+/*
+ * ACPI implementation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+/*
+ *  Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ *                     VA Linux Systems Japan K.K.
+ *
+ *  This is based on acpi.c, but heavily rewritten.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "pm_smbus.h"
+#include "pci.h"
+#include "sysemu.h"
+#include "i2c.h"
+#include "smbus.h"
+
+#include "q35.h"
+
+typedef struct ICH9_SMBState {
+    PCIDevice dev;
+
+    PMSMBus smb;
+} ICH9_SMBState;
+
+static ICH9_SMBState *ich9_pci_to_smb(PCIDevice* pci_dev)
+{
+    return DO_UPCAST(ICH9_SMBState, dev, pci_dev);
+}
+
+static const VMStateDescription vmstate_ich9_smbus = {
+    .name = "ich9_smb",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(dev, struct ICH9_SMBState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+    ICH9_SMBState *s = opaque;
+    uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
+
+    if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
+        uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
+        smb_ioport_writeb(&s->smb, offset, val);
+    }
+}
+
+static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
+{
+    ICH9_SMBState *s = opaque;
+    uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
+
+    if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
+        uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
+        return smb_ioport_readb(&s->smb, offset);
+    }
+
+    return 0xff;
+}
+
+static void ich9_smb_map_ioport(PCIDevice *dev, int region_num,
+                                uint64_t addr, uint64_t size, int type)
+{
+    ICH9_SMBState *s = ich9_pci_to_smb(dev);
+
+    assert(size == ICH9_SMB_SMB_BASE_SIZE);
+    assert(type == PCI_BASE_ADDRESS_SPACE_IO);
+
+    register_ioport_write(addr, 64, 1, ich9_smb_ioport_writeb, s);
+    register_ioport_read(addr, 64, 1, ich9_smb_ioport_readb, s);
+}
+
+static int ich9_smb_initfn(PCIDevice *d)
+{
+    ICH9_SMBState *s = ich9_pci_to_smb(d);
+
+    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+    pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_6);
+
+    pci_set_word(d->wmask + PCI_STATUS,
+                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
+
+    pci_config_set_revision(d->config, ICH9_A2_SMB_REVISION);
+    pci_config_set_prog_interface(d->config, ICH9_SMB_PI);
+    pci_config_set_class(d->config, PCI_CLASS_SERIAL_SMBUS);
+
+    /* TODO? D31IP.SMIP in chipset configuration space */
+    pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
+
+    pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
+
+    /*
+     * update parameters based on
+     * paralell_hds[0]
+     * serial_hds[0]
+     * serial_hds[0]
+     * fdc
+     *
+     * Is there any OS that depends on them?
+     */
+
+    /* TODO smb_io_base */
+    pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
+    /* TODO bar0, bar1: 64bit BAR support*/
+    pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR,
+                     ICH9_SMB_SMB_BASE_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
+                     &ich9_smb_map_ioport);
+
+    pm_smbus_init(&d->qdev, &s->smb);
+    return 0;
+}
+
+i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
+{
+    PCIDevice *d =
+        pci_create_simple_multifunction(bus, devfn, true, "ICH9 SMB");
+    ICH9_SMBState *s = ich9_pci_to_smb(d);
+    return s->smb.smbus;
+}
+
+static PCIDeviceInfo ich9_smb_info = {
+    .qdev.name = "ICH9 SMB",
+    .qdev.desc = "ICH9 SMBUS Bridge",
+    .qdev.size = sizeof(ICH9_SMBState),
+    .qdev.vmsd = &vmstate_ich9_smbus,
+    .qdev.no_user = 1,
+    .init = ich9_smb_initfn,
+};
+
+static void ich9_smb_register(void)
+{
+    pci_qdev_register(&ich9_smb_info);
+}
+
+device_init(ich9_smb_register);
-- 
1.7.1.1

[Qemu-devel] ACPI table loading [was: q35 chipset support for native pci express support]

[Michael Tokarev]

16.03.2011 12:29, Isaku Yamahata wrote:
> This patch series adds basic q35 chipset support for native pci express
> support. Some bios related patches are still needed.
> For those who want to try it, the following repo is avaiable.
> (vgabios doesn't need patches, so use the upstream one)
> 
> git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
> git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/seabios
> 
> Example:
> qemu-system-x86_64 ... -M pc_q35 -acpitable 'load_header,data=roms/seabios/src/q35-acpi-dsdt.aml

My question is unrelated to your q35 work, but I have a suggestion
here: can we avoid this "load_header" thing please?  I hacked this
area locally a while back while trying to run OEM-licensed windows
with a SLIC table in BIOS, and wanted to come with alternative
approach.  Now when you reminded me that again I'd rather finish
that old thing and post a real patch...

Here's my "idea".  First, if there's no other options provided
except of data=..., just treat it as "headerful", ie, complete with
the header.  Or alternatively (or at the same time), recognize
"file=" the same way as "data=".  We can go even further and load
file/data first and patch in the other header field if specified,
so it'll be possible to overwrite only certain parts of the header
but load the rest of the table (complete with all other headers)
from a file.

Does it make sense?



> 
> 
> The motivation is to support newer hardware features because
> piix chipset is very old.
> Especially I have PCI express in mind and this is the basic infrastructure
> for PCI express hot plug and PCI express native direct attach.
> I can boot Linux with PCIe MMCONFIG with APIC mode pci interrupt routing.
> I haven't tested other OSes.
> 
> The patch series consist as following
> 
> - Firstly, some PCI patches which introduce helper functions and so on.
> - Then, PC initialization related patches which simplifies pc board
>   initialization, pc_init1().
> - Thirdly, factoring out the logics which are common to the existing
>    piix and q35. ie. smram, pam and acpi logic.
> - At last introduce q35 chipset emulator which is able to handle
>   pci express natively.
> 
> Thanks,
> 
> Change from v7:
> - heavily reorganized and improved.
> - factoring out code duplication.
> - improved irq routing fully.
> 
> Changes from split out piix specific part from pc emulator. V6
> - rebased to 731c54f86988d3f28268f184fabfe9b2a32fb5d3
> - PCIe MMCONFIG
> - pci bridge related fixes
> - chipset emulator works.
> - IOAPIC patches
> 
> Changes from v5:
> - rebased 0.11.0-rc0
> - changed qemu_system_powerdown_register() to call
>   qemu_system_shutdown_request() if qemu_system_shutdown() is called before
>   registering.
> 
> Changes from v4:
> - fix version number.
> - rebased anthony's staging tree whose latest change set is
>   62969268f876c547ee64da6d60e0f363e0f1df75
> 
> Changes from v3:
> - move qemu_system_powerdown() in vl.c and more generic
>   following the comment by Marcelo Tosatti <mtosatti@redhat.com>
>   acpi.c: make qemu_system_powerdown() piix independent.
> - define cmos_set_s3_resume_init() and cmos_set_s3_resume() in pc.c
>   even if TARGET_I386 isn't defined following th ecommit by
>   Paolo Bonzini <bonzini@gnu.org>
>   pc.c: remove a global variable, RTCState *rtc_state.
> - minor compilation fixes
> 
> Changes from v2:
> - clean up pc_pci_device_init() not to use unnecessary braces.
> 
> Changes from v1:
> - make patches full bisectable
> - typo s/allocte/allocate/
> - some minor fixes
> - dropped a merged patch
> 
> Isaku Yamahata (26):
>   pci: replace the magic, 256, for the maximum of slot
>   pci: add opaque argument to pci_map_irq_fn
>   pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt
>     pin swizzle
>   pci: add accessor function to get irq levels
>   piix_pci: eliminate PIIX3State::pci_irq_levels
>   pci_bridge: add helper function to convert PCIBridge into PCIDevice
>   pci/p2pbr: generic pci p2p bridge
>   apb_pci: simplify apb_pci.c by using pci_p2pbr
>   dec_pci: simplify dec_pci.c by using pci_p2pbr
>   ide/ahci/ich: use qdev.reset
>   ahci: add ide device initialization helper
>   usb/uhci: generalize initialization
>   usb/uhci: add ich9 usb uhci id's device
>   ide: consolidate drive_get(IF_IDE)
>   smbus_eeprom: consolidate smbus eeprom creation
>   pc, pc_piix: split out allocating isa irqs
>   pc, pc_piix: split out pc nic initialization
>   ioapic: move ioapic_init() from pc_piix.c to pc.c
>   pc/piix_pci: factor out smram/pam logic
>   pc, i440fx: simply i440fx initialization
>   acpi, acpi_piix: factor out PM_TMR logic
>   acpi, acpi_piix: factor out PM1a EVT logic
>   acpi, acpi_piix: factor out PM1_CNT logic
>   acpi, acpi_piix: factor out GPE logic
>   pci_ids: add intel 82801BA pci-to-pci bridge id and
>     PCI_CLASS_SERIAL_SMBUS
>   pc q35 based chipset emulator
> 
>  Makefile.objs      |    2 +-
>  Makefile.target    |    3 +-
>  hw/acpi.c          |  197 ++++++++++++
>  hw/acpi.h          |   68 ++++
>  hw/acpi_ich9.c     |  314 +++++++++++++++++++
>  hw/acpi_ich9.h     |   53 ++++
>  hw/acpi_piix4.c    |  220 ++++----------
>  hw/apb_pci.c       |   67 ++---
>  hw/bonito.c        |    2 +-
>  hw/dec_pci.c       |   51 +---
>  hw/grackle_pci.c   |    2 +-
>  hw/gt64xxx.c       |    2 +-
>  hw/ide.h           |    6 +
>  hw/ide/ahci.c      |   15 +
>  hw/ide/core.c      |   14 +
>  hw/ide/ich.c       |    9 +-
>  hw/mips_fulong2e.c |   18 +-
>  hw/mips_malta.c    |   22 +--
>  hw/mips_r4k.c      |   10 +-
>  hw/pam.c           |  128 ++++++++
>  hw/pam.h           |   96 ++++++
>  hw/pc.c            |   47 +++-
>  hw/pc.h            |    7 +-
>  hw/pc_piix.c       |   64 +----
>  hw/pc_q35.c        |  359 +++++++++++++++++++++
>  hw/pci.c           |   27 ++-
>  hw/pci.h           |    6 +-
>  hw/pci_bridge.c    |    6 +
>  hw/pci_bridge.h    |    1 +
>  hw/pci_ids.h       |   17 +
>  hw/pci_internals.h |    2 +-
>  hw/pci_p2pbr.c     |  151 +++++++++
>  hw/pci_p2pbr.h     |   61 ++++
>  hw/piix_pci.c      |  117 +++-----
>  hw/ppc4xx_pci.c    |    2 +-
>  hw/ppc_newworld.c  |   11 +-
>  hw/ppc_oldworld.c  |   11 +-
>  hw/ppc_prep.c      |   10 +-
>  hw/ppce500_pci.c   |    2 +-
>  hw/prep_pci.c      |    2 +-
>  hw/q35.c           |  877 ++++++++++++++++++++++++++++++++++++++++++++++++++++
>  hw/q35.h           |  271 ++++++++++++++++
>  hw/q35_smbus.c     |  154 +++++++++
>  hw/sh_pci.c        |    2 +-
>  hw/smbus.h         |    3 +
>  hw/smbus_eeprom.c  |   22 ++-
>  hw/sun4u.c         |    9 +-
>  hw/unin_pci.c      |    2 +-
>  hw/usb-uhci.c      |   93 +++---
>  hw/versatile_pci.c |    2 +-
>  50 files changed, 3116 insertions(+), 521 deletions(-)
>  create mode 100644 hw/acpi_ich9.c
>  create mode 100644 hw/acpi_ich9.h
>  create mode 100644 hw/pam.c
>  create mode 100644 hw/pam.h
>  create mode 100644 hw/pc_q35.c
>  create mode 100644 hw/pci_p2pbr.c
>  create mode 100644 hw/pci_p2pbr.h
>  create mode 100644 hw/q35.c
>  create mode 100644 hw/q35.h
>  create mode 100644 hw/q35_smbus.c
> 
> 
	

Re: [Qemu-devel] ACPI table loading [was: q35 chipset support for native pci express support]

[Isaku Yamahata]

On Wed, Mar 16, 2011 at 01:12:27PM +0300, Michael Tokarev wrote:
> 16.03.2011 12:29, Isaku Yamahata wrote:
> > This patch series adds basic q35 chipset support for native pci express
> > support. Some bios related patches are still needed.
> > For those who want to try it, the following repo is avaiable.
> > (vgabios doesn't need patches, so use the upstream one)
> > 
> > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
> > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/seabios
> > 
> > Example:
> > qemu-system-x86_64 ... -M pc_q35 -acpitable 'load_header,data=roms/seabios/src/q35-acpi-dsdt.aml
> 
> My question is unrelated to your q35 work, but I have a suggestion
> here: can we avoid this "load_header" thing please?  I hacked this
> area locally a while back while trying to run OEM-licensed windows
> with a SLIC table in BIOS, and wanted to come with alternative
> approach.  Now when you reminded me that again I'd rather finish
> that old thing and post a real patch...
> 
> Here's my "idea".  First, if there's no other options provided
> except of data=..., just treat it as "headerful", ie, complete with
> the header.  Or alternatively (or at the same time), recognize
> "file=" the same way as "data=".  We can go even further and load
> file/data first and patch in the other header field if specified,
> so it'll be possible to overwrite only certain parts of the header
> but load the rest of the table (complete with all other headers)
> from a file.
> 
> Does it make sense?

It sounds reasonable. As long as the patch is acceptable,
I'm willing to update the patch.
Let me summarize it. Your suggestion for -acpitable is
  
                existing behavior               your suggested way
data= only
no sig=,...     header is filled with zero      headerful
                (headerless)                    (new behaviour)
                useless behavior

with sig=...    header is created               header is created
                (headerless)                    (headerless)

thanks,

> > 
> > 
> > The motivation is to support newer hardware features because
> > piix chipset is very old.
> > Especially I have PCI express in mind and this is the basic infrastructure
> > for PCI express hot plug and PCI express native direct attach.
> > I can boot Linux with PCIe MMCONFIG with APIC mode pci interrupt routing.
> > I haven't tested other OSes.
> > 
> > The patch series consist as following
> > 
> > - Firstly, some PCI patches which introduce helper functions and so on.
> > - Then, PC initialization related patches which simplifies pc board
> >   initialization, pc_init1().
> > - Thirdly, factoring out the logics which are common to the existing
> >    piix and q35. ie. smram, pam and acpi logic.
> > - At last introduce q35 chipset emulator which is able to handle
> >   pci express natively.
> > 
> > Thanks,
> > 
> > Change from v7:
> > - heavily reorganized and improved.
> > - factoring out code duplication.
> > - improved irq routing fully.
> > 
> > Changes from split out piix specific part from pc emulator. V6
> > - rebased to 731c54f86988d3f28268f184fabfe9b2a32fb5d3
> > - PCIe MMCONFIG
> > - pci bridge related fixes
> > - chipset emulator works.
> > - IOAPIC patches
> > 
> > Changes from v5:
> > - rebased 0.11.0-rc0
> > - changed qemu_system_powerdown_register() to call
> >   qemu_system_shutdown_request() if qemu_system_shutdown() is called before
> >   registering.
> > 
> > Changes from v4:
> > - fix version number.
> > - rebased anthony's staging tree whose latest change set is
> >   62969268f876c547ee64da6d60e0f363e0f1df75
> > 
> > Changes from v3:
> > - move qemu_system_powerdown() in vl.c and more generic
> >   following the comment by Marcelo Tosatti <mtosatti@redhat.com>
> >   acpi.c: make qemu_system_powerdown() piix independent.
> > - define cmos_set_s3_resume_init() and cmos_set_s3_resume() in pc.c
> >   even if TARGET_I386 isn't defined following th ecommit by
> >   Paolo Bonzini <bonzini@gnu.org>
> >   pc.c: remove a global variable, RTCState *rtc_state.
> > - minor compilation fixes
> > 
> > Changes from v2:
> > - clean up pc_pci_device_init() not to use unnecessary braces.
> > 
> > Changes from v1:
> > - make patches full bisectable
> > - typo s/allocte/allocate/
> > - some minor fixes
> > - dropped a merged patch
> > 
> > Isaku Yamahata (26):
> >   pci: replace the magic, 256, for the maximum of slot
> >   pci: add opaque argument to pci_map_irq_fn
> >   pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt
> >     pin swizzle
> >   pci: add accessor function to get irq levels
> >   piix_pci: eliminate PIIX3State::pci_irq_levels
> >   pci_bridge: add helper function to convert PCIBridge into PCIDevice
> >   pci/p2pbr: generic pci p2p bridge
> >   apb_pci: simplify apb_pci.c by using pci_p2pbr
> >   dec_pci: simplify dec_pci.c by using pci_p2pbr
> >   ide/ahci/ich: use qdev.reset
> >   ahci: add ide device initialization helper
> >   usb/uhci: generalize initialization
> >   usb/uhci: add ich9 usb uhci id's device
> >   ide: consolidate drive_get(IF_IDE)
> >   smbus_eeprom: consolidate smbus eeprom creation
> >   pc, pc_piix: split out allocating isa irqs
> >   pc, pc_piix: split out pc nic initialization
> >   ioapic: move ioapic_init() from pc_piix.c to pc.c
> >   pc/piix_pci: factor out smram/pam logic
> >   pc, i440fx: simply i440fx initialization
> >   acpi, acpi_piix: factor out PM_TMR logic
> >   acpi, acpi_piix: factor out PM1a EVT logic
> >   acpi, acpi_piix: factor out PM1_CNT logic
> >   acpi, acpi_piix: factor out GPE logic
> >   pci_ids: add intel 82801BA pci-to-pci bridge id and
> >     PCI_CLASS_SERIAL_SMBUS
> >   pc q35 based chipset emulator
> > 
> >  Makefile.objs      |    2 +-
> >  Makefile.target    |    3 +-
> >  hw/acpi.c          |  197 ++++++++++++
> >  hw/acpi.h          |   68 ++++
> >  hw/acpi_ich9.c     |  314 +++++++++++++++++++
> >  hw/acpi_ich9.h     |   53 ++++
> >  hw/acpi_piix4.c    |  220 ++++----------
> >  hw/apb_pci.c       |   67 ++---
> >  hw/bonito.c        |    2 +-
> >  hw/dec_pci.c       |   51 +---
> >  hw/grackle_pci.c   |    2 +-
> >  hw/gt64xxx.c       |    2 +-
> >  hw/ide.h           |    6 +
> >  hw/ide/ahci.c      |   15 +
> >  hw/ide/core.c      |   14 +
> >  hw/ide/ich.c       |    9 +-
> >  hw/mips_fulong2e.c |   18 +-
> >  hw/mips_malta.c    |   22 +--
> >  hw/mips_r4k.c      |   10 +-
> >  hw/pam.c           |  128 ++++++++
> >  hw/pam.h           |   96 ++++++
> >  hw/pc.c            |   47 +++-
> >  hw/pc.h            |    7 +-
> >  hw/pc_piix.c       |   64 +----
> >  hw/pc_q35.c        |  359 +++++++++++++++++++++
> >  hw/pci.c           |   27 ++-
> >  hw/pci.h           |    6 +-
> >  hw/pci_bridge.c    |    6 +
> >  hw/pci_bridge.h    |    1 +
> >  hw/pci_ids.h       |   17 +
> >  hw/pci_internals.h |    2 +-
> >  hw/pci_p2pbr.c     |  151 +++++++++
> >  hw/pci_p2pbr.h     |   61 ++++
> >  hw/piix_pci.c      |  117 +++-----
> >  hw/ppc4xx_pci.c    |    2 +-
> >  hw/ppc_newworld.c  |   11 +-
> >  hw/ppc_oldworld.c  |   11 +-
> >  hw/ppc_prep.c      |   10 +-
> >  hw/ppce500_pci.c   |    2 +-
> >  hw/prep_pci.c      |    2 +-
> >  hw/q35.c           |  877 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> >  hw/q35.h           |  271 ++++++++++++++++
> >  hw/q35_smbus.c     |  154 +++++++++
> >  hw/sh_pci.c        |    2 +-
> >  hw/smbus.h         |    3 +
> >  hw/smbus_eeprom.c  |   22 ++-
> >  hw/sun4u.c         |    9 +-
> >  hw/unin_pci.c      |    2 +-
> >  hw/usb-uhci.c      |   93 +++---
> >  hw/versatile_pci.c |    2 +-
> >  50 files changed, 3116 insertions(+), 521 deletions(-)
> >  create mode 100644 hw/acpi_ich9.c
> >  create mode 100644 hw/acpi_ich9.h
> >  create mode 100644 hw/pam.c
> >  create mode 100644 hw/pam.h
> >  create mode 100644 hw/pc_q35.c
> >  create mode 100644 hw/pci_p2pbr.c
> >  create mode 100644 hw/pci_p2pbr.h
> >  create mode 100644 hw/q35.c
> >  create mode 100644 hw/q35.h
> >  create mode 100644 hw/q35_smbus.c
> > 
> > 
> 	
> 

-- 
yamahata

[Qemu-devel] RFC: ACPI table loading

[Michael Tokarev]

16.03.2011 15:10, Isaku Yamahata wrote:
> On Wed, Mar 16, 2011 at 01:12:27PM +0300, Michael Tokarev wrote:
>> 16.03.2011 12:29, Isaku Yamahata wrote:

>>> Example:
>>> qemu-system-x86_64 ... -M pc_q35 -acpitable 'load_header,data=roms/seabios/src/q35-acpi-dsdt.aml
>>
>> My question is unrelated to your q35 work, but I have a suggestion
>> here: can we avoid this "load_header" thing please?  I hacked this
>> area locally a while back while trying to run OEM-licensed windows
>> with a SLIC table in BIOS, and wanted to come with alternative
>> approach.  Now when you reminded me that again I'd rather finish
>> that old thing and post a real patch...
>>
>> Here's my "idea".  First, if there's no other options provided
>> except of data=..., just treat it as "headerful", ie, complete with
>> the header.  Or alternatively (or at the same time), recognize
>> "file=" the same way as "data=".  We can go even further and load
>> file/data first and patch in the other header field if specified,
>> so it'll be possible to overwrite only certain parts of the header
>> but load the rest of the table (complete with all other headers)
>> from a file.
>>
>> Does it make sense?
> 
> It sounds reasonable. As long as the patch is acceptable,
> I'm willing to update the patch.
> Let me summarize it. Your suggestion for -acpitable is
>   
>                 existing behavior               your suggested way
> data= only
> no sig=,...     header is filled with zero      headerful
>                 (headerless)                    (new behaviour)
>                 useless behavior
> 
> with sig=...    header is created               header is created
>                 (headerless)                    (headerless)

I just implemented the whole thing, and refined it at the same
time.  With data= it works the same way as before, so no
new behavour is introduced.  Only with file= it is possible
to specify whole table (with header) in a file, but other
header fields specified on the command line (sig= etc) will
work still, replacing the corresponding fields in the header
read from the file.

Something like the below, it's just an RFC, but it appears
to work.

/mjt

Subject: rewamp acpitable parsing, and allow specifying complete file with headers

This patch almost rewrites acpi_table_add() function
(but still leaves it using old get_param_value() interface).
The result is that it's now possible to specify whole table
(together with a header) in an external file, instead of just
data portion, with a new file= parameter, but at the same time
it's still possible to specify header fields as before.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

diff --git a/hw/acpi.c b/hw/acpi.c
index 237526d..d12527e 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -22,18 +22,8 @@
 #include "qemu-kvm.h"
 #include "string.h"

-struct acpi_table_header
-{
-    char signature [4];    /* ACPI signature (4 ASCII characters) */
-    uint32_t length;          /* Length of table, in bytes, including header */
-    uint8_t revision;         /* ACPI Specification minor version # */
-    uint8_t checksum;         /* To make sum of entire table == 0 */
-    char oem_id [6];       /* OEM identification */
-    char oem_table_id [8]; /* OEM table identification */
-    uint32_t oem_revision;    /* OEM revision number */
-    char asl_compiler_id [4]; /* ASL compiler vendor ID */
-    uint32_t asl_compiler_revision; /* ASL compiler revision number */
-} __attribute__((packed));
+
+#define ACPI_TABLE_HDR_SIZE (4+4+1+1+6+8+4+4+4)

 char *acpi_tables;
 size_t acpi_tables_len;
@@ -50,153 +40,220 @@ static int acpi_checksum(const uint8_t *data, int len)
 int acpi_table_add(const char *t)
 {
     static const char *dfl_id = "QEMUQEMU";
-    char buf[1024], *p, *f;
-    struct acpi_table_header acpi_hdr;
+    char buf[1024], *f, *p;
     unsigned long val;
-    uint32_t length;
-    struct acpi_table_header *acpi_hdr_p;
-    size_t off;
-
-    memset(&acpi_hdr, 0, sizeof(acpi_hdr));
-
-    if (get_param_value(buf, sizeof(buf), "sig", t)) {
-        strncpy(acpi_hdr.signature, buf, 4);
-    } else {
-        strncpy(acpi_hdr.signature, dfl_id, 4);
-    }
-    if (get_param_value(buf, sizeof(buf), "rev", t)) {
+    size_t len, start;
+    bool has_header;
+    int changed;
+
+    /*XXX fixme: this function uses obsolete argument parsing interface */
+    /*XXX note: all 32bit accesses in there are misaligned */
+
+    if (get_param_value(buf, sizeof(buf), "data", t))
+    {
+	has_header = 0;
+    }
+    else if (get_param_value(buf, sizeof(buf), "file", t))
+    {
+	has_header = 1;
+    }
+    else {
+	has_header = 0;
+	buf[0] = '\0';
+    }
+
+    if (!acpi_tables)
+    {
+	acpi_tables_len = sizeof(uint16_t);
+	acpi_tables = qemu_mallocz(acpi_tables_len);
+    }
+    start = acpi_tables_len;
+
+    len = sizeof(uint16_t) + ACPI_TABLE_HDR_SIZE;
+    acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len + len);
+    acpi_tables_len += sizeof(uint16_t);
+
+    if (!has_header)
+    {
+       memset(acpi_tables + acpi_tables_len, 0, ACPI_TABLE_HDR_SIZE);
+       acpi_tables_len += ACPI_TABLE_HDR_SIZE;
+    }
+
+    /* now read in the data files, reallocating buffer as needed */
+
+    for(f = strtok(buf, ":"); f; f = strtok(NULL, ":"))
+    {
+	int fd = open(f, O_RDONLY);
+
+        if(fd < 0)
+	{
+	    /*XXX fixme: report error */
+            goto out;
+	}
+
+	for(;;)
+        {
+            char data[8192];
+	    int r = read(fd, data, sizeof(data));
+	    if (r == 0)
+	    {
+	      break;
+	    }
+	    else if (r > 0)
+	    {
+		acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len + r);
+		memcpy(acpi_tables + acpi_tables_len, data, r);
+		acpi_tables_len += r;
+	    }
+	    else if (errno != EINTR)
+	    {
+		/*XXX fixme: report error */
+		close(fd);
+		goto out;
+	    }
+	}
+
+	close(fd);
+    }
+
+    /* fill in the complete length of the table */
+    len = acpi_tables_len - start - sizeof(uint16_t);
+    f = acpi_tables + start;
+    *(uint16_t*)f = cpu_to_le32(len);
+    f += sizeof(uint16_t);
+
+    /* now fill in the header fields */
+    changed = 0;
+
+    /* 0..3, signature, string (4 bytes) */
+    if (get_param_value(buf, sizeof(buf), "sig", t))
+    {
+        strncpy(f + 0, buf, 4);
+	++changed;
+    }
+    else if (!has_header)
+    {
+        strncpy(f + 0, dfl_id, 4);
+    }
+
+    /* 4..7, length of the table, in bytes, including header (4 bytes) */
+
+    /* 8, ACPI specification minor version #, 1 byte */
+    if (get_param_value(buf, sizeof(buf), "rev", t))
+    {
         val = strtoul(buf, &p, 10);
         if (val > 255 || *p != '\0')
-            goto out;
-    } else {
-        val = 1;
+            goto out;	/*XXX fixme: report error */
+	f[8] = (uint8_t)val;
+	++changed;
+    }
+    else if (!has_header)
+    {
+	f[8] = 1;
     }
-    acpi_hdr.revision = (int8_t)val;

-    if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
-        strncpy(acpi_hdr.oem_id, buf, 6);
-    } else {
-        strncpy(acpi_hdr.oem_id, dfl_id, 6);
+    /* 9, checksum of entire table (1 byte) */
+
+    /* 10..15 OEM identification (6 bytes) */
+    if (get_param_value(buf, sizeof(buf), "oem_id", t))
+    {
+        strncpy(f + 10, buf, 6);
+	++changed;
+    }
+    else if (!has_header)
+    {
+        strncpy(f + 10, dfl_id, 6);
     }

-    if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
-        strncpy(acpi_hdr.oem_table_id, buf, 8);
-    } else {
-        strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
+    /* 16..23 OEM table identifiaction, 8 bytes */
+    if (get_param_value(buf, sizeof(buf), "oem_table_id", t))
+    {
+        strncpy(f + 16, buf, 8);
+	++changed;
+    }
+    else if (!has_header)
+    {
+        strncpy(f + 16, dfl_id, 8);
     }

-    if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
+    /* 24..27 OEM revision number, 4 bytes */
+    if (get_param_value(buf, sizeof(buf), "oem_rev", t))
+    {
         val = strtol(buf, &p, 10);
         if(*p != '\0')
-            goto out;
-    } else {
-        val = 1;
+            goto out;	/*XXX fixme: report error */
+	*(uint32_t*)(f + 24) = cpu_to_le32(val);
+	++changed;
+    } else if (!has_header)
+    {
+	*(uint32_t*)(f + 24) = cpu_to_le32(1);
     }
-    acpi_hdr.oem_revision = cpu_to_le32(val);

-    if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
-        strncpy(acpi_hdr.asl_compiler_id, buf, 4);
-    } else {
-        strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
+    /* 28..31 ASL compiler vendor ID (4 bytes) */
+    if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t))
+    {
+        strncpy(f + 28, buf, 4);
+        ++changed;
+    }
+    else if (!has_header)
+    {
+        strncpy(f + 28, dfl_id, 4);
     }

-    if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
+    /* 32..35 ASL compiler revision number (4 bytes) */
+    if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t))
+    {
         val = strtol(buf, &p, 10);
         if(*p != '\0')
-            goto out;
-    } else {
-        val = 1;
+            goto out;	/*XXX fixme: report error */
+	*(uint32_t*)(f + 32) = cpu_to_le32(val);
+	++changed;
     }
-    acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
-
-    if (!get_param_value(buf, sizeof(buf), "data", t)) {
-         buf[0] = '\0';
+    else if (!has_header) {
+	*(uint32_t*)(f + 32) = cpu_to_le32(1);
     }

-    length = sizeof(acpi_hdr);
+    /* 4..7 length of the table including header, in bytes (4 bytes) */
+    if (!has_header)
+    {
+	if (!changed)
+	    fprintf(stderr,
+		"warning: acpi table specified with data="
+		" but no table headers are provided, defaults are used\n");
+    }
+    else
+    {
+	/* check if actual length is correct */
+	val = le32_to_cpu(*(uint32_t*)(f + 4));
+	if (val != len)
+	{
+	    fprintf(stderr,
+		"warning: acpi table specified with file= has wrong length,"
+		" header says %lu, actual size %u\n",
+		val, len);
+	    ++changed;
+	}
+    }

-    f = buf;
-    while (buf[0]) {
-        struct stat s;
-        char *n = strchr(f, ':');
-        if (n)
-            *n = '\0';
-        if(stat(f, &s) < 0) {
-            fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
-            goto out;
-        }
-        length += s.st_size;
-        if (!n)
-            break;
-        *n = ':';
-        f = n + 1;
-    }
-
-    if (!acpi_tables) {
-        acpi_tables_len = sizeof(uint16_t);
-        acpi_tables = qemu_mallocz(acpi_tables_len);
-    }
-    acpi_tables = qemu_realloc(acpi_tables,
-                               acpi_tables_len + sizeof(uint16_t) + length);
-    p = acpi_tables + acpi_tables_len;
-    acpi_tables_len += sizeof(uint16_t) + length;
-
-    *(uint16_t*)p = cpu_to_le32(length);
-    p += sizeof(uint16_t);
-    memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
-    off = sizeof(acpi_hdr);
-
-    f = buf;
-    while (buf[0]) {
-        struct stat s;
-        int fd;
-        char *n = strchr(f, ':');
-        if (n)
-            *n = '\0';
-        fd = open(f, O_RDONLY);
+    /* fix table length */
+    /* we may avoid putting length here if has_header is true */
+    *(uint32_t*)(f + 4) = cpu_to_le32(len);
+
+    /* 9 checksum (1 byte) */
+    /* we may as well leave checksum intact if has_header is true */
+    /* alternatively there may be a way to set cksum to a given value */
+    if (changed || !has_header || 1)
+    {
+	f[9] = 0;
+	f[9] = acpi_checksum((uint8_t*)f, len);
+    }

-        if(fd < 0)
-            goto out;
-        if(fstat(fd, &s) < 0) {
-            close(fd);
-            goto out;
-        }
-
-        /* off < length is necessary because file size can be changed
-           under our foot */
-        while(s.st_size && off < length) {
-            int r;
-            r = read(fd, p + off, s.st_size);
-            if (r > 0) {
-                off += r;
-                s.st_size -= r;
-            } else if ((r < 0 && errno != EINTR) || r == 0) {
-                close(fd);
-                goto out;
-            }
-        }
-
-        close(fd);
-        if (!n)
-            break;
-        f = n + 1;
-    }
-    if (off < length) {
-        /* don't pass random value in process to guest */
-        memset(p + off, 0, length - off);
-    }
-
-    acpi_hdr_p = (struct acpi_table_header*)p;
-    acpi_hdr_p->length = cpu_to_le32(length);
-    acpi_hdr_p->checksum = acpi_checksum((uint8_t*)p, length);
     /* increase number of tables */
     (*(uint16_t*)acpi_tables) =
 	    cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
     return 0;
+
 out:
-    if (acpi_tables) {
-        qemu_free(acpi_tables);
-        acpi_tables = NULL;
-    }
+    acpi_tables_len = start;
     return -1;
 }
diff --git a/qemu-options.hx b/qemu-options.hx
index 18f54d2..e1d26b4 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -995,12 +995,17 @@ Enable virtio balloon device (default), optionally with PCI address
 ETEXI

 DEF("acpitable", HAS_ARG, QEMU_OPTION_acpitable,
-    "-acpitable [sig=str][,rev=n][,oem_id=str][,oem_table_id=str][,oem_rev=n][,asl_compiler_id=str][,asl_compiler_rev=n][,data=file1[:file2]...]\n"
+    "-acpitable [sig=str][,rev=n][,oem_id=str][,oem_table_id=str][,oem_rev=n][,asl_compiler_id=str][,asl_compiler_rev=n][,{data|file}=file1[:file2]...]\n"
     "                ACPI table description\n", QEMU_ARCH_I386)
 STEXI
 @item -acpitable [sig=@var{str}][,rev=@var{n}][,oem_id=@var{str}][,oem_table_id=@var{str}][,oem_rev=@var{n}] [,asl_compiler_id=@var{str}][,asl_compiler_rev=@var{n}][,data=@var{file1}[:@var{file2}]...]
 @findex -acpitable
 Add ACPI table with specified header fields and context from specified files.
+For file=, take whole ACPI table from the specified files, including all
+ACPI headers (possible overridden by other options).
+For data=, only data
+portion of the table is used, all header information is specified in the
+command line.
 ETEXI

 DEF("smbios", HAS_ARG, QEMU_OPTION_smbios,

[Qemu-devel] Re: [PATCH 07/26] pci/p2pbr: generic pci p2p bridge

[Michael S. Tsirkin]

On Wed, Mar 16, 2011 at 06:29:18PM +0900, Isaku Yamahata wrote:
> Create generic pci p2p bridge device which can be customized
> via properties like vendor id/device id and so on.
> With this, we can avoid to create many pci p2p bridge which only
> differs in those ids.
> 
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>

So we added 213 lines and we saved all of 20 in other places?
Maybe I miss the point ...


> ---
>  Makefile.objs  |    2 +-
>  hw/pci_p2pbr.c |  151 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  hw/pci_p2pbr.h |   61 +++++++++++++++++++++++
>  3 files changed, 213 insertions(+), 1 deletions(-)
>  create mode 100644 hw/pci_p2pbr.c
>  create mode 100644 hw/pci_p2pbr.h

Re: [Qemu-devel] Re: [PATCH 07/26] pci/p2pbr: generic pci p2p bridge

[Isaku Yamahata]

On Wed, Mar 16, 2011 at 11:34:42PM +0200, Michael S. Tsirkin wrote:
> On Wed, Mar 16, 2011 at 06:29:18PM +0900, Isaku Yamahata wrote:
> > Create generic pci p2p bridge device which can be customized
> > via properties like vendor id/device id and so on.
> > With this, we can avoid to create many pci p2p bridge which only
> > differs in those ids.
> > 
> > Cc: Michael S. Tsirkin <mst@redhat.com>
> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> 
> So we added 213 lines and we saved all of 20 in other places?
> Maybe I miss the point ...

What are missing is,
- The patch eliminates logic duplication rather than simple
  line insertion/deletion.
- It also simplifies q35 code which is 26/26. Its code saving isn't counted.
- The lines of newly added copyright notice are counted.
- If line saving is so important, the numbers of lines can be
  reduced dramatically by accepting 14 arguments functions instead
  of using struct. struct initialization bloated line insertion.
  But I think it doesn't increase code complexity.

Anyway this patch isn't very critical. I think the available choice is

- this patch
- modify the patch to use 14 arguments function.
  Thus we can save much more lines.
- Add one more p2p bridge code which q35 uses, accepting same code which
  differs only in IDs.
- any other ideas?

Which option do you prefer?

> 
> 
> > ---
> >  Makefile.objs  |    2 +-
> >  hw/pci_p2pbr.c |  151 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> >  hw/pci_p2pbr.h |   61 +++++++++++++++++++++++
> >  3 files changed, 213 insertions(+), 1 deletions(-)
> >  create mode 100644 hw/pci_p2pbr.c
> >  create mode 100644 hw/pci_p2pbr.h
> 

-- 
yamahata

Re: [Qemu-devel] RFC: ACPI table loading

[Isaku Yamahata]

The behavior seems reasonable. So I cleaned it up for upstream merge.

thanks,

>From cd336e50ebda63ecd84f8172dcf4d4456059d615 Mon Sep 17 00:00:00 2001
Message-Id: <cd336e50ebda63ecd84f8172dcf4d4456059d615.1300332741.git.yamahata@valinux.co.jp>
From: Isaku Yamahata <yamahata@valinux.co.jp>
Date: Thu, 17 Mar 2011 12:28:52 +0900
Subject: [PATCH] acpi: rewamp acpitable parsing, and allow specifying complete file with headers

This patch almost rewrites acpi_table_add() function
(but still leaves it using old get_param_value() interface).
The result is that it's now possible to specify whole table
(together with a header) in an external file, instead of just
data portion, with a new file= parameter, but at the same time
it's still possible to specify header fields as before.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
Changes v2:
- rebased to 31d3c9b8c15d7b42f508d5fc2adc4abb7c732b70
- style fix
- eliminated unaligned access
- replace magic numbers with symbolic constants
- error report
---
 hw/acpi.c |  294 ++++++++++++++++++++++++++++++++++++++-----------------------
 1 files changed, 184 insertions(+), 110 deletions(-)

diff --git a/hw/acpi.c b/hw/acpi.c
index 8071e7b..b058e20 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -32,6 +32,30 @@ struct acpi_table_header
     uint32_t asl_compiler_revision; /* ASL compiler revision number */
 } __attribute__((packed));
 
+#define ACPI_TABLE_OFF(x)       (offsetof(struct acpi_table_header, x))
+#define ACPI_TABLE_SIZE(x)      (sizeof(((struct acpi_table_header*)0)->x))
+
+#define ACPI_TABLE_SIG_OFF              ACPI_TABLE_OFF(signature)
+#define ACPI_TABLE_SIG_SIZE             ACPI_TABLE_SIZE(signature)
+#define ACPI_TABLE_LEN_OFF              ACPI_TABLE_OFF(length)
+#define ACPI_TABLE_LEN_SIZE             ACPI_TABLE_SIZE(length)
+#define ACPI_TABLE_REV_OFF              ACPI_TABLE_OFF(revision)
+#define ACPI_TABLE_REV_SIZE             ACPI_TABLE_SIZE(revision)
+#define ACPI_TABLE_CSUM_OFF             ACPI_TABLE_OFF(checksum)
+#define ACPI_TABLE_CSUM_SIZE            ACPI_TABLE_SIZE(checksum)
+#define ACPI_TABLE_OEM_ID_OFF           ACPI_TABLE_OFF(oem_id)
+#define ACPI_TABLE_OEM_ID_SIZE          ACPI_TABLE_SIZE(oem_id)
+#define ACPI_TABLE_OEM_TABLE_ID_OFF     ACPI_TABLE_OFF(oem_table_id)
+#define ACPI_TABLE_OEM_TABLE_ID_SIZE    ACPI_TABLE_SIZE(oem_table_id)
+#define ACPI_TABLE_OEM_REV_OFF          ACPI_TABLE_OFF(oem_revision)
+#define ACPI_TABLE_OEM_REV_SIZE         ACPI_TABLE_SIZE(oem_revision)
+#define ACPI_TABLE_ASL_COMPILER_ID_OFF  ACPI_TABLE_OFF(asl_compiler_id)
+#define ACPI_TABLE_ASL_COMPILER_ID_SIZE ACPI_TABLE_SIZE(asl_compiler_id)
+#define ACPI_TABLE_ASL_COMPILER_REV_OFF ACPI_TABLE_OFF(asl_compiler_revision)
+#define ACPI_TABLE_ASL_COMPILER_REV_SIZE ACPI_TABLE_SIZE(asl_compiler_revision)
+
+#define ACPI_TABLE_HDR_SIZE sizeof(struct acpi_table_header)
+
 char *acpi_tables;
 size_t acpi_tables_len;
 
@@ -44,156 +68,206 @@ static int acpi_checksum(const uint8_t *data, int len)
     return (-sum) & 0xff;
 }
 
+/* XXX fixme: this function uses obsolete argument parsing interface */
 int acpi_table_add(const char *t)
 {
     static const char *dfl_id = "QEMUQEMU";
-    char buf[1024], *p, *f;
-    struct acpi_table_header acpi_hdr;
+    char buf[1024], *f, *p;
     unsigned long val;
-    uint32_t length;
-    struct acpi_table_header *acpi_hdr_p;
-    size_t off;
+    uint16_t val16;
+    uint32_t val32;
+    size_t len, start;
+    bool has_header;
+    int changed;
 
-    memset(&acpi_hdr, 0, sizeof(acpi_hdr));
-  
-    if (get_param_value(buf, sizeof(buf), "sig", t)) {
-        strncpy(acpi_hdr.signature, buf, 4);
+    if (get_param_value(buf, sizeof(buf), "data", t)) {
+        has_header = false;
+    } else if (get_param_value(buf, sizeof(buf), "file", t)) {
+        has_header = true;
     } else {
-        strncpy(acpi_hdr.signature, dfl_id, 4);
+        has_header = 0;
+        buf[0] = '\0';
+    }
+
+    if (!acpi_tables) {
+        acpi_tables_len = sizeof(uint16_t);
+        acpi_tables = qemu_mallocz(acpi_tables_len);
+    }
+    start = acpi_tables_len;
+
+    len = sizeof(uint16_t) + ACPI_TABLE_HDR_SIZE;
+    acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len + len);
+    acpi_tables_len += sizeof(uint16_t);
+
+    if (!has_header) {
+        memset(acpi_tables + acpi_tables_len, 0, ACPI_TABLE_HDR_SIZE);
+        acpi_tables_len += ACPI_TABLE_HDR_SIZE;
     }
+
+    /* now read in the data files, reallocating buffer as needed */
+    for(f = strtok(buf, ":"); f; f = strtok(NULL, ":")) {
+        int fd = open(f, O_RDONLY);
+        if(fd < 0) {
+            fprintf(stderr, "can't open file %s: %s\n", f, strerror(errno));
+            goto out;
+        }
+
+        for(;;) {
+            char data[8192];
+            ssize_t r = read(fd, data, sizeof(data));
+            if (r == 0) {
+                break;
+            } else if (r > 0) {
+                acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len + r);
+                memcpy(acpi_tables + acpi_tables_len, data, r);
+                acpi_tables_len += r;
+            } else if (errno != EINTR) {
+                fprintf(stderr, "can't read file %s: %s\n",
+                        f, strerror(errno));
+                close(fd);
+                goto out;
+            }
+        }
+
+        close(fd);
+    }
+
+    /* fill in the complete length of the table */
+    len = acpi_tables_len - start - sizeof(uint16_t);
+    f = acpi_tables + start;
+    val16 = cpu_to_le16(len);
+    memcpy(f, &val16, sizeof(uint16_t));
+    f += sizeof(uint16_t);
+
+    /* now fill in the header fields */
+    changed = 0;
+
+    /* 0..3, signature, string (4 bytes) */
+    if (get_param_value(buf, sizeof(buf), "sig", t)) {
+        strncpy(f + ACPI_TABLE_SIG_OFF, buf, ACPI_TABLE_SIG_SIZE);
+        ++changed;
+    } else if (!has_header) {
+        strncpy(f + ACPI_TABLE_SIG_OFF, dfl_id, ACPI_TABLE_SIG_SIZE);
+    }
+
+    /* 4..7, length of the table, in bytes, including header (4 bytes) */
+
+    /* 8, ACPI specification minor version #, 1 byte */
     if (get_param_value(buf, sizeof(buf), "rev", t)) {
         val = strtoul(buf, &p, 10);
-        if (val > 255 || *p != '\0')
+        if (val > 255 || *p != '\0') {
+            fprintf(stderr, "invalid acpi rev.\n");
             goto out;
-    } else {
-        val = 1;
+        }
+        f[ACPI_TABLE_REV_OFF] = (uint8_t)val;
+        ++changed;
+    } else if (!has_header) {
+        f[ACPI_TABLE_REV_OFF] = 1;
     }
-    acpi_hdr.revision = (int8_t)val;
 
+    /* 9, checksum of entire table (1 byte)
+       this will be processed after all the headers are modified */
+
+    /* 10..15 OEM identification (6 bytes) */
     if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
-        strncpy(acpi_hdr.oem_id, buf, 6);
-    } else {
-        strncpy(acpi_hdr.oem_id, dfl_id, 6);
+        strncpy(f + ACPI_TABLE_OEM_ID_OFF, buf, ACPI_TABLE_OEM_ID_SIZE);
+        ++changed;
+    } else if (!has_header) {
+        strncpy(f + ACPI_TABLE_OEM_ID_OFF, dfl_id, ACPI_TABLE_OEM_ID_SIZE);
     }
 
+    /* 16..23 OEM table identifiaction, 8 bytes */
     if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
-        strncpy(acpi_hdr.oem_table_id, buf, 8);
-    } else {
-        strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
+        strncpy(f + ACPI_TABLE_OEM_TABLE_ID_OFF, buf,
+                ACPI_TABLE_OEM_TABLE_ID_SIZE);
+        ++changed;
+    } else if (!has_header) {
+        strncpy(f + ACPI_TABLE_OEM_TABLE_ID_OFF, dfl_id,
+                ACPI_TABLE_OEM_TABLE_ID_SIZE);
     }
 
+    /* 24..27 OEM revision number, 4 bytes */
     if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
         val = strtol(buf, &p, 10);
-        if(*p != '\0')
+        if(*p != '\0') {
+            fprintf(stderr, "invalid acpi oem_rev.\n");
             goto out;
-    } else {
-        val = 1;
+        }
+        val32 = cpu_to_le32(val);
+        memcpy(f + ACPI_TABLE_OEM_REV_OFF, &val32, ACPI_TABLE_OEM_REV_SIZE);
+        ++changed;
+    } else if (!has_header) {
+        val32 = cpu_to_le32(1);
+        memcpy(f + ACPI_TABLE_OEM_REV_OFF, &val32, ACPI_TABLE_OEM_REV_SIZE);
     }
-    acpi_hdr.oem_revision = cpu_to_le32(val);
 
+    /* 28..31 ASL compiler vendor ID (4 bytes) */
     if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
-        strncpy(acpi_hdr.asl_compiler_id, buf, 4);
-    } else {
-        strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
+        strncpy(f + ACPI_TABLE_ASL_COMPILER_ID_OFF, buf,
+                ACPI_TABLE_ASL_COMPILER_ID_SIZE);
+        ++changed;
+    } else if (!has_header) {
+        strncpy(f + ACPI_TABLE_ASL_COMPILER_ID_OFF, dfl_id,
+                ACPI_TABLE_ASL_COMPILER_ID_SIZE);
     }
 
+    /* 32..35 ASL compiler revision number (4 bytes) */
     if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
         val = strtol(buf, &p, 10);
-        if(*p != '\0')
-            goto out;
-    } else {
-        val = 1;
-    }
-    acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
-    
-    if (!get_param_value(buf, sizeof(buf), "data", t)) {
-         buf[0] = '\0';
-    }
-
-    length = sizeof(acpi_hdr);
-
-    f = buf;
-    while (buf[0]) {
-        struct stat s;
-        char *n = strchr(f, ':');
-        if (n)
-            *n = '\0';
-        if(stat(f, &s) < 0) {
-            fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
+        if(*p != '\0') {
+            fprintf(stderr, "invalid acpi asl_compiler_rev.\n");
             goto out;
         }
-        length += s.st_size;
-        if (!n)
-            break;
-        *n = ':';
-        f = n + 1;
-    }
+        val32 = cpu_to_le32(val);
+        memcpy(f + ACPI_TABLE_ASL_COMPILER_REV_OFF, &val32,
+               ACPI_TABLE_ASL_COMPILER_REV_SIZE);
+        ++changed;
+    } else if (!has_header) {
+        val32 = cpu_to_le32(1);
+        memcpy(f + ACPI_TABLE_ASL_COMPILER_REV_OFF, &val32,
+               ACPI_TABLE_ASL_COMPILER_REV_SIZE);
 
-    if (!acpi_tables) {
-        acpi_tables_len = sizeof(uint16_t);
-        acpi_tables = qemu_mallocz(acpi_tables_len);
     }
-    acpi_tables = qemu_realloc(acpi_tables,
-                               acpi_tables_len + sizeof(uint16_t) + length);
-    p = acpi_tables + acpi_tables_len;
-    acpi_tables_len += sizeof(uint16_t) + length;
-
-    *(uint16_t*)p = cpu_to_le32(length);
-    p += sizeof(uint16_t);
-    memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
-    off = sizeof(acpi_hdr);
-
-    f = buf;
-    while (buf[0]) {
-        struct stat s;
-        int fd;
-        char *n = strchr(f, ':');
-        if (n)
-            *n = '\0';
-        fd = open(f, O_RDONLY);
-
-        if(fd < 0)
-            goto out;
-        if(fstat(fd, &s) < 0) {
-            close(fd);
-            goto out;
-        }
 
-        /* off < length is necessary because file size can be changed
-           under our foot */
-        while(s.st_size && off < length) {
-            int r;
-            r = read(fd, p + off, s.st_size);
-            if (r > 0) {
-                off += r;
-                s.st_size -= r;
-            } else if ((r < 0 && errno != EINTR) || r == 0) {
-                close(fd);
-                goto out;
-            }
+    /* 4..7 length of the table including header, in bytes (4 bytes) */
+    if (!has_header) {
+        if (!changed) {
+            fprintf(stderr,
+                    "warning: acpi table specified with data="
+                    " but no table headers are provided, defaults are used\n");
+        }
+    } else {
+        /* check if actual length is correct */
+        memcpy(&val32, f + ACPI_TABLE_LEN_OFF, ACPI_TABLE_LEN_SIZE);
+        val = le32_to_cpu(val32);
+        if (val != len) {
+            fprintf(stderr,
+                    "warning: acpi table specified with file= has wrong length,"
+                    " header says %lu, actual size %zu\n",
+                    val, len);
+            ++changed;
         }
-
-        close(fd);
-        if (!n)
-            break;
-        f = n + 1;
     }
-    if (off < length) {
-        /* don't pass random value in process to guest */
-        memset(p + off, 0, length - off);
+
+    /* fix table length */
+    /* we may avoid putting length here if has_header is true */
+    val32 = cpu_to_le32(len);
+    memcpy(f + ACPI_TABLE_LEN_OFF, &val32, ACPI_TABLE_LEN_SIZE);
+
+    /* 9 checksum (1 byte) */
+    /* we may as well leave checksum intact if has_header is true */
+    /* alternatively there may be a way to set cksum to a given value */
+    if (changed || !has_header || 1) {
+        f[ACPI_TABLE_CSUM_OFF] = 0;
+        f[ACPI_TABLE_CSUM_OFF] = acpi_checksum((uint8_t*)f, len);
     }
 
-    acpi_hdr_p = (struct acpi_table_header*)p;
-    acpi_hdr_p->length = cpu_to_le32(length);
-    acpi_hdr_p->checksum = acpi_checksum((uint8_t*)p, length);
     /* increase number of tables */
     (*(uint16_t*)acpi_tables) =
-	    cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
+        cpu_to_le16(le16_to_cpu(*(uint16_t*)acpi_tables) + 1);
     return 0;
+
 out:
-    if (acpi_tables) {
-        qemu_free(acpi_tables);
-        acpi_tables = NULL;
-    }
+    acpi_tables_len = start;
     return -1;
 }
-- 
1.7.1.1




On Wed, Mar 16, 2011 at 04:47:01PM +0300, Michael Tokarev wrote:
> 16.03.2011 15:10, Isaku Yamahata wrote:
> > On Wed, Mar 16, 2011 at 01:12:27PM +0300, Michael Tokarev wrote:
> >> 16.03.2011 12:29, Isaku Yamahata wrote:
> 
> >>> Example:
> >>> qemu-system-x86_64 ... -M pc_q35 -acpitable 'load_header,data=roms/seabios/src/q35-acpi-dsdt.aml
> >>
> >> My question is unrelated to your q35 work, but I have a suggestion
> >> here: can we avoid this "load_header" thing please?  I hacked this
> >> area locally a while back while trying to run OEM-licensed windows
> >> with a SLIC table in BIOS, and wanted to come with alternative
> >> approach.  Now when you reminded me that again I'd rather finish
> >> that old thing and post a real patch...
> >>
> >> Here's my "idea".  First, if there's no other options provided
> >> except of data=..., just treat it as "headerful", ie, complete with
> >> the header.  Or alternatively (or at the same time), recognize
> >> "file=" the same way as "data=".  We can go even further and load
> >> file/data first and patch in the other header field if specified,
> >> so it'll be possible to overwrite only certain parts of the header
> >> but load the rest of the table (complete with all other headers)
> >> from a file.
> >>
> >> Does it make sense?
> > 
> > It sounds reasonable. As long as the patch is acceptable,
> > I'm willing to update the patch.
> > Let me summarize it. Your suggestion for -acpitable is
> >   
> >                 existing behavior               your suggested way
> > data= only
> > no sig=,...     header is filled with zero      headerful
> >                 (headerless)                    (new behaviour)
> >                 useless behavior
> > 
> > with sig=...    header is created               header is created
> >                 (headerless)                    (headerless)
> 
> I just implemented the whole thing, and refined it at the same
> time.  With data= it works the same way as before, so no
> new behavour is introduced.  Only with file= it is possible
> to specify whole table (with header) in a file, but other
> header fields specified on the command line (sig= etc) will
> work still, replacing the corresponding fields in the header
> read from the file.
> 
> Something like the below, it's just an RFC, but it appears
> to work.
> 
> /mjt
> 
> Subject: rewamp acpitable parsing, and allow specifying complete file with headers
> 
> This patch almost rewrites acpi_table_add() function
> (but still leaves it using old get_param_value() interface).
> The result is that it's now possible to specify whole table
> (together with a header) in an external file, instead of just
> data portion, with a new file= parameter, but at the same time
> it's still possible to specify header fields as before.
> 
> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
> 
> diff --git a/hw/acpi.c b/hw/acpi.c
> index 237526d..d12527e 100644
> --- a/hw/acpi.c
> +++ b/hw/acpi.c
> @@ -22,18 +22,8 @@
>  #include "qemu-kvm.h"
>  #include "string.h"
> 
> -struct acpi_table_header
> -{
> -    char signature [4];    /* ACPI signature (4 ASCII characters) */
> -    uint32_t length;          /* Length of table, in bytes, including header */
> -    uint8_t revision;         /* ACPI Specification minor version # */
> -    uint8_t checksum;         /* To make sum of entire table == 0 */
> -    char oem_id [6];       /* OEM identification */
> -    char oem_table_id [8]; /* OEM table identification */
> -    uint32_t oem_revision;    /* OEM revision number */
> -    char asl_compiler_id [4]; /* ASL compiler vendor ID */
> -    uint32_t asl_compiler_revision; /* ASL compiler revision number */
> -} __attribute__((packed));
> +
> +#define ACPI_TABLE_HDR_SIZE (4+4+1+1+6+8+4+4+4)
> 
>  char *acpi_tables;
>  size_t acpi_tables_len;
> @@ -50,153 +40,220 @@ static int acpi_checksum(const uint8_t *data, int len)
>  int acpi_table_add(const char *t)
>  {
>      static const char *dfl_id = "QEMUQEMU";
> -    char buf[1024], *p, *f;
> -    struct acpi_table_header acpi_hdr;
> +    char buf[1024], *f, *p;
>      unsigned long val;
> -    uint32_t length;
> -    struct acpi_table_header *acpi_hdr_p;
> -    size_t off;
> -
> -    memset(&acpi_hdr, 0, sizeof(acpi_hdr));
> -
> -    if (get_param_value(buf, sizeof(buf), "sig", t)) {
> -        strncpy(acpi_hdr.signature, buf, 4);
> -    } else {
> -        strncpy(acpi_hdr.signature, dfl_id, 4);
> -    }
> -    if (get_param_value(buf, sizeof(buf), "rev", t)) {
> +    size_t len, start;
> +    bool has_header;
> +    int changed;
> +
> +    /*XXX fixme: this function uses obsolete argument parsing interface */
> +    /*XXX note: all 32bit accesses in there are misaligned */
> +
> +    if (get_param_value(buf, sizeof(buf), "data", t))
> +    {
> +	has_header = 0;
> +    }
> +    else if (get_param_value(buf, sizeof(buf), "file", t))
> +    {
> +	has_header = 1;
> +    }
> +    else {
> +	has_header = 0;
> +	buf[0] = '\0';
> +    }
> +
> +    if (!acpi_tables)
> +    {
> +	acpi_tables_len = sizeof(uint16_t);
> +	acpi_tables = qemu_mallocz(acpi_tables_len);
> +    }
> +    start = acpi_tables_len;
> +
> +    len = sizeof(uint16_t) + ACPI_TABLE_HDR_SIZE;
> +    acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len + len);
> +    acpi_tables_len += sizeof(uint16_t);
> +
> +    if (!has_header)
> +    {
> +       memset(acpi_tables + acpi_tables_len, 0, ACPI_TABLE_HDR_SIZE);
> +       acpi_tables_len += ACPI_TABLE_HDR_SIZE;
> +    }
> +
> +    /* now read in the data files, reallocating buffer as needed */
> +
> +    for(f = strtok(buf, ":"); f; f = strtok(NULL, ":"))
> +    {
> +	int fd = open(f, O_RDONLY);
> +
> +        if(fd < 0)
> +	{
> +	    /*XXX fixme: report error */
> +            goto out;
> +	}
> +
> +	for(;;)
> +        {
> +            char data[8192];
> +	    int r = read(fd, data, sizeof(data));
> +	    if (r == 0)
> +	    {
> +	      break;
> +	    }
> +	    else if (r > 0)
> +	    {
> +		acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len + r);
> +		memcpy(acpi_tables + acpi_tables_len, data, r);
> +		acpi_tables_len += r;
> +	    }
> +	    else if (errno != EINTR)
> +	    {
> +		/*XXX fixme: report error */
> +		close(fd);
> +		goto out;
> +	    }
> +	}
> +
> +	close(fd);
> +    }
> +
> +    /* fill in the complete length of the table */
> +    len = acpi_tables_len - start - sizeof(uint16_t);
> +    f = acpi_tables + start;
> +    *(uint16_t*)f = cpu_to_le32(len);
> +    f += sizeof(uint16_t);
> +
> +    /* now fill in the header fields */
> +    changed = 0;
> +
> +    /* 0..3, signature, string (4 bytes) */
> +    if (get_param_value(buf, sizeof(buf), "sig", t))
> +    {
> +        strncpy(f + 0, buf, 4);
> +	++changed;
> +    }
> +    else if (!has_header)
> +    {
> +        strncpy(f + 0, dfl_id, 4);
> +    }
> +
> +    /* 4..7, length of the table, in bytes, including header (4 bytes) */
> +
> +    /* 8, ACPI specification minor version #, 1 byte */
> +    if (get_param_value(buf, sizeof(buf), "rev", t))
> +    {
>          val = strtoul(buf, &p, 10);
>          if (val > 255 || *p != '\0')
> -            goto out;
> -    } else {
> -        val = 1;
> +            goto out;	/*XXX fixme: report error */
> +	f[8] = (uint8_t)val;
> +	++changed;
> +    }
> +    else if (!has_header)
> +    {
> +	f[8] = 1;
>      }
> -    acpi_hdr.revision = (int8_t)val;
> 
> -    if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
> -        strncpy(acpi_hdr.oem_id, buf, 6);
> -    } else {
> -        strncpy(acpi_hdr.oem_id, dfl_id, 6);
> +    /* 9, checksum of entire table (1 byte) */
> +
> +    /* 10..15 OEM identification (6 bytes) */
> +    if (get_param_value(buf, sizeof(buf), "oem_id", t))
> +    {
> +        strncpy(f + 10, buf, 6);
> +	++changed;
> +    }
> +    else if (!has_header)
> +    {
> +        strncpy(f + 10, dfl_id, 6);
>      }
> 
> -    if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
> -        strncpy(acpi_hdr.oem_table_id, buf, 8);
> -    } else {
> -        strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
> +    /* 16..23 OEM table identifiaction, 8 bytes */
> +    if (get_param_value(buf, sizeof(buf), "oem_table_id", t))
> +    {
> +        strncpy(f + 16, buf, 8);
> +	++changed;
> +    }
> +    else if (!has_header)
> +    {
> +        strncpy(f + 16, dfl_id, 8);
>      }
> 
> -    if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
> +    /* 24..27 OEM revision number, 4 bytes */
> +    if (get_param_value(buf, sizeof(buf), "oem_rev", t))
> +    {
>          val = strtol(buf, &p, 10);
>          if(*p != '\0')
> -            goto out;
> -    } else {
> -        val = 1;
> +            goto out;	/*XXX fixme: report error */
> +	*(uint32_t*)(f + 24) = cpu_to_le32(val);
> +	++changed;
> +    } else if (!has_header)
> +    {
> +	*(uint32_t*)(f + 24) = cpu_to_le32(1);
>      }
> -    acpi_hdr.oem_revision = cpu_to_le32(val);
> 
> -    if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
> -        strncpy(acpi_hdr.asl_compiler_id, buf, 4);
> -    } else {
> -        strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
> +    /* 28..31 ASL compiler vendor ID (4 bytes) */
> +    if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t))
> +    {
> +        strncpy(f + 28, buf, 4);
> +        ++changed;
> +    }
> +    else if (!has_header)
> +    {
> +        strncpy(f + 28, dfl_id, 4);
>      }
> 
> -    if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
> +    /* 32..35 ASL compiler revision number (4 bytes) */
> +    if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t))
> +    {
>          val = strtol(buf, &p, 10);
>          if(*p != '\0')
> -            goto out;
> -    } else {
> -        val = 1;
> +            goto out;	/*XXX fixme: report error */
> +	*(uint32_t*)(f + 32) = cpu_to_le32(val);
> +	++changed;
>      }
> -    acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
> -
> -    if (!get_param_value(buf, sizeof(buf), "data", t)) {
> -         buf[0] = '\0';
> +    else if (!has_header) {
> +	*(uint32_t*)(f + 32) = cpu_to_le32(1);
>      }
> 
> -    length = sizeof(acpi_hdr);
> +    /* 4..7 length of the table including header, in bytes (4 bytes) */
> +    if (!has_header)
> +    {
> +	if (!changed)
> +	    fprintf(stderr,
> +		"warning: acpi table specified with data="
> +		" but no table headers are provided, defaults are used\n");
> +    }
> +    else
> +    {
> +	/* check if actual length is correct */
> +	val = le32_to_cpu(*(uint32_t*)(f + 4));
> +	if (val != len)
> +	{
> +	    fprintf(stderr,
> +		"warning: acpi table specified with file= has wrong length,"
> +		" header says %lu, actual size %u\n",
> +		val, len);
> +	    ++changed;
> +	}
> +    }
> 
> -    f = buf;
> -    while (buf[0]) {
> -        struct stat s;
> -        char *n = strchr(f, ':');
> -        if (n)
> -            *n = '\0';
> -        if(stat(f, &s) < 0) {
> -            fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
> -            goto out;
> -        }
> -        length += s.st_size;
> -        if (!n)
> -            break;
> -        *n = ':';
> -        f = n + 1;
> -    }
> -
> -    if (!acpi_tables) {
> -        acpi_tables_len = sizeof(uint16_t);
> -        acpi_tables = qemu_mallocz(acpi_tables_len);
> -    }
> -    acpi_tables = qemu_realloc(acpi_tables,
> -                               acpi_tables_len + sizeof(uint16_t) + length);
> -    p = acpi_tables + acpi_tables_len;
> -    acpi_tables_len += sizeof(uint16_t) + length;
> -
> -    *(uint16_t*)p = cpu_to_le32(length);
> -    p += sizeof(uint16_t);
> -    memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
> -    off = sizeof(acpi_hdr);
> -
> -    f = buf;
> -    while (buf[0]) {
> -        struct stat s;
> -        int fd;
> -        char *n = strchr(f, ':');
> -        if (n)
> -            *n = '\0';
> -        fd = open(f, O_RDONLY);
> +    /* fix table length */
> +    /* we may avoid putting length here if has_header is true */
> +    *(uint32_t*)(f + 4) = cpu_to_le32(len);
> +
> +    /* 9 checksum (1 byte) */
> +    /* we may as well leave checksum intact if has_header is true */
> +    /* alternatively there may be a way to set cksum to a given value */
> +    if (changed || !has_header || 1)
> +    {
> +	f[9] = 0;
> +	f[9] = acpi_checksum((uint8_t*)f, len);
> +    }
> 
> -        if(fd < 0)
> -            goto out;
> -        if(fstat(fd, &s) < 0) {
> -            close(fd);
> -            goto out;
> -        }
> -
> -        /* off < length is necessary because file size can be changed
> -           under our foot */
> -        while(s.st_size && off < length) {
> -            int r;
> -            r = read(fd, p + off, s.st_size);
> -            if (r > 0) {
> -                off += r;
> -                s.st_size -= r;
> -            } else if ((r < 0 && errno != EINTR) || r == 0) {
> -                close(fd);
> -                goto out;
> -            }
> -        }
> -
> -        close(fd);
> -        if (!n)
> -            break;
> -        f = n + 1;
> -    }
> -    if (off < length) {
> -        /* don't pass random value in process to guest */
> -        memset(p + off, 0, length - off);
> -    }
> -
> -    acpi_hdr_p = (struct acpi_table_header*)p;
> -    acpi_hdr_p->length = cpu_to_le32(length);
> -    acpi_hdr_p->checksum = acpi_checksum((uint8_t*)p, length);
>      /* increase number of tables */
>      (*(uint16_t*)acpi_tables) =
>  	    cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
>      return 0;
> +
>  out:
> -    if (acpi_tables) {
> -        qemu_free(acpi_tables);
> -        acpi_tables = NULL;
> -    }
> +    acpi_tables_len = start;
>      return -1;
>  }
> diff --git a/qemu-options.hx b/qemu-options.hx
> index 18f54d2..e1d26b4 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx
> @@ -995,12 +995,17 @@ Enable virtio balloon device (default), optionally with PCI address
>  ETEXI
> 
>  DEF("acpitable", HAS_ARG, QEMU_OPTION_acpitable,
> -    "-acpitable [sig=str][,rev=n][,oem_id=str][,oem_table_id=str][,oem_rev=n][,asl_compiler_id=str][,asl_compiler_rev=n][,data=file1[:file2]...]\n"
> +    "-acpitable [sig=str][,rev=n][,oem_id=str][,oem_table_id=str][,oem_rev=n][,asl_compiler_id=str][,asl_compiler_rev=n][,{data|file}=file1[:file2]...]\n"
>      "                ACPI table description\n", QEMU_ARCH_I386)
>  STEXI
>  @item -acpitable [sig=@var{str}][,rev=@var{n}][,oem_id=@var{str}][,oem_table_id=@var{str}][,oem_rev=@var{n}] [,asl_compiler_id=@var{str}][,asl_compiler_rev=@var{n}][,data=@var{file1}[:@var{file2}]...]
>  @findex -acpitable
>  Add ACPI table with specified header fields and context from specified files.
> +For file=, take whole ACPI table from the specified files, including all
> +ACPI headers (possible overridden by other options).
> +For data=, only data
> +portion of the table is used, all header information is specified in the
> +command line.
>  ETEXI
> 
>  DEF("smbios", HAS_ARG, QEMU_OPTION_smbios,
> 

-- 
yamahata

Re: [Qemu-devel] Re: [PATCH 07/26] pci/p2pbr: generic pci p2p bridge

[Michael S. Tsirkin]

On Thu, Mar 17, 2011 at 11:08:51AM +0900, Isaku Yamahata wrote:
> On Wed, Mar 16, 2011 at 11:34:42PM +0200, Michael S. Tsirkin wrote:
> > On Wed, Mar 16, 2011 at 06:29:18PM +0900, Isaku Yamahata wrote:
> > > Create generic pci p2p bridge device which can be customized
> > > via properties like vendor id/device id and so on.
> > > With this, we can avoid to create many pci p2p bridge which only
> > > differs in those ids.
> > > 
> > > Cc: Michael S. Tsirkin <mst@redhat.com>
> > > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> > 
> > So we added 213 lines and we saved all of 20 in other places?
> > Maybe I miss the point ...
> 
> What are missing is,
> - The patch eliminates logic duplication rather than simple
>   line insertion/deletion.
> - It also simplifies q35 code which is 26/26. Its code saving isn't counted.
> - The lines of newly added copyright notice are counted.
> - If line saving is so important, the numbers of lines can be
>   reduced dramatically by accepting 14 arguments functions instead
>   of using struct. struct initialization bloated line insertion.
>   But I think it doesn't increase code complexity.
> 

But doesn't seem to reduce it either.
Line count is just an attempt to see how well the abstraction works.
All this one does is move from pci_config_set_vendor_id(dev, XXX) to
.vendor_id = XXX. This just does not seem to be a big win.

qdev properties are also user-visible, aren't they? Adding properties
that, if changed, will confuse the guest doesn't seem to be a good idea
either.

> Anyway this patch isn't very critical. I think the available choice is
> 
> - this patch
> - modify the patch to use 14 arguments function.
>   Thus we can save much more lines.
> - Add one more p2p bridge code which q35 uses, accepting same code which
>   differs only in IDs.
> - any other ideas?
> 
> Which option do you prefer?

Add one more bridge for q35.

> > 
> > 
> > > ---
> > >  Makefile.objs  |    2 +-
> > >  hw/pci_p2pbr.c |  151 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > >  hw/pci_p2pbr.h |   61 +++++++++++++++++++++++
> > >  3 files changed, 213 insertions(+), 1 deletions(-)
> > >  create mode 100644 hw/pci_p2pbr.c
> > >  create mode 100644 hw/pci_p2pbr.h
> > 
> 
> -- 
> yamahata

Re: [Qemu-devel] Re: [PATCH 07/26] pci/p2pbr: generic pci p2p bridge

[Isaku Yamahata]

On Thu, Mar 17, 2011 at 07:17:18AM +0200, Michael S. Tsirkin wrote:
> > Anyway this patch isn't very critical. I think the available choice is
> > 
> > - this patch
> > - modify the patch to use 14 arguments function.
> >   Thus we can save much more lines.
> > - Add one more p2p bridge code which q35 uses, accepting same code which
> >   differs only in IDs.
> > - any other ideas?
> > 
> > Which option do you prefer?
> 
> Add one more bridge for q35.

Okay.
How about other pci related patches? I think they are trivial.
-- 
yamahata

[Qemu-devel] Re: [PATCH 04/26] pci: add accessor function to get irq levels

[Michael S. Tsirkin]

On Wed, Mar 16, 2011 at 06:29:15PM +0900, Isaku Yamahata wrote:
> Introduce accessor function to know INTx levels.
> It will be used later by q35.
> Although piix_pci tracks the intx line levels, it can be eliminated
> by this helper function.

At least for piix, the right thing to IMO is to have bit per
IRQ, then the for loop can be replaced with a single !!.  There's a TODO
there which this will fix.  I think we can reuse pci device irq_state
for this: need to check. Haven't looked at q35 yet - applies there as
well?

> 
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> ---
>  hw/pci.c |    7 +++++++
>  hw/pci.h |    1 +
>  2 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/hw/pci.c b/hw/pci.c
> index d6c5e66..67cb3d7 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -126,6 +126,13 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
>      bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
>  }
>  
> +int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
> +{
> +    assert(irq_num >= 0);
> +    assert(irq_num < bus->nirq);
> +    return !!bus->irq_count[irq_num];
> +}
> +
>  /* Update interrupt status bit in config space on interrupt
>   * state change. */
>  static void pci_update_irq_status(PCIDevice *dev)
> diff --git a/hw/pci.h b/hw/pci.h
> index 46b3ad3..f523722 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -234,6 +234,7 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
>  PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
>  void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
>                    void *irq_opaque, int nirq);
> +int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
>  void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
>  /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
>  int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin);
> -- 
> 1.7.1.1

Re: [Qemu-devel] Re: [PATCH 07/26] pci/p2pbr: generic pci p2p bridge

[Michael S. Tsirkin]

On Thu, Mar 17, 2011 at 02:26:24PM +0900, Isaku Yamahata wrote:
> On Thu, Mar 17, 2011 at 07:17:18AM +0200, Michael S. Tsirkin wrote:
> > > Anyway this patch isn't very critical. I think the available choice is
> > > 
> > > - this patch
> > > - modify the patch to use 14 arguments function.
> > >   Thus we can save much more lines.
> > > - Add one more p2p bridge code which q35 uses, accepting same code which
> > >   differs only in IDs.
> > > - any other ideas?
> > > 
> > > Which option do you prefer?
> > 
> > Add one more bridge for q35.
> 
> Okay.
> How about other pci related patches? I think they are trivial.

I'll look at the usage to see how good new APIs are.

> -- 
> yamahata

[Qemu-devel] Re: [PATCH 02/26] pci: add opaque argument to pci_map_irq_fn

[Michael S. Tsirkin]

On Wed, Mar 16, 2011 at 06:29:13PM +0900, Isaku Yamahata wrote:
> Pass opaque argument to pci_map_irq_fn like pci_set_irq_fn.
> ICH9 irq routing is not static, but configurable by chipset configuration
> registers, so the corresponding irq mapping function of pci_map_irq_fn
> needs to know the pointer to ich9.
> 
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>

Not an objection to this patch - just thinking aloud: as mapping changes
rarely, something I wanted to do for a while now is replace
the walk up the bus with indirect function calls
at each step on each set_irq call with:
- walk down the bus on each mapping change, update all devices
- pci_set_irq which is not indirect, just calls directly to
  the interrupt controller

But we can do this optimization later.

> ---
>  hw/apb_pci.c       |    4 ++--
>  hw/bonito.c        |    2 +-
>  hw/dec_pci.c       |    2 +-
>  hw/grackle_pci.c   |    2 +-
>  hw/gt64xxx.c       |    2 +-
>  hw/pci.c           |    2 +-
>  hw/pci.h           |    2 +-
>  hw/piix_pci.c      |    2 +-
>  hw/ppc4xx_pci.c    |    2 +-
>  hw/ppce500_pci.c   |    2 +-
>  hw/prep_pci.c      |    2 +-
>  hw/sh_pci.c        |    2 +-
>  hw/unin_pci.c      |    2 +-
>  hw/versatile_pci.c |    2 +-
>  14 files changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/hw/apb_pci.c b/hw/apb_pci.c
> index 84e9af7..c56ea9a 100644
> --- a/hw/apb_pci.c
> +++ b/hw/apb_pci.c
> @@ -264,12 +264,12 @@ static CPUReadMemoryFunc * const pci_apb_ioread[] = {
>  };
>  
>  /* The APB host has an IRQ line for each IRQ line of each slot.  */
> -static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int pci_apb_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
>  }
>  
> -static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int pci_pbm_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      int bus_offset;
>      if (pci_dev->devfn & 1)
> diff --git a/hw/bonito.c b/hw/bonito.c
> index 65a4a63..94e69f5 100644
> --- a/hw/bonito.c
> +++ b/hw/bonito.c
> @@ -632,7 +632,7 @@ static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
>  }
>  
>  /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
> -static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
> +static int pci_bonito_map_irq(void *opaque, PCIDevice * pci_dev, int irq_num)
>  {
>      int slot;
>  
> diff --git a/hw/dec_pci.c b/hw/dec_pci.c
> index bf88f2a..3cc4f04 100644
> --- a/hw/dec_pci.c
> +++ b/hw/dec_pci.c
> @@ -45,7 +45,7 @@ typedef struct DECState {
>      PCIHostState host_state;
>  } DECState;
>  
> -static int dec_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int dec_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      return irq_num;
>  }
> diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
> index d35701f..4ed1ec6 100644
> --- a/hw/grackle_pci.c
> +++ b/hw/grackle_pci.c
> @@ -44,7 +44,7 @@ typedef struct GrackleState {
>  } GrackleState;
>  
>  /* Don't know if this matches real hardware, but it agrees with OHW.  */
> -static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int pci_grackle_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      return (irq_num + (pci_dev->devfn >> 3)) & 3;
>  }
> diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
> index c66188f..e6e2828 100644
> --- a/hw/gt64xxx.c
> +++ b/hw/gt64xxx.c
> @@ -862,7 +862,7 @@ static CPUReadMemoryFunc * const gt64120_read[] = {
>      &gt64120_readl,
>  };
>  
> -static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int gt64120_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      int slot;
>  
> diff --git a/hw/pci.c b/hw/pci.c
> index 8d7bfff..5349488 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -117,7 +117,7 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
>      PCIBus *bus;
>      for (;;) {
>          bus = pci_dev->bus;
> -        irq_num = bus->map_irq(pci_dev, irq_num);
> +        irq_num = bus->map_irq(bus->irq_opaque, pci_dev, irq_num);
>          if (bus->set_irq)
>              break;
>          pci_dev = bus->parent_dev;
> diff --git a/hw/pci.h b/hw/pci.h
> index 7d56337..1a08139 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -219,7 +219,7 @@ void pci_device_save(PCIDevice *s, QEMUFile *f);
>  int pci_device_load(PCIDevice *s, QEMUFile *f);
>  
>  typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
> -typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
> +typedef int (*pci_map_irq_fn)(void *opaque, PCIDevice *pci_dev, int irq_num);
>  
>  typedef enum {
>      PCI_HOTPLUG_DISABLED,
> diff --git a/hw/piix_pci.c b/hw/piix_pci.c
> index 358da58..892c576 100644
> --- a/hw/piix_pci.c
> +++ b/hw/piix_pci.c
> @@ -60,7 +60,7 @@ static void piix3_set_irq(void *opaque, int irq_num, int level);
>  /* return the global irq number corresponding to a given device irq
>     pin. We could also use the bus number to have a more precise
>     mapping. */
> -static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
> +static int pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      int slot_addend;
>      slot_addend = (pci_dev->devfn >> 3) - 1;
> diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
> index f62f1f9..11ca763 100644
> --- a/hw/ppc4xx_pci.c
> +++ b/hw/ppc4xx_pci.c
> @@ -267,7 +267,7 @@ static void ppc4xx_pci_reset(void *opaque)
>  
>  /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
>   * may need further refactoring for other boards. */
> -static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int ppc4xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      int slot = pci_dev->devfn >> 3;
>  
> diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
> index 11edd03..029a3f9 100644
> --- a/hw/ppce500_pci.c
> +++ b/hw/ppce500_pci.c
> @@ -187,7 +187,7 @@ static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
>      &pci_reg_write4,
>  };
>  
> -static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int mpc85xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      int devno = pci_dev->devfn >> 3, ret = 0;
>  
> diff --git a/hw/prep_pci.c b/hw/prep_pci.c
> index f88b825..8287246 100644
> --- a/hw/prep_pci.c
> +++ b/hw/prep_pci.c
> @@ -98,7 +98,7 @@ static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
>      &PPC_PCIIO_readl,
>  };
>  
> -static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int prep_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      return (irq_num + (pci_dev->devfn >> 3)) & 1;
>  }
> diff --git a/hw/sh_pci.c b/hw/sh_pci.c
> index e99d8db..f108759 100644
> --- a/hw/sh_pci.c
> +++ b/hw/sh_pci.c
> @@ -93,7 +93,7 @@ static MemOp sh_pci_reg = {
>      { NULL, NULL, sh_pci_reg_write },
>  };
>  
> -static int sh_pci_map_irq(PCIDevice *d, int irq_num)
> +static int sh_pci_map_irq(void *opaque, PCIDevice *d, int irq_num)
>  {
>      return (d->devfn >> 3);
>  }
> diff --git a/hw/unin_pci.c b/hw/unin_pci.c
> index c57c0a1..1496625 100644
> --- a/hw/unin_pci.c
> +++ b/hw/unin_pci.c
> @@ -44,7 +44,7 @@ typedef struct UNINState {
>      ReadWriteHandler data_handler;
>  } UNINState;
>  
> -static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
> +static int pci_unin_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>  {
>      int retval;
>      int devfn = pci_dev->devfn & 0x00FFFFFF;
> diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
> index 2fed8a0..c002fb2 100644
> --- a/hw/versatile_pci.c
> +++ b/hw/versatile_pci.c
> @@ -74,7 +74,7 @@ static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
>      &pci_vpb_config_readl,
>  };
>  
> -static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
> +static int pci_vpb_map_irq(void *opaque, PCIDevice *d, int irq_num)
>  {
>      return irq_num;
>  }
> -- 
> 1.7.1.1

[Qemu-devel] Re: [PATCH 04/26] pci: add accessor function to get irq levels

[Isaku Yamahata]

On Thu, Mar 17, 2011 at 07:29:09AM +0200, Michael S. Tsirkin wrote:
> On Wed, Mar 16, 2011 at 06:29:15PM +0900, Isaku Yamahata wrote:
> > Introduce accessor function to know INTx levels.
> > It will be used later by q35.
> > Although piix_pci tracks the intx line levels, it can be eliminated
> > by this helper function.
> 
> At least for piix, the right thing to IMO is to have bit per
> IRQ, then the for loop can be replaced with a single !!.  There's a TODO
> there which this will fix.  I think we can reuse pci device irq_state
> for this: need to check. Haven't looked at q35 yet - applies there as
> well?

Yes, such bitmap optimization is possible.
But this accessor function is still necessary,
please see the following. (I didn't do any test yet. Just to show the idea)
If you like it, I'll post it as separate patch.

diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 151353c..82b7daf 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -40,6 +40,7 @@ typedef PCIHostState I440FXState;
 
 typedef struct PIIX3State {
     PCIDevice dev;
+    unsigned long irq_level[16];
     int32_t dummy_for_save_load_compat[4];
     qemu_irq *pic;
 } PIIX3State;
@@ -200,25 +201,51 @@ PCIBus *i440fx_init(int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
 }
 
 /* PIIX3 PCI to ISA bridge */
-
 static void piix3_set_irq(void *opaque, int irq_num, int level)
 {
     int i, pic_irq, pic_level;
     PIIX3State *piix3 = opaque;
 
-    /* now we change the pic irq level according to the piix irq mappings */
-    /* XXX: optimize */
     pic_irq = piix3->dev.config[0x60 + irq_num];
-    if (pic_irq < 16) {
-        /* The pic level is the logical OR of all the PCI irqs mapped
-           to it */
-        pic_level = 0;
-        for (i = 0; i < 4; i++) {
-            if (pic_irq == piix3->dev.config[0x60 + i]) {
-                pic_level |= pci_bus_get_irq_level(piix3->dev.bus, i);
-            }
+    if (pic_irq >= 16) {
+        return;
+    }
+
+    /* The pic level is the logical OR of all the PCI irqs mapped to it */
+    if (level) {
+        set_bit(&piix3->irq_level[pic_irq], irq_num);
+    } else {
+        clear_bit(&piix3->irq_level[pic_irq], irq_num);
+    }
+    qemu_set_irq(piix3->pic[pic_irq], !!piix3->irq_level[pic_irq]);
+}
+
+/* irq routing is changed. so rebuild bitmap */
+static void piix3_update_irq_levels(PIIX3State *piix3)
+{
+    int i;
+    for (i = 0; i < 16; i++) {
+        piix3->irq_level[i] = 0;
+    }
+    for (i = 0; i < 4; i++) {
+        int pic_irq = piix3->dev.config[0x60 + irq_num];
+        if (pic_irq >= 16) {
+            continue;
+        }
+        if (pci_bus_get_irq_level(piix3->dev.bus, i)) {
+            set_bit(&piix3->irq_level[pic_irq], i);
         }
-        qemu_set_irq(piix3->pic[pic_irq], pic_level);
+    }
+}
+
+static void piix3_write_config(PCIDevice *dev,
+                               uint32_t address, uint32_t val, int len)
+{
+    PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
+
+    pci_default_write_config(dev, address, val, len);
+    if (ranges_overlap(address, len, 0x60, 4)) {
+        piix3_update_irq_levels(piix3);
     }
 }
 
@@ -318,6 +345,7 @@ static PCIDeviceInfo i440fx_info[] = {
         .qdev.no_user = 1,
         .no_hotplug   = 1,
         .init         = piix3_initfn,
+        .config_write = piix3_write_config,
     },{
         /* end of list */
     }

-- 
yamahata

[Qemu-devel] Re: [PATCH 04/26] pci: add accessor function to get irq levels

[Michael S. Tsirkin]

On Thu, Mar 17, 2011 at 03:05:00PM +0900, Isaku Yamahata wrote:
> On Thu, Mar 17, 2011 at 07:29:09AM +0200, Michael S. Tsirkin wrote:
> > On Wed, Mar 16, 2011 at 06:29:15PM +0900, Isaku Yamahata wrote:
> > > Introduce accessor function to know INTx levels.
> > > It will be used later by q35.
> > > Although piix_pci tracks the intx line levels, it can be eliminated
> > > by this helper function.
> > 
> > At least for piix, the right thing to IMO is to have bit per
> > IRQ, then the for loop can be replaced with a single !!.  There's a TODO
> > there which this will fix.  I think we can reuse pci device irq_state
> > for this: need to check. Haven't looked at q35 yet - applies there as
> > well?
> 
> Yes, such bitmap optimization is possible.
> But this accessor function is still necessary,

OK, I'm convinced. It makes sense off data path,
much easier than try to unswizzle and swizzle back
to the new values.

> please see the following. (I didn't do any test yet. Just to show the idea)
> If you like it, I'll post it as separate patch.

Yes. BTW as long as we touch it, we might want some symbolic
name for constants 0x60, 16, and use PCI_NUM_PINS instead of 4.
Some more suggestions below.

Also, save/restore needs to be updated.

> diff --git a/hw/piix_pci.c b/hw/piix_pci.c
> index 151353c..82b7daf 100644
> --- a/hw/piix_pci.c
> +++ b/hw/piix_pci.c
> @@ -40,6 +40,7 @@ typedef PCIHostState I440FXState;
>  
>  typedef struct PIIX3State {
>      PCIDevice dev;
> +    unsigned long irq_level[16];

That's 1024 bits. We really only need 4*16 = 64 bits.
Also pic_levels might be a better name.
So just
   uint64_t pic_levels;

Maybe stick a check there:
#if PCI_NUM_PINS * PIIX_NUM_PIC_IRQS > 64
#error unable to encode pic state in 64 bit in pic_levels
#endif
Also, need to clear on init?

>      int32_t dummy_for_save_load_compat[4];
>      qemu_irq *pic;
>  } PIIX3State;
> @@ -200,25 +201,51 @@ PCIBus *i440fx_init(int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
>  }
>  
>  /* PIIX3 PCI to ISA bridge */
> -
>  static void piix3_set_irq(void *opaque, int irq_num, int level)
>  {
>      int i, pic_irq, pic_level;
>      PIIX3State *piix3 = opaque;
>  
> -    /* now we change the pic irq level according to the piix irq mappings */
> -    /* XXX: optimize */
>      pic_irq = piix3->dev.config[0x60 + irq_num];
> -    if (pic_irq < 16) {
> -        /* The pic level is the logical OR of all the PCI irqs mapped
> -           to it */
> -        pic_level = 0;
> -        for (i = 0; i < 4; i++) {
> -            if (pic_irq == piix3->dev.config[0x60 + i]) {
> -                pic_level |= pci_bus_get_irq_level(piix3->dev.bus, i);
> -            }
> +    if (pic_irq >= 16) {
> +        return;
> +    }
> +
> +    /* The pic level is the logical OR of all the PCI irqs mapped to it */
> +    if (level) {
> +        set_bit(&piix3->irq_level[pic_irq], irq_num);
> +    } else {
> +        clear_bit(&piix3->irq_level[pic_irq], irq_num);
> +    }

We can do this without a branch too I think (assuming uint64_t suggested
above):
	mask = 0x1ull << (pic_irq * 16 + irq_num);
	piix3->pic_levels &= ~mask;
	piix3->pic_levels |= mask;

> +    qemu_set_irq(piix3->pic[pic_irq], !!piix3->irq_level[pic_irq]);
> +}
> +
> +/* irq routing is changed. so rebuild bitmap */
> +static void piix3_update_irq_levels(PIIX3State *piix3)
> +{
> +    int i;
> +    for (i = 0; i < 16; i++) {
> +        piix3->irq_level[i] = 0;
> +    }

memset(piix3->irq_level, 0, sizeof piix3->irq_level);

> +    for (i = 0; i < 4; i++) {
> +        int pic_irq = piix3->dev.config[0x60 + irq_num];
> +        if (pic_irq >= 16) {
> +            continue;
> +        }
> +        if (pci_bus_get_irq_level(piix3->dev.bus, i)) {
> +            set_bit(&piix3->irq_level[pic_irq], i);
>          }
> -        qemu_set_irq(piix3->pic[pic_irq], pic_level);

Hmm, don't we need to set the levels in guest appropriately?

There's also some duplication here.
Can't we just do
	for (i = 0; i < 4; i++) {
		piix3_set_irq(piix3, i, pci_bus_get_irq_level(piix3->dev.bus, i));
	}
?

> +    }
> +}
> +
> +static void piix3_write_config(PCIDevice *dev,
> +                               uint32_t address, uint32_t val, int len)
> +{
> +    PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
> +
> +    pci_default_write_config(dev, address, val, len);
> +    if (ranges_overlap(address, len, 0x60, 4)) {
> +        piix3_update_irq_levels(piix3);
>      }
>  }
>  
> @@ -318,6 +345,7 @@ static PCIDeviceInfo i440fx_info[] = {
>          .qdev.no_user = 1,
>          .no_hotplug   = 1,
>          .init         = piix3_initfn,
> +        .config_write = piix3_write_config,
>      },{
>          /* end of list */
>      }
> 
> -- 
> yamahata

[Qemu-devel] Re: [PATCH 03/26] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle

[Michael S. Tsirkin]

On Wed, Mar 16, 2011 at 06:29:14PM +0900, Isaku Yamahata wrote:
> introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
> standardized. PCI bridge swizzle is common logic, by introducing
> this function duplicated swizzle logic will be avoided later.
> 
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>

As long as it's used on data path, better to inline it?

> ---
>  hw/pci.c |   18 ++++++++++++++++++
>  hw/pci.h |    2 ++
>  2 files changed, 20 insertions(+), 0 deletions(-)
> 
> diff --git a/hw/pci.c b/hw/pci.c
> index 5349488..d6c5e66 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -1117,6 +1117,24 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
>      pci_change_irq_level(pci_dev, irq_num, change);
>  }
>  
> +/*
> + * PCI-to-PCI bridge specification
> + * 9.1: Interrupt routing. Table 9-1
> + *
> + * the PCI Express Base Specification, Revision 2.1
> + * 2.2.8.1: INTx interrutp signaling - Rules
> + *          the Implementation Note
> + *          Table 2-20
> + */
> +/*
> + * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
> + * 0-origin unlike PCI interrupt pin register.
> + */
> +int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin)
> +{
> +    return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
> +}
> +
>  /***********************************************************/
>  /* monitor info on PCI */
>  
> diff --git a/hw/pci.h b/hw/pci.h
> index 1a08139..46b3ad3 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -235,6 +235,8 @@ PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
>  void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
>                    void *irq_opaque, int nirq);
>  void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
> +/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
> +int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin);
>  PCIBus *pci_register_bus(DeviceState *parent, const char *name,
>                           pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
>                           void *irq_opaque, int devfn_min, int nirq);
> -- 
> 1.7.1.1

Re: [Qemu-devel] Re: [PATCH 03/26] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle

[Isaku Yamahata]

On Thu, Mar 17, 2011 at 04:43:36PM +0200, Michael S. Tsirkin wrote:
> On Wed, Mar 16, 2011 at 06:29:14PM +0900, Isaku Yamahata wrote:
> > introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
> > standardized. PCI bridge swizzle is common logic, by introducing
> > this function duplicated swizzle logic will be avoided later.
> > 
> > Cc: Michael S. Tsirkin <mst@redhat.com>
> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> 
> As long as it's used on data path, better to inline it?

The function is passed for pci_map_irq_fn as function pointer.
So inlining doesn't make sense.

> 
> > ---
> >  hw/pci.c |   18 ++++++++++++++++++
> >  hw/pci.h |    2 ++
> >  2 files changed, 20 insertions(+), 0 deletions(-)
> > 
> > diff --git a/hw/pci.c b/hw/pci.c
> > index 5349488..d6c5e66 100644
> > --- a/hw/pci.c
> > +++ b/hw/pci.c
> > @@ -1117,6 +1117,24 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
> >      pci_change_irq_level(pci_dev, irq_num, change);
> >  }
> >  
> > +/*
> > + * PCI-to-PCI bridge specification
> > + * 9.1: Interrupt routing. Table 9-1
> > + *
> > + * the PCI Express Base Specification, Revision 2.1
> > + * 2.2.8.1: INTx interrutp signaling - Rules
> > + *          the Implementation Note
> > + *          Table 2-20
> > + */
> > +/*
> > + * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
> > + * 0-origin unlike PCI interrupt pin register.
> > + */
> > +int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin)
> > +{
> > +    return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
> > +}
> > +
> >  /***********************************************************/
> >  /* monitor info on PCI */
> >  
> > diff --git a/hw/pci.h b/hw/pci.h
> > index 1a08139..46b3ad3 100644
> > --- a/hw/pci.h
> > +++ b/hw/pci.h
> > @@ -235,6 +235,8 @@ PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
> >  void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
> >                    void *irq_opaque, int nirq);
> >  void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
> > +/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
> > +int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin);
> >  PCIBus *pci_register_bus(DeviceState *parent, const char *name,
> >                           pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
> >                           void *irq_opaque, int devfn_min, int nirq);
> > -- 
> > 1.7.1.1
> 

-- 
yamahata

[Qemu-devel] Re: [PATCH 09/26] dec_pci: simplify dec_pci.c by using pci_p2pbr

[Blue Swirl]

On Wed, Mar 16, 2011 at 11:29 AM, Isaku Yamahata <yamahata@valinux.co.jp> wrote:
> apply pci_p2pbr for dec_pci.c.
>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: Blue Swirl <blauwirbel@gmail.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> ---
>  hw/dec_pci.c |   49 ++++++++++++++-----------------------------------
>  1 files changed, 14 insertions(+), 35 deletions(-)
>
> diff --git a/hw/dec_pci.c b/hw/dec_pci.c
> index 3cc4f04..fbd1363 100644
> --- a/hw/dec_pci.c
> +++ b/hw/dec_pci.c
> @@ -29,6 +29,7 @@
>  #include "pci_host.h"
>  #include "pci_bridge.h"
>  #include "pci_internals.h"
> +#include "pci_p2pbr.h"
>
>  /* debug DEC */
>  //#define DEBUG_DEC
> @@ -50,42 +51,21 @@ static int dec_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
>     return irq_num;
>  }
>
> -static int dec_21154_initfn(PCIDevice *dev)
> -{
> -    int rc;
> -
> -    rc = pci_bridge_initfn(dev);
> -    if (rc < 0) {
> -        return rc;
> -    }
> -
> -    pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_DEC);
> -    pci_config_set_device_id(dev->config, PCI_DEVICE_ID_DEC_21154);
> -    return 0;
> -}
> -
> -static PCIDeviceInfo dec_21154_pci_bridge_info = {
> -    .qdev.name = "dec-21154-p2p-bridge",
> -    .qdev.desc = "DEC 21154 PCI-PCI bridge",
> -    .qdev.size = sizeof(PCIBridge),
> -    .qdev.vmsd = &vmstate_pci_device,
> -    .qdev.reset = pci_bridge_reset,
> -    .init = dec_21154_initfn,
> -    .exit = pci_bridge_exitfn,
> -    .config_write = pci_bridge_write_config,
> -    .is_bridge = 1,
> -};
> -
>  PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
>  {
> -    PCIDevice *dev;
> -    PCIBridge *br;
> -
> -    dev = pci_create_multifunction(parent_bus, devfn, false,
> -                                   "dec-21154-p2p-bridge");
> -    br = DO_UPCAST(PCIBridge, dev, dev);
> -    pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq);
> -    qdev_init_nofail(&dev->qdev);
> +    const PCIP2PBridgeInit init = {
> +        .bus = parent_bus,
> +        .devfn = devfn,
> +        .multifunction = false,
> +
> +        .bus_name = "DEC 21154 PCI-PCI bridge",
> +        .map_irq = dec_map_irq,
> +    };
> +    const PCIP2PBridgeProp prop = {
> +        .vendor_id = PCI_VENDOR_ID_DEC,
> +        .device_id = PCI_DEVICE_ID_DEC_21154,
> +    };

I'd make the above structures static.

> +    PCIBridge *br = pci_p2pbr_create_simple(&init, &prop);
>     return pci_bridge_get_sec_bus(br);
>  }
>
> @@ -127,7 +107,6 @@ static void dec_register_devices(void)
>     sysbus_register_dev("dec-21154", sizeof(DECState),
>                         pci_dec_21154_init_device);
>     pci_qdev_register(&dec_21154_pci_host_info);
> -    pci_qdev_register(&dec_21154_pci_bridge_info);
>  }
>
>  device_init(dec_register_devices)
> --
> 1.7.1.1
>
>

[Qemu-devel] Re: [PATCH 08/26] apb_pci: simplify apb_pci.c by using pci_p2pbr

[Blue Swirl]

On Wed, Mar 16, 2011 at 11:29 AM, Isaku Yamahata <yamahata@valinux.co.jp> wrote:
> apply pci_p2pbr for apb_pci.c.
>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: Blue Swirl <blauwirbel@gmail.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> ---
>  hw/apb_pci.c |   63 ++++++++++++++++++++++++---------------------------------
>  1 files changed, 27 insertions(+), 36 deletions(-)
>
> diff --git a/hw/apb_pci.c b/hw/apb_pci.c
> index c56ea9a..c9f2a6b 100644
> --- a/hw/apb_pci.c
> +++ b/hw/apb_pci.c
> @@ -31,6 +31,7 @@
>  #include "pci_host.h"
>  #include "pci_bridge.h"
>  #include "pci_internals.h"
> +#include "pci_p2pbr.h"
>  #include "rwhandler.h"
>  #include "apb_pci.h"
>  #include "sysemu.h"
> @@ -297,16 +298,6 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
>
>  static int apb_pci_bridge_initfn(PCIDevice *dev)
>  {
> -    int rc;
> -
> -    rc = pci_bridge_initfn(dev);
> -    if (rc < 0) {
> -        return rc;
> -    }
> -
> -    pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_SUN);
> -    pci_config_set_device_id(dev->config, PCI_DEVICE_ID_SUN_SIMBA);
> -
>     /*
>      * command register:
>      * According to PCI bridge spec, after reset
> @@ -321,10 +312,31 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
>     pci_set_word(dev->config + PCI_STATUS,
>                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
>                  PCI_STATUS_DEVSEL_MEDIUM);
> -    pci_set_byte(dev->config + PCI_REVISION_ID, 0x11);
>     return 0;
>  }
>
> +static PCIBridge *apb_pci_bridge_init(PCIBus *bus,
> +                                      uint8_t devfn, const char *bus_name)
> +{
> +    const PCIP2PBridgeInit init = {
> +        .bus = bus,
> +        .devfn = devfn,
> +        .multifunction = true,
> +
> +        .bus_name = bus_name,
> +        .map_irq = pci_apb_map_irq,
> +
> +        .initfn = apb_pci_bridge_initfn,
> +    };
> +    const PCIP2PBridgeProp prop = {
> +        .vendor_id = PCI_VENDOR_ID_SUN,
> +        .device_id = PCI_DEVICE_ID_SUN_SIMBA,
> +        .revision_id = 0x11,
> +    };

'static' again.

Re: [Qemu-devel] [PATCH 13/26] usb/uhci: add ich9 usb uhci id's device

[Blue Swirl]

On Wed, Mar 16, 2011 at 11:29 AM, Isaku Yamahata <yamahata@valinux.co.jp> wrote:
> add uhci device which has ich9 device id.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> ---
>  hw/pci_ids.h  |    2 ++
>  hw/usb-uhci.c |    8 ++++++++
>  2 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pci_ids.h b/hw/pci_ids.h
> index ea3418c..9daea23 100644
> --- a/hw/pci_ids.h
> +++ b/hw/pci_ids.h
> @@ -108,3 +108,5 @@
>  #define PCI_DEVICE_ID_INTEL_82371AB      0x7111
>  #define PCI_DEVICE_ID_INTEL_82371AB_2    0x7112
>  #define PCI_DEVICE_ID_INTEL_82371AB_3    0x7113
> +
> +#define PCI_DEVICE_ID_INTEL_ICH9_UCHI1   0x2934

s/UCHI/UHCI/g

> diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
> index 2fb2a85..247f1bf 100644
> --- a/hw/usb-uhci.c
> +++ b/hw/usb-uhci.c
> @@ -1193,6 +1193,14 @@ static UHCIDeviceInfo uhci_info[] = {
>         .device_id        = PCI_DEVICE_ID_INTEL_82371AB_2,
>         .revision_id      = 0x01,
>     },{
> +        .pci.qdev.name    = "ich9-usb-uhci1",
> +        .pci.qdev.size    = sizeof(UHCIState),
> +        .pci.qdev.vmsd    = &vmstate_uhci,
> +        .pci.init         = usb_uhci_common_initfn,
> +        .vendor_id        = PCI_VENDOR_ID_INTEL,
> +        .device_id        = PCI_DEVICE_ID_INTEL_ICH9_UCHI1,
> +        .revision_id      = 0x03,
> +    },{
>         .pci.qdev.name    = "vt82c686b-usb-uhci",
>         .pci.qdev.size    = sizeof(UHCIState),
>         .pci.qdev.vmsd    = &vmstate_uhci,
> --
> 1.7.1.1
>
>
>

Re: [Qemu-devel] [PATCH 21/26] acpi, acpi_piix: factor out PM_TMR logic

[Blue Swirl]

On Wed, Mar 16, 2011 at 11:29 AM, Isaku Yamahata <yamahata@valinux.co.jp> wrote:
> factor out PM_TMR logic. Later This will be used by ich9 acpi.

Please also refactor vt82c686.c.

Re: [Qemu-devel] [PATCH 22/26] acpi, acpi_piix: factor out PM1a EVT logic

[Blue Swirl]

On Wed, Mar 16, 2011 at 11:29 AM, Isaku Yamahata <yamahata@valinux.co.jp> wrote:
> factor out ACPI PM1a EVT logic.
> Later this will be used by ich9 acpi.

Also this logic is duplicated in vt82c686.c.

Re: [Qemu-devel] [PATCH 15/26] smbus_eeprom: consolidate smbus eeprom creation

[Aurelien Jarno]

On Wed, Mar 16, 2011 at 06:29:26PM +0900, Isaku Yamahata wrote:
> consolidate smbus initialization for pc_piix, mips_malta and mips_fulong.
> 
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> 
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> Cc: Huacai Chen <zltjiangshi@gmail.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> ---
>  hw/mips_fulong2e.c |    9 +--------
>  hw/mips_malta.c    |   12 ++----------
>  hw/pc_piix.c       |   10 ++--------
>  hw/smbus.h         |    3 +++
>  hw/smbus_eeprom.c  |   22 ++++++++++++++++++++--
>  5 files changed, 28 insertions(+), 28 deletions(-)
> 
> diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
> index 0e90d68..420fada 100644
> --- a/hw/mips_fulong2e.c
> +++ b/hw/mips_fulong2e.c
> @@ -263,11 +263,9 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
>      qemu_irq *cpu_exit_irq;
>      int via_devfn;
>      PCIBus *pci_bus;
> -    uint8_t *eeprom_buf;
>      i2c_bus *smbus;
>      int i;
>      DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
> -    DeviceState *eeprom;
>      CPUState *env;
>  
>      /* init CPUs */
> @@ -353,13 +351,8 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
>  
>      smbus = vt82c686b_pm_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 4),
>                                0xeee1, NULL);
> -    eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
> -    memcpy(eeprom_buf, eeprom_spd, sizeof(eeprom_spd));
>      /* TODO: Populate SPD eeprom data.  */
> -    eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
> -    qdev_prop_set_uint8(eeprom, "address", 0x50);
> -    qdev_prop_set_ptr(eeprom, "data", eeprom_buf);
> -    qdev_init_nofail(eeprom);
> +    smbus_eeprom_init(smbus, 1, eeprom_spd, sizeof(eeprom_spd));
>  
>      /* init other devices */
>      pit = pit_init(0x40, 0);
> diff --git a/hw/mips_malta.c b/hw/mips_malta.c
> index bf0d76d..ed2a483 100644
> --- a/hw/mips_malta.c
> +++ b/hw/mips_malta.c
> @@ -770,7 +770,6 @@ void mips_malta_init (ram_addr_t ram_size,
>      qemu_irq *i8259;
>      qemu_irq *cpu_exit_irq;
>      int piix4_devfn;
> -    uint8_t *eeprom_buf;
>      i2c_bus *smbus;
>      int i;
>      DriveInfo *dinfo;
> @@ -913,15 +912,8 @@ void mips_malta_init (ram_addr_t ram_size,
>      usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
>      smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(9),
>                            NULL, NULL, 0);
> -    eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
> -    for (i = 0; i < 8; i++) {
> -        /* TODO: Populate SPD eeprom data.  */
> -        DeviceState *eeprom;
> -        eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
> -        qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
> -        qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
> -        qdev_init_nofail(eeprom);
> -    }
> +    /* TODO: Populate SPD eeprom data.  */
> +    smbus_eeprom_init(smbus, 8, NULL, 0);
>      pit = pit_init(0x40, 0);
>      cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
>      DMA_init(0, cpu_exit_irq);
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index 8ea023d..337f2ec 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -37,6 +37,7 @@
>  #include "sysbus.h"
>  #include "arch_init.h"
>  #include "blockdev.h"
> +#include "smbus.h"
>  
>  #define MAX_IDE_BUS 2
>  
> @@ -153,7 +154,6 @@ static void pc_init1(ram_addr_t ram_size,
>      }
>  
>      if (pci_enabled && acpi_enabled) {
> -        uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
>          i2c_bus *smbus;
>  
>          cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
> @@ -162,13 +162,7 @@ static void pc_init1(ram_addr_t ram_size,
>          smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
>                                isa_get_irq(9), *cmos_s3, *smi_irq,
>                                kvm_enabled());
> -        for (i = 0; i < 8; i++) {
> -            DeviceState *eeprom;
> -            eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
> -            qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
> -            qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
> -            qdev_init_nofail(eeprom);
> -        }
> +        smbus_eeprom_init(smbus, 8, NULL, 0);
>      }
>  
>      if (i440fx_state) {
> diff --git a/hw/smbus.h b/hw/smbus.h
> index 571c52d..a398715 100644
> --- a/hw/smbus.h
> +++ b/hw/smbus.h
> @@ -66,3 +66,6 @@ void smbus_write_word(i2c_bus *bus, uint8_t addr, uint8_t command, uint16_t data
>  int smbus_read_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data);
>  void smbus_write_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data,
>                         int len);
> +
> +void smbus_eeprom_init(i2c_bus *smbus, int nb_eeprom,
> +                       const uint8_t *eeprom_spd, int size);
> diff --git a/hw/smbus_eeprom.c b/hw/smbus_eeprom.c
> index 52463e0..3634754 100644
> --- a/hw/smbus_eeprom.c
> +++ b/hw/smbus_eeprom.c
> @@ -96,7 +96,7 @@ static uint8_t eeprom_read_data(SMBusDevice *dev, uint8_t cmd, int n)
>      return eeprom_receive_byte(dev);
>  }
>  
> -static int smbus_eeprom_init(SMBusDevice *dev)
> +static int smbus_eeprom_initfn(SMBusDevice *dev)
>  {
>      SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *)dev;
>  
> @@ -111,7 +111,7 @@ static SMBusDeviceInfo smbus_eeprom_info = {
>          DEFINE_PROP_PTR("data", SMBusEEPROMDevice, data),
>          DEFINE_PROP_END_OF_LIST(),
>      },
> -    .init = smbus_eeprom_init,
> +    .init = smbus_eeprom_initfn,
>      .quick_cmd = eeprom_quick_cmd,
>      .send_byte = eeprom_send_byte,
>      .receive_byte = eeprom_receive_byte,
> @@ -125,3 +125,21 @@ static void smbus_eeprom_register_devices(void)
>  }
>  
>  device_init(smbus_eeprom_register_devices)
> +
> +void smbus_eeprom_init(i2c_bus *smbus, int nb_eeprom,
> +                       const uint8_t *eeprom_spd, int eeprom_spd_size)
> +{
> +    int i;
> +    uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
> +    if (eeprom_spd_size > 0) {
> +        memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size);
> +    }
> +
> +    for (i = 0; i < nb_eeprom; i++) {
> +        DeviceState *eeprom;
> +        eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
> +        qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
> +        qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
> +        qdev_init_nofail(eeprom);
> +    }
> +}
> -- 
> 1.7.1.1
> 
 
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 24/26] acpi, acpi_piix: factor out GPE logic

[Avi Kivity]

On 03/16/2011 11:29 AM, Isaku Yamahata wrote:
> factor out ACPI GPE logic. Later it will be used by ICH9 ACPI.
>

I think this patch is causing qemu-kvm failures on migration:
(gdb) bt
#0  0x000000000049aff4 in qemu_put_be16s (f=0x1a74490, pv=0x2c02580, 
size=2) at hw/hw.h:108
#1  put_uint16 (f=0x1a74490, pv=0x2c02580, size=2) at savevm.c:855
#2  0x000000000049c3e4 in vmstate_save_state (f=0x1a74490, 
vmsd=0x6f0b00, opaque=0x1842ef0) at savevm.c:1436
#3  0x000000000049c3b6 in vmstate_save_state (f=0x1a74490, 
vmsd=0x6f0aa0, opaque=0x1842b90) at savevm.c:1434
#4  0x000000000049c6f1 in vmstate_save (mon=<value optimized out>, 
f=0x1a74490) at savevm.c:1459
#5  qemu_savevm_state_complete (mon=<value optimized out>, f=0x1a74490) 
at savevm.c:1600
#6  0x000000000049455a in migrate_fd_put_ready (opaque=0x1847890) at 
migration.c:383
#7  0x00000000004ce2eb in qemu_run_timers (clock=<value optimized out>) 
at qemu-timer.c:505
#8  0x00000000004ce806 in qemu_run_all_timers () at qemu-timer.c:619
#9  0x0000000000419463 in main_loop_wait (nonblocking=<value optimized 
out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:1339
#10 0x0000000000433927 in kvm_main_loop () at 
/build/home/tlv/akivity/qemu-kvm/qemu-kvm.c:1590
#11 0x000000000041a3a6 in main_loop (argc=<value optimized out>, 
argv=<value optimized out>, envp=<value optimized out>)
     at /build/home/tlv/akivity/qemu-kvm/vl.c:1369
#12 main (argc=<value optimized out>, argv=<value optimized out>, 
envp=<value optimized out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:3257

The vmstate being migrated is "gpe".



>
> +#define VMSTATE_GPE_ARRAY(_field, _state)                            \
> + {                                                                   \
> +     .name       = (stringify(_field)),                              \
> +     .version_id = 0,                                                \
> +     .num        = GPE_LEN,                                          \
> +     .info       =&vmstate_info_uint16,                             \
> +     .size       = sizeof(uint16_t),                                 \
> +     .flags      = VMS_ARRAY | VMS_POINTER,                          \
> +     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
> + }
> +
>   static const VMStateDescription vmstate_gpe = {
>       .name = "gpe",
>       .version_id = 1,
>       .minimum_version_id = 1,
>       .minimum_version_id_old = 1,
>       .fields      = (VMStateField []) {
> -        VMSTATE_UINT16(sts, struct gpe_regs),
> -        VMSTATE_UINT16(en, struct gpe_regs),
> +        VMSTATE_GPE_ARRAY(sts, ACPIGPE),
> +        VMSTATE_GPE_ARRAY(en, ACPIGPE),
>           VMSTATE_END_OF_LIST()
>       }
>   };

I'm no vmstate expert, but this does look odd.  Why both VMS_ARRAY and 
VMS_POINTER? aren't we trying to save/restore a simple 16-bit value?  Or 
at least we did before this patch.

-- 
error compiling committee.c: too many arguments to function

Re: [Qemu-devel] [PATCH 24/26] acpi, acpi_piix: factor out GPE logic

[Isaku Yamahata]

On Sun, Apr 17, 2011 at 04:17:51PM +0300, Avi Kivity wrote:
> On 03/16/2011 11:29 AM, Isaku Yamahata wrote:
>> factor out ACPI GPE logic. Later it will be used by ICH9 ACPI.
>>
>
> I think this patch is causing qemu-kvm failures on migration:
> (gdb) bt
> #0  0x000000000049aff4 in qemu_put_be16s (f=0x1a74490, pv=0x2c02580,  
> size=2) at hw/hw.h:108
> #1  put_uint16 (f=0x1a74490, pv=0x2c02580, size=2) at savevm.c:855
> #2  0x000000000049c3e4 in vmstate_save_state (f=0x1a74490,  
> vmsd=0x6f0b00, opaque=0x1842ef0) at savevm.c:1436
> #3  0x000000000049c3b6 in vmstate_save_state (f=0x1a74490,  
> vmsd=0x6f0aa0, opaque=0x1842b90) at savevm.c:1434
> #4  0x000000000049c6f1 in vmstate_save (mon=<value optimized out>,  
> f=0x1a74490) at savevm.c:1459
> #5  qemu_savevm_state_complete (mon=<value optimized out>, f=0x1a74490)  
> at savevm.c:1600
> #6  0x000000000049455a in migrate_fd_put_ready (opaque=0x1847890) at  
> migration.c:383
> #7  0x00000000004ce2eb in qemu_run_timers (clock=<value optimized out>)  
> at qemu-timer.c:505
> #8  0x00000000004ce806 in qemu_run_all_timers () at qemu-timer.c:619
> #9  0x0000000000419463 in main_loop_wait (nonblocking=<value optimized  
> out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:1339
> #10 0x0000000000433927 in kvm_main_loop () at  
> /build/home/tlv/akivity/qemu-kvm/qemu-kvm.c:1590
> #11 0x000000000041a3a6 in main_loop (argc=<value optimized out>,  
> argv=<value optimized out>, envp=<value optimized out>)
>     at /build/home/tlv/akivity/qemu-kvm/vl.c:1369
> #12 main (argc=<value optimized out>, argv=<value optimized out>,  
> envp=<value optimized out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:3257
>
> The vmstate being migrated is "gpe".
>
>
>
>>
>> +#define VMSTATE_GPE_ARRAY(_field, _state)                            \
>> + {                                                                   \
>> +     .name       = (stringify(_field)),                              \
>> +     .version_id = 0,                                                \
>> +     .num        = GPE_LEN,                                          \
>> +     .info       =&vmstate_info_uint16,                             \
>> +     .size       = sizeof(uint16_t),                                 \
>> +     .flags      = VMS_ARRAY | VMS_POINTER,                          \
>> +     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
>> + }
>> +
>>   static const VMStateDescription vmstate_gpe = {
>>       .name = "gpe",
>>       .version_id = 1,
>>       .minimum_version_id = 1,
>>       .minimum_version_id_old = 1,
>>       .fields      = (VMStateField []) {
>> -        VMSTATE_UINT16(sts, struct gpe_regs),
>> -        VMSTATE_UINT16(en, struct gpe_regs),
>> +        VMSTATE_GPE_ARRAY(sts, ACPIGPE),
>> +        VMSTATE_GPE_ARRAY(en, ACPIGPE),
>>           VMSTATE_END_OF_LIST()
>>       }
>>   };
>
> I'm no vmstate expert, but this does look odd.  Why both VMS_ARRAY and  
> VMS_POINTER? aren't we trying to save/restore a simple 16-bit value?  Or  
> at least we did before this patch.

That's right. the difference is, the new member type became uint8_t*.
Does the following help?

diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 96f5222..3a8fece 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -214,10 +214,9 @@ static int vmstate_acpi_post_load(void *opaque, int version_id)
  {                                                                   \
      .name       = (stringify(_field)),                              \
      .version_id = 0,                                                \
-     .num        = GPE_LEN,                                          \
      .info       = &vmstate_info_uint16,                             \
      .size       = sizeof(uint16_t),                                 \
-     .flags      = VMS_ARRAY | VMS_POINTER,                          \
+     .flags      = VMS_SINGLE | VMS_POINTER,                         \
      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
  }
 


-- 
yamahata

Re: [Qemu-devel] [PATCH 24/26] acpi, acpi_piix: factor out GPE logic

[Avi Kivity]

On 04/17/2011 04:50 PM, Isaku Yamahata wrote:
> On Sun, Apr 17, 2011 at 04:17:51PM +0300, Avi Kivity wrote:
> >  On 03/16/2011 11:29 AM, Isaku Yamahata wrote:
> >>  factor out ACPI GPE logic. Later it will be used by ICH9 ACPI.
> >>
> >
> >  I think this patch is causing qemu-kvm failures on migration:
> >  (gdb) bt
> >  #0  0x000000000049aff4 in qemu_put_be16s (f=0x1a74490, pv=0x2c02580,
> >  size=2) at hw/hw.h:108
> >  #1  put_uint16 (f=0x1a74490, pv=0x2c02580, size=2) at savevm.c:855
> >  #2  0x000000000049c3e4 in vmstate_save_state (f=0x1a74490,
> >  vmsd=0x6f0b00, opaque=0x1842ef0) at savevm.c:1436
> >  #3  0x000000000049c3b6 in vmstate_save_state (f=0x1a74490,
> >  vmsd=0x6f0aa0, opaque=0x1842b90) at savevm.c:1434
> >  #4  0x000000000049c6f1 in vmstate_save (mon=<value optimized out>,
> >  f=0x1a74490) at savevm.c:1459
> >  #5  qemu_savevm_state_complete (mon=<value optimized out>, f=0x1a74490)
> >  at savevm.c:1600
> >  #6  0x000000000049455a in migrate_fd_put_ready (opaque=0x1847890) at
> >  migration.c:383
> >  #7  0x00000000004ce2eb in qemu_run_timers (clock=<value optimized out>)
> >  at qemu-timer.c:505
> >  #8  0x00000000004ce806 in qemu_run_all_timers () at qemu-timer.c:619
> >  #9  0x0000000000419463 in main_loop_wait (nonblocking=<value optimized
> >  out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:1339
> >  #10 0x0000000000433927 in kvm_main_loop () at
> >  /build/home/tlv/akivity/qemu-kvm/qemu-kvm.c:1590
> >  #11 0x000000000041a3a6 in main_loop (argc=<value optimized out>,
> >  argv=<value optimized out>, envp=<value optimized out>)
> >      at /build/home/tlv/akivity/qemu-kvm/vl.c:1369
> >  #12 main (argc=<value optimized out>, argv=<value optimized out>,
> >  envp=<value optimized out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:3257
> >
> >  The vmstate being migrated is "gpe".
> >
> >
> >
> >>
> >>  +#define VMSTATE_GPE_ARRAY(_field, _state)                            \
> >>  + {                                                                   \
> >>  +     .name       = (stringify(_field)),                              \
> >>  +     .version_id = 0,                                                \
> >>  +     .num        = GPE_LEN,                                          \
> >>  +     .info       =&vmstate_info_uint16,                             \
> >>  +     .size       = sizeof(uint16_t),                                 \
> >>  +     .flags      = VMS_ARRAY | VMS_POINTER,                          \
> >>  +     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
> >>  + }
> >>  +
> >>    static const VMStateDescription vmstate_gpe = {
> >>        .name = "gpe",
> >>        .version_id = 1,
> >>        .minimum_version_id = 1,
> >>        .minimum_version_id_old = 1,
> >>        .fields      = (VMStateField []) {
> >>  -        VMSTATE_UINT16(sts, struct gpe_regs),
> >>  -        VMSTATE_UINT16(en, struct gpe_regs),
> >>  +        VMSTATE_GPE_ARRAY(sts, ACPIGPE),
> >>  +        VMSTATE_GPE_ARRAY(en, ACPIGPE),
> >>            VMSTATE_END_OF_LIST()
> >>        }
> >>    };
> >
> >  I'm no vmstate expert, but this does look odd.  Why both VMS_ARRAY and
> >  VMS_POINTER? aren't we trying to save/restore a simple 16-bit value?  Or
> >  at least we did before this patch.
>
> That's right. the difference is, the new member type became uint8_t*.
> Does the following help?
>

Unforunately not.  The core is very similar though:

#0  0x000000000049aff4 in qemu_put_be16s (f=0x2427490, pv=0x1ae7580, 
size=2) at hw/hw.h:108
#1  put_uint16 (f=0x2427490, pv=0x1ae7580, size=2) at savevm.c:855
#2  0x000000000049c3e4 in vmstate_save_state (f=0x2427490, 
vmsd=0x6f0b00, opaque=0x21f5ef0) at savevm.c:1436
#3  0x000000000049c3b6 in vmstate_save_state (f=0x2427490, 
vmsd=0x6f0aa0, opaque=0x21f5b90) at savevm.c:1434
#4  0x000000000049c6f1 in vmstate_save (mon=<value optimized out>, 
f=0x2427490) at savevm.c:1459
#5  qemu_savevm_state_complete (mon=<value optimized out>, f=0x2427490) 
at savevm.c:1600
#6  0x000000000049455a in migrate_fd_put_ready (opaque=0x21fa8c0) at 
migration.c:383
#7  0x00000000004ce2eb in qemu_run_timers (clock=<value optimized out>) 
at qemu-timer.c:505
#8  0x00000000004ce806 in qemu_run_all_timers () at qemu-timer.c:619
#9  0x0000000000419463 in main_loop_wait (nonblocking=<value optimized 
out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:1339
#10 0x0000000000433927 in kvm_main_loop () at 
/build/home/tlv/akivity/qemu-kvm/qemu-kvm.c:1590
#11 0x000000000041a3a6 in main_loop (argc=<value optimized out>, 
argv=<value optimized out>, envp=<value optimized out>)
     at /build/home/tlv/akivity/qemu-kvm/vl.c:1369
#12 main (argc=<value optimized out>, argv=<value optimized out>, 
envp=<value optimized out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:3257


-- 
error compiling committee.c: too many arguments to function

Re: [Qemu-devel] [PATCH 24/26] acpi, acpi_piix: factor out GPE logic

[Isaku Yamahata]

On Sun, Apr 17, 2011 at 06:53:12PM +0300, Avi Kivity wrote:
> On 04/17/2011 04:50 PM, Isaku Yamahata wrote:
>> On Sun, Apr 17, 2011 at 04:17:51PM +0300, Avi Kivity wrote:
>> >  On 03/16/2011 11:29 AM, Isaku Yamahata wrote:
>> >>  factor out ACPI GPE logic. Later it will be used by ICH9 ACPI.
>> >>
>> >
>> >  I think this patch is causing qemu-kvm failures on migration:
>> >  (gdb) bt
>> >  #0  0x000000000049aff4 in qemu_put_be16s (f=0x1a74490, pv=0x2c02580,
>> >  size=2) at hw/hw.h:108
>> >  #1  put_uint16 (f=0x1a74490, pv=0x2c02580, size=2) at savevm.c:855
>> >  #2  0x000000000049c3e4 in vmstate_save_state (f=0x1a74490,
>> >  vmsd=0x6f0b00, opaque=0x1842ef0) at savevm.c:1436
>> >  #3  0x000000000049c3b6 in vmstate_save_state (f=0x1a74490,
>> >  vmsd=0x6f0aa0, opaque=0x1842b90) at savevm.c:1434
>> >  #4  0x000000000049c6f1 in vmstate_save (mon=<value optimized out>,
>> >  f=0x1a74490) at savevm.c:1459
>> >  #5  qemu_savevm_state_complete (mon=<value optimized out>, f=0x1a74490)
>> >  at savevm.c:1600
>> >  #6  0x000000000049455a in migrate_fd_put_ready (opaque=0x1847890) at
>> >  migration.c:383
>> >  #7  0x00000000004ce2eb in qemu_run_timers (clock=<value optimized out>)
>> >  at qemu-timer.c:505
>> >  #8  0x00000000004ce806 in qemu_run_all_timers () at qemu-timer.c:619
>> >  #9  0x0000000000419463 in main_loop_wait (nonblocking=<value optimized
>> >  out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:1339
>> >  #10 0x0000000000433927 in kvm_main_loop () at
>> >  /build/home/tlv/akivity/qemu-kvm/qemu-kvm.c:1590
>> >  #11 0x000000000041a3a6 in main_loop (argc=<value optimized out>,
>> >  argv=<value optimized out>, envp=<value optimized out>)
>> >      at /build/home/tlv/akivity/qemu-kvm/vl.c:1369
>> >  #12 main (argc=<value optimized out>, argv=<value optimized out>,
>> >  envp=<value optimized out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:3257
>> >
>> >  The vmstate being migrated is "gpe".
>> >
>> >
>> >
>> >>
>> >>  +#define VMSTATE_GPE_ARRAY(_field, _state)                            \
>> >>  + {                                                                   \
>> >>  +     .name       = (stringify(_field)),                              \
>> >>  +     .version_id = 0,                                                \
>> >>  +     .num        = GPE_LEN,                                          \
>> >>  +     .info       =&vmstate_info_uint16,                             \
>> >>  +     .size       = sizeof(uint16_t),                                 \
>> >>  +     .flags      = VMS_ARRAY | VMS_POINTER,                          \
>> >>  +     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
>> >>  + }
>> >>  +
>> >>    static const VMStateDescription vmstate_gpe = {
>> >>        .name = "gpe",
>> >>        .version_id = 1,
>> >>        .minimum_version_id = 1,
>> >>        .minimum_version_id_old = 1,
>> >>        .fields      = (VMStateField []) {
>> >>  -        VMSTATE_UINT16(sts, struct gpe_regs),
>> >>  -        VMSTATE_UINT16(en, struct gpe_regs),
>> >>  +        VMSTATE_GPE_ARRAY(sts, ACPIGPE),
>> >>  +        VMSTATE_GPE_ARRAY(en, ACPIGPE),
>> >>            VMSTATE_END_OF_LIST()
>> >>        }
>> >>    };
>> >
>> >  I'm no vmstate expert, but this does look odd.  Why both VMS_ARRAY and
>> >  VMS_POINTER? aren't we trying to save/restore a simple 16-bit value?  Or
>> >  at least we did before this patch.
>>
>> That's right. the difference is, the new member type became uint8_t*.
>> Does the following help?
>>
>
> Unforunately not.  The core is very similar though:

Hmm but it seems that there is another issue.
With the previous patch, I confirmed sts and en are saved as expected.

The related VMStateDescription are defined in acpi_piix.c in
the following order.
vmstate_acpi calls vmstate_gpe. and &vmstate_gpe < &vmstate_acpi.

However, your call trace shows something different.
(I'm assuming the stack trace is correct. gdb or compiler optimization?)

static const VMStateDescription vmstate_gpe = {
...

static const VMStateDescription vmstate_acpi = {
    .fields      = (VMStateField []) {
...
        VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),


>
> #0  0x000000000049aff4 in qemu_put_be16s (f=0x2427490, pv=0x1ae7580,  
> size=2) at hw/hw.h:108
> #1  put_uint16 (f=0x2427490, pv=0x1ae7580, size=2) at savevm.c:855
> #2  0x000000000049c3e4 in vmstate_save_state (f=0x2427490,  
> vmsd=0x6f0b00, opaque=0x21f5ef0) at savevm.c:1436

vmsd = 0x6f0b00 = &vmstate_gpe <<<<<< correct???
opaque = 0x21f5ef0 = &PIIX4PMState->gpe

> #3  0x000000000049c3b6 in vmstate_save_state (f=0x2427490,  
> vmsd=0x6f0aa0, opaque=0x21f5b90) at savevm.c:1434

vmsd = 0x6f0aa0 = &vmstate_acpi  <<<<<<<<<<<<< correct?
opaque = 0x21f5b90 = &PIIX4PMState

opaque seems correct as 
0x21f5b90 - 0x21f5ef0 = 0x348 = offsetof(PIIX4PMState, gpe)


On my environment the stack trace looks like
(gdb) where
#0  vmstate_save_state (f=0x25d16d0, vmsd=0x695940, opaque=0x283a218)
    at savevm.c:1374
#1  0x00000000004bb4f7 in vmstate_save_state (f=0x25d16d0, vmsd=0x695a40, 
    opaque=0x2839ed0) at savevm.c:1412
...

(gdb) print &vmstate_gpe
$32 = (const VMStateDescription *) 0x695940
(gdb) print &vmstate_acpi
$33 = (const VMStateDescription *) 0x695a40

thanks,

> #4  0x000000000049c6f1 in vmstate_save (mon=<value optimized out>,  
> f=0x2427490) at savevm.c:1459
> #5  qemu_savevm_state_complete (mon=<value optimized out>, f=0x2427490)  
> at savevm.c:1600
> #6  0x000000000049455a in migrate_fd_put_ready (opaque=0x21fa8c0) at  
> migration.c:383
> #7  0x00000000004ce2eb in qemu_run_timers (clock=<value optimized out>)  
> at qemu-timer.c:505
> #8  0x00000000004ce806 in qemu_run_all_timers () at qemu-timer.c:619
> #9  0x0000000000419463 in main_loop_wait (nonblocking=<value optimized  
> out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:1339
> #10 0x0000000000433927 in kvm_main_loop () at  
> /build/home/tlv/akivity/qemu-kvm/qemu-kvm.c:1590
> #11 0x000000000041a3a6 in main_loop (argc=<value optimized out>,  
> argv=<value optimized out>, envp=<value optimized out>)
>     at /build/home/tlv/akivity/qemu-kvm/vl.c:1369
> #12 main (argc=<value optimized out>, argv=<value optimized out>,  
> envp=<value optimized out>) at /build/home/tlv/akivity/qemu-kvm/vl.c:3257

>
>
> -- 
> error compiling committee.c: too many arguments to function
>

-- 
yamahata

Re: [Qemu-devel] [PATCH 24/26] acpi, acpi_piix: factor out GPE logic

[Avi Kivity]

On 04/18/2011 10:47 AM, Isaku Yamahata wrote:
> Hmm but it seems that there is another issue.
> With the previous patch, I confirmed sts and en are saved as expected.
>
> The related VMStateDescription are defined in acpi_piix.c in
> the following order.
> vmstate_acpi calls vmstate_gpe. and&vmstate_gpe<  &vmstate_acpi.
>

(gdb) p &vmstate_gpe
$1 = (const VMStateDescription *) 0x6f0b00
(gdb) p &vmstate_acpi
$2 = (const VMStateDescription *) 0x6f0aa0

So no.

> However, your call trace shows something different.
> (I'm assuming the stack trace is correct. gdb or compiler optimization?)
>
> static const VMStateDescription vmstate_gpe = {
> ...
>
> static const VMStateDescription vmstate_acpi = {
>      .fields      = (VMStateField []) {
> ...
>          VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
>
>
> >
> >  #0  0x000000000049aff4 in qemu_put_be16s (f=0x2427490, pv=0x1ae7580,
> >  size=2) at hw/hw.h:108
> >  #1  put_uint16 (f=0x2427490, pv=0x1ae7580, size=2) at savevm.c:855
> >  #2  0x000000000049c3e4 in vmstate_save_state (f=0x2427490,
> >  vmsd=0x6f0b00, opaque=0x21f5ef0) at savevm.c:1436
>
> vmsd = 0x6f0b00 =&vmstate_gpe<<<<<<  correct???

Correct.

> opaque = 0x21f5ef0 =&PIIX4PMState->gpe
>
> >  #3  0x000000000049c3b6 in vmstate_save_state (f=0x2427490,
> >  vmsd=0x6f0aa0, opaque=0x21f5b90) at savevm.c:1434
>
> vmsd = 0x6f0aa0 =&vmstate_acpi<<<<<<<<<<<<<  correct?

Correct.

> opaque = 0x21f5b90 =&PIIX4PMState
>
> opaque seems correct as
> 0x21f5b90 - 0x21f5ef0 = 0x348 = offsetof(PIIX4PMState, gpe)
>
>
> On my environment the stack trace looks like
> (gdb) where
> #0  vmstate_save_state (f=0x25d16d0, vmsd=0x695940, opaque=0x283a218)
>      at savevm.c:1374
> #1  0x00000000004bb4f7 in vmstate_save_state (f=0x25d16d0, vmsd=0x695a40,
>      opaque=0x2839ed0) at savevm.c:1412
> ...
>
> (gdb) print&vmstate_gpe
> $32 = (const VMStateDescription *) 0x695940
> (gdb) print&vmstate_acpi
> $33 = (const VMStateDescription *) 0x695a40
>

Are you using qemu-kvm.git or qemu.git?  I think there are indeed two 
issues, your patch fixes the first and there is another that is specific 
to qemu-kvm.

-- 
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.

Re: [Qemu-devel] [PATCH 24/26] acpi, acpi_piix: factor out GPE logic

[Isaku Yamahata]

On Mon, Apr 18, 2011 at 11:22:40AM +0300, Avi Kivity wrote:
> Are you using qemu-kvm.git or qemu.git?  I think there are indeed two  
> issues, your patch fixes the first and there is another that is specific  
> to qemu-kvm.

I'm using qemu.git. I've start to have a look at qemu-kvm.git,
-- 
yamahata

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Hu Tao]

On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
> This patch series adds basic q35 chipset support for native pci express
> support. Some bios related patches are still needed.
> For those who want to try it, the following repo is avaiable.
> (vgabios doesn't need patches, so use the upstream one)
> 
> git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
> git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/seabios

Hi,

When I visit the links, the pages say 'You dont have permission'. Could
you make these git-repos avaiable again?  Thanks in advance.

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Isaku Yamahata]

On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
> On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
> > This patch series adds basic q35 chipset support for native pci express
> > support. Some bios related patches are still needed.
> > For those who want to try it, the following repo is avaiable.
> > (vgabios doesn't need patches, so use the upstream one)
> > 
> > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
> > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/seabios
> 
> Hi,
> 
> When I visit the links, the pages say 'You dont have permission'. Could
> you make these git-repos avaiable again?  Thanks in advance.

The link is not for human-reading. Just issue the git command.
-- 
yamahata

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Hu Tao]

On Tue, Apr 19, 2011 at 05:51:27PM +0900, Isaku Yamahata wrote:
> On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
> > On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
> > > This patch series adds basic q35 chipset support for native pci express
> > > support. Some bios related patches are still needed.
> > > For those who want to try it, the following repo is avaiable.
> > > (vgabios doesn't need patches, so use the upstream one)
> > > 
> > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
> > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/seabios
> > 
> > Hi,
> > 
> > When I visit the links, the pages say 'You dont have permission'. Could
> > you make these git-repos avaiable again?  Thanks in advance.
> 
> The link is not for human-reading. Just issue the git command.

Done. Thanks:)

> -- 
> yamahata

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Isaku Yamahata]

I forgot to changet its HEAD. Now it's fixed.
So please change the branch manually or clone the repo again.

On Tue, Apr 19, 2011 at 04:58:32PM +0800, Hu Tao wrote:
> On Tue, Apr 19, 2011 at 05:51:27PM +0900, Isaku Yamahata wrote:
> > On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
> > > On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
> > > > This patch series adds basic q35 chipset support for native pci express
> > > > support. Some bios related patches are still needed.
> > > > For those who want to try it, the following repo is avaiable.
> > > > (vgabios doesn't need patches, so use the upstream one)
> > > > 
> > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
> > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/seabios
> > > 
> > > Hi,
> > > 
> > > When I visit the links, the pages say 'You dont have permission'. Could
> > > you make these git-repos avaiable again?  Thanks in advance.
> > 
> > The link is not for human-reading. Just issue the git command.
> 
> Done. Thanks:)
> 
> > -- 
> > yamahata
> 

-- 
yamahata

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Isaku Yamahata]

On Wed, May 25, 2011 at 09:15:55AM +0200, Jan Kiszka wrote:
> FWIW, patch below fixes UHCI here. I suspect more bugs in this area as
> accessing the chip_config registers appears to rely on the host being
> little endian (direct memcpy).
> 
> In contrast, the PCI mapping issue turned out to be a read herring. The
> unmapped regions were actually ROM BARs which are usually unmapped. And
> the network issues were related to an outdated DSDT. Somehow rebuilding
> Seabios did not always properly regenerate them, so my polarity fixes
> were not inluded. Haven't looked into details, but deleting out/ and
> src/*.hex resolved that.

Good catch. I queued it in my repo.


> 
> I'll have to put this topic aside for now as it looks like we don't
> depend on it for PCIe pass-through. Still, it's a cool thing, and I
> would be happy to find it upstream soon!
> 
> Jan
> 
> ------8<-------
> 
> From: Jan Kiszka <jan.kiszka@siemens.com>
> Subject: [PATCH] q35: Fix irr initialization for slots 25..31
> 
> This was totally off: The CC registers are 16 bit (stored as little
> endian), their offsets run in reverse order, and D26IR as well as D25IR
> have 4 bytes offset to their successors.
> 
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> ---
>  hw/q35.c |   10 +++++++---
>  1 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/q35.c b/hw/q35.c
> index a06ea7d..0ab8532 100644
> --- a/hw/q35.c
> +++ b/hw/q35.c
> @@ -424,14 +424,18 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
>  static void ich9_cc_update(ICH9_LPCState *lpc)
>  {
>      int slot;
> -    int reg_offset;
> +    int reg;
>      int intx;
>  
>      /* D{25 - 31}IR, but D30IR is read only to 0. */
> -    for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
> +    for (slot = 31, reg = ICH9_CC_D31IR; slot >= 25; slot--, reg += 2) {
>          if (slot != 30) {
>              ich9_cc_update_ir(lpc->irr[slot],
> -                              lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
> +                              lpc->chip_config[reg] |
> +                              (uint32_t)lpc->chip_config[reg + 1] << 8);
> +        }
> +        if (slot <= 27) {
> +            reg += 2;
>          }
>      }
>  
> -- 
> 1.7.1
> 



-- 
yamahata

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Jan Kiszka]

[-- Attachment #1: Type: text/plain, Size: 5016 bytes --]

On 2011-05-17 09:15, Jan Kiszka wrote:
> On 2011-05-16 23:55, Adnan Khaleel wrote:
>> I finally got this work after I realised that the AHCI driver was not being loaded in my disk image and that ACHI was not being enabled in the Seabios .config file.
>> This is really good work Yamahata, thanks.
>>
>>
>> As far as I can tell, everything works like the stock Qemu 0.14 except networking. The guest OS sees the network device and initialises it but I think the Qemu DHCP server/firewall never gets back, since the network device doesn't even get a 10.0.2.15 ip address during bootup and the guest dhcp client never gets an ip address, 
>>
>>
>> eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
>> eth0   Starting DHCP4 client. . . . . . . .
>> eth0   DHCP4 continues in background 
>> eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
>> eth0   DHCP4 client (dhcpcd) is running
>> eth0   . . . but is still waiting for data
>> eth0   interface could not be set up until now
>>
>>
>> So doing an ifconfig later on just shows
>>
>>
>> eth0   Link encap:Ethernet  HWaddr 52:54:00:12:34:56
>>          UP BROADCAST MULTICAST  MTU:1500  Metric:1
>>          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>>          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>>          collisions:0 txqueuelen:1000
>>          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
>>
>>
>>
>> lo      Link encap:Local loopback  
>>          inet addr:127.0.0.1  Mask:255.0.0.0
>>          inet6 addr: ::1/128 Scope:Host
>>          UP LOOPBACK RUNING  MTU:16436  Metric:1
>>          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>>          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>>          collisions:0 txqueuelen:1000
>>          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
>>
>>
>> I'm going to start a separate thread to see what the possible cause might be and what might be the best way to debug this. Do you have any idea if this q35 chipset going to be committed to Qemu upstream?
> 
> I've recently hacked a bit on q35, rebased it over current master, found
> and fixed a few bugs to allow booting of WinXP and Win7, and
> particularly added kvm support to improve testability significantly. You
> can find my current work at
> 
> git://git.kiszka.org/qemu.git q35-test
> git://git.kiszka.org/seabios.git q35-test
> 
> There are some issues remaining, e.g. usb appeared broken to me. Now I
> just tested your scenario (e1000+usernet) with a Win7 guest, and I do
> not get an IP either. There is no traffic on the vlan (I attached a dump
> device to verify). Looking closer, it seems PCI bar mapping is failing,
> at least partially, see 'info pci'. I hope it's not yet another ACPI
> issue. Fixing the polarity bug already forced me to dig way too deep
> into this horrible domain.

FWIW, patch below fixes UHCI here. I suspect more bugs in this area as
accessing the chip_config registers appears to rely on the host being
little endian (direct memcpy).

In contrast, the PCI mapping issue turned out to be a read herring. The
unmapped regions were actually ROM BARs which are usually unmapped. And
the network issues were related to an outdated DSDT. Somehow rebuilding
Seabios did not always properly regenerate them, so my polarity fixes
were not inluded. Haven't looked into details, but deleting out/ and
src/*.hex resolved that.

I'll have to put this topic aside for now as it looks like we don't
depend on it for PCIe pass-through. Still, it's a cool thing, and I
would be happy to find it upstream soon!

Jan

------8<-------

From: Jan Kiszka <jan.kiszka@siemens.com>
Subject: [PATCH] q35: Fix irr initialization for slots 25..31

This was totally off: The CC registers are 16 bit (stored as little
endian), their offsets run in reverse order, and D26IR as well as D25IR
have 4 bytes offset to their successors.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 hw/q35.c |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/q35.c b/hw/q35.c
index a06ea7d..0ab8532 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -424,14 +424,18 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
 static void ich9_cc_update(ICH9_LPCState *lpc)
 {
     int slot;
-    int reg_offset;
+    int reg;
     int intx;
 
     /* D{25 - 31}IR, but D30IR is read only to 0. */
-    for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
+    for (slot = 31, reg = ICH9_CC_D31IR; slot >= 25; slot--, reg += 2) {
         if (slot != 30) {
             ich9_cc_update_ir(lpc->irr[slot],
-                              lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
+                              lpc->chip_config[reg] |
+                              (uint32_t)lpc->chip_config[reg + 1] << 8);
+        }
+        if (slot <= 27) {
+            reg += 2;
         }
     }
 
-- 
1.7.1


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 259 bytes --]

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Isaku Yamahata]

On Tue, May 17, 2011 at 04:21:11PM +0200, Jan Kiszka wrote:
> I also succeeded with passing through a PCIe host device. Nicely, the
> full set capabilities showed up on the guest side this way. But GPU
> pass-through did not improve this way (it rather regressed, yet unclear
> why).

Interesting.

> > I had a quick look at your patches.
> > With seabios patch of 94710189f5323034e00b510fe5a0865a7b576a9f,
> > you ignored MCFG area.
> > 
> > (start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR, size = 256MB) is used
> > for MCFG (!= pci region), so it can't be used for PCI region.
> > That's why 256M is added to s.
> > And Q35_HOST_BRIDGE_PCIEXBAR_ADDR in dev-q35.h also needs to be adjusted.
> 
> Confused. Where was the PCI region located without my hack?

I mean the following patch on top of your tree.
At the moment, I only compiled it.

diff --git a/src/dev-q35.c b/src/dev-q35.c
index c0aa057..eee50c4 100644
--- a/src/dev-q35.c
+++ b/src/dev-q35.c
@@ -36,13 +36,15 @@ void mch_mem_addr_init(u16 bdf, void *arg)
 
     /*
      * BUILD_MAX_HIGHMEM == 0xc0000000
-     * [0xc000 0000, 0xf000 0000) for MCFG
-     *  4GB - 1GB, 4GB - 256MB
+     * [0xc000 0000, 0xd000 0000) for MCFG
+     *  3GB ,        3GB + 256MB
+     * [0xd000 0000, 0xf000 0000) for pci memory region
+     *  3GB + 256MB, 4GB - 256MB
      * [0xf000 0000, 0xfec0 0000) for DMI interface(subtractive decode)
      *  4GB - 256MB, 4GB - 20MB
      */
-    s = BUILD_MAX_HIGHMEM;
-    e = s + 128 * 1024 * 1024 - 1 + 512 * 1024 * 1024;
+    s = Q35_HOST_BRIDGE_PCIEXBAR_ADDR + Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
+    e = s + 512 * 1024 * 1024 - 1;
     pci_region_init(addr->pci_bios_mem_region, s, e);
 
     /* pci_bios_mem_addr + <some value: 128M is used here> */
diff --git a/src/dev-q35.h b/src/dev-q35.h
index f5cae62..0d83dba 100644
--- a/src/dev-q35.h
+++ b/src/dev-q35.h
@@ -8,7 +8,7 @@
 #define  Q35_HOST_BRIDGE_SMRAM          0x9d
 #define Q35_HOST_BRIDGE_PCIEXBAR        0x60
 #define  Q35_HOST_BRIDGE_PCIEXBAR_SIZE  (256 * 1024 * 1024)
-#define  Q35_HOST_BRIDGE_PCIEXBAR_ADDR  0xe0000000
+#define  Q35_HOST_BRIDGE_PCIEXBAR_ADDR   BUILD_MAX_HIGHMEM
 #define  Q35_HOST_BRIDGE_PCIEXBAREN     ((u64)1)
 #define  Q35_HOST_PCIE_PCI_SEGMENT      0
 #define  Q35_HOST_PCIE_START_BUS_NUMBER 0


> BTW, the PCI bar mapping failures of VGA or e1000 are independent of
> that seabios commit. You should see them with your tree as well.

Hmm, I'll look into it.


> > After pushing out pci id clean up and once they are accepted,
> > I'll publish rebased/cleaned up one.
> 
> Note that I dropped "simply i440fx initialization". It was a premature
> cleanup that caused regressions. The good news: I'm working on PAM/SMRAM
> fixes that will include such a cleanup after removing the need for the
> init function. The bad news: Those patches will force you to rebase
> again (to break out the new PAM/SMRAM code).

Please keep CCed on me.
-- 
yamahata

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Jan Kiszka]

On 2011-05-17 15:57, Isaku Yamahata wrote:
> On Tue, May 17, 2011 at 09:15:39AM +0200, Jan Kiszka wrote:
>> On 2011-05-16 23:55, Adnan Khaleel wrote:
>>> I finally got this work after I realised that the AHCI driver was not being loaded in my disk image and that ACHI was not being enabled in the Seabios .config file.
>>> This is really good work Yamahata, thanks.
>>>
>>>
>>> As far as I can tell, everything works like the stock Qemu 0.14 except networking. The guest OS sees the network device and initialises it but I think the Qemu DHCP server/firewall never gets back, since the network device doesn't even get a 10.0.2.15 ip address during bootup and the guest dhcp client never gets an ip address, 
>>>
>>>
>>> eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
>>> eth0   Starting DHCP4 client. . . . . . . .
>>> eth0   DHCP4 continues in background 
>>> eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
>>> eth0   DHCP4 client (dhcpcd) is running
>>> eth0   . . . but is still waiting for data
>>> eth0   interface could not be set up until now
>>>
>>>
>>> So doing an ifconfig later on just shows
>>>
>>>
>>> eth0   Link encap:Ethernet  HWaddr 52:54:00:12:34:56
>>>          UP BROADCAST MULTICAST  MTU:1500  Metric:1
>>>          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>>>          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>>>          collisions:0 txqueuelen:1000
>>>          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
>>>
>>>
>>>
>>> lo      Link encap:Local loopback  
>>>          inet addr:127.0.0.1  Mask:255.0.0.0
>>>          inet6 addr: ::1/128 Scope:Host
>>>          UP LOOPBACK RUNING  MTU:16436  Metric:1
>>>          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>>>          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>>>          collisions:0 txqueuelen:1000
>>>          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
>>>
>>>
>>> I'm going to start a separate thread to see what the possible cause might be and what might be the best way to debug this. Do you have any idea if this q35 chipset going to be committed to Qemu upstream?
>>
>> I've recently hacked a bit on q35, rebased it over current master, found
>> and fixed a few bugs to allow booting of WinXP and Win7, and
>> particularly added kvm support to improve testability significantly. You
>> can find my current work at
>>
>> git://git.kiszka.org/qemu.git q35-test
>> git://git.kiszka.org/seabios.git q35-test
>>
>> There are some issues remaining, e.g. usb appeared broken to me. Now I
>> just tested your scenario (e1000+usernet) with a Win7 guest, and I do
>> not get an IP either. There is no traffic on the vlan (I attached a dump
>> device to verify). Looking closer, it seems PCI bar mapping is failing,
>> at least partially, see 'info pci'. I hope it's not yet another ACPI
>> issue. Fixing the polarity bug already forced me to dig way too deep
>> into this horrible domain.
> 
> Wow, very great. So is kvm working with q35?

Mostly. The key was to avoid that seabios does smm initialization as
that mode is not support by kvm. I also merged the q35 into qemu-kvm to
enable in-kernel irqchip support. That finally revealed the polarity
issues (only with win7 guests). I also posted a qemu ioapic patch to
make it polarity aware as well [1][2].

I also succeeded with passing through a PCIe host device. Nicely, the
full set capabilities showed up on the guest side this way. But GPU
pass-through did not improve this way (it rather regressed, yet unclear
why).

> 
> I had a quick look at your patches.
> With seabios patch of 94710189f5323034e00b510fe5a0865a7b576a9f,
> you ignored MCFG area.
> 
> (start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR, size = 256MB) is used
> for MCFG (!= pci region), so it can't be used for PCI region.
> That's why 256M is added to s.
> And Q35_HOST_BRIDGE_PCIEXBAR_ADDR in dev-q35.h also needs to be adjusted.

Confused. Where was the PCI region located without my hack?

BTW, the PCI bar mapping failures of VGA or e1000 are independent of
that seabios commit. You should see them with your tree as well.

> 
> After pushing out pci id clean up and once they are accepted,
> I'll publish rebased/cleaned up one.

Note that I dropped "simply i440fx initialization". It was a premature
cleanup that caused regressions. The good news: I'm working on PAM/SMRAM
fixes that will include such a cleanup after removing the need for the
init function. The bad news: Those patches will force you to rebase
again (to break out the new PAM/SMRAM code).

Jan

[1] http://thread.gmane.org/gmane.comp.emulators.qemu/102459
[2] http://thread.gmane.org/gmane.comp.emulators.qemu/102460

-- 
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Isaku Yamahata]

On Tue, May 17, 2011 at 09:15:39AM +0200, Jan Kiszka wrote:
> On 2011-05-16 23:55, Adnan Khaleel wrote:
> > I finally got this work after I realised that the AHCI driver was not being loaded in my disk image and that ACHI was not being enabled in the Seabios .config file.
> > This is really good work Yamahata, thanks.
> > 
> > 
> > As far as I can tell, everything works like the stock Qemu 0.14 except networking. The guest OS sees the network device and initialises it but I think the Qemu DHCP server/firewall never gets back, since the network device doesn't even get a 10.0.2.15 ip address during bootup and the guest dhcp client never gets an ip address, 
> > 
> > 
> > eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
> > eth0   Starting DHCP4 client. . . . . . . .
> > eth0   DHCP4 continues in background 
> > eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
> > eth0   DHCP4 client (dhcpcd) is running
> > eth0   . . . but is still waiting for data
> > eth0   interface could not be set up until now
> > 
> > 
> > So doing an ifconfig later on just shows
> > 
> > 
> > eth0   Link encap:Ethernet  HWaddr 52:54:00:12:34:56
> >          UP BROADCAST MULTICAST  MTU:1500  Metric:1
> >          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
> >          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
> >          collisions:0 txqueuelen:1000
> >          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
> > 
> > 
> > 
> > lo      Link encap:Local loopback  
> >          inet addr:127.0.0.1  Mask:255.0.0.0
> >          inet6 addr: ::1/128 Scope:Host
> >          UP LOOPBACK RUNING  MTU:16436  Metric:1
> >          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
> >          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
> >          collisions:0 txqueuelen:1000
> >          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
> > 
> > 
> > I'm going to start a separate thread to see what the possible cause might be and what might be the best way to debug this. Do you have any idea if this q35 chipset going to be committed to Qemu upstream?
> 
> I've recently hacked a bit on q35, rebased it over current master, found
> and fixed a few bugs to allow booting of WinXP and Win7, and
> particularly added kvm support to improve testability significantly. You
> can find my current work at
> 
> git://git.kiszka.org/qemu.git q35-test
> git://git.kiszka.org/seabios.git q35-test
> 
> There are some issues remaining, e.g. usb appeared broken to me. Now I
> just tested your scenario (e1000+usernet) with a Win7 guest, and I do
> not get an IP either. There is no traffic on the vlan (I attached a dump
> device to verify). Looking closer, it seems PCI bar mapping is failing,
> at least partially, see 'info pci'. I hope it's not yet another ACPI
> issue. Fixing the polarity bug already forced me to dig way too deep
> into this horrible domain.

Wow, very great. So is kvm working with q35?

I had a quick look at your patches.
With seabios patch of 94710189f5323034e00b510fe5a0865a7b576a9f,
you ignored MCFG area.

(start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR, size = 256MB) is used
for MCFG (!= pci region), so it can't be used for PCI region.
That's why 256M is added to s.
And Q35_HOST_BRIDGE_PCIEXBAR_ADDR in dev-q35.h also needs to be adjusted.

After pushing out pci id clean up and once they are accepted,
I'll publish rebased/cleaned up one.
-- 
yamahata

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Jan Kiszka]

On 2011-05-16 23:55, Adnan Khaleel wrote:
> I finally got this work after I realised that the AHCI driver was not being loaded in my disk image and that ACHI was not being enabled in the Seabios .config file.
> This is really good work Yamahata, thanks.
> 
> 
> As far as I can tell, everything works like the stock Qemu 0.14 except networking. The guest OS sees the network device and initialises it but I think the Qemu DHCP server/firewall never gets back, since the network device doesn't even get a 10.0.2.15 ip address during bootup and the guest dhcp client never gets an ip address, 
> 
> 
> eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
> eth0   Starting DHCP4 client. . . . . . . .
> eth0   DHCP4 continues in background 
> eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
> eth0   DHCP4 client (dhcpcd) is running
> eth0   . . . but is still waiting for data
> eth0   interface could not be set up until now
> 
> 
> So doing an ifconfig later on just shows
> 
> 
> eth0   Link encap:Ethernet  HWaddr 52:54:00:12:34:56
>          UP BROADCAST MULTICAST  MTU:1500  Metric:1
>          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>          collisions:0 txqueuelen:1000
>          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
> 
> 
> 
> lo      Link encap:Local loopback  
>          inet addr:127.0.0.1  Mask:255.0.0.0
>          inet6 addr: ::1/128 Scope:Host
>          UP LOOPBACK RUNING  MTU:16436  Metric:1
>          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>          collisions:0 txqueuelen:1000
>          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
> 
> 
> I'm going to start a separate thread to see what the possible cause might be and what might be the best way to debug this. Do you have any idea if this q35 chipset going to be committed to Qemu upstream?

I've recently hacked a bit on q35, rebased it over current master, found
and fixed a few bugs to allow booting of WinXP and Win7, and
particularly added kvm support to improve testability significantly. You
can find my current work at

git://git.kiszka.org/qemu.git q35-test
git://git.kiszka.org/seabios.git q35-test

There are some issues remaining, e.g. usb appeared broken to me. Now I
just tested your scenario (e1000+usernet) with a Win7 guest, and I do
not get an IP either. There is no traffic on the vlan (I attached a dump
device to verify). Looking closer, it seems PCI bar mapping is failing,
at least partially, see 'info pci'. I hope it's not yet another ACPI
issue. Fixing the polarity bug already forced me to dig way too deep
into this horrible domain.

Jan

-- 
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Adnan Khaleel]

[-- Attachment #1: Type: text/plain, Size: 1914 bytes --]

I finally got this work after I realised that the AHCI driver was not being loaded in my disk image and that ACHI was not being enabled in the Seabios .config file.
This is really good work Yamahata, thanks.


As far as I can tell, everything works like the stock Qemu 0.14 except networking. The guest OS sees the network device and initialises it but I think the Qemu DHCP server/firewall never gets back, since the network device doesn't even get a 10.0.2.15 ip address during bootup and the guest dhcp client never gets an ip address, 


eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
eth0   Starting DHCP4 client. . . . . . . .
eth0   DHCP4 continues in background 
eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
eth0   DHCP4 client (dhcpcd) is running
eth0   . . . but is still waiting for data
eth0   interface could not be set up until now


So doing an ifconfig later on just shows


eth0   Link encap:Ethernet  HWaddr 52:54:00:12:34:56
         UP BROADCAST MULTICAST  MTU:1500  Metric:1
         RX packets:0 errors:0 dropped:0 overruns:0 frame:0
         TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
         collisions:0 txqueuelen:1000
         RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)



lo      Link encap:Local loopback  
         inet addr:127.0.0.1  Mask:255.0.0.0
         inet6 addr: ::1/128 Scope:Host
         UP LOOPBACK RUNING  MTU:16436  Metric:1
         RX packets:0 errors:0 dropped:0 overruns:0 frame:0
         TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
         collisions:0 txqueuelen:1000
         RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)


I'm going to start a separate thread to see what the possible cause might be and what might be the best way to debug this. Do you have any idea if this q35 chipset going to be committed to Qemu upstream?


Thanks


AK

[-- Attachment #2: Type: text/html, Size: 4076 bytes --]

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?express support

[Adnan Khaleel]

[-- Attachment #1: Type: text/plain, Size: 5528 bytes --]

I found one problem in the bios config that was preventing the BIOS from seeing the MBR. 
The AHCI support was not enabled. To fix this 
change seabios/.config


CONFIG_AHCI=y


The system now loads the boot loader and does some device initialization. However, the boot gets stuck when the OS partition cannot be seen and I get a message saying 


"Waiting for device /dev/disk/by-uuid/xxxx to appear: ............ Could not find /dev/disk/by-uuid/xxxx"


Any ideas whats happening here?


AK
  _____  

From: Adnan Khaleel [mailto:adnan@khaleel.us]
To: adnan@khaleel.us
Cc: Hu Tao [mailto:hutao@cn.fujitsu.com]
Sent: Tue, 10 May 2011 11:43:33 -0500
Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?express support

                Hi Hu,


Have you managed to get this working? 


Adnan
  _____  

From: Adnan Khaleel [mailto:adnan@khaleel.us]
To: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
Cc: Hu Tao [mailto:hutao@cn.fujitsu.com], qemu-devel@nongnu.org
Sent: Thu, 21 Apr 2011 11:12:37 -0500
Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?express support

                I still get the same error:



akhaleel@depot5 qemu_0.14_q35 $ git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
Getting alternates list for http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
Getting pack list for http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
Getting index for pack c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557
Getting pack c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557
 which contains ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
error: cannot unpack 000198da6f46c240e46c562caf57b14268d27597 from /users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
:
:

error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
while processing commit 0000000000000000000000000000000000000000.
rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/clone-tmp': Directory not empty

  _____  

From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
To: Adnan Khaleel [mailto:adnan@khaleel.us]
Cc: Hu Tao [mailto:hutao@cn.fujitsu.com], qemu-devel@nongnu.org
Sent: Wed, 20 Apr 2011 21:07:46 -0500
Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?express support

Okay. Can you please try git clone again?
  
  On Wed, Apr 20, 2011 at 06:41:56PM -0500, Adnan Khaleel wrote:
  > Something is still wrong,
  > 
  > I get the following errors now:
  > 
  > :
  > error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users/
  > akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
  > pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
  > error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under http://
  > people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
  > Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
  > while processing commit 0000000000000000000000000000000000000000.
  > rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/
  > qemu/.git/clone-tmp': Directory not empty
  > 
  > Adnan
  > 
  > 
  >     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
  >     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
  >     To: Hu Tao [mailto:hutao@cn.fujitsu.com], Adnan Khaleel
  >     [mailto:adnan@khaleel.us]
  >     Cc: qemu-devel@nongnu.org
  >     Sent: Wed, 20 Apr 2011 17:46:44 -0500
  >     Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci
  >     express support
  > 
  >     I forgot to changet its HEAD. Now it's fixed.
  >     So please change the branch manually or clone the repo again.
  > 
  >     On Tue, Apr 19, 2011 at 04:58:32PM +0800, Hu Tao wrote:
  >     > On Tue, Apr 19, 2011 at 05:51:27PM +0900, Isaku Yamahata wrote:
  >     > > On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
  >     > > > On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
  >     > > > > This patch series adds basic q35 chipset support for native pci
  >     express
  >     > > > > support. Some bios related patches are still needed.
  >     > > > > For those who want to try it, the following repo is avaiable.
  >     > > > > (vgabios doesn't need patches, so use the upstream one)
  >     > > > >
  >     > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
  >     qemu
  >     > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
  >     seabios
  >     > > >
  >     > > > Hi,
  >     > > >
  >     > > > When I visit the links, the pages say 'You dont have permission'.
  >     Could
  >     > > > you make these git-repos avaiable again? Thanks in advance.
  >     > >
  >     > > The link is not for human-reading. Just issue the git command.
  >     >
  >     > Done. Thanks:)
  >     >
  >     > > --
  >     > > yamahata
  >     >
  > 
  >     --
  >     yamahata
  > 
  
  -- 
  yamahata
        

[-- Attachment #2: Type: text/html, Size: 8156 bytes --]

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native?pci?express support

[Adnan Khaleel]

[-- Attachment #1: Type: text/plain, Size: 5442 bytes --]

Yes, it was a git version conflict.  Thanks.


Adnan
  _____  

From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
To: Adnan Khaleel [mailto:adnan@khaleel.us]
Cc: Hu Tao [mailto:hutao@cn.fujitsu.com], qemu-devel@nongnu.org
Sent: Thu, 21 Apr 2011 11:38:36 -0500
Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native?pci?express support

git clone works for me. Hmmm git installation issue?
  My git is 
  $ git --version
  git version 1.7.1.1
  
  thanks,
  
  On Thu, Apr 21, 2011 at 11:12:37AM -0500, Adnan Khaleel wrote:
  > I still get the same error:
  > 
  > akhaleel@depot5 qemu_0.14_q35 $ git clone http://people.valinux.co.jp/~yamahata
  > /qemu/q35/20110316/qemu
  > Getting alternates list for http://people.valinux.co.jp/~yamahata/qemu/q35/
  > 20110316/qemu/
  > Getting pack list for http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
  > qemu/
  > Getting index for pack c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557
  > Getting pack c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557
  >  which contains ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
  > error: cannot unpack 000198da6f46c240e46c562caf57b14268d27597 from /users/
  > akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
  > pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
  > :
  > :
  > error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users/
  > akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
  > pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
  > error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under http://
  > people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
  > Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
  > while processing commit 0000000000000000000000000000000000000000.
  > rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/
  > qemu/.git/clone-tmp': Directory not empty
  > 
  > 
  >     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
  >     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
  >     To: Adnan Khaleel [mailto:adnan@khaleel.us]
  >     Cc: Hu Tao [mailto:hutao@cn.fujitsu.com], qemu-devel@nongnu.org
  >     Sent: Wed, 20 Apr 2011 21:07:46 -0500
  >     Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?
  >     express support
  > 
  >     Okay. Can you please try git clone again?
  > 
  >     On Wed, Apr 20, 2011 at 06:41:56PM -0500, Adnan Khaleel wrote:
  >     > Something is still wrong,
  >     >
  >     > I get the following errors now:
  >     >
  >     > :
  >     > error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users
  >     /
  >     > akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
  >     > pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
  >     > error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under
  >     http://
  >     > people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
  >     > Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
  >     > while processing commit 0000000000000000000000000000000000000000.
  >     > rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/
  >     qemu_0.14_q35/
  >     > qemu/.git/clone-tmp': Directory not empty
  >     >
  >     > Adnan
  >     >
  >     >
  >     > ?????????????????????????????????????
  >     > From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
  >     > To: Hu Tao [mailto:hutao@cn.fujitsu.com], Adnan Khaleel
  >     > [mailto:adnan@khaleel.us]
  >     > Cc: qemu-devel@nongnu.org
  >     > Sent: Wed, 20 Apr 2011 17:46:44 -0500
  >     > Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native
  >     pci
  >     > express support
  >     >
  >     > I forgot to changet its HEAD. Now it's fixed.
  >     > So please change the branch manually or clone the repo again.
  >     >
  >     > On Tue, Apr 19, 2011 at 04:58:32PM +0800, Hu Tao wrote:
  >     > > On Tue, Apr 19, 2011 at 05:51:27PM +0900, Isaku Yamahata wrote:
  >     > > > On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
  >     > > > > On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
  >     > > > > > This patch series adds basic q35 chipset support for native pci
  >     > express
  >     > > > > > support. Some bios related patches are still needed.
  >     > > > > > For those who want to try it, the following repo is avaiable.
  >     > > > > > (vgabios doesn't need patches, so use the upstream one)
  >     > > > > >
  >     > > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316
  >     /
  >     > qemu
  >     > > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316
  >     /
  >     > seabios
  >     > > > >
  >     > > > > Hi,
  >     > > > >
  >     > > > > When I visit the links, the pages say 'You dont have permission'.
  >     > Could
  >     > > > > you make these git-repos avaiable again? Thanks in advance.
  >     > > >
  >     > > > The link is not for human-reading. Just issue the git command.
  >     > >
  >     > > Done. Thanks:)
  >     > >
  >     > > > --
  >     > > > yamahata
  >     > >
  >     >
  >     > --
  >     > yamahata
  >     >
  > 
  >     --
  >     yamahata
  > 
  
  -- 
  yamahata
    

[-- Attachment #2: Type: text/html, Size: 7604 bytes --]

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native?pci?express support

[Isaku Yamahata]

git clone works for me. Hmmm git installation issue?
My git is 
$ git --version
git version 1.7.1.1

thanks,

On Thu, Apr 21, 2011 at 11:12:37AM -0500, Adnan Khaleel wrote:
> I still get the same error:
> 
> akhaleel@depot5 qemu_0.14_q35 $ git clone http://people.valinux.co.jp/~yamahata
> /qemu/q35/20110316/qemu
> Getting alternates list for http://people.valinux.co.jp/~yamahata/qemu/q35/
> 20110316/qemu/
> Getting pack list for http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
> qemu/
> Getting index for pack c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557
> Getting pack c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557
>  which contains ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
> error: cannot unpack 000198da6f46c240e46c562caf57b14268d27597 from /users/
> akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
> pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
> :
> :
> error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users/
> akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
> pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
> error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under http://
> people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
> Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
> while processing commit 0000000000000000000000000000000000000000.
> rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/
> qemu/.git/clone-tmp': Directory not empty
> 
> 
>     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
>     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
>     To: Adnan Khaleel [mailto:adnan@khaleel.us]
>     Cc: Hu Tao [mailto:hutao@cn.fujitsu.com], qemu-devel@nongnu.org
>     Sent: Wed, 20 Apr 2011 21:07:46 -0500
>     Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?
>     express support
> 
>     Okay. Can you please try git clone again?
> 
>     On Wed, Apr 20, 2011 at 06:41:56PM -0500, Adnan Khaleel wrote:
>     > Something is still wrong,
>     >
>     > I get the following errors now:
>     >
>     > :
>     > error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users
>     /
>     > akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
>     > pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
>     > error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under
>     http://
>     > people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
>     > Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
>     > while processing commit 0000000000000000000000000000000000000000.
>     > rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/
>     qemu_0.14_q35/
>     > qemu/.git/clone-tmp': Directory not empty
>     >
>     > Adnan
>     >
>     >
>     > ?????????????????????????????????????
>     > From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
>     > To: Hu Tao [mailto:hutao@cn.fujitsu.com], Adnan Khaleel
>     > [mailto:adnan@khaleel.us]
>     > Cc: qemu-devel@nongnu.org
>     > Sent: Wed, 20 Apr 2011 17:46:44 -0500
>     > Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native
>     pci
>     > express support
>     >
>     > I forgot to changet its HEAD. Now it's fixed.
>     > So please change the branch manually or clone the repo again.
>     >
>     > On Tue, Apr 19, 2011 at 04:58:32PM +0800, Hu Tao wrote:
>     > > On Tue, Apr 19, 2011 at 05:51:27PM +0900, Isaku Yamahata wrote:
>     > > > On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
>     > > > > On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
>     > > > > > This patch series adds basic q35 chipset support for native pci
>     > express
>     > > > > > support. Some bios related patches are still needed.
>     > > > > > For those who want to try it, the following repo is avaiable.
>     > > > > > (vgabios doesn't need patches, so use the upstream one)
>     > > > > >
>     > > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316
>     /
>     > qemu
>     > > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316
>     /
>     > seabios
>     > > > >
>     > > > > Hi,
>     > > > >
>     > > > > When I visit the links, the pages say 'You dont have permission'.
>     > Could
>     > > > > you make these git-repos avaiable again? Thanks in advance.
>     > > >
>     > > > The link is not for human-reading. Just issue the git command.
>     > >
>     > > Done. Thanks:)
>     > >
>     > > > --
>     > > > yamahata
>     > >
>     >
>     > --
>     > yamahata
>     >
> 
>     --
>     yamahata
> 

-- 
yamahata

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?express support

[Adnan Khaleel]

[-- Attachment #1: Type: text/plain, Size: 4351 bytes --]

I still get the same error:



akhaleel@depot5 qemu_0.14_q35 $ git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
Getting alternates list for http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
Getting pack list for http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
Getting index for pack c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557
Getting pack c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557
 which contains ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
error: cannot unpack 000198da6f46c240e46c562caf57b14268d27597 from /users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
:
:

error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
while processing commit 0000000000000000000000000000000000000000.
rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/clone-tmp': Directory not empty

  _____  

From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
To: Adnan Khaleel [mailto:adnan@khaleel.us]
Cc: Hu Tao [mailto:hutao@cn.fujitsu.com], qemu-devel@nongnu.org
Sent: Wed, 20 Apr 2011 21:07:46 -0500
Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?express support

Okay. Can you please try git clone again?
  
  On Wed, Apr 20, 2011 at 06:41:56PM -0500, Adnan Khaleel wrote:
  > Something is still wrong,
  > 
  > I get the following errors now:
  > 
  > :
  > error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users/
  > akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
  > pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
  > error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under http://
  > people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
  > Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
  > while processing commit 0000000000000000000000000000000000000000.
  > rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/
  > qemu/.git/clone-tmp': Directory not empty
  > 
  > Adnan
  > 
  > 
  >     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
  >     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
  >     To: Hu Tao [mailto:hutao@cn.fujitsu.com], Adnan Khaleel
  >     [mailto:adnan@khaleel.us]
  >     Cc: qemu-devel@nongnu.org
  >     Sent: Wed, 20 Apr 2011 17:46:44 -0500
  >     Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci
  >     express support
  > 
  >     I forgot to changet its HEAD. Now it's fixed.
  >     So please change the branch manually or clone the repo again.
  > 
  >     On Tue, Apr 19, 2011 at 04:58:32PM +0800, Hu Tao wrote:
  >     > On Tue, Apr 19, 2011 at 05:51:27PM +0900, Isaku Yamahata wrote:
  >     > > On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
  >     > > > On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
  >     > > > > This patch series adds basic q35 chipset support for native pci
  >     express
  >     > > > > support. Some bios related patches are still needed.
  >     > > > > For those who want to try it, the following repo is avaiable.
  >     > > > > (vgabios doesn't need patches, so use the upstream one)
  >     > > > >
  >     > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
  >     qemu
  >     > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
  >     seabios
  >     > > >
  >     > > > Hi,
  >     > > >
  >     > > > When I visit the links, the pages say 'You dont have permission'.
  >     Could
  >     > > > you make these git-repos avaiable again? Thanks in advance.
  >     > >
  >     > > The link is not for human-reading. Just issue the git command.
  >     >
  >     > Done. Thanks:)
  >     >
  >     > > --
  >     > > yamahata
  >     >
  > 
  >     --
  >     yamahata
  > 
  
  -- 
  yamahata
    

[-- Attachment #2: Type: text/html, Size: 5786 bytes --]

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?express support

[Gui Jianfeng]

Hi Yamahata

I'm wondering if there're any PCI-e device emulated by QEmu?
And I think the hogplug patches are in this repo, right?

Thanks,
Gui

Isaku Yamahata wrote:
> Okay. Can you please try git clone again?
> 
> On Wed, Apr 20, 2011 at 06:41:56PM -0500, Adnan Khaleel wrote:
>> Something is still wrong,
>>
>> I get the following errors now:
>>
>> :
>> error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users/
>> akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
>> pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
>> error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under http://
>> people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
>> Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
>> while processing commit 0000000000000000000000000000000000000000.
>> rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/
>> qemu/.git/clone-tmp': Directory not empty
>>
>> Adnan
>>
>>
>>     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
>>     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
>>     To: Hu Tao [mailto:hutao@cn.fujitsu.com], Adnan Khaleel
>>     [mailto:adnan@khaleel.us]
>>     Cc: qemu-devel@nongnu.org
>>     Sent: Wed, 20 Apr 2011 17:46:44 -0500
>>     Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci
>>     express support
>>
>>     I forgot to changet its HEAD. Now it's fixed.
>>     So please change the branch manually or clone the repo again.
>>
>>     On Tue, Apr 19, 2011 at 04:58:32PM +0800, Hu Tao wrote:
>>     > On Tue, Apr 19, 2011 at 05:51:27PM +0900, Isaku Yamahata wrote:
>>     > > On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
>>     > > > On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
>>     > > > > This patch series adds basic q35 chipset support for native pci
>>     express
>>     > > > > support. Some bios related patches are still needed.
>>     > > > > For those who want to try it, the following repo is avaiable.
>>     > > > > (vgabios doesn't need patches, so use the upstream one)
>>     > > > >
>>     > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
>>     qemu
>>     > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
>>     seabios
>>     > > >
>>     > > > Hi,
>>     > > >
>>     > > > When I visit the links, the pages say 'You dont have permission'.
>>     Could
>>     > > > you make these git-repos avaiable again? Thanks in advance.
>>     > >
>>     > > The link is not for human-reading. Just issue the git command.
>>     >
>>     > Done. Thanks:)
>>     >
>>     > > --
>>     > > yamahata
>>     >
>>
>>     --
>>     yamahata
>>
> 

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci?express support

[Isaku Yamahata]

Okay. Can you please try git clone again?

On Wed, Apr 20, 2011 at 06:41:56PM -0500, Adnan Khaleel wrote:
> Something is still wrong,
> 
> I get the following errors now:
> 
> :
> error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users/
> akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/
> pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
> error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under http://
> people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
> Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
> while processing commit 0000000000000000000000000000000000000000.
> rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/
> qemu/.git/clone-tmp': Directory not empty
> 
> Adnan
> 
> 
>     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
>     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
>     To: Hu Tao [mailto:hutao@cn.fujitsu.com], Adnan Khaleel
>     [mailto:adnan@khaleel.us]
>     Cc: qemu-devel@nongnu.org
>     Sent: Wed, 20 Apr 2011 17:46:44 -0500
>     Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci
>     express support
> 
>     I forgot to changet its HEAD. Now it's fixed.
>     So please change the branch manually or clone the repo again.
> 
>     On Tue, Apr 19, 2011 at 04:58:32PM +0800, Hu Tao wrote:
>     > On Tue, Apr 19, 2011 at 05:51:27PM +0900, Isaku Yamahata wrote:
>     > > On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
>     > > > On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
>     > > > > This patch series adds basic q35 chipset support for native pci
>     express
>     > > > > support. Some bios related patches are still needed.
>     > > > > For those who want to try it, the following repo is avaiable.
>     > > > > (vgabios doesn't need patches, so use the upstream one)
>     > > > >
>     > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
>     qemu
>     > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/
>     seabios
>     > > >
>     > > > Hi,
>     > > >
>     > > > When I visit the links, the pages say 'You dont have permission'.
>     Could
>     > > > you make these git-repos avaiable again? Thanks in advance.
>     > >
>     > > The link is not for human-reading. Just issue the git command.
>     >
>     > Done. Thanks:)
>     >
>     > > --
>     > > yamahata
>     >
> 
>     --
>     yamahata
> 

-- 
yamahata

Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Adnan Khaleel]

[-- Attachment #1: Type: text/plain, Size: 2177 bytes --]

Something is still wrong,


I get the following errors now:


:

error: cannot unpack fffd440d2ca664a03ee83eabc00107eaf74d7af4 from /users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/objects/pack/pack-c0c6d1b7fc8ae79abf99bfb6a402b50e2ec98557.pack
error: Unable to find ad620c29c2da573e3a5f13f5b1eb2694fee64cfb under http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu/
Cannot obtain needed none ad620c29c2da573e3a5f13f5b1eb2694fee64cfb
while processing commit 0000000000000000000000000000000000000000.
rm: cannot remove directory `/users/akhaleel/akhaleel/MergeSpace/qemu_0.14_q35/qemu/.git/clone-tmp': Directory not empty


Adnan

  _____  

From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
To: Hu Tao [mailto:hutao@cn.fujitsu.com], Adnan Khaleel [mailto:adnan@khaleel.us]
Cc: qemu-devel@nongnu.org
Sent: Wed, 20 Apr 2011 17:46:44 -0500
Subject: Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

I forgot to changet its HEAD. Now it's fixed.
  So please change the branch manually or clone the repo again.
  
  On Tue, Apr 19, 2011 at 04:58:32PM +0800, Hu Tao wrote:
  > On Tue, Apr 19, 2011 at 05:51:27PM +0900, Isaku Yamahata wrote:
  > > On Tue, Apr 19, 2011 at 04:28:01PM +0800, Hu Tao wrote:
  > > > On Wed, Mar 16, 2011 at 06:29:11PM +0900, Isaku Yamahata wrote:
  > > > > This patch series adds basic q35 chipset support for native pci express
  > > > > support. Some bios related patches are still needed.
  > > > > For those who want to try it, the following repo is avaiable.
  > > > > (vgabios doesn't need patches, so use the upstream one)
  > > > > 
  > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/qemu
  > > > > git clone http://people.valinux.co.jp/~yamahata/qemu/q35/20110316/seabios
  > > > 
  > > > Hi,
  > > > 
  > > > When I visit the links, the pages say 'You dont have permission'. Could
  > > > you make these git-repos avaiable again?  Thanks in advance.
  > > 
  > > The link is not for human-reading. Just issue the git command.
  > 
  > Done. Thanks:)
  > 
  > > -- 
  > > yamahata
  > 
  
  -- 
  yamahata
    

[-- Attachment #2: Type: text/html, Size: 3151 bytes --]