[PATCH 1/2] drm/i915: Use existing function instead of open-coding fence reg clear.

[PATCH 1/2] drm/i915: Use existing function instead of open-coding fence reg clear.

[Eric Anholt]

This is once less place to miss a new INTEL_INFO(dev)->gen update now.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_gem.c |   21 +++------------------
 1 files changed, 3 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bf32527..4304f74 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3856,25 +3856,10 @@ i915_gem_load(struct drm_device *dev)
 		dev_priv->num_fence_regs = 8;
 
 	/* Initialize fence registers to zero */
-	switch (INTEL_INFO(dev)->gen) {
-	case 6:
-		for (i = 0; i < 16; i++)
-			I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
-		break;
-	case 5:
-	case 4:
-		for (i = 0; i < 16; i++)
-			I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
-		break;
-	case 3:
-		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-			for (i = 0; i < 8; i++)
-				I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
-	case 2:
-		for (i = 0; i < 8; i++)
-			I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
-		break;
+	for (i = 0; i < dev_priv->num_fence_regs; i++) {
+		i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
 	}
+
 	i915_gem_detect_bit_6_swizzle(dev);
 	init_waitqueue_head(&dev_priv->pending_flip_queue);
 
-- 
1.7.4.4

[PATCH 2/2] drm/i915: Add support for fence registers on Ivybridge.

[Eric Anholt]

The registers are the same as on Sandybridge.  Fixes scrambled display
in X when it does software drawing to the GTT, and scans the results
out as tiled.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_gem.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4304f74..c628903 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2673,6 +2673,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
 update:
 	obj->tiling_changed = false;
 	switch (INTEL_INFO(dev)->gen) {
+	case 7:
 	case 6:
 		ret = sandybridge_write_fence_reg(obj, pipelined);
 		break;
@@ -2706,6 +2707,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev,
 	uint32_t fence_reg = reg - dev_priv->fence_regs;
 
 	switch (INTEL_INFO(dev)->gen) {
+	case 7:
 	case 6:
 		I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
 		break;
-- 
1.7.4.4

Re: [PATCH 1/2] drm/i915: Use existing function instead of open-coding fence reg clear.

[Jesse Barnes]

On Fri,  6 May 2011 14:03:31 -0700
Eric Anholt <eric@anholt.net> wrote:

> This is once less place to miss a new INTEL_INFO(dev)->gen update now.
> 
> Signed-off-by: Eric Anholt <eric@anholt.net>
> ---
>  drivers/gpu/drm/i915/i915_gem.c |   21 +++------------------
>  1 files changed, 3 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index bf32527..4304f74 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3856,25 +3856,10 @@ i915_gem_load(struct drm_device *dev)
>  		dev_priv->num_fence_regs = 8;
>  
>  	/* Initialize fence registers to zero */
> -	switch (INTEL_INFO(dev)->gen) {
> -	case 6:
> -		for (i = 0; i < 16; i++)
> -			I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
> -		break;
> -	case 5:
> -	case 4:
> -		for (i = 0; i < 16; i++)
> -			I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
> -		break;
> -	case 3:
> -		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> -			for (i = 0; i < 8; i++)
> -				I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
> -	case 2:
> -		for (i = 0; i < 8; i++)
> -			I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
> -		break;
> +	for (i = 0; i < dev_priv->num_fence_regs; i++) {
> +		i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
>  	}
> +
>  	i915_gem_detect_bit_6_swizzle(dev);
>  	init_waitqueue_head(&dev_priv->pending_flip_queue);
>  

Aside from the extra curly braces:

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 2/2] drm/i915: Add support for fence registers on Ivybridge.

[Jesse Barnes]

On Fri,  6 May 2011 14:03:32 -0700
Eric Anholt <eric@anholt.net> wrote:

> The registers are the same as on Sandybridge.  Fixes scrambled display
> in X when it does software drawing to the GTT, and scans the results
> out as tiled.
> 
> Signed-off-by: Eric Anholt <eric@anholt.net>
> ---
>  drivers/gpu/drm/i915/i915_gem.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4304f74..c628903 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2673,6 +2673,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
>  update:
>  	obj->tiling_changed = false;
>  	switch (INTEL_INFO(dev)->gen) {
> +	case 7:
>  	case 6:
>  		ret = sandybridge_write_fence_reg(obj, pipelined);
>  		break;
> @@ -2706,6 +2707,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev,
>  	uint32_t fence_reg = reg - dev_priv->fence_regs;
>  
>  	switch (INTEL_INFO(dev)->gen) {
> +	case 7:
>  	case 6:
>  		I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
>  		break;

Yep, definitely needed.  I'll factor out the tiled stuff I added to
testdisplay (for testing video sprites) so we can catch this stuff more
easily.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center