* question on memory barriers
@ 2011-07-26 11:39 Oliver Neukum
2011-07-26 14:18 ` Alan Stern
0 siblings, 1 reply; 2+ messages in thread
From: Oliver Neukum @ 2011-07-26 11:39 UTC (permalink / raw)
To: Alan Stern, linux-arm-msm
Hi,
this code made me think:
/* Give this link TRB to the hardware */
wmb();
next->link.control ^= cpu_to_le32(TRB_CYCLE);
Can you do this or may there be a CPU that speculatively writes before
it reads next->link.control ?
Regards
Oliver
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: question on memory barriers
2011-07-26 11:39 question on memory barriers Oliver Neukum
@ 2011-07-26 14:18 ` Alan Stern
0 siblings, 0 replies; 2+ messages in thread
From: Alan Stern @ 2011-07-26 14:18 UTC (permalink / raw)
To: Oliver Neukum; +Cc: linux-arm-msm
On Tue, 26 Jul 2011, Oliver Neukum wrote:
> Hi,
>
> this code made me think:
>
> /* Give this link TRB to the hardware */
> wmb();
> next->link.control ^= cpu_to_le32(TRB_CYCLE);
>
> Can you do this or may there be a CPU that speculatively writes before
> it reads next->link.control ?
CPUs never do speculative writes. And even if they did, the wmb()
would prevent the speculative write from preceding any statement that
comes before the memory barrier.
Alan Stern
^ permalink raw reply [flat|nested] 2+ messages in thread
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2011-07-26 11:39 question on memory barriers Oliver Neukum
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