[PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Kirill A. Shutemov]

Between "clean D line..." and "invalidate I line" operations in
v7_coherent_user_range(), the memory page may get swapped out.
And the fault on "invalidate I line" could not be properly handled
causing the oops.

In ARMv6 "external abort on linefetch" replaced by "instruction cache
maintenance fault". Let's handle it as translation fault. It fixes the
issue.

I'm not sure if it's reasonable to check arch version in run-time.
Let's do it in compile time for now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
---

Sorry for resend. I've made mistake in maillist address.

---
 arch/arm/mm/fault.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 9d40c34..7f193ea 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -463,7 +463,12 @@ static struct fsr_info {
 	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
 	{ do_bad,		SIGKILL, 0,		"terminal exception"		   },
 	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
+/* Do we need runtime check ? */
+#if __LINUX_ARM_ARCH__ < 6
 	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
+#else
+	{ do_translation_fault,	SIGSEGV, SEGV_MAPPER,	"I-cache maintenance
fault"	   },
+#endif
 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"section translation
fault"	   },
 	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
 	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"page translation fault"	   },
-- 
1.7.0.4

[PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Kirill A. Shutemov]

Between "clean D line..." and "invalidate I line" operations in
v7_coherent_user_range(), the memory page may get swapped out.
And the fault on "invalidate I line" could not be properly handled
causing the oops.

In ARMv6 "external abort on linefetch" replaced by "instruction cache
maintenance fault". Let's handle it as translation fault. It fixes the
issue.

I'm not sure if it's reasonable to check arch version in run-time.
Let's do it in compile time for now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
---

Sorry for resend. I've made mistake in maillist address.

---
 arch/arm/mm/fault.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 9d40c34..7f193ea 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -463,7 +463,12 @@ static struct fsr_info {
 	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
 	{ do_bad,		SIGKILL, 0,		"terminal exception"		   },
 	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
+/* Do we need runtime check ? */
+#if __LINUX_ARM_ARCH__ < 6
 	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
+#else
+	{ do_translation_fault,	SIGSEGV, SEGV_MAPPER,	"I-cache maintenance
fault"	   },
+#endif
 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"section translation
fault"	   },
 	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
 	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"page translation fault"	   },
-- 
1.7.0.4

Re: [PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Catalin Marinas]

On Tue, 2010-05-11 at 11:33 +0100, Kirill A. Shutemov wrote:
> Between "clean D line..." and "invalidate I line" operations in
> v7_coherent_user_range(), the memory page may get swapped out.
> And the fault on "invalidate I line" could not be properly handled
> causing the oops.
> 
> In ARMv6 "external abort on linefetch" replaced by "instruction cache
> maintenance fault". Let's handle it as translation fault. It fixes the
> issue.
> 
> I'm not sure if it's reasonable to check arch version in run-time.
> Let's do it in compile time for now.
> 
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>

FWIW:

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

-- 
Catalin

[PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Catalin Marinas]

On Tue, 2010-05-11 at 11:33 +0100, Kirill A. Shutemov wrote:
> Between "clean D line..." and "invalidate I line" operations in
> v7_coherent_user_range(), the memory page may get swapped out.
> And the fault on "invalidate I line" could not be properly handled
> causing the oops.
> 
> In ARMv6 "external abort on linefetch" replaced by "instruction cache
> maintenance fault". Let's handle it as translation fault. It fixes the
> issue.
> 
> I'm not sure if it's reasonable to check arch version in run-time.
> Let's do it in compile time for now.
> 
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>

FWIW:

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

-- 
Catalin

Re: [PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Catalin Marinas]

On Tue, 2010-05-11 at 11:33 +0100, Kirill A. Shutemov wrote:
> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> index 9d40c34..7f193ea 100644
> --- a/arch/arm/mm/fault.c
> +++ b/arch/arm/mm/fault.c
> @@ -463,7 +463,12 @@ static struct fsr_info {
>         { do_bad,               SIGILL,  BUS_ADRALN,    "alignment exception"              },
>         { do_bad,               SIGKILL, 0,             "terminal exception"               },
>         { do_bad,               SIGILL,  BUS_ADRALN,    "alignment exception"              },
> +/* Do we need runtime check ? */
> +#if __LINUX_ARM_ARCH__ < 6
>         { do_bad,               SIGBUS,  0,             "external abort on linefetch"      },
> +#else
> +       { do_translation_fault, SIGSEGV, SEGV_MAPPER,   "I-cache maintenance
> fault"     },
> +#endif

Apart from line wrapping, it should be SEGV_MAPERR above.

-- 
Catalin

[PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Catalin Marinas]

On Tue, 2010-05-11 at 11:33 +0100, Kirill A. Shutemov wrote:
> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> index 9d40c34..7f193ea 100644
> --- a/arch/arm/mm/fault.c
> +++ b/arch/arm/mm/fault.c
> @@ -463,7 +463,12 @@ static struct fsr_info {
>         { do_bad,               SIGILL,  BUS_ADRALN,    "alignment exception"              },
>         { do_bad,               SIGKILL, 0,             "terminal exception"               },
>         { do_bad,               SIGILL,  BUS_ADRALN,    "alignment exception"              },
> +/* Do we need runtime check ? */
> +#if __LINUX_ARM_ARCH__ < 6
>         { do_bad,               SIGBUS,  0,             "external abort on linefetch"      },
> +#else
> +       { do_translation_fault, SIGSEGV, SEGV_MAPPER,   "I-cache maintenance
> fault"     },
> +#endif

Apart from line wrapping, it should be SEGV_MAPERR above.

-- 
Catalin

Re: [PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Uwe Kleine-König]

Hello,

On Tue, May 11, 2010 at 01:33:14PM +0300, Kirill A. Shutemov wrote:
> Between "clean D line..." and "invalidate I line" operations in
> v7_coherent_user_range(), the memory page may get swapped out.
> And the fault on "invalidate I line" could not be properly handled
> causing the oops.
> 
> In ARMv6 "external abort on linefetch" replaced by "instruction cache
> maintenance fault". Let's handle it as translation fault. It fixes the
> issue.
> 
> I'm not sure if it's reasonable to check arch version in run-time.
> Let's do it in compile time for now.
> 
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
I found this patch in Catalin's stack that I picked up to get support
for Cortex-M3. Is this still relevant?

Best regards
Uwe

> Sorry for resend. I've made mistake in maillist address.
> 
> ---
>  arch/arm/mm/fault.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> index 9d40c34..7f193ea 100644
> --- a/arch/arm/mm/fault.c
> +++ b/arch/arm/mm/fault.c
> @@ -463,7 +463,12 @@ static struct fsr_info {
>  	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
>  	{ do_bad,		SIGKILL, 0,		"terminal exception"		   },
>  	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
> +/* Do we need runtime check ? */
> +#if __LINUX_ARM_ARCH__ < 6
>  	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
> +#else
> +	{ do_translation_fault,	SIGSEGV, SEGV_MAPPER,	"I-cache maintenance
> fault"	   },
> +#endif
>  	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"section translation
> fault"	   },
>  	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
>  	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"page translation fault"	   },
> -- 
> 1.7.0.4
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Uwe Kleine-König]

Hello,

On Tue, May 11, 2010 at 01:33:14PM +0300, Kirill A. Shutemov wrote:
> Between "clean D line..." and "invalidate I line" operations in
> v7_coherent_user_range(), the memory page may get swapped out.
> And the fault on "invalidate I line" could not be properly handled
> causing the oops.
> 
> In ARMv6 "external abort on linefetch" replaced by "instruction cache
> maintenance fault". Let's handle it as translation fault. It fixes the
> issue.
> 
> I'm not sure if it's reasonable to check arch version in run-time.
> Let's do it in compile time for now.
> 
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
I found this patch in Catalin's stack that I picked up to get support
for Cortex-M3. Is this still relevant?

Best regards
Uwe

> Sorry for resend. I've made mistake in maillist address.
> 
> ---
>  arch/arm/mm/fault.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> index 9d40c34..7f193ea 100644
> --- a/arch/arm/mm/fault.c
> +++ b/arch/arm/mm/fault.c
> @@ -463,7 +463,12 @@ static struct fsr_info {
>  	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
>  	{ do_bad,		SIGKILL, 0,		"terminal exception"		   },
>  	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
> +/* Do we need runtime check ? */
> +#if __LINUX_ARM_ARCH__ < 6
>  	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
> +#else
> +	{ do_translation_fault,	SIGSEGV, SEGV_MAPPER,	"I-cache maintenance
> fault"	   },
> +#endif
>  	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"section translation
> fault"	   },
>  	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
>  	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"page translation fault"	   },
> -- 
> 1.7.0.4
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Kirill A. Shutemov]

On Thu, Dec 15, 2011 at 10:56:49PM +0100, Uwe Kleine-König wrote:
> Hello,
> 
> On Tue, May 11, 2010 at 01:33:14PM +0300, Kirill A. Shutemov wrote:
> > Between "clean D line..." and "invalidate I line" operations in
> > v7_coherent_user_range(), the memory page may get swapped out.
> > And the fault on "invalidate I line" could not be properly handled
> > causing the oops.
> > 
> > In ARMv6 "external abort on linefetch" replaced by "instruction cache
> > maintenance fault". Let's handle it as translation fault. It fixes the
> > issue.
> > 
> > I'm not sure if it's reasonable to check arch version in run-time.
> > Let's do it in compile time for now.
> > 
> > Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
> > Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
> I found this patch in Catalin's stack that I picked up to get support
> for Cortex-M3. Is this still relevant?

It's in upstream. See 8c0b742.

> 
> Best regards
> Uwe
> 
> > Sorry for resend. I've made mistake in maillist address.
> > 
> > ---
> >  arch/arm/mm/fault.c |    5 +++++
> >  1 files changed, 5 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> > index 9d40c34..7f193ea 100644
> > --- a/arch/arm/mm/fault.c
> > +++ b/arch/arm/mm/fault.c
> > @@ -463,7 +463,12 @@ static struct fsr_info {
> >  	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
> >  	{ do_bad,		SIGKILL, 0,		"terminal exception"		   },
> >  	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
> > +/* Do we need runtime check ? */
> > +#if __LINUX_ARM_ARCH__ < 6
> >  	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
> > +#else
> > +	{ do_translation_fault,	SIGSEGV, SEGV_MAPPER,	"I-cache maintenance
> > fault"	   },
> > +#endif
> >  	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"section translation
> > fault"	   },
> >  	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
> >  	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"page translation fault"	   },
> > -- 
> > 1.7.0.4
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 
> 
> -- 
> Pengutronix e.K.                           | Uwe Kleine-König            |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |

-- 
 Kirill A. Shutemov

[PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Kirill A. Shutemov]

On Thu, Dec 15, 2011 at 10:56:49PM +0100, Uwe Kleine-K?nig wrote:
> Hello,
> 
> On Tue, May 11, 2010 at 01:33:14PM +0300, Kirill A. Shutemov wrote:
> > Between "clean D line..." and "invalidate I line" operations in
> > v7_coherent_user_range(), the memory page may get swapped out.
> > And the fault on "invalidate I line" could not be properly handled
> > causing the oops.
> > 
> > In ARMv6 "external abort on linefetch" replaced by "instruction cache
> > maintenance fault". Let's handle it as translation fault. It fixes the
> > issue.
> > 
> > I'm not sure if it's reasonable to check arch version in run-time.
> > Let's do it in compile time for now.
> > 
> > Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
> > Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
> I found this patch in Catalin's stack that I picked up to get support
> for Cortex-M3. Is this still relevant?

It's in upstream. See 8c0b742.

> 
> Best regards
> Uwe
> 
> > Sorry for resend. I've made mistake in maillist address.
> > 
> > ---
> >  arch/arm/mm/fault.c |    5 +++++
> >  1 files changed, 5 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> > index 9d40c34..7f193ea 100644
> > --- a/arch/arm/mm/fault.c
> > +++ b/arch/arm/mm/fault.c
> > @@ -463,7 +463,12 @@ static struct fsr_info {
> >  	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
> >  	{ do_bad,		SIGKILL, 0,		"terminal exception"		   },
> >  	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
> > +/* Do we need runtime check ? */
> > +#if __LINUX_ARM_ARCH__ < 6
> >  	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
> > +#else
> > +	{ do_translation_fault,	SIGSEGV, SEGV_MAPPER,	"I-cache maintenance
> > fault"	   },
> > +#endif
> >  	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"section translation
> > fault"	   },
> >  	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
> >  	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"page translation fault"	   },
> > -- 
> > 1.7.0.4
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 
> 
> -- 
> Pengutronix e.K.                           | Uwe Kleine-K?nig            |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |

-- 
 Kirill A. Shutemov

Re: [PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Uwe Kleine-König]

Hallo,

On Fri, Dec 16, 2011 at 04:22:05AM +0200, Kirill A. Shutemov wrote:
> On Thu, Dec 15, 2011 at 10:56:49PM +0100, Uwe Kleine-König wrote:
> > Hello,
> > 
> > On Tue, May 11, 2010 at 01:33:14PM +0300, Kirill A. Shutemov wrote:
> > > Between "clean D line..." and "invalidate I line" operations in
> > > v7_coherent_user_range(), the memory page may get swapped out.
> > > And the fault on "invalidate I line" could not be properly handled
> > > causing the oops.
> > > 
> > > In ARMv6 "external abort on linefetch" replaced by "instruction cache
> > > maintenance fault". Let's handle it as translation fault. It fixes the
> > > issue.
> > > 
> > > I'm not sure if it's reasonable to check arch version in run-time.
> > > Let's do it in compile time for now.
> > > 
> > > Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
> > > Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
> > I found this patch in Catalin's stack that I picked up to get support
> > for Cortex-M3. Is this still relevant?
> 
> It's in upstream. See 8c0b742.
Ah, I missed that because it applies again on top of 3.2-rc because of

	993bf4e (ARM: 6256/1: Check arch version and modify fsr_info[] depends on it at runtime)

Thanks and sorry for the noise,
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH v2] [RESEND] Handle instruction cache maintenance fault properly

[Uwe Kleine-König]

Hallo,

On Fri, Dec 16, 2011 at 04:22:05AM +0200, Kirill A. Shutemov wrote:
> On Thu, Dec 15, 2011 at 10:56:49PM +0100, Uwe Kleine-K?nig wrote:
> > Hello,
> > 
> > On Tue, May 11, 2010 at 01:33:14PM +0300, Kirill A. Shutemov wrote:
> > > Between "clean D line..." and "invalidate I line" operations in
> > > v7_coherent_user_range(), the memory page may get swapped out.
> > > And the fault on "invalidate I line" could not be properly handled
> > > causing the oops.
> > > 
> > > In ARMv6 "external abort on linefetch" replaced by "instruction cache
> > > maintenance fault". Let's handle it as translation fault. It fixes the
> > > issue.
> > > 
> > > I'm not sure if it's reasonable to check arch version in run-time.
> > > Let's do it in compile time for now.
> > > 
> > > Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
> > > Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
> > I found this patch in Catalin's stack that I picked up to get support
> > for Cortex-M3. Is this still relevant?
> 
> It's in upstream. See 8c0b742.
Ah, I missed that because it applies again on top of 3.2-rc because of

	993bf4e (ARM: 6256/1: Check arch version and modify fsr_info[] depends on it at runtime)

Thanks and sorry for the noise,
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |