* [PATCH v6 0/9] Versatile Express DT support
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
Hi All,
This is the last (at least this year) version of the patches. I've added
Tested-by: Tixy to the patches that hasn't change since v5. I didn't add
Arnd's and Rob's Acked-bys as the code changed significantly since. If
still applicable, I'll add then on the first opportunity.
Arnd, Russell, if you think that the code is ready enough for 3.3, please
pull from this branch based on today's tip (v3.2-rc5+):
8<---------------------------------------------------------------------
The following changes since commit 55b02d2f4445ad625213817a1736bf2884d32547:
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux (2011-12-14 19:45:40 -0800)
are available in the git repository at:
git://git.linaro.org/people/pawelmoll/linux.git vexpress-dt
8<---------------------------------------------------------------------
I also have a "vexpress-dt-rmk-devel-stable" branch there, based on
today's Russell's devel-stable. The only difference is "handle_irq"
added to DT machine description.
If there are still some issues I'll address them once I'm back from
holiday (today it's the last day before I loose all access to the
Internet for a month).
Changes since v5:
* As suggested by Russell, DT-based local timers take precedence over
statically defined ones (so the twd_base if overwritten).
* Minor redactorial changes in DT-based SMP initialization (the logic
stays the same).
* Added last missing device node to the V2M trees: "arm,vexpress-vram".
* Similarly to "arm,vexpress-cf" added "arm,vexpress-psram" to the
relevant node, just in case we need to detect it in future.
Tested on:
- V2P-CA9 with ATAGs (both with a ATAGs-only and ATAGs+DT kernels).
- V2P-CA9 with DT
- V2P-CA5s with DT
- V2P-CA15 with DT
- V2F-2XV6 Cortex-A7 SMM with DT
Thanks to all involved for your help!
8<---------------------------------------------------------------------
Pawel Moll (9):
ARM: versatile: Add missing ENDPROC to headsmp.S
ARM: vexpress: Get rid of MMIO_P2V
ARM: versatile: Map local timers using Device Tree when possible
ARM: vexpress: Use FDT data in platform SMP calls
ARM: vexpress: Add Device Tree support
ARM: vexpress: Motherboard RS1 memory map support
ARM: vexpress: Add Device Tree for V2P-CA5s core tile
ARM: vexpress: Add Device Tree for V2P-CA9 core tile
ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++++++++++
arch/arm/Kconfig | 2 +-
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 201 ++++++++++++++
arch/arm/boot/dts/vexpress-v2m.dtsi | 200 ++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 155 +++++++++++
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 160 +++++++++++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190 +++++++++++++
arch/arm/include/asm/hardware/arm_timer.h | 5 +
arch/arm/mach-realview/platsmp.c | 3 +-
arch/arm/mach-vexpress/Kconfig | 45 +++-
arch/arm/mach-vexpress/Makefile.boot | 6 +
arch/arm/mach-vexpress/core.h | 9 +-
arch/arm/mach-vexpress/ct-ca9x4.c | 48 +---
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++-
arch/arm/mach-vexpress/include/mach/irqs.h | 2 +-
arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++--
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +-
arch/arm/mach-vexpress/platsmp.c | 153 ++++++++++-
arch/arm/mach-vexpress/v2m.c | 282 ++++++++++++++++++--
arch/arm/mm/Kconfig | 2 +-
arch/arm/plat-versatile/headsmp.S | 1 +
arch/arm/plat-versatile/localtimer.c | 12 +
23 files changed, 1621 insertions(+), 120 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
--
1.7.5.4
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 0/9] Versatile Express DT support
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi All,
This is the last (at least this year) version of the patches. I've added
Tested-by: Tixy to the patches that hasn't change since v5. I didn't add
Arnd's and Rob's Acked-bys as the code changed significantly since. If
still applicable, I'll add then on the first opportunity.
Arnd, Russell, if you think that the code is ready enough for 3.3, please
pull from this branch based on today's tip (v3.2-rc5+):
8<---------------------------------------------------------------------
The following changes since commit 55b02d2f4445ad625213817a1736bf2884d32547:
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux (2011-12-14 19:45:40 -0800)
are available in the git repository at:
git://git.linaro.org/people/pawelmoll/linux.git vexpress-dt
8<---------------------------------------------------------------------
I also have a "vexpress-dt-rmk-devel-stable" branch there, based on
today's Russell's devel-stable. The only difference is "handle_irq"
added to DT machine description.
If there are still some issues I'll address them once I'm back from
holiday (today it's the last day before I loose all access to the
Internet for a month).
Changes since v5:
* As suggested by Russell, DT-based local timers take precedence over
statically defined ones (so the twd_base if overwritten).
* Minor redactorial changes in DT-based SMP initialization (the logic
stays the same).
* Added last missing device node to the V2M trees: "arm,vexpress-vram".
* Similarly to "arm,vexpress-cf" added "arm,vexpress-psram" to the
relevant node, just in case we need to detect it in future.
Tested on:
- V2P-CA9 with ATAGs (both with a ATAGs-only and ATAGs+DT kernels).
- V2P-CA9 with DT
- V2P-CA5s with DT
- V2P-CA15 with DT
- V2F-2XV6 Cortex-A7 SMM with DT
Thanks to all involved for your help!
8<---------------------------------------------------------------------
Pawel Moll (9):
ARM: versatile: Add missing ENDPROC to headsmp.S
ARM: vexpress: Get rid of MMIO_P2V
ARM: versatile: Map local timers using Device Tree when possible
ARM: vexpress: Use FDT data in platform SMP calls
ARM: vexpress: Add Device Tree support
ARM: vexpress: Motherboard RS1 memory map support
ARM: vexpress: Add Device Tree for V2P-CA5s core tile
ARM: vexpress: Add Device Tree for V2P-CA9 core tile
ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++++++++++
arch/arm/Kconfig | 2 +-
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 201 ++++++++++++++
arch/arm/boot/dts/vexpress-v2m.dtsi | 200 ++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 155 +++++++++++
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 160 +++++++++++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190 +++++++++++++
arch/arm/include/asm/hardware/arm_timer.h | 5 +
arch/arm/mach-realview/platsmp.c | 3 +-
arch/arm/mach-vexpress/Kconfig | 45 +++-
arch/arm/mach-vexpress/Makefile.boot | 6 +
arch/arm/mach-vexpress/core.h | 9 +-
arch/arm/mach-vexpress/ct-ca9x4.c | 48 +---
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++-
arch/arm/mach-vexpress/include/mach/irqs.h | 2 +-
arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++--
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +-
arch/arm/mach-vexpress/platsmp.c | 153 ++++++++++-
arch/arm/mach-vexpress/v2m.c | 282 ++++++++++++++++++--
arch/arm/mm/Kconfig | 2 +-
arch/arm/plat-versatile/headsmp.S | 1 +
arch/arm/plat-versatile/localtimer.c | 12 +
23 files changed, 1621 insertions(+), 120 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
--
1.7.5.4
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 1/9] ARM: versatile: Add missing ENDPROC to headsmp.S
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
Once the ENDPROC is in place, BSYM() in not longer necessary
to get correct pointer to versatile_secondary_startup().
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/mach-realview/platsmp.c | 3 +--
arch/arm/mach-vexpress/platsmp.c | 4 +---
arch/arm/plat-versatile/headsmp.S | 1 +
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index e83c654..17c878d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -17,7 +17,6 @@
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
-#include <asm/unified.h>
#include <mach/board-eb.h>
#include <mach/board-pb11mp.h>
@@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
+ __raw_writel(virt_to_phys(versatile_secondary_startup),
__io_address(REALVIEW_SYS_FLAGSSET));
}
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 2b5f7ac..124ffb1 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -13,8 +13,6 @@
#include <linux/smp.h>
#include <linux/io.h>
-#include <asm/unified.h>
-
#include <mach/motherboard.h>
#define V2M_PA_CS7 0x10000000
@@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* secondary CPU branches to this address.
*/
writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
- writel(BSYM(virt_to_phys(versatile_secondary_startup)),
+ writel(virt_to_phys(versatile_secondary_startup),
MMIO_P2V(V2M_SYS_FLAGSSET));
}
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index d397a1f..dd703ef 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -38,3 +38,4 @@ pen: ldr r7, [r6]
.align
1: .long .
.long pen_release
+ENDPROC(versatile_secondary_startup)
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 1/9] ARM: versatile: Add missing ENDPROC to headsmp.S
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
Once the ENDPROC is in place, BSYM() in not longer necessary
to get correct pointer to versatile_secondary_startup().
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/mach-realview/platsmp.c | 3 +--
arch/arm/mach-vexpress/platsmp.c | 4 +---
arch/arm/plat-versatile/headsmp.S | 1 +
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index e83c654..17c878d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -17,7 +17,6 @@
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
-#include <asm/unified.h>
#include <mach/board-eb.h>
#include <mach/board-pb11mp.h>
@@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
+ __raw_writel(virt_to_phys(versatile_secondary_startup),
__io_address(REALVIEW_SYS_FLAGSSET));
}
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 2b5f7ac..124ffb1 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -13,8 +13,6 @@
#include <linux/smp.h>
#include <linux/io.h>
-#include <asm/unified.h>
-
#include <mach/motherboard.h>
#define V2M_PA_CS7 0x10000000
@@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* secondary CPU branches to this address.
*/
writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
- writel(BSYM(virt_to_phys(versatile_secondary_startup)),
+ writel(virt_to_phys(versatile_secondary_startup),
MMIO_P2V(V2M_SYS_FLAGSSET));
}
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index d397a1f..dd703ef 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -38,3 +38,4 @@ pen: ldr r7, [r6]
.align
1: .long .
.long pen_release
+ENDPROC(versatile_secondary_startup)
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 2/9] ARM: vexpress: Get rid of MMIO_P2V
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch gets rid of the MMIO_P2V and __MMIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/include/asm/hardware/arm_timer.h | 5 ++
arch/arm/mach-vexpress/core.h | 9 ++-
arch/arm/mach-vexpress/ct-ca9x4.c | 48 +++------------
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 ++---
arch/arm/mach-vexpress/include/mach/motherboard.h | 52 ++++++++--------
arch/arm/mach-vexpress/platsmp.c | 5 +-
arch/arm/mach-vexpress/v2m.c | 68 ++++++++++++++-------
7 files changed, 98 insertions(+), 102 deletions(-)
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7b..d6030ff 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
*
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
* can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
*/
+#define TIMER_1_BASE 0x00
+#define TIMER_2_BASE 0x20
+
#define TIMER_LOAD 0x00 /* ACVR rw */
#define TIMER_VALUE 0x04 /* ACVR ro */
#define TIMER_CTRL 0x08 /* ACVR rw */
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f439715..75a640a 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x) (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
-#define MMIO_P2V(x) ((void __iomem *)__MMIO_P2V(x))
-
#define AMBA_DEVICE(name,busid,base,plat) \
struct amba_device name##_device = { \
.dev = { \
@@ -17,3 +14,9 @@ struct amba_device name##_device = { \
.irq = IRQ_##base, \
/* .dma = DMA_##base,*/ \
}
+
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH ((void __iomem *)0xf8000000)
+
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH ((void __iomem *)0xf8200000)
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836..743a147 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,29 @@
#include <plat/clcd.h>
-#define V2M_PA_CS7 0x10000000
-
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
{
- .virtual = __MMIO_P2V(CT_CA9X4_MPIC),
- .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
- .pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = __MMIO_P2V(CT_CA9X4_L2CC),
- .pfn = __phys_to_pfn(CT_CA9X4_L2CC),
- .length = SZ_4K,
- .type = MT_DEVICE,
+ .virtual = (unsigned long)V2T_PERIPH,
+ .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
},
};
static void __init ct_ca9x4_map_io(void)
{
#ifdef CONFIG_LOCAL_TIMERS
- twd_base = MMIO_P2V(A9_MPCORE_TWD);
+ twd_base = V2T_PERIPH + A9_MPCORE_TWD;
#endif
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
static void __init ct_ca9x4_init_irq(void)
{
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
- MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
- writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- "ct-timer0");
+ gic_init(0, 29, V2T_PERIPH + A9_MPCORE_GIC_DIST,
+ V2T_PERIPH + A9_MPCORE_GIC_CPU);
}
-static struct sys_timer ct_ca9x4_timer = {
- .init = ct_ca9x4_timer_init,
-};
-#endif
-
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -201,7 +173,7 @@ static void __init ct_ca9x4_init(void)
int i;
#ifdef CONFIG_CACHE_L2X0
- void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+ void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
/* set RAM latencies to 1 cycle for this core tile. */
writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -219,7 +191,7 @@ static void __init ct_ca9x4_init(void)
#ifdef CONFIG_SMP
static void ct_ca9x4_init_cpu_map(void)
{
- int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
+ int i, ncores = scu_get_core_count(V2T_PERIPH + A9_MPCORE_SCU);
if (ncores > nr_cpu_ids) {
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
@@ -235,7 +207,7 @@ static void ct_ca9x4_init_cpu_map(void)
static void ct_ca9x4_smp_enable(unsigned int max_cpus)
{
- scu_enable(MMIO_P2V(A9_MPCORE_SCU));
+ scu_enable(V2T_PERIPH + A9_MPCORE_SCU);
}
#endif
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index a34d3d4..8f962fb 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -22,14 +22,11 @@
#define CT_CA9X4_SYSWDT (0x1e007000)
#define CT_CA9X4_L2CC (0x1e00a000)
-#define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000)
-#define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020)
-
-#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
-#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
-#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
-#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600)
-#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
+#define A9_MPCORE_SCU 0x0000
+#define A9_MPCORE_GIC_CPU 0x0100
+#define A9_MPCORE_GIT 0x0200
+#define A9_MPCORE_TWD 0x0600
+#define A9_MPCORE_GIC_DIST 0x1000
/*
* Interrupts. Those in {} are for AMBA devices
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 0a3a375..b4c498c 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -39,33 +39,30 @@
#define V2M_CF (V2M_PA_CS7 + 0x0001a000)
#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000)
-#define V2M_SYS_ID (V2M_SYSREGS + 0x000)
-#define V2M_SYS_SW (V2M_SYSREGS + 0x004)
-#define V2M_SYS_LED (V2M_SYSREGS + 0x008)
-#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024)
-#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034)
-#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_MCI (V2M_SYSREGS + 0x048)
-#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058)
-#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c)
-#define V2M_SYS_MISC (V2M_SYSREGS + 0x060)
-#define V2M_SYS_DMA (V2M_SYSREGS + 0x064)
-#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084)
-#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088)
-#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
-#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
-#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
-
-#define V2M_TIMER0 (V2M_TIMER01 + 0x000)
-#define V2M_TIMER1 (V2M_TIMER01 + 0x020)
-
-#define V2M_TIMER2 (V2M_TIMER23 + 0x000)
-#define V2M_TIMER3 (V2M_TIMER23 + 0x020)
+/*
+ * Offsets from SYSREGS base
+ */
+#define V2M_SYS_ID 0x000
+#define V2M_SYS_SW 0x004
+#define V2M_SYS_LED 0x008
+#define V2M_SYS_100HZ 0x024
+#define V2M_SYS_FLAGS 0x030
+#define V2M_SYS_FLAGSSET 0x030
+#define V2M_SYS_FLAGSCLR 0x034
+#define V2M_SYS_NVFLAGS 0x038
+#define V2M_SYS_NVFLAGSSET 0x038
+#define V2M_SYS_NVFLAGSCLR 0x03c
+#define V2M_SYS_MCI 0x048
+#define V2M_SYS_FLASH 0x03c
+#define V2M_SYS_CFGSW 0x058
+#define V2M_SYS_24MHZ 0x05c
+#define V2M_SYS_MISC 0x060
+#define V2M_SYS_DMA 0x064
+#define V2M_SYS_PROCID0 0x084
+#define V2M_SYS_PROCID1 0x088
+#define V2M_SYS_CFGDATA 0x0a0
+#define V2M_SYS_CFGCTRL 0x0a4
+#define V2M_SYS_CFGSTAT 0x0a8
/*
@@ -117,6 +114,7 @@
int v2m_cfg_write(u32 devfn, u32 data);
int v2m_cfg_read(u32 devfn, u32 *data);
+void v2m_flags_set(u32 data);
/*
* Core tile IDs
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 124ffb1..a1ed6d6 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -14,7 +14,6 @@
#include <linux/io.h>
#include <mach/motherboard.h>
-#define V2M_PA_CS7 0x10000000
#include "core.h"
@@ -43,7 +42,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
- writel(virt_to_phys(versatile_secondary_startup),
- MMIO_P2V(V2M_SYS_FLAGSSET));
+ v2m_flags_set(virt_to_phys(versatile_secondary_startup));
}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 1fafc32..05b4f46 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -39,29 +39,45 @@
static struct map_desc v2m_io_desc[] __initdata = {
{
- .virtual = __MMIO_P2V(V2M_PA_CS7),
+ .virtual = (unsigned long)V2M_PERIPH,
.pfn = __phys_to_pfn(V2M_PA_CS7),
.length = SZ_128K,
.type = MT_DEVICE,
},
};
-static void __init v2m_timer_init(void)
+static void __iomem *v2m_sysreg_base;
+
+static void __init v2m_sysctl_init(void __iomem *base)
{
u32 scctrl;
+ if (WARN_ON(!base))
+ return;
+
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
- scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
+ scctrl = readl(base + SCCTRL);
scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
- writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
+ writel(scctrl, base + SCCTRL);
+}
- writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
+static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
+{
+ if (WARN_ON(!base || irq == NO_IRQ))
+ return;
+
+ writel(0, base + TIMER_1_BASE + TIMER_CTRL);
+ writel(0, base + TIMER_2_BASE + TIMER_CTRL);
- sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
- sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
- "v2m-timer0");
+ sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
+ sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
+}
+
+static void __init v2m_timer_init(void)
+{
+ v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
+ v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
}
static struct sys_timer v2m_timer = {
@@ -81,14 +97,14 @@ int v2m_cfg_write(u32 devfn, u32 data)
devfn |= SYS_CFG_START | SYS_CFG_WRITE;
spin_lock(&v2m_cfg_lock);
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
- writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
+ writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
- writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
- writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+ writel(data, v2m_sysreg_base + V2M_SYS_CFGDATA);
+ writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
do {
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
} while (val == 0);
spin_unlock(&v2m_cfg_lock);
@@ -102,22 +118,28 @@ int v2m_cfg_read(u32 devfn, u32 *data)
devfn |= SYS_CFG_START;
spin_lock(&v2m_cfg_lock);
- writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
- writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+ writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
+ writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
mb();
do {
cpu_relax();
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
} while (val == 0);
- *data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
+ *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
spin_unlock(&v2m_cfg_lock);
return !!(val & SYS_CFG_ERR);
}
+void __init v2m_flags_set(u32 data)
+{
+ writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
+ writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
+}
+
static struct resource v2m_pcie_i2c_resource = {
.start = V2M_SERIAL_BUS_PCI,
@@ -203,7 +225,7 @@ static struct platform_device v2m_usb_device = {
static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
{
- writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
+ writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
}
static struct physmap_flash_data v2m_flash_data = {
@@ -257,7 +279,7 @@ static struct platform_device v2m_cf_device = {
static unsigned int v2m_mmci_status(struct device *dev)
{
- return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
+ return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
}
static struct mmci_platform_data v2m_mmci_data = {
@@ -370,7 +392,7 @@ static void __init v2m_init_early(void)
{
ct_desc->init_early();
clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
- versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+ versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
}
static void v2m_power_off(void)
@@ -399,7 +421,8 @@ static void __init v2m_populate_ct_desc(void)
u32 current_tile_id;
ct_desc = NULL;
- current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
+ current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
+ & V2M_CT_ID_MASK;
for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
if (ct_descs[i]->id == current_tile_id)
@@ -413,6 +436,7 @@ static void __init v2m_populate_ct_desc(void)
static void __init v2m_map_io(void)
{
iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+ v2m_sysreg_base = V2M_PERIPH + (V2M_SYSREGS & ~V2M_PA_CS7);
v2m_populate_ct_desc();
ct_desc->map_io();
}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 2/9] ARM: vexpress: Get rid of MMIO_P2V
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
This patch gets rid of the MMIO_P2V and __MMIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/include/asm/hardware/arm_timer.h | 5 ++
arch/arm/mach-vexpress/core.h | 9 ++-
arch/arm/mach-vexpress/ct-ca9x4.c | 48 +++------------
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 ++---
arch/arm/mach-vexpress/include/mach/motherboard.h | 52 ++++++++--------
arch/arm/mach-vexpress/platsmp.c | 5 +-
arch/arm/mach-vexpress/v2m.c | 68 ++++++++++++++-------
7 files changed, 98 insertions(+), 102 deletions(-)
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7b..d6030ff 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
*
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
* can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
*/
+#define TIMER_1_BASE 0x00
+#define TIMER_2_BASE 0x20
+
#define TIMER_LOAD 0x00 /* ACVR rw */
#define TIMER_VALUE 0x04 /* ACVR ro */
#define TIMER_CTRL 0x08 /* ACVR rw */
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f439715..75a640a 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x) (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
-#define MMIO_P2V(x) ((void __iomem *)__MMIO_P2V(x))
-
#define AMBA_DEVICE(name,busid,base,plat) \
struct amba_device name##_device = { \
.dev = { \
@@ -17,3 +14,9 @@ struct amba_device name##_device = { \
.irq = IRQ_##base, \
/* .dma = DMA_##base,*/ \
}
+
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH ((void __iomem *)0xf8000000)
+
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH ((void __iomem *)0xf8200000)
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836..743a147 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,29 @@
#include <plat/clcd.h>
-#define V2M_PA_CS7 0x10000000
-
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
{
- .virtual = __MMIO_P2V(CT_CA9X4_MPIC),
- .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
- .pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = __MMIO_P2V(CT_CA9X4_L2CC),
- .pfn = __phys_to_pfn(CT_CA9X4_L2CC),
- .length = SZ_4K,
- .type = MT_DEVICE,
+ .virtual = (unsigned long)V2T_PERIPH,
+ .pfn = __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
},
};
static void __init ct_ca9x4_map_io(void)
{
#ifdef CONFIG_LOCAL_TIMERS
- twd_base = MMIO_P2V(A9_MPCORE_TWD);
+ twd_base = V2T_PERIPH + A9_MPCORE_TWD;
#endif
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
static void __init ct_ca9x4_init_irq(void)
{
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
- MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
- writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- "ct-timer0");
+ gic_init(0, 29, V2T_PERIPH + A9_MPCORE_GIC_DIST,
+ V2T_PERIPH + A9_MPCORE_GIC_CPU);
}
-static struct sys_timer ct_ca9x4_timer = {
- .init = ct_ca9x4_timer_init,
-};
-#endif
-
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -201,7 +173,7 @@ static void __init ct_ca9x4_init(void)
int i;
#ifdef CONFIG_CACHE_L2X0
- void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+ void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
/* set RAM latencies to 1 cycle for this core tile. */
writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -219,7 +191,7 @@ static void __init ct_ca9x4_init(void)
#ifdef CONFIG_SMP
static void ct_ca9x4_init_cpu_map(void)
{
- int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
+ int i, ncores = scu_get_core_count(V2T_PERIPH + A9_MPCORE_SCU);
if (ncores > nr_cpu_ids) {
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
@@ -235,7 +207,7 @@ static void ct_ca9x4_init_cpu_map(void)
static void ct_ca9x4_smp_enable(unsigned int max_cpus)
{
- scu_enable(MMIO_P2V(A9_MPCORE_SCU));
+ scu_enable(V2T_PERIPH + A9_MPCORE_SCU);
}
#endif
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index a34d3d4..8f962fb 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -22,14 +22,11 @@
#define CT_CA9X4_SYSWDT (0x1e007000)
#define CT_CA9X4_L2CC (0x1e00a000)
-#define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000)
-#define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020)
-
-#define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000)
-#define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100)
-#define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200)
-#define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600)
-#define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000)
+#define A9_MPCORE_SCU 0x0000
+#define A9_MPCORE_GIC_CPU 0x0100
+#define A9_MPCORE_GIT 0x0200
+#define A9_MPCORE_TWD 0x0600
+#define A9_MPCORE_GIC_DIST 0x1000
/*
* Interrupts. Those in {} are for AMBA devices
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 0a3a375..b4c498c 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -39,33 +39,30 @@
#define V2M_CF (V2M_PA_CS7 + 0x0001a000)
#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000)
-#define V2M_SYS_ID (V2M_SYSREGS + 0x000)
-#define V2M_SYS_SW (V2M_SYSREGS + 0x004)
-#define V2M_SYS_LED (V2M_SYSREGS + 0x008)
-#define V2M_SYS_100HZ (V2M_SYSREGS + 0x024)
-#define V2M_SYS_FLAGS (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSSET (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSCLR (V2M_SYSREGS + 0x034)
-#define V2M_SYS_NVFLAGS (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSSET (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSCLR (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_MCI (V2M_SYSREGS + 0x048)
-#define V2M_SYS_FLASH (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_CFGSW (V2M_SYSREGS + 0x058)
-#define V2M_SYS_24MHZ (V2M_SYSREGS + 0x05c)
-#define V2M_SYS_MISC (V2M_SYSREGS + 0x060)
-#define V2M_SYS_DMA (V2M_SYSREGS + 0x064)
-#define V2M_SYS_PROCID0 (V2M_SYSREGS + 0x084)
-#define V2M_SYS_PROCID1 (V2M_SYSREGS + 0x088)
-#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
-#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
-#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
-
-#define V2M_TIMER0 (V2M_TIMER01 + 0x000)
-#define V2M_TIMER1 (V2M_TIMER01 + 0x020)
-
-#define V2M_TIMER2 (V2M_TIMER23 + 0x000)
-#define V2M_TIMER3 (V2M_TIMER23 + 0x020)
+/*
+ * Offsets from SYSREGS base
+ */
+#define V2M_SYS_ID 0x000
+#define V2M_SYS_SW 0x004
+#define V2M_SYS_LED 0x008
+#define V2M_SYS_100HZ 0x024
+#define V2M_SYS_FLAGS 0x030
+#define V2M_SYS_FLAGSSET 0x030
+#define V2M_SYS_FLAGSCLR 0x034
+#define V2M_SYS_NVFLAGS 0x038
+#define V2M_SYS_NVFLAGSSET 0x038
+#define V2M_SYS_NVFLAGSCLR 0x03c
+#define V2M_SYS_MCI 0x048
+#define V2M_SYS_FLASH 0x03c
+#define V2M_SYS_CFGSW 0x058
+#define V2M_SYS_24MHZ 0x05c
+#define V2M_SYS_MISC 0x060
+#define V2M_SYS_DMA 0x064
+#define V2M_SYS_PROCID0 0x084
+#define V2M_SYS_PROCID1 0x088
+#define V2M_SYS_CFGDATA 0x0a0
+#define V2M_SYS_CFGCTRL 0x0a4
+#define V2M_SYS_CFGSTAT 0x0a8
/*
@@ -117,6 +114,7 @@
int v2m_cfg_write(u32 devfn, u32 data);
int v2m_cfg_read(u32 devfn, u32 *data);
+void v2m_flags_set(u32 data);
/*
* Core tile IDs
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 124ffb1..a1ed6d6 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -14,7 +14,6 @@
#include <linux/io.h>
#include <mach/motherboard.h>
-#define V2M_PA_CS7 0x10000000
#include "core.h"
@@ -43,7 +42,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
- writel(virt_to_phys(versatile_secondary_startup),
- MMIO_P2V(V2M_SYS_FLAGSSET));
+ v2m_flags_set(virt_to_phys(versatile_secondary_startup));
}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 1fafc32..05b4f46 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -39,29 +39,45 @@
static struct map_desc v2m_io_desc[] __initdata = {
{
- .virtual = __MMIO_P2V(V2M_PA_CS7),
+ .virtual = (unsigned long)V2M_PERIPH,
.pfn = __phys_to_pfn(V2M_PA_CS7),
.length = SZ_128K,
.type = MT_DEVICE,
},
};
-static void __init v2m_timer_init(void)
+static void __iomem *v2m_sysreg_base;
+
+static void __init v2m_sysctl_init(void __iomem *base)
{
u32 scctrl;
+ if (WARN_ON(!base))
+ return;
+
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
- scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
+ scctrl = readl(base + SCCTRL);
scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
- writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
+ writel(scctrl, base + SCCTRL);
+}
- writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
+static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
+{
+ if (WARN_ON(!base || irq == NO_IRQ))
+ return;
+
+ writel(0, base + TIMER_1_BASE + TIMER_CTRL);
+ writel(0, base + TIMER_2_BASE + TIMER_CTRL);
- sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
- sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
- "v2m-timer0");
+ sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
+ sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
+}
+
+static void __init v2m_timer_init(void)
+{
+ v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
+ v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
}
static struct sys_timer v2m_timer = {
@@ -81,14 +97,14 @@ int v2m_cfg_write(u32 devfn, u32 data)
devfn |= SYS_CFG_START | SYS_CFG_WRITE;
spin_lock(&v2m_cfg_lock);
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
- writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
+ writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
- writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
- writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+ writel(data, v2m_sysreg_base + V2M_SYS_CFGDATA);
+ writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
do {
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
} while (val == 0);
spin_unlock(&v2m_cfg_lock);
@@ -102,22 +118,28 @@ int v2m_cfg_read(u32 devfn, u32 *data)
devfn |= SYS_CFG_START;
spin_lock(&v2m_cfg_lock);
- writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
- writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+ writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
+ writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
mb();
do {
cpu_relax();
- val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+ val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
} while (val == 0);
- *data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
+ *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
spin_unlock(&v2m_cfg_lock);
return !!(val & SYS_CFG_ERR);
}
+void __init v2m_flags_set(u32 data)
+{
+ writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
+ writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
+}
+
static struct resource v2m_pcie_i2c_resource = {
.start = V2M_SERIAL_BUS_PCI,
@@ -203,7 +225,7 @@ static struct platform_device v2m_usb_device = {
static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
{
- writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
+ writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
}
static struct physmap_flash_data v2m_flash_data = {
@@ -257,7 +279,7 @@ static struct platform_device v2m_cf_device = {
static unsigned int v2m_mmci_status(struct device *dev)
{
- return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
+ return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
}
static struct mmci_platform_data v2m_mmci_data = {
@@ -370,7 +392,7 @@ static void __init v2m_init_early(void)
{
ct_desc->init_early();
clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
- versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+ versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
}
static void v2m_power_off(void)
@@ -399,7 +421,8 @@ static void __init v2m_populate_ct_desc(void)
u32 current_tile_id;
ct_desc = NULL;
- current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
+ current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
+ & V2M_CT_ID_MASK;
for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
if (ct_descs[i]->id == current_tile_id)
@@ -413,6 +436,7 @@ static void __init v2m_populate_ct_desc(void)
static void __init v2m_map_io(void)
{
iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+ v2m_sysreg_base = V2M_PERIPH + (V2M_SYSREGS & ~V2M_PA_CS7);
v2m_populate_ct_desc();
ct_desc->map_io();
}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
Try to map TWD registers basing on a "arm,smp-twd" Device Tree
node (compatible value as used in Highbank's DT). This overrides
existing twd_base value.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/plat-versatile/localtimer.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-versatile/localtimer.c b/arch/arm/plat-versatile/localtimer.c
index 0fb3961..8f0dc10 100644
--- a/arch/arm/plat-versatile/localtimer.c
+++ b/arch/arm/plat-versatile/localtimer.c
@@ -11,6 +11,8 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include <asm/smp_twd.h>
#include <asm/localtimer.h>
@@ -21,6 +23,16 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ struct device_node *node = of_find_compatible_node(NULL,
+ NULL, "arm,smp-twd");
+
+ if (node)
+ twd_base = of_iomap(node, 0);
+#endif
+ if (!twd_base)
+ return -ENXIO;
+
evt->irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
Try to map TWD registers basing on a "arm,smp-twd" Device Tree
node (compatible value as used in Highbank's DT). This overrides
existing twd_base value.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/plat-versatile/localtimer.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-versatile/localtimer.c b/arch/arm/plat-versatile/localtimer.c
index 0fb3961..8f0dc10 100644
--- a/arch/arm/plat-versatile/localtimer.c
+++ b/arch/arm/plat-versatile/localtimer.c
@@ -11,6 +11,8 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include <asm/smp_twd.h>
#include <asm/localtimer.h>
@@ -21,6 +23,16 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ struct device_node *node = of_find_compatible_node(NULL,
+ NULL, "arm,smp-twd");
+
+ if (node)
+ twd_base = of_iomap(node, 0);
+#endif
+ if (!twd_base)
+ return -ENXIO;
+
evt->irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 4/9] ARM: vexpress: Use FDT data in platform SMP calls
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
If ct_desc is not set (so a board was booted with DT machine ID)
try to look for "arm,cortex-a9-scu" node and initialize the SCU
using base address in "reg" property.
Otherwise assume that there is no special SCU initialization
required and initialize CPUs basing on numbers of "cpu" type
devices in "cpus" node of the Device Tree.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/mach-vexpress/platsmp.c | 148 +++++++++++++++++++++++++++++++++++++-
1 files changed, 146 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index a1ed6d6..d49e800d 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,6 +12,11 @@
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/io.h>
+#include <linux/of_fdt.h>
+
+#include <asm/smp_scu.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
#include <mach/motherboard.h>
@@ -19,13 +24,149 @@
extern void versatile_secondary_startup(void);
+#if defined(CONFIG_OF)
+
+static enum {
+ UNKNOWN_SCU,
+ GENERIC_SCU,
+ CORTEX_A9_SCU,
+} vexpress_dt_scu = UNKNOWN_SCU;
+
+static void __init vexpress_dt_init_cpu_map(int ncores)
+{
+ int i;
+
+ if (ncores > nr_cpu_ids) {
+ pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+ ncores, nr_cpu_ids);
+ ncores = nr_cpu_ids;
+ }
+
+ for (i = 0; i < ncores; ++i)
+ set_cpu_possible(i, true);
+}
+
+static struct map_desc vexpress_dt_cortex_a9_scu_map[] __initdata = {
+ {
+ .virtual = (unsigned long)V2T_PERIPH,
+ /* .pfn set in vexpress_dt_init_cortex_a9_scu() */
+ .length = SZ_128,
+ .type = MT_DEVICE,
+ },
+};
+
+static int __init vexpress_dt_find_scu(unsigned long node,
+ const char *uname, int depth, void *data)
+{
+ if (of_flat_dt_is_compatible(node, "arm,cortex-a9-scu")) {
+ __be32 *reg = of_get_flat_dt_prop(node, "reg", NULL);
+
+ if (WARN_ON(!reg))
+ return -EINVAL;
+
+ vexpress_dt_cortex_a9_scu_map[0].pfn =
+ __phys_to_pfn(be32_to_cpup(reg));
+ iotable_init(vexpress_dt_cortex_a9_scu_map,
+ ARRAY_SIZE(vexpress_dt_cortex_a9_scu_map));
+
+ vexpress_dt_init_cpu_map(scu_get_core_count(V2T_PERIPH));
+ set_smp_cross_call(gic_raise_softirq);
+
+ vexpress_dt_scu = CORTEX_A9_SCU;
+
+ return 1;
+ }
+
+ return 0;
+}
+
+static int __init vexpress_dt_nr_cpus(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ static int prev_depth = -1;
+ static int nr_cpus = -1;
+
+ if (prev_depth > depth && nr_cpus > 0)
+ return nr_cpus;
+
+ if (nr_cpus < 0 && strcmp(uname, "cpus") == 0)
+ nr_cpus = 0;
+
+ if (nr_cpus >= 0) {
+ const char *device_type = of_get_flat_dt_prop(node,
+ "device_type", NULL);
+
+ if (device_type && strcmp(device_type, "cpu") == 0)
+ nr_cpus++;
+ }
+
+ prev_depth = depth;
+
+ return 0;
+}
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+ int res = of_scan_flat_dt(vexpress_dt_find_scu, NULL);
+
+ if (WARN_ON(res < 0))
+ return;
+
+ if (vexpress_dt_scu == UNKNOWN_SCU) {
+ int ncores = of_scan_flat_dt(vexpress_dt_nr_cpus, NULL);
+ if (ncores < 2)
+ return;
+
+ vexpress_dt_scu = GENERIC_SCU;
+
+ vexpress_dt_init_cpu_map(ncores);
+ set_smp_cross_call(gic_raise_softirq);
+ }
+}
+
+static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ switch (vexpress_dt_scu) {
+ case GENERIC_SCU:
+ for (i = 0; i < max_cpus; i++)
+ set_cpu_present(i, true);
+ break;
+ case CORTEX_A9_SCU:
+ scu_enable(V2T_PERIPH);
+ break;
+ default:
+ WARN_ON(1);
+ break;
+ }
+}
+
+#else
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+ WARN_ON(1);
+}
+
+void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+ WARN_ON(1);
+}
+
+#endif
+
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
void __init smp_init_cpus(void)
{
- ct_desc->init_cpu_map();
+ if (ct_desc)
+ ct_desc->init_cpu_map();
+ else
+ vexpress_dt_smp_init_cpus();
+
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
@@ -34,7 +175,10 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* Initialise the present map, which describes the set of CPUs
* actually populated at the present time.
*/
- ct_desc->smp_enable(max_cpus);
+ if (ct_desc)
+ ct_desc->smp_enable(max_cpus);
+ else
+ vexpress_dt_smp_prepare_cpus(max_cpus);
/*
* Write the address of secondary startup into the
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 4/9] ARM: vexpress: Use FDT data in platform SMP calls
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
If ct_desc is not set (so a board was booted with DT machine ID)
try to look for "arm,cortex-a9-scu" node and initialize the SCU
using base address in "reg" property.
Otherwise assume that there is no special SCU initialization
required and initialize CPUs basing on numbers of "cpu" type
devices in "cpus" node of the Device Tree.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/mach-vexpress/platsmp.c | 148 +++++++++++++++++++++++++++++++++++++-
1 files changed, 146 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index a1ed6d6..d49e800d 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,6 +12,11 @@
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/io.h>
+#include <linux/of_fdt.h>
+
+#include <asm/smp_scu.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
#include <mach/motherboard.h>
@@ -19,13 +24,149 @@
extern void versatile_secondary_startup(void);
+#if defined(CONFIG_OF)
+
+static enum {
+ UNKNOWN_SCU,
+ GENERIC_SCU,
+ CORTEX_A9_SCU,
+} vexpress_dt_scu = UNKNOWN_SCU;
+
+static void __init vexpress_dt_init_cpu_map(int ncores)
+{
+ int i;
+
+ if (ncores > nr_cpu_ids) {
+ pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+ ncores, nr_cpu_ids);
+ ncores = nr_cpu_ids;
+ }
+
+ for (i = 0; i < ncores; ++i)
+ set_cpu_possible(i, true);
+}
+
+static struct map_desc vexpress_dt_cortex_a9_scu_map[] __initdata = {
+ {
+ .virtual = (unsigned long)V2T_PERIPH,
+ /* .pfn set in vexpress_dt_init_cortex_a9_scu() */
+ .length = SZ_128,
+ .type = MT_DEVICE,
+ },
+};
+
+static int __init vexpress_dt_find_scu(unsigned long node,
+ const char *uname, int depth, void *data)
+{
+ if (of_flat_dt_is_compatible(node, "arm,cortex-a9-scu")) {
+ __be32 *reg = of_get_flat_dt_prop(node, "reg", NULL);
+
+ if (WARN_ON(!reg))
+ return -EINVAL;
+
+ vexpress_dt_cortex_a9_scu_map[0].pfn =
+ __phys_to_pfn(be32_to_cpup(reg));
+ iotable_init(vexpress_dt_cortex_a9_scu_map,
+ ARRAY_SIZE(vexpress_dt_cortex_a9_scu_map));
+
+ vexpress_dt_init_cpu_map(scu_get_core_count(V2T_PERIPH));
+ set_smp_cross_call(gic_raise_softirq);
+
+ vexpress_dt_scu = CORTEX_A9_SCU;
+
+ return 1;
+ }
+
+ return 0;
+}
+
+static int __init vexpress_dt_nr_cpus(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ static int prev_depth = -1;
+ static int nr_cpus = -1;
+
+ if (prev_depth > depth && nr_cpus > 0)
+ return nr_cpus;
+
+ if (nr_cpus < 0 && strcmp(uname, "cpus") == 0)
+ nr_cpus = 0;
+
+ if (nr_cpus >= 0) {
+ const char *device_type = of_get_flat_dt_prop(node,
+ "device_type", NULL);
+
+ if (device_type && strcmp(device_type, "cpu") == 0)
+ nr_cpus++;
+ }
+
+ prev_depth = depth;
+
+ return 0;
+}
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+ int res = of_scan_flat_dt(vexpress_dt_find_scu, NULL);
+
+ if (WARN_ON(res < 0))
+ return;
+
+ if (vexpress_dt_scu == UNKNOWN_SCU) {
+ int ncores = of_scan_flat_dt(vexpress_dt_nr_cpus, NULL);
+ if (ncores < 2)
+ return;
+
+ vexpress_dt_scu = GENERIC_SCU;
+
+ vexpress_dt_init_cpu_map(ncores);
+ set_smp_cross_call(gic_raise_softirq);
+ }
+}
+
+static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ switch (vexpress_dt_scu) {
+ case GENERIC_SCU:
+ for (i = 0; i < max_cpus; i++)
+ set_cpu_present(i, true);
+ break;
+ case CORTEX_A9_SCU:
+ scu_enable(V2T_PERIPH);
+ break;
+ default:
+ WARN_ON(1);
+ break;
+ }
+}
+
+#else
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+ WARN_ON(1);
+}
+
+void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+ WARN_ON(1);
+}
+
+#endif
+
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
void __init smp_init_cpus(void)
{
- ct_desc->init_cpu_map();
+ if (ct_desc)
+ ct_desc->init_cpu_map();
+ else
+ vexpress_dt_smp_init_cpus();
+
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
@@ -34,7 +175,10 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* Initialise the present map, which describes the set of CPUs
* actually populated at the present time.
*/
- ct_desc->smp_enable(max_cpus);
+ if (ct_desc)
+ ct_desc->smp_enable(max_cpus);
+ else
+ vexpress_dt_smp_prepare_cpus(max_cpus);
/*
* Write the address of secondary startup into the
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 5/9] ARM: vexpress: Add Device Tree support
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch adds generic Versatile Express DT machine description,
Device Tree description for the motherboard and documentation for
the bindings.
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++++++++++++++
arch/arm/Kconfig | 2 +-
arch/arm/boot/dts/vexpress-v2m.dtsi | 200 ++++++++++++++++++++
arch/arm/mach-vexpress/Kconfig | 45 ++++-
arch/arm/mach-vexpress/Makefile.boot | 2 +
arch/arm/mach-vexpress/include/mach/motherboard.h | 6 +
arch/arm/mach-vexpress/v2m.c | 152 +++++++++++++++-
arch/arm/mm/Kconfig | 2 +-
8 files changed, 546 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt
new file mode 100644
index 0000000..87b9ee7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress.txt
@@ -0,0 +1,144 @@
+ARM Versatile Express boards family
+-----------------------------------
+
+ARM's Versatile Express platform consists of a motherboard and one
+or more daughterboards (tiles). The motherboard provides a set of
+peripherals. Processor and RAM "live" on the tiles.
+
+The motherboard and each core tile should be described by a separate
+Device Tree source file, with the tile's description including
+the motherboard file using a /include/ directive. As the motherboard
+can be initialized in one of two different configurations ("memory
+maps"), care must be taken to include the correct one.
+
+Required properties in the root node:
+- compatible value:
+ compatible = "arm,vexpress,<model>", "arm,vexpress";
+ where <model> is the full tile model name (as used in the tile's
+ Technical Reference Manual), eg.:
+ - for Coretile Express A5x2 (V2P-CA5s):
+ compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
+ - for Coretile Express A9x4 (V2P-CA9):
+ compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
+ If a tile comes in several variants or can be used in more then one
+ configuration, the compatible value should be:
+ compatible = "arm,vexpress,<model>,<variant>", \
+ "arm,vexpress,<model>", "arm,vexpress";
+ eg:
+ - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
+ compatible = "arm,vexpress,v2p-ca15,tc1", \
+ "arm,vexpress,v2p-ca15", "arm,vexpress";
+ - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
+ compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
+ "arm,vexpress,v2f-2xv6", "arm,vexpress";
+
+Optional properties in the root node:
+- tile model name (use name from the tile's Technical Reference
+ Manual, eg. "V2P-CA5s")
+ model = "<model>";
+- tile's HBI number (unique ARM's board model ID, visible on the
+ PCB's silkscreen) in hexadecimal transcription:
+ arm,hbi = <0xhbi>
+ eg:
+ - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
+ arm,hbi = <0x191>;
+ - Coretile Express A9x4 (V2P-CA9) HBI-0225:
+ arm,hbi = <0x225>;
+
+Top-level standard "cpus" node is required. It must contain a node
+with device_type = "cpu" property for every available core, eg.:
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <0>;
+ };
+ };
+
+The motherboard description file provides a single "motherboard" node
+using 2 address cells corresponding to the Static Memory Bus used
+between the motherboard and the tile. The first cell defines the Chip
+Select (CS) line number, the second cell address offset within the CS.
+All interrupt lines between the motherboard and the tile are active
+high and are described using single cell.
+
+Optional properties of the "motherboard" node:
+- motherboard's memory map variant:
+ arm,v2m-memory-map = "<name>";
+ where name is one of:
+ - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
+ referred to as "ARM Cortex-A Series memory map":
+ arm,v2m-memory-map = "rs1";
+ When this property is missing, the motherboard is using the original
+ memory map (also known as the "Legacy memory map", primarily used
+ with the original CoreTile Express A9x4) with peripherals on CS7.
+
+Motherboard .dtsi files provide a set of labelled peripherals that
+can be used to obtain required phandle in the tile's "aliases" node:
+- UARTs, note that the numbers correspond to the physical connectors
+ on the motherboard's back panel:
+ v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
+- I2C controllers:
+ v2m_i2c_dvi and v2m_i2c_pcie
+- SP804 timers:
+ v2m_timer01 and v2m_timer23
+
+Current Linux implementation requires a "arm,v2m_timer" alias
+pointing at one of the motherboard's SP804 timers, if it is to be
+used as the system timer. This alias should be defined in the
+motherboard files.
+
+The tile description must define "ranges", "interrupt-map-mask" and
+"interrupt-map" properties to translate the motherboard's address
+and interrupt space into one used by the tile's processor.
+
+Abbreviated example:
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA5s";
+ arm,hbi = <0x225>;
+ compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &v2m_serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <0>;
+ };
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2c001000 0x1000>,
+ <0x2c000100 0x100>;
+ };
+
+ motherboard {
+ /* CS0 is visible at 0x08000000 */
+ ranges = <0 0 0x08000000 0x04000000>;
+ interrupt-map-mask = <0 0 63>;
+ /* Active high IRQ 0 is connected to GIC's SPI0 */
+ interrupt-map = <0 0 0 &gic 0 0 4>;
+ };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 776d76b..9e484a7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1441,7 +1441,7 @@ config SMP
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
- ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+ ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS || \
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
depends on MMU
select USE_GENERIC_SMP_HELPERS
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
new file mode 100644
index 0000000..a6c9c7c
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -0,0 +1,200 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * Original memory map ("Legacy memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m-rs1.dtsi!
+ */
+
+/ {
+ aliases {
+ arm,v2m_timer = &v2m_timer01;
+ };
+
+ motherboard {
+ compatible = "simple-bus";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ flash@0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000>,
+ <1 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ psram@2,00000000 {
+ compatible = "arm,vexpress-psram", "mtd-ram";
+ reg = <2 0x00000000 0x02000000>;
+ bank-width = <4>;
+ };
+
+ vram@3,00000000 {
+ compatible = "arm,vexpress-vram";
+ reg = <3 0x00000000 0x00800000>;
+ };
+
+ ethernet@3,02000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <3 0x02000000 0x10000>;
+ interrupts = <15>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@3,03000000 {
+ compatible = "nxp,usb-isp1761";
+ reg = <3 0x03000000 0x20000>;
+ interrupts = <16>;
+ port1-otg;
+ };
+
+ iofpga@7,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 7 0 0x20000>;
+
+ sysreg@00000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x00000 0x1000>;
+ };
+
+ sysctl@01000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x01000 0x1000>;
+ };
+
+ /* PCI-E I2C bus */
+ v2m_i2c_pcie: i2c@02000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x02000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie-switch@60 {
+ compatible = "idt,89hpes32h8";
+ reg = <0x60>;
+ };
+ };
+
+ aaci@04000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x04000 0x1000>;
+ interrupts = <11>;
+ };
+
+ mmci@05000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x05000 0x1000>;
+ interrupts = <9 10>;
+ };
+
+ kmi@06000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x06000 0x1000>;
+ interrupts = <12>;
+ };
+
+ kmi@07000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x07000 0x1000>;
+ interrupts = <13>;
+ };
+
+ v2m_serial0: uart@09000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x09000 0x1000>;
+ interrupts = <5>;
+ };
+
+ v2m_serial1: uart@0a000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a000 0x1000>;
+ interrupts = <6>;
+ };
+
+ v2m_serial2: uart@0b000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b000 0x1000>;
+ interrupts = <7>;
+ };
+
+ v2m_serial3: uart@0c000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c000 0x1000>;
+ interrupts = <8>;
+ };
+
+ wdt@0f000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f000 0x1000>;
+ interrupts = <0>;
+ };
+
+ v2m_timer01: timer@11000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x11000 0x1000>;
+ interrupts = <2>;
+ };
+
+ v2m_timer23: timer@12000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ };
+
+ /* DVI I2C bus */
+ v2m_i2c_dvi: i2c@16000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x16000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dvi-transmitter@39 {
+ compatible = "sil,sii9022-tpi", "sil,sii9022";
+ reg = <0x39>;
+ };
+
+ dvi-transmitter@60 {
+ compatible = "sil,sii9022-cpi", "sil,sii9022";
+ reg = <0x60>;
+ };
+ };
+
+ rtc@17000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x17000 0x1000>;
+ interrupts = <4>;
+ };
+
+ compact-flash@1a000 {
+ compatible = "arm,vexpress-cf", "ata-generic";
+ reg = <0x1a000 0x100
+ 0x1a100 0xf00>;
+ reg-shift = <2>;
+ };
+
+ clcd@1f000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f000 0x1000>;
+ interrupts = <14>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 9311484..4c1dcd0 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,12 +1,51 @@
menu "Versatile Express platform type"
depends on ARCH_VEXPRESS
+config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+ bool
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_751472
+ select PL310_ERRATA_753970 if CACHE_PL310
+ help
+ Provides common dependencies for Versatile Express platforms
+ based on Cortex-A5 and Cortex-A9 processors. In order to
+ build a working kernel, you must also enable relevant core
+ tile support or Flattened Device Tree based support options.
+
config ARCH_VEXPRESS_CA9X4
bool "Versatile Express Cortex-A9x4 tile"
+ select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+ select ARM_GIC
select CPU_V7
+
+config ARCH_VEXPRESS_DT
+ bool "Device Tree support for Versatile Express platforms"
+ select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
select ARM_GIC
- select ARM_ERRATA_720789
- select ARM_ERRATA_751472
- select ARM_ERRATA_753970
+ select ARM_PATCH_PHYS_VIRT
+ select AUTO_ZRELADDR
+ select CPU_V7
+ select USE_OF
+ help
+ New Versatile Express platforms require Flattened Device Tree to
+ be passed to the kernel.
+
+ This option enables support for systems using Cortex processor based
+ ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
+ for example:
+
+ - CoreTile Express A5x2 (V2P-CA5s)
+ - CoreTile Express A9x4 (V2P-CA9)
+ - CoreTile Express A15x2 (V2P-CA15)
+ - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
+ (Soft Macrocell Models)
+ - Versatile Express RTSMs (Models)
+
+ You must boot using a Flattened Device Tree in order to use these
+ platforms. The traditional (ATAGs) boot method is not usable on
+ these boards with this option.
+
+ If your bootloader supports Flattened Device Tree based booting,
+ say Y here.
endmenu
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 8630b3d..c6dd891 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -1,3 +1,5 @@
+# Those numbers are used only by the non-DT V2P-CA9 platform
+# The DT-enabled ones require CONFIG_AUTO_ZRELADDR=y
zreladdr-y += 0x60008000
params_phys-y := 0x60000100
initrd_phys-y := 0x60800000
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index b4c498c..31a9289 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -117,6 +117,12 @@ int v2m_cfg_read(u32 devfn, u32 *data);
void v2m_flags_set(u32 data);
/*
+ * Miscellaneous
+ */
+#define SYS_MISC_MASTERSITE (1 << 14)
+#define SYS_PROCIDx_HBI_MASK 0xfff
+
+/*
* Core tile IDs
*/
#define V2M_CT_ID_CA9 0x0c000191
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 05b4f46..2544958 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -6,6 +6,10 @@
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/smsc911x.h>
@@ -21,6 +25,8 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/hardware/arm_timer.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
#include <asm/hardware/timer-sp.h>
#include <asm/hardware/sp810.h>
@@ -429,8 +435,9 @@ static void __init v2m_populate_ct_desc(void)
ct_desc = ct_descs[i];
if (!ct_desc)
- panic("vexpress: failed to populate core tile description "
- "for tile ID 0x%8x\n", current_tile_id);
+ panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
+ "You may need a device tree blob or a different kernel to boot on this board.\n",
+ current_tile_id);
}
static void __init v2m_map_io(void)
@@ -474,3 +481,144 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
.timer = &v2m_timer,
.init_machine = v2m_init,
MACHINE_END
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+void __init v2m_dt_map_io(void)
+{
+ iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+}
+
+static struct clk_lookup v2m_dt_lookups[] = {
+ { /* AMBA bus clock */
+ .con_id = "apb_pclk",
+ .clk = &dummy_apb_pclk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer0",
+ .clk = &v2m_sp804_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer1",
+ .clk = &v2m_sp804_clk,
+ }, { /* PL180 MMCI */
+ .dev_id = "mb:mmci", /* 10005000.mmci */
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI0 */
+ .dev_id = "10006000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI1 */
+ .dev_id = "10007000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART0 */
+ .dev_id = "10009000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART1 */
+ .dev_id = "1000a000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART2 */
+ .dev_id = "1000b000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART3 */
+ .dev_id = "1000c000.uart",
+ .clk = &osc2_clk,
+ }, { /* SP805 WDT */
+ .dev_id = "1000f000.wdt",
+ .clk = &v2m_ref_clk,
+ }, { /* PL111 CLCD */
+ .dev_id = "1001f000.clcd",
+ .clk = &osc1_clk,
+ },
+};
+
+void __init v2m_dt_init_early(void)
+{
+ struct device_node *node;
+ const __be32 *reg;
+ u32 dt_hbi;
+
+ node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
+ reg = of_get_property(node, "reg", NULL);
+ if (WARN_ON(!reg))
+ return;
+
+ v2m_sysreg_base = V2M_PERIPH + be32_to_cpup(reg);
+
+ /* Confirm board type against DT property, if available */
+ if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
+ u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
+ u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
+ V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
+ u32 hbi = id & SYS_PROCIDx_HBI_MASK;
+
+ if (WARN_ON(dt_hbi != hbi))
+ pr_warning("vexpress: DT HBI (%x) is not matching "
+ "hardware (%x)!\n", dt_hbi, hbi);
+ }
+
+ clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
+ versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+
+ pm_power_off = v2m_power_off;
+ arm_pm_restart = v2m_restart;
+}
+
+static struct of_device_id vexpress_irq_match[] __initdata = {
+ { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ {}
+};
+
+static void __init v2m_dt_init_irq(void)
+{
+ of_irq_init(vexpress_irq_match);
+}
+
+static void __init v2m_dt_timer_init(void)
+{
+ struct device_node *node;
+ const char *path;
+ int err;
+
+ node = of_find_compatible_node(NULL, NULL, "arm,sp810");
+ v2m_sysctl_init(of_iomap(node, 0));
+
+ err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
+ if (WARN_ON(err))
+ return;
+ node = of_find_node_by_path(path);
+ v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
+}
+
+static struct sys_timer v2m_dt_timer = {
+ .init = v2m_dt_timer_init,
+};
+
+static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
+ &v2m_flash_data),
+ OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+ {}
+};
+
+static void __init v2m_dt_init(void)
+{
+ l2x0_of_init(0x00400000, 0xfe0fffff);
+ of_platform_populate(NULL, of_default_bus_match_table,
+ v2m_dt_auxdata_lookup, NULL);
+}
+
+static const char *v2m_dt_match[] __initdata = {
+ "arm,vexpress",
+ NULL,
+};
+
+DT_MACHINE_START(VEXPRESS_DT, "ARM Versatile Express")
+ .map_io = v2m_dt_map_io,
+ .init_early = v2m_dt_init_early,
+ .init_irq = v2m_dt_init_irq,
+ .timer = &v2m_dt_timer,
+ .init_machine = v2m_dt_init,
+ .dt_compat = v2m_dt_match,
+MACHINE_END
+
+#endif
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 67f75a0..2506e58 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -821,7 +821,7 @@ config CACHE_L2X0
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
+ ARCH_U8500 || ARCH_VEXPRESS || ARCH_SHMOBILE || \
ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
default y
select OUTER_CACHE
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 5/9] ARM: vexpress: Add Device Tree support
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds generic Versatile Express DT machine description,
Device Tree description for the motherboard and documentation for
the bindings.
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++++++++++++++
arch/arm/Kconfig | 2 +-
arch/arm/boot/dts/vexpress-v2m.dtsi | 200 ++++++++++++++++++++
arch/arm/mach-vexpress/Kconfig | 45 ++++-
arch/arm/mach-vexpress/Makefile.boot | 2 +
arch/arm/mach-vexpress/include/mach/motherboard.h | 6 +
arch/arm/mach-vexpress/v2m.c | 152 +++++++++++++++-
arch/arm/mm/Kconfig | 2 +-
8 files changed, 546 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt
new file mode 100644
index 0000000..87b9ee7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress.txt
@@ -0,0 +1,144 @@
+ARM Versatile Express boards family
+-----------------------------------
+
+ARM's Versatile Express platform consists of a motherboard and one
+or more daughterboards (tiles). The motherboard provides a set of
+peripherals. Processor and RAM "live" on the tiles.
+
+The motherboard and each core tile should be described by a separate
+Device Tree source file, with the tile's description including
+the motherboard file using a /include/ directive. As the motherboard
+can be initialized in one of two different configurations ("memory
+maps"), care must be taken to include the correct one.
+
+Required properties in the root node:
+- compatible value:
+ compatible = "arm,vexpress,<model>", "arm,vexpress";
+ where <model> is the full tile model name (as used in the tile's
+ Technical Reference Manual), eg.:
+ - for Coretile Express A5x2 (V2P-CA5s):
+ compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
+ - for Coretile Express A9x4 (V2P-CA9):
+ compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
+ If a tile comes in several variants or can be used in more then one
+ configuration, the compatible value should be:
+ compatible = "arm,vexpress,<model>,<variant>", \
+ "arm,vexpress,<model>", "arm,vexpress";
+ eg:
+ - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
+ compatible = "arm,vexpress,v2p-ca15,tc1", \
+ "arm,vexpress,v2p-ca15", "arm,vexpress";
+ - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
+ compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
+ "arm,vexpress,v2f-2xv6", "arm,vexpress";
+
+Optional properties in the root node:
+- tile model name (use name from the tile's Technical Reference
+ Manual, eg. "V2P-CA5s")
+ model = "<model>";
+- tile's HBI number (unique ARM's board model ID, visible on the
+ PCB's silkscreen) in hexadecimal transcription:
+ arm,hbi = <0xhbi>
+ eg:
+ - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
+ arm,hbi = <0x191>;
+ - Coretile Express A9x4 (V2P-CA9) HBI-0225:
+ arm,hbi = <0x225>;
+
+Top-level standard "cpus" node is required. It must contain a node
+with device_type = "cpu" property for every available core, eg.:
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <0>;
+ };
+ };
+
+The motherboard description file provides a single "motherboard" node
+using 2 address cells corresponding to the Static Memory Bus used
+between the motherboard and the tile. The first cell defines the Chip
+Select (CS) line number, the second cell address offset within the CS.
+All interrupt lines between the motherboard and the tile are active
+high and are described using single cell.
+
+Optional properties of the "motherboard" node:
+- motherboard's memory map variant:
+ arm,v2m-memory-map = "<name>";
+ where name is one of:
+ - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
+ referred to as "ARM Cortex-A Series memory map":
+ arm,v2m-memory-map = "rs1";
+ When this property is missing, the motherboard is using the original
+ memory map (also known as the "Legacy memory map", primarily used
+ with the original CoreTile Express A9x4) with peripherals on CS7.
+
+Motherboard .dtsi files provide a set of labelled peripherals that
+can be used to obtain required phandle in the tile's "aliases" node:
+- UARTs, note that the numbers correspond to the physical connectors
+ on the motherboard's back panel:
+ v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
+- I2C controllers:
+ v2m_i2c_dvi and v2m_i2c_pcie
+- SP804 timers:
+ v2m_timer01 and v2m_timer23
+
+Current Linux implementation requires a "arm,v2m_timer" alias
+pointing at one of the motherboard's SP804 timers, if it is to be
+used as the system timer. This alias should be defined in the
+motherboard files.
+
+The tile description must define "ranges", "interrupt-map-mask" and
+"interrupt-map" properties to translate the motherboard's address
+and interrupt space into one used by the tile's processor.
+
+Abbreviated example:
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA5s";
+ arm,hbi = <0x225>;
+ compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &v2m_serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <0>;
+ };
+ };
+
+ gic: interrupt-controller at 2c001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2c001000 0x1000>,
+ <0x2c000100 0x100>;
+ };
+
+ motherboard {
+ /* CS0 is visible at 0x08000000 */
+ ranges = <0 0 0x08000000 0x04000000>;
+ interrupt-map-mask = <0 0 63>;
+ /* Active high IRQ 0 is connected to GIC's SPI0 */
+ interrupt-map = <0 0 0 &gic 0 0 4>;
+ };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 776d76b..9e484a7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1441,7 +1441,7 @@ config SMP
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
- ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+ ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS || \
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
depends on MMU
select USE_GENERIC_SMP_HELPERS
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
new file mode 100644
index 0000000..a6c9c7c
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -0,0 +1,200 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * Original memory map ("Legacy memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m-rs1.dtsi!
+ */
+
+/ {
+ aliases {
+ arm,v2m_timer = &v2m_timer01;
+ };
+
+ motherboard {
+ compatible = "simple-bus";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ flash at 0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000>,
+ <1 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ psram at 2,00000000 {
+ compatible = "arm,vexpress-psram", "mtd-ram";
+ reg = <2 0x00000000 0x02000000>;
+ bank-width = <4>;
+ };
+
+ vram at 3,00000000 {
+ compatible = "arm,vexpress-vram";
+ reg = <3 0x00000000 0x00800000>;
+ };
+
+ ethernet at 3,02000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <3 0x02000000 0x10000>;
+ interrupts = <15>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb at 3,03000000 {
+ compatible = "nxp,usb-isp1761";
+ reg = <3 0x03000000 0x20000>;
+ interrupts = <16>;
+ port1-otg;
+ };
+
+ iofpga at 7,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 7 0 0x20000>;
+
+ sysreg at 00000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x00000 0x1000>;
+ };
+
+ sysctl at 01000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x01000 0x1000>;
+ };
+
+ /* PCI-E I2C bus */
+ v2m_i2c_pcie: i2c at 02000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x02000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie-switch at 60 {
+ compatible = "idt,89hpes32h8";
+ reg = <0x60>;
+ };
+ };
+
+ aaci at 04000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x04000 0x1000>;
+ interrupts = <11>;
+ };
+
+ mmci at 05000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x05000 0x1000>;
+ interrupts = <9 10>;
+ };
+
+ kmi at 06000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x06000 0x1000>;
+ interrupts = <12>;
+ };
+
+ kmi at 07000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x07000 0x1000>;
+ interrupts = <13>;
+ };
+
+ v2m_serial0: uart at 09000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x09000 0x1000>;
+ interrupts = <5>;
+ };
+
+ v2m_serial1: uart at 0a000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a000 0x1000>;
+ interrupts = <6>;
+ };
+
+ v2m_serial2: uart at 0b000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b000 0x1000>;
+ interrupts = <7>;
+ };
+
+ v2m_serial3: uart at 0c000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c000 0x1000>;
+ interrupts = <8>;
+ };
+
+ wdt at 0f000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f000 0x1000>;
+ interrupts = <0>;
+ };
+
+ v2m_timer01: timer at 11000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x11000 0x1000>;
+ interrupts = <2>;
+ };
+
+ v2m_timer23: timer at 12000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ };
+
+ /* DVI I2C bus */
+ v2m_i2c_dvi: i2c at 16000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x16000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dvi-transmitter at 39 {
+ compatible = "sil,sii9022-tpi", "sil,sii9022";
+ reg = <0x39>;
+ };
+
+ dvi-transmitter at 60 {
+ compatible = "sil,sii9022-cpi", "sil,sii9022";
+ reg = <0x60>;
+ };
+ };
+
+ rtc at 17000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x17000 0x1000>;
+ interrupts = <4>;
+ };
+
+ compact-flash at 1a000 {
+ compatible = "arm,vexpress-cf", "ata-generic";
+ reg = <0x1a000 0x100
+ 0x1a100 0xf00>;
+ reg-shift = <2>;
+ };
+
+ clcd at 1f000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f000 0x1000>;
+ interrupts = <14>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 9311484..4c1dcd0 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,12 +1,51 @@
menu "Versatile Express platform type"
depends on ARCH_VEXPRESS
+config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+ bool
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_751472
+ select PL310_ERRATA_753970 if CACHE_PL310
+ help
+ Provides common dependencies for Versatile Express platforms
+ based on Cortex-A5 and Cortex-A9 processors. In order to
+ build a working kernel, you must also enable relevant core
+ tile support or Flattened Device Tree based support options.
+
config ARCH_VEXPRESS_CA9X4
bool "Versatile Express Cortex-A9x4 tile"
+ select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+ select ARM_GIC
select CPU_V7
+
+config ARCH_VEXPRESS_DT
+ bool "Device Tree support for Versatile Express platforms"
+ select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
select ARM_GIC
- select ARM_ERRATA_720789
- select ARM_ERRATA_751472
- select ARM_ERRATA_753970
+ select ARM_PATCH_PHYS_VIRT
+ select AUTO_ZRELADDR
+ select CPU_V7
+ select USE_OF
+ help
+ New Versatile Express platforms require Flattened Device Tree to
+ be passed to the kernel.
+
+ This option enables support for systems using Cortex processor based
+ ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
+ for example:
+
+ - CoreTile Express A5x2 (V2P-CA5s)
+ - CoreTile Express A9x4 (V2P-CA9)
+ - CoreTile Express A15x2 (V2P-CA15)
+ - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
+ (Soft Macrocell Models)
+ - Versatile Express RTSMs (Models)
+
+ You must boot using a Flattened Device Tree in order to use these
+ platforms. The traditional (ATAGs) boot method is not usable on
+ these boards with this option.
+
+ If your bootloader supports Flattened Device Tree based booting,
+ say Y here.
endmenu
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 8630b3d..c6dd891 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -1,3 +1,5 @@
+# Those numbers are used only by the non-DT V2P-CA9 platform
+# The DT-enabled ones require CONFIG_AUTO_ZRELADDR=y
zreladdr-y += 0x60008000
params_phys-y := 0x60000100
initrd_phys-y := 0x60800000
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index b4c498c..31a9289 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -117,6 +117,12 @@ int v2m_cfg_read(u32 devfn, u32 *data);
void v2m_flags_set(u32 data);
/*
+ * Miscellaneous
+ */
+#define SYS_MISC_MASTERSITE (1 << 14)
+#define SYS_PROCIDx_HBI_MASK 0xfff
+
+/*
* Core tile IDs
*/
#define V2M_CT_ID_CA9 0x0c000191
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 05b4f46..2544958 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -6,6 +6,10 @@
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/smsc911x.h>
@@ -21,6 +25,8 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/hardware/arm_timer.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
#include <asm/hardware/timer-sp.h>
#include <asm/hardware/sp810.h>
@@ -429,8 +435,9 @@ static void __init v2m_populate_ct_desc(void)
ct_desc = ct_descs[i];
if (!ct_desc)
- panic("vexpress: failed to populate core tile description "
- "for tile ID 0x%8x\n", current_tile_id);
+ panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
+ "You may need a device tree blob or a different kernel to boot on this board.\n",
+ current_tile_id);
}
static void __init v2m_map_io(void)
@@ -474,3 +481,144 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
.timer = &v2m_timer,
.init_machine = v2m_init,
MACHINE_END
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+void __init v2m_dt_map_io(void)
+{
+ iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+}
+
+static struct clk_lookup v2m_dt_lookups[] = {
+ { /* AMBA bus clock */
+ .con_id = "apb_pclk",
+ .clk = &dummy_apb_pclk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer0",
+ .clk = &v2m_sp804_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer1",
+ .clk = &v2m_sp804_clk,
+ }, { /* PL180 MMCI */
+ .dev_id = "mb:mmci", /* 10005000.mmci */
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI0 */
+ .dev_id = "10006000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI1 */
+ .dev_id = "10007000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART0 */
+ .dev_id = "10009000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART1 */
+ .dev_id = "1000a000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART2 */
+ .dev_id = "1000b000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART3 */
+ .dev_id = "1000c000.uart",
+ .clk = &osc2_clk,
+ }, { /* SP805 WDT */
+ .dev_id = "1000f000.wdt",
+ .clk = &v2m_ref_clk,
+ }, { /* PL111 CLCD */
+ .dev_id = "1001f000.clcd",
+ .clk = &osc1_clk,
+ },
+};
+
+void __init v2m_dt_init_early(void)
+{
+ struct device_node *node;
+ const __be32 *reg;
+ u32 dt_hbi;
+
+ node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
+ reg = of_get_property(node, "reg", NULL);
+ if (WARN_ON(!reg))
+ return;
+
+ v2m_sysreg_base = V2M_PERIPH + be32_to_cpup(reg);
+
+ /* Confirm board type against DT property, if available */
+ if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
+ u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
+ u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
+ V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
+ u32 hbi = id & SYS_PROCIDx_HBI_MASK;
+
+ if (WARN_ON(dt_hbi != hbi))
+ pr_warning("vexpress: DT HBI (%x) is not matching "
+ "hardware (%x)!\n", dt_hbi, hbi);
+ }
+
+ clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
+ versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+
+ pm_power_off = v2m_power_off;
+ arm_pm_restart = v2m_restart;
+}
+
+static struct of_device_id vexpress_irq_match[] __initdata = {
+ { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ {}
+};
+
+static void __init v2m_dt_init_irq(void)
+{
+ of_irq_init(vexpress_irq_match);
+}
+
+static void __init v2m_dt_timer_init(void)
+{
+ struct device_node *node;
+ const char *path;
+ int err;
+
+ node = of_find_compatible_node(NULL, NULL, "arm,sp810");
+ v2m_sysctl_init(of_iomap(node, 0));
+
+ err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
+ if (WARN_ON(err))
+ return;
+ node = of_find_node_by_path(path);
+ v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
+}
+
+static struct sys_timer v2m_dt_timer = {
+ .init = v2m_dt_timer_init,
+};
+
+static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
+ &v2m_flash_data),
+ OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+ {}
+};
+
+static void __init v2m_dt_init(void)
+{
+ l2x0_of_init(0x00400000, 0xfe0fffff);
+ of_platform_populate(NULL, of_default_bus_match_table,
+ v2m_dt_auxdata_lookup, NULL);
+}
+
+static const char *v2m_dt_match[] __initdata = {
+ "arm,vexpress",
+ NULL,
+};
+
+DT_MACHINE_START(VEXPRESS_DT, "ARM Versatile Express")
+ .map_io = v2m_dt_map_io,
+ .init_early = v2m_dt_init_early,
+ .init_irq = v2m_dt_init_irq,
+ .timer = &v2m_dt_timer,
+ .init_machine = v2m_dt_init,
+ .dt_compat = v2m_dt_match,
+MACHINE_END
+
+#endif
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 67f75a0..2506e58 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -821,7 +821,7 @@ config CACHE_L2X0
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
+ ARCH_U8500 || ARCH_VEXPRESS || ARCH_SHMOBILE || \
ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
default y
select OUTER_CACHE
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch adds support for RS1 memory map based Versatile Express
motherboard.
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 201 +++++++++++++++++++++
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 ++++-
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/v2m.c | 64 +++++++-
4 files changed, 309 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 0000000..16076e2
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,201 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+ aliases {
+ arm,v2m_timer = &v2m_timer01;
+ };
+
+ motherboard {
+ compatible = "simple-bus";
+ arm,v2m-memory-map = "rs1";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ flash@0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000>,
+ <4 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ psram@1,00000000 {
+ compatible = "arm,vexpress-psram", "mtd-ram";
+ reg = <1 0x00000000 0x02000000>;
+ bank-width = <4>;
+ };
+
+ vram@2,00000000 {
+ compatible = "arm,vexpress-vram";
+ reg = <2 0x00000000 0x00800000>;
+ };
+
+ ethernet@2,02000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <2 0x02000000 0x10000>;
+ interrupts = <15>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@2,03000000 {
+ compatible = "nxp,usb-isp1761";
+ reg = <2 0x03000000 0x20000>;
+ interrupts = <16>;
+ port1-otg;
+ };
+
+ iofpga@3,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 3 0 0x200000>;
+
+ sysreg@010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x010000 0x1000>;
+ };
+
+ sysctl@020000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ };
+
+ /* PCI-E I2C bus */
+ v2m_i2c_pcie: i2c@030000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x030000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie-switch@60 {
+ compatible = "idt,89hpes32h8";
+ reg = <0x60>;
+ };
+ };
+
+ aaci@040000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x040000 0x1000>;
+ interrupts = <11>;
+ };
+
+ mmci@050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x050000 0x1000>;
+ interrupts = <9 10>;
+ };
+
+ kmi@060000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x060000 0x1000>;
+ interrupts = <12>;
+ };
+
+ kmi@070000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x070000 0x1000>;
+ interrupts = <13>;
+ };
+
+ v2m_serial0: uart@090000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x090000 0x1000>;
+ interrupts = <5>;
+ };
+
+ v2m_serial1: uart@0a0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a0000 0x1000>;
+ interrupts = <6>;
+ };
+
+ v2m_serial2: uart@0b0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b0000 0x1000>;
+ interrupts = <7>;
+ };
+
+ v2m_serial3: uart@0c0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c0000 0x1000>;
+ interrupts = <8>;
+ };
+
+ wdt@0f0000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f0000 0x1000>;
+ interrupts = <0>;
+ };
+
+ v2m_timer01: timer@110000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x110000 0x1000>;
+ interrupts = <2>;
+ };
+
+ v2m_timer23: timer@120000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x120000 0x1000>;
+ };
+
+ /* DVI I2C bus */
+ v2m_i2c_dvi: i2c@160000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x160000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dvi-transmitter@39 {
+ compatible = "sil,sii9022-tpi", "sil,sii9022";
+ reg = <0x39>;
+ };
+
+ dvi-transmitter@60 {
+ compatible = "sil,sii9022-cpi", "sil,sii9022";
+ reg = <0x60>;
+ };
+ };
+
+ rtc@170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x170000 0x1000>;
+ interrupts = <4>;
+ };
+
+ compact-flash@1a0000 {
+ compatible = "arm,vexpress-cf", "ata-generic";
+ reg = <0x1a0000 0x100
+ 0x1a0100 0xf00>;
+ reg-shift = <2>;
+ };
+
+ clcd@1f0000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f0000 0x1000>;
+ interrupts = <14>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fd9e6c7..8010ff9 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -10,12 +10,41 @@
* published by the Free Software Foundation.
*/
-#define DEBUG_LL_UART_OFFSET 0x00009000
+#define DEBUG_LL_PHYS_BASE 0x10000000
+#define DEBUG_LL_UART_OFFSET 0x00009000
+
+#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
+#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
+
+#define DEBUG_LL_VIRT_BASE 0xf8000000
.macro addruart,rp,rv,tmp
- mov \rp, #DEBUG_LL_UART_OFFSET
- orr \rv, \rp, #0xf8000000 @ virtual base
- orr \rp, \rp, #0x10000000 @ physical base
+
+ @ Check the MMU state
+#if defined(CONFIG_MMU)
+ mrc p15, 0, \tmp, c1, c0 @ SCTRL
+ tst \tmp, #1 @ MMU enabled?
+ moveq \tmp, #DEBUG_LL_PHYS_BASE
+ movne \tmp, #DEBUG_LL_VIRT_BASE
+#else
+ mov \tmp, #DEBUG_LL_PHYS_BASE
+#endif
+
+ @ PL011 present in "original" place?
+ orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
+ ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
+ teq \tmp, #0x11 @ PL011
+
+ @ Original memory map
+ moveq \rp, #DEBUG_LL_UART_OFFSET
+ orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
+ orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
+
+ @ RS1 memory map
+ movne \rp, #DEBUG_LL_UART_OFFSET_RS1
+ orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
+ orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+
.endm
#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7972c57..c491565 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -22,7 +22,18 @@
#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
-#define get_uart_base() (0x10000000 + 0x00009000)
+#define AMBA_PERIPH_ID0(base) (*(volatile unsigned char *)((base) + 0xfe0))
+
+#define UART_BASE 0x10009000
+#define UART_BASE_RS1 0x1c090000
+
+static unsigned long get_uart_base(void)
+{
+ if (AMBA_PERIPH_ID0(UART_BASE) == 0x11)
+ return UART_BASE;
+ else
+ return UART_BASE_RS1;
+}
/*
* This does not append a newline
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 2544958..c5aff7b 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -484,9 +484,38 @@ MACHINE_END
#if defined(CONFIG_ARCH_VEXPRESS_DT)
+static struct map_desc v2m_rs1_io_desc[] __initdata = {
+ {
+ .virtual = (unsigned long)V2M_PERIPH,
+ .pfn = __phys_to_pfn(0x1c000000),
+ .length = SZ_2M,
+ .type = MT_DEVICE,
+ },
+};
+
+static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ const char **map = data;
+
+ if (strcmp(uname, "motherboard") != 0)
+ return 0;
+
+ *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
+
+ return 1;
+}
+
void __init v2m_dt_map_io(void)
{
- iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+ const char *map = NULL;
+
+ of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
+
+ if (map && strcmp(map, "rs1") == 0)
+ iotable_init(v2m_rs1_io_desc, ARRAY_SIZE(v2m_rs1_io_desc));
+ else
+ iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
}
static struct clk_lookup v2m_dt_lookups[] = {
@@ -529,6 +558,35 @@ static struct clk_lookup v2m_dt_lookups[] = {
.dev_id = "1001f000.clcd",
.clk = &osc1_clk,
},
+ /* RS1 memory map */
+ { /* PL180 MMCI */
+ .dev_id = "mb:mmci", /* 1c050000.mmci */
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI0 */
+ .dev_id = "1c060000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI1 */
+ .dev_id = "1c070000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART0 */
+ .dev_id = "1c090000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART1 */
+ .dev_id = "1c0a0000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART2 */
+ .dev_id = "1c0b0000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART3 */
+ .dev_id = "1c0c0000.uart",
+ .clk = &osc2_clk,
+ }, { /* SP805 WDT */
+ .dev_id = "1c0f0000.wdt",
+ .clk = &v2m_ref_clk,
+ }, { /* PL111 CLCD */
+ .dev_id = "1c1f0000.clcd",
+ .clk = &osc1_clk,
+ },
};
void __init v2m_dt_init_early(void)
@@ -597,6 +655,10 @@ static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
&v2m_flash_data),
OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+ /* RS1 memory map */
+ OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
+ &v2m_flash_data),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
{}
};
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for RS1 memory map based Versatile Express
motherboard.
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 201 +++++++++++++++++++++
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 ++++-
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/v2m.c | 64 +++++++-
4 files changed, 309 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 0000000..16076e2
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,201 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+ aliases {
+ arm,v2m_timer = &v2m_timer01;
+ };
+
+ motherboard {
+ compatible = "simple-bus";
+ arm,v2m-memory-map = "rs1";
+ #address-cells = <2>; /* SMB chipselect number and offset */
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ flash at 0,00000000 {
+ compatible = "arm,vexpress-flash", "cfi-flash";
+ reg = <0 0x00000000 0x04000000>,
+ <4 0x00000000 0x04000000>;
+ bank-width = <4>;
+ };
+
+ psram at 1,00000000 {
+ compatible = "arm,vexpress-psram", "mtd-ram";
+ reg = <1 0x00000000 0x02000000>;
+ bank-width = <4>;
+ };
+
+ vram at 2,00000000 {
+ compatible = "arm,vexpress-vram";
+ reg = <2 0x00000000 0x00800000>;
+ };
+
+ ethernet at 2,02000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <2 0x02000000 0x10000>;
+ interrupts = <15>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb at 2,03000000 {
+ compatible = "nxp,usb-isp1761";
+ reg = <2 0x03000000 0x20000>;
+ interrupts = <16>;
+ port1-otg;
+ };
+
+ iofpga at 3,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 3 0 0x200000>;
+
+ sysreg at 010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x010000 0x1000>;
+ };
+
+ sysctl at 020000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ };
+
+ /* PCI-E I2C bus */
+ v2m_i2c_pcie: i2c at 030000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x030000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcie-switch at 60 {
+ compatible = "idt,89hpes32h8";
+ reg = <0x60>;
+ };
+ };
+
+ aaci at 040000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x040000 0x1000>;
+ interrupts = <11>;
+ };
+
+ mmci at 050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x050000 0x1000>;
+ interrupts = <9 10>;
+ };
+
+ kmi at 060000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x060000 0x1000>;
+ interrupts = <12>;
+ };
+
+ kmi at 070000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x070000 0x1000>;
+ interrupts = <13>;
+ };
+
+ v2m_serial0: uart at 090000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x090000 0x1000>;
+ interrupts = <5>;
+ };
+
+ v2m_serial1: uart at 0a0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0a0000 0x1000>;
+ interrupts = <6>;
+ };
+
+ v2m_serial2: uart at 0b0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0b0000 0x1000>;
+ interrupts = <7>;
+ };
+
+ v2m_serial3: uart at 0c0000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0c0000 0x1000>;
+ interrupts = <8>;
+ };
+
+ wdt at 0f0000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0f0000 0x1000>;
+ interrupts = <0>;
+ };
+
+ v2m_timer01: timer at 110000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x110000 0x1000>;
+ interrupts = <2>;
+ };
+
+ v2m_timer23: timer at 120000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x120000 0x1000>;
+ };
+
+ /* DVI I2C bus */
+ v2m_i2c_dvi: i2c at 160000 {
+ compatible = "arm,versatile-i2c";
+ reg = <0x160000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dvi-transmitter at 39 {
+ compatible = "sil,sii9022-tpi", "sil,sii9022";
+ reg = <0x39>;
+ };
+
+ dvi-transmitter at 60 {
+ compatible = "sil,sii9022-cpi", "sil,sii9022";
+ reg = <0x60>;
+ };
+ };
+
+ rtc at 170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x170000 0x1000>;
+ interrupts = <4>;
+ };
+
+ compact-flash at 1a0000 {
+ compatible = "arm,vexpress-cf", "ata-generic";
+ reg = <0x1a0000 0x100
+ 0x1a0100 0xf00>;
+ reg-shift = <2>;
+ };
+
+ clcd at 1f0000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f0000 0x1000>;
+ interrupts = <14>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fd9e6c7..8010ff9 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -10,12 +10,41 @@
* published by the Free Software Foundation.
*/
-#define DEBUG_LL_UART_OFFSET 0x00009000
+#define DEBUG_LL_PHYS_BASE 0x10000000
+#define DEBUG_LL_UART_OFFSET 0x00009000
+
+#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
+#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
+
+#define DEBUG_LL_VIRT_BASE 0xf8000000
.macro addruart,rp,rv,tmp
- mov \rp, #DEBUG_LL_UART_OFFSET
- orr \rv, \rp, #0xf8000000 @ virtual base
- orr \rp, \rp, #0x10000000 @ physical base
+
+ @ Check the MMU state
+#if defined(CONFIG_MMU)
+ mrc p15, 0, \tmp, c1, c0 @ SCTRL
+ tst \tmp, #1 @ MMU enabled?
+ moveq \tmp, #DEBUG_LL_PHYS_BASE
+ movne \tmp, #DEBUG_LL_VIRT_BASE
+#else
+ mov \tmp, #DEBUG_LL_PHYS_BASE
+#endif
+
+ @ PL011 present in "original" place?
+ orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
+ ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
+ teq \tmp, #0x11 @ PL011
+
+ @ Original memory map
+ moveq \rp, #DEBUG_LL_UART_OFFSET
+ orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
+ orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
+
+ @ RS1 memory map
+ movne \rp, #DEBUG_LL_UART_OFFSET_RS1
+ orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
+ orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+
.endm
#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7972c57..c491565 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -22,7 +22,18 @@
#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
-#define get_uart_base() (0x10000000 + 0x00009000)
+#define AMBA_PERIPH_ID0(base) (*(volatile unsigned char *)((base) + 0xfe0))
+
+#define UART_BASE 0x10009000
+#define UART_BASE_RS1 0x1c090000
+
+static unsigned long get_uart_base(void)
+{
+ if (AMBA_PERIPH_ID0(UART_BASE) == 0x11)
+ return UART_BASE;
+ else
+ return UART_BASE_RS1;
+}
/*
* This does not append a newline
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 2544958..c5aff7b 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -484,9 +484,38 @@ MACHINE_END
#if defined(CONFIG_ARCH_VEXPRESS_DT)
+static struct map_desc v2m_rs1_io_desc[] __initdata = {
+ {
+ .virtual = (unsigned long)V2M_PERIPH,
+ .pfn = __phys_to_pfn(0x1c000000),
+ .length = SZ_2M,
+ .type = MT_DEVICE,
+ },
+};
+
+static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ const char **map = data;
+
+ if (strcmp(uname, "motherboard") != 0)
+ return 0;
+
+ *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
+
+ return 1;
+}
+
void __init v2m_dt_map_io(void)
{
- iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+ const char *map = NULL;
+
+ of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
+
+ if (map && strcmp(map, "rs1") == 0)
+ iotable_init(v2m_rs1_io_desc, ARRAY_SIZE(v2m_rs1_io_desc));
+ else
+ iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
}
static struct clk_lookup v2m_dt_lookups[] = {
@@ -529,6 +558,35 @@ static struct clk_lookup v2m_dt_lookups[] = {
.dev_id = "1001f000.clcd",
.clk = &osc1_clk,
},
+ /* RS1 memory map */
+ { /* PL180 MMCI */
+ .dev_id = "mb:mmci", /* 1c050000.mmci */
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI0 */
+ .dev_id = "1c060000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL050 KMI1 */
+ .dev_id = "1c070000.kmi",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART0 */
+ .dev_id = "1c090000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART1 */
+ .dev_id = "1c0a0000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART2 */
+ .dev_id = "1c0b0000.uart",
+ .clk = &osc2_clk,
+ }, { /* PL011 UART3 */
+ .dev_id = "1c0c0000.uart",
+ .clk = &osc2_clk,
+ }, { /* SP805 WDT */
+ .dev_id = "1c0f0000.wdt",
+ .clk = &v2m_ref_clk,
+ }, { /* PL111 CLCD */
+ .dev_id = "1c1f0000.clcd",
+ .clk = &osc1_clk,
+ },
};
void __init v2m_dt_init_early(void)
@@ -597,6 +655,10 @@ static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
&v2m_flash_data),
OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+ /* RS1 memory map */
+ OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
+ &v2m_flash_data),
+ OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
{}
};
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 7/9] ARM: vexpress: Add Device Tree for V2P-CA5s core tile
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch adds Device Tree file for the CoreTile Express A5x2 (V2P-CA5s).
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 160 +++++++++++++++++++++++++++++++
arch/arm/mach-vexpress/Makefile.boot | 2 +
2 files changed, 162 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 0000000..da26a13
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,160 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA5s";
+ arm,hbi = <0x225>;
+ compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ i2c0 = &v2m_i2c_dvi;
+ i2c1 = &v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ hdlcd@2a110000 {
+ compatible = "arm,hdlcd";
+ reg = <0x2a110000 0x1000>;
+ interrupts = <0 85 4>;
+ };
+
+ memory-controller@2a150000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x2a150000 0x1000>;
+ };
+
+ memory-controller@2a190000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x2a190000 0x1000>;
+ interrupts = <0 86 4>,
+ <0 87 4>;
+ };
+
+ scu@2c000000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x2c000000 0x58>;
+ };
+
+ timer@2c000600 {
+ compatible = "arm,smp-twd";
+ reg = <0x2c000600 0x38>;
+ interrupts = <1 2 0x304>,
+ <1 3 0x304>;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2c001000 0x1000>,
+ <0x2c000100 0x100>;
+ };
+
+ L2: cache-controller@2c0f0000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x2c0f0000 0x1000>;
+ interrupts = <0 84 4>;
+ cache-level = <2>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 68 4>,
+ <0 69 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x08000000 0x04000000>,
+ <1 0 0x14000000 0x04000000>,
+ <2 0 0x18000000 0x04000000>,
+ <3 0 0x1c000000 0x04000000>,
+ <4 0 0x0c000000 0x04000000>,
+ <5 0 0x10000000 0x04000000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index c6dd891..5e2177e 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -3,3 +3,5 @@
zreladdr-y += 0x60008000
params_phys-y := 0x60000100
initrd_phys-y := 0x60800000
+
+dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 7/9] ARM: vexpress: Add Device Tree for V2P-CA5s core tile
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds Device Tree file for the CoreTile Express A5x2 (V2P-CA5s).
Tested-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 160 +++++++++++++++++++++++++++++++
arch/arm/mach-vexpress/Makefile.boot | 2 +
2 files changed, 162 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 0000000..da26a13
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,160 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA5s";
+ arm,hbi = <0x225>;
+ compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ i2c0 = &v2m_i2c_dvi;
+ i2c1 = &v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ hdlcd at 2a110000 {
+ compatible = "arm,hdlcd";
+ reg = <0x2a110000 0x1000>;
+ interrupts = <0 85 4>;
+ };
+
+ memory-controller at 2a150000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x2a150000 0x1000>;
+ };
+
+ memory-controller at 2a190000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x2a190000 0x1000>;
+ interrupts = <0 86 4>,
+ <0 87 4>;
+ };
+
+ scu at 2c000000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x2c000000 0x58>;
+ };
+
+ timer at 2c000600 {
+ compatible = "arm,smp-twd";
+ reg = <0x2c000600 0x38>;
+ interrupts = <1 2 0x304>,
+ <1 3 0x304>;
+ };
+
+ gic: interrupt-controller at 2c001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2c001000 0x1000>,
+ <0x2c000100 0x100>;
+ };
+
+ L2: cache-controller at 2c0f0000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x2c0f0000 0x1000>;
+ interrupts = <0 84 4>;
+ cache-level = <2>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 68 4>,
+ <0 69 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x08000000 0x04000000>,
+ <1 0 0x14000000 0x04000000>,
+ <2 0 0x18000000 0x04000000>,
+ <3 0 0x1c000000 0x04000000>,
+ <4 0 0x0c000000 0x04000000>,
+ <5 0 0x10000000 0x04000000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index c6dd891..5e2177e 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -3,3 +3,5 @@
zreladdr-y += 0x60008000
params_phys-y := 0x60000100
initrd_phys-y := 0x60800000
+
+dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 8/9] ARM: vexpress: Add Device Tree for V2P-CA9 core tile
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch adds Device Tree file for the CoreTile Express A9x4 (V2P-CA9).
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190 ++++++++++++++++++++++++++++++++
arch/arm/mach-vexpress/Makefile.boot | 3 +-
2 files changed, 192 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 0000000..84542e7
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,190 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA9";
+ arm,hbi = <0x191>;
+ compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ i2c0 = &v2m_i2c_dvi;
+ i2c1 = &v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ clcd@10020000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x10020000 0x1000>;
+ interrupts = <0 44 4>;
+ };
+
+ memory-controller@100e0000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x100e0000 0x1000>;
+ };
+
+ memory-controller@100e1000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x100e1000 0x1000>;
+ interrupts = <0 45 4>,
+ <0 46 4>;
+ };
+
+ timer@100e4000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x100e4000 0x1000>;
+ interrupts = <0 48 4>,
+ <0 49 4>;
+ };
+
+ watchdog@100e5000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x100e5000 0x1000>;
+ interrupts = <0 51 4>;
+ };
+
+ scu@1e000000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x1e000000 0x58>;
+ };
+
+ timer@1e000600 {
+ compatible = "arm,smp-twd";
+ reg = <0x1e000600 0x20>;
+ interrupts = <1 2 0xf04>,
+ <1 3 0xf04>;
+ };
+
+ gic: interrupt-controller@1e001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1e001000 0x1000>,
+ <0x1e000100 0x100>;
+ };
+
+ L2: cache-controller@1e00a000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1e00a000 0x1000>;
+ interrupts = <0 43 4>;
+ cache-level = <2>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <1 1 1>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 60 4>,
+ <0 61 4>,
+ <0 62 4>,
+ <0 63 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x40000000 0x04000000>,
+ <1 0 0x44000000 0x04000000>,
+ <2 0 0x48000000 0x04000000>,
+ <3 0 0x4c000000 0x04000000>,
+ <7 0 0x10000000 0x00020000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m.dtsi"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 5e2177e..2f0ad9f 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -4,4 +4,5 @@
params_phys-y := 0x60000100
initrd_phys-y := 0x60800000
-dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \
+ vexpress-v2p-ca9.dtb
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 8/9] ARM: vexpress: Add Device Tree for V2P-CA9 core tile
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds Device Tree file for the CoreTile Express A9x4 (V2P-CA9).
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190 ++++++++++++++++++++++++++++++++
arch/arm/mach-vexpress/Makefile.boot | 3 +-
2 files changed, 192 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 0000000..84542e7
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,190 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA9";
+ arm,hbi = <0x191>;
+ compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ i2c0 = &v2m_i2c_dvi;
+ i2c1 = &v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory at 60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ clcd at 10020000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x10020000 0x1000>;
+ interrupts = <0 44 4>;
+ };
+
+ memory-controller at 100e0000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x100e0000 0x1000>;
+ };
+
+ memory-controller at 100e1000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x100e1000 0x1000>;
+ interrupts = <0 45 4>,
+ <0 46 4>;
+ };
+
+ timer at 100e4000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x100e4000 0x1000>;
+ interrupts = <0 48 4>,
+ <0 49 4>;
+ };
+
+ watchdog at 100e5000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x100e5000 0x1000>;
+ interrupts = <0 51 4>;
+ };
+
+ scu at 1e000000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x1e000000 0x58>;
+ };
+
+ timer at 1e000600 {
+ compatible = "arm,smp-twd";
+ reg = <0x1e000600 0x20>;
+ interrupts = <1 2 0xf04>,
+ <1 3 0xf04>;
+ };
+
+ gic: interrupt-controller at 1e001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1e001000 0x1000>,
+ <0x1e000100 0x100>;
+ };
+
+ L2: cache-controller at 1e00a000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1e00a000 0x1000>;
+ interrupts = <0 43 4>;
+ cache-level = <2>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <1 1 1>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 60 4>,
+ <0 61 4>,
+ <0 62 4>,
+ <0 63 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x40000000 0x04000000>,
+ <1 0 0x44000000 0x04000000>,
+ <2 0 0x48000000 0x04000000>,
+ <3 0 0x4c000000 0x04000000>,
+ <7 0 0x10000000 0x00020000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m.dtsi"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 5e2177e..2f0ad9f 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -4,4 +4,5 @@
params_phys-y := 0x60000100
initrd_phys-y := 0x60800000
-dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \
+ vexpress-v2p-ca9.dtb
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: devicetree-discuss, linux-arm-kernel; +Cc: Pawel Moll
This patch adds Device Tree file for the CoreTile Express A15x2
(V2P-CA15) with Test Chip 1.
As the chip's GIC has 160 interrupt inputs and equivalent SMM
(FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
increased.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 155 +++++++++++++++++++++++++++
arch/arm/mach-vexpress/Makefile.boot | 3 +-
arch/arm/mach-vexpress/include/mach/irqs.h | 2 +-
3 files changed, 158 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
new file mode 100644
index 0000000..02cada5
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -0,0 +1,155 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 (version with Test Chip 1)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ * HBI-0237A
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA15";
+ arm,hbi = <0x237>;
+ compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ i2c0 = &v2m_i2c_dvi;
+ i2c1 = &v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ hdlcd@2b000000 {
+ compatible = "arm,hdlcd";
+ reg = <0x2b000000 0x1000>;
+ interrupts = <0 85 4>;
+ };
+
+ memory-controller@2b0a0000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x2b0a0000 0x1000>;
+ };
+
+ wdt@2b060000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x2b060000 0x1000>;
+ interrupts = <98>;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2c001000 0x1000>,
+ <0x2c002000 0x100>;
+ };
+
+ memory-controller@7ffd0000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x7ffd0000 0x1000>;
+ interrupts = <0 86 4>,
+ <0 87 4>;
+ };
+
+ dma@7ffb0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x7ffb0000 0x1000>;
+ interrupts = <0 92 4>,
+ <0 88 4>,
+ <0 89 4>,
+ <0 90 4>,
+ <0 91 4>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 68 4>,
+ <0 69 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x08000000 0x04000000>,
+ <1 0 0x14000000 0x04000000>,
+ <2 0 0x18000000 0x04000000>,
+ <3 0 0x1c000000 0x04000000>,
+ <4 0 0x0c000000 0x04000000>,
+ <5 0 0x10000000 0x04000000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 2f0ad9f..909f85e 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -5,4 +5,5 @@ params_phys-y := 0x60000100
initrd_phys-y := 0x60800000
dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \
- vexpress-v2p-ca9.dtb
+ vexpress-v2p-ca9.dtb \
+ vexpress-v2p-ca15-tc1.dtb
diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h
index 7054cbf..4b10ee7 100644
--- a/arch/arm/mach-vexpress/include/mach/irqs.h
+++ b/arch/arm/mach-vexpress/include/mach/irqs.h
@@ -1,4 +1,4 @@
#define IRQ_LOCALTIMER 29
#define IRQ_LOCALWDOG 30
-#define NR_IRQS 128
+#define NR_IRQS 256
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2011-12-15 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 14:02 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds Device Tree file for the CoreTile Express A15x2
(V2P-CA15) with Test Chip 1.
As the chip's GIC has 160 interrupt inputs and equivalent SMM
(FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
increased.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 155 +++++++++++++++++++++++++++
arch/arm/mach-vexpress/Makefile.boot | 3 +-
arch/arm/mach-vexpress/include/mach/irqs.h | 2 +-
3 files changed, 158 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
new file mode 100644
index 0000000..02cada5
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -0,0 +1,155 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 (version with Test Chip 1)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ * HBI-0237A
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "V2P-CA15";
+ arm,hbi = <0x237>;
+ compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &v2m_serial0;
+ serial1 = &v2m_serial1;
+ serial2 = &v2m_serial2;
+ serial3 = &v2m_serial3;
+ i2c0 = &v2m_i2c_dvi;
+ i2c1 = &v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ };
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ hdlcd at 2b000000 {
+ compatible = "arm,hdlcd";
+ reg = <0x2b000000 0x1000>;
+ interrupts = <0 85 4>;
+ };
+
+ memory-controller at 2b0a0000 {
+ compatible = "arm,pl341", "arm,primecell";
+ reg = <0x2b0a0000 0x1000>;
+ };
+
+ wdt at 2b060000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x2b060000 0x1000>;
+ interrupts = <98>;
+ };
+
+ gic: interrupt-controller at 2c001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2c001000 0x1000>,
+ <0x2c002000 0x100>;
+ };
+
+ memory-controller at 7ffd0000 {
+ compatible = "arm,pl354", "arm,primecell";
+ reg = <0x7ffd0000 0x1000>;
+ interrupts = <0 86 4>,
+ <0 87 4>;
+ };
+
+ dma at 7ffb0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x7ffb0000 0x1000>;
+ interrupts = <0 92 4>,
+ <0 88 4>,
+ <0 89 4>,
+ <0 90 4>,
+ <0 91 4>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 68 4>,
+ <0 69 4>;
+ };
+
+ motherboard {
+ ranges = <0 0 0x08000000 0x04000000>,
+ <1 0 0x14000000 0x04000000>,
+ <2 0 0x18000000 0x04000000>,
+ <3 0 0x1c000000 0x04000000>,
+ <4 0 0x0c000000 0x04000000>,
+ <5 0 0x10000000 0x04000000>;
+
+ interrupt-map-mask = <0 0 63>;
+ interrupt-map = <0 0 0 &gic 0 0 4>,
+ <0 0 1 &gic 0 1 4>,
+ <0 0 2 &gic 0 2 4>,
+ <0 0 3 &gic 0 3 4>,
+ <0 0 4 &gic 0 4 4>,
+ <0 0 5 &gic 0 5 4>,
+ <0 0 6 &gic 0 6 4>,
+ <0 0 7 &gic 0 7 4>,
+ <0 0 8 &gic 0 8 4>,
+ <0 0 9 &gic 0 9 4>,
+ <0 0 10 &gic 0 10 4>,
+ <0 0 11 &gic 0 11 4>,
+ <0 0 12 &gic 0 12 4>,
+ <0 0 13 &gic 0 13 4>,
+ <0 0 14 &gic 0 14 4>,
+ <0 0 15 &gic 0 15 4>,
+ <0 0 16 &gic 0 16 4>,
+ <0 0 17 &gic 0 17 4>,
+ <0 0 18 &gic 0 18 4>,
+ <0 0 19 &gic 0 19 4>,
+ <0 0 20 &gic 0 20 4>,
+ <0 0 21 &gic 0 21 4>,
+ <0 0 22 &gic 0 22 4>,
+ <0 0 23 &gic 0 23 4>,
+ <0 0 24 &gic 0 24 4>,
+ <0 0 25 &gic 0 25 4>,
+ <0 0 26 &gic 0 26 4>,
+ <0 0 27 &gic 0 27 4>,
+ <0 0 28 &gic 0 28 4>,
+ <0 0 29 &gic 0 29 4>,
+ <0 0 30 &gic 0 30 4>,
+ <0 0 31 &gic 0 31 4>,
+ <0 0 32 &gic 0 32 4>,
+ <0 0 33 &gic 0 33 4>,
+ <0 0 34 &gic 0 34 4>,
+ <0 0 35 &gic 0 35 4>,
+ <0 0 36 &gic 0 36 4>,
+ <0 0 37 &gic 0 37 4>,
+ <0 0 38 &gic 0 38 4>,
+ <0 0 39 &gic 0 39 4>,
+ <0 0 40 &gic 0 40 4>,
+ <0 0 41 &gic 0 41 4>,
+ <0 0 42 &gic 0 42 4>;
+ };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 2f0ad9f..909f85e 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -5,4 +5,5 @@ params_phys-y := 0x60000100
initrd_phys-y := 0x60800000
dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \
- vexpress-v2p-ca9.dtb
+ vexpress-v2p-ca9.dtb \
+ vexpress-v2p-ca15-tc1.dtb
diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h
index 7054cbf..4b10ee7 100644
--- a/arch/arm/mach-vexpress/include/mach/irqs.h
+++ b/arch/arm/mach-vexpress/include/mach/irqs.h
@@ -1,4 +1,4 @@
#define IRQ_LOCALTIMER 29
#define IRQ_LOCALWDOG 30
-#define NR_IRQS 128
+#define NR_IRQS 256
--
1.7.5.4
^ permalink raw reply related [flat|nested] 76+ messages in thread
* Re: [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
2011-12-15 14:02 ` Pawel Moll
@ 2011-12-15 14:53 ` Rob Herring
-1 siblings, 0 replies; 76+ messages in thread
From: Rob Herring @ 2011-12-15 14:53 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 12/15/2011 08:02 AM, Pawel Moll wrote:
> Try to map TWD registers basing on a "arm,smp-twd" Device Tree
> node (compatible value as used in Highbank's DT). This overrides
> existing twd_base value.
>
> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> ---
> arch/arm/plat-versatile/localtimer.c | 12 ++++++++++++
> 1 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-versatile/localtimer.c b/arch/arm/plat-versatile/localtimer.c
> index 0fb3961..8f0dc10 100644
> --- a/arch/arm/plat-versatile/localtimer.c
> +++ b/arch/arm/plat-versatile/localtimer.c
> @@ -11,6 +11,8 @@
> #include <linux/init.h>
> #include <linux/smp.h>
> #include <linux/clockchips.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
>
> #include <asm/smp_twd.h>
> #include <asm/localtimer.h>
> @@ -21,6 +23,16 @@
> */
> int __cpuinit local_timer_setup(struct clock_event_device *evt)
> {
> +#if defined(CONFIG_OF)
> + struct device_node *node = of_find_compatible_node(NULL,
> + NULL, "arm,smp-twd");
> +
> + if (node)
> + twd_base = of_iomap(node, 0);
> +#endif
I think your previous version was more correct. This is going to find
the node and do ioremap N times where N is the number of cores. It does
work though because that is what I did initially too.
Rob
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
@ 2011-12-15 14:53 ` Rob Herring
0 siblings, 0 replies; 76+ messages in thread
From: Rob Herring @ 2011-12-15 14:53 UTC (permalink / raw)
To: linux-arm-kernel
On 12/15/2011 08:02 AM, Pawel Moll wrote:
> Try to map TWD registers basing on a "arm,smp-twd" Device Tree
> node (compatible value as used in Highbank's DT). This overrides
> existing twd_base value.
>
> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> ---
> arch/arm/plat-versatile/localtimer.c | 12 ++++++++++++
> 1 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-versatile/localtimer.c b/arch/arm/plat-versatile/localtimer.c
> index 0fb3961..8f0dc10 100644
> --- a/arch/arm/plat-versatile/localtimer.c
> +++ b/arch/arm/plat-versatile/localtimer.c
> @@ -11,6 +11,8 @@
> #include <linux/init.h>
> #include <linux/smp.h>
> #include <linux/clockchips.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
>
> #include <asm/smp_twd.h>
> #include <asm/localtimer.h>
> @@ -21,6 +23,16 @@
> */
> int __cpuinit local_timer_setup(struct clock_event_device *evt)
> {
> +#if defined(CONFIG_OF)
> + struct device_node *node = of_find_compatible_node(NULL,
> + NULL, "arm,smp-twd");
> +
> + if (node)
> + twd_base = of_iomap(node, 0);
> +#endif
I think your previous version was more correct. This is going to find
the node and do ioremap N times where N is the number of cores. It does
work though because that is what I did initially too.
Rob
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
2011-12-15 14:53 ` Rob Herring
@ 2011-12-15 15:25 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 15:25 UTC (permalink / raw)
To: Rob Herring; +Cc: devicetree-discuss, linux-arm-kernel
On Thu, 2011-12-15 at 14:53 +0000, Rob Herring wrote:
> > @@ -21,6 +23,16 @@
> > */
> > int __cpuinit local_timer_setup(struct clock_event_device *evt)
> > {
> > +#if defined(CONFIG_OF)
> > + struct device_node *node = of_find_compatible_node(NULL,
> > + NULL, "arm,smp-twd");
> > +
> > + if (node)
> > + twd_base = of_iomap(node, 0);
> > +#endif
>
> I think your previous version was more correct. This is going to find
> the node and do ioremap N times where N is the number of cores. It does
> work though because that is what I did initially too.
Right, how about that, then:
@@ -21,6 +23,22 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ static int dt_node_probed;
+
+ if (!dt_node_probed) {
+ struct device_node *node = of_find_compatible_node(NULL,
+ NULL, "arm,smp-twd");
+
+ if (node)
+ twd_base = of_iomap(node, 0);
+
+ dt_node_probed = 1;
+ }
+#endif
+ if (!twd_base)
+ return -ENXIO;
+
evt->irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
Cheers!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
@ 2011-12-15 15:25 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 15:25 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2011-12-15 at 14:53 +0000, Rob Herring wrote:
> > @@ -21,6 +23,16 @@
> > */
> > int __cpuinit local_timer_setup(struct clock_event_device *evt)
> > {
> > +#if defined(CONFIG_OF)
> > + struct device_node *node = of_find_compatible_node(NULL,
> > + NULL, "arm,smp-twd");
> > +
> > + if (node)
> > + twd_base = of_iomap(node, 0);
> > +#endif
>
> I think your previous version was more correct. This is going to find
> the node and do ioremap N times where N is the number of cores. It does
> work though because that is what I did initially too.
Right, how about that, then:
@@ -21,6 +23,22 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ static int dt_node_probed;
+
+ if (!dt_node_probed) {
+ struct device_node *node = of_find_compatible_node(NULL,
+ NULL, "arm,smp-twd");
+
+ if (node)
+ twd_base = of_iomap(node, 0);
+
+ dt_node_probed = 1;
+ }
+#endif
+ if (!twd_base)
+ return -ENXIO;
+
evt->irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
Cheers!
Pawe?
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
2011-12-15 15:25 ` Pawel Moll
@ 2011-12-15 17:25 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 17:25 UTC (permalink / raw)
To: Rob Herring; +Cc: devicetree-discuss, linux-arm-kernel
On Thu, 2011-12-15 at 15:25 +0000, Pawel Moll wrote:
> > I think your previous version was more correct. This is going to find
> > the node and do ioremap N times where N is the number of cores. It does
> > work though because that is what I did initially too.
>
> Right, how about that, then:
>
> @@ -21,6 +23,22 @@
> */
> int __cpuinit local_timer_setup(struct clock_event_device *evt)
> {
> +#if defined(CONFIG_OF)
> + static int dt_node_probed;
> +
> + if (!dt_node_probed) {
> + struct device_node *node = of_find_compatible_node(NULL,
> + NULL, "arm,smp-twd");
> +
> + if (node)
> + twd_base = of_iomap(node, 0);
> +
> + dt_node_probed = 1;
> + }
> +#endif
> + if (!twd_base)
> + return -ENXIO;
> +
> evt->irq = IRQ_LOCALTIMER;
> twd_timer_setup(evt);
> return 0;
Ok, so I have updated the both vexpress-dt and
vexpress-dt-rmk-devel-stable branches like that.
Arnd, Russell, the new pull request below.
I'll see you all next year!
Cheers!
Paweł
8<-------------------------------------------------------------------
The following changes since commit 55b02d2f4445ad625213817a1736bf2884d32547:
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux (2011-12-14 19:45:40 -0800)
are available in the git repository at:
git://git.linaro.org/people/pawelmoll/linux.git vexpress-dt
Pawel Moll (9):
ARM: versatile: Add missing ENDPROC to headsmp.S
ARM: vexpress: Get rid of MMIO_P2V
ARM: versatile: Map local timers using Device Tree when possible
ARM: vexpress: Use FDT data in platform SMP calls
ARM: vexpress: Add Device Tree support
ARM: vexpress: Motherboard RS1 memory map support
ARM: vexpress: Add Device Tree for V2P-CA5s core tile
ARM: vexpress: Add Device Tree for V2P-CA9 core tile
ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++++++++++
arch/arm/Kconfig | 2 +-
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 201 ++++++++++++++
arch/arm/boot/dts/vexpress-v2m.dtsi | 200 ++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 155 +++++++++++
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 160 +++++++++++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190 +++++++++++++
arch/arm/include/asm/hardware/arm_timer.h | 5 +
arch/arm/mach-realview/platsmp.c | 3 +-
arch/arm/mach-vexpress/Kconfig | 45 +++-
arch/arm/mach-vexpress/Makefile.boot | 6 +
arch/arm/mach-vexpress/core.h | 9 +-
arch/arm/mach-vexpress/ct-ca9x4.c | 48 +---
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++-
arch/arm/mach-vexpress/include/mach/irqs.h | 2 +-
arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++--
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +-
arch/arm/mach-vexpress/platsmp.c | 153 ++++++++++-
arch/arm/mach-vexpress/v2m.c | 282 ++++++++++++++++++--
arch/arm/mm/Kconfig | 2 +-
arch/arm/plat-versatile/headsmp.S | 1 +
arch/arm/plat-versatile/localtimer.c | 19 ++
23 files changed, 1628 insertions(+), 120 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
@ 2011-12-15 17:25 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2011-12-15 17:25 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2011-12-15 at 15:25 +0000, Pawel Moll wrote:
> > I think your previous version was more correct. This is going to find
> > the node and do ioremap N times where N is the number of cores. It does
> > work though because that is what I did initially too.
>
> Right, how about that, then:
>
> @@ -21,6 +23,22 @@
> */
> int __cpuinit local_timer_setup(struct clock_event_device *evt)
> {
> +#if defined(CONFIG_OF)
> + static int dt_node_probed;
> +
> + if (!dt_node_probed) {
> + struct device_node *node = of_find_compatible_node(NULL,
> + NULL, "arm,smp-twd");
> +
> + if (node)
> + twd_base = of_iomap(node, 0);
> +
> + dt_node_probed = 1;
> + }
> +#endif
> + if (!twd_base)
> + return -ENXIO;
> +
> evt->irq = IRQ_LOCALTIMER;
> twd_timer_setup(evt);
> return 0;
Ok, so I have updated the both vexpress-dt and
vexpress-dt-rmk-devel-stable branches like that.
Arnd, Russell, the new pull request below.
I'll see you all next year!
Cheers!
Pawe?
8<-------------------------------------------------------------------
The following changes since commit 55b02d2f4445ad625213817a1736bf2884d32547:
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux (2011-12-14 19:45:40 -0800)
are available in the git repository at:
git://git.linaro.org/people/pawelmoll/linux.git vexpress-dt
Pawel Moll (9):
ARM: versatile: Add missing ENDPROC to headsmp.S
ARM: vexpress: Get rid of MMIO_P2V
ARM: versatile: Map local timers using Device Tree when possible
ARM: vexpress: Use FDT data in platform SMP calls
ARM: vexpress: Add Device Tree support
ARM: vexpress: Motherboard RS1 memory map support
ARM: vexpress: Add Device Tree for V2P-CA5s core tile
ARM: vexpress: Add Device Tree for V2P-CA9 core tile
ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++++++++++
arch/arm/Kconfig | 2 +-
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 201 ++++++++++++++
arch/arm/boot/dts/vexpress-v2m.dtsi | 200 ++++++++++++++
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 155 +++++++++++
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 160 +++++++++++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190 +++++++++++++
arch/arm/include/asm/hardware/arm_timer.h | 5 +
arch/arm/mach-realview/platsmp.c | 3 +-
arch/arm/mach-vexpress/Kconfig | 45 +++-
arch/arm/mach-vexpress/Makefile.boot | 6 +
arch/arm/mach-vexpress/core.h | 9 +-
arch/arm/mach-vexpress/ct-ca9x4.c | 48 +---
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++-
arch/arm/mach-vexpress/include/mach/irqs.h | 2 +-
arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++--
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +-
arch/arm/mach-vexpress/platsmp.c | 153 ++++++++++-
arch/arm/mach-vexpress/v2m.c | 282 ++++++++++++++++++--
arch/arm/mm/Kconfig | 2 +-
arch/arm/plat-versatile/headsmp.S | 1 +
arch/arm/plat-versatile/localtimer.c | 19 ++
23 files changed, 1628 insertions(+), 120 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
2011-12-15 14:02 ` Pawel Moll
@ 2012-01-04 16:35 ` David Vrabel
-1 siblings, 0 replies; 76+ messages in thread
From: David Vrabel @ 2012-01-04 16:35 UTC (permalink / raw)
To: Pawel Moll; +Cc: devicetree-discuss, linux-arm-kernel
On 15/12/11 14:02, Pawel Moll wrote:
> This patch adds support for RS1 memory map based Versatile Express
> motherboard.
>
[...]
> --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
> +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
> @@ -10,12 +10,41 @@
> * published by the Free Software Foundation.
> */
>
> -#define DEBUG_LL_UART_OFFSET 0x00009000
> +#define DEBUG_LL_PHYS_BASE 0x10000000
> +#define DEBUG_LL_UART_OFFSET 0x00009000
> +
> +#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
> +#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
> +
> +#define DEBUG_LL_VIRT_BASE 0xf8000000
>
> .macro addruart,rp,rv,tmp
> - mov \rp, #DEBUG_LL_UART_OFFSET
> - orr \rv, \rp, #0xf8000000 @ virtual base
> - orr \rp, \rp, #0x10000000 @ physical base
> +
> + @ Check the MMU state
> +#if defined(CONFIG_MMU)
> + mrc p15, 0, \tmp, c1, c0 @ SCTRL
> + tst \tmp, #1 @ MMU enabled?
> + moveq \tmp, #DEBUG_LL_PHYS_BASE
> + movne \tmp, #DEBUG_LL_VIRT_BASE
> +#else
> + mov \tmp, #DEBUG_LL_PHYS_BASE
> +#endif
> +
> + @ PL011 present in "original" place?
> + orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
> + ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
This doesn't work with CONFIG_EARLY_PRINTK=y on a system with the RS1
memory map. __create_page_tables has only mapped the single physical
page at 0x1c090000 and thus the test for the UART in the other memory
map faults.
I made it work with this hack, but I'm not sure what the correct
solution would be.
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S
b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index 8010ff9..af443b4 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -30,6 +30,7 @@
mov \tmp, #DEBUG_LL_PHYS_BASE
#endif
+#if 0
@ PL011 present in "original" place?
orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
@@ -39,11 +40,12 @@
moveq \rp, #DEBUG_LL_UART_OFFSET
orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
+#endif
- @ RS1 memory map
- movne \rp, #DEBUG_LL_UART_OFFSET_RS1
- orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
- orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+ @ RS1 memory map
+ mov \rp, #DEBUG_LL_UART_OFFSET_RS1
+ mov \rv, \rp, #DEBUG_LL_VIRT_BASE
+ orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
.endm
> + teq \tmp, #0x11 @ PL011
> +
> + @ Original memory map
> + moveq \rp, #DEBUG_LL_UART_OFFSET
> + orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
> + orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
> +
> + @ RS1 memory map
> + movne \rp, #DEBUG_LL_UART_OFFSET_RS1
> + orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
> + orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
> +
> .endm
>
> #include <asm/hardware/debug-pl01x.S>
David
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
@ 2012-01-04 16:35 ` David Vrabel
0 siblings, 0 replies; 76+ messages in thread
From: David Vrabel @ 2012-01-04 16:35 UTC (permalink / raw)
To: linux-arm-kernel
On 15/12/11 14:02, Pawel Moll wrote:
> This patch adds support for RS1 memory map based Versatile Express
> motherboard.
>
[...]
> --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
> +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
> @@ -10,12 +10,41 @@
> * published by the Free Software Foundation.
> */
>
> -#define DEBUG_LL_UART_OFFSET 0x00009000
> +#define DEBUG_LL_PHYS_BASE 0x10000000
> +#define DEBUG_LL_UART_OFFSET 0x00009000
> +
> +#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
> +#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
> +
> +#define DEBUG_LL_VIRT_BASE 0xf8000000
>
> .macro addruart,rp,rv,tmp
> - mov \rp, #DEBUG_LL_UART_OFFSET
> - orr \rv, \rp, #0xf8000000 @ virtual base
> - orr \rp, \rp, #0x10000000 @ physical base
> +
> + @ Check the MMU state
> +#if defined(CONFIG_MMU)
> + mrc p15, 0, \tmp, c1, c0 @ SCTRL
> + tst \tmp, #1 @ MMU enabled?
> + moveq \tmp, #DEBUG_LL_PHYS_BASE
> + movne \tmp, #DEBUG_LL_VIRT_BASE
> +#else
> + mov \tmp, #DEBUG_LL_PHYS_BASE
> +#endif
> +
> + @ PL011 present in "original" place?
> + orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
> + ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
This doesn't work with CONFIG_EARLY_PRINTK=y on a system with the RS1
memory map. __create_page_tables has only mapped the single physical
page at 0x1c090000 and thus the test for the UART in the other memory
map faults.
I made it work with this hack, but I'm not sure what the correct
solution would be.
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S
b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index 8010ff9..af443b4 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -30,6 +30,7 @@
mov \tmp, #DEBUG_LL_PHYS_BASE
#endif
+#if 0
@ PL011 present in "original" place?
orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
@@ -39,11 +40,12 @@
moveq \rp, #DEBUG_LL_UART_OFFSET
orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
+#endif
- @ RS1 memory map
- movne \rp, #DEBUG_LL_UART_OFFSET_RS1
- orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
- orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+ @ RS1 memory map
+ mov \rp, #DEBUG_LL_UART_OFFSET_RS1
+ mov \rv, \rp, #DEBUG_LL_VIRT_BASE
+ orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
.endm
> + teq \tmp, #0x11 @ PL011
> +
> + @ Original memory map
> + moveq \rp, #DEBUG_LL_UART_OFFSET
> + orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
> + orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
> +
> + @ RS1 memory map
> + movne \rp, #DEBUG_LL_UART_OFFSET_RS1
> + orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
> + orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
> +
> .endm
>
> #include <asm/hardware/debug-pl01x.S>
David
^ permalink raw reply related [flat|nested] 76+ messages in thread
* Re: [PATCH v6 5/9] ARM: vexpress: Add Device Tree support
2011-12-15 14:02 ` Pawel Moll
@ 2012-01-10 11:13 ` Jon Medhurst (Tixy)
-1 siblings, 0 replies; 76+ messages in thread
From: Jon Medhurst (Tixy) @ 2012-01-10 11:13 UTC (permalink / raw)
To: Pawel Moll; +Cc: devicetree-discuss, linux-arm-kernel
On Thu, 2011-12-15 at 14:02 +0000, Pawel Moll wrote:
> This patch adds generic Versatile Express DT machine description,
> Device Tree description for the motherboard and documentation for
> the bindings.
[...]
> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
[...]
> +DT_MACHINE_START(VEXPRESS_DT, "ARM Versatile Express")
> + .map_io = v2m_dt_map_io,
> + .init_early = v2m_dt_init_early,
> + .init_irq = v2m_dt_init_irq,
> + .timer = &v2m_dt_timer,
> + .init_machine = v2m_dt_init,
> + .dt_compat = v2m_dt_match,
> +MACHINE_END
The machine name here is missing a '-' that is in the original non
device-tree machine description, which is "ARM-Versatile Express".
The hyphen is also in Integrator and Realview machine names, so this
seems to be a convention with ARM boards.
(I found this because Android parses machine name for configuration
purposes.)
--
Tixy
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 5/9] ARM: vexpress: Add Device Tree support
@ 2012-01-10 11:13 ` Jon Medhurst (Tixy)
0 siblings, 0 replies; 76+ messages in thread
From: Jon Medhurst (Tixy) @ 2012-01-10 11:13 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2011-12-15 at 14:02 +0000, Pawel Moll wrote:
> This patch adds generic Versatile Express DT machine description,
> Device Tree description for the motherboard and documentation for
> the bindings.
[...]
> diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
[...]
> +DT_MACHINE_START(VEXPRESS_DT, "ARM Versatile Express")
> + .map_io = v2m_dt_map_io,
> + .init_early = v2m_dt_init_early,
> + .init_irq = v2m_dt_init_irq,
> + .timer = &v2m_dt_timer,
> + .init_machine = v2m_dt_init,
> + .dt_compat = v2m_dt_match,
> +MACHINE_END
The machine name here is missing a '-' that is in the original non
device-tree machine description, which is "ARM-Versatile Express".
The hyphen is also in Integrator and Realview machine names, so this
seems to be a convention with ARM boards.
(I found this because Android parses machine name for configuration
purposes.)
--
Tixy
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2011-12-15 14:02 ` Pawel Moll
@ 2012-01-10 14:21 ` David Vrabel
-1 siblings, 0 replies; 76+ messages in thread
From: David Vrabel @ 2012-01-10 14:21 UTC (permalink / raw)
To: Pawel Moll; +Cc: devicetree-discuss, linux-arm-kernel
On 15/12/11 14:02, Pawel Moll wrote:
> This patch adds Device Tree file for the CoreTile Express A15x2
> (V2P-CA15) with Test Chip 1.
This doesn't work as-is with the software model as accessing some of the
peripherals that aren't modeled will cause an exception. Is it worth
having a device tree file suitable for the models? Or are the models too
configurable for this to be workable?
> As the chip's GIC has 160 interrupt inputs and equivalent SMM
> (FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
> increased.
>
[...]
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
[...]
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x40000000>;
> + };
If CONFIG_ARM_ATAG_DTB_COMPAT is enabled the device tree will end up
with two nodes describing the memory ("memory" and "memory@80000000" in
this case).
>From 22cc6a3410077b99d81e42c4d7f4e29eab6070e3 Mon Sep 17 00:00:00 2001
From: David Vrabel <david.vrabel@citrix.com>
Date: Mon, 9 Jan 2012 16:13:19 +0000
Subject: [PATCH] ARM: vexpress: rename device tree "memory@..." nodes to
"memory"
If CONFIG_ARM_ATAG_DTB_COMPAT enabled it expects the memory
information to be in a node named "memory". If the memory is
described in a different node, the device tree will end up with two
nodes describing the memory.
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
---
arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts
b/arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts
index 064132e..6667936 100644
--- a/arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts
@@ -33,7 +33,7 @@
};
};
- memory@80000000 {
+ memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 02cada5..0d82ac8 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -43,7 +43,7 @@
};
};
- memory@80000000 {
+ memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index da26a13..e4c3935 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -45,7 +45,7 @@
};
};
- memory@80000000 {
+ memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 84542e7..d4aa1cc 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -59,7 +59,7 @@
};
};
- memory@60000000 {
+ memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
--
1.7.2.5
David
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-10 14:21 ` David Vrabel
0 siblings, 0 replies; 76+ messages in thread
From: David Vrabel @ 2012-01-10 14:21 UTC (permalink / raw)
To: linux-arm-kernel
On 15/12/11 14:02, Pawel Moll wrote:
> This patch adds Device Tree file for the CoreTile Express A15x2
> (V2P-CA15) with Test Chip 1.
This doesn't work as-is with the software model as accessing some of the
peripherals that aren't modeled will cause an exception. Is it worth
having a device tree file suitable for the models? Or are the models too
configurable for this to be workable?
> As the chip's GIC has 160 interrupt inputs and equivalent SMM
> (FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
> increased.
>
[...]
> --- /dev/null
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
[...]
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x40000000>;
> + };
If CONFIG_ARM_ATAG_DTB_COMPAT is enabled the device tree will end up
with two nodes describing the memory ("memory" and "memory at 80000000" in
this case).
>From 22cc6a3410077b99d81e42c4d7f4e29eab6070e3 Mon Sep 17 00:00:00 2001
From: David Vrabel <david.vrabel@citrix.com>
Date: Mon, 9 Jan 2012 16:13:19 +0000
Subject: [PATCH] ARM: vexpress: rename device tree "memory at ..." nodes to
"memory"
If CONFIG_ARM_ATAG_DTB_COMPAT enabled it expects the memory
information to be in a node named "memory". If the memory is
described in a different node, the device tree will end up with two
nodes describing the memory.
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
---
arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts
b/arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts
index 064132e..6667936 100644
--- a/arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-aem-v7a.dts
@@ -33,7 +33,7 @@
};
};
- memory at 80000000 {
+ memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 02cada5..0d82ac8 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -43,7 +43,7 @@
};
};
- memory at 80000000 {
+ memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index da26a13..e4c3935 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -45,7 +45,7 @@
};
};
- memory at 80000000 {
+ memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 84542e7..d4aa1cc 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -59,7 +59,7 @@
};
};
- memory at 60000000 {
+ memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
--
1.7.2.5
David
^ permalink raw reply related [flat|nested] 76+ messages in thread
* Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
2012-01-04 16:35 ` David Vrabel
@ 2012-01-19 13:21 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 13:21 UTC (permalink / raw)
To: David Vrabel; +Cc: devicetree-discuss, linux-arm-kernel
Hi,
Sorry about loooong delay - I've been on holiday.
On Wed, 2012-01-04 at 16:35 +0000, David Vrabel wrote:
> On 15/12/11 14:02, Pawel Moll wrote:
> > This patch adds support for RS1 memory map based Versatile Express
> > motherboard.
> >
> [...]
> > --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
> > +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
> > @@ -10,12 +10,41 @@
> > * published by the Free Software Foundation.
> > */
> >
> > -#define DEBUG_LL_UART_OFFSET 0x00009000
> > +#define DEBUG_LL_PHYS_BASE 0x10000000
> > +#define DEBUG_LL_UART_OFFSET 0x00009000
> > +
> > +#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
> > +#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
> > +
> > +#define DEBUG_LL_VIRT_BASE 0xf8000000
> >
> > .macro addruart,rp,rv,tmp
> > - mov \rp, #DEBUG_LL_UART_OFFSET
> > - orr \rv, \rp, #0xf8000000 @ virtual base
> > - orr \rp, \rp, #0x10000000 @ physical base
> > +
> > + @ Check the MMU state
> > +#if defined(CONFIG_MMU)
> > + mrc p15, 0, \tmp, c1, c0 @ SCTRL
> > + tst \tmp, #1 @ MMU enabled?
> > + moveq \tmp, #DEBUG_LL_PHYS_BASE
> > + movne \tmp, #DEBUG_LL_VIRT_BASE
> > +#else
> > + mov \tmp, #DEBUG_LL_PHYS_BASE
> > +#endif
> > +
> > + @ PL011 present in "original" place?
> > + orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
> > + ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
>
> This doesn't work with CONFIG_EARLY_PRINTK=y on a system with the RS1
> memory map.
It does for me:
# zcat /proc/config.gz | grep EARLY_PRINTK
CONFIG_EARLY_PRINTK=y
# cat /proc/device-tree/motherboard/arm,v2m-memory-map && echo
rs1
#
Can you tell me what exactly is going wrong in your case? Does it hang
without any warning? Do you get at least part of the boot log? Can you
send me (privately probably) your kernel config?
> __create_page_tables has only mapped the single physical
> page at 0x1c090000 and thus the test for the UART in the other memory
> map faults.
I investigated this when writing the code and I vaguely remember it was
fine, partly by accident. I'll dig in again and let you know my
findings.
Thanks for trying this out!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
@ 2012-01-19 13:21 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 13:21 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Sorry about loooong delay - I've been on holiday.
On Wed, 2012-01-04 at 16:35 +0000, David Vrabel wrote:
> On 15/12/11 14:02, Pawel Moll wrote:
> > This patch adds support for RS1 memory map based Versatile Express
> > motherboard.
> >
> [...]
> > --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
> > +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
> > @@ -10,12 +10,41 @@
> > * published by the Free Software Foundation.
> > */
> >
> > -#define DEBUG_LL_UART_OFFSET 0x00009000
> > +#define DEBUG_LL_PHYS_BASE 0x10000000
> > +#define DEBUG_LL_UART_OFFSET 0x00009000
> > +
> > +#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
> > +#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
> > +
> > +#define DEBUG_LL_VIRT_BASE 0xf8000000
> >
> > .macro addruart,rp,rv,tmp
> > - mov \rp, #DEBUG_LL_UART_OFFSET
> > - orr \rv, \rp, #0xf8000000 @ virtual base
> > - orr \rp, \rp, #0x10000000 @ physical base
> > +
> > + @ Check the MMU state
> > +#if defined(CONFIG_MMU)
> > + mrc p15, 0, \tmp, c1, c0 @ SCTRL
> > + tst \tmp, #1 @ MMU enabled?
> > + moveq \tmp, #DEBUG_LL_PHYS_BASE
> > + movne \tmp, #DEBUG_LL_VIRT_BASE
> > +#else
> > + mov \tmp, #DEBUG_LL_PHYS_BASE
> > +#endif
> > +
> > + @ PL011 present in "original" place?
> > + orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
> > + ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
>
> This doesn't work with CONFIG_EARLY_PRINTK=y on a system with the RS1
> memory map.
It does for me:
# zcat /proc/config.gz | grep EARLY_PRINTK
CONFIG_EARLY_PRINTK=y
# cat /proc/device-tree/motherboard/arm,v2m-memory-map && echo
rs1
#
Can you tell me what exactly is going wrong in your case? Does it hang
without any warning? Do you get at least part of the boot log? Can you
send me (privately probably) your kernel config?
> __create_page_tables has only mapped the single physical
> page at 0x1c090000 and thus the test for the UART in the other memory
> map faults.
I investigated this when writing the code and I vaguely remember it was
fine, partly by accident. I'll dig in again and let you know my
findings.
Thanks for trying this out!
Pawe?
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-10 14:21 ` David Vrabel
@ 2012-01-19 13:27 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 13:27 UTC (permalink / raw)
To: David Vrabel, rob.herring; +Cc: devicetree-discuss, linux-arm-kernel
On Tue, 2012-01-10 at 14:21 +0000, David Vrabel wrote:
> On 15/12/11 14:02, Pawel Moll wrote:
> > This patch adds Device Tree file for the CoreTile Express A15x2
> > (V2P-CA15) with Test Chip 1.
>
> This doesn't work as-is with the software model as accessing some of the
> peripherals that aren't modeled will cause an exception. Is it worth
> having a device tree file suitable for the models? Or are the models too
> configurable for this to be workable?
The model as you have it doesn't exactly represent the board for a
number of reasons, mainly because there was no hardware design when the
model was created, so some of the solution was best-guessed by the model
people. Anyway, current A15 model can't be considered a 1-to-1
equivalent of the VE board. The plan is that the models will be shipped
with their own DTSes. I'll work on that in the following months, I can
keep you updated (and use as a beta tester ;-) if you want.
> > As the chip's GIC has 160 interrupt inputs and equivalent SMM
> > (FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
> > increased.
> >
> [...]
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
> [...]
> > + memory@80000000 {
> > + device_type = "memory";
> > + reg = <0x80000000 0x40000000>;
> > + };
>
> If CONFIG_ARM_ATAG_DTB_COMPAT is enabled the device tree will end up
> with two nodes describing the memory ("memory" and "memory@80000000" in
> this case).
You're right - the skeleton.dtsi contains "memory" mode... Funnily
enough originally I was using that name, but then Rob Herring suggested
changing it to @80000000, which seemed reasonable.
Now I wonder - is the "memory" node special and should not contain
"@address", or the skelton shouldn't contain the empty "memory" node...
Cheers!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 13:27 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 13:27 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 2012-01-10 at 14:21 +0000, David Vrabel wrote:
> On 15/12/11 14:02, Pawel Moll wrote:
> > This patch adds Device Tree file for the CoreTile Express A15x2
> > (V2P-CA15) with Test Chip 1.
>
> This doesn't work as-is with the software model as accessing some of the
> peripherals that aren't modeled will cause an exception. Is it worth
> having a device tree file suitable for the models? Or are the models too
> configurable for this to be workable?
The model as you have it doesn't exactly represent the board for a
number of reasons, mainly because there was no hardware design when the
model was created, so some of the solution was best-guessed by the model
people. Anyway, current A15 model can't be considered a 1-to-1
equivalent of the VE board. The plan is that the models will be shipped
with their own DTSes. I'll work on that in the following months, I can
keep you updated (and use as a beta tester ;-) if you want.
> > As the chip's GIC has 160 interrupt inputs and equivalent SMM
> > (FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
> > increased.
> >
> [...]
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
> [...]
> > + memory at 80000000 {
> > + device_type = "memory";
> > + reg = <0x80000000 0x40000000>;
> > + };
>
> If CONFIG_ARM_ATAG_DTB_COMPAT is enabled the device tree will end up
> with two nodes describing the memory ("memory" and "memory at 80000000" in
> this case).
You're right - the skeleton.dtsi contains "memory" mode... Funnily
enough originally I was using that name, but then Rob Herring suggested
changing it to @80000000, which seemed reasonable.
Now I wonder - is the "memory" node special and should not contain
"@address", or the skelton shouldn't contain the empty "memory" node...
Cheers!
Pawe?
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 13:27 ` Pawel Moll
@ 2012-01-19 13:34 ` Rob Herring
-1 siblings, 0 replies; 76+ messages in thread
From: Rob Herring @ 2012-01-19 13:34 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, David Vrabel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 01/19/2012 07:27 AM, Pawel Moll wrote:
> On Tue, 2012-01-10 at 14:21 +0000, David Vrabel wrote:
>> On 15/12/11 14:02, Pawel Moll wrote:
>>> This patch adds Device Tree file for the CoreTile Express A15x2
>>> (V2P-CA15) with Test Chip 1.
>>
>> This doesn't work as-is with the software model as accessing some of the
>> peripherals that aren't modeled will cause an exception. Is it worth
>> having a device tree file suitable for the models? Or are the models too
>> configurable for this to be workable?
>
> The model as you have it doesn't exactly represent the board for a
> number of reasons, mainly because there was no hardware design when the
> model was created, so some of the solution was best-guessed by the model
> people. Anyway, current A15 model can't be considered a 1-to-1
> equivalent of the VE board. The plan is that the models will be shipped
> with their own DTSes. I'll work on that in the following months, I can
> keep you updated (and use as a beta tester ;-) if you want.
>
>>> As the chip's GIC has 160 interrupt inputs and equivalent SMM
>>> (FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
>>> increased.
>>>
>> [...]
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
>> [...]
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> + reg = <0x80000000 0x40000000>;
>>> + };
>>
>> If CONFIG_ARM_ATAG_DTB_COMPAT is enabled the device tree will end up
>> with two nodes describing the memory ("memory" and "memory@80000000" in
>> this case).
>
> You're right - the skeleton.dtsi contains "memory" mode... Funnily
> enough originally I was using that name, but then Rob Herring suggested
> changing it to @80000000, which seemed reasonable.
>
> Now I wonder - is the "memory" node special and should not contain
> "@address", or the skelton shouldn't contain the empty "memory" node...
>
Hummm... I guess you should just use "memory" if you are using
skeleton.dtsi.
Rob
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 13:34 ` Rob Herring
0 siblings, 0 replies; 76+ messages in thread
From: Rob Herring @ 2012-01-19 13:34 UTC (permalink / raw)
To: linux-arm-kernel
On 01/19/2012 07:27 AM, Pawel Moll wrote:
> On Tue, 2012-01-10 at 14:21 +0000, David Vrabel wrote:
>> On 15/12/11 14:02, Pawel Moll wrote:
>>> This patch adds Device Tree file for the CoreTile Express A15x2
>>> (V2P-CA15) with Test Chip 1.
>>
>> This doesn't work as-is with the software model as accessing some of the
>> peripherals that aren't modeled will cause an exception. Is it worth
>> having a device tree file suitable for the models? Or are the models too
>> configurable for this to be workable?
>
> The model as you have it doesn't exactly represent the board for a
> number of reasons, mainly because there was no hardware design when the
> model was created, so some of the solution was best-guessed by the model
> people. Anyway, current A15 model can't be considered a 1-to-1
> equivalent of the VE board. The plan is that the models will be shipped
> with their own DTSes. I'll work on that in the following months, I can
> keep you updated (and use as a beta tester ;-) if you want.
>
>>> As the chip's GIC has 160 interrupt inputs and equivalent SMM
>>> (FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
>>> increased.
>>>
>> [...]
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
>> [...]
>>> + memory at 80000000 {
>>> + device_type = "memory";
>>> + reg = <0x80000000 0x40000000>;
>>> + };
>>
>> If CONFIG_ARM_ATAG_DTB_COMPAT is enabled the device tree will end up
>> with two nodes describing the memory ("memory" and "memory at 80000000" in
>> this case).
>
> You're right - the skeleton.dtsi contains "memory" mode... Funnily
> enough originally I was using that name, but then Rob Herring suggested
> changing it to @80000000, which seemed reasonable.
>
> Now I wonder - is the "memory" node special and should not contain
> "@address", or the skelton shouldn't contain the empty "memory" node...
>
Hummm... I guess you should just use "memory" if you are using
skeleton.dtsi.
Rob
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 13:34 ` Rob Herring
@ 2012-01-19 13:43 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 13:43 UTC (permalink / raw)
To: Rob Herring; +Cc: devicetree-discuss, David Vrabel, linux-arm-kernel
On Thu, 2012-01-19 at 13:34 +0000, Rob Herring wrote:
> > You're right - the skeleton.dtsi contains "memory" mode... Funnily
> > enough originally I was using that name, but then Rob Herring suggested
> > changing it to @80000000, which seemed reasonable.
> >
> > Now I wonder - is the "memory" node special and should not contain
> > "@address", or the skelton shouldn't contain the empty "memory" node...
> >
>
> Hummm... I guess you should just use "memory" if you are using
> skeleton.dtsi.
Well, I don't mind _not_ using skeleton, but I had an impression the
general policy was to use it?
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 13:43 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 13:43 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2012-01-19 at 13:34 +0000, Rob Herring wrote:
> > You're right - the skeleton.dtsi contains "memory" mode... Funnily
> > enough originally I was using that name, but then Rob Herring suggested
> > changing it to @80000000, which seemed reasonable.
> >
> > Now I wonder - is the "memory" node special and should not contain
> > "@address", or the skelton shouldn't contain the empty "memory" node...
> >
>
> Hummm... I guess you should just use "memory" if you are using
> skeleton.dtsi.
Well, I don't mind _not_ using skeleton, but I had an impression the
general policy was to use it?
Pawe?
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 13:43 ` Pawel Moll
@ 2012-01-19 14:01 ` Rob Herring
-1 siblings, 0 replies; 76+ messages in thread
From: Rob Herring @ 2012-01-19 14:01 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, David Vrabel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 01/19/2012 07:43 AM, Pawel Moll wrote:
> On Thu, 2012-01-19 at 13:34 +0000, Rob Herring wrote:
>>> You're right - the skeleton.dtsi contains "memory" mode... Funnily
>>> enough originally I was using that name, but then Rob Herring suggested
>>> changing it to @80000000, which seemed reasonable.
>>>
>>> Now I wonder - is the "memory" node special and should not contain
>>> "@address", or the skelton shouldn't contain the empty "memory" node...
>>>
>>
>> Hummm... I guess you should just use "memory" if you are using
>> skeleton.dtsi.
>
> Well, I don't mind _not_ using skeleton, but I had an impression the
> general policy was to use it?
Either way is fine. I don't really think it buys you much.
Rob
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 14:01 ` Rob Herring
0 siblings, 0 replies; 76+ messages in thread
From: Rob Herring @ 2012-01-19 14:01 UTC (permalink / raw)
To: linux-arm-kernel
On 01/19/2012 07:43 AM, Pawel Moll wrote:
> On Thu, 2012-01-19 at 13:34 +0000, Rob Herring wrote:
>>> You're right - the skeleton.dtsi contains "memory" mode... Funnily
>>> enough originally I was using that name, but then Rob Herring suggested
>>> changing it to @80000000, which seemed reasonable.
>>>
>>> Now I wonder - is the "memory" node special and should not contain
>>> "@address", or the skelton shouldn't contain the empty "memory" node...
>>>
>>
>> Hummm... I guess you should just use "memory" if you are using
>> skeleton.dtsi.
>
> Well, I don't mind _not_ using skeleton, but I had an impression the
> general policy was to use it?
Either way is fine. I don't really think it buys you much.
Rob
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 14:01 ` Rob Herring
@ 2012-01-19 14:51 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 14:51 UTC (permalink / raw)
To: Rob Herring; +Cc: devicetree-discuss, David Vrabel, linux-arm-kernel
On Thu, 2012-01-19 at 14:01 +0000, Rob Herring wrote:
> On 01/19/2012 07:43 AM, Pawel Moll wrote:
> > On Thu, 2012-01-19 at 13:34 +0000, Rob Herring wrote:
> >>> You're right - the skeleton.dtsi contains "memory" mode... Funnily
> >>> enough originally I was using that name, but then Rob Herring suggested
> >>> changing it to @80000000, which seemed reasonable.
> >>>
> >>> Now I wonder - is the "memory" node special and should not contain
> >>> "@address", or the skelton shouldn't contain the empty "memory" node...
> >>>
> >>
> >> Hummm... I guess you should just use "memory" if you are using
> >> skeleton.dtsi.
> >
> > Well, I don't mind _not_ using skeleton, but I had an impression the
> > general policy was to use it?
>
> Either way is fine. I don't really think it buys you much.
Ok, /include/ "skeleton.dtsi" is gone then :-)
Cheers!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 14:51 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 14:51 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2012-01-19 at 14:01 +0000, Rob Herring wrote:
> On 01/19/2012 07:43 AM, Pawel Moll wrote:
> > On Thu, 2012-01-19 at 13:34 +0000, Rob Herring wrote:
> >>> You're right - the skeleton.dtsi contains "memory" mode... Funnily
> >>> enough originally I was using that name, but then Rob Herring suggested
> >>> changing it to @80000000, which seemed reasonable.
> >>>
> >>> Now I wonder - is the "memory" node special and should not contain
> >>> "@address", or the skelton shouldn't contain the empty "memory" node...
> >>>
> >>
> >> Hummm... I guess you should just use "memory" if you are using
> >> skeleton.dtsi.
> >
> > Well, I don't mind _not_ using skeleton, but I had an impression the
> > general policy was to use it?
>
> Either way is fine. I don't really think it buys you much.
Ok, /include/ "skeleton.dtsi" is gone then :-)
Cheers!
Pawe?
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
2012-01-19 13:21 ` Pawel Moll
@ 2012-01-19 16:46 ` David Vrabel
-1 siblings, 0 replies; 76+ messages in thread
From: David Vrabel @ 2012-01-19 16:46 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 19/01/12 13:21, Pawel Moll wrote:
> Hi,
>
> Sorry about loooong delay - I've been on holiday.
>
> On Wed, 2012-01-04 at 16:35 +0000, David Vrabel wrote:
>> On 15/12/11 14:02, Pawel Moll wrote:
>>> This patch adds support for RS1 memory map based Versatile Express
>>> motherboard.
>>>
>> [...]
>>> --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
>>> +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
>>> @@ -10,12 +10,41 @@
>>> * published by the Free Software Foundation.
>>> */
>>>
>>> -#define DEBUG_LL_UART_OFFSET 0x00009000
>>> +#define DEBUG_LL_PHYS_BASE 0x10000000
>>> +#define DEBUG_LL_UART_OFFSET 0x00009000
>>> +
>>> +#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
>>> +#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
>>> +
>>> +#define DEBUG_LL_VIRT_BASE 0xf8000000
>>>
>>> .macro addruart,rp,rv,tmp
>>> - mov \rp, #DEBUG_LL_UART_OFFSET
>>> - orr \rv, \rp, #0xf8000000 @ virtual base
>>> - orr \rp, \rp, #0x10000000 @ physical base
>>> +
>>> + @ Check the MMU state
>>> +#if defined(CONFIG_MMU)
>>> + mrc p15, 0, \tmp, c1, c0 @ SCTRL
>>> + tst \tmp, #1 @ MMU enabled?
>>> + moveq \tmp, #DEBUG_LL_PHYS_BASE
>>> + movne \tmp, #DEBUG_LL_VIRT_BASE
>>> +#else
>>> + mov \tmp, #DEBUG_LL_PHYS_BASE
>>> +#endif
>>> +
>>> + @ PL011 present in "original" place?
>>> + orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
>>> + ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
>>
>> This doesn't work with CONFIG_EARLY_PRINTK=y on a system with the RS1
>> memory map.
>
> It does for me:
>
> # zcat /proc/config.gz | grep EARLY_PRINTK
> CONFIG_EARLY_PRINTK=y
> # cat /proc/device-tree/motherboard/arm,v2m-memory-map && echo
> rs1
> #
earlyprintk needs to be on the kernel command line to enable it.
Without this option it will work fine.
> Can you tell me what exactly is going wrong in your case? Does it hang
> without any warning? Do you get at least part of the boot log? Can you
> send me (privately probably) your kernel config?
The only output is from the zImage decompressor.
It's a synchronous data fault and DFAR is 0xf8009fe0.
>> __create_page_tables has only mapped the single physical
>> page at 0x1c090000 and thus the test for the UART in the other memory
>> map faults.
>
> I investigated this when writing the code and I vaguely remember it was
> fine, partly by accident. I'll dig in again and let you know my
> findings.
It's also a problem when running as a guest under a hypervisor as there
won't be any stage 2 translation table entries for non-existent peripherals.
I think there needs to be someway of finding out from the DTB which UART
to use.
David
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
@ 2012-01-19 16:46 ` David Vrabel
0 siblings, 0 replies; 76+ messages in thread
From: David Vrabel @ 2012-01-19 16:46 UTC (permalink / raw)
To: linux-arm-kernel
On 19/01/12 13:21, Pawel Moll wrote:
> Hi,
>
> Sorry about loooong delay - I've been on holiday.
>
> On Wed, 2012-01-04 at 16:35 +0000, David Vrabel wrote:
>> On 15/12/11 14:02, Pawel Moll wrote:
>>> This patch adds support for RS1 memory map based Versatile Express
>>> motherboard.
>>>
>> [...]
>>> --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
>>> +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
>>> @@ -10,12 +10,41 @@
>>> * published by the Free Software Foundation.
>>> */
>>>
>>> -#define DEBUG_LL_UART_OFFSET 0x00009000
>>> +#define DEBUG_LL_PHYS_BASE 0x10000000
>>> +#define DEBUG_LL_UART_OFFSET 0x00009000
>>> +
>>> +#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
>>> +#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
>>> +
>>> +#define DEBUG_LL_VIRT_BASE 0xf8000000
>>>
>>> .macro addruart,rp,rv,tmp
>>> - mov \rp, #DEBUG_LL_UART_OFFSET
>>> - orr \rv, \rp, #0xf8000000 @ virtual base
>>> - orr \rp, \rp, #0x10000000 @ physical base
>>> +
>>> + @ Check the MMU state
>>> +#if defined(CONFIG_MMU)
>>> + mrc p15, 0, \tmp, c1, c0 @ SCTRL
>>> + tst \tmp, #1 @ MMU enabled?
>>> + moveq \tmp, #DEBUG_LL_PHYS_BASE
>>> + movne \tmp, #DEBUG_LL_VIRT_BASE
>>> +#else
>>> + mov \tmp, #DEBUG_LL_PHYS_BASE
>>> +#endif
>>> +
>>> + @ PL011 present in "original" place?
>>> + orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
>>> + ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
>>
>> This doesn't work with CONFIG_EARLY_PRINTK=y on a system with the RS1
>> memory map.
>
> It does for me:
>
> # zcat /proc/config.gz | grep EARLY_PRINTK
> CONFIG_EARLY_PRINTK=y
> # cat /proc/device-tree/motherboard/arm,v2m-memory-map && echo
> rs1
> #
earlyprintk needs to be on the kernel command line to enable it.
Without this option it will work fine.
> Can you tell me what exactly is going wrong in your case? Does it hang
> without any warning? Do you get at least part of the boot log? Can you
> send me (privately probably) your kernel config?
The only output is from the zImage decompressor.
It's a synchronous data fault and DFAR is 0xf8009fe0.
>> __create_page_tables has only mapped the single physical
>> page at 0x1c090000 and thus the test for the UART in the other memory
>> map faults.
>
> I investigated this when writing the code and I vaguely remember it was
> fine, partly by accident. I'll dig in again and let you know my
> findings.
It's also a problem when running as a guest under a hypervisor as there
won't be any stage 2 translation table entries for non-existent peripherals.
I think there needs to be someway of finding out from the DTB which UART
to use.
David
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 14:51 ` Pawel Moll
@ 2012-01-19 17:00 ` David Vrabel
-1 siblings, 0 replies; 76+ messages in thread
From: David Vrabel @ 2012-01-19 17:00 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 19/01/12 14:51, Pawel Moll wrote:
> On Thu, 2012-01-19 at 14:01 +0000, Rob Herring wrote:
>> On 01/19/2012 07:43 AM, Pawel Moll wrote:
>>> On Thu, 2012-01-19 at 13:34 +0000, Rob Herring wrote:
>>>>> You're right - the skeleton.dtsi contains "memory" mode... Funnily
>>>>> enough originally I was using that name, but then Rob Herring suggested
>>>>> changing it to @80000000, which seemed reasonable.
>>>>>
>>>>> Now I wonder - is the "memory" node special and should not contain
>>>>> "@address", or the skelton shouldn't contain the empty "memory" node...
>>>>>
>>>>
>>>> Hummm... I guess you should just use "memory" if you are using
>>>> skeleton.dtsi.
>>>
>>> Well, I don't mind _not_ using skeleton, but I had an impression the
>>> general policy was to use it?
>>
>> Either way is fine. I don't really think it buys you much.
>
> Ok, /include/ "skeleton.dtsi" is gone then :-)
The problem wasn't with including skeleton.dtsi. With
CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
DTB using information from the ATAGs (see atags_to_fdt()).
If there's an ATAG giving the amount of RAM the DTB's "memory" node is
replaced with a new one. Since the vexpress DTBs don't have a "memory"
node it's added and the DTB ends up with two nodes describing memory.
I don't expect any real production vexpress system to use this config
options -- we're using it now when running as a guest under Xen because
Xen doesn't (yet) support device tree and we're using ATAGs to tell the
guest how much RAM it's been allocated.
David
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 17:00 ` David Vrabel
0 siblings, 0 replies; 76+ messages in thread
From: David Vrabel @ 2012-01-19 17:00 UTC (permalink / raw)
To: linux-arm-kernel
On 19/01/12 14:51, Pawel Moll wrote:
> On Thu, 2012-01-19 at 14:01 +0000, Rob Herring wrote:
>> On 01/19/2012 07:43 AM, Pawel Moll wrote:
>>> On Thu, 2012-01-19 at 13:34 +0000, Rob Herring wrote:
>>>>> You're right - the skeleton.dtsi contains "memory" mode... Funnily
>>>>> enough originally I was using that name, but then Rob Herring suggested
>>>>> changing it to @80000000, which seemed reasonable.
>>>>>
>>>>> Now I wonder - is the "memory" node special and should not contain
>>>>> "@address", or the skelton shouldn't contain the empty "memory" node...
>>>>>
>>>>
>>>> Hummm... I guess you should just use "memory" if you are using
>>>> skeleton.dtsi.
>>>
>>> Well, I don't mind _not_ using skeleton, but I had an impression the
>>> general policy was to use it?
>>
>> Either way is fine. I don't really think it buys you much.
>
> Ok, /include/ "skeleton.dtsi" is gone then :-)
The problem wasn't with including skeleton.dtsi. With
CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
DTB using information from the ATAGs (see atags_to_fdt()).
If there's an ATAG giving the amount of RAM the DTB's "memory" node is
replaced with a new one. Since the vexpress DTBs don't have a "memory"
node it's added and the DTB ends up with two nodes describing memory.
I don't expect any real production vexpress system to use this config
options -- we're using it now when running as a guest under Xen because
Xen doesn't (yet) support device tree and we're using ATAGs to tell the
guest how much RAM it's been allocated.
David
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 17:00 ` David Vrabel
@ 2012-01-19 17:11 ` Russell King - ARM Linux
-1 siblings, 0 replies; 76+ messages in thread
From: Russell King - ARM Linux @ 2012-01-19 17:11 UTC (permalink / raw)
To: David Vrabel
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Pawel Moll
On Thu, Jan 19, 2012 at 05:00:56PM +0000, David Vrabel wrote:
> I don't expect any real production vexpress system to use this config
> options
I do - _if_ I decide to try DT on my Versatile Express. That'll be
with the existing boot setup, which will be ATAG based.
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 17:11 ` Russell King - ARM Linux
0 siblings, 0 replies; 76+ messages in thread
From: Russell King - ARM Linux @ 2012-01-19 17:11 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jan 19, 2012 at 05:00:56PM +0000, David Vrabel wrote:
> I don't expect any real production vexpress system to use this config
> options
I do - _if_ I decide to try DT on my Versatile Express. That'll be
with the existing boot setup, which will be ATAG based.
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 17:00 ` David Vrabel
@ 2012-01-19 17:27 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 17:27 UTC (permalink / raw)
To: David Vrabel; +Cc: devicetree-discuss, linux-arm-kernel
On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> The problem wasn't with including skeleton.dtsi.
Including as it is creates two device_type="memory" nodes, one with
regs=<0 0>, which is definitely wrong.
> With
> CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> DTB using information from the ATAGs (see atags_to_fdt()).
>
> If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> replaced with a new one. Since the vexpress DTBs don't have a "memory"
> node it's added and the DTB ends up with two nodes describing memory.
The "memory@address" node name is in my opinion perfectly legal - p. 3.4
of the DT spec says "The name component of the node name (see 2.2.1)
shall be memory.". So the decompressor code may be wrong in looking for
adress-less "memory" node...
One way or the other, I'll get this fixed.
Thanks for letting me know!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 17:27 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 17:27 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> The problem wasn't with including skeleton.dtsi.
Including as it is creates two device_type="memory" nodes, one with
regs=<0 0>, which is definitely wrong.
> With
> CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> DTB using information from the ATAGs (see atags_to_fdt()).
>
> If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> replaced with a new one. Since the vexpress DTBs don't have a "memory"
> node it's added and the DTB ends up with two nodes describing memory.
The "memory at address" node name is in my opinion perfectly legal - p. 3.4
of the DT spec says "The name component of the node name (see 2.2.1)
shall be memory.". So the decompressor code may be wrong in looking for
adress-less "memory" node...
One way or the other, I'll get this fixed.
Thanks for letting me know!
Pawe?
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
2012-01-19 16:46 ` David Vrabel
@ 2012-01-19 17:31 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 17:31 UTC (permalink / raw)
To: David Vrabel; +Cc: devicetree-discuss, linux-arm-kernel
On Thu, 2012-01-19 at 16:46 +0000, David Vrabel wrote:
> > It does for me:
> >
> > # zcat /proc/config.gz | grep EARLY_PRINTK
> > CONFIG_EARLY_PRINTK=y
> > # cat /proc/device-tree/motherboard/arm,v2m-memory-map && echo
> > rs1
> > #
>
> earlyprintk needs to be on the kernel command line to enable it.
> Without this option it will work fine.
# cat /proc/cmdline
console=ttyAMA0,38400 earlyprintk rootwait root=/dev/mmcblk0p2 mmci.fmax=12000000 debug
I'll investigate the matter to the bottom, though. Your kernel config
would be helpful, thanks!
> It's also a problem when running as a guest under a hypervisor as there
> won't be any stage 2 translation table entries for non-existent peripherals.
>
> I think there needs to be someway of finding out from the DTB which UART
> to use.
Yess... The DT+earlyprintk problem was discussed several times already,
without any happy resolution so far...
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
@ 2012-01-19 17:31 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-19 17:31 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2012-01-19 at 16:46 +0000, David Vrabel wrote:
> > It does for me:
> >
> > # zcat /proc/config.gz | grep EARLY_PRINTK
> > CONFIG_EARLY_PRINTK=y
> > # cat /proc/device-tree/motherboard/arm,v2m-memory-map && echo
> > rs1
> > #
>
> earlyprintk needs to be on the kernel command line to enable it.
> Without this option it will work fine.
# cat /proc/cmdline
console=ttyAMA0,38400 earlyprintk rootwait root=/dev/mmcblk0p2 mmci.fmax=12000000 debug
I'll investigate the matter to the bottom, though. Your kernel config
would be helpful, thanks!
> It's also a problem when running as a guest under a hypervisor as there
> won't be any stage 2 translation table entries for non-existent peripherals.
>
> I think there needs to be someway of finding out from the DTB which UART
> to use.
Yess... The DT+earlyprintk problem was discussed several times already,
without any happy resolution so far...
Pawe?
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 17:27 ` Pawel Moll
@ 2012-01-19 17:50 ` Russell King - ARM Linux
-1 siblings, 0 replies; 76+ messages in thread
From: Russell King - ARM Linux @ 2012-01-19 17:50 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, David Vrabel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Thu, Jan 19, 2012 at 05:27:15PM +0000, Pawel Moll wrote:
> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > The problem wasn't with including skeleton.dtsi.
>
> Including as it is creates two device_type="memory" nodes, one with
> regs=<0 0>, which is definitely wrong.
>
> > With
> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> > DTB using information from the ATAGs (see atags_to_fdt()).
> >
> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> > replaced with a new one. Since the vexpress DTBs don't have a "memory"
> > node it's added and the DTB ends up with two nodes describing memory.
>
> The "memory@address" node name is in my opinion perfectly legal - p. 3.4
> of the DT spec says "The name component of the node name (see 2.2.1)
> shall be memory.". So the decompressor code may be wrong in looking for
> adress-less "memory" node...
I don't think you can expect such early code to properly parse a DT tree
with a variability in how memory stuff is declared into that DT tree.
What if you have two memory nodes specified in the DT file, and the
ATAG data contains one?
The more I look at this, the more I'm convinced that Grant's idea that
DT should entirely override ATAGs all the way to the kernel proper was
the wrong solution - at least in the kernel, if we had both available,
we could make a choice there, and have the full DT library to be able
to manipulate the DT blob.
Unfortunately, that's not so, so we're just going to have to accept
that on ARM it should be "memory" if we want the ATAG code to override
it. Expecting the decompressor to figure out that it needs to delete
DT nodes and all that I think is asking far too much.
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 17:50 ` Russell King - ARM Linux
0 siblings, 0 replies; 76+ messages in thread
From: Russell King - ARM Linux @ 2012-01-19 17:50 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jan 19, 2012 at 05:27:15PM +0000, Pawel Moll wrote:
> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > The problem wasn't with including skeleton.dtsi.
>
> Including as it is creates two device_type="memory" nodes, one with
> regs=<0 0>, which is definitely wrong.
>
> > With
> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> > DTB using information from the ATAGs (see atags_to_fdt()).
> >
> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> > replaced with a new one. Since the vexpress DTBs don't have a "memory"
> > node it's added and the DTB ends up with two nodes describing memory.
>
> The "memory at address" node name is in my opinion perfectly legal - p. 3.4
> of the DT spec says "The name component of the node name (see 2.2.1)
> shall be memory.". So the decompressor code may be wrong in looking for
> adress-less "memory" node...
I don't think you can expect such early code to properly parse a DT tree
with a variability in how memory stuff is declared into that DT tree.
What if you have two memory nodes specified in the DT file, and the
ATAG data contains one?
The more I look at this, the more I'm convinced that Grant's idea that
DT should entirely override ATAGs all the way to the kernel proper was
the wrong solution - at least in the kernel, if we had both available,
we could make a choice there, and have the full DT library to be able
to manipulate the DT blob.
Unfortunately, that's not so, so we're just going to have to accept
that on ARM it should be "memory" if we want the ATAG code to override
it. Expecting the decompressor to figure out that it needs to delete
DT nodes and all that I think is asking far too much.
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 17:50 ` Russell King - ARM Linux
@ 2012-01-19 17:59 ` Grant Likely
-1 siblings, 0 replies; 76+ messages in thread
From: Grant Likely @ 2012-01-19 17:59 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, David Vrabel,
Pawel Moll
On Thu, Jan 19, 2012 at 10:50 AM, Russell King - ARM Linux
<linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
> On Thu, Jan 19, 2012 at 05:27:15PM +0000, Pawel Moll wrote:
>> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
>> > The problem wasn't with including skeleton.dtsi.
>>
>> Including as it is creates two device_type="memory" nodes, one with
>> regs=<0 0>, which is definitely wrong.
>>
>> > With
>> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
>> > DTB using information from the ATAGs (see atags_to_fdt()).
>> >
>> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
>> > replaced with a new one. Since the vexpress DTBs don't have a "memory"
>> > node it's added and the DTB ends up with two nodes describing memory.
>>
>> The "memory@address" node name is in my opinion perfectly legal - p. 3.4
>> of the DT spec says "The name component of the node name (see 2.2.1)
>> shall be memory.". So the decompressor code may be wrong in looking for
>> adress-less "memory" node...
>
> I don't think you can expect such early code to properly parse a DT tree
> with a variability in how memory stuff is declared into that DT tree.
>
> What if you have two memory nodes specified in the DT file, and the
> ATAG data contains one?
Yes, just because it is technically legal doesn't make it okay. The
pragmatic approach here is that the skeleton.dtsi file calls the node
"memory", so this .dts file must do the same.
> The more I look at this, the more I'm convinced that Grant's idea that
> DT should entirely override ATAGs all the way to the kernel proper was
> the wrong solution - at least in the kernel, if we had both available,
> we could make a choice there, and have the full DT library to be able
> to manipulate the DT blob.
Hey! I was originally lobbying for the dt pointer carried by an ATAG.
Nico conviced me otherwise. :-)
> Unfortunately, that's not so, so we're just going to have to accept
> that on ARM it should be "memory" if we want the ATAG code to override
> it. Expecting the decompressor to figure out that it needs to delete
> DT nodes and all that I think is asking far too much.
+1
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 17:59 ` Grant Likely
0 siblings, 0 replies; 76+ messages in thread
From: Grant Likely @ 2012-01-19 17:59 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jan 19, 2012 at 10:50 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Thu, Jan 19, 2012 at 05:27:15PM +0000, Pawel Moll wrote:
>> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
>> > The problem wasn't with including skeleton.dtsi.
>>
>> Including as it is creates two device_type="memory" nodes, one with
>> regs=<0 0>, which is definitely wrong.
>>
>> > With
>> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
>> > DTB using information from the ATAGs (see atags_to_fdt()).
>> >
>> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
>> > replaced with a new one. ?Since the vexpress DTBs don't have a "memory"
>> > node it's added and the DTB ends up with two nodes describing memory.
>>
>> The "memory at address" node name is in my opinion perfectly legal - p. 3.4
>> of the DT spec says "The name component of the node name (see 2.2.1)
>> shall be memory.". So the decompressor code may be wrong in looking for
>> adress-less "memory" node...
>
> I don't think you can expect such early code to properly parse a DT tree
> with a variability in how memory stuff is declared into that DT tree.
>
> What if you have two memory nodes specified in the DT file, and the
> ATAG data contains one?
Yes, just because it is technically legal doesn't make it okay. The
pragmatic approach here is that the skeleton.dtsi file calls the node
"memory", so this .dts file must do the same.
> The more I look at this, the more I'm convinced that Grant's idea that
> DT should entirely override ATAGs all the way to the kernel proper was
> the wrong solution - at least in the kernel, if we had both available,
> we could make a choice there, and have the full DT library to be able
> to manipulate the DT blob.
Hey! I was originally lobbying for the dt pointer carried by an ATAG.
Nico conviced me otherwise. :-)
> Unfortunately, that's not so, so we're just going to have to accept
> that on ARM it should be "memory" if we want the ATAG code to override
> it. ?Expecting the decompressor to figure out that it needs to delete
> DT nodes and all that I think is asking far too much.
+1
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 17:59 ` Grant Likely
@ 2012-01-19 18:09 ` Nicolas Pitre
-1 siblings, 0 replies; 76+ messages in thread
From: Nicolas Pitre @ 2012-01-19 18:09 UTC (permalink / raw)
To: Grant Likely
Cc: Pawel Moll, devicetree-discuss, Russell King - ARM Linux,
David Vrabel, linux-arm-kernel
[-- Attachment #1: Type: TEXT/PLAIN, Size: 2274 bytes --]
On Thu, 19 Jan 2012, Grant Likely wrote:
> On Thu, Jan 19, 2012 at 10:50 AM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > On Thu, Jan 19, 2012 at 05:27:15PM +0000, Pawel Moll wrote:
> >> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> >> > The problem wasn't with including skeleton.dtsi.
> >>
> >> Including as it is creates two device_type="memory" nodes, one with
> >> regs=<0 0>, which is definitely wrong.
> >>
> >> > With
> >> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> >> > DTB using information from the ATAGs (see atags_to_fdt()).
> >> >
> >> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> >> > replaced with a new one. Since the vexpress DTBs don't have a "memory"
> >> > node it's added and the DTB ends up with two nodes describing memory.
> >>
> >> The "memory@address" node name is in my opinion perfectly legal - p. 3.4
> >> of the DT spec says "The name component of the node name (see 2.2.1)
> >> shall be memory.". So the decompressor code may be wrong in looking for
> >> adress-less "memory" node...
> >
> > I don't think you can expect such early code to properly parse a DT tree
> > with a variability in how memory stuff is declared into that DT tree.
> >
> > What if you have two memory nodes specified in the DT file, and the
> > ATAG data contains one?
>
> Yes, just because it is technically legal doesn't make it okay. The
> pragmatic approach here is that the skeleton.dtsi file calls the node
> "memory", so this .dts file must do the same.
>
> > The more I look at this, the more I'm convinced that Grant's idea that
> > DT should entirely override ATAGs all the way to the kernel proper was
> > the wrong solution - at least in the kernel, if we had both available,
> > we could make a choice there, and have the full DT library to be able
> > to manipulate the DT blob.
>
> Hey! I was originally lobbying for the dt pointer carried by an ATAG.
> Nico conviced me otherwise. :-)
Hey! I was originally lobbying for people to have a fully DT aware
bootloader if they wanted to play with DT, otherwise there is no
incentive for updated bootloaders. But someone else convinced me
otherwise. :-)
Mixed bags always have loose ends.
Nicolas
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 18:09 ` Nicolas Pitre
0 siblings, 0 replies; 76+ messages in thread
From: Nicolas Pitre @ 2012-01-19 18:09 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 19 Jan 2012, Grant Likely wrote:
> On Thu, Jan 19, 2012 at 10:50 AM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > On Thu, Jan 19, 2012 at 05:27:15PM +0000, Pawel Moll wrote:
> >> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> >> > The problem wasn't with including skeleton.dtsi.
> >>
> >> Including as it is creates two device_type="memory" nodes, one with
> >> regs=<0 0>, which is definitely wrong.
> >>
> >> > With
> >> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> >> > DTB using information from the ATAGs (see atags_to_fdt()).
> >> >
> >> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> >> > replaced with a new one. ?Since the vexpress DTBs don't have a "memory"
> >> > node it's added and the DTB ends up with two nodes describing memory.
> >>
> >> The "memory at address" node name is in my opinion perfectly legal - p. 3.4
> >> of the DT spec says "The name component of the node name (see 2.2.1)
> >> shall be memory.". So the decompressor code may be wrong in looking for
> >> adress-less "memory" node...
> >
> > I don't think you can expect such early code to properly parse a DT tree
> > with a variability in how memory stuff is declared into that DT tree.
> >
> > What if you have two memory nodes specified in the DT file, and the
> > ATAG data contains one?
>
> Yes, just because it is technically legal doesn't make it okay. The
> pragmatic approach here is that the skeleton.dtsi file calls the node
> "memory", so this .dts file must do the same.
>
> > The more I look at this, the more I'm convinced that Grant's idea that
> > DT should entirely override ATAGs all the way to the kernel proper was
> > the wrong solution - at least in the kernel, if we had both available,
> > we could make a choice there, and have the full DT library to be able
> > to manipulate the DT blob.
>
> Hey! I was originally lobbying for the dt pointer carried by an ATAG.
> Nico conviced me otherwise. :-)
Hey! I was originally lobbying for people to have a fully DT aware
bootloader if they wanted to play with DT, otherwise there is no
incentive for updated bootloaders. But someone else convinced me
otherwise. :-)
Mixed bags always have loose ends.
Nicolas
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 18:09 ` Nicolas Pitre
@ 2012-01-19 22:07 ` Grant Likely
-1 siblings, 0 replies; 76+ messages in thread
From: Grant Likely @ 2012-01-19 22:07 UTC (permalink / raw)
To: Nicolas Pitre
Cc: Pawel Moll, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
Russell King - ARM Linux, David Vrabel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Thu, Jan 19, 2012 at 11:09 AM, Nicolas Pitre <nico-vtqb6HGKxmzR7s880joybQ@public.gmane.org> wrote:
> On Thu, 19 Jan 2012, Grant Likely wrote:
>
>> On Thu, Jan 19, 2012 at 10:50 AM, Russell King - ARM Linux
>> <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
>> > On Thu, Jan 19, 2012 at 05:27:15PM +0000, Pawel Moll wrote:
>> >> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
>> >> > The problem wasn't with including skeleton.dtsi.
>> >>
>> >> Including as it is creates two device_type="memory" nodes, one with
>> >> regs=<0 0>, which is definitely wrong.
>> >>
>> >> > With
>> >> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
>> >> > DTB using information from the ATAGs (see atags_to_fdt()).
>> >> >
>> >> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
>> >> > replaced with a new one. Since the vexpress DTBs don't have a "memory"
>> >> > node it's added and the DTB ends up with two nodes describing memory.
>> >>
>> >> The "memory@address" node name is in my opinion perfectly legal - p. 3.4
>> >> of the DT spec says "The name component of the node name (see 2.2.1)
>> >> shall be memory.". So the decompressor code may be wrong in looking for
>> >> adress-less "memory" node...
>> >
>> > I don't think you can expect such early code to properly parse a DT tree
>> > with a variability in how memory stuff is declared into that DT tree.
>> >
>> > What if you have two memory nodes specified in the DT file, and the
>> > ATAG data contains one?
>>
>> Yes, just because it is technically legal doesn't make it okay. The
>> pragmatic approach here is that the skeleton.dtsi file calls the node
>> "memory", so this .dts file must do the same.
>>
>> > The more I look at this, the more I'm convinced that Grant's idea that
>> > DT should entirely override ATAGs all the way to the kernel proper was
>> > the wrong solution - at least in the kernel, if we had both available,
>> > we could make a choice there, and have the full DT library to be able
>> > to manipulate the DT blob.
>>
>> Hey! I was originally lobbying for the dt pointer carried by an ATAG.
>> Nico conviced me otherwise. :-)
>
> Hey! I was originally lobbying for people to have a fully DT aware
> bootloader if they wanted to play with DT, otherwise there is no
> incentive for updated bootloaders. But someone else convinced me
> otherwise. :-)
>
> Mixed bags always have loose ends.
Hahaha. Having said that though, I still strongly agree with what we
have. Giving the kernel only one or the other avoids any weirdness
about which the kernel should choose when both are present. The
bootwrapper atag-to-dt conversion is a migration and development tool,
and it should not do any DT manipulation must be kept to a bare
minimum.
g.
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-19 22:07 ` Grant Likely
0 siblings, 0 replies; 76+ messages in thread
From: Grant Likely @ 2012-01-19 22:07 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jan 19, 2012 at 11:09 AM, Nicolas Pitre <nico@fluxnic.net> wrote:
> On Thu, 19 Jan 2012, Grant Likely wrote:
>
>> On Thu, Jan 19, 2012 at 10:50 AM, Russell King - ARM Linux
>> <linux@arm.linux.org.uk> wrote:
>> > On Thu, Jan 19, 2012 at 05:27:15PM +0000, Pawel Moll wrote:
>> >> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
>> >> > The problem wasn't with including skeleton.dtsi.
>> >>
>> >> Including as it is creates two device_type="memory" nodes, one with
>> >> regs=<0 0>, which is definitely wrong.
>> >>
>> >> > With
>> >> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
>> >> > DTB using information from the ATAGs (see atags_to_fdt()).
>> >> >
>> >> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
>> >> > replaced with a new one. ?Since the vexpress DTBs don't have a "memory"
>> >> > node it's added and the DTB ends up with two nodes describing memory.
>> >>
>> >> The "memory at address" node name is in my opinion perfectly legal - p. 3.4
>> >> of the DT spec says "The name component of the node name (see 2.2.1)
>> >> shall be memory.". So the decompressor code may be wrong in looking for
>> >> adress-less "memory" node...
>> >
>> > I don't think you can expect such early code to properly parse a DT tree
>> > with a variability in how memory stuff is declared into that DT tree.
>> >
>> > What if you have two memory nodes specified in the DT file, and the
>> > ATAG data contains one?
>>
>> Yes, just because it is technically legal doesn't make it okay. ?The
>> pragmatic approach here is that the skeleton.dtsi file calls the node
>> "memory", so this .dts file must do the same.
>>
>> > The more I look at this, the more I'm convinced that Grant's idea that
>> > DT should entirely override ATAGs all the way to the kernel proper was
>> > the wrong solution - at least in the kernel, if we had both available,
>> > we could make a choice there, and have the full DT library to be able
>> > to manipulate the DT blob.
>>
>> Hey! ?I was originally lobbying for the dt pointer carried by an ATAG.
>> ?Nico conviced me otherwise. ?:-)
>
> Hey! ?I was originally lobbying for people to have a fully DT aware
> bootloader if they wanted to play with DT, otherwise there is no
> incentive for updated bootloaders. ?But someone else convinced me
> otherwise. ?:-)
>
> Mixed bags always have loose ends.
Hahaha. Having said that though, I still strongly agree with what we
have. Giving the kernel only one or the other avoids any weirdness
about which the kernel should choose when both are present. The
bootwrapper atag-to-dt conversion is a migration and development tool,
and it should not do any DT manipulation must be kept to a bare
minimum.
g.
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-19 17:00 ` David Vrabel
@ 2012-01-25 17:43 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-25 17:43 UTC (permalink / raw)
To: David Vrabel; +Cc: Grant Likely, devicetree-discuss, linux-arm-kernel
On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > Ok, /include/ "skeleton.dtsi" is gone then :-)
>
> The problem wasn't with including skeleton.dtsi. With
> CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> DTB using information from the ATAGs (see atags_to_fdt()).
>
> If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> replaced with a new one. Since the vexpress DTBs don't have a "memory"
> node it's added and the DTB ends up with two nodes describing memory.
As it turned out it was just the "skeleton.dtsi" problem after all - I
mean the fact that there where two device_type="memory" nodes in the
tree.
The decompressor's setprop()
(arch/arm/boot/compressed/atags_to_fdt.c:12) uses libfdt's
fdt_setprop(), which correctly ignores the "@00000000" component of the
node name and sets the reg property as expected. So as long as there is
exactly one "memory[@address]" node in the tree,
CONFIG_ARM_ATAG_DTB_COMPAT is happy.
I will remove the /include/ from the dts files for VE (see below) in the
v3.3-rc1 based series.
Thanks for spotting this!
Paweł
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 02cada5..2a690f2 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -9,13 +9,15 @@
/dts-v1/;
-/include/ "skeleton.dtsi"
-
/ {
model = "V2P-CA15";
arm,hbi = <0x237>;
compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen { };
aliases {
serial0 = &v2m_serial0;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index da26a13..d4c5322 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -9,13 +9,15 @@
/dts-v1/;
-/include/ "skeleton.dtsi"
-
/ {
model = "V2P-CA5s";
arm,hbi = <0x225>;
compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen { };
aliases {
serial0 = &v2m_serial0;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 84542e7..5d90ce5 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -9,13 +9,15 @@
/dts-v1/;
-/include/ "skeleton.dtsi"
-
/ {
model = "V2P-CA9";
arm,hbi = <0x191>;
compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen { };
aliases {
serial0 = &v2m_serial0;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-25 17:43 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-25 17:43 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > Ok, /include/ "skeleton.dtsi" is gone then :-)
>
> The problem wasn't with including skeleton.dtsi. With
> CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> DTB using information from the ATAGs (see atags_to_fdt()).
>
> If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> replaced with a new one. Since the vexpress DTBs don't have a "memory"
> node it's added and the DTB ends up with two nodes describing memory.
As it turned out it was just the "skeleton.dtsi" problem after all - I
mean the fact that there where two device_type="memory" nodes in the
tree.
The decompressor's setprop()
(arch/arm/boot/compressed/atags_to_fdt.c:12) uses libfdt's
fdt_setprop(), which correctly ignores the "@00000000" component of the
node name and sets the reg property as expected. So as long as there is
exactly one "memory[@address]" node in the tree,
CONFIG_ARM_ATAG_DTB_COMPAT is happy.
I will remove the /include/ from the dts files for VE (see below) in the
v3.3-rc1 based series.
Thanks for spotting this!
Pawe?
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 02cada5..2a690f2 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -9,13 +9,15 @@
/dts-v1/;
-/include/ "skeleton.dtsi"
-
/ {
model = "V2P-CA15";
arm,hbi = <0x237>;
compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen { };
aliases {
serial0 = &v2m_serial0;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index da26a13..d4c5322 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -9,13 +9,15 @@
/dts-v1/;
-/include/ "skeleton.dtsi"
-
/ {
model = "V2P-CA5s";
arm,hbi = <0x225>;
compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen { };
aliases {
serial0 = &v2m_serial0;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 84542e7..5d90ce5 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -9,13 +9,15 @@
/dts-v1/;
-/include/ "skeleton.dtsi"
-
/ {
model = "V2P-CA9";
arm,hbi = <0x191>;
compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen { };
aliases {
serial0 = &v2m_serial0;
^ permalink raw reply related [flat|nested] 76+ messages in thread
* Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
2012-01-19 16:46 ` David Vrabel
@ 2012-01-27 14:02 ` Pawel Moll
-1 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-27 14:02 UTC (permalink / raw)
To: David Vrabel; +Cc: devicetree-discuss, linux-arm-kernel
On Thu, 2012-01-19 at 16:46 +0000, David Vrabel wrote:
> >> __create_page_tables has only mapped the single physical
> >> page at 0x1c090000 and thus the test for the UART in the other memory
> >> map faults.
I got to the bottom of the problem... The mapping created by the
DEBUG_LL code in __create_page_tables is actually a section (1MB) so
covers both possible accesses (0xf8009000 and 0xf8090000). The
difference between model and hardware is that "real" RS1 VE has a DAP
ROM located between 0xf8000000 and 0xf800ffff so the 0xf8009000 succeeds
(returning some irrelevant data), while model is "empty" in that space,
so it faults.
Anyway, I have an idea how to solve (or rather work around) the problem
and will get if working on models in the next version of the series.
I'll send you a modified version of the relevant patch before that so
you can test it.
Thanks for your time!
Paweł
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
@ 2012-01-27 14:02 ` Pawel Moll
0 siblings, 0 replies; 76+ messages in thread
From: Pawel Moll @ 2012-01-27 14:02 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2012-01-19 at 16:46 +0000, David Vrabel wrote:
> >> __create_page_tables has only mapped the single physical
> >> page at 0x1c090000 and thus the test for the UART in the other memory
> >> map faults.
I got to the bottom of the problem... The mapping created by the
DEBUG_LL code in __create_page_tables is actually a section (1MB) so
covers both possible accesses (0xf8009000 and 0xf8090000). The
difference between model and hardware is that "real" RS1 VE has a DAP
ROM located between 0xf8000000 and 0xf800ffff so the 0xf8009000 succeeds
(returning some irrelevant data), while model is "empty" in that space,
so it faults.
Anyway, I have an idea how to solve (or rather work around) the problem
and will get if working on models in the next version of the series.
I'll send you a modified version of the relevant patch before that so
you can test it.
Thanks for your time!
Pawe?
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
2012-01-19 13:21 ` Pawel Moll
@ 2012-01-30 17:26 ` Dave Martin
-1 siblings, 0 replies; 76+ messages in thread
From: Dave Martin @ 2012-01-30 17:26 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, David Vrabel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Thu, Jan 19, 2012 at 01:21:06PM +0000, Pawel Moll wrote:
> Hi,
>
> Sorry about loooong delay - I've been on holiday.
>
> On Wed, 2012-01-04 at 16:35 +0000, David Vrabel wrote:
> > On 15/12/11 14:02, Pawel Moll wrote:
> > > This patch adds support for RS1 memory map based Versatile Express
> > > motherboard.
> > >
> > [...]
> > > --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
> > > +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
> > > @@ -10,12 +10,41 @@
> > > * published by the Free Software Foundation.
> > > */
> > >
> > > -#define DEBUG_LL_UART_OFFSET 0x00009000
> > > +#define DEBUG_LL_PHYS_BASE 0x10000000
> > > +#define DEBUG_LL_UART_OFFSET 0x00009000
> > > +
> > > +#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
> > > +#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
> > > +
> > > +#define DEBUG_LL_VIRT_BASE 0xf8000000
> > >
> > > .macro addruart,rp,rv,tmp
> > > - mov \rp, #DEBUG_LL_UART_OFFSET
> > > - orr \rv, \rp, #0xf8000000 @ virtual base
> > > - orr \rp, \rp, #0x10000000 @ physical base
> > > +
> > > + @ Check the MMU state
> > > +#if defined(CONFIG_MMU)
> > > + mrc p15, 0, \tmp, c1, c0 @ SCTRL
> > > + tst \tmp, #1 @ MMU enabled?
> > > + moveq \tmp, #DEBUG_LL_PHYS_BASE
> > > + movne \tmp, #DEBUG_LL_VIRT_BASE
> > > +#else
> > > + mov \tmp, #DEBUG_LL_PHYS_BASE
> > > +#endif
> > > +
> > > + @ PL011 present in "original" place?
> > > + orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
> > > + ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
> >
> > This doesn't work with CONFIG_EARLY_PRINTK=y on a system with the RS1
> > memory map.
>
> It does for me:
>
> # zcat /proc/config.gz | grep EARLY_PRINTK
> CONFIG_EARLY_PRINTK=y
> # cat /proc/device-tree/motherboard/arm,v2m-memory-map && echo
> rs1
> #
>
> Can you tell me what exactly is going wrong in your case? Does it hang
> without any warning? Do you get at least part of the boot log? Can you
> send me (privately probably) your kernel config?
I had to disable this when running on the ARM fast model with your vexpress
DT series. I didn't debug into exactly why I had to disable it, but I
think I was getting aborts when the kernel was probing for nonexistent
legacy memory map location of the UART. I don't know whether this will
affect real hardware though... and maybe I was hitting the problem due
to something else.
Anyway unless I've misunderstood something, AMBA devices are only really
probable if there is some real bus slave at the probed address, which is
free from nasty side-effects.
Really we should have a way for getting this info from the device tree,
yada yada. (Repeating myself here, I know)
In the meantime, I don't see a practical alternative to adding distinct
lowlevel debug UART selection options for the two memory maps ...?
Cheers
---Dave
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
@ 2012-01-30 17:26 ` Dave Martin
0 siblings, 0 replies; 76+ messages in thread
From: Dave Martin @ 2012-01-30 17:26 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jan 19, 2012 at 01:21:06PM +0000, Pawel Moll wrote:
> Hi,
>
> Sorry about loooong delay - I've been on holiday.
>
> On Wed, 2012-01-04 at 16:35 +0000, David Vrabel wrote:
> > On 15/12/11 14:02, Pawel Moll wrote:
> > > This patch adds support for RS1 memory map based Versatile Express
> > > motherboard.
> > >
> > [...]
> > > --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
> > > +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
> > > @@ -10,12 +10,41 @@
> > > * published by the Free Software Foundation.
> > > */
> > >
> > > -#define DEBUG_LL_UART_OFFSET 0x00009000
> > > +#define DEBUG_LL_PHYS_BASE 0x10000000
> > > +#define DEBUG_LL_UART_OFFSET 0x00009000
> > > +
> > > +#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
> > > +#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
> > > +
> > > +#define DEBUG_LL_VIRT_BASE 0xf8000000
> > >
> > > .macro addruart,rp,rv,tmp
> > > - mov \rp, #DEBUG_LL_UART_OFFSET
> > > - orr \rv, \rp, #0xf8000000 @ virtual base
> > > - orr \rp, \rp, #0x10000000 @ physical base
> > > +
> > > + @ Check the MMU state
> > > +#if defined(CONFIG_MMU)
> > > + mrc p15, 0, \tmp, c1, c0 @ SCTRL
> > > + tst \tmp, #1 @ MMU enabled?
> > > + moveq \tmp, #DEBUG_LL_PHYS_BASE
> > > + movne \tmp, #DEBUG_LL_VIRT_BASE
> > > +#else
> > > + mov \tmp, #DEBUG_LL_PHYS_BASE
> > > +#endif
> > > +
> > > + @ PL011 present in "original" place?
> > > + orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET
> > > + ldr \tmp, [\tmp, #0xfe0] @ PeriphID0
> >
> > This doesn't work with CONFIG_EARLY_PRINTK=y on a system with the RS1
> > memory map.
>
> It does for me:
>
> # zcat /proc/config.gz | grep EARLY_PRINTK
> CONFIG_EARLY_PRINTK=y
> # cat /proc/device-tree/motherboard/arm,v2m-memory-map && echo
> rs1
> #
>
> Can you tell me what exactly is going wrong in your case? Does it hang
> without any warning? Do you get at least part of the boot log? Can you
> send me (privately probably) your kernel config?
I had to disable this when running on the ARM fast model with your vexpress
DT series. I didn't debug into exactly why I had to disable it, but I
think I was getting aborts when the kernel was probing for nonexistent
legacy memory map location of the UART. I don't know whether this will
affect real hardware though... and maybe I was hitting the problem due
to something else.
Anyway unless I've misunderstood something, AMBA devices are only really
probable if there is some real bus slave at the probed address, which is
free from nasty side-effects.
Really we should have a way for getting this info from the device tree,
yada yada. (Repeating myself here, I know)
In the meantime, I don't see a practical alternative to adding distinct
lowlevel debug UART selection options for the two memory maps ...?
Cheers
---Dave
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
2012-01-27 14:02 ` Pawel Moll
@ 2012-01-30 17:32 ` Dave Martin
-1 siblings, 0 replies; 76+ messages in thread
From: Dave Martin @ 2012-01-30 17:32 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, David Vrabel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Fri, Jan 27, 2012 at 02:02:40PM +0000, Pawel Moll wrote:
> On Thu, 2012-01-19 at 16:46 +0000, David Vrabel wrote:
> > >> __create_page_tables has only mapped the single physical
> > >> page at 0x1c090000 and thus the test for the UART in the other memory
> > >> map faults.
>
> I got to the bottom of the problem... The mapping created by the
> DEBUG_LL code in __create_page_tables is actually a section (1MB) so
> covers both possible accesses (0xf8009000 and 0xf8090000). The
> difference between model and hardware is that "real" RS1 VE has a DAP
> ROM located between 0xf8000000 and 0xf800ffff so the 0xf8009000 succeeds
> (returning some irrelevant data), while model is "empty" in that space,
> so it faults.
>
> Anyway, I have an idea how to solve (or rather work around) the problem
> and will get if working on models in the next version of the series.
> I'll send you a modified version of the relevant patch before that so
> you can test it.
>
> Thanks for your time!
I would be interested in that too.
However, I would still prefer the explicit debug UART selection route,
since we already have to do that for many boards and I'm not sure how
much I trust the memory maps of future tiles and models to "evolve"
relative to what currently exists. Are you sure it won't change again?
If we rely on lucky arrangement of slaves on the bus in order to have
a workaround, sooner or later our luck is liable to run out.
Cheers
---Dave
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
@ 2012-01-30 17:32 ` Dave Martin
0 siblings, 0 replies; 76+ messages in thread
From: Dave Martin @ 2012-01-30 17:32 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 27, 2012 at 02:02:40PM +0000, Pawel Moll wrote:
> On Thu, 2012-01-19 at 16:46 +0000, David Vrabel wrote:
> > >> __create_page_tables has only mapped the single physical
> > >> page at 0x1c090000 and thus the test for the UART in the other memory
> > >> map faults.
>
> I got to the bottom of the problem... The mapping created by the
> DEBUG_LL code in __create_page_tables is actually a section (1MB) so
> covers both possible accesses (0xf8009000 and 0xf8090000). The
> difference between model and hardware is that "real" RS1 VE has a DAP
> ROM located between 0xf8000000 and 0xf800ffff so the 0xf8009000 succeeds
> (returning some irrelevant data), while model is "empty" in that space,
> so it faults.
>
> Anyway, I have an idea how to solve (or rather work around) the problem
> and will get if working on models in the next version of the series.
> I'll send you a modified version of the relevant patch before that so
> you can test it.
>
> Thanks for your time!
I would be interested in that too.
However, I would still prefer the explicit debug UART selection route,
since we already have to do that for many boards and I'm not sure how
much I trust the memory maps of future tiles and models to "evolve"
relative to what currently exists. Are you sure it won't change again?
If we rely on lucky arrangement of slaves on the bus in order to have
a workaround, sooner or later our luck is liable to run out.
Cheers
---Dave
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-25 17:43 ` Pawel Moll
@ 2012-01-30 17:42 ` Dave Martin
-1 siblings, 0 replies; 76+ messages in thread
From: Dave Martin @ 2012-01-30 17:42 UTC (permalink / raw)
To: Pawel Moll
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, David Vrabel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wed, Jan 25, 2012 at 05:43:16PM +0000, Pawel Moll wrote:
> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > > Ok, /include/ "skeleton.dtsi" is gone then :-)
> >
> > The problem wasn't with including skeleton.dtsi. With
> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> > DTB using information from the ATAGs (see atags_to_fdt()).
> >
> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> > replaced with a new one. Since the vexpress DTBs don't have a "memory"
> > node it's added and the DTB ends up with two nodes describing memory.
>
> As it turned out it was just the "skeleton.dtsi" problem after all - I
> mean the fact that there where two device_type="memory" nodes in the
> tree.
>
> The decompressor's setprop()
> (arch/arm/boot/compressed/atags_to_fdt.c:12) uses libfdt's
> fdt_setprop(), which correctly ignores the "@00000000" component of the
> node name and sets the reg property as expected. So as long as there is
> exactly one "memory[@address]" node in the tree,
> CONFIG_ARM_ATAG_DTB_COMPAT is happy.
>
> I will remove the /include/ from the dts files for VE (see below) in the
> v3.3-rc1 based series.
>
> Thanks for spotting this!
>
> Pawe??
This carries a significant risk of unintended fragmentation and buggy
maintenance. This patch is a good example of the kind of change which
could easily go wrong. (I'm not saying that it is wrong -- just using
it as an example.)
Since we will end up with a significantly large number of device trees
for vexpress, I can foresee that we'll end up with a highly reduncant
set of .dts{,i} files (each of which is often rather internally redundant
too).
Does anyone have a view on whether it's acceptable to generate device
tree sources from another form, instead of having them verbatim in the
kernel tree? This could involve a preprocessor, or something more
heavyweight.
The dts /include/ mechanism solves this problem only for the simplest
of cases.
Cheers
---Dave
>
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
> index 02cada5..2a690f2 100644
> --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
> @@ -9,13 +9,15 @@
>
> /dts-v1/;
>
> -/include/ "skeleton.dtsi"
> -
> / {
> model = "V2P-CA15";
> arm,hbi = <0x237>;
> compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
> interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen { };
>
> aliases {
> serial0 = &v2m_serial0;
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> index da26a13..d4c5322 100644
> --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> @@ -9,13 +9,15 @@
>
> /dts-v1/;
>
> -/include/ "skeleton.dtsi"
> -
> / {
> model = "V2P-CA5s";
> arm,hbi = <0x225>;
> compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
> interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen { };
>
> aliases {
> serial0 = &v2m_serial0;
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> index 84542e7..5d90ce5 100644
> --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> @@ -9,13 +9,15 @@
>
> /dts-v1/;
>
> -/include/ "skeleton.dtsi"
> -
> / {
> model = "V2P-CA9";
> arm,hbi = <0x191>;
> compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
> interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen { };
>
> aliases {
> serial0 = &v2m_serial0;
>
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-30 17:42 ` Dave Martin
0 siblings, 0 replies; 76+ messages in thread
From: Dave Martin @ 2012-01-30 17:42 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 25, 2012 at 05:43:16PM +0000, Pawel Moll wrote:
> On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > > Ok, /include/ "skeleton.dtsi" is gone then :-)
> >
> > The problem wasn't with including skeleton.dtsi. With
> > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> > DTB using information from the ATAGs (see atags_to_fdt()).
> >
> > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> > replaced with a new one. Since the vexpress DTBs don't have a "memory"
> > node it's added and the DTB ends up with two nodes describing memory.
>
> As it turned out it was just the "skeleton.dtsi" problem after all - I
> mean the fact that there where two device_type="memory" nodes in the
> tree.
>
> The decompressor's setprop()
> (arch/arm/boot/compressed/atags_to_fdt.c:12) uses libfdt's
> fdt_setprop(), which correctly ignores the "@00000000" component of the
> node name and sets the reg property as expected. So as long as there is
> exactly one "memory[@address]" node in the tree,
> CONFIG_ARM_ATAG_DTB_COMPAT is happy.
>
> I will remove the /include/ from the dts files for VE (see below) in the
> v3.3-rc1 based series.
>
> Thanks for spotting this!
>
> Pawe??
This carries a significant risk of unintended fragmentation and buggy
maintenance. This patch is a good example of the kind of change which
could easily go wrong. (I'm not saying that it is wrong -- just using
it as an example.)
Since we will end up with a significantly large number of device trees
for vexpress, I can foresee that we'll end up with a highly reduncant
set of .dts{,i} files (each of which is often rather internally redundant
too).
Does anyone have a view on whether it's acceptable to generate device
tree sources from another form, instead of having them verbatim in the
kernel tree? This could involve a preprocessor, or something more
heavyweight.
The dts /include/ mechanism solves this problem only for the simplest
of cases.
Cheers
---Dave
>
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
> index 02cada5..2a690f2 100644
> --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
> @@ -9,13 +9,15 @@
>
> /dts-v1/;
>
> -/include/ "skeleton.dtsi"
> -
> / {
> model = "V2P-CA15";
> arm,hbi = <0x237>;
> compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
> interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen { };
>
> aliases {
> serial0 = &v2m_serial0;
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> index da26a13..d4c5322 100644
> --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
> @@ -9,13 +9,15 @@
>
> /dts-v1/;
>
> -/include/ "skeleton.dtsi"
> -
> / {
> model = "V2P-CA5s";
> arm,hbi = <0x225>;
> compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
> interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen { };
>
> aliases {
> serial0 = &v2m_serial0;
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> index 84542e7..5d90ce5 100644
> --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
> @@ -9,13 +9,15 @@
>
> /dts-v1/;
>
> -/include/ "skeleton.dtsi"
> -
> / {
> model = "V2P-CA9";
> arm,hbi = <0x191>;
> compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
> interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen { };
>
> aliases {
> serial0 = &v2m_serial0;
>
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-30 17:42 ` Dave Martin
@ 2012-01-30 21:31 ` Grant Likely
-1 siblings, 0 replies; 76+ messages in thread
From: Grant Likely @ 2012-01-30 21:31 UTC (permalink / raw)
To: Dave Martin
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, David Vrabel,
Pawel Moll
On Mon, Jan 30, 2012 at 05:42:12PM +0000, Dave Martin wrote:
> On Wed, Jan 25, 2012 at 05:43:16PM +0000, Pawel Moll wrote:
> > On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > > > Ok, /include/ "skeleton.dtsi" is gone then :-)
> > >
> > > The problem wasn't with including skeleton.dtsi. With
> > > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> > > DTB using information from the ATAGs (see atags_to_fdt()).
> > >
> > > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> > > replaced with a new one. Since the vexpress DTBs don't have a "memory"
> > > node it's added and the DTB ends up with two nodes describing memory.
> >
> > As it turned out it was just the "skeleton.dtsi" problem after all - I
> > mean the fact that there where two device_type="memory" nodes in the
> > tree.
> >
> > The decompressor's setprop()
> > (arch/arm/boot/compressed/atags_to_fdt.c:12) uses libfdt's
> > fdt_setprop(), which correctly ignores the "@00000000" component of the
> > node name and sets the reg property as expected. So as long as there is
> > exactly one "memory[@address]" node in the tree,
> > CONFIG_ARM_ATAG_DTB_COMPAT is happy.
> >
> > I will remove the /include/ from the dts files for VE (see below) in the
> > v3.3-rc1 based series.
> >
> > Thanks for spotting this!
> >
> > Pawe??
>
> This carries a significant risk of unintended fragmentation and buggy
> maintenance. This patch is a good example of the kind of change which
> could easily go wrong. (I'm not saying that it is wrong -- just using
> it as an example.)
>
> Since we will end up with a significantly large number of device trees
> for vexpress, I can foresee that we'll end up with a highly reduncant
> set of .dts{,i} files (each of which is often rather internally redundant
> too).
>
> Does anyone have a view on whether it's acceptable to generate device
> tree sources from another form, instead of having them verbatim in the
> kernel tree? This could involve a preprocessor, or something more
> heavyweight.
Yes, the xilinx folks have been using a dts generator to create the
device tree that matches an FPGA design. This works on ppc and
microblaze, and they'll do the same thing for their ARM FPGA SoC.
g.
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-30 21:31 ` Grant Likely
0 siblings, 0 replies; 76+ messages in thread
From: Grant Likely @ 2012-01-30 21:31 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 30, 2012 at 05:42:12PM +0000, Dave Martin wrote:
> On Wed, Jan 25, 2012 at 05:43:16PM +0000, Pawel Moll wrote:
> > On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > > > Ok, /include/ "skeleton.dtsi" is gone then :-)
> > >
> > > The problem wasn't with including skeleton.dtsi. With
> > > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> > > DTB using information from the ATAGs (see atags_to_fdt()).
> > >
> > > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> > > replaced with a new one. Since the vexpress DTBs don't have a "memory"
> > > node it's added and the DTB ends up with two nodes describing memory.
> >
> > As it turned out it was just the "skeleton.dtsi" problem after all - I
> > mean the fact that there where two device_type="memory" nodes in the
> > tree.
> >
> > The decompressor's setprop()
> > (arch/arm/boot/compressed/atags_to_fdt.c:12) uses libfdt's
> > fdt_setprop(), which correctly ignores the "@00000000" component of the
> > node name and sets the reg property as expected. So as long as there is
> > exactly one "memory[@address]" node in the tree,
> > CONFIG_ARM_ATAG_DTB_COMPAT is happy.
> >
> > I will remove the /include/ from the dts files for VE (see below) in the
> > v3.3-rc1 based series.
> >
> > Thanks for spotting this!
> >
> > Pawe??
>
> This carries a significant risk of unintended fragmentation and buggy
> maintenance. This patch is a good example of the kind of change which
> could easily go wrong. (I'm not saying that it is wrong -- just using
> it as an example.)
>
> Since we will end up with a significantly large number of device trees
> for vexpress, I can foresee that we'll end up with a highly reduncant
> set of .dts{,i} files (each of which is often rather internally redundant
> too).
>
> Does anyone have a view on whether it's acceptable to generate device
> tree sources from another form, instead of having them verbatim in the
> kernel tree? This could involve a preprocessor, or something more
> heavyweight.
Yes, the xilinx folks have been using a dts generator to create the
device tree that matches an FPGA design. This works on ppc and
microblaze, and they'll do the same thing for their ARM FPGA SoC.
g.
^ permalink raw reply [flat|nested] 76+ messages in thread
* Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
2012-01-30 21:31 ` Grant Likely
@ 2012-01-31 11:50 ` Dave Martin
-1 siblings, 0 replies; 76+ messages in thread
From: Dave Martin @ 2012-01-31 11:50 UTC (permalink / raw)
To: Grant Likely
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, David Vrabel,
Pawel Moll
On Mon, Jan 30, 2012 at 02:31:15PM -0700, Grant Likely wrote:
> On Mon, Jan 30, 2012 at 05:42:12PM +0000, Dave Martin wrote:
> > On Wed, Jan 25, 2012 at 05:43:16PM +0000, Pawel Moll wrote:
> > > On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > > > > Ok, /include/ "skeleton.dtsi" is gone then :-)
> > > >
> > > > The problem wasn't with including skeleton.dtsi. With
> > > > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> > > > DTB using information from the ATAGs (see atags_to_fdt()).
> > > >
> > > > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> > > > replaced with a new one. Since the vexpress DTBs don't have a "memory"
> > > > node it's added and the DTB ends up with two nodes describing memory.
> > >
> > > As it turned out it was just the "skeleton.dtsi" problem after all - I
> > > mean the fact that there where two device_type="memory" nodes in the
> > > tree.
> > >
> > > The decompressor's setprop()
> > > (arch/arm/boot/compressed/atags_to_fdt.c:12) uses libfdt's
> > > fdt_setprop(), which correctly ignores the "@00000000" component of the
> > > node name and sets the reg property as expected. So as long as there is
> > > exactly one "memory[@address]" node in the tree,
> > > CONFIG_ARM_ATAG_DTB_COMPAT is happy.
> > >
> > > I will remove the /include/ from the dts files for VE (see below) in the
> > > v3.3-rc1 based series.
> > >
> > > Thanks for spotting this!
> > >
> > > Pawe??
> >
> > This carries a significant risk of unintended fragmentation and buggy
> > maintenance. This patch is a good example of the kind of change which
> > could easily go wrong. (I'm not saying that it is wrong -- just using
> > it as an example.)
> >
> > Since we will end up with a significantly large number of device trees
> > for vexpress, I can foresee that we'll end up with a highly reduncant
> > set of .dts{,i} files (each of which is often rather internally redundant
> > too).
> >
> > Does anyone have a view on whether it's acceptable to generate device
> > tree sources from another form, instead of having them verbatim in the
> > kernel tree? This could involve a preprocessor, or something more
> > heavyweight.
>
> Yes, the xilinx folks have been using a dts generator to create the
> device tree that matches an FPGA design. This works on ppc and
> microblaze, and they'll do the same thing for their ARM FPGA SoC.
OK, well I guess it's good to know we have the option to consider such
techniques for vexpress in the future.
For now, I suggest we paste in the .dts files as-is, since the situation
is not too unmanageable for now, and we don't unnecessary feature creep
to hold up merging of the series.
Cheers
---Dave
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
@ 2012-01-31 11:50 ` Dave Martin
0 siblings, 0 replies; 76+ messages in thread
From: Dave Martin @ 2012-01-31 11:50 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 30, 2012 at 02:31:15PM -0700, Grant Likely wrote:
> On Mon, Jan 30, 2012 at 05:42:12PM +0000, Dave Martin wrote:
> > On Wed, Jan 25, 2012 at 05:43:16PM +0000, Pawel Moll wrote:
> > > On Thu, 2012-01-19 at 17:00 +0000, David Vrabel wrote:
> > > > > Ok, /include/ "skeleton.dtsi" is gone then :-)
> > > >
> > > > The problem wasn't with including skeleton.dtsi. With
> > > > CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
> > > > DTB using information from the ATAGs (see atags_to_fdt()).
> > > >
> > > > If there's an ATAG giving the amount of RAM the DTB's "memory" node is
> > > > replaced with a new one. Since the vexpress DTBs don't have a "memory"
> > > > node it's added and the DTB ends up with two nodes describing memory.
> > >
> > > As it turned out it was just the "skeleton.dtsi" problem after all - I
> > > mean the fact that there where two device_type="memory" nodes in the
> > > tree.
> > >
> > > The decompressor's setprop()
> > > (arch/arm/boot/compressed/atags_to_fdt.c:12) uses libfdt's
> > > fdt_setprop(), which correctly ignores the "@00000000" component of the
> > > node name and sets the reg property as expected. So as long as there is
> > > exactly one "memory[@address]" node in the tree,
> > > CONFIG_ARM_ATAG_DTB_COMPAT is happy.
> > >
> > > I will remove the /include/ from the dts files for VE (see below) in the
> > > v3.3-rc1 based series.
> > >
> > > Thanks for spotting this!
> > >
> > > Pawe??
> >
> > This carries a significant risk of unintended fragmentation and buggy
> > maintenance. This patch is a good example of the kind of change which
> > could easily go wrong. (I'm not saying that it is wrong -- just using
> > it as an example.)
> >
> > Since we will end up with a significantly large number of device trees
> > for vexpress, I can foresee that we'll end up with a highly reduncant
> > set of .dts{,i} files (each of which is often rather internally redundant
> > too).
> >
> > Does anyone have a view on whether it's acceptable to generate device
> > tree sources from another form, instead of having them verbatim in the
> > kernel tree? This could involve a preprocessor, or something more
> > heavyweight.
>
> Yes, the xilinx folks have been using a dts generator to create the
> device tree that matches an FPGA design. This works on ppc and
> microblaze, and they'll do the same thing for their ARM FPGA SoC.
OK, well I guess it's good to know we have the option to consider such
techniques for vexpress in the future.
For now, I suggest we paste in the .dts files as-is, since the situation
is not too unmanageable for now, and we don't unnecessary feature creep
to hold up merging of the series.
Cheers
---Dave
^ permalink raw reply [flat|nested] 76+ messages in thread
end of thread, other threads:[~2012-01-31 11:50 UTC | newest]
Thread overview: 76+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-12-15 14:02 [PATCH v6 0/9] Versatile Express DT support Pawel Moll
2011-12-15 14:02 ` Pawel Moll
2011-12-15 14:02 ` [PATCH v6 1/9] ARM: versatile: Add missing ENDPROC to headsmp.S Pawel Moll
2011-12-15 14:02 ` Pawel Moll
2011-12-15 14:02 ` [PATCH v6 2/9] ARM: vexpress: Get rid of MMIO_P2V Pawel Moll
2011-12-15 14:02 ` Pawel Moll
2011-12-15 14:02 ` [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible Pawel Moll
2011-12-15 14:02 ` Pawel Moll
[not found] ` <1323957761-13553-4-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org>
2011-12-15 14:53 ` Rob Herring
2011-12-15 14:53 ` Rob Herring
2011-12-15 15:25 ` Pawel Moll
2011-12-15 15:25 ` Pawel Moll
2011-12-15 17:25 ` Pawel Moll
2011-12-15 17:25 ` Pawel Moll
2011-12-15 14:02 ` [PATCH v6 4/9] ARM: vexpress: Use FDT data in platform SMP calls Pawel Moll
2011-12-15 14:02 ` Pawel Moll
2011-12-15 14:02 ` [PATCH v6 5/9] ARM: vexpress: Add Device Tree support Pawel Moll
2011-12-15 14:02 ` Pawel Moll
2012-01-10 11:13 ` Jon Medhurst (Tixy)
2012-01-10 11:13 ` Jon Medhurst (Tixy)
2011-12-15 14:02 ` [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support Pawel Moll
2011-12-15 14:02 ` Pawel Moll
2012-01-04 16:35 ` David Vrabel
2012-01-04 16:35 ` David Vrabel
2012-01-19 13:21 ` Pawel Moll
2012-01-19 13:21 ` Pawel Moll
[not found] ` <1326979266.32197.60.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2012-01-19 16:46 ` David Vrabel
2012-01-19 16:46 ` David Vrabel
2012-01-19 17:31 ` Pawel Moll
2012-01-19 17:31 ` Pawel Moll
2012-01-27 14:02 ` Pawel Moll
2012-01-27 14:02 ` Pawel Moll
[not found] ` <1327672960.24701.55.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2012-01-30 17:32 ` Dave Martin
2012-01-30 17:32 ` Dave Martin
2012-01-30 17:26 ` Dave Martin
2012-01-30 17:26 ` Dave Martin
2011-12-15 14:02 ` [PATCH v6 7/9] ARM: vexpress: Add Device Tree for V2P-CA5s core tile Pawel Moll
2011-12-15 14:02 ` Pawel Moll
2011-12-15 14:02 ` [PATCH v6 8/9] ARM: vexpress: Add Device Tree for V2P-CA9 " Pawel Moll
2011-12-15 14:02 ` Pawel Moll
2011-12-15 14:02 ` [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant) Pawel Moll
2011-12-15 14:02 ` Pawel Moll
2012-01-10 14:21 ` David Vrabel
2012-01-10 14:21 ` David Vrabel
2012-01-19 13:27 ` Pawel Moll
2012-01-19 13:27 ` Pawel Moll
[not found] ` <1326979652.32197.66.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2012-01-19 13:34 ` Rob Herring
2012-01-19 13:34 ` Rob Herring
2012-01-19 13:43 ` Pawel Moll
2012-01-19 13:43 ` Pawel Moll
[not found] ` <1326980594.32197.67.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2012-01-19 14:01 ` Rob Herring
2012-01-19 14:01 ` Rob Herring
2012-01-19 14:51 ` Pawel Moll
2012-01-19 14:51 ` Pawel Moll
[not found] ` <1326984672.32197.68.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2012-01-19 17:00 ` David Vrabel
2012-01-19 17:00 ` David Vrabel
[not found] ` <4F184C48.2050505-Sxgqhf6Nn4DQT0dZR+AlfA@public.gmane.org>
2012-01-19 17:11 ` Russell King - ARM Linux
2012-01-19 17:11 ` Russell King - ARM Linux
2012-01-19 17:27 ` Pawel Moll
2012-01-19 17:27 ` Pawel Moll
[not found] ` <1326994035.13748.7.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2012-01-19 17:50 ` Russell King - ARM Linux
2012-01-19 17:50 ` Russell King - ARM Linux
[not found] ` <20120119175053.GE10404-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2012-01-19 17:59 ` Grant Likely
2012-01-19 17:59 ` Grant Likely
2012-01-19 18:09 ` Nicolas Pitre
2012-01-19 18:09 ` Nicolas Pitre
[not found] ` <alpine.LFD.2.02.1201191305180.19587-QuJgVwGFrdf/9pzu0YdTqQ@public.gmane.org>
2012-01-19 22:07 ` Grant Likely
2012-01-19 22:07 ` Grant Likely
2012-01-25 17:43 ` Pawel Moll
2012-01-25 17:43 ` Pawel Moll
[not found] ` <1327513396.2355.28.camel-okZbbLrgpR/YkXV2EHHjLW3o5bpOHsLO@public.gmane.org>
2012-01-30 17:42 ` Dave Martin
2012-01-30 17:42 ` Dave Martin
[not found] ` <20120130174212.GH2248-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2012-01-30 21:31 ` Grant Likely
2012-01-30 21:31 ` Grant Likely
[not found] ` <20120130213115.GA22611-e0URQFbLeQY2iJbIjFUEsiwD8/FfD2ys@public.gmane.org>
2012-01-31 11:50 ` Dave Martin
2012-01-31 11:50 ` Dave Martin
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