[U-Boot] [PATCH V6 - Part 1 - 1/1] mx6q: define GPIO macros for translating between ordinals and port:index

[U-Boot] [PATCH V6 - Part 1 - 1/1] mx6q: define GPIO macros for translating between ordinals and port:index

[Eric Nelson]

The interface to the mxc_gpio driver uses integer (ordinal) values to
refer to all GPIOs on the i.MX processors. The registers themselves
and much of the i.MX documentation are banked in groups of 32, and these
macros allow the use of the port:index numbering for clarity.

GPIO_NUMBER() converts to ordinal value from port:index
GPIO_PORT() returns the port of an ordinal value
GPIO_INDEX() returns the index or offset of the ordinal.

Discussion on the mailing list at
	http://lists.denx.de/pipermail/u-boot/2012-January/116927.html

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 5227b44..8a9eeb4 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -164,6 +164,10 @@
 #define IRAM_SIZE                    0x00040000
 #define IMX_IIM_BASE                 OCOTP_BASE_ADDR
 
+#define GPIO_NUMBER(port, index)		((((port)-1)*32)+((index)&31))
+#define GPIO_TO_PORT(number)		(((number)/32)+1)
+#define GPIO_TO_INDEX(number)		((number)&31)
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
-- 
1.7.1

[U-Boot] [PATCH V6 - Part 2 - 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite)

[Eric Nelson]

This patch set refactors mxc_spi as described in 
    http://lists.denx.de/pipermail/u-boot/2010-March/068791.html   
and requested in 
    http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite 
specifically.

Patch 1 simply moves the conditional parts of mxc_spi.c into the
respective CPU-specific imx-regs.h files.

Patch 2 adds general support for SPI to the i.MX6.

Patch 3 adds support to the mx6qsabrelite board

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

[U-Boot] [PATCH V6 - Part 2 - 1/3] mxc_spi: move machine specifics into CPU headers

[Eric Nelson]

Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU

Introduce two new macros to control conditional setup
     MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
     MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
---
 arch/arm/include/asm/arch-mx31/imx-regs.h |   27 ++++++++
 arch/arm/include/asm/arch-mx35/imx-regs.h |   25 ++++++++
 arch/arm/include/asm/arch-mx5/imx-regs.h  |   30 +++++++++
 drivers/spi/mxc_spi.c                     |   93 ++---------------------------
 4 files changed, 88 insertions(+), 87 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 798cc74..6454acb 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -901,4 +901,31 @@ struct esdc_regs {
 #define MXC_EHCI_IPPUE_DOWN		(1 << 8)
 #define MXC_EHCI_IPPUE_UP		(1 << 9)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_SMC	(1 << 3)
+#define MXC_CSPICTRL_POL	(1 << 4)
+#define MXC_CSPICTRL_PHA	(1 << 5)
+#define MXC_CSPICTRL_SSCTL	(1 << 6)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC		(1 << 8)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPICTRL_MAXBITS	0x1f
+
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	4
+
+#define MXC_SPI_BASE_ADDRESSES \
+	0x43fa4000, \
+	0x50010000, \
+	0x53f84000,
+
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index df74508..e570ad1 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -179,6 +179,31 @@
 #define IPU_CONF_IC_EN		(1<<1)
 #define IPU_CONF_SCI_EN		(1<<0)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_SMC	(1 << 3)
+#define MXC_CSPICTRL_POL	(1 << 4)
+#define MXC_CSPICTRL_PHA	(1 << 5)
+#define MXC_CSPICTRL_SSCTL	(1 << 6)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	4
+
+#define MXC_SPI_BASE_ADDRESSES \
+	0x43fa4000, \
+	0x50010000,
+
 #define GPIO_PORT_NUM		3
 #define GPIO_NUM_PIN		32
 
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 0ee88d2..4fa6658 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -223,6 +223,36 @@
 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
 
 /*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN	18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL		4
+#define MXC_CSPICON_PHA		0
+#define MXC_CSPICON_SSPOL	12
+#define MXC_SPI_BASE_ADDRESSES \
+	CSPI1_BASE_ADDR, \
+	CSPI2_BASE_ADDR, \
+	CSPI3_BASE_ADDR,
+
+/*
  * Number of GPIO pins per port
  */
 #define GPIO_NUM_PIN            32
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 2fa7486..2e15318 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -33,93 +33,12 @@
 
 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
 "See linux mxc_spi driver from Freescale for details."
-
-#elif defined(CONFIG_MX31)
-
-#define MXC_CSPICTRL_EN		(1 << 0)
-#define MXC_CSPICTRL_MODE	(1 << 1)
-#define MXC_CSPICTRL_XCH	(1 << 2)
-#define MXC_CSPICTRL_SMC	(1 << 3)
-#define MXC_CSPICTRL_POL	(1 << 4)
-#define MXC_CSPICTRL_PHA	(1 << 5)
-#define MXC_CSPICTRL_SSCTL	(1 << 6)
-#define MXC_CSPICTRL_SSPOL	(1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
-#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
-#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC		(1 << 8)
-#define MXC_CSPICTRL_RXOVF	(1 << 6)
-#define MXC_CSPICTRL_MAXBITS	0x1f
-
-#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
-#define MAX_SPI_BYTES	4
-
-static unsigned long spi_bases[] = {
-	0x43fa4000,
-	0x50010000,
-	0x53f84000,
-};
-
-#elif defined(CONFIG_MX51)
-
-#define MXC_CSPICTRL_EN		(1 << 0)
-#define MXC_CSPICTRL_MODE	(1 << 1)
-#define MXC_CSPICTRL_XCH	(1 << 2)
-#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
-#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
-#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
-#define MXC_CSPICTRL_MAXBITS	0xfff
-#define MXC_CSPICTRL_TC		(1 << 7)
-#define MXC_CSPICTRL_RXOVF	(1 << 6)
-
-#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
-#define MAX_SPI_BYTES	32
-
-/* Bit position inside CTRL register to be associated with SS */
-#define MXC_CSPICTRL_CHAN	18
-
-/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL		4
-#define MXC_CSPICON_PHA		0
-#define MXC_CSPICON_SSPOL	12
-
-static unsigned long spi_bases[] = {
-	CSPI1_BASE_ADDR,
-	CSPI2_BASE_ADDR,
-	CSPI3_BASE_ADDR,
-};
-
-#elif defined(CONFIG_MX35)
-
-#define MXC_CSPICTRL_EN		(1 << 0)
-#define MXC_CSPICTRL_MODE	(1 << 1)
-#define MXC_CSPICTRL_XCH	(1 << 2)
-#define MXC_CSPICTRL_SMC	(1 << 3)
-#define MXC_CSPICTRL_POL	(1 << 4)
-#define MXC_CSPICTRL_PHA	(1 << 5)
-#define MXC_CSPICTRL_SSCTL	(1 << 6)
-#define MXC_CSPICTRL_SSPOL	(1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC		(1 << 7)
-#define MXC_CSPICTRL_RXOVF	(1 << 6)
-#define MXC_CSPICTRL_MAXBITS	0xfff
-
-#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
-#define MAX_SPI_BYTES	4
+#endif
 
 static unsigned long spi_bases[] = {
-	0x43fa4000,
-	0x50010000,
+	MXC_SPI_BASE_ADDRESSES
 };
 
-#else
-#error "Unsupported architecture"
-#endif
-
 #define OUT	MXC_GPIO_DIRECTION_OUT
 
 #define reg_read readl
@@ -129,7 +48,7 @@ struct mxc_spi_slave {
 	struct spi_slave slave;
 	unsigned long	base;
 	u32		ctrl_reg;
-#if defined(CONFIG_MX51)
+#if defined(MXC_ECSPI)
 	u32		cfg_reg;
 #endif
 	int		gpio;
@@ -167,7 +86,7 @@ u32 get_cspi_div(u32 div)
 	return i;
 }
 
-#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#ifdef MXC_CSPI
 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
@@ -204,7 +123,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 }
 #endif
 
-#if defined(CONFIG_MX51)
+#ifdef MXC_ECSPI
 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
@@ -316,7 +235,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
 		MXC_CSPICTRL_BITCOUNT(bitlen - 1);
 
 	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
-#ifdef CONFIG_MX51
+#ifdef MXC_ECSPI
 	reg_write(&regs->cfg, mxcs->cfg_reg);
 #endif
 
-- 
1.7.1

[U-Boot] [PATCH V6 - Part 2 - 2/3] mx6q: Add support for ECSPI through mxc_spi driver

[Eric Nelson]

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |   44 ++++++++++++++++++++++++++++++
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 29841dd..326f865 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -194,6 +194,50 @@ struct src {
 	u32     gpr10;
 };
 
+/* ECSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 cfg;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN	18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL		4
+#define MXC_CSPICON_PHA		0
+#define MXC_CSPICON_SSPOL	12
+#define MXC_SPI_BASE_ADDRESSES \
+	ECSPI1_BASE_ADDR, \
+	ECSPI2_BASE_ADDR, \
+	ECSPI3_BASE_ADDR, \
+	ECSPI4_BASE_ADDR, \
+	ECSPI5_BASE_ADDR
+
 struct iim_regs {
 	u32	ctrl;
 	u32	ctrl_set;
-- 
1.7.1

[U-Boot] [PATCH V6 - Part 2 - 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform

[Eric Nelson]

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
---
 board/freescale/mx6qsabrelite/imximage.cfg    |    2 +-
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   25 +++++++++++++++++++++++++
 include/configs/mx6qsabrelite.h               |    9 +++++++++
 3 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg
index 83dee6f..c389427 100644
--- a/board/freescale/mx6qsabrelite/imximage.cfg
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006
 
 # set the default clock gate to save power
 DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF00000
 DATA 4 0x020c4078 0x00FFF300
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index a53b01f..97a77e8 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t ecspi1_pads[] = {
+	/* SS1 */
+	MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+void setup_spi(void)
+{
+	gpio_direction_output(GPIO_NUMBER(3, 19), 1);
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+					 ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
 #define MII_1000BASET_CTRL		0x9
 #define MII_EXTENDED_CTRL		0xb
 #define MII_EXTENDED_DATAW		0xc
@@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis)
 		return ret;
 	}
 
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+
 	return 0;
 }
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index d650ee3..bcb1a42 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -44,6 +44,15 @@
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE           UART2_BASE
 
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-- 
1.7.1

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

Patch 1 modifies the 'sf' command to allow a default bus and chip-select
to be specified by board headers. This allows a bare 'sf' probe command:
      U-Boot> sf probe
instead of the more cumbersome usage when a GPIO is tacked onto
the chip-select. Otherwise, this command-line would be needed
to specify GP3:19 on SabreLite:
      U-Boot> sf probe 0x5300

Patch 2 provides a description of usage and configuration of CONFIG_CMD_SF.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

[U-Boot] [PATCH V6 - Part 3 - 1/2] sf command: allow default bus and chip selects

[Eric Nelson]

This patch allows a board configuration file to provide default bus
and chip-selects for SPI flash so that first argument to the 'sf' command
is optional.

On boards that use the mxc_spi driver and a GPIO for chip select, this allows
a much simpler command line:
	U-Boot> sf probe
instead of
	U-Boot> sf probe 0x5300
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 common/cmd_sf.c |   37 +++++++++++++++++++++----------------
 1 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 612fd18..98e4162 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -17,6 +17,12 @@
 #ifndef CONFIG_SF_DEFAULT_MODE
 # define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
 #endif
+#ifndef CONFIG_SF_DEFAULT_CS
+# define CONFIG_SF_DEFAULT_CS		0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+# define CONFIG_SF_DEFAULT_BUS		0
+#endif
 
 static struct spi_flash *flash;
 
@@ -63,27 +69,26 @@ static int sf_parse_len_arg(char *arg, ulong *len)
 
 static int do_spi_flash_probe(int argc, char * const argv[])
 {
-	unsigned int bus = 0;
-	unsigned int cs;
+	unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+	unsigned int cs = CONFIG_SF_DEFAULT_CS;
 	unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
 	unsigned int mode = CONFIG_SF_DEFAULT_MODE;
 	char *endp;
 	struct spi_flash *new;
 
-	if (argc < 2)
-		return -1;
-
-	cs = simple_strtoul(argv[1], &endp, 0);
-	if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
-		return -1;
-	if (*endp == ':') {
-		if (endp[1] == 0)
-			return -1;
-
-		bus = cs;
-		cs = simple_strtoul(endp + 1, &endp, 0);
-		if (*endp != 0)
+	if (argc >= 2) {
+		cs = simple_strtoul(argv[1], &endp, 0);
+		if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
 			return -1;
+		if (*endp == ':') {
+			if (endp[1] == 0)
+				return -1;
+
+			bus = cs;
+			cs = simple_strtoul(endp + 1, &endp, 0);
+			if (*endp != 0)
+				return -1;
+		}
 	}
 
 	if (argc >= 3) {
@@ -299,7 +304,7 @@ usage:
 U_BOOT_CMD(
 	sf,	5,	1,	do_spi_flash,
 	"SPI flash sub-system",
-	"probe [bus:]cs [hz] [mode]	- init flash device on given SPI bus\n"
+	"probe [[bus:]cs] [hz] [mode]	- init flash device on given SPI bus\n"
 	"				  and chip select\n"
 	"sf read addr offset len 	- read `len' bytes starting at\n"
 	"				  `offset' to memory at `addr'\n"
-- 
1.7.1

[U-Boot] [PATCH V6 - Part 2 - 2/2] README: Add description of SPI Flash (SF) command configuration

[Eric Nelson]

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
---
 README |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/README b/README
index 9d713e8..4dbebcb 100644
--- a/README
+++ b/README
@@ -809,6 +809,7 @@ The following options need to be configured:
 					  (requires CONFIG_CMD_I2C)
 		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
 					  (4xx only)
+		CONFIG_CMD_SF		* Read/write/erase SPI NOR flash
 		CONFIG_CMD_SHA1SUM	  print sha1 memory digest
 					  (requires CONFIG_CMD_MEMORY)
 		CONFIG_CMD_SOURCE	  "source" command Support
@@ -2191,6 +2192,25 @@ The following options need to be configured:
 		allows to read/write in Dataflash via the standard
 		commands cp, md...
 
+- Serial Flash support
+		CONFIG_CMD_SF
+
+		Defining this option enables SPI flash commands
+		'sf probe/read/write/erase/update'.
+
+		Usage requires an initial 'probe' to define the serial
+		flash parameters, followed by read/write/erase/update
+		commands.
+
+		The following defaults may be provided by the platform
+		to handle the common case when only a single serial
+		flash is present on the system.
+
+		CONFIG_SF_DEFAULT_BUS		Bus identifier
+		CONFIG_SF_DEFAULT_CS		Chip-select
+		CONFIG_SF_DEFAULT_MODE 		(see include/spi.h)
+		CONFIG_SF_DEFAULT_SPEED		in Hz
+
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 
-- 
1.7.1

[U-Boot] [PATCH V6 - Part 4 - 1/1] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Eric Nelson]

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |    2 +-
 include/configs/mx6qsabrelite.h               |    2 ++
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 97a77e8..03a088a 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -208,7 +208,7 @@ iomux_v3_cfg_t ecspi1_pads[] = {
 
 void setup_spi(void)
 {
-	gpio_direction_output(GPIO_NUMBER(3, 19), 1);
+	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 					 ARRAY_SIZE(ecspi1_pads));
 }
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index bcb1a42..2286bb0 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -49,6 +49,8 @@
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS  0
+#define CONFIG_SF_DEFAULT_CS   (0|(GPIO_NUMBER(3, 19)<<8))
 #define CONFIG_SF_DEFAULT_SPEED 25000000
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
-- 
1.7.1

[U-Boot] [PATCH V6 - Part 5 - 1/1] mx6q: mx6qsabrelite: Conditionally define macros for environment in serial flash

[Eric Nelson]

The default settings store the persistent environment on SD card
and not serial flash (SPI NOR).

To use SPI NOR to save the environment instead of SD card, edit
include/configs/mx6qsabrelite.h and

- undefine CONFIG_ENV_IS_IN_MMC
- define   CONFIG_ENV_IS_IN_SPI_FLASH

The SPI driver can take as chip select the controller's chip selects
as well as an external GPIO. The LSB byte has the value of the internal
chip select, the highest (thought as 16-bit value) contains the GPIO
number.

The GPIO used on Sabre Lite is GP3:19 == 83.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

---
 include/configs/mx6qsabrelite.h |   18 +++++++++++++++---
 1 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 2286bb0..c49e3ab 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -174,10 +174,22 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ENV_OFFSET              (6 * 64 * 1024)
-#define CONFIG_ENV_SIZE                        (8 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV         0
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#endif
 
 #define CONFIG_OF_LIBFDT
 
-- 
1.7.1

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Mike Frysinger]

On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:
> Patch 1 modifies the 'sf' command to allow a default bus and chip-select
> to be specified by board headers. This allows a bare 'sf' probe command:
>       U-Boot> sf probe
> instead of the more cumbersome usage when a GPIO is tacked onto
> the chip-select. Otherwise, this command-line would be needed
> to specify GP3:19 on SabreLite:
>       U-Boot> sf probe 0x5300
> 
> Patch 2 provides a description of usage and configuration of CONFIG_CMD_SF.

you can drop these two SF patches from your mx6q series.  i don't want to keep 
checking to see if you've updated them :p.
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20120131/eeb25e19/attachment.pgp>

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

On 01/31/2012 11:11 AM, Mike Frysinger wrote:
> On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:
>> Patch 1 modifies the 'sf' command to allow a default bus and chip-select
>> to be specified by board headers. This allows a bare 'sf' probe command:
>>        U-Boot>  sf probe
>> instead of the more cumbersome usage when a GPIO is tacked onto
>> the chip-select. Otherwise, this command-line would be needed
>> to specify GP3:19 on SabreLite:
>>        U-Boot>  sf probe 0x5300
>>
>> Patch 2 provides a description of usage and configuration of CONFIG_CMD_SF.
>
> you can drop these two SF patches from your mx6q series.  i don't want to keep
> checking to see if you've updated them :p.
> -mike

I figured as much, but I can't really test them without the rest of the
series...

[U-Boot] [PATCH V6 - Part 2 - 1/3] mxc_spi: move machine specifics into CPU headers

[Jason Hui]

On Wed, Feb 1, 2012 at 1:52 AM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU
>
> Introduce two new macros to control conditional setup
> ? ? MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
> ? ? MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)
>
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
> Acked-by: Stefano Babic <sbabic@denx.de>
> ---
> ?arch/arm/include/asm/arch-mx31/imx-regs.h | ? 27 ++++++++
> ?arch/arm/include/asm/arch-mx35/imx-regs.h | ? 25 ++++++++
> ?arch/arm/include/asm/arch-mx5/imx-regs.h ?| ? 30 +++++++++
> ?drivers/spi/mxc_spi.c ? ? ? ? ? ? ? ? ? ? | ? 93 ++---------------------------
> ?4 files changed, 88 insertions(+), 87 deletions(-)

Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>

>
> diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
> index 798cc74..6454acb 100644
> --- a/arch/arm/include/asm/arch-mx31/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
> @@ -901,4 +901,31 @@ struct esdc_regs {
> ?#define MXC_EHCI_IPPUE_DOWN ? ? ? ? ? ?(1 << 8)
> ?#define MXC_EHCI_IPPUE_UP ? ? ? ? ? ? ?(1 << 9)
>
> +/*
> + * CSPI register definitions
> + */
> +#define MXC_CSPI
> +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0)
> +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1)
> +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2)
> +#define MXC_CSPICTRL_SMC ? ? ? (1 << 3)
> +#define MXC_CSPICTRL_POL ? ? ? (1 << 4)
> +#define MXC_CSPICTRL_PHA ? ? ? (1 << 5)
> +#define MXC_CSPICTRL_SSCTL ? ? (1 << 6)
> +#define MXC_CSPICTRL_SSPOL ? ? (1 << 7)
> +#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 24)
> +#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0x1f) << 8)
> +#define MXC_CSPICTRL_DATARATE(x) ? ? ? (((x) & 0x7) << 16)
> +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 8)
> +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6)
> +#define MXC_CSPICTRL_MAXBITS ? 0x1f
> +
> +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15)
> +#define MAX_SPI_BYTES ?4
> +
> +#define MXC_SPI_BASE_ADDRESSES \
> + ? ? ? 0x43fa4000, \
> + ? ? ? 0x50010000, \
> + ? ? ? 0x53f84000,
> +
> ?#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
> diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
> index df74508..e570ad1 100644
> --- a/arch/arm/include/asm/arch-mx35/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
> @@ -179,6 +179,31 @@
> ?#define IPU_CONF_IC_EN ? ? ? ? (1<<1)
> ?#define IPU_CONF_SCI_EN ? ? ? ? ? ? ? ?(1<<0)
>
> +/*
> + * CSPI register definitions
> + */
> +#define MXC_CSPI
> +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0)
> +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1)
> +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2)
> +#define MXC_CSPICTRL_SMC ? ? ? (1 << 3)
> +#define MXC_CSPICTRL_POL ? ? ? (1 << 4)
> +#define MXC_CSPICTRL_PHA ? ? ? (1 << 5)
> +#define MXC_CSPICTRL_SSCTL ? ? (1 << 6)
> +#define MXC_CSPICTRL_SSPOL ? ? (1 << 7)
> +#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12)
> +#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20)
> +#define MXC_CSPICTRL_DATARATE(x) ? ? ? (((x) & 0x7) << 16)
> +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7)
> +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6)
> +#define MXC_CSPICTRL_MAXBITS ? 0xfff
> +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15)
> +#define MAX_SPI_BYTES ?4
> +
> +#define MXC_SPI_BASE_ADDRESSES \
> + ? ? ? 0x43fa4000, \
> + ? ? ? 0x50010000,
> +
> ?#define GPIO_PORT_NUM ? ? ? ? ?3
> ?#define GPIO_NUM_PIN ? ? ? ? ? 32
>
> diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
> index 0ee88d2..4fa6658 100644
> --- a/arch/arm/include/asm/arch-mx5/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
> @@ -223,6 +223,36 @@
> ?#define CS0_32M_CS1_32M_CS2_32M_CS3_32M ? ? ? ? ? ? ? ?3
>
> ?/*
> + * CSPI register definitions
> + */
> +#define MXC_ECSPI
> +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0)
> +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1)
> +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2)
> +#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12)
> +#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20)
> +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
> +#define MXC_CSPICTRL_POSTDIV(x) ? ? ? ?(((x) & 0xF) << 8)
> +#define MXC_CSPICTRL_SELCHAN(x) ? ? ? ?(((x) & 0x3) << 18)
> +#define MXC_CSPICTRL_MAXBITS ? 0xfff
> +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7)
> +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6)
> +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15)
> +#define MAX_SPI_BYTES ?32
> +
> +/* Bit position inside CTRL register to be associated with SS */
> +#define MXC_CSPICTRL_CHAN ? ? ?18
> +
> +/* Bit position inside CON register to be associated with SS */
> +#define MXC_CSPICON_POL ? ? ? ? ? ? ? ?4
> +#define MXC_CSPICON_PHA ? ? ? ? ? ? ? ?0
> +#define MXC_CSPICON_SSPOL ? ? ?12
> +#define MXC_SPI_BASE_ADDRESSES \
> + ? ? ? CSPI1_BASE_ADDR, \
> + ? ? ? CSPI2_BASE_ADDR, \
> + ? ? ? CSPI3_BASE_ADDR,
> +
> +/*
> ?* Number of GPIO pins per port
> ?*/
> ?#define GPIO_NUM_PIN ? ? ? ? ? ?32
> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
> index 2fa7486..2e15318 100644
> --- a/drivers/spi/mxc_spi.c
> +++ b/drivers/spi/mxc_spi.c
> @@ -33,93 +33,12 @@
>
> ?#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
> ?"See linux mxc_spi driver from Freescale for details."
> -
> -#elif defined(CONFIG_MX31)
> -
> -#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0)
> -#define MXC_CSPICTRL_MODE ? ? ?(1 << 1)
> -#define MXC_CSPICTRL_XCH ? ? ? (1 << 2)
> -#define MXC_CSPICTRL_SMC ? ? ? (1 << 3)
> -#define MXC_CSPICTRL_POL ? ? ? (1 << 4)
> -#define MXC_CSPICTRL_PHA ? ? ? (1 << 5)
> -#define MXC_CSPICTRL_SSCTL ? ? (1 << 6)
> -#define MXC_CSPICTRL_SSPOL ? ? (1 << 7)
> -#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 24)
> -#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0x1f) << 8)
> -#define MXC_CSPICTRL_DATARATE(x) ? ? ? (((x) & 0x7) << 16)
> -#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 8)
> -#define MXC_CSPICTRL_RXOVF ? ? (1 << 6)
> -#define MXC_CSPICTRL_MAXBITS ? 0x1f
> -
> -#define MXC_CSPIPERIOD_32KHZ ? (1 << 15)
> -#define MAX_SPI_BYTES ?4
> -
> -static unsigned long spi_bases[] = {
> - ? ? ? 0x43fa4000,
> - ? ? ? 0x50010000,
> - ? ? ? 0x53f84000,
> -};
> -
> -#elif defined(CONFIG_MX51)
> -
> -#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0)
> -#define MXC_CSPICTRL_MODE ? ? ?(1 << 1)
> -#define MXC_CSPICTRL_XCH ? ? ? (1 << 2)
> -#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12)
> -#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20)
> -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
> -#define MXC_CSPICTRL_POSTDIV(x) ? ? ? ?(((x) & 0xF) << 8)
> -#define MXC_CSPICTRL_SELCHAN(x) ? ? ? ?(((x) & 0x3) << 18)
> -#define MXC_CSPICTRL_MAXBITS ? 0xfff
> -#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7)
> -#define MXC_CSPICTRL_RXOVF ? ? (1 << 6)
> -
> -#define MXC_CSPIPERIOD_32KHZ ? (1 << 15)
> -#define MAX_SPI_BYTES ?32
> -
> -/* Bit position inside CTRL register to be associated with SS */
> -#define MXC_CSPICTRL_CHAN ? ? ?18
> -
> -/* Bit position inside CON register to be associated with SS */
> -#define MXC_CSPICON_POL ? ? ? ? ? ? ? ?4
> -#define MXC_CSPICON_PHA ? ? ? ? ? ? ? ?0
> -#define MXC_CSPICON_SSPOL ? ? ?12
> -
> -static unsigned long spi_bases[] = {
> - ? ? ? CSPI1_BASE_ADDR,
> - ? ? ? CSPI2_BASE_ADDR,
> - ? ? ? CSPI3_BASE_ADDR,
> -};
> -
> -#elif defined(CONFIG_MX35)
> -
> -#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0)
> -#define MXC_CSPICTRL_MODE ? ? ?(1 << 1)
> -#define MXC_CSPICTRL_XCH ? ? ? (1 << 2)
> -#define MXC_CSPICTRL_SMC ? ? ? (1 << 3)
> -#define MXC_CSPICTRL_POL ? ? ? (1 << 4)
> -#define MXC_CSPICTRL_PHA ? ? ? (1 << 5)
> -#define MXC_CSPICTRL_SSCTL ? ? (1 << 6)
> -#define MXC_CSPICTRL_SSPOL ? ? (1 << 7)
> -#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12)
> -#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20)
> -#define MXC_CSPICTRL_DATARATE(x) ? ? ? (((x) & 0x7) << 16)
> -#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7)
> -#define MXC_CSPICTRL_RXOVF ? ? (1 << 6)
> -#define MXC_CSPICTRL_MAXBITS ? 0xfff
> -
> -#define MXC_CSPIPERIOD_32KHZ ? (1 << 15)
> -#define MAX_SPI_BYTES ?4
> +#endif
>
> ?static unsigned long spi_bases[] = {
> - ? ? ? 0x43fa4000,
> - ? ? ? 0x50010000,
> + ? ? ? MXC_SPI_BASE_ADDRESSES
> ?};
>
> -#else
> -#error "Unsupported architecture"
> -#endif
> -
> ?#define OUT ? ?MXC_GPIO_DIRECTION_OUT
>
> ?#define reg_read readl
> @@ -129,7 +48,7 @@ struct mxc_spi_slave {
> ? ? ? ?struct spi_slave slave;
> ? ? ? ?unsigned long ? base;
> ? ? ? ?u32 ? ? ? ? ? ? ctrl_reg;
> -#if defined(CONFIG_MX51)
> +#if defined(MXC_ECSPI)
> ? ? ? ?u32 ? ? ? ? ? ? cfg_reg;
> ?#endif
> ? ? ? ?int ? ? ? ? ? ? gpio;
> @@ -167,7 +86,7 @@ u32 get_cspi_div(u32 div)
> ? ? ? ?return i;
> ?}
>
> -#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
> +#ifdef MXC_CSPI
> ?static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
> ? ? ? ? ? ? ? ?unsigned int max_hz, unsigned int mode)
> ?{
> @@ -204,7 +123,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
> ?}
> ?#endif
>
> -#if defined(CONFIG_MX51)
> +#ifdef MXC_ECSPI
> ?static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
> ? ? ? ? ? ? ? ?unsigned int max_hz, unsigned int mode)
> ?{
> @@ -316,7 +235,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
> ? ? ? ? ? ? ? ?MXC_CSPICTRL_BITCOUNT(bitlen - 1);
>
> ? ? ? ?reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
> -#ifdef CONFIG_MX51
> +#ifdef MXC_ECSPI
> ? ? ? ?reg_write(&regs->cfg, mxcs->cfg_reg);
> ?#endif
>
> --
> 1.7.1
>

[U-Boot] [PATCH V6 - Part 2 - 2/3] mx6q: Add support for ECSPI through mxc_spi driver

[Jason Hui]

On Wed, Feb 1, 2012 at 1:52 AM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
> Acked-by: Stefano Babic <sbabic@denx.de>
> ---
> ?arch/arm/include/asm/arch-mx6/imx-regs.h | ? 44 ++++++++++++++++++++++++++++++
> ?1 files changed, 44 insertions(+), 0 deletions(-)

Acked-by: Jason Liu <jason.hui@linaro.org>

>
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 29841dd..326f865 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -194,6 +194,50 @@ struct src {
> ? ? ? ?u32 ? ? gpr10;
> ?};
>
> +/* ECSPI registers */
> +struct cspi_regs {
> + ? ? ? u32 rxdata;
> + ? ? ? u32 txdata;
> + ? ? ? u32 ctrl;
> + ? ? ? u32 cfg;
> + ? ? ? u32 intr;
> + ? ? ? u32 dma;
> + ? ? ? u32 stat;
> + ? ? ? u32 period;
> +};
> +
> +/*
> + * CSPI register definitions
> + */
> +#define MXC_ECSPI
> +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0)
> +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1)
> +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2)
> +#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12)
> +#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20)
> +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
> +#define MXC_CSPICTRL_POSTDIV(x) ? ? ? ?(((x) & 0xF) << 8)
> +#define MXC_CSPICTRL_SELCHAN(x) ? ? ? ?(((x) & 0x3) << 18)
> +#define MXC_CSPICTRL_MAXBITS ? 0xfff
> +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7)
> +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6)
> +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15)
> +#define MAX_SPI_BYTES ?32
> +
> +/* Bit position inside CTRL register to be associated with SS */
> +#define MXC_CSPICTRL_CHAN ? ? ?18
> +
> +/* Bit position inside CON register to be associated with SS */
> +#define MXC_CSPICON_POL ? ? ? ? ? ? ? ?4
> +#define MXC_CSPICON_PHA ? ? ? ? ? ? ? ?0
> +#define MXC_CSPICON_SSPOL ? ? ?12
> +#define MXC_SPI_BASE_ADDRESSES \
> + ? ? ? ECSPI1_BASE_ADDR, \
> + ? ? ? ECSPI2_BASE_ADDR, \
> + ? ? ? ECSPI3_BASE_ADDR, \
> + ? ? ? ECSPI4_BASE_ADDR, \
> + ? ? ? ECSPI5_BASE_ADDR
> +
> ?struct iim_regs {
> ? ? ? ?u32 ? ? ctrl;
> ? ? ? ?u32 ? ? ctrl_set;
> --
> 1.7.1
>

[U-Boot] [PATCH V6 - Part 2 - 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform

[Jason Hui]

On Wed, Feb 1, 2012 at 1:52 AM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
> Acked-by: Stefano Babic <sbabic@denx.de>
> ---
> ?board/freescale/mx6qsabrelite/imximage.cfg ? ?| ? ?2 +-
> ?board/freescale/mx6qsabrelite/mx6qsabrelite.c | ? 25 +++++++++++++++++++++++++
> ?include/configs/mx6qsabrelite.h ? ? ? ? ? ? ? | ? ?9 +++++++++
> ?3 files changed, 35 insertions(+), 1 deletions(-)

Acked-by: Jason Liu <jason.hui@linaro.org>

Tested on Sabre-lite board.

Tested-by: Jason Liu <jason.hui@linaro.org>

>
> diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg
> index 83dee6f..c389427 100644
> --- a/board/freescale/mx6qsabrelite/imximage.cfg
> +++ b/board/freescale/mx6qsabrelite/imximage.cfg
> @@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006
>
> ?# set the default clock gate to save power
> ?DATA 4 0x020c4068 0x00C03F3F
> -DATA 4 0x020c406c 0x0030FC00
> +DATA 4 0x020c406c 0x0030FC03
> ?DATA 4 0x020c4070 0x0FFFC000
> ?DATA 4 0x020c4074 0x3FF00000
> ?DATA 4 0x020c4078 0x00FFF300
> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> index a53b01f..97a77e8 100644
> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> @@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR;
> ? ? ? ?PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED ? | ? ? ? ? ? ? \
> ? ? ? ?PAD_CTL_DSE_40ohm ? | PAD_CTL_HYS)
>
> +#define SPI_PAD_CTRL (PAD_CTL_HYS | ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | ? ? ? ? ? ? \
> + ? ? ? PAD_CTL_DSE_40ohm ? ? | PAD_CTL_SRE_FAST)
> +
> ?int dram_init(void)
> ?{
> ? ? ? ?gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> @@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis)
> ?}
> ?#endif
>
> +#ifdef CONFIG_MXC_SPI
> +iomux_v3_cfg_t ecspi1_pads[] = {
> + ? ? ? /* SS1 */
> + ? ? ? MX6Q_PAD_EIM_D19__GPIO_3_19 ? | MUX_PAD_CTRL(SPI_PAD_CTRL),
> + ? ? ? MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
> + ? ? ? MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
> + ? ? ? MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +};
> +
> +void setup_spi(void)
> +{
> + ? ? ? gpio_direction_output(GPIO_NUMBER(3, 19), 1);
> + ? ? ? imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARRAY_SIZE(ecspi1_pads));
> +}
> +#endif
> +
> ?#define MII_1000BASET_CTRL ? ? ? ? ? ? 0x9
> ?#define MII_EXTENDED_CTRL ? ? ? ? ? ? ?0xb
> ?#define MII_EXTENDED_DATAW ? ? ? ? ? ? 0xc
> @@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis)
> ? ? ? ? ? ? ? ?return ret;
> ? ? ? ?}
>
> +#ifdef CONFIG_MXC_SPI
> + ? ? ? setup_spi();
> +#endif
> +
> ? ? ? ?return 0;
> ?}
>
> diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
> index d650ee3..bcb1a42 100644
> --- a/include/configs/mx6qsabrelite.h
> +++ b/include/configs/mx6qsabrelite.h
> @@ -44,6 +44,15 @@
> ?#define CONFIG_MXC_UART
> ?#define CONFIG_MXC_UART_BASE ? ? ? ? ? UART2_BASE
>
> +#define CONFIG_CMD_SF
> +#ifdef CONFIG_CMD_SF
> +#define CONFIG_SPI_FLASH
> +#define CONFIG_SPI_FLASH_SST
> +#define CONFIG_MXC_SPI
> +#define CONFIG_SF_DEFAULT_SPEED 25000000
> +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
> +#endif
> +
> ?/* MMC Configs */
> ?#define CONFIG_FSL_ESDHC
> ?#define CONFIG_FSL_USDHC
> --
> 1.7.1
>

[U-Boot] [PATCH V6 - Part 3 - 1/2] sf command: allow default bus and chip selects

[Jason Hui]

On Wed, Feb 1, 2012 at 1:52 AM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> This patch allows a board configuration file to provide default bus
> and chip-selects for SPI flash so that first argument to the 'sf' command
> is optional.
>
> On boards that use the mxc_spi driver and a GPIO for chip select, this allows
> a much simpler command line:
> ? ? ? ?U-Boot> sf probe
> instead of
> ? ? ? ?U-Boot> sf probe 0x5300
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> ---
> ?common/cmd_sf.c | ? 37 +++++++++++++++++++++----------------
> ?1 files changed, 21 insertions(+), 16 deletions(-)

Acked-by: Jason Liu <jason.hui@linaro.org>

Tested on i.mx6q sabre-lite board with sf command:

MX6QSABRELITE U-Boot > sf probe
SF: Detected SST25VF016B with page size 4 KiB, total 2 MiB

Tested-by: Jason Liu <jason.hui@linaro.org>

>
> diff --git a/common/cmd_sf.c b/common/cmd_sf.c
> index 612fd18..98e4162 100644
> --- a/common/cmd_sf.c
> +++ b/common/cmd_sf.c
> @@ -17,6 +17,12 @@
> ?#ifndef CONFIG_SF_DEFAULT_MODE
> ?# define CONFIG_SF_DEFAULT_MODE ? ? ? ? ? ? ? ?SPI_MODE_3
> ?#endif
> +#ifndef CONFIG_SF_DEFAULT_CS
> +# define CONFIG_SF_DEFAULT_CS ? ? ? ? ?0
> +#endif
> +#ifndef CONFIG_SF_DEFAULT_BUS
> +# define CONFIG_SF_DEFAULT_BUS ? ? ? ? 0
> +#endif
>
> ?static struct spi_flash *flash;
>
> @@ -63,27 +69,26 @@ static int sf_parse_len_arg(char *arg, ulong *len)
>
> ?static int do_spi_flash_probe(int argc, char * const argv[])
> ?{
> - ? ? ? unsigned int bus = 0;
> - ? ? ? unsigned int cs;
> + ? ? ? unsigned int bus = CONFIG_SF_DEFAULT_BUS;
> + ? ? ? unsigned int cs = CONFIG_SF_DEFAULT_CS;
> ? ? ? ?unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
> ? ? ? ?unsigned int mode = CONFIG_SF_DEFAULT_MODE;
> ? ? ? ?char *endp;
> ? ? ? ?struct spi_flash *new;
>
> - ? ? ? if (argc < 2)
> - ? ? ? ? ? ? ? return -1;
> -
> - ? ? ? cs = simple_strtoul(argv[1], &endp, 0);
> - ? ? ? if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
> - ? ? ? ? ? ? ? return -1;
> - ? ? ? if (*endp == ':') {
> - ? ? ? ? ? ? ? if (endp[1] == 0)
> - ? ? ? ? ? ? ? ? ? ? ? return -1;
> -
> - ? ? ? ? ? ? ? bus = cs;
> - ? ? ? ? ? ? ? cs = simple_strtoul(endp + 1, &endp, 0);
> - ? ? ? ? ? ? ? if (*endp != 0)
> + ? ? ? if (argc >= 2) {
> + ? ? ? ? ? ? ? cs = simple_strtoul(argv[1], &endp, 0);
> + ? ? ? ? ? ? ? if (*argv[1] == 0 || (*endp != 0 && *endp != ':'))
> ? ? ? ? ? ? ? ? ? ? ? ?return -1;
> + ? ? ? ? ? ? ? if (*endp == ':') {
> + ? ? ? ? ? ? ? ? ? ? ? if (endp[1] == 0)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? return -1;
> +
> + ? ? ? ? ? ? ? ? ? ? ? bus = cs;
> + ? ? ? ? ? ? ? ? ? ? ? cs = simple_strtoul(endp + 1, &endp, 0);
> + ? ? ? ? ? ? ? ? ? ? ? if (*endp != 0)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? return -1;
> + ? ? ? ? ? ? ? }
> ? ? ? ?}
>
> ? ? ? ?if (argc >= 3) {
> @@ -299,7 +304,7 @@ usage:
> ?U_BOOT_CMD(
> ? ? ? ?sf, ? ? 5, ? ? ?1, ? ? ?do_spi_flash,
> ? ? ? ?"SPI flash sub-system",
> - ? ? ? "probe [bus:]cs [hz] [mode] ? ? - init flash device on given SPI bus\n"
> + ? ? ? "probe [[bus:]cs] [hz] [mode] ? - init flash device on given SPI bus\n"
> ? ? ? ?" ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? and chip select\n"
> ? ? ? ?"sf read addr offset len ? ? ? ?- read `len' bytes starting at\n"
> ? ? ? ?" ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? `offset' to memory at `addr'\n"
> --
> 1.7.1
>

[U-Boot] [PATCH V6 - Part 2 - 2/2] README: Add description of SPI Flash (SF) command configuration

[Jason Hui]

On Wed, Feb 1, 2012 at 1:52 AM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> ---
> ?README | ? 20 ++++++++++++++++++++
> ?1 files changed, 20 insertions(+), 0 deletions(-)

Acked-by: Jason Liu <jason.hui@linaro.org>

>
> diff --git a/README b/README
> index 9d713e8..4dbebcb 100644
> --- a/README
> +++ b/README
> @@ -809,6 +809,7 @@ The following options need to be configured:
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(requires CONFIG_CMD_I2C)
> ? ? ? ? ? ? ? ?CONFIG_CMD_SETGETDCR ? ? ?Support for DCR Register access
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(4xx only)
> + ? ? ? ? ? ? ? CONFIG_CMD_SF ? ? ? ? ? * Read/write/erase SPI NOR flash
> ? ? ? ? ? ? ? ?CONFIG_CMD_SHA1SUM ? ? ? ?print sha1 memory digest
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(requires CONFIG_CMD_MEMORY)
> ? ? ? ? ? ? ? ?CONFIG_CMD_SOURCE ? ? ? ? "source" command Support
> @@ -2191,6 +2192,25 @@ The following options need to be configured:
> ? ? ? ? ? ? ? ?allows to read/write in Dataflash via the standard
> ? ? ? ? ? ? ? ?commands cp, md...
>
> +- Serial Flash support
> + ? ? ? ? ? ? ? CONFIG_CMD_SF
> +
> + ? ? ? ? ? ? ? Defining this option enables SPI flash commands
> + ? ? ? ? ? ? ? 'sf probe/read/write/erase/update'.
> +
> + ? ? ? ? ? ? ? Usage requires an initial 'probe' to define the serial
> + ? ? ? ? ? ? ? flash parameters, followed by read/write/erase/update
> + ? ? ? ? ? ? ? commands.
> +
> + ? ? ? ? ? ? ? The following defaults may be provided by the platform
> + ? ? ? ? ? ? ? to handle the common case when only a single serial
> + ? ? ? ? ? ? ? flash is present on the system.
> +
> + ? ? ? ? ? ? ? CONFIG_SF_DEFAULT_BUS ? ? ? ? ? Bus identifier
> + ? ? ? ? ? ? ? CONFIG_SF_DEFAULT_CS ? ? ? ? ? ?Chip-select
> + ? ? ? ? ? ? ? CONFIG_SF_DEFAULT_MODE ? ? ? ? ?(see include/spi.h)
> + ? ? ? ? ? ? ? CONFIG_SF_DEFAULT_SPEED ? ? ? ? in Hz
> +
> ?- SystemACE Support:
> ? ? ? ? ? ? ? ?CONFIG_SYSTEMACE
>
> --
> 1.7.1
>

[U-Boot] [PATCH V6 - Part 4 - 1/1] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Jason Hui]

On Wed, Feb 1, 2012 at 1:52 AM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
> Acked-by: Stefano Babic <sbabic@denx.de>
> ---
> ?board/freescale/mx6qsabrelite/mx6qsabrelite.c | ? ?2 +-
> ?include/configs/mx6qsabrelite.h ? ? ? ? ? ? ? | ? ?2 ++
> ?2 files changed, 3 insertions(+), 1 deletions(-)

Acked-by: Jason Liu <jason.hui@linaro.org>

Tested on Sabre-lite board.

Tested-by: Jason Liu <jason.hui@linaro.org>

>
> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> index 97a77e8..03a088a 100644
> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> @@ -208,7 +208,7 @@ iomux_v3_cfg_t ecspi1_pads[] = {
>
> ?void setup_spi(void)
> ?{
> - ? ? ? gpio_direction_output(GPIO_NUMBER(3, 19), 1);
> + ? ? ? gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
> ? ? ? ?imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(ecspi1_pads));
> ?}
> diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
> index bcb1a42..2286bb0 100644
> --- a/include/configs/mx6qsabrelite.h
> +++ b/include/configs/mx6qsabrelite.h
> @@ -49,6 +49,8 @@
> ?#define CONFIG_SPI_FLASH
> ?#define CONFIG_SPI_FLASH_SST
> ?#define CONFIG_MXC_SPI
> +#define CONFIG_SF_DEFAULT_BUS ?0
> +#define CONFIG_SF_DEFAULT_CS ? (0|(GPIO_NUMBER(3, 19)<<8))
> ?#define CONFIG_SF_DEFAULT_SPEED 25000000
> ?#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
> ?#endif
> --
> 1.7.1
>

[U-Boot] [PATCH V6 - Part 5 - 1/1] mx6q: mx6qsabrelite: Conditionally define macros for environment in serial flash

[Jason Hui]

On Wed, Feb 1, 2012 at 1:52 AM, Eric Nelson
<eric.nelson@boundarydevices.com> wrote:
> The default settings store the persistent environment on SD card
> and not serial flash (SPI NOR).
>
> To use SPI NOR to save the environment instead of SD card, edit
> include/configs/mx6qsabrelite.h and
>
> - undefine CONFIG_ENV_IS_IN_MMC
> - define ? CONFIG_ENV_IS_IN_SPI_FLASH
>
> The SPI driver can take as chip select the controller's chip selects
> as well as an external GPIO. The LSB byte has the value of the internal
> chip select, the highest (thought as 16-bit value) contains the GPIO
> number.
>
> The GPIO used on Sabre Lite is GP3:19 == 83.
>
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
>
> ---
> ?include/configs/mx6qsabrelite.h | ? 18 +++++++++++++++---
> ?1 files changed, 15 insertions(+), 3 deletions(-)

Acked-by: Jason Liu <jason.hui@linaro.org>

Tested on Sabre-lite board.

Tested-by: Jason Liu <jason.hui@linaro.org>

>
> diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
> index 2286bb0..c49e3ab 100644
> --- a/include/configs/mx6qsabrelite.h
> +++ b/include/configs/mx6qsabrelite.h
> @@ -174,10 +174,22 @@
> ?/* FLASH and environment organization */
> ?#define CONFIG_SYS_NO_FLASH
>
> -#define CONFIG_ENV_OFFSET ? ? ? ? ? ? ?(6 * 64 * 1024)
> -#define CONFIG_ENV_SIZE ? ? ? ? ? ? ? ? ? ? ? ?(8 * 1024)
> +#define CONFIG_ENV_SIZE ? ? ? ? ? ? ? ? ? ? ? ?(8 * 1024)
> +
> ?#define CONFIG_ENV_IS_IN_MMC
> -#define CONFIG_SYS_MMC_ENV_DEV ? ? ? ? 0
> +/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
> +
> +#if defined(CONFIG_ENV_IS_IN_MMC)
> +#define CONFIG_ENV_OFFSET ? ? ? ? ? ? ?(6 * 64 * 1024)
> +#define CONFIG_SYS_MMC_ENV_DEV ? ? ? ? 0
> +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
> +#define CONFIG_ENV_OFFSET ? ? ? ? ? ? ?(768 * 1024)
> +#define CONFIG_ENV_SECT_SIZE ? ? ? ? ? (8 * 1024)
> +#define CONFIG_ENV_SPI_BUS ? ? ? ? ? ? CONFIG_SF_DEFAULT_BUS
> +#define CONFIG_ENV_SPI_CS ? ? ? ? ? ? ?CONFIG_SF_DEFAULT_CS
> +#define CONFIG_ENV_SPI_MODE ? ? ? ? ? ?CONFIG_SF_DEFAULT_MODE
> +#define CONFIG_ENV_SPI_MAX_HZ ? ? ? ? ?CONFIG_SF_DEFAULT_SPEED
> +#endif
>
> ?#define CONFIG_OF_LIBFDT
>
> --
> 1.7.1
>

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Stefano Babic]

On 31/01/2012 20:14, Eric Nelson wrote:
> On 01/31/2012 11:11 AM, Mike Frysinger wrote:
>> On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:
>>> Patch 1 modifies the 'sf' command to allow a default bus and chip-select
>>> to be specified by board headers. This allows a bare 'sf' probe command:
>>>        U-Boot>  sf probe
>>> instead of the more cumbersome usage when a GPIO is tacked onto
>>> the chip-select. Otherwise, this command-line would be needed
>>> to specify GP3:19 on SabreLite:
>>>        U-Boot>  sf probe 0x5300
>>>
>>> Patch 2 provides a description of usage and configuration of
>>> CONFIG_CMD_SF.
>>
>> you can drop these two SF patches from your mx6q series.  i don't want
>> to keep
>> checking to see if you've updated them :p.
>> -mike
> 
> I figured as much, but I can't really test them without the rest of the
> series...

It does not matter - Mike, what do you think if I merge the whole
patchset into u-boot-imx ? Else the mx6qsabrelite board cannot be built
until all patches will be merged by Wolfgang.

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Dirk Behme]

On 01.02.2012 12:30, Stefano Babic wrote:
> On 31/01/2012 20:14, Eric Nelson wrote:
>> On 01/31/2012 11:11 AM, Mike Frysinger wrote:
>>> On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:
>>>> Patch 1 modifies the 'sf' command to allow a default bus and chip-select
>>>> to be specified by board headers. This allows a bare 'sf' probe command:
>>>>        U-Boot>  sf probe
>>>> instead of the more cumbersome usage when a GPIO is tacked onto
>>>> the chip-select. Otherwise, this command-line would be needed
>>>> to specify GP3:19 on SabreLite:
>>>>        U-Boot>  sf probe 0x5300
>>>>
>>>> Patch 2 provides a description of usage and configuration of
>>>> CONFIG_CMD_SF.
>>> you can drop these two SF patches from your mx6q series.  i don't want
>>> to keep
>>> checking to see if you've updated them :p.
>>> -mike
>> I figured as much, but I can't really test them without the rest of the
>> series...
> 
> It does not matter - Mike, what do you think if I merge the whole
> patchset into u-boot-imx ? Else the mx6qsabrelite board cannot be built
> until all patches will be merged by Wolfgang.

+1

Thanks

Dirk

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Mike Frysinger]

On Wednesday 01 February 2012 06:30:04 Stefano Babic wrote:
> On 31/01/2012 20:14, Eric Nelson wrote:
> > On 01/31/2012 11:11 AM, Mike Frysinger wrote:
> >> On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:
> >>> Patch 1 modifies the 'sf' command to allow a default bus and
> >>> chip-select
> >>> 
> >>> to be specified by board headers. This allows a bare 'sf' probe command:
> >>>        U-Boot>  sf probe
> >>> 
> >>> instead of the more cumbersome usage when a GPIO is tacked onto
> >>> the chip-select. Otherwise, this command-line would be needed
> >>> 
> >>> to specify GP3:19 on SabreLite:
> >>>        U-Boot>  sf probe 0x5300
> >>> 
> >>> Patch 2 provides a description of usage and configuration of
> >>> CONFIG_CMD_SF.
> >> 
> >> you can drop these two SF patches from your mx6q series.  i don't want
> >> to keep
> >> checking to see if you've updated them :p.
> > 
> > I figured as much, but I can't really test them without the rest of the
> > series...
> 
> It does not matter - Mike, what do you think if I merge the whole
> patchset into u-boot-imx ? Else the mx6qsabrelite board cannot be built
> until all patches will be merged by Wolfgang.

i don't see why this series depends on the two spi flash patches.  they were 
both "nice to have" patches which only change the default `sf` behavior.  the 
boards will compile & run perfectly fine without them.
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20120201/5866ffb6/attachment.pgp>

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

On 02/01/2012 10:00 AM, Mike Frysinger wrote:
> On Wednesday 01 February 2012 06:30:04 Stefano Babic wrote:
>> On 31/01/2012 20:14, Eric Nelson wrote:
>>> On 01/31/2012 11:11 AM, Mike Frysinger wrote:
>>>> On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:
>>>>> Patch 1 modifies the 'sf' command to allow a default bus and
>>>>> chip-select
>>>>>
>>>>> to be specified by board headers. This allows a bare 'sf' probe command:
>>>>>         U-Boot>   sf probe
>>>>>
>>>>> instead of the more cumbersome usage when a GPIO is tacked onto
>>>>> the chip-select. Otherwise, this command-line would be needed
>>>>>
>>>>> to specify GP3:19 on SabreLite:
>>>>>         U-Boot>   sf probe 0x5300
>>>>>
>>>>> Patch 2 provides a description of usage and configuration of
>>>>> CONFIG_CMD_SF.
>>>>
>>>> you can drop these two SF patches from your mx6q series.  i don't want
>>>> to keep
>>>> checking to see if you've updated them :p.
>>>
>>> I figured as much, but I can't really test them without the rest of the
>>> series...
>>
>> It does not matter - Mike, what do you think if I merge the whole
>> patchset into u-boot-imx ? Else the mx6qsabrelite board cannot be built
>> until all patches will be merged by Wolfgang.
>
> i don't see why this series depends on the two spi flash patches.  they were
> both "nice to have" patches which only change the default `sf` behavior.  the
> boards will compile&  run perfectly fine without them.
> -mike

Hi Mike,

My comment was the inverse: I can't test just the 'sf probe' updates unless I
have the core SPI flash support for mx6qsabrelite.

AFAIK, the update to cmd_sf doesn't have any dependencies and of course the 
README update doesn't.

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Mike Frysinger]

On Wednesday 01 February 2012 14:31:39 Eric Nelson wrote:
> On 02/01/2012 10:00 AM, Mike Frysinger wrote:
> > On Wednesday 01 February 2012 06:30:04 Stefano Babic wrote:
> >> On 31/01/2012 20:14, Eric Nelson wrote:
> >>> On 01/31/2012 11:11 AM, Mike Frysinger wrote:
> >>>> On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:
> >>>>> Patch 1 modifies the 'sf' command to allow a default bus and
> >>>>> chip-select
> >>>>> 
> >>>>> Patch 2 provides a description of usage and configuration of
> >>>>> CONFIG_CMD_SF.
> >>>> 
> >>>> you can drop these two SF patches from your mx6q series.  i don't want
> >>>> to keep checking to see if you've updated them :p.
> >>> 
> >>> I figured as much, but I can't really test them without the rest of the
> >>> series...
> >> 
> >> It does not matter - Mike, what do you think if I merge the whole
> >> patchset into u-boot-imx ? Else the mx6qsabrelite board cannot be built
> >> until all patches will be merged by Wolfgang.
> > 
> > i don't see why this series depends on the two spi flash patches.  they
> > were both "nice to have" patches which only change the default `sf`
> > behavior.  the boards will compile&  run perfectly fine without them.
> 
> My comment was the inverse: I can't test just the 'sf probe' updates unless
> I have the core SPI flash support for mx6qsabrelite.
> 
> AFAIK, the update to cmd_sf doesn't have any dependencies and of course the
> README update doesn't.

i don't see any dependencies in either direction.  i can push the sf updates 
before or after your board patchset.  in either case, the build will produce a 
u-boot that's just as usable.
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20120201/4e3371a9/attachment.pgp>

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Stefano Babic]

On 01/02/2012 20:31, Eric Nelson wrote:

> Hi Mike,
> 
> My comment was the inverse: I can't test just the 'sf probe' updates
> unless I
> have the core SPI flash support for mx6qsabrelite.
> 
> AFAIK, the update to cmd_sf doesn't have any dependencies and of course
> the README update doesn't.

Then I think the best way is to proceed is as suggested by Mike - the
patches are orthogonal, and they can applied to different trees - and
merged together at the end by Wolfgang.

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Eric Nelson]

On 02/02/2012 02:18 AM, Stefano Babic wrote:
> On 01/02/2012 20:31, Eric Nelson wrote:
>
>> Hi Mike,
>>
>> My comment was the inverse: I can't test just the 'sf probe' updates
>> unless I
>> have the core SPI flash support for mx6qsabrelite.
>>
>> AFAIK, the update to cmd_sf doesn't have any dependencies and of course
>> the README update doesn't.
>
> Then I think the best way is to proceed is as suggested by Mike - the
> patches are orthogonal, and they can applied to different trees - and
> merged together at the end by Wolfgang.
>
> Stefano
>

Okay. I'll leave the process stuff in your capable hands.

Mine is just to code... (or so I like to think)

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Mike Frysinger]

On Thursday 02 February 2012 04:18:45 Stefano Babic wrote:
> On 01/02/2012 20:31, Eric Nelson wrote:
> > My comment was the inverse: I can't test just the 'sf probe' updates
> > unless I have the core SPI flash support for mx6qsabrelite.
> > 
> > AFAIK, the update to cmd_sf doesn't have any dependencies and of course
> > the README update doesn't.
> 
> Then I think the best way is to proceed is as suggested by Mike - the
> patches are orthogonal, and they can applied to different trees - and
> merged together at the end by Wolfgang.

to be clear, i'm not trying to "hoard" patches or anything ... i just can't 
see there being a hard requirement here between the two sets.  if people 
*really* want to merge patches for me, i don't mind ;).
-mike
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part.
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20120202/b468ffe2/attachment.pgp>

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Stefano Babic]

On 02/02/2012 17:32, Mike Frysinger wrote:

> to be clear, i'm not trying to "hoard" patches or anything ...

Do not worry, I have never thought this... ;-)

> i just can't see there being a hard requirement here between the
> two sets.

Agree, and the patches should be merged by the maintainer responsible
for the changes, as general rule - or IMHO as exception by a single
maintainer if the patches break some boards. But agree we should stick
with the general rule when there is no issues, as in this case.

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH V6 - Part 2 - 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform

[Stefano Babic]

On 31/01/2012 18:52, Eric Nelson wrote:
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
> Acked-by: Stefano Babic <sbabic@denx.de>
> ---
Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH V6 - Part 5 - 1/1] mx6q: mx6qsabrelite: Conditionally define macros for environment in serial flash

[Stefano Babic]

On 31/01/2012 18:52, Eric Nelson wrote:
> The default settings store the persistent environment on SD card
> and not serial flash (SPI NOR).
> 
> To use SPI NOR to save the environment instead of SD card, edit
> include/configs/mx6qsabrelite.h and
> 
> - undefine CONFIG_ENV_IS_IN_MMC
> - define   CONFIG_ENV_IS_IN_SPI_FLASH
> 
> The SPI driver can take as chip select the controller's chip selects
> as well as an external GPIO. The LSB byte has the value of the internal
> chip select, the highest (thought as 16-bit value) contains the GPIO
> number.
> 
> The GPIO used on Sabre Lite is GP3:19 == 83.
> 
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> 
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH V6 - Part 4 - 1/1] mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select

[Stefano Babic]

On 31/01/2012 18:52, Eric Nelson wrote:
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
> Acked-by: Stefano Babic <sbabic@denx.de>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH V6 - Part 1 - 1/1] mx6q: define GPIO macros for translating between ordinals and port:index

[Stefano Babic]

On 31/01/2012 18:52, Eric Nelson wrote:
> The interface to the mxc_gpio driver uses integer (ordinal) values to
> refer to all GPIOs on the i.MX processors. The registers themselves
> and much of the i.MX documentation are banked in groups of 32, and these
> macros allow the use of the port:index numbering for clarity.
> 
> GPIO_NUMBER() converts to ordinal value from port:index
> GPIO_PORT() returns the port of an ordinal value
> GPIO_INDEX() returns the index or offset of the ordinal.
> 
> Discussion on the mailing list at
> 	http://lists.denx.de/pipermail/u-boot/2012-January/116927.html
> 
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH V6 - Part 2 - 1/3] mxc_spi: move machine specifics into CPU headers

[Stefano Babic]

On 31/01/2012 18:52, Eric Nelson wrote:
> Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU
> 
> Introduce two new macros to control conditional setup
>      MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x)
>      MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)
> 
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
> Acked-by: Stefano Babic <sbabic@denx.de>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH V6 - Part 2 - 2/3] mx6q: Add support for ECSPI through mxc_spi driver

[Stefano Babic]

On 31/01/2012 18:52, Eric Nelson wrote:
> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
> Acked-by: Stefano Babic <sbabic@denx.de>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects

[Dirk Behme]

On 31.01.2012 19:11, Mike Frysinger wrote:
> On Tuesday 31 January 2012 12:52:06 Eric Nelson wrote:
>> Patch 1 modifies the 'sf' command to allow a default bus and chip-select
>> to be specified by board headers. This allows a bare 'sf' probe command:
>>       U-Boot> sf probe
>> instead of the more cumbersome usage when a GPIO is tacked onto
>> the chip-select. Otherwise, this command-line would be needed
>> to specify GP3:19 on SabreLite:
>>       U-Boot> sf probe 0x5300
>>
>> Patch 2 provides a description of usage and configuration of CONFIG_CMD_SF.
> 
> you can drop these two SF patches from your mx6q series.  i don't want to keep 
> checking to see if you've updated them :p.

Now that part 1, 2, 4 and 5 are merged by Stefano to u-boot-imx.git, 
could we get the two part 3 patches merged, too?

Many thanks and best regards

Dirk