[PATCH 0/8] interlaced support v2

[PATCH 0/8] interlaced support v2

[Daniel Vetter]

Hi all,

These are the patches I'd like to queue to -next for interlaced support. Needs
the patch "fixup interlaced bits clearing in PIPECONF on PCH_SPLIT" and also the
drm core fix "drm/modes: do not enforce an odd vtotal for interlaced modes" if
you want to use interlaced modelines with an even vtotal.

The entire series is available in my interlaced branch at

http://cgit.freedesktop.org/~danvet/drm/log/?h=interlaced

Review, comments and testing highly welcome.

Yours, Daniel

Daniel Vetter (6):
  drm/i915: clean up interlaced pipeconf bit definitions
  drm/i915: fixup interlaced vertical timings confusion, part 1
  drm/i915: fixup interlaced vertical timings confusion, part 2
  drm/i915: fixup interlaced support on ilk+
  drm/i915: don't allow interlaced pipeconf on gen2
  drm/i915: correctly program the VSYNCSHIFT register

Peter Ross (2):
  drm/i915: allow interlaced mode output on the SDVO connector
  drm/i915: allow interlaced mode output on the HDMI connector

 drivers/gpu/drm/i915/i915_reg.h      |   25 +++++++++++++++++++--
 drivers/gpu/drm/i915/intel_crt.c     |    5 +++-
 drivers/gpu/drm/i915/intel_display.c |   39 ++++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_dvo.c     |    1 -
 drivers/gpu/drm/i915/intel_hdmi.c    |    2 +-
 drivers/gpu/drm/i915/intel_overlay.c |    2 +-
 drivers/gpu/drm/i915/intel_panel.c   |    2 +-
 drivers/gpu/drm/i915/intel_sdvo.c    |    3 +-
 drivers/gpu/drm/i915/intel_tv.c      |    2 +-
 9 files changed, 52 insertions(+), 29 deletions(-)

-- 
1.7.7.5

[PATCH 1/8] drm/i915: clean up interlaced pipeconf bit definitions

[Daniel Vetter]

- Clarify which bits are for which chips.
- Note that gen2 can't do interlaced directly (only via dvo tv chips).
- Move the mask to the top to make it clearer how wide this field is.
- Add defintions for all possible values.

This patch doesn't change any code.

v2: Paulo Zanoni pointed out that the pixel doubling modes do no
longer exist on ivb.

Cc: Peter Ross <pross@xvid.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h |   17 ++++++++++++++---
 1 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3afb78..58f0cec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2319,10 +2319,21 @@
 #define   PIPECONF_PALETTE	0
 #define   PIPECONF_GAMMA		(1<<24)
 #define   PIPECONF_FORCE_BORDER	(1<<25)
-#define   PIPECONF_PROGRESSIVE	(0 << 21)
-#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
-#define   PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
 #define   PIPECONF_INTERLACE_MASK	(7 << 21)
+/* Note that pre-gen3 does not support interlaced display directly. Panel
+ * fitting must be disabled on pre-ilk for interlaced. */
+#define   PIPECONF_PROGRESSIVE			(0 << 21)
+#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
+#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
+#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
+#define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
+/* Ironlake and later have a complete new set of values for interlaced. PFIT
+ * means panel fitter required, PF means progressive fetch, DBL means power
+ * saving pixel doubling. */
+#define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
+#define   PIPECONF_INTERLACED_ILK		(3 << 21)
+#define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
+#define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
 #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
 #define   PIPECONF_BPP_MASK	(0x000000e0)
 #define   PIPECONF_BPP_8	(0<<5)
-- 
1.7.7.5

[PATCH 2/8] drm/i915: fixup interlaced vertical timings confusion, part 1

[Daniel Vetter]

We have a pretty decent confusion about vertical timings of interlaced
modes. Peter Ross has written a patch that makes interlace modes work
on a lot more platforms/output combinations by doubling the vertical
timings.

The issue with that patch is that core drm _does_ support specifying
whether we want these vertical timings in fields or frames, we just
haven't managed to consistently use this facility. The relavant
function is drm_mode_set_crtcinfo, which fills in the crtc timing
information.

The first thing to note is that the drm core keeps interlaced modes in
frames, but displays modelines in fields. So when the crtc modeset
helper copies over the mode into adjusted_mode it will already contain
vertical timings in half-frames. The result is that the fixup code in
intel_crtc_mode_fixup doesn't actually do anything (in most cases at
least).

Now gen3+ natively supports interlaced modes and wants the vertical
timings in frames. Which is what sdvo already fixes up, at least under
some conditions.

There are a few other place that demand vertical timings in fields
but never actually deal with interlaced modes, so use frame timings
for consistency, too. These are:
- lvds panel,
- dvo encoders - dvo is the only way gen2 could support interlaced
  mode, but currently we don't support any encoders that do.
- tv out - despite that the tv dac sends out an interlaced signal it
  expects a progressive mode pipe configuration.
All these encoders enforce progressive modes by resetting
interlace_allowed.

Hence we always want crtc vertical timings in frames. Enforce this in
our crtc mode_fixup function and rip out any redudant timing
computations from the encoders' mode_fixup function.

v2-4: Adjust the vertical timings a bit.

v5: Split out the 'subtract-one for interlaced' fixes.

v6: Clarify issues around tv-out and gen2.

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c |    7 ++-----
 drivers/gpu/drm/i915/intel_dvo.c     |    1 -
 drivers/gpu/drm/i915/intel_overlay.c |    2 +-
 drivers/gpu/drm/i915/intel_panel.c   |    2 +-
 drivers/gpu/drm/i915/intel_sdvo.c    |    1 -
 drivers/gpu/drm/i915/intel_tv.c      |    2 +-
 6 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index de26748..3af13ac 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3425,11 +3425,8 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
 			return false;
 	}
 
-	/* XXX some encoders set the crtcinfo, others don't.
-	 * Obviously we need some form of conflict resolution here...
-	 */
-	if (adjusted_mode->crtc_htotal == 0)
-		drm_mode_set_crtcinfo(adjusted_mode, 0);
+	/* All interlaced capable intel hw wants timings in frames. */
+	drm_mode_set_crtcinfo(adjusted_mode, 0);
 
 	return true;
 }
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 6eda1b5..020a7d7 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -157,7 +157,6 @@ static bool intel_dvo_mode_fixup(struct drm_encoder *encoder,
 		C(vsync_end);
 		C(vtotal);
 		C(clock);
-		drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
 #undef C
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index cdf17d4..aac74ec 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -263,7 +263,7 @@ i830_activate_pipe_a(struct drm_device *dev)
 	DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
 
 	mode = drm_mode_duplicate(dev, &vesa_640x480);
-	drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
+	drm_mode_set_crtcinfo(mode, 0);
 	if (!drm_crtc_helper_set_mode(&crtc->base, mode,
 				       crtc->base.x, crtc->base.y,
 				       crtc->base.fb))
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c935cda..230a141 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -48,7 +48,7 @@ intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
 
 	adjusted_mode->clock = fixed_mode->clock;
 
-	drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
+	drm_mode_set_crtcinfo(adjusted_mode, 0);
 }
 
 /* adjusted_mode has been preset to be the panel's fixed mode */
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index e334ec3..5b480bb 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -944,7 +944,6 @@ intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
 
 	intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
 
-	drm_mode_set_crtcinfo(adjusted_mode, 0);
 	return true;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 1571be3..05f765e 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1240,7 +1240,7 @@ intel_tv_detect(struct drm_connector *connector, bool force)
 	int type;
 
 	mode = reported_modes[0];
-	drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V);
+	drm_mode_set_crtcinfo(&mode, 0);
 
 	if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) {
 		type = intel_tv_detect_type(intel_tv, connector);
-- 
1.7.7.5

[PATCH 3/8] drm/i915: fixup interlaced vertical timings confusion, part 2

[Daniel Vetter]

According to bspec, we need to subtract an additional line from vtotal
for interlaced modes and vblank_end needs to equal vtotal. All other
timing fields do not need this special treatment, so kill it.

Bspec says that this is irrespective of whether the interlaced mode
has an odd or even vtotal, both modes are supported.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c |    8 --------
 1 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3af13ac..d108146 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5366,12 +5366,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
 		/* the chip adds 2 halflines automatically */
-		adjusted_mode->crtc_vdisplay -= 1;
 		adjusted_mode->crtc_vtotal -= 1;
-		adjusted_mode->crtc_vblank_start -= 1;
 		adjusted_mode->crtc_vblank_end -= 1;
-		adjusted_mode->crtc_vsync_end -= 1;
-		adjusted_mode->crtc_vsync_start -= 1;
 	} else
 		pipeconf |= PIPECONF_PROGRESSIVE;
 
@@ -5959,12 +5955,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
 		/* the chip adds 2 halflines automatically */
-		adjusted_mode->crtc_vdisplay -= 1;
 		adjusted_mode->crtc_vtotal -= 1;
-		adjusted_mode->crtc_vblank_start -= 1;
 		adjusted_mode->crtc_vblank_end -= 1;
-		adjusted_mode->crtc_vsync_end -= 1;
-		adjusted_mode->crtc_vsync_start -= 1;
 	} else
 		pipeconf |= PIPECONF_PROGRESSIVE;
 
-- 
1.7.7.5

[PATCH 4/8] drm/i915: fixup interlaced support on ilk+

[Daniel Vetter]

According to Paulo Zanoni, this is what windows does.

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d108146..e7c9154 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5953,7 +5953,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 
 	pipeconf &= ~PIPECONF_INTERLACE_MASK;
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
-		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+		pipeconf |= PIPECONF_INTERLACED_ILK;
 		/* the chip adds 2 halflines automatically */
 		adjusted_mode->crtc_vtotal -= 1;
 		adjusted_mode->crtc_vblank_end -= 1;
-- 
1.7.7.5

[PATCH 5/8] drm/i915: don't allow interlaced pipeconf on gen2

[Daniel Vetter]

gen2 doesn't support it, so be a bit more paranoid and add a check to
ensure that we never ever set an unsupported interlaced bit.

Ensure that userspace can't set an interlaced mode by resetting
interlace_allowed for the crt on gen2. dvo and lvds are the only other
encoders that gen2 supports and these already disallow interlaced
modes.

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c     |    5 ++++-
 drivers/gpu/drm/i915/intel_display.c |    3 ++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index dd729d4..4d3d736 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -594,7 +594,10 @@ void intel_crt_init(struct drm_device *dev)
 				1 << INTEL_ANALOG_CLONE_BIT |
 				1 << INTEL_SDVO_LVDS_CLONE_BIT);
 	crt->base.crtc_mask = (1 << 0) | (1 << 1);
-	connector->interlace_allowed = 1;
+	if (IS_GEN2(dev))
+		connector->interlace_allowed = 0;
+	else
+		connector->interlace_allowed = 1;
 	connector->doublescan_allowed = 0;
 
 	drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e7c9154..dc80842 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5363,7 +5363,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	}
 
 	pipeconf &= ~PIPECONF_INTERLACE_MASK;
-	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+	if (!IS_GEN2(dev) &&
+	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
 		/* the chip adds 2 halflines automatically */
 		adjusted_mode->crtc_vtotal -= 1;
-- 
1.7.7.5

[PATCH 6/8] drm/i915: correctly program the VSYNCSHIFT register

[Daniel Vetter]

The hw seems to use this to correctly insert the required delay
before/after an even/odd interlaced field. This might also explain
why we need to substract 1 half-line from vtotal - if the hw just
adds the delay programmend in VSYNCSHIFT the total frame time would be
about that too long.

These registers seems to only exist on gen4 and later. For paranoia
also program it to 0 for progressive modes, but according to
documentation the hw should just ignore it in this case.

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h      |    8 ++++++++
 drivers/gpu/drm/i915/intel_display.c |   19 ++++++++++++++++---
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58f0cec..bcd5cce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1316,6 +1316,7 @@
 #define _VSYNC_A		0x60014
 #define _PIPEASRC	0x6001c
 #define _BCLRPAT_A	0x60020
+#define _VSYNCSHIFT_A	0x60028
 
 /* Pipe B timing regs */
 #define _HTOTAL_B	0x61000
@@ -1326,6 +1327,8 @@
 #define _VSYNC_B		0x61014
 #define _PIPEBSRC	0x6101c
 #define _BCLRPAT_B	0x61020
+#define _VSYNCSHIFT_B	0x61028
+
 
 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
@@ -1334,6 +1337,7 @@
 #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
 #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
+#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
 
 /* VGA port control */
 #define ADPA			0x61100
@@ -3216,6 +3220,7 @@
 #define _TRANS_VSYNC_A           0xe0014
 #define  TRANS_VSYNC_END_SHIFT  16
 #define  TRANS_VSYNC_START_SHIFT 0
+#define _TRANS_VSYNCSHIFT_A	0xe0028
 
 #define _TRANSA_DATA_M1          0xe0030
 #define _TRANSA_DATA_N1          0xe0034
@@ -3246,6 +3251,7 @@
 #define _TRANS_VTOTAL_B          0xe100c
 #define _TRANS_VBLANK_B          0xe1010
 #define _TRANS_VSYNC_B           0xe1014
+#define _TRANS_VSYNCSHIFT_B	 0xe1028
 
 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
@@ -3253,6 +3259,8 @@
 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
+#define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
+				     _TRANS_VSYNCSHIFT_B)
 
 #define _TRANSB_DATA_M1          0xe1030
 #define _TRANSB_DATA_N1          0xe1034
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dc80842..e842961 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2961,6 +2961,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
 	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
 	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
+	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
 
 	intel_fdi_normal_train(crtc);
 
@@ -5081,7 +5082,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	int plane = intel_crtc->plane;
 	int refclk, num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
-	u32 dpll, dspcntr, pipeconf;
+	u32 dpll, dspcntr, pipeconf, vsyncshift;
 	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
 	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
 	struct drm_mode_config *mode_config = &dev->mode_config;
@@ -5369,8 +5370,15 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		/* the chip adds 2 halflines automatically */
 		adjusted_mode->crtc_vtotal -= 1;
 		adjusted_mode->crtc_vblank_end -= 1;
-	} else
+		vsyncshift = adjusted_mode->crtc_hsync_start
+			     - adjusted_mode->crtc_htotal/2;
+	} else {
 		pipeconf |= PIPECONF_PROGRESSIVE;
+		vsyncshift = 0;
+	}
+
+	if (!IS_GEN3(dev))
+		I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
 
 	I915_WRITE(HTOTAL(pipe),
 		   (adjusted_mode->crtc_hdisplay - 1) |
@@ -5958,8 +5966,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		/* the chip adds 2 halflines automatically */
 		adjusted_mode->crtc_vtotal -= 1;
 		adjusted_mode->crtc_vblank_end -= 1;
-	} else
+		I915_WRITE(VSYNCSHIFT(pipe),
+			   adjusted_mode->crtc_hsync_start
+			   - adjusted_mode->crtc_htotal/2);
+	} else {
 		pipeconf |= PIPECONF_PROGRESSIVE;
+		I915_WRITE(VSYNCSHIFT(pipe), 0);
+	}
 
 	I915_WRITE(HTOTAL(pipe),
 		   (adjusted_mode->crtc_hdisplay - 1) |
-- 
1.7.7.5

[PATCH 7/8] drm/i915: allow interlaced mode output on the SDVO connector

[Daniel Vetter]

From: Peter Ross <pross@xvid.org>

Signed-off-by: Peter Ross <pross@xvid.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_sdvo.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 5b480bb..80fb5da 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1984,7 +1984,7 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
 	drm_connector_helper_add(&connector->base.base,
 				 &intel_sdvo_connector_helper_funcs);
 
-	connector->base.base.interlace_allowed = 0;
+	connector->base.base.interlace_allowed = 1;
 	connector->base.base.doublescan_allowed = 0;
 	connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
 
-- 
1.7.7.5

[PATCH 8/8] drm/i915: allow interlaced mode output on the HDMI connector

[Daniel Vetter]

From: Peter Ross <pross@xvid.org>

Signed-off-by: Peter Ross <pross@xvid.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_hdmi.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 64541f7..086288e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -514,7 +514,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 	intel_encoder->type = INTEL_OUTPUT_HDMI;
 
 	connector->polled = DRM_CONNECTOR_POLL_HPD;
-	connector->interlace_allowed = 0;
+	connector->interlace_allowed = 1;
 	connector->doublescan_allowed = 0;
 	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
-- 
1.7.7.5

Re: [PATCH 0/8] interlaced support v2

[Paulo Zanoni]

Hi

2012/1/28 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Hi all,
>
> http://cgit.freedesktop.org/~danvet/drm/log/?h=interlaced

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

So far, tested on ILK and SNB.

Your series contains 8 patches, but your branch contains 10.
- Patch "drm/i915: fixup interlaced bits clearing in PIPECONF on
PCH_SPLIT" also has my R-B and T-B
- Patch "drm/modes: do not enforce an odd vtotal for interlaced modes"
was only tested on Intel and with modes with odd vtotal. I didn't
check if it breaks the other drivers, so I'm not sure I should give a
R-B.

-- 
Paulo Zanoni

Re: [PATCH 0/8] interlaced support v2

[Daniel Vetter]

On Sat, Jan 28, 2012 at 02:49:18PM +0100, Daniel Vetter wrote:
> Hi all,
> 
> These are the patches I'd like to queue to -next for interlaced support. Needs
> the patch "fixup interlaced bits clearing in PIPECONF on PCH_SPLIT" and also the
> drm core fix "drm/modes: do not enforce an odd vtotal for interlaced modes" if
> you want to use interlaced modelines with an even vtotal.
> 
> The entire series is available in my interlaced branch at
> 
> http://cgit.freedesktop.org/~danvet/drm/log/?h=interlaced
> 
> Review, comments and testing highly welcome.

>From irc:

Tested-by: Christopher Egert <cme3000@gmail.com>

On an i915gm eeepc over the VGA connector: 1080i@50Hz on a TV and
1600x1200@100Hz on a CRT. For him interlaced over VGA is broken on at
least the 3.1 kernel his ubuntu install shipped with.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 0/8] interlaced support v2

[Alfonso Fiore]

On Sat, Jan 28, 2012 at 2:49 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Hi all,
>
> These are the patches I'd like to queue to -next for interlaced support. Needs
> the patch "fixup interlaced bits clearing in PIPECONF on PCH_SPLIT" and also the
> drm core fix "drm/modes: do not enforce an odd vtotal for interlaced modes" if
> you want to use interlaced modelines with an even vtotal.
>
> The entire series is available in my interlaced branch at
>
> http://cgit.freedesktop.org/~danvet/drm/log/?h=interlaced
>
> Review, comments and testing highly welcome.

Tested-by: Alfonso Fiore <alfonso.fiore@gmail.com>

i3 2130 connected to a Philips 32pf9731d over HDMI:
- 1920x1080i@30Hz
- 1280x720p@60Hz
- 1024x768p@60Hz

thanks again,
alfonso

[PATCH] drm/i915: fixup overlay checks for interlaced modes

[Daniel Vetter]

The drm core _really_ likes to frob around with the crtc timings and
put halfed vertical timings (in fields) in there. Which confuses the
overlay code, resulting in it's refusal to display anything at the
lower half of an interlaced pipe.

Tested-by: Christopher Egert <cme3000@gmail.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_overlay.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index cdf17d4..2cb67bf 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -935,10 +935,10 @@ static int check_overlay_dst(struct intel_overlay *overlay,
 {
 	struct drm_display_mode *mode = &overlay->crtc->base.mode;
 
-	if (rec->dst_x < mode->crtc_hdisplay &&
-	    rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
-	    rec->dst_y < mode->crtc_vdisplay &&
-	    rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
+	if (rec->dst_x < mode->hdisplay &&
+	    rec->dst_x + rec->dst_width <= mode->hdisplay &&
+	    rec->dst_y < mode->vdisplay &&
+	    rec->dst_y + rec->dst_height <= mode->vdisplay)
 		return 0;
 	else
 		return -EINVAL;
-- 
1.7.8.3

Re: [PATCH 1/8] drm/i915: clean up interlaced pipeconf bit definitions

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 690 bytes --]

On Sat, Jan 28, 2012 at 11:49, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> +#define   PIPECONF_PROGRESSIVE                 (0 << 21)
> +#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL        (4 << 21) /* gen4
> only */
> +#define   PIPECONF_INTERLACE_W_SYNC_SHIFT      (5 << 21) /* gen4 only */
> +#define   PIPECONF_INTERLACE_W_FIELD_INDICATION        (6 << 21)
> +#define   PIPECONF_INTERLACE_FIELD_0_ONLY      (7 << 21) /* gen3 only */
>

<bikeshedding>
As you are touching this code, perhaps you could align the
tabification/spacing as well?
</bikeshedding>

Other than that,
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
Eugeni Dodonov
 <http://eugeni.dodonov.net/>

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Re: [PATCH 2/8] drm/i915: fixup interlaced vertical timings confusion, part 1

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 2164 bytes --]

On Sat, Jan 28, 2012 at 11:49, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> We have a pretty decent confusion about vertical timings of interlaced
> modes. Peter Ross has written a patch that makes interlace modes work
> on a lot more platforms/output combinations by doubling the vertical
> timings.
>
> The issue with that patch is that core drm _does_ support specifying
> whether we want these vertical timings in fields or frames, we just
> haven't managed to consistently use this facility. The relavant
> function is drm_mode_set_crtcinfo, which fills in the crtc timing
> information.
>
> The first thing to note is that the drm core keeps interlaced modes in
> frames, but displays modelines in fields. So when the crtc modeset
> helper copies over the mode into adjusted_mode it will already contain
> vertical timings in half-frames. The result is that the fixup code in
> intel_crtc_mode_fixup doesn't actually do anything (in most cases at
> least).
>
> Now gen3+ natively supports interlaced modes and wants the vertical
> timings in frames. Which is what sdvo already fixes up, at least under
> some conditions.
>
> There are a few other place that demand vertical timings in fields
> but never actually deal with interlaced modes, so use frame timings
> for consistency, too. These are:
> - lvds panel,
> - dvo encoders - dvo is the only way gen2 could support interlaced
>  mode, but currently we don't support any encoders that do.
> - tv out - despite that the tv dac sends out an interlaced signal it
>  expects a progressive mode pipe configuration.
> All these encoders enforce progressive modes by resetting
> interlace_allowed.
>
> Hence we always want crtc vertical timings in frames. Enforce this in
> our crtc mode_fixup function and rip out any redudant timing
> computations from the encoders' mode_fixup function.
>
> v2-4: Adjust the vertical timings a bit.
>
> v5: Split out the 'subtract-one for interlaced' fixes.
>
> v6: Clarify issues around tv-out and gen2.
>
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 3/8] drm/i915: fixup interlaced vertical timings confusion, part 2

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 578 bytes --]

On Sat, Jan 28, 2012 at 11:49, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> According to bspec, we need to subtract an additional line from vtotal
> for interlaced modes and vblank_end needs to equal vtotal. All other
> timing fields do not need this special treatment, so kill it.
>
> Bspec says that this is irrespective of whether the interlaced mode
> has an odd or even vtotal, both modes are supported.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 1/8] drm/i915: clean up interlaced pipeconf bit definitions

[Daniel Vetter]

On Sun, Jan 29, 2012 at 12:09:05PM -0200, Eugeni Dodonov wrote:
> On Sat, Jan 28, 2012 at 11:49, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> 
> > +#define   PIPECONF_PROGRESSIVE                 (0 << 21)
> > +#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL        (4 << 21) /* gen4
> > only */
> > +#define   PIPECONF_INTERLACE_W_SYNC_SHIFT      (5 << 21) /* gen4 only */
> > +#define   PIPECONF_INTERLACE_W_FIELD_INDICATION        (6 << 21)
> > +#define   PIPECONF_INTERLACE_FIELD_0_ONLY      (7 << 21) /* gen3 only */
> >
> 
> <bikeshedding>
> As you are touching this code, perhaps you could align the
> tabification/spacing as well?
> </bikeshedding>

I've aligned them, unfortunately the additional +/- in the diff creates
havoc if the tab is only one space wide in the real file ;-)
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 5/8] drm/i915: don't allow interlaced pipeconf on gen2

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 596 bytes --]

On Sat, Jan 28, 2012 at 11:49, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> gen2 doesn't support it, so be a bit more paranoid and add a check to
> ensure that we never ever set an unsupported interlaced bit.
>
> Ensure that userspace can't set an interlaced mode by resetting
> interlace_allowed for the crt on gen2. dvo and lvds are the only other
> encoders that gen2 supports and these already disallow interlaced
> modes.
>
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 7/8] drm/i915: allow interlaced mode output on the SDVO connector

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 324 bytes --]

On Sat, Jan 28, 2012 at 11:49, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> From: Peter Ross <pross@xvid.org>
>
> Signed-off-by: Peter Ross <pross@xvid.org>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 8/8] drm/i915: allow interlaced mode output on the HDMI connector

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 324 bytes --]

On Sat, Jan 28, 2012 at 11:49, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> From: Peter Ross <pross@xvid.org>
>
> Signed-off-by: Peter Ross <pross@xvid.org>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 0/8] interlaced support v2

[Alfonso Fiore]

On Sat, Jan 28, 2012 at 7:30 PM, Alfonso Fiore <alfonso.fiore@gmail.com> wrote:
>
> i3 2130 connected to a Philips 32pf9731d over HDMI:
> - 1920x1080i@30Hz
> - 1280x720p@60Hz
> - 1024x768p@60Hz

Hi guys,

after grub, the TV switches to 1920x1080i. Even if I add vga=0x037b to
grub menu entry, I get 1280x720p while loading services (I don't use
"quiet splash") but then it goes back to 1920x1080i. Since everything
else is 1280x720p (LightDM login and the desktop) I'd prefer to not
keep switching resolution during boot.

Is there a way?

Thank you,
alfonso

Re: [PATCH 0/8] interlaced support v2

[Angela Schmid]

Hello Daniel

I also want to confirm that interlacing is working over HDMI with 1920x1080i@50hz for Sandy Bridge 2600k. Thanks a lot.

The fixes are not part of the intel gfx driver, correct ?
When will it be pushed and to which kernel release will it presumably be addressed to.

Angela


> -----Original Message-----
> From: intel-gfx-bounces+angela.schmid=wolke7.net@lists.freedesktop.org [mailto:intel-gfx-
> bounces+angela.schmid=wolke7.net@lists.freedesktop.org] On Behalf Of Alfonso Fiore
> Sent: 28 January 2012 19:30
> To: Daniel Vetter
> Cc: Intel Graphics Development
> Subject: Re: [Intel-gfx] [PATCH 0/8] interlaced support v2
> 
> On Sat, Jan 28, 2012 at 2:49 PM, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > Hi all,
> >
> > These are the patches I'd like to queue to -next for interlaced support. Needs
> > the patch "fixup interlaced bits clearing in PIPECONF on PCH_SPLIT" and also the
> > drm core fix "drm/modes: do not enforce an odd vtotal for interlaced modes" if
> > you want to use interlaced modelines with an even vtotal.
> >
> > The entire series is available in my interlaced branch at
> >
> > http://cgit.freedesktop.org/~danvet/drm/log/?h=interlaced
> >
> > Review, comments and testing highly welcome.
> 
> Tested-by: Alfonso Fiore <alfonso.fiore@gmail.com>
> 
> i3 2130 connected to a Philips 32pf9731d over HDMI:
> - 1920x1080i@30Hz
> - 1280x720p@60Hz
> - 1024x768p@60Hz
> 
> thanks again,
> alfonso
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/8] interlaced support v2

[Daniel Vetter]

On Wed, Feb 01, 2012 at 11:18:48PM +0100, Angela Schmid wrote:
> Hello Daniel
> 
> I also want to confirm that interlacing is working over HDMI with 1920x1080i@50hz for Sandy Bridge 2600k. Thanks a lot.
> 
> The fixes are not part of the intel gfx driver, correct ?
> When will it be pushed and to which kernel release will it presumably be addressed to.

Correct, this is all kernel work and doesn't required any changes to the X
server or driver. Because it's a new feature, it'll go through next and
should land in linux kernel v3.4, which releases in about half a year or
so.

Thanks a lot for testing.

Yours, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH] drm/i915: fixup overlay checks for interlaced modes

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 619 bytes --]

On Sat, Jan 28, 2012 at 20:48, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> The drm core _really_ likes to frob around with the crtc timings and
> put halfed vertical timings (in fields) in there. Which confuses the
> overlay code, resulting in it's refusal to display anything at the
> lower half of an interlaced pipe.
>
> Tested-by: Christopher Egert <cme3000@gmail.com>
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>

This makes sense, and we have a test-case where it actually solves issues.
So
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH] drm/i915: fixup overlay checks for interlaced modes

[Daniel Vetter]

On Fri, Feb 10, 2012 at 02:42:05PM -0200, Eugeni Dodonov wrote:
> On Sat, Jan 28, 2012 at 20:48, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> 
> > The drm core _really_ likes to frob around with the crtc timings and
> > put halfed vertical timings (in fields) in there. Which confuses the
> > overlay code, resulting in it's refusal to display anything at the
> > lower half of an interlaced pipe.
> >
> > Tested-by: Christopher Egert <cme3000@gmail.com>
> > Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >
> 
> This makes sense, and we have a test-case where it actually solves issues.
> So
> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

Ok, I've slurped this in for -next. Thanks a lot for patches, review,
testing, crawling through docs and digging up register dumps from all over
the place.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48