[PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

This prototype patch extends the sh7372 DT support with actual
IRQ support. The heavy lifting is all done by the prototype patch
 "[PATCH] sh: INTC IRQ domain and DT support prototype".

It is worth noting that we have 3 root interrupt controllers on
sh7372 and to set the parent pointer to NULL we let the device
tree point to itself as interrupt-parent. Seems a bit overly
complex so perhaps it is not the right way forward.

All root interrupt controllers are using IRQ domains but their
allocation is kept the same as the non-DT case to allow us to
leave the demux code as-is without any modifications. So in
the DT case INTCA, IRQ16L and IRQ16H are kept at their original
IRQ positions. INTCS is allocated dynamically in case of DT
and at a fixed location as usual for non-DT boards.

Anyone that wants to play with DT with interrupts on sh7372
will need to include this patch. The INTC IRQ domain patch above
needs further work which will delay the merge.

Not-yet-signed-off-by: Magnus Damm <damm@opensource.se>
---

 Dependencies are:
 [PATCH 00/06] mach-shmobile device tree preparation patches V2
 [PATCH] ARM: mach-shmobile: sh7372 generic board support via DT V2
 [PATCH] sh: INTC IRQ domain and DT support prototype
 
 arch/arm/boot/dts/sh7372.dtsi                |   28 +++++++
 arch/arm/mach-shmobile/include/mach/common.h |    1 
 arch/arm/mach-shmobile/intc-sh7372.c         |   93 ++++++++++++++++++++++++--
 arch/arm/mach-shmobile/setup-sh7372.c        |    2 
 4 files changed, 116 insertions(+), 8 deletions(-)

--- 0008/arch/arm/boot/dts/sh7372.dtsi
+++ work/arch/arm/boot/dts/sh7372.dtsi	2012-03-28 17:35:24.000000000 +0900
@@ -18,4 +18,32 @@
 			compatible = "arm,cortex-a8";
 		};
 	};
+
+	intca: interrupt-controller@0 {
+		compatible = "renesas,intca-sh7372";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	irq16l: interrupt-controller@1 {
+		compatible = "renesas,intca-irq-lo-sh7372";
+		interrupt-parent = <&irq16l>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	irq16h: interrupt-controller@2 {
+		compatible = "renesas,intca-irq-hi-sh7372";
+		interrupt-parent = <&irq16h>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	intcs: interrupt-controller@3 {
+		compatible = "renesas,intcs-sh7372";
+		interrupt-parent = <&intca>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
 };
--- 0002/arch/arm/mach-shmobile/include/mach/common.h
+++ work/arch/arm/mach-shmobile/include/mach/common.h	2012-03-28 17:26:37.000000000 +0900
@@ -35,6 +35,7 @@ extern struct clk sh7377_extalc1_clk;
 extern struct clk sh7377_extal2_clk;
 
 extern void sh7372_init_irq(void);
+extern void sh7372_init_irq_dt(void);
 extern void sh7372_map_io(void);
 extern void sh7372_add_early_devices(void);
 extern void sh7372_add_standard_devices(void);
--- 0007/arch/arm/mach-shmobile/intc-sh7372.c
+++ work/arch/arm/mach-shmobile/intc-sh7372.c	2012-03-28 17:26:37.000000000 +0900
@@ -21,8 +21,11 @@
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
 #include <linux/sh_intc.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 #include <mach/intc.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -551,20 +554,15 @@ static void intcs_demux(unsigned int irq
 static void __iomem *intcs_ffd2;
 static void __iomem *intcs_ffd5;
 
-void __init sh7372_init_irq(void)
+static void __init sh7372_init_intcs(void)
 {
 	void __iomem *intevtsa;
 	int n;
 
+	/* ioremap() to allow suspend/resume */
 	intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
-	intevtsa = intcs_ffd2 + 0x100;
 	intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
 
-	register_intc_controller(&intca_desc);
-	register_intc_controller(&intca_irq_pins_lo_desc);
-	register_intc_controller(&intca_irq_pins_hi_desc);
-	register_intc_controller(&intcs_desc);
-
 	/* setup dummy cascade chip for INTCS */
 	n = evt2irq(0xf80);
 	irq_alloc_desc_at(n, numa_node_id());
@@ -573,6 +571,7 @@ void __init sh7372_init_irq(void)
 	set_irq_flags(n, IRQF_VALID); /* yuck */
 
 	/* demux using INTEVTSA */
+	intevtsa = intcs_ffd2 + 0x100;
 	irq_set_handler_data(n, (void *)intevtsa);
 	irq_set_chained_handler(n, intcs_demux);
 
@@ -580,6 +579,86 @@ void __init sh7372_init_irq(void)
 	iowrite16(0, intcs_ffd2 + 0x104);
 }
 
+#ifdef CONFIG_USE_OF
+
+static int __init intca_of_init(struct device_node *node,
+				struct device_node *parent)
+{
+	return register_intc_controller_dt(&intca_desc, node, parent, NULL);
+}
+
+static int __init irqhi_of_init(struct device_node *node,
+				 struct device_node *parent)
+{
+	return register_intc_controller_dt(&intca_irq_pins_hi_desc,
+					   node, parent, NULL);
+}
+
+static int __init irqlo_of_init(struct device_node *node,
+				 struct device_node *parent)
+{
+	return register_intc_controller_dt(&intca_irq_pins_lo_desc,
+					   node, parent, NULL);
+}
+
+static int intcs_irq_domain_dt_translate(struct irq_domain *d,
+					 struct device_node *controller,
+					 const u32 *intspec,
+					 unsigned int intsize,
+					 unsigned long *out_hwirq,
+					 unsigned int *out_type)
+{
+	if (d->of_node != controller)
+		return -EINVAL;
+
+	if (intsize < 1)
+		return -EINVAL;
+
+	*out_hwirq = intcs_evt2irq(intspec[0]);
+	*out_type = 0;
+	return 0;
+}
+
+const struct irq_domain_ops intcs_irq_domain_ops = {
+	.dt_translate = intcs_irq_domain_dt_translate,
+};
+
+static int __init intcs_of_init(struct device_node *node,
+				struct device_node *parent)
+{
+	int ret = register_intc_controller_dt(&intcs_desc, node, parent,
+					      &intcs_irq_domain_ops);
+	if (!ret)
+		sh7372_init_intcs();
+
+	return ret;
+}
+
+static const struct of_device_id sh7372_intc_of_match[] __initconst = {
+	{ .compatible = "renesas,intca-sh7372", .data = intca_of_init },
+	{ .compatible = "renesas,intca-irq-lo-sh7372", .data = irqlo_of_init },
+	{ .compatible = "renesas,intca-irq-hi-sh7372", .data = irqhi_of_init },
+	{ .compatible = "renesas,intcs-sh7372", .data = intcs_of_init },
+	{},
+};
+
+void __init sh7372_init_irq_dt(void)
+{
+	of_irq_init(sh7372_intc_of_match);
+}
+
+#endif /* CONFIG_USE_OF */
+
+void __init sh7372_init_irq(void)
+{
+	register_intc_controller(&intca_desc);
+	register_intc_controller(&intca_irq_pins_lo_desc);
+	register_intc_controller(&intca_irq_pins_hi_desc);
+
+	sh7372_init_intcs();
+	register_intc_controller(&intcs_desc);
+}
+
 static unsigned short ffd2[0x200];
 static unsigned short ffd5[0x100];
 
--- 0008/arch/arm/mach-shmobile/setup-sh7372.c
+++ work/arch/arm/mach-shmobile/setup-sh7372.c	2012-03-28 17:26:37.000000000 +0900
@@ -1122,7 +1122,7 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7
 	.map_io		= sh7372_map_io,
 	.init_early	= sh7372_add_early_devices_dt,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= sh7372_init_irq,
+	.init_irq	= sh7372_init_irq_dt,
 	.handle_irq	= shmobile_handle_irq_intc,
 	.init_machine	= sh7372_add_standard_devices_dt,
 	.timer		= &shmobile_timer,

Re: [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Arnd Bergmann]

On Wednesday 28 March 2012, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> This prototype patch extends the sh7372 DT support with actual
> IRQ support. The heavy lifting is all done by the prototype patch
>  "[PATCH] sh: INTC IRQ domain and DT support prototype".
> 
> It is worth noting that we have 3 root interrupt controllers on
> sh7372 and to set the parent pointer to NULL we let the device
> tree point to itself as interrupt-parent. Seems a bit overly
> complex so perhaps it is not the right way forward.
> 
> All root interrupt controllers are using IRQ domains but their
> allocation is kept the same as the non-DT case to allow us to
> leave the demux code as-is without any modifications. So in
> the DT case INTCA, IRQ16L and IRQ16H are kept at their original
> IRQ positions. INTCS is allocated dynamically in case of DT
> and at a fixed location as usual for non-DT boards.
> 
> Anyone that wants to play with DT with interrupts on sh7372
> will need to include this patch. The INTC IRQ domain patch above
> needs further work which will delay the merge.
> 
> Not-yet-signed-off-by: Magnus Damm <damm@opensource.se>

Hi Magnus,

I'm trying to find my way through your patches, but I still have
a little trouble figuring out how it all fits together.

My feeling is that the soc specific parts can be done better
if you generalize the interrupt controller bindings so that
you can describe the controller(s) as a single device, and
allow all the information that is now in the intc-*.c files
to be moved into device tree attributes to be parsed at boot
time, or from the translate() function of the interrupt controller
driver.

That feeling may of course be completely wrong. Do you have
a link to a data sheet describing how that controller actually
works, or can you explain what the various arrays are needed
for today, and how the various interrupt controllers you register
fit together?

	Arnd

Re: [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Magnus Damm]

Hello Arnd,

On Wed, Mar 28, 2012 at 10:15 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Wednesday 28 March 2012, Magnus Damm wrote:
>> From: Magnus Damm <damm@opensource.se>
>>
>> This prototype patch extends the sh7372 DT support with actual
>> IRQ support. The heavy lifting is all done by the prototype patch
>>  "[PATCH] sh: INTC IRQ domain and DT support prototype".
>>
>> It is worth noting that we have 3 root interrupt controllers on
>> sh7372 and to set the parent pointer to NULL we let the device
>> tree point to itself as interrupt-parent. Seems a bit overly
>> complex so perhaps it is not the right way forward.
>>
>> All root interrupt controllers are using IRQ domains but their
>> allocation is kept the same as the non-DT case to allow us to
>> leave the demux code as-is without any modifications. So in
>> the DT case INTCA, IRQ16L and IRQ16H are kept at their original
>> IRQ positions. INTCS is allocated dynamically in case of DT
>> and at a fixed location as usual for non-DT boards.
>>
>> Anyone that wants to play with DT with interrupts on sh7372
>> will need to include this patch. The INTC IRQ domain patch above
>> needs further work which will delay the merge.
>>
>> Not-yet-signed-off-by: Magnus Damm <damm@opensource.se>
>
> Hi Magnus,
>
> I'm trying to find my way through your patches, but I still have
> a little trouble figuring out how it all fits together.

Right, sorry for spitting out patches to the left and to the right. =)

So the full dependencies for "base DT support" are:

renesas.git a6e24019468009a21b674e392d74283a90f415dd (origin/master)
[PATCH 00/06] mach-shmobile device tree preparation patches V2
[PATCH] ARM: mach-shmobile: sh7372 generic board support via DT V2

The patches above are rather ready IMO, and they've got Signed-off-by.

To get prototype level support of IRQs you will also need the following:
[PATCH] sh: INTC IRQ domain and DT support prototype
[PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

The two patches above are experimental with Not-yet-signed-off-by.

There are more patches as well, but most depend on the prototype IRQ code above.

> My feeling is that the soc specific parts can be done better
> if you generalize the interrupt controller bindings so that
> you can describe the controller(s) as a single device, and
> allow all the information that is now in the intc-*.c files
> to be moved into device tree attributes to be parsed at boot
> time, or from the translate() function of the interrupt controller
> driver.

For sh7372 and most other of our SoCs I believe it will be difficult
to use a single device for interrupts. This since there are a few
different interrupt controllers working together, and they have
different interrupt ranges associated with them. They fit quite well
with IRQ domains and the ->dt_translate() callback and gluing them
back together would sort of defeat the point with IRQ domains to begin
with. It would also make it more difficult to implement proper power
management.

However, the idea that you'd like to describe the controller with the
device tree is interesting. At this point I'm unsure how to do that.
Also, I do wonder if it makes sense to do so at all - most new parts
use the GIC as the main interrupt controller anyway. I do agree with
the plan of separating configuration from code, and in our INTC case
we've sort of already done so about 5 years ago. At that point I
converted a few separate random implementations to the current table
driven INTC code base. Since then we have soon close to 100 different
users in arch/sh and arch/arm/mach-shmobile. Each is different. Feel
free to grep for "register_intc_controller" to explore by yourself. It
would be fun to try to use the device tree for this, but I wonder how
we can describe anything half-complex without a preprocessor. Both the
INTC code and the PFC used for GPIO and pinmux use C enums a lot.

> That feeling may of course be completely wrong. Do you have
> a link to a data sheet describing how that controller actually
> works, or can you explain what the various arrays are needed
> for today, and how the various interrupt controllers you register
> fit together?

Sorry to say this, but I doubt that there are any public documents for
our ARM based SoCs. Next time we meet face to face perhaps we can
discuss about providing a board and documentation to you?

I'd be happy to try to describe how the INTC code works and how the
sh7372 interrupt controllers are hooked together. Perhaps we can
combine this with a chat for some more interactivity?

Thanks for your help!

Cheers,

/ magnus

Re: [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Arnd Bergmann]

On Thursday 29 March 2012, Magnus Damm wrote:

> > Hi Magnus,
> >
> > I'm trying to find my way through your patches, but I still have
> > a little trouble figuring out how it all fits together.
> 
> Right, sorry for spitting out patches to the left and to the right. =)
> 
> So the full dependencies for "base DT support" are:
> 
> renesas.git a6e24019468009a21b674e392d74283a90f415dd (origin/master)
> [PATCH 00/06] mach-shmobile device tree preparation patches V2
> [PATCH] ARM: mach-shmobile: sh7372 generic board support via DT V2
> 
> The patches above are rather ready IMO, and they've got Signed-off-by.
> 
> To get prototype level support of IRQs you will also need the following:
> [PATCH] sh: INTC IRQ domain and DT support prototype
> [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype
> 
> The two patches above are experimental with Not-yet-signed-off-by.
> 
> There are more patches as well, but most depend on the prototype IRQ code above.

Do you have a public git tree that has all of them applied?
The separate patches are good for reviewing when one already
knows the code, but in trying to get the big picture, I'
prefer to look at the state after the patches.

> > My feeling is that the soc specific parts can be done better
> > if you generalize the interrupt controller bindings so that
> > you can describe the controller(s) as a single device, and
> > allow all the information that is now in the intc-*.c files
> > to be moved into device tree attributes to be parsed at boot
> > time, or from the translate() function of the interrupt controller
> > driver.
> 
> For sh7372 and most other of our SoCs I believe it will be difficult
> to use a single device for interrupts. This since there are a few
> different interrupt controllers working together, and they have
> different interrupt ranges associated with them. They fit quite well
> with IRQ domains and the ->dt_translate() callback and gluing them
> back together would sort of defeat the point with IRQ domains to begin
> with. It would also make it more difficult to implement proper power
> management.

Right. It wasn't clear to what degree they are actually separate bits
of hardware. If the controllers are nested in some way, you should
definitely describe them as individual device nodes.

> However, the idea that you'd like to describe the controller with the
> device tree is interesting. At this point I'm unsure how to do that.
> Also, I do wonder if it makes sense to do so at all - most new parts
> use the GIC as the main interrupt controller anyway. I do agree with
> the plan of separating configuration from code, and in our INTC case
> we've sort of already done so about 5 years ago. At that point I
> converted a few separate random implementations to the current table
> driven INTC code base. Since then we have soon close to 100 different
> users in arch/sh and arch/arm/mach-shmobile. Each is different. Feel
> free to grep for "register_intc_controller" to explore by yourself. It
> would be fun to try to use the device tree for this, but I wonder how
> we can describe anything half-complex without a preprocessor. Both the
> INTC code and the PFC used for GPIO and pinmux use C enums a lot.

Ah, so the vast majority of these are not for shmobile but for arch/sh
and I support you have no plans to move those to DT along with shmobile,
right?

From my reading of the source code, your INTCA and INTCS controllers
all follow the same basic model, but they all differ in the mapping
between interrupt vectors to register locations.

I would probably not try to describe this mapping in the interrupt
controller node, but instead use a more elaborate way to describe
an interrupt than just the vector.

Taking the sh7372 USB0_USB0I0 interrupt as an arbitrary example,
you could encode it as

	interrupts = <0x1ca0	 /* vector */
			0xa4 5	 /* mask register offset and bit position */
			0x4c 1>; /* prio register offset and bit position */

An interrupt controller that only needs these (no sense/ack registers),
would set #interrupt-cells=<5>;, while other interrupt controllers would
use a larger number of interrupt cells to also encode the extra data.

You can also use the interrupt-map to turn these into more readable
numbers for use by the devices.

I don't understand what your interrupt groups are, or whether you need
even more attributes somewhere.

> > That feeling may of course be completely wrong. Do you have
> > a link to a data sheet describing how that controller actually
> > works, or can you explain what the various arrays are needed
> > for today, and how the various interrupt controllers you register
> > fit together?
> 
> Sorry to say this, but I doubt that there are any public documents for
> our ARM based SoCs. Next time we meet face to face perhaps we can
> discuss about providing a board and documentation to you?

Sounds good. I'll be at LinuxCon Japan in June, after the Hong Kong
Linaro Connect.

> I'd be happy to try to describe how the INTC code works and how the
> sh7372 interrupt controllers are hooked together. Perhaps we can
> combine this with a chat for some more interactivity?

Ok, let's try to meet up on IRC on #armlinux on freenode then.

	Arnd

Re: [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Paul Mundt]

On Thu, Mar 29, 2012 at 01:06:38PM +0000, Arnd Bergmann wrote:
> On Thursday 29 March 2012, Magnus Damm wrote:
> > However, the idea that you'd like to describe the controller with the
> > device tree is interesting. At this point I'm unsure how to do that.
> > Also, I do wonder if it makes sense to do so at all - most new parts
> > use the GIC as the main interrupt controller anyway. I do agree with
> > the plan of separating configuration from code, and in our INTC case
> > we've sort of already done so about 5 years ago. At that point I
> > converted a few separate random implementations to the current table
> > driven INTC code base. Since then we have soon close to 100 different
> > users in arch/sh and arch/arm/mach-shmobile. Each is different. Feel
> > free to grep for "register_intc_controller" to explore by yourself. It
> > would be fun to try to use the device tree for this, but I wonder how
> > we can describe anything half-complex without a preprocessor. Both the
> > INTC code and the PFC used for GPIO and pinmux use C enums a lot.
> 
> Ah, so the vast majority of these are not for shmobile but for arch/sh
> and I support you have no plans to move those to DT along with shmobile,
> right?
> 
At the moment the main priority is really just the shared SoC blocks, so
things like the interrupt controllers, serial driver, pfc/pinmux/gpios,
dmaengine, etc. The interrupt controller subystem that we use for all of
our cases is sufficiently complex that it's really not an ideal choice in
terms of low-hanging fruit for DT support, in fact, it's probably the
worst possible place to start.

I'm in the middle of irqdomain refactoring for it now, which will also
entail quite a lot of rework with regards to how we deal with our virtual
IRQs, radix tree utilization, and so forth. What sort of information we
need to still keep around ultimately won't be known until we have a
clearer picture of how the irqdomain tie-in will look for the existing
cases. Only after that does it really make any sense to start on anything
but the most trivial of DT bindings.

Beyond that, while the vast majority of the INTC cases are in arch/sh
today, infrastructure-wise everything is sufficiently coupled together
that it wouldn't make things any simpler to treat INTCA/INTCS specially.

Once we start seeing DT bindings in shared infrastructure (especially
drivers/sh and so on) then I'll probably start gradually migrating
arch/sh users over to it, too. For the majority of users we don't really
have any sort of coherent boot ABI, which means that we're more than
likely going to always have to link the blob in to the kernel directly,
but that's another matter.

The GPIO/PFC pinmux/pinctrl bits are likewise quite complex and in flux
while I work on pinctrl migration (some work done now, but more
realistically after the irqdomain rework has happened), so it's not worth
spending any time on DT bindings there for the moment either.

At the moment pretty much any other platform device is orders of
magnitude more simplistic and workable though. I'm not sure why DT
prototyping didn't start there, instead.

Re: [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Magnus Damm]

Hello Arnd,

On Thu, Mar 29, 2012 at 10:06 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday 29 March 2012, Magnus Damm wrote:
>
>> > Hi Magnus,
>> >
>> > I'm trying to find my way through your patches, but I still have
>> > a little trouble figuring out how it all fits together.
>>
>> Right, sorry for spitting out patches to the left and to the right. =)
>>
>> So the full dependencies for "base DT support" are:
>>
>> renesas.git a6e24019468009a21b674e392d74283a90f415dd (origin/master)
>> [PATCH 00/06] mach-shmobile device tree preparation patches V2
>> [PATCH] ARM: mach-shmobile: sh7372 generic board support via DT V2
>>
>> The patches above are rather ready IMO, and they've got Signed-off-by.
>>
>> To get prototype level support of IRQs you will also need the following:
>> [PATCH] sh: INTC IRQ domain and DT support prototype
>> [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype
>>
>> The two patches above are experimental with Not-yet-signed-off-by.
>>
>> There are more patches as well, but most depend on the prototype IRQ code above.
>
> Do you have a public git tree that has all of them applied?

Sorry, there is no such thing. I believe Rafael will pick up the ones
with Signed-off-by and put them in a branch based on v3.4-rc1. He may
be able to pull in other more experimental patches based on that tree,
but I am somewhat hesitant since I don't want to give people the false
impression that the code is ready when it's certainly not. The
experimental code will change a lot, that's a fact.

> The separate patches are good for reviewing when one already
> knows the code, but in trying to get the big picture, I'
> prefer to look at the state after the patches.

I understand. I suppose the branch created by Rafael will take you
half-way at least.

>> > My feeling is that the soc specific parts can be done better
>> > if you generalize the interrupt controller bindings so that
>> > you can describe the controller(s) as a single device, and
>> > allow all the information that is now in the intc-*.c files
>> > to be moved into device tree attributes to be parsed at boot
>> > time, or from the translate() function of the interrupt controller
>> > driver.
>>
>> For sh7372 and most other of our SoCs I believe it will be difficult
>> to use a single device for interrupts. This since there are a few
>> different interrupt controllers working together, and they have
>> different interrupt ranges associated with them. They fit quite well
>> with IRQ domains and the ->dt_translate() callback and gluing them
>> back together would sort of defeat the point with IRQ domains to begin
>> with. It would also make it more difficult to implement proper power
>> management.
>
> Right. It wasn't clear to what degree they are actually separate bits
> of hardware. If the controllers are nested in some way, you should
> definitely describe them as individual device nodes.

Good!

>> However, the idea that you'd like to describe the controller with the
>> device tree is interesting. At this point I'm unsure how to do that.
>> Also, I do wonder if it makes sense to do so at all - most new parts
>> use the GIC as the main interrupt controller anyway. I do agree with
>> the plan of separating configuration from code, and in our INTC case
>> we've sort of already done so about 5 years ago. At that point I
>> converted a few separate random implementations to the current table
>> driven INTC code base. Since then we have soon close to 100 different
>> users in arch/sh and arch/arm/mach-shmobile. Each is different. Feel
>> free to grep for "register_intc_controller" to explore by yourself. It
>> would be fun to try to use the device tree for this, but I wonder how
>> we can describe anything half-complex without a preprocessor. Both the
>> INTC code and the PFC used for GPIO and pinmux use C enums a lot.
>
> Ah, so the vast majority of these are not for shmobile but for arch/sh
> and I support you have no plans to move those to DT along with shmobile,
> right?

Most use cases are still on SH, but for mach-shmobile we make use of
either GIC of INTCA together with a cascaded INTCS. We also have IRQ
pins that can be controlled from either INTCA or INTCS or just
level/edge trigger configuration in front of GIC. In some cases we
have an interrupt controller called PINT. Some PFC/GPIO controllers
have built-in interrupt controllers, and some GPIOs have their
interrupts tied into the INTC as IRQ pins. There is a big jambalaya of
hardware IP with history from Mitsubishi, Hitachi and NEC, plus the
usual not-so-exotic ones.

So with this in mind I believe we will need INTC support for
mach-shmobile in the future as well. The INTC controllers seem to
become more like leaf nodes these days though. =)

> From my reading of the source code, your INTCA and INTCS controllers
> all follow the same basic model, but they all differ in the mapping
> between interrupt vectors to register locations.

All INTC tables are unique. So the INTCS in sh7372 is not the same as
the INTCS in sh7367. Some parts of the tables may look similar, but
low hanging fruit such as external IRQ pin handling has been broken
out into reusable components already.

> I would probably not try to describe this mapping in the interrupt
> controller node, but instead use a more elaborate way to describe
> an interrupt than just the vector.

That's certainly one way to split out the information, but I wonder if
that's the right way to go. I worry that with such setup the
correctness of the mappings between vectors and register fields is
dependent on the system integrator doing proper copy-paste
"development". One character wrong and you will have a silent error
somewhere with the wrong interrupt being masked by accident for
instance.

> Taking the sh7372 USB0_USB0I0 interrupt as an arbitrary example,
> you could encode it as
>
>        interrupts = <0x1ca0     /* vector */
>                        0xa4 5   /* mask register offset and bit position */
>                        0x4c 1>; /* prio register offset and bit position */
>
> An interrupt controller that only needs these (no sense/ack registers),
> would set #interrupt-cells=<5>;, while other interrupt controllers would
> use a larger number of interrupt cells to also encode the extra data.

Thanks for showing this example. I think your proposal is interesting.
I believe I get the big picture, but I wonder if it is that simple
after all. In this specific example the USB0_USB0I0 interrupt source
also needs a 0xe4 associated with the mask register. Some mask
registers come in pairs with one clear and one set register. We also
have the width of the register and width of the priority field as
data. Of course the actual register mapping with such information
could be kept together with the INTC configuration data for the
interrupt controller, and we can for instance use register offset and
bit field index to locate the actual bit field or bit. This becomes
quite close to how INTC is working today though, with the exception
that we use enums with the same names as the data sheet. I don't see
how this can be done in Device Tree lingo.

If possible I'd like to keep the interrupt tables self-contained in
one place. I don't mind so much if it is kept in C or DT, but I'd like
to keep the same goals as we had with our INTC tables:
- Easy data entry straight from data sheet
- O(1) interrupt handling for timing critical interrupt handling
- Low memory consumption
- Some way to reduce risk of typos (preprocessor in case of C)

> You can also use the interrupt-map to turn these into more readable
> numbers for use by the devices.

Ok, perhaps that will remove the undesired side effects then. If so it
may be a nice idea.

> I don't understand what your interrupt groups are, or whether you need
> even more attributes somewhere.

The groups are used to link together multiple interrupt sources
(enums) that share a priority setting.

Anyway, just to be clear, at this point i mainly wanted to enable DT
support on the mach-shmobile subarch and sh7372 in particular. So in
my mind this excludes reworking the INTC and PFC tables. Such
activities will take quite some time due to them being shared with SH.
Of course we should work in that direction, but at this point I 'd
like to focus on getting other people to work with DT support in the
drivers. So because of that I spent time on getting interrupts going
with the device tree instead of figuring out how to replace the INTC
tables with something else. Step by step.

I assume that your current merge policy is that boards should be
implemented in DT, but we can still merge new SoCs with current style
of INTC and PFC tables as usual?

I hope that's the case, and if not then there is an increased risk of
out of tree SoCs development. This to be able to meet customer demand
on schedule. I'd like to keep the customer bits synchronized with
upstream, and if we can't get things merged due to lacking
dependencies then we will need to rethink how to deal with this.

Thanks for your help with the review. I very much welcome your
comments on the patches with Signed-off-by, and as for the patches
with Not-yet-signed-off-by, please note that they are work in
progress. The IRQ related bits will be reworked and upstreamed by Paul
Mundt. So I see my work in the IRQ department close to done - apart
from chatting with you about it of course.

>> > That feeling may of course be completely wrong. Do you have
>> > a link to a data sheet describing how that controller actually
>> > works, or can you explain what the various arrays are needed
>> > for today, and how the various interrupt controllers you register
>> > fit together?
>>
>> Sorry to say this, but I doubt that there are any public documents for
>> our ARM based SoCs. Next time we meet face to face perhaps we can
>> discuss about providing a board and documentation to you?
>
> Sounds good. I'll be at LinuxCon Japan in June, after the Hong Kong
> Linaro Connect.

Cool, see you then!

>> I'd be happy to try to describe how the INTC code works and how the
>> sh7372 interrupt controllers are hooked together. Perhaps we can
>> combine this with a chat for some more interactivity?
>
> Ok, let's try to meet up on IRC on #armlinux on freenode then.

Good idea. I'll contact you privately to agree on some time that works
with both meeting schedules and time zones.

Thanks,

/ magnus

Re: [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Magnus Damm]

On Fri, Mar 30, 2012 at 1:01 PM, Paul Mundt <lethal@linux-sh.org> wrote:
> On Thu, Mar 29, 2012 at 01:06:38PM +0000, Arnd Bergmann wrote:
>> On Thursday 29 March 2012, Magnus Damm wrote:
>> > However, the idea that you'd like to describe the controller with the
>> > device tree is interesting. At this point I'm unsure how to do that.
>> > Also, I do wonder if it makes sense to do so at all - most new parts
>> > use the GIC as the main interrupt controller anyway. I do agree with
>> > the plan of separating configuration from code, and in our INTC case
>> > we've sort of already done so about 5 years ago. At that point I
>> > converted a few separate random implementations to the current table
>> > driven INTC code base. Since then we have soon close to 100 different
>> > users in arch/sh and arch/arm/mach-shmobile. Each is different. Feel
>> > free to grep for "register_intc_controller" to explore by yourself. It
>> > would be fun to try to use the device tree for this, but I wonder how
>> > we can describe anything half-complex without a preprocessor. Both the
>> > INTC code and the PFC used for GPIO and pinmux use C enums a lot.
>>
>> Ah, so the vast majority of these are not for shmobile but for arch/sh
>> and I support you have no plans to move those to DT along with shmobile,
>> right?
>>
> At the moment the main priority is really just the shared SoC blocks, so
> things like the interrupt controllers, serial driver, pfc/pinmux/gpios,
> dmaengine, etc. The interrupt controller subystem that we use for all of
> our cases is sufficiently complex that it's really not an ideal choice in
> terms of low-hanging fruit for DT support, in fact, it's probably the
> worst possible place to start.
>
> I'm in the middle of irqdomain refactoring for it now, which will also
> entail quite a lot of rework with regards to how we deal with our virtual
> IRQs, radix tree utilization, and so forth. What sort of information we
> need to still keep around ultimately won't be known until we have a
> clearer picture of how the irqdomain tie-in will look for the existing
> cases. Only after that does it really make any sense to start on anything
> but the most trivial of DT bindings.
>
> Beyond that, while the vast majority of the INTC cases are in arch/sh
> today, infrastructure-wise everything is sufficiently coupled together
> that it wouldn't make things any simpler to treat INTCA/INTCS specially.
>
> Once we start seeing DT bindings in shared infrastructure (especially
> drivers/sh and so on) then I'll probably start gradually migrating
> arch/sh users over to it, too. For the majority of users we don't really
> have any sort of coherent boot ABI, which means that we're more than
> likely going to always have to link the blob in to the kernel directly,
> but that's another matter.
>
> The GPIO/PFC pinmux/pinctrl bits are likewise quite complex and in flux
> while I work on pinctrl migration (some work done now, but more
> realistically after the irqdomain rework has happened), so it's not worth
> spending any time on DT bindings there for the moment either.
>
> At the moment pretty much any other platform device is orders of
> magnitude more simplistic and workable though. I'm not sure why DT
> prototyping didn't start there, instead.

It did, but more or less all device drivers need IRQs.

/ magnus

Re: [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Arnd Bergmann]

On Friday 30 March 2012, Magnus Damm wrote:

> >> However, the idea that you'd like to describe the controller with the
> >> device tree is interesting. At this point I'm unsure how to do that.
> >> Also, I do wonder if it makes sense to do so at all - most new parts
> >> use the GIC as the main interrupt controller anyway. I do agree with
> >> the plan of separating configuration from code, and in our INTC case
> >> we've sort of already done so about 5 years ago. At that point I
> >> converted a few separate random implementations to the current table
> >> driven INTC code base. Since then we have soon close to 100 different
> >> users in arch/sh and arch/arm/mach-shmobile. Each is different. Feel
> >> free to grep for "register_intc_controller" to explore by yourself. It
> >> would be fun to try to use the device tree for this, but I wonder how
> >> we can describe anything half-complex without a preprocessor. Both the
> >> INTC code and the PFC used for GPIO and pinmux use C enums a lot.
> >
> > Ah, so the vast majority of these are not for shmobile but for arch/sh
> > and I support you have no plans to move those to DT along with shmobile,
> > right?
> 
> Most use cases are still on SH, but for mach-shmobile we make use of
> either GIC of INTCA together with a cascaded INTCS. We also have IRQ
> pins that can be controlled from either INTCA or INTCS or just
> level/edge trigger configuration in front of GIC. In some cases we
> have an interrupt controller called PINT. Some PFC/GPIO controllers
> have built-in interrupt controllers, and some GPIOs have their
> interrupts tied into the INTC as IRQ pins. There is a big jambalaya of
> hardware IP with history from Mitsubishi, Hitachi and NEC, plus the
> usual not-so-exotic ones.
> 
> So with this in mind I believe we will need INTC support for
> mach-shmobile in the future as well. The INTC controllers seem to
> become more like leaf nodes these days though. =)

Ok, I see

> > From my reading of the source code, your INTCA and INTCS controllers
> > all follow the same basic model, but they all differ in the mapping
> > between interrupt vectors to register locations.
> 
> All INTC tables are unique. So the INTCS in sh7372 is not the same as
> the INTCS in sh7367. Some parts of the tables may look similar, but
> low hanging fruit such as external IRQ pin handling has been broken
> out into reusable components already.

What I meant was that the table structure is always the same, even
if the contents are are different. It's fairly easy to replace
data from the kernel sources with data in the device tree, but
replacing code from the kernel with data is much harder.

> > I would probably not try to describe this mapping in the interrupt
> > controller node, but instead use a more elaborate way to describe
> > an interrupt than just the vector.
> 
> That's certainly one way to split out the information, but I wonder if
> that's the right way to go. I worry that with such setup the
> correctness of the mappings between vectors and register fields is
> dependent on the system integrator doing proper copy-paste
> "development". One character wrong and you will have a silent error
> somewhere with the wrong interrupt being masked by accident for
> instance.

All the bits describing the interrupt controller node specific
to one soc should be able to go into the .dtsi file for that soc,
so that a system integrator only needs to hook up the devices that
are outside of the soc.

> > Taking the sh7372 USB0_USB0I0 interrupt as an arbitrary example,
> > you could encode it as
> >
> >        interrupts = <0x1ca0     /* vector */
> >                        0xa4 5   /* mask register offset and bit position */
> >                        0x4c 1>; /* prio register offset and bit position */
> >
> > An interrupt controller that only needs these (no sense/ack registers),
> > would set #interrupt-cells=<5>;, while other interrupt controllers would
> > use a larger number of interrupt cells to also encode the extra data.
> 
> Thanks for showing this example. I think your proposal is interesting.
> I believe I get the big picture, but I wonder if it is that simple
> after all. In this specific example the USB0_USB0I0 interrupt source
> also needs a 0xe4 associated with the mask register. Some mask
> registers come in pairs with one clear and one set register. We also
> have the width of the register and width of the priority field as
> data. Of course the actual register mapping with such information
> could be kept together with the INTC configuration data for the
> interrupt controller, and we can for instance use register offset and
> bit field index to locate the actual bit field or bit. This becomes
> quite close to how INTC is working today though, with the exception
> that we use enums with the same names as the data sheet. I don't see
> how this can be done in Device Tree lingo.

There are two places where you could put that information. The one
I described above is the interrupts property, but if you have to
add many more fields, this gets impractical.

The other place would be sub-nodes of the interrupt controller node
that don't get translated into individual platform devices.

You can have one node per interrupt line, like this:

	intc@6940000 {
		#address-cells = <2>;
		#size-cells = <0>;
		reg = <0x6940000 0x1000>;
		ranges = <1 0  0x6940000 0x54   /* prio */
			  2 0  0x6940080 0x3c   /* mask */
			  3 0  0x69400c0 0x3c>; /* unmask /

		/* common properties for priority nodes,
		   could get overridden if necessary */
		prio-reg-width = <16>;
		prio-width = <4>;

		iprta3 {
			#address-cells = <2>;
			#size-cells = <0>;
			ranges;

			reg = <1 0x4c> /* priority reg 0x4c */

			usb0_usb0i0 {
				reg = <0 0x1ca0  /* vector 0x1ca0 */
					1 0x34   /* mask   0x80 + 0x34 */
					2 0x34>; /* unmask 0xc0 + 0x34 */
				reg-mask = <0x04>; /* bitmask for registers */
			};
		};
	};

> > I don't understand what your interrupt groups are, or whether you need
> > even more attributes somewhere.
> 
> The groups are used to link together multiple interrupt sources
> (enums) that share a priority setting.
> 
> Anyway, just to be clear, at this point i mainly wanted to enable DT
> support on the mach-shmobile subarch and sh7372 in particular. So in
> my mind this excludes reworking the INTC and PFC tables. Such
> activities will take quite some time due to them being shared with SH.
> Of course we should work in that direction, but at this point I 'd
> like to focus on getting other people to work with DT support in the
> drivers. So because of that I spent time on getting interrupts going
> with the device tree instead of figuring out how to replace the INTC
> tables with something else. Step by step.
> 
> I assume that your current merge policy is that boards should be
> implemented in DT, but we can still merge new SoCs with current style
> of INTC and PFC tables as usual?

Yes, that sounds ok. The part that I would not want to see though
is having a preliminary binding for INTC that you later have to
replace by another binding, breaking all device tree files that
were produced at first.

It's ok if you add more data to the intc nodes at a later
point while incrementally moving stuff into dts files, but I think
you should decide on how to represent an interrupt line in the devices
using intc.

	Arnd

Re: [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Arnd Bergmann]

On Friday 30 March 2012, Paul Mundt wrote:
> On Thu, Mar 29, 2012 at 01:06:38PM +0000, Arnd Bergmann wrote:
> > On Thursday 29 March 2012, Magnus Damm wrote:
> > > However, the idea that you'd like to describe the controller with the
> > > device tree is interesting. At this point I'm unsure how to do that.
> > > Also, I do wonder if it makes sense to do so at all - most new parts
> > > use the GIC as the main interrupt controller anyway. I do agree with
> > > the plan of separating configuration from code, and in our INTC case
> > > we've sort of already done so about 5 years ago. At that point I
> > > converted a few separate random implementations to the current table
> > > driven INTC code base. Since then we have soon close to 100 different
> > > users in arch/sh and arch/arm/mach-shmobile. Each is different. Feel
> > > free to grep for "register_intc_controller" to explore by yourself. It
> > > would be fun to try to use the device tree for this, but I wonder how
> > > we can describe anything half-complex without a preprocessor. Both the
> > > INTC code and the PFC used for GPIO and pinmux use C enums a lot.
> > 
> > Ah, so the vast majority of these are not for shmobile but for arch/sh
> > and I support you have no plans to move those to DT along with shmobile,
> > right?
> > 
> At the moment the main priority is really just the shared SoC blocks, so
> things like the interrupt controllers, serial driver, pfc/pinmux/gpios,
> dmaengine, etc. The interrupt controller subystem that we use for all of
> our cases is sufficiently complex that it's really not an ideal choice in
> terms of low-hanging fruit for DT support, in fact, it's probably the
> worst possible place to start.
> 
> I'm in the middle of irqdomain refactoring for it now, which will also
> entail quite a lot of rework with regards to how we deal with our virtual
> IRQs, radix tree utilization, and so forth. What sort of information we
> need to still keep around ultimately won't be known until we have a
> clearer picture of how the irqdomain tie-in will look for the existing
> cases. Only after that does it really make any sense to start on anything
> but the most trivial of DT bindings.

In my experience, the interrupt controller bindings are among the first
things that one wants to work on, followed by the gpio bindings, because
most other things tend to depend on them. Now that doesn't mean the code
has to actually use all the information you put into the device tree,
but since it describes the hardware, it should be possible to find out
what information is really needed in there to describe each interrupt
line.

For INTC, you basically have two options of describing them:

a) As in Magnus' patch, give a separate "compatible" name to each
version, and let it be handled by its own code.

b) As I suggested, make a fully generic INTC binding that encodes
all the differences in device tree properties.

The first one has the significant advantage of requiring only
moderate changes to the source code, and you already have a prototype
for them. The second one requires much more work but has the advantage
that you can use it later to add support for new SoC versions
without having to add source code for the new instance of that
interrupt controller. If all other drivers for the new Soc are already
present in the kernel, you can even keep using the same kernel binaries,
which you would not be able to do with approach a).

You can probably defer the problem for a bit if you first do DT work
only for the SoCs that use GIC, which already has an established
binding. Also, it's possible to come up with a binding that you
expect to work and that can represent all the data you need, but
still keep using the existing code for as long as you need before
you get to convert it to actually use the data from the binding.
Just mark the node as compatible with both the generic INTC binding
as well as the specific itnerrupt controller for one of the SoCs,
so you can use the existing code with the tables in the kernel,
and ignore all the duplicate data from the device tree (possibly
checking the data to make sure it matches).

	Arnd

Re: [PATCH] ARM: mach-shmobile: sh7372 DT IRQ prototype

[Magnus Damm]

On Fri, Mar 30, 2012 at 11:38 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Friday 30 March 2012, Magnus Damm wrote:
>
>> >> However, the idea that you'd like to describe the controller with the
>> >> device tree is interesting. At this point I'm unsure how to do that.
>> >> Also, I do wonder if it makes sense to do so at all - most new parts
>> >> use the GIC as the main interrupt controller anyway. I do agree with
>> >> the plan of separating configuration from code, and in our INTC case
>> >> we've sort of already done so about 5 years ago. At that point I
>> >> converted a few separate random implementations to the current table
>> >> driven INTC code base. Since then we have soon close to 100 different
>> >> users in arch/sh and arch/arm/mach-shmobile. Each is different. Feel
>> >> free to grep for "register_intc_controller" to explore by yourself. It
>> >> would be fun to try to use the device tree for this, but I wonder how
>> >> we can describe anything half-complex without a preprocessor. Both the
>> >> INTC code and the PFC used for GPIO and pinmux use C enums a lot.
>> >
>> > Ah, so the vast majority of these are not for shmobile but for arch/sh
>> > and I support you have no plans to move those to DT along with shmobile,
>> > right?
>>
>> Most use cases are still on SH, but for mach-shmobile we make use of
>> either GIC of INTCA together with a cascaded INTCS. We also have IRQ
>> pins that can be controlled from either INTCA or INTCS or just
>> level/edge trigger configuration in front of GIC. In some cases we
>> have an interrupt controller called PINT. Some PFC/GPIO controllers
>> have built-in interrupt controllers, and some GPIOs have their
>> interrupts tied into the INTC as IRQ pins. There is a big jambalaya of
>> hardware IP with history from Mitsubishi, Hitachi and NEC, plus the
>> usual not-so-exotic ones.
>>
>> So with this in mind I believe we will need INTC support for
>> mach-shmobile in the future as well. The INTC controllers seem to
>> become more like leaf nodes these days though. =)
>
> Ok, I see
>
>> > From my reading of the source code, your INTCA and INTCS controllers
>> > all follow the same basic model, but they all differ in the mapping
>> > between interrupt vectors to register locations.
>>
>> All INTC tables are unique. So the INTCS in sh7372 is not the same as
>> the INTCS in sh7367. Some parts of the tables may look similar, but
>> low hanging fruit such as external IRQ pin handling has been broken
>> out into reusable components already.
>
> What I meant was that the table structure is always the same, even
> if the contents are are different. It's fairly easy to replace
> data from the kernel sources with data in the device tree, but
> replacing code from the kernel with data is much harder.

Right. =)

>> > I would probably not try to describe this mapping in the interrupt
>> > controller node, but instead use a more elaborate way to describe
>> > an interrupt than just the vector.
>>
>> That's certainly one way to split out the information, but I wonder if
>> that's the right way to go. I worry that with such setup the
>> correctness of the mappings between vectors and register fields is
>> dependent on the system integrator doing proper copy-paste
>> "development". One character wrong and you will have a silent error
>> somewhere with the wrong interrupt being masked by accident for
>> instance.
>
> All the bits describing the interrupt controller node specific
> to one soc should be able to go into the .dtsi file for that soc,
> so that a system integrator only needs to hook up the devices that
> are outside of the soc.

Sure, splitting data that way makes sense. That's how I'd like it to be.

I was more confused about the example of "interrupts = < vector, foo,
bar >;". I got the impression that this information was going to be
kept together with each device that makes use of interrupts, and we
would need such vector/foo/bar information also for interrupts used by
board specific devices. So the ethernet chip on our Mackerel board
would look something like this:

       lan9220@14000000 {
               compatible = "smsc,lan9220", "smsc,lan9115";
               reg = <0x14000000 0x2000000>;
               phy-mode = "mii";
               interrupt-parent = <&intca>;
               interrupts = <0x2c0, foo, bar>;
               reg-io-width = <4>;
               smsc,irq-push-pull;
       };

I'm concerned that system integrators would have trouble copy-pasting
the above "interrupts" correctly. I'm sure there's some elegant
solution to this issue though.

>> > Taking the sh7372 USB0_USB0I0 interrupt as an arbitrary example,
>> > you could encode it as
>> >
>> >        interrupts = <0x1ca0     /* vector */
>> >                        0xa4 5   /* mask register offset and bit position */
>> >                        0x4c 1>; /* prio register offset and bit position */
>> >
>> > An interrupt controller that only needs these (no sense/ack registers),
>> > would set #interrupt-cells=<5>;, while other interrupt controllers would
>> > use a larger number of interrupt cells to also encode the extra data.
>>
>> Thanks for showing this example. I think your proposal is interesting.
>> I believe I get the big picture, but I wonder if it is that simple
>> after all. In this specific example the USB0_USB0I0 interrupt source
>> also needs a 0xe4 associated with the mask register. Some mask
>> registers come in pairs with one clear and one set register. We also
>> have the width of the register and width of the priority field as
>> data. Of course the actual register mapping with such information
>> could be kept together with the INTC configuration data for the
>> interrupt controller, and we can for instance use register offset and
>> bit field index to locate the actual bit field or bit. This becomes
>> quite close to how INTC is working today though, with the exception
>> that we use enums with the same names as the data sheet. I don't see
>> how this can be done in Device Tree lingo.
>
> There are two places where you could put that information. The one
> I described above is the interrupts property, but if you have to
> add many more fields, this gets impractical.

I agree!

> The other place would be sub-nodes of the interrupt controller node
> that don't get translated into individual platform devices.
>
> You can have one node per interrupt line, like this:
>
>        intc@6940000 {
>                #address-cells = <2>;
>                #size-cells = <0>;
>                reg = <0x6940000 0x1000>;
>                ranges = <1 0  0x6940000 0x54   /* prio */
>                          2 0  0x6940080 0x3c   /* mask */
>                          3 0  0x69400c0 0x3c>; /* unmask /
>
>                /* common properties for priority nodes,
>                   could get overridden if necessary */
>                prio-reg-width = <16>;
>                prio-width = <4>;
>
>                iprta3 {
>                        #address-cells = <2>;
>                        #size-cells = <0>;
>                        ranges;
>
>                        reg = <1 0x4c> /* priority reg 0x4c */
>
>                        usb0_usb0i0 {
>                                reg = <0 0x1ca0  /* vector 0x1ca0 */
>                                        1 0x34   /* mask   0x80 + 0x34 */
>                                        2 0x34>; /* unmask 0xc0 + 0x34 */
>                                reg-mask = <0x04>; /* bitmask for registers */
>                        };
>                };
>        };

Thanks, that looks more like the self-contained INTC tables that we
represent in C today.

>> > I don't understand what your interrupt groups are, or whether you need
>> > even more attributes somewhere.
>>
>> The groups are used to link together multiple interrupt sources
>> (enums) that share a priority setting.
>>
>> Anyway, just to be clear, at this point i mainly wanted to enable DT
>> support on the mach-shmobile subarch and sh7372 in particular. So in
>> my mind this excludes reworking the INTC and PFC tables. Such
>> activities will take quite some time due to them being shared with SH.
>> Of course we should work in that direction, but at this point I 'd
>> like to focus on getting other people to work with DT support in the
>> drivers. So because of that I spent time on getting interrupts going
>> with the device tree instead of figuring out how to replace the INTC
>> tables with something else. Step by step.
>>
>> I assume that your current merge policy is that boards should be
>> implemented in DT, but we can still merge new SoCs with current style
>> of INTC and PFC tables as usual?
>
> Yes, that sounds ok. The part that I would not want to see though
> is having a preliminary binding for INTC that you later have to
> replace by another binding, breaking all device tree files that
> were produced at first.

Sure, but since we enable SoC one by one, can't we just start with
something simple for sh7372, and then decide on a per-SoC basis
depending on the state of device tree support in the INTC code versus
the complexity of the INTC hardware block?

So for instance on sh7372 we use just vector numbers as interrupt. In
parallel we can work towards representing the INTC tables as device
tree data. And when that is done, and we happen to have a SoC that can
implement support for INTC via just device tree only then we can use
the device tree for the INTC table information. So before we have INTC
table support via device tree our only choice is to do as sh7372. And
the same for the corner cases where we cannot use the device tree for
INTC tables - perhaps because it needs some special handling or it
uses something that doesn't have a proper device tree binding yet.

My point is that we can evolve forward for each new SoC. Replacing
bindings for a certain SoC sounds very bad.

> It's ok if you add more data to the intc nodes at a later
> point while incrementally moving stuff into dts files, but I think
> you should decide on how to represent an interrupt line in the devices
> using intc.

So you would like an interrupt line for "renesas,intca-sh7372" to be
the same as "renesas,intca-potential-new-soc"?

Thanks,

/ magnus