[U-Boot] [PATCH V3] i.MX6: mx6q_sabrelite: add SATA bindings

[U-Boot] [PATCH V3] i.MX6: mx6q_sabrelite: add SATA bindings

[Eric Nelson]

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

---
V2 has been stripped of the board-independent changes and
uses clrsetbits_le32() instead of twiddling bits by hand.

V3 returns immediately from setup_sata() if enable_sata_clock()
returns an error.

 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   32 +++++++++++++++++++++++++
 include/configs/mx6qsabrelite.h               |   13 ++++++++++
 2 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 1d09a72..c9a108f 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -25,6 +25,8 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>
@@ -267,6 +269,32 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int rval = enable_sata_clock();
+	if (rval)
+		return rval ;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0 ;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
@@ -283,6 +311,10 @@ int board_init(void)
 	setup_spi();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
        return 0;
 }
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index f52c3c7..1d92dd0 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -71,6 +71,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
-- 
1.7.9

[U-Boot] [PATCH V3] i.MX6: mx6q_sabrelite: add SATA bindings

[Dirk Behme]

Hi Eric,

On 26.04.2012 01:50, Eric Nelson wrote:
> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com>
>
> ---
> V2 has been stripped of the board-independent changes and
> uses clrsetbits_le32() instead of twiddling bits by hand.
>
> V3 returns immediately from setup_sata() if enable_sata_clock()
> returns an error.
>
>   board/freescale/mx6qsabrelite/mx6qsabrelite.c |   32 +++++++++++++++++++++++++
>   include/configs/mx6qsabrelite.h               |   13 ++++++++++
>   2 files changed, 45 insertions(+), 0 deletions(-)
>
> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> index 1d09a72..c9a108f 100644
> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> @@ -25,6 +25,8 @@
>   #include<asm/arch/imx-regs.h>
>   #include<asm/arch/mx6x_pins.h>
>   #include<asm/arch/iomux-v3.h>
> +#include<asm/arch/ccm_regs.h>

Do we need ccm_regs.h here?

Best regards

Dirk

[U-Boot] [PATCH V3] i.MX6: mx6q_sabrelite: add SATA bindings

[Eric Nelson]

Hi Dirk,

On 04/28/2012 07:51 AM, Dirk Behme wrote:
> Hi Eric,
>
> On 26.04.2012 01:50, Eric Nelson wrote:
>> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com>
>>
>> ---
>> V2 has been stripped of the board-independent changes and
>> uses clrsetbits_le32() instead of twiddling bits by hand.
>>
>> V3 returns immediately from setup_sata() if enable_sata_clock()
>> returns an error.
>>
>> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 32 +++++++++++++++++++++++++
>> include/configs/mx6qsabrelite.h | 13 ++++++++++
>> 2 files changed, 45 insertions(+), 0 deletions(-)
>>
>> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> index 1d09a72..c9a108f 100644
>> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>> @@ -25,6 +25,8 @@
>> #include<asm/arch/imx-regs.h>
>> #include<asm/arch/mx6x_pins.h>
>> #include<asm/arch/iomux-v3.h>
>> +#include<asm/arch/ccm_regs.h>
>
> Do we need ccm_regs.h here?
>

Nope. Good catch.

I'll generate a V4 in a day or two to allow some other review.

Stefano, what's the status of the dwc_ahsata driver?

Without that, the bindings are clearly useless.

Regards,


Eric

[U-Boot] [PATCH V3] i.MX6: mx6q_sabrelite: add SATA bindings

[Stefano Babic]

On 28/04/2012 17:36, Eric Nelson wrote:
> Hi Dirk,
> 
> On 04/28/2012 07:51 AM, Dirk Behme wrote:
>> Hi Eric,
>>
>> On 26.04.2012 01:50, Eric Nelson wrote:
>>> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com>
>>>
>>> ---
>>> V2 has been stripped of the board-independent changes and
>>> uses clrsetbits_le32() instead of twiddling bits by hand.
>>>
>>> V3 returns immediately from setup_sata() if enable_sata_clock()
>>> returns an error.
>>>
>>> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 32
>>> +++++++++++++++++++++++++
>>> include/configs/mx6qsabrelite.h | 13 ++++++++++
>>> 2 files changed, 45 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>>> b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>>> index 1d09a72..c9a108f 100644
>>> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>>> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
>>> @@ -25,6 +25,8 @@
>>> #include<asm/arch/imx-regs.h>
>>> #include<asm/arch/mx6x_pins.h>
>>> #include<asm/arch/iomux-v3.h>
>>> +#include<asm/arch/ccm_regs.h>
>>
>> Do we need ccm_regs.h here?
>>
> 
> Nope. Good catch.
> 
> I'll generate a V4 in a day or two to allow some other review.
> 
> Stefano, what's the status of the dwc_ahsata driver?

Hi Eric, hi Dirk,

I have merged the dwc_ahsata into the master branch, and the drive ris
available.

Best regards,
Stefano Babic


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[U-Boot] [PATCH V3] i.MX6: mx6q_sabrelite: add SATA bindings

[Marek Vasut]

Dear Eric Nelson,

> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
> 
> ---
> V2 has been stripped of the board-independent changes and
> uses clrsetbits_le32() instead of twiddling bits by hand.
> 
> V3 returns immediately from setup_sata() if enable_sata_clock()
> returns an error.
> 
>  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   32
> +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h               | 
>  13 ++++++++++
>  2 files changed, 45 insertions(+), 0 deletions(-)
> 
> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 1d09a72..c9a108f
> 100644
> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> @@ -25,6 +25,8 @@
>  #include <asm/arch/imx-regs.h>
>  #include <asm/arch/mx6x_pins.h>
>  #include <asm/arch/iomux-v3.h>
> +#include <asm/arch/ccm_regs.h>
> +#include <asm/arch/clock.h>
>  #include <asm/errno.h>
>  #include <asm/gpio.h>
>  #include <mmc.h>
> @@ -267,6 +269,32 @@ int board_eth_init(bd_t *bis)
>  	return 0;
>  }
> 
> +#ifdef CONFIG_CMD_SATA
> +
> +int setup_sata(void)
> +{
> +	struct iomuxc_base_regs *const iomuxc_regs
> +		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
> +	int rval = enable_sata_clock();
> +	if (rval)
> +		return rval ;

Can you keep the return <val>; consistent with the rest of the file? (so avoid 
return <val>[space];) ... I dunno if this violates some coding style document 
though. Just a nitpick.

> +
> +	clrsetbits_le32(&iomuxc_regs->gpr[13],
> +			IOMUXC_GPR13_SATA_MASK,
> +			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
> +			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
> +			|IOMUXC_GPR13_SATA_SPEED_3G
> +			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
> +			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
> +			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
> +			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
> +			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
> +			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
> +
> +	return 0 ;
> +}
> +#endif
> +
>  int board_early_init_f(void)
>  {
>         setup_iomux_uart();
> @@ -283,6 +311,10 @@ int board_init(void)
>  	setup_spi();
>  #endif
> 
> +#ifdef CONFIG_CMD_SATA
> +	setup_sata();
> +#endif
> +
>         return 0;
>  }
> 
> diff --git a/include/configs/mx6qsabrelite.h
> b/include/configs/mx6qsabrelite.h index f52c3c7..1d92dd0 100644
> --- a/include/configs/mx6qsabrelite.h
> +++ b/include/configs/mx6qsabrelite.h
> @@ -71,6 +71,19 @@
>  #define CONFIG_CMD_FAT
>  #define CONFIG_DOS_PARTITION
> 
> +#define CONFIG_CMD_SATA
> +/*
> + * SATA Configs
> + */
> +#ifdef CONFIG_CMD_SATA
> +#define CONFIG_DWC_AHSATA
> +#define CONFIG_SYS_SATA_MAX_DEVICE	1
> +#define CONFIG_DWC_AHSATA_PORT_ID	0
> +#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
> +#define CONFIG_LBA48
> +#define CONFIG_LIBATA
> +#endif
> +
>  #define CONFIG_CMD_PING
>  #define CONFIG_CMD_DHCP
>  #define CONFIG_CMD_MII

[U-Boot] [PATCH V3] i.MX6: mx6q_sabrelite: add SATA bindings

[Eric Nelson]

Hi Marek,

On 04/29/2012 07:27 PM, Marek Vasut wrote:
> Dear Eric Nelson,
>
>> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com>
>>
>> ---
>> V2 has been stripped of the board-independent changes and
>> uses clrsetbits_le32() instead of twiddling bits by hand.
>>
 >> <snip>
 >>
>> +int setup_sata(void)
>> +{
>> +	struct iomuxc_base_regs *const iomuxc_regs
>> +		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
>> +	int rval = enable_sata_clock();
>> +	if (rval)
>> +		return rval ;
>
> Can you keep the return<val>; consistent with the rest of the file? (so avoid
> return<val>[space];) ... I dunno if this violates some coding style document
> though. Just a nitpick.
>

Can do. I'll update this in V4.