Incorrect Register Offsets in OMAP Mailbox

Incorrect Register Offsets in OMAP Mailbox

[Henry Chan]

[-- Attachment #1: Type: text/plain, Size: 374 bytes --]

Hi,

Looks like the register offsets are incorrect in the OMAP mailbox code
(arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The
discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K.
Patch attached.

My hardware hasn't come in yet, so I would appreciate it if anyone can
share their experience using this code.

Thanks.
-H
-- 
Henry Chan

[-- Attachment #2: 0001-Fix-mailbox-IRQ-offsets.patch --]
[-- Type: text/x-patch, Size: 841 bytes --]

 arch/arm/mach-omap2/mailbox.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 609ea2d..4801e01 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -26,9 +26,9 @@
 #define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
 #define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
 
-#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))
+#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
 
 #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))


[-- Attachment #3: enli_chan.vcf --]
[-- Type: text/x-vcard, Size: 142 bytes --]

begin:vcard
fn:Henry Chan
n:Chan;Henry
email;internet:enli.chan@gmail.com
tel;cell:(315) 834-2426
x-mozilla-html:FALSE
version:2.1
end:vcard

Re: Incorrect Register Offsets in OMAP Mailbox

[Tony Lindgren]

Hi Henry,

* Henry Chan <enli.chan@gmail.com> [120207 09:25]:
> Hi,
> 
> Looks like the register offsets are incorrect in the OMAP mailbox code
> (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The
> discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K.
> Patch attached.
> 
> My hardware hasn't come in yet, so I would appreciate it if anyone can
> share their experience using this code.

Can you please reply with your Signed-off-by, it's missing from the
patch.

Thanks,

Tony

> --- a/arch/arm/mach-omap2/mailbox.c
> +++ b/arch/arm/mach-omap2/mailbox.c
> @@ -26,9 +26,9 @@
>  #define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
>  #define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
>  
> -#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
> -#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
> -#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))
> +#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
> +#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
> +#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
>  
>  #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
>  #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))
> 

Re: Incorrect Register Offsets in OMAP Mailbox

[Henry Chan]

Sorry about that. Kind of new at this.
-H

Signed-off-by: Henry Chan <enli.chan@gmail.com>

On 03/05/12 11:34, Tony Lindgren wrote:
> Hi Henry,
> 
> * Henry Chan <enli.chan@gmail.com> [120207 09:25]:
>> Hi,
>>
>> Looks like the register offsets are incorrect in the OMAP mailbox code
>> (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The
>> discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K.
>> Patch attached.
>>
>> My hardware hasn't come in yet, so I would appreciate it if anyone can
>> share their experience using this code.
> 
> Can you please reply with your Signed-off-by, it's missing from the
> patch.
> 
> Thanks,
> 
> Tony
> 
>> --- a/arch/arm/mach-omap2/mailbox.c
>> +++ b/arch/arm/mach-omap2/mailbox.c
>> @@ -26,9 +26,9 @@
>>  #define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
>>  #define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
>>  
>> -#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
>> -#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
>> -#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))
>> +#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
>> +#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
>> +#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
>>  
>>  #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
>>  #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))
>>
> 
-- 
Henry Chan

Re: Incorrect Register Offsets in OMAP Mailbox

[Tony Lindgren]

* Henry Chan <enli.chan@gmail.com> [120307 23:33]:
> Sorry about that. Kind of new at this.
> -H
> 
> Signed-off-by: Henry Chan <enli.chan@gmail.com>

Thanks, applying this finally into fixes-non-critical.

Tony
 
> On 03/05/12 11:34, Tony Lindgren wrote:
> > Hi Henry,
> > 
> > * Henry Chan <enli.chan@gmail.com> [120207 09:25]:
> >> Hi,
> >>
> >> Looks like the register offsets are incorrect in the OMAP mailbox code
> >> (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The
> >> discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K.
> >> Patch attached.
> >>
> >> My hardware hasn't come in yet, so I would appreciate it if anyone can
> >> share their experience using this code.
> > 
> > Can you please reply with your Signed-off-by, it's missing from the
> > patch.
> > 
> > Thanks,
> > 
> > Tony
> > 
> >> --- a/arch/arm/mach-omap2/mailbox.c
> >> +++ b/arch/arm/mach-omap2/mailbox.c
> >> @@ -26,9 +26,9 @@
> >>  #define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
> >>  #define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
> >>  
> >> -#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
> >> -#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
> >> -#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))
> >> +#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
> >> +#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
> >> +#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
> >>  
> >>  #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
> >>  #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))
> >>
> > 
> -- 
> Henry Chan

RE: Incorrect Register Offsets in OMAP Mailbox

[Bedia, Vaibhav]

Hi Tony,

On Fri, Feb 10, 2012 at 06:44:47, Tony Lindgren wrote:
> * Bedia, Vaibhav <vaibhav.bedia@ti.com> [120209 09:27]:
> > On Thu, Feb 09, 2012 at 23:17:10, Tony Lindgren wrote:
> > > Care to reply with Acked-by/Tested-by so I can queue this into fixes?
> > > 
> > 
> > Acked-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> 
> Is the mailbox now actually usable on this hardware with this patch?
> 

I am using this fix to make use of the mailbox on AM335x which has the same IP
as OMAP4. With a couple of patches to add AM335x support I have been able to make
use of the mailbox for one-way communication between the A8 and Cortex-M3.

I don't have an OMAP4 board with me to test this out.

Regards,
Vaibhav

Re: Incorrect Register Offsets in OMAP Mailbox

[Tony Lindgren]

* Bedia, Vaibhav <vaibhav.bedia@ti.com> [120209 09:27]:
> On Thu, Feb 09, 2012 at 23:17:10, Tony Lindgren wrote:
> > Care to reply with Acked-by/Tested-by so I can queue this into fixes?
> > 
> 
> Acked-by: Vaibhav Bedia <vaibhav.bedia@ti.com>

Is the mailbox now actually usable on this hardware with this patch?

Regards,

Tony

RE: Incorrect Register Offsets in OMAP Mailbox

[Bedia, Vaibhav]

On Thu, Feb 09, 2012 at 23:17:10, Tony Lindgren wrote:
> Care to reply with Acked-by/Tested-by so I can queue this into fixes?
> 

Acked-by: Vaibhav Bedia <vaibhav.bedia@ti.com>

Re: Incorrect Register Offsets in OMAP Mailbox

[Tony Lindgren]

* Bedia, Vaibhav <vaibhav.bedia@ti.com> [120209 02:54]:
> > -----Original Message-----
> > From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Henry Chan
> > Sent: Tuesday, February 07, 2012 11:27 PM
> > To: linux-omap@vger.kernel.org
> > Subject: Incorrect Register Offsets in OMAP Mailbox
> > 
> > Hi,
> > 
> > Looks like the register offsets are incorrect in the OMAP mailbox code
> > (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The
> > discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K.
> > Patch attached.
> > 
> > My hardware hasn't come in yet, so I would appreciate it if anyone can
> > share their experience using this code.
> > 
> 
> Yes, this change is required. Other than this fix the code is fine IMO.
> 
> I guess the address calculation macros can be simplified to match with the
> terminology used in the TRM. I'll submit a patch for that once I manage to
> get some time for doing it right.

Care to reply with Acked-by/Tested-by so I can queue this into fixes?

Regards,

Tony

RE: Incorrect Register Offsets in OMAP Mailbox

[Bedia, Vaibhav]

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Henry Chan
> Sent: Tuesday, February 07, 2012 11:27 PM
> To: linux-omap@vger.kernel.org
> Subject: Incorrect Register Offsets in OMAP Mailbox
> 
> Hi,
> 
> Looks like the register offsets are incorrect in the OMAP mailbox code
> (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The
> discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K.
> Patch attached.
> 
> My hardware hasn't come in yet, so I would appreciate it if anyone can
> share their experience using this code.
> 

Yes, this change is required. Other than this fix the code is fine IMO.

I guess the address calculation macros can be simplified to match with the
terminology used in the TRM. I'll submit a patch for that once I manage to
get some time for doing it right.

Regards,
Vaibhav