* [PATCH 00/10] spi: s3c64xx: add support for device tree
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
This patch series adds device tree based discovery support for Samsung's
s3c64xx compatible spi controller. This is mainly tested for Exynos4210
and Exynos5250 with onboard spi nor flash device.
This patch series is based on Linux 3.4-rc5 with the following two
patch series applied.
[1] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg10494.html
[PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0
[2] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg09640.html
[PATCH 0/6] S3C24XX: Add support for HSSPI on S3C2416/S3C2443
Thomas Abraham (10):
spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
spi: s3c64xx: move controller information into driver data
ARM: Samsung: Remove spi hardware controller information from platform data
ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions
ARM: Samsung: Update the device names for spi clock lookup
ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
spi: s3c64xx: Remove the 'set_level' callback from controller data
ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
ARM: Exynos5: Add spi clock support
spi: s3c64xx: add device tree support
.../devicetree/bindings/spi/spi-samsung.txt | 113 +++++
arch/arm/mach-exynos/clock-exynos4.c | 66 ++-
arch/arm/mach-exynos/clock-exynos5.c | 98 ++++
arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
arch/arm/mach-exynos/setup-spi.c | 33 +--
arch/arm/mach-s3c24xx/clock-s3c2416.c | 2 +-
arch/arm/mach-s3c24xx/clock-s3c2443.c | 2 +-
arch/arm/mach-s3c24xx/common-s3c2443.c | 4 +-
arch/arm/mach-s3c24xx/setup-spi.c | 10 +-
arch/arm/mach-s3c64xx/clock.c | 20 +-
arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
arch/arm/mach-s3c64xx/setup-spi.c | 19 +-
arch/arm/mach-s5p64x0/clock-s5p6440.c | 12 +-
arch/arm/mach-s5p64x0/clock-s5p6450.c | 12 +-
arch/arm/mach-s5p64x0/setup-spi.c | 21 +-
arch/arm/mach-s5pc100/clock.c | 30 +-
arch/arm/mach-s5pc100/setup-spi.c | 30 +--
arch/arm/mach-s5pv210/clock.c | 14 +-
arch/arm/mach-s5pv210/setup-spi.c | 21 +-
arch/arm/plat-samsung/devs.c | 50 +--
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 31 +-
drivers/spi/spi-s3c64xx.c | 467 +++++++++++++++++---
22 files changed, 753 insertions(+), 308 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 00/10] spi: s3c64xx: add support for device tree
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
This patch series adds device tree based discovery support for Samsung's
s3c64xx compatible spi controller. This is mainly tested for Exynos4210
and Exynos5250 with onboard spi nor flash device.
This patch series is based on Linux 3.4-rc5 with the following two
patch series applied.
[1] http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg10494.html
[PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0
[2] http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg09640.html
[PATCH 0/6] S3C24XX: Add support for HSSPI on S3C2416/S3C2443
Thomas Abraham (10):
spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
spi: s3c64xx: move controller information into driver data
ARM: Samsung: Remove spi hardware controller information from platform data
ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions
ARM: Samsung: Update the device names for spi clock lookup
ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
spi: s3c64xx: Remove the 'set_level' callback from controller data
ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
ARM: Exynos5: Add spi clock support
spi: s3c64xx: add device tree support
.../devicetree/bindings/spi/spi-samsung.txt | 113 +++++
arch/arm/mach-exynos/clock-exynos4.c | 66 ++-
arch/arm/mach-exynos/clock-exynos5.c | 98 ++++
arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
arch/arm/mach-exynos/setup-spi.c | 33 +--
arch/arm/mach-s3c24xx/clock-s3c2416.c | 2 +-
arch/arm/mach-s3c24xx/clock-s3c2443.c | 2 +-
arch/arm/mach-s3c24xx/common-s3c2443.c | 4 +-
arch/arm/mach-s3c24xx/setup-spi.c | 10 +-
arch/arm/mach-s3c64xx/clock.c | 20 +-
arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
arch/arm/mach-s3c64xx/setup-spi.c | 19 +-
arch/arm/mach-s5p64x0/clock-s5p6440.c | 12 +-
arch/arm/mach-s5p64x0/clock-s5p6450.c | 12 +-
arch/arm/mach-s5p64x0/setup-spi.c | 21 +-
arch/arm/mach-s5pc100/clock.c | 30 +-
arch/arm/mach-s5pc100/setup-spi.c | 30 +--
arch/arm/mach-s5pv210/clock.c | 14 +-
arch/arm/mach-s5pv210/setup-spi.c | 21 +-
arch/arm/plat-samsung/devs.c | 50 +--
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 31 +-
drivers/spi/spi-s3c64xx.c | 467 +++++++++++++++++---
22 files changed, 753 insertions(+), 308 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 01/10] spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
The macro S3C64XX_SPI_ST_TRLCNTZ is not used and hence it is removed.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
drivers/spi/spi-s3c64xx.c | 4 ----
1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 972a94c..6a3d51a 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -113,10 +113,6 @@
#define S3C64XX_SPI_FBCLK_MSK (3<<0)
-#define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
- (((i)->fifo_lvl_mask + 1))) \
- ? 1 : 0)
-
#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 01/10] spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
The macro S3C64XX_SPI_ST_TRLCNTZ is not used and hence it is removed.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
drivers/spi/spi-s3c64xx.c | 4 ----
1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 972a94c..6a3d51a 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -113,10 +113,6 @@
#define S3C64XX_SPI_FBCLK_MSK (3<<0)
-#define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
- (((i)->fifo_lvl_mask + 1))) \
- ? 1 : 0)
-
#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 02/10] spi: s3c64xx: move controller information into driver data
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
Platform data is used to specify controller hardware specific information
such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
information is not suitable to be supplied from device tree. Instead,
it can be moved into the driver data and removed from platform data.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
drivers/spi/spi-s3c64xx.c | 180 ++++++++++++++++++++++++++++++++++++++-------
1 files changed, 153 insertions(+), 27 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 6a3d51a..f6bc0e3 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -31,6 +31,8 @@
#include <mach/dma.h>
#include <plat/s3c64xx-spi.h>
+#define MAX_SPI_PORTS 3
+
/* Registers and bit-fields */
#define S3C64XX_SPI_CH_CFG 0x00
@@ -113,9 +115,12 @@
#define S3C64XX_SPI_FBCLK_MSK (3<<0)
-#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
-#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
-#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
+#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
+#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
+ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
+#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
+#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
+ FIFO_LVL_MASK(i))
#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
#define S3C64XX_SPI_TRAILCNT_OFF 19
@@ -134,6 +139,28 @@ struct s3c64xx_spi_dma_data {
};
/**
+ * struct s3c64xx_spi_info - SPI Controller hardware info
+ * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
+ * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
+ * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
+ * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
+ * @clk_from_cmu: True, if the controller does not include a clock mux and
+ * prescaler unit.
+ *
+ * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
+ * differ in some aspects such as the size of the fifo and spi bus clock
+ * setup. Such differences are specified to the driver using this structure
+ * which is provided as driver data to the driver.
+ */
+struct s3c64xx_spi_port_config {
+ int fifo_lvl_mask[MAX_SPI_PORTS];
+ int rx_lvl_offset;
+ int tx_st_done;
+ bool high_speed;
+ bool clk_from_cmu;
+};
+
+/**
* struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
* @clk: Pointer to the spi clock.
* @src_clk: Pointer to the clock used to generate SPI signals.
@@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data {
struct s3c64xx_spi_dma_data rx_dma;
struct s3c64xx_spi_dma_data tx_dma;
struct samsung_dma_ops *ops;
+ struct s3c64xx_spi_port_config *port_conf;
+ unsigned port_id;
};
static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
@@ -179,7 +208,6 @@ static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
void __iomem *regs = sdd->regs;
unsigned long loops;
u32 val;
@@ -195,7 +223,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
loops = msecs_to_loops(1);
do {
val = readl(regs + S3C64XX_SPI_STATUS);
- } while (TX_FIFO_LVL(val, sci) && loops--);
+ } while (TX_FIFO_LVL(val, sdd) && loops--);
if (loops == 0)
dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
@@ -204,7 +232,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
loops = msecs_to_loops(1);
do {
val = readl(regs + S3C64XX_SPI_STATUS);
- if (RX_FIFO_LVL(val, sci))
+ if (RX_FIFO_LVL(val, sdd))
readl(regs + S3C64XX_SPI_RX_DATA);
else
break;
@@ -302,7 +330,6 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
struct spi_device *spi,
struct spi_transfer *xfer, int dma_mode)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
void __iomem *regs = sdd->regs;
u32 modecfg, chcfg;
@@ -352,7 +379,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
if (xfer->rx_buf != NULL) {
sdd->state |= RXBUSY;
- if (sci->high_speed && sdd->cur_speed >= 30000000UL
+ if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
&& !(sdd->cur_mode & SPI_CPHA))
chcfg |= S3C64XX_SPI_CH_HS_EN;
@@ -392,7 +419,6 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
struct spi_transfer *xfer, int dma_mode)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
void __iomem *regs = sdd->regs;
unsigned long val;
int ms;
@@ -409,7 +435,7 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
val = msecs_to_loops(ms);
do {
status = readl(regs + S3C64XX_SPI_STATUS);
- } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
+ } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
}
if (!val)
@@ -428,8 +454,8 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
if (xfer->rx_buf == NULL) {
val = msecs_to_loops(10);
status = readl(regs + S3C64XX_SPI_STATUS);
- while ((TX_FIFO_LVL(status, sci)
- || !S3C64XX_SPI_ST_TX_DONE(status, sci))
+ while ((TX_FIFO_LVL(status, sdd)
+ || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
&& --val) {
cpu_relax();
status = readl(regs + S3C64XX_SPI_STATUS);
@@ -478,12 +504,11 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
void __iomem *regs = sdd->regs;
u32 val;
/* Disable Clock */
- if (sci->clk_from_cmu) {
+ if (sdd->port_conf->clk_from_cmu) {
clk_disable(sdd->src_clk);
} else {
val = readl(regs + S3C64XX_SPI_CLK_CFG);
@@ -527,7 +552,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
writel(val, regs + S3C64XX_SPI_MODE_CFG);
- if (sci->clk_from_cmu) {
+ if (sdd->port_conf->clk_from_cmu) {
/* Configure Clock */
/* There is half-multiplier before the SPI */
clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
@@ -553,7 +578,6 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
struct spi_message *msg)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
struct device *dev = &sdd->pdev->dev;
struct spi_transfer *xfer;
@@ -569,7 +593,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
/* Map until end or first fail */
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
- if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
+ if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
continue;
if (xfer->tx_buf != NULL) {
@@ -603,7 +627,6 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
struct spi_message *msg)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
struct device *dev = &sdd->pdev->dev;
struct spi_transfer *xfer;
@@ -612,7 +635,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
- if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
+ if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
continue;
if (xfer->rx_buf != NULL
@@ -631,7 +654,6 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
struct spi_message *msg)
{
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
struct spi_device *spi = msg->spi;
struct s3c64xx_spi_csinfo *cs = spi->controller_data;
struct spi_transfer *xfer;
@@ -686,7 +708,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
}
/* Polling method for xfers not bigger than FIFO capacity */
- if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
+ if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
use_dma = 0;
else
use_dma = 1;
@@ -840,7 +862,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
pm_runtime_get_sync(&sdd->pdev->dev);
/* Check if we can provide the requested rate */
- if (!sci->clk_from_cmu) {
+ if (!sdd->port_conf->clk_from_cmu) {
u32 psr, speed;
/* Max possible */
@@ -921,7 +943,7 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
/* Disable Interrupts - we use Polling if not DMA mode */
writel(0, regs + S3C64XX_SPI_INT_EN);
- if (!sci->clk_from_cmu)
+ if (!sdd->port_conf->clk_from_cmu)
writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
regs + S3C64XX_SPI_CLK_CFG);
writel(0, regs + S3C64XX_SPI_MODE_CFG);
@@ -942,6 +964,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
flush_fifo(sdd);
}
+static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
+ struct platform_device *pdev)
+{
+ return (struct s3c64xx_spi_port_config *)
+ platform_get_device_id(pdev)->driver_data;
+}
+
static int __init s3c64xx_spi_probe(struct platform_device *pdev)
{
struct resource *mem_res, *dmatx_res, *dmarx_res;
@@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, master);
sdd = spi_master_get_devdata(master);
+ sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
sdd->master = master;
sdd->cntrlr_info = sci;
sdd->pdev = pdev;
@@ -1008,10 +1038,11 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
sdd->tx_dma.direction = DMA_MEM_TO_DEV;
sdd->rx_dma.dmach = dmarx_res->start;
sdd->rx_dma.direction = DMA_DEV_TO_MEM;
+ sdd->port_id = pdev->id;
sdd->cur_bpw = 8;
- master->bus_num = pdev->id;
+ master->bus_num = sdd->port_id;
master->setup = s3c64xx_spi_setup;
master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
master->transfer_one_message = s3c64xx_spi_transfer_one_message;
@@ -1071,7 +1102,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
}
/* Setup Deufult Mode */
- s3c64xx_spi_hwinit(sdd, pdev->id);
+ s3c64xx_spi_hwinit(sdd, sdd->port_id);
spin_lock_init(&sdd->lock);
init_completion(&sdd->xfer_completion);
@@ -1096,7 +1127,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
"with %d Slaves attached\n",
- pdev->id, master->num_chipselect);
+ sdd->port_id, master->num_chipselect);
dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
mem_res->end, mem_res->start,
sdd->rx_dma.dmach, sdd->tx_dma.dmach);
@@ -1189,7 +1220,7 @@ static int s3c64xx_spi_resume(struct device *dev)
clk_enable(sdd->src_clk);
clk_enable(sdd->clk);
- s3c64xx_spi_hwinit(sdd, pdev->id);
+ s3c64xx_spi_hwinit(sdd, sdd->port_id);
spi_master_resume(master);
@@ -1227,6 +1258,100 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
s3c64xx_spi_runtime_resume, NULL)
};
+#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
+struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
+ .fifo_lvl_mask = { 0x7f },
+ .rx_lvl_offset = 13,
+ .tx_st_done = 21,
+ .high_speed = true,
+};
+#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c2443_spi_port_config)
+#else
+#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
+ .fifo_lvl_mask = { 0x7f, 0x7F },
+ .rx_lvl_offset = 13,
+ .tx_st_done = 21,
+};
+#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c6410_spi_port_config)
+#else
+#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S3C64XX */
+
+#ifdef CONFIG_ARCH_S5P64X0
+struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
+ .fifo_lvl_mask = { 0x1ff, 0x7F },
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+};
+#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)&s5p64x0_spi_port_config)
+#else
+#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S5P64X0 */
+
+#ifdef CONFIG_ARCH_S5PC100
+struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
+ .fifo_lvl_mask = { 0x7f, 0x7F },
+ .rx_lvl_offset = 13,
+ .tx_st_done = 21,
+ .high_speed = true,
+};
+#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pc100_spi_port_config)
+#else
+#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S5PC100 */
+
+#ifdef CONFIG_ARCH_S5PV210
+struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
+ .fifo_lvl_mask = { 0x1ff, 0x7F },
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+ .high_speed = 1,
+};
+#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pv210_spi_port_config)
+#else
+#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S5PV210 */
+
+#ifdef CONFIG_ARCH_EXYNOS4
+struct s3c64xx_spi_port_config exynos4_spi_port_config = {
+ .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+ .high_speed = 1,
+ .clk_from_cmu = true,
+};
+#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)&exynos4_spi_port_config)
+#else
+#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_EXYNOS4 */
+
+static struct platform_device_id s3c64xx_spi_driver_ids[] = {
+ {
+ .name = "s3c2443-spi",
+ .driver_data = S3C2443_SPI_PORT_CONFIG,
+ }, {
+ .name = "s3c6410-spi",
+ .driver_data = S3C6410_SPI_PORT_CONFIG,
+ }, {
+ .name = "s5p64x0-spi",
+ .driver_data = S5P64X0_SPI_PORT_CONFIG,
+ }, {
+ .name = "s5pc100-spi",
+ .driver_data = S5PC100_SPI_PORT_CONFIG,
+ }, {
+ .name = "s5pv210-spi",
+ .driver_data = S5PV210_SPI_PORT_CONFIG,
+ }, {
+ .name = "exynos4210-spi",
+ .driver_data = EXYNOS4_SPI_PORT_CONFIG,
+ },
+ { },
+};
+
static struct platform_driver s3c64xx_spi_driver = {
.driver = {
.name = "s3c64xx-spi",
@@ -1234,6 +1359,7 @@ static struct platform_driver s3c64xx_spi_driver = {
.pm = &s3c64xx_spi_pm,
},
.remove = s3c64xx_spi_remove,
+ .id_table = s3c64xx_spi_driver_ids,
};
MODULE_ALIAS("platform:s3c64xx-spi");
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 02/10] spi: s3c64xx: move controller information into driver data
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
Platform data is used to specify controller hardware specific information
such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
information is not suitable to be supplied from device tree. Instead,
it can be moved into the driver data and removed from platform data.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
drivers/spi/spi-s3c64xx.c | 180 ++++++++++++++++++++++++++++++++++++++-------
1 files changed, 153 insertions(+), 27 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 6a3d51a..f6bc0e3 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -31,6 +31,8 @@
#include <mach/dma.h>
#include <plat/s3c64xx-spi.h>
+#define MAX_SPI_PORTS 3
+
/* Registers and bit-fields */
#define S3C64XX_SPI_CH_CFG 0x00
@@ -113,9 +115,12 @@
#define S3C64XX_SPI_FBCLK_MSK (3<<0)
-#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
-#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
-#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
+#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
+#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
+ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
+#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
+#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
+ FIFO_LVL_MASK(i))
#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
#define S3C64XX_SPI_TRAILCNT_OFF 19
@@ -134,6 +139,28 @@ struct s3c64xx_spi_dma_data {
};
/**
+ * struct s3c64xx_spi_info - SPI Controller hardware info
+ * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
+ * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
+ * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
+ * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
+ * @clk_from_cmu: True, if the controller does not include a clock mux and
+ * prescaler unit.
+ *
+ * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
+ * differ in some aspects such as the size of the fifo and spi bus clock
+ * setup. Such differences are specified to the driver using this structure
+ * which is provided as driver data to the driver.
+ */
+struct s3c64xx_spi_port_config {
+ int fifo_lvl_mask[MAX_SPI_PORTS];
+ int rx_lvl_offset;
+ int tx_st_done;
+ bool high_speed;
+ bool clk_from_cmu;
+};
+
+/**
* struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
* @clk: Pointer to the spi clock.
* @src_clk: Pointer to the clock used to generate SPI signals.
@@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data {
struct s3c64xx_spi_dma_data rx_dma;
struct s3c64xx_spi_dma_data tx_dma;
struct samsung_dma_ops *ops;
+ struct s3c64xx_spi_port_config *port_conf;
+ unsigned port_id;
};
static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
@@ -179,7 +208,6 @@ static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
void __iomem *regs = sdd->regs;
unsigned long loops;
u32 val;
@@ -195,7 +223,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
loops = msecs_to_loops(1);
do {
val = readl(regs + S3C64XX_SPI_STATUS);
- } while (TX_FIFO_LVL(val, sci) && loops--);
+ } while (TX_FIFO_LVL(val, sdd) && loops--);
if (loops == 0)
dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
@@ -204,7 +232,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
loops = msecs_to_loops(1);
do {
val = readl(regs + S3C64XX_SPI_STATUS);
- if (RX_FIFO_LVL(val, sci))
+ if (RX_FIFO_LVL(val, sdd))
readl(regs + S3C64XX_SPI_RX_DATA);
else
break;
@@ -302,7 +330,6 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
struct spi_device *spi,
struct spi_transfer *xfer, int dma_mode)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
void __iomem *regs = sdd->regs;
u32 modecfg, chcfg;
@@ -352,7 +379,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
if (xfer->rx_buf != NULL) {
sdd->state |= RXBUSY;
- if (sci->high_speed && sdd->cur_speed >= 30000000UL
+ if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
&& !(sdd->cur_mode & SPI_CPHA))
chcfg |= S3C64XX_SPI_CH_HS_EN;
@@ -392,7 +419,6 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
struct spi_transfer *xfer, int dma_mode)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
void __iomem *regs = sdd->regs;
unsigned long val;
int ms;
@@ -409,7 +435,7 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
val = msecs_to_loops(ms);
do {
status = readl(regs + S3C64XX_SPI_STATUS);
- } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
+ } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
}
if (!val)
@@ -428,8 +454,8 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
if (xfer->rx_buf == NULL) {
val = msecs_to_loops(10);
status = readl(regs + S3C64XX_SPI_STATUS);
- while ((TX_FIFO_LVL(status, sci)
- || !S3C64XX_SPI_ST_TX_DONE(status, sci))
+ while ((TX_FIFO_LVL(status, sdd)
+ || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
&& --val) {
cpu_relax();
status = readl(regs + S3C64XX_SPI_STATUS);
@@ -478,12 +504,11 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
void __iomem *regs = sdd->regs;
u32 val;
/* Disable Clock */
- if (sci->clk_from_cmu) {
+ if (sdd->port_conf->clk_from_cmu) {
clk_disable(sdd->src_clk);
} else {
val = readl(regs + S3C64XX_SPI_CLK_CFG);
@@ -527,7 +552,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
writel(val, regs + S3C64XX_SPI_MODE_CFG);
- if (sci->clk_from_cmu) {
+ if (sdd->port_conf->clk_from_cmu) {
/* Configure Clock */
/* There is half-multiplier before the SPI */
clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
@@ -553,7 +578,6 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
struct spi_message *msg)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
struct device *dev = &sdd->pdev->dev;
struct spi_transfer *xfer;
@@ -569,7 +593,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
/* Map until end or first fail */
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
- if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
+ if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
continue;
if (xfer->tx_buf != NULL) {
@@ -603,7 +627,6 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
struct spi_message *msg)
{
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
struct device *dev = &sdd->pdev->dev;
struct spi_transfer *xfer;
@@ -612,7 +635,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
- if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
+ if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
continue;
if (xfer->rx_buf != NULL
@@ -631,7 +654,6 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
struct spi_message *msg)
{
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
- struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
struct spi_device *spi = msg->spi;
struct s3c64xx_spi_csinfo *cs = spi->controller_data;
struct spi_transfer *xfer;
@@ -686,7 +708,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
}
/* Polling method for xfers not bigger than FIFO capacity */
- if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
+ if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
use_dma = 0;
else
use_dma = 1;
@@ -840,7 +862,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
pm_runtime_get_sync(&sdd->pdev->dev);
/* Check if we can provide the requested rate */
- if (!sci->clk_from_cmu) {
+ if (!sdd->port_conf->clk_from_cmu) {
u32 psr, speed;
/* Max possible */
@@ -921,7 +943,7 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
/* Disable Interrupts - we use Polling if not DMA mode */
writel(0, regs + S3C64XX_SPI_INT_EN);
- if (!sci->clk_from_cmu)
+ if (!sdd->port_conf->clk_from_cmu)
writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
regs + S3C64XX_SPI_CLK_CFG);
writel(0, regs + S3C64XX_SPI_MODE_CFG);
@@ -942,6 +964,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
flush_fifo(sdd);
}
+static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
+ struct platform_device *pdev)
+{
+ return (struct s3c64xx_spi_port_config *)
+ platform_get_device_id(pdev)->driver_data;
+}
+
static int __init s3c64xx_spi_probe(struct platform_device *pdev)
{
struct resource *mem_res, *dmatx_res, *dmarx_res;
@@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, master);
sdd = spi_master_get_devdata(master);
+ sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
sdd->master = master;
sdd->cntrlr_info = sci;
sdd->pdev = pdev;
@@ -1008,10 +1038,11 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
sdd->tx_dma.direction = DMA_MEM_TO_DEV;
sdd->rx_dma.dmach = dmarx_res->start;
sdd->rx_dma.direction = DMA_DEV_TO_MEM;
+ sdd->port_id = pdev->id;
sdd->cur_bpw = 8;
- master->bus_num = pdev->id;
+ master->bus_num = sdd->port_id;
master->setup = s3c64xx_spi_setup;
master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
master->transfer_one_message = s3c64xx_spi_transfer_one_message;
@@ -1071,7 +1102,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
}
/* Setup Deufult Mode */
- s3c64xx_spi_hwinit(sdd, pdev->id);
+ s3c64xx_spi_hwinit(sdd, sdd->port_id);
spin_lock_init(&sdd->lock);
init_completion(&sdd->xfer_completion);
@@ -1096,7 +1127,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
"with %d Slaves attached\n",
- pdev->id, master->num_chipselect);
+ sdd->port_id, master->num_chipselect);
dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
mem_res->end, mem_res->start,
sdd->rx_dma.dmach, sdd->tx_dma.dmach);
@@ -1189,7 +1220,7 @@ static int s3c64xx_spi_resume(struct device *dev)
clk_enable(sdd->src_clk);
clk_enable(sdd->clk);
- s3c64xx_spi_hwinit(sdd, pdev->id);
+ s3c64xx_spi_hwinit(sdd, sdd->port_id);
spi_master_resume(master);
@@ -1227,6 +1258,100 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
s3c64xx_spi_runtime_resume, NULL)
};
+#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
+struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
+ .fifo_lvl_mask = { 0x7f },
+ .rx_lvl_offset = 13,
+ .tx_st_done = 21,
+ .high_speed = true,
+};
+#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c2443_spi_port_config)
+#else
+#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
+ .fifo_lvl_mask = { 0x7f, 0x7F },
+ .rx_lvl_offset = 13,
+ .tx_st_done = 21,
+};
+#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c6410_spi_port_config)
+#else
+#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S3C64XX */
+
+#ifdef CONFIG_ARCH_S5P64X0
+struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
+ .fifo_lvl_mask = { 0x1ff, 0x7F },
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+};
+#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)&s5p64x0_spi_port_config)
+#else
+#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S5P64X0 */
+
+#ifdef CONFIG_ARCH_S5PC100
+struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
+ .fifo_lvl_mask = { 0x7f, 0x7F },
+ .rx_lvl_offset = 13,
+ .tx_st_done = 21,
+ .high_speed = true,
+};
+#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pc100_spi_port_config)
+#else
+#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S5PC100 */
+
+#ifdef CONFIG_ARCH_S5PV210
+struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
+ .fifo_lvl_mask = { 0x1ff, 0x7F },
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+ .high_speed = 1,
+};
+#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pv210_spi_port_config)
+#else
+#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S5PV210 */
+
+#ifdef CONFIG_ARCH_EXYNOS4
+struct s3c64xx_spi_port_config exynos4_spi_port_config = {
+ .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+ .high_speed = 1,
+ .clk_from_cmu = true,
+};
+#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)&exynos4_spi_port_config)
+#else
+#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_EXYNOS4 */
+
+static struct platform_device_id s3c64xx_spi_driver_ids[] = {
+ {
+ .name = "s3c2443-spi",
+ .driver_data = S3C2443_SPI_PORT_CONFIG,
+ }, {
+ .name = "s3c6410-spi",
+ .driver_data = S3C6410_SPI_PORT_CONFIG,
+ }, {
+ .name = "s5p64x0-spi",
+ .driver_data = S5P64X0_SPI_PORT_CONFIG,
+ }, {
+ .name = "s5pc100-spi",
+ .driver_data = S5PC100_SPI_PORT_CONFIG,
+ }, {
+ .name = "s5pv210-spi",
+ .driver_data = S5PV210_SPI_PORT_CONFIG,
+ }, {
+ .name = "exynos4210-spi",
+ .driver_data = EXYNOS4_SPI_PORT_CONFIG,
+ },
+ { },
+};
+
static struct platform_driver s3c64xx_spi_driver = {
.driver = {
.name = "s3c64xx-spi",
@@ -1234,6 +1359,7 @@ static struct platform_driver s3c64xx_spi_driver = {
.pm = &s3c64xx_spi_pm,
},
.remove = s3c64xx_spi_remove,
+ .id_table = s3c64xx_spi_driver_ids,
};
MODULE_ALIAS("platform:s3c64xx-spi");
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 03/10] ARM: Samsung: Remove spi hardware controller information from platform data
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
With the spi hardware controller information moved to spi driver data,
this information can be removed from the spi platform data.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/setup-spi.c | 25 ----------------------
arch/arm/mach-s3c24xx/setup-spi.c | 8 -------
arch/arm/mach-s3c64xx/setup-spi.c | 13 -----------
arch/arm/mach-s5p64x0/setup-spi.c | 16 --------------
arch/arm/mach-s5pc100/setup-spi.c | 22 -------------------
arch/arm/mach-s5pv210/setup-spi.c | 15 -------------
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 15 -------------
7 files changed, 0 insertions(+), 114 deletions(-)
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
index 833ff40..a71ec4d 100644
--- a/arch/arm/mach-exynos/setup-spi.c
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -12,17 +12,8 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x1ff,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .clk_from_cmu = true,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
@@ -34,14 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .clk_from_cmu = true,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
@@ -53,14 +36,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .clk_from_cmu = true,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
index 5712c85..42abe15 100644
--- a/arch/arm/mach-s3c24xx/setup-spi.c
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -13,19 +13,11 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .tx_st_done = 21,
- .high_speed = 1,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
{
/* enable hsspi bit in misccr */
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index d9592ad..ff999d9 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -12,15 +12,8 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
@@ -30,12 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
index e9b8412..1cf84b5 100644
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -10,19 +10,9 @@
#include <linux/gpio.h>
#include <linux/platform_device.h>
-#include <linux/io.h>
-
#include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x1ff,
- .rx_lvl_offset = 15,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
if (soc_is_s5p6450())
@@ -36,12 +26,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 15,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
if (soc_is_s5p6450())
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
index 431a6f7..4b42718 100644
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -12,16 +12,8 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .high_speed = 1,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
@@ -31,13 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .high_speed = 1,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
@@ -47,13 +32,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .high_speed = 1,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
index f43c504..2cd66a6 100644
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -12,16 +12,8 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
- .fifo_lvl_mask = 0x1ff,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
@@ -33,13 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index fa95e9a..4e9b9c3 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -33,28 +33,13 @@ struct s3c64xx_spi_csinfo {
/**
* struct s3c64xx_spi_info - SPI Controller defining structure
* @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @clk_from_cmu: If the SPI clock/prescalar control block is present
- * by the platform's clock-management-unit and not in SPI controller.
* @num_cs: Number of CS this controller emulates.
* @cfg_gpio: Configure pins for this SPI controller.
- * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
- * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
- * @high_speed: If the controller supports HIGH_SPEED_EN bit
- * @tx_st_done: Depends on tx fifo_lvl field
*/
struct s3c64xx_spi_info {
int src_clk_nr;
- bool clk_from_cmu;
-
int num_cs;
-
int (*cfg_gpio)(struct platform_device *pdev);
-
- /* Following two fields are for future compatibility */
- int fifo_lvl_mask;
- int rx_lvl_offset;
- int high_speed;
- int tx_st_done;
};
/**
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 03/10] ARM: Samsung: Remove spi hardware controller information from platform data
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
With the spi hardware controller information moved to spi driver data,
this information can be removed from the spi platform data.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/setup-spi.c | 25 ----------------------
arch/arm/mach-s3c24xx/setup-spi.c | 8 -------
arch/arm/mach-s3c64xx/setup-spi.c | 13 -----------
arch/arm/mach-s5p64x0/setup-spi.c | 16 --------------
arch/arm/mach-s5pc100/setup-spi.c | 22 -------------------
arch/arm/mach-s5pv210/setup-spi.c | 15 -------------
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 15 -------------
7 files changed, 0 insertions(+), 114 deletions(-)
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
index 833ff40..a71ec4d 100644
--- a/arch/arm/mach-exynos/setup-spi.c
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -12,17 +12,8 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x1ff,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .clk_from_cmu = true,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
@@ -34,14 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .clk_from_cmu = true,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
@@ -53,14 +36,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .clk_from_cmu = true,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
index 5712c85..42abe15 100644
--- a/arch/arm/mach-s3c24xx/setup-spi.c
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -13,19 +13,11 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .tx_st_done = 21,
- .high_speed = 1,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
{
/* enable hsspi bit in misccr */
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index d9592ad..ff999d9 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -12,15 +12,8 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
@@ -30,12 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
index e9b8412..1cf84b5 100644
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -10,19 +10,9 @@
#include <linux/gpio.h>
#include <linux/platform_device.h>
-#include <linux/io.h>
-
#include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x1ff,
- .rx_lvl_offset = 15,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
if (soc_is_s5p6450())
@@ -36,12 +26,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 15,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
if (soc_is_s5p6450())
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
index 431a6f7..4b42718 100644
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -12,16 +12,8 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .high_speed = 1,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
@@ -31,13 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .high_speed = 1,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
@@ -47,13 +32,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 13,
- .high_speed = 1,
- .tx_st_done = 21,
-};
-
int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
index f43c504..2cd66a6 100644
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -12,16 +12,8 @@
#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
- .fifo_lvl_mask = 0x1ff,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
@@ -33,13 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
- .fifo_lvl_mask = 0x7f,
- .rx_lvl_offset = 15,
- .high_speed = 1,
- .tx_st_done = 25,
-};
-
int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index fa95e9a..4e9b9c3 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -33,28 +33,13 @@ struct s3c64xx_spi_csinfo {
/**
* struct s3c64xx_spi_info - SPI Controller defining structure
* @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @clk_from_cmu: If the SPI clock/prescalar control block is present
- * by the platform's clock-management-unit and not in SPI controller.
* @num_cs: Number of CS this controller emulates.
* @cfg_gpio: Configure pins for this SPI controller.
- * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
- * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
- * @high_speed: If the controller supports HIGH_SPEED_EN bit
- * @tx_st_done: Depends on tx fifo_lvl field
*/
struct s3c64xx_spi_info {
int src_clk_nr;
- bool clk_from_cmu;
-
int num_cs;
-
int (*cfg_gpio)(struct platform_device *pdev);
-
- /* Following two fields are for future compatibility */
- int fifo_lvl_mask;
- int rx_lvl_offset;
- int high_speed;
- int tx_st_done;
};
/**
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 04/10] ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
The platform data pointer that is passed to the spi gpio setup functions
is not used. Hence, this paremeter is removed from all the spi gpio setup
functions.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/setup-spi.c | 8 +++-----
arch/arm/mach-s3c24xx/setup-spi.c | 2 +-
arch/arm/mach-s3c64xx/setup-spi.c | 6 ++----
arch/arm/mach-s5p64x0/setup-spi.c | 5 ++---
arch/arm/mach-s5pc100/setup-spi.c | 8 +++-----
arch/arm/mach-s5pv210/setup-spi.c | 6 ++----
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 8 ++++----
7 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
index a71ec4d..4999829 100644
--- a/arch/arm/mach-exynos/setup-spi.c
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -9,12 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
@@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
@@ -36,7 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
{
s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
index 42abe15..3d47e02 100644
--- a/arch/arm/mach-s3c24xx/setup-spi.c
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -18,7 +18,7 @@
#include <mach/regs-gpio.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
+int s3c64xx_spi0_cfg_gpio(void)
{
/* enable hsspi bit in misccr */
s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index ff999d9..4dc5345 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -9,12 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
index 1cf84b5..7664356 100644
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -9,11 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
if (soc_is_s5p6450())
s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
@@ -26,7 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
if (soc_is_s5p6450())
s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
index 4b42718..1835679 100644
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -9,12 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -32,7 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
{
s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
index 2cd66a6..81aecc1 100644
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -9,12 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
@@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4e9b9c3..89dbaee 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -39,7 +39,7 @@ struct s3c64xx_spi_csinfo {
struct s3c64xx_spi_info {
int src_clk_nr;
int num_cs;
- int (*cfg_gpio)(struct platform_device *pdev);
+ int (*cfg_gpio)(void);
};
/**
@@ -60,9 +60,9 @@ extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
int src_clk_nr, int num_cs);
/* defined by architecture to configure gpio */
-extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
+extern int s3c64xx_spi0_cfg_gpio(void);
+extern int s3c64xx_spi1_cfg_gpio(void);
+extern int s3c64xx_spi2_cfg_gpio(void);
extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 04/10] ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
The platform data pointer that is passed to the spi gpio setup functions
is not used. Hence, this paremeter is removed from all the spi gpio setup
functions.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/setup-spi.c | 8 +++-----
arch/arm/mach-s3c24xx/setup-spi.c | 2 +-
arch/arm/mach-s3c64xx/setup-spi.c | 6 ++----
arch/arm/mach-s5p64x0/setup-spi.c | 5 ++---
arch/arm/mach-s5pc100/setup-spi.c | 8 +++-----
arch/arm/mach-s5pv210/setup-spi.c | 6 ++----
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 8 ++++----
7 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
index a71ec4d..4999829 100644
--- a/arch/arm/mach-exynos/setup-spi.c
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -9,12 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
@@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
@@ -36,7 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
{
s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
index 42abe15..3d47e02 100644
--- a/arch/arm/mach-s3c24xx/setup-spi.c
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -18,7 +18,7 @@
#include <mach/regs-gpio.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
+int s3c64xx_spi0_cfg_gpio(void)
{
/* enable hsspi bit in misccr */
s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index ff999d9..4dc5345 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -9,12 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
index 1cf84b5..7664356 100644
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -9,11 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
if (soc_is_s5p6450())
s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
@@ -26,7 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
if (soc_is_s5p6450())
s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
index 4b42718..1835679 100644
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -9,12 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -32,7 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
{
s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
index 2cd66a6..81aecc1 100644
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -9,12 +9,10 @@
*/
#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
#include <plat/gpio-cfg.h>
#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
@@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
#endif
#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4e9b9c3..89dbaee 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -39,7 +39,7 @@ struct s3c64xx_spi_csinfo {
struct s3c64xx_spi_info {
int src_clk_nr;
int num_cs;
- int (*cfg_gpio)(struct platform_device *pdev);
+ int (*cfg_gpio)(void);
};
/**
@@ -60,9 +60,9 @@ extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
int src_clk_nr, int num_cs);
/* defined by architecture to configure gpio */
-extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
+extern int s3c64xx_spi0_cfg_gpio(void);
+extern int s3c64xx_spi1_cfg_gpio(void);
+extern int s3c64xx_spi2_cfg_gpio(void);
extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
With the addition of platform specific driver data in the spi-s3c64xx
driver, the device name of spi controllers are changed. Accordingly,
update the device name of spi clocks instances.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/clock-exynos4.c | 18 +++++++++---------
arch/arm/mach-s3c24xx/clock-s3c2416.c | 2 +-
arch/arm/mach-s3c24xx/clock-s3c2443.c | 2 +-
arch/arm/mach-s3c24xx/common-s3c2443.c | 4 ++--
arch/arm/mach-s3c64xx/clock.c | 20 ++++++++++----------
arch/arm/mach-s5p64x0/clock-s5p6440.c | 12 ++++++------
arch/arm/mach-s5p64x0/clock-s5p6450.c | 12 ++++++------
arch/arm/mach-s5pc100/clock.c | 30 +++++++++++++++---------------
arch/arm/mach-s5pv210/clock.c | 14 +++++++-------
9 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 6efd1e5..57b5464 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -581,17 +581,17 @@ static struct clk exynos4_init_clocks_off[] = {
.ctrlbit = (1 << 13),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "exynos4210-spi.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "exynos4210-spi.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "exynos4210-spi.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
@@ -1246,7 +1246,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "exynos4210-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
@@ -1258,7 +1258,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi0 = {
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "exynos4210-spi.1",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
@@ -1270,7 +1270,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi1 = {
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "exynos4210-spi.2",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
@@ -1348,9 +1348,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
- CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+ CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+ CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+ CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
};
static int xtal_rate;
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 8702ecf..a582ba1 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,7 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
+ CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
};
void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index a4c5a52..7f689ce 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = {
static struct clk_lookup s3c2443_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
+ CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
};
void __init s3c2443_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index aeeb2be..aeb4a24 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = {
static struct clk hsspi_clk = {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s3c2443-spi.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_HSSPI,
@@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
+ CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
};
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 52f079a..28041e8 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = {
.ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s3c6410-spi.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s3c6410-spi.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = {
static struct clk clk_48m_spi0 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.0",
+ .devname = "s3c6410-spi.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = {
static struct clk clk_48m_spi1 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.1",
+ .devname = "s3c6410-spi.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "spi-bus",
- .devname = "s3c64xx-spi.0",
+ .devname = "s3c6410-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "spi-bus",
- .devname = "s3c64xx-spi.1",
+ .devname = "s3c6410-spi.1",
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl,
},
@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+ CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
+ CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
};
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index ee1e8e7..55ea3ab 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5p64x0-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5p64x0-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
@@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5p64x0-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5p64x0-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s5p64x0.0", "spi_busclk1", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s5p64x0.1", "spi_busclk1", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index dae6a13..f3e0ef3 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5p64x0-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5p64x0-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
@@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5p64x0-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5p64x0-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 16eca4e..9262197 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 5),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pc100-spi.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pc100-spi.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "s5pc100-spi.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 8),
@@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = {
static struct clk clk_48m_spi0 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pc100-spi.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 7),
@@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = {
static struct clk clk_48m_spi1 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pc100-spi.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 8),
@@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = {
static struct clk clk_48m_spi2 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.2",
+ .devname = "s5pc100-spi.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 9),
@@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pc100-spi.0",
.ctrlbit = (1 << 4),
.enable = s5pc100_sclk0_ctrl,
},
@@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pc100-spi.1",
.ctrlbit = (1 << 5),
.enable = s5pc100_sclk0_ctrl,
},
@@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = {
static struct clksrc_clk clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "s5pc100-spi.2",
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
},
@@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
- CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
- CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
+ CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
+ CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
+ CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
+ CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
};
void __init s5pc100_register_clocks(void)
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 09609d5..fcdf52d 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 11),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pv210-spi.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<12),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pv210-spi.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<13),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "s5pv210-spi.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<14),
@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pv210-spi.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16),
},
@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pv210-spi.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17),
},
@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
};
void __init s5pv210_register_clocks(void)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
With the addition of platform specific driver data in the spi-s3c64xx
driver, the device name of spi controllers are changed. Accordingly,
update the device name of spi clocks instances.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/clock-exynos4.c | 18 +++++++++---------
arch/arm/mach-s3c24xx/clock-s3c2416.c | 2 +-
arch/arm/mach-s3c24xx/clock-s3c2443.c | 2 +-
arch/arm/mach-s3c24xx/common-s3c2443.c | 4 ++--
arch/arm/mach-s3c64xx/clock.c | 20 ++++++++++----------
arch/arm/mach-s5p64x0/clock-s5p6440.c | 12 ++++++------
arch/arm/mach-s5p64x0/clock-s5p6450.c | 12 ++++++------
arch/arm/mach-s5pc100/clock.c | 30 +++++++++++++++---------------
arch/arm/mach-s5pv210/clock.c | 14 +++++++-------
9 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 6efd1e5..57b5464 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -581,17 +581,17 @@ static struct clk exynos4_init_clocks_off[] = {
.ctrlbit = (1 << 13),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "exynos4210-spi.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "exynos4210-spi.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "exynos4210-spi.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
@@ -1246,7 +1246,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "exynos4210-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
@@ -1258,7 +1258,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi0 = {
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "exynos4210-spi.1",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
@@ -1270,7 +1270,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi1 = {
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "exynos4210-spi.2",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
@@ -1348,9 +1348,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
- CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+ CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+ CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+ CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
};
static int xtal_rate;
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 8702ecf..a582ba1 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,7 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
+ CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
};
void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index a4c5a52..7f689ce 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = {
static struct clk_lookup s3c2443_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
+ CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
};
void __init s3c2443_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index aeeb2be..aeb4a24 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = {
static struct clk hsspi_clk = {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s3c2443-spi.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_HSSPI,
@@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
+ CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
};
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 52f079a..28041e8 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = {
.ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s3c6410-spi.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s3c6410-spi.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = {
static struct clk clk_48m_spi0 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.0",
+ .devname = "s3c6410-spi.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = {
static struct clk clk_48m_spi1 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.1",
+ .devname = "s3c6410-spi.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "spi-bus",
- .devname = "s3c64xx-spi.0",
+ .devname = "s3c6410-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "spi-bus",
- .devname = "s3c64xx-spi.1",
+ .devname = "s3c6410-spi.1",
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl,
},
@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+ CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
+ CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
};
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index ee1e8e7..55ea3ab 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5p64x0-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5p64x0-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
@@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5p64x0-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5p64x0-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s5p64x0.0", "spi_busclk1", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s5p64x0.1", "spi_busclk1", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index dae6a13..f3e0ef3 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5p64x0-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5p64x0-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
@@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5p64x0-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5p64x0-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 16eca4e..9262197 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 5),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pc100-spi.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pc100-spi.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "s5pc100-spi.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 8),
@@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = {
static struct clk clk_48m_spi0 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pc100-spi.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 7),
@@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = {
static struct clk clk_48m_spi1 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pc100-spi.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 8),
@@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = {
static struct clk clk_48m_spi2 = {
.name = "spi_48m",
- .devname = "s3c64xx-spi.2",
+ .devname = "s5pc100-spi.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 9),
@@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pc100-spi.0",
.ctrlbit = (1 << 4),
.enable = s5pc100_sclk0_ctrl,
},
@@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pc100-spi.1",
.ctrlbit = (1 << 5),
.enable = s5pc100_sclk0_ctrl,
},
@@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = {
static struct clksrc_clk clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "s5pc100-spi.2",
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
},
@@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
- CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
- CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
+ CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
+ CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
+ CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
+ CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
};
void __init s5pc100_register_clocks(void)
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 09609d5..fcdf52d 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 11),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pv210-spi.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<12),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pv210-spi.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<13),
}, {
.name = "spi",
- .devname = "s3c64xx-spi.2",
+ .devname = "s5pv210-spi.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<14),
@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = {
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
+ .devname = "s5pv210-spi.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16),
},
@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
+ .devname = "s5pv210-spi.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17),
},
@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
- CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+ CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+ CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
};
void __init s5pv210_register_clocks(void)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
With the spi controller hardware configuration moved into the driver data, there
are no more default hardware configuration data that is passed through platform
data. Accordingly, the s3c64xx_spi{0|1|2}_set_platdata functions are adapted to
these changes.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
arch/arm/plat-samsung/devs.c | 50 ++++++++-------------
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 6 +-
3 files changed, 23 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index e20bf58..0cea12f 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -793,7 +793,7 @@ static void __init crag6410_machine_init(void)
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
samsung_keypad_set_platdata(&crag6410_keypad_data);
- s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
+ s3c64xx_spi0_set_platdata("s3c6410-spi", NULL, 0, 1);
platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 8b928f9..2deabda 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1534,13 +1534,10 @@ struct platform_device s3c64xx_device_spi0 = {
},
};
-void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
+void __init s3c64xx_spi0_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs)
{
- if (!pd) {
- pr_err("%s:Need to pass platform data\n", __func__);
- return;
- }
+ struct s3c64xx_spi_info pd;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0) {
@@ -1548,12 +1545,11 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
return;
}
- pd->num_cs = num_cs;
- pd->src_clk_nr = src_clk_nr;
- if (!pd->cfg_gpio)
- pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
+ pd.src_clk_nr = src_clk_nr;
+ pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
+ s3c64xx_device_spi0.name = dev_name;
- s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
+ s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
}
#endif /* CONFIG_S3C64XX_DEV_SPI0 */
@@ -1576,26 +1572,21 @@ struct platform_device s3c64xx_device_spi1 = {
},
};
-void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
+void __init s3c64xx_spi1_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs)
{
- if (!pd) {
- pr_err("%s:Need to pass platform data\n", __func__);
- return;
- }
-
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0) {
pr_err("%s: Invalid SPI configuration\n", __func__);
return;
}
- pd->num_cs = num_cs;
- pd->src_clk_nr = src_clk_nr;
- if (!pd->cfg_gpio)
- pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
+ pd.num_cs = num_cs;
+ pd.src_clk_nr = src_clk_nr;
+ pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
+ s3c64xx_device_spi1.name = dev_name;
- s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
+ s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
}
#endif /* CONFIG_S3C64XX_DEV_SPI1 */
@@ -1618,13 +1609,10 @@ struct platform_device s3c64xx_device_spi2 = {
},
};
-void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
+void __init s3c64xx_spi2_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs)
{
- if (!pd) {
- pr_err("%s:Need to pass platform data\n", __func__);
- return;
- }
+ struct s3c64xx_spi_info pd;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0) {
@@ -1632,11 +1620,11 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
return;
}
- pd->num_cs = num_cs;
- pd->src_clk_nr = src_clk_nr;
- if (!pd->cfg_gpio)
- pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
+ pd.num_cs = num_cs;
+ pd.src_clk_nr = src_clk_nr;
+ pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
+ s3c64xx_device_spi2.name = dev_name;
- s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
+ s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
}
#endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 89dbaee..a733ce9 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -52,11 +52,11 @@ struct s3c64xx_spi_info {
* Call this from machine init code for each SPI Controller that
* has some chips attached to it.
*/
-extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
+extern void s3c64xx_spi0_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs);
-extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
+extern void s3c64xx_spi1_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs);
-extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
+extern void s3c64xx_spi2_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs);
/* defined by architecture to configure gpio */
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
With the spi controller hardware configuration moved into the driver data, there
are no more default hardware configuration data that is passed through platform
data. Accordingly, the s3c64xx_spi{0|1|2}_set_platdata functions are adapted to
these changes.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
arch/arm/plat-samsung/devs.c | 50 ++++++++-------------
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 6 +-
3 files changed, 23 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index e20bf58..0cea12f 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -793,7 +793,7 @@ static void __init crag6410_machine_init(void)
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
samsung_keypad_set_platdata(&crag6410_keypad_data);
- s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
+ s3c64xx_spi0_set_platdata("s3c6410-spi", NULL, 0, 1);
platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 8b928f9..2deabda 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1534,13 +1534,10 @@ struct platform_device s3c64xx_device_spi0 = {
},
};
-void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
+void __init s3c64xx_spi0_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs)
{
- if (!pd) {
- pr_err("%s:Need to pass platform data\n", __func__);
- return;
- }
+ struct s3c64xx_spi_info pd;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0) {
@@ -1548,12 +1545,11 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
return;
}
- pd->num_cs = num_cs;
- pd->src_clk_nr = src_clk_nr;
- if (!pd->cfg_gpio)
- pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
+ pd.src_clk_nr = src_clk_nr;
+ pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
+ s3c64xx_device_spi0.name = dev_name;
- s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
+ s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
}
#endif /* CONFIG_S3C64XX_DEV_SPI0 */
@@ -1576,26 +1572,21 @@ struct platform_device s3c64xx_device_spi1 = {
},
};
-void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
+void __init s3c64xx_spi1_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs)
{
- if (!pd) {
- pr_err("%s:Need to pass platform data\n", __func__);
- return;
- }
-
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0) {
pr_err("%s: Invalid SPI configuration\n", __func__);
return;
}
- pd->num_cs = num_cs;
- pd->src_clk_nr = src_clk_nr;
- if (!pd->cfg_gpio)
- pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
+ pd.num_cs = num_cs;
+ pd.src_clk_nr = src_clk_nr;
+ pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
+ s3c64xx_device_spi1.name = dev_name;
- s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
+ s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
}
#endif /* CONFIG_S3C64XX_DEV_SPI1 */
@@ -1618,13 +1609,10 @@ struct platform_device s3c64xx_device_spi2 = {
},
};
-void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
+void __init s3c64xx_spi2_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs)
{
- if (!pd) {
- pr_err("%s:Need to pass platform data\n", __func__);
- return;
- }
+ struct s3c64xx_spi_info pd;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0) {
@@ -1632,11 +1620,11 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
return;
}
- pd->num_cs = num_cs;
- pd->src_clk_nr = src_clk_nr;
- if (!pd->cfg_gpio)
- pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
+ pd.num_cs = num_cs;
+ pd.src_clk_nr = src_clk_nr;
+ pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
+ s3c64xx_device_spi2.name = dev_name;
- s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
+ s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
}
#endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 89dbaee..a733ce9 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -52,11 +52,11 @@ struct s3c64xx_spi_info {
* Call this from machine init code for each SPI Controller that
* has some chips attached to it.
*/
-extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
+extern void s3c64xx_spi0_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs);
-extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
+extern void s3c64xx_spi1_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs);
-extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
+extern void s3c64xx_spi2_set_platdata(char *dev_name, int (*cfg_gpio)(void),
int src_clk_nr, int num_cs);
/* defined by architecture to configure gpio */
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
The set_level callback in the controller data, which is used to configure
the slave select line, cannot be supported when migrating the driver to
device tree based discovery. Since all the platforms currently use gpio
as the slave select line, this callback can be removed from the
controller data and replaced with call to gpio_set_value in the driver.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 2 --
drivers/spi/spi-s3c64xx.c | 8 ++++----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index a733ce9..48a6495 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -18,7 +18,6 @@ struct platform_device;
* @fb_delay: Slave specific feedback delay.
* Refer to FB_CLK_SEL register definition in SPI chapter.
* @line: Custom 'identity' of the CS line.
- * @set_level: CS line control.
*
* This is per SPI-Slave Chipselect information.
* Allocate and initialize one in machine init code and make the
@@ -27,7 +26,6 @@ struct platform_device;
struct s3c64xx_spi_csinfo {
u8 fb_delay;
unsigned line;
- void (*set_level)(unsigned line_id, int lvl);
};
/**
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index f6bc0e3..d84ce7f 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -406,14 +406,14 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
/* Deselect the last toggled device */
cs = sdd->tgl_spi->controller_data;
- cs->set_level(cs->line,
- spi->mode & SPI_CS_HIGH ? 0 : 1);
+ gpio_set_value(cs->line,
+ spi->mode & SPI_CS_HIGH ? 0 : 1);
}
sdd->tgl_spi = NULL;
}
cs = spi->controller_data;
- cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
+ gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
}
static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
@@ -499,7 +499,7 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
if (sdd->tgl_spi == spi)
sdd->tgl_spi = NULL;
- cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
+ gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
}
static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
The set_level callback in the controller data, which is used to configure
the slave select line, cannot be supported when migrating the driver to
device tree based discovery. Since all the platforms currently use gpio
as the slave select line, this callback can be removed from the
controller data and replaced with call to gpio_set_value in the driver.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 2 --
drivers/spi/spi-s3c64xx.c | 8 ++++----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index a733ce9..48a6495 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -18,7 +18,6 @@ struct platform_device;
* @fb_delay: Slave specific feedback delay.
* Refer to FB_CLK_SEL register definition in SPI chapter.
* @line: Custom 'identity' of the CS line.
- * @set_level: CS line control.
*
* This is per SPI-Slave Chipselect information.
* Allocate and initialize one in machine init code and make the
@@ -27,7 +26,6 @@ struct platform_device;
struct s3c64xx_spi_csinfo {
u8 fb_delay;
unsigned line;
- void (*set_level)(unsigned line_id, int lvl);
};
/**
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index f6bc0e3..d84ce7f 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -406,14 +406,14 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
/* Deselect the last toggled device */
cs = sdd->tgl_spi->controller_data;
- cs->set_level(cs->line,
- spi->mode & SPI_CS_HIGH ? 0 : 1);
+ gpio_set_value(cs->line,
+ spi->mode & SPI_CS_HIGH ? 0 : 1);
}
sdd->tgl_spi = NULL;
}
cs = spi->controller_data;
- cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
+ gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
}
static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
@@ -499,7 +499,7 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
if (sdd->tgl_spi == spi)
sdd->tgl_spi = NULL;
- cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
+ gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
}
static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 08/10] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
The sclk_spi clock is derived currently from the first level divider
(MMCx_RATIO) which is incorrect. The output of the first level clock
is divided by a second level divider (MMCx_PRE_RATIO), the output of
which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
issues for the sclk_spi clock.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/clock-exynos4.c | 48 ++++++++++++++++++++++++++++-----
1 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 57b5464..331186e 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -1243,40 +1243,70 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
+static struct clksrc_clk exynos4_clk_mdout_spi0 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+
+};
+
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.0",
+ .parent = &exynos4_clk_mdout_spi0.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi1 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.1",
+ },
.sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+
};
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.1",
+ .parent = &exynos4_clk_mdout_spi1.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi2 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.2",
+ },
.sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+
};
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.2",
+ .parent = &exynos4_clk_mdout_spi2.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
- .sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
};
/* Clock initialization code */
@@ -1332,7 +1362,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
&exynos4_clk_sclk_spi0,
&exynos4_clk_sclk_spi1,
&exynos4_clk_sclk_spi2,
-
+ &exynos4_clk_mdout_spi0,
+ &exynos4_clk_mdout_spi1,
+ &exynos4_clk_mdout_spi2,
};
static struct clk_lookup exynos4_clk_lookup[] = {
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 08/10] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
The sclk_spi clock is derived currently from the first level divider
(MMCx_RATIO) which is incorrect. The output of the first level clock
is divided by a second level divider (MMCx_PRE_RATIO), the output of
which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
issues for the sclk_spi clock.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/clock-exynos4.c | 48 ++++++++++++++++++++++++++++-----
1 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 57b5464..331186e 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -1243,40 +1243,70 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
+static struct clksrc_clk exynos4_clk_mdout_spi0 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+
+};
+
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.0",
+ .parent = &exynos4_clk_mdout_spi0.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi1 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.1",
+ },
.sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+
};
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.1",
+ .parent = &exynos4_clk_mdout_spi1.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi2 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.2",
+ },
.sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+
};
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.2",
+ .parent = &exynos4_clk_mdout_spi2.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
- .sources = &exynos4_clkset_group,
- .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
- .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
};
/* Clock initialization code */
@@ -1332,7 +1362,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
&exynos4_clk_sclk_spi0,
&exynos4_clk_sclk_spi1,
&exynos4_clk_sclk_spi2,
-
+ &exynos4_clk_mdout_spi0,
+ &exynos4_clk_mdout_spi1,
+ &exynos4_clk_mdout_spi2,
};
static struct clk_lookup exynos4_clk_lookup[] = {
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 09/10] ARM: Exynos5: Add spi clock support
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
Add support for clock instances for each spi controller.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/clock-exynos5.c | 98 ++++++++++++++++++++++++
arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
2 files changed, 102 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 7c0f810..0293beb 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
}
+static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
+}
+
static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
@@ -700,6 +705,24 @@ static struct clk exynos5_init_clocks_off[] = {
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 14),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 18),
}
};
@@ -924,6 +947,72 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
+static struct clksrc_clk exynos5_clk_mdout_spi0 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_mdout_spi0.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi1 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.1",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_mdout_spi1.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi2 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.2",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi2 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_mdout_spi2.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
+};
+
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk = {
@@ -1055,6 +1144,12 @@ static struct clksrc_clk *exynos5_clksrc_cdev[] = {
&exynos5_clk_sclk_mmc1,
&exynos5_clk_sclk_mmc2,
&exynos5_clk_sclk_mmc3,
+ &exynos5_clk_mdout_spi0,
+ &exynos5_clk_sclk_spi0,
+ &exynos5_clk_mdout_spi1,
+ &exynos5_clk_sclk_spi1,
+ &exynos5_clk_mdout_spi2,
+ &exynos5_clk_sclk_spi2,
};
static struct clk_lookup exynos5_clk_lookup[] = {
@@ -1066,6 +1161,9 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+ CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
+ CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
+ CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 130034d..8ff7d83 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -284,12 +284,14 @@
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
+#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
+#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
@@ -301,6 +303,8 @@
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
+#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
+#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 09/10] ARM: Exynos5: Add spi clock support
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
Add support for clock instances for each spi controller.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/clock-exynos5.c | 98 ++++++++++++++++++++++++
arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
2 files changed, 102 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 7c0f810..0293beb 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
}
+static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
+}
+
static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
@@ -700,6 +705,24 @@ static struct clk exynos5_init_clocks_off[] = {
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 14),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 18),
}
};
@@ -924,6 +947,72 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
+static struct clksrc_clk exynos5_clk_mdout_spi0 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_mdout_spi0.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi1 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.1",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_mdout_spi1.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi2 = {
+ .clk = {
+ .name = "sclk_spi_mdout",
+ .devname = "exynos4210-spi.2",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
+
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi2 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_mdout_spi2.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
+};
+
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk = {
@@ -1055,6 +1144,12 @@ static struct clksrc_clk *exynos5_clksrc_cdev[] = {
&exynos5_clk_sclk_mmc1,
&exynos5_clk_sclk_mmc2,
&exynos5_clk_sclk_mmc3,
+ &exynos5_clk_mdout_spi0,
+ &exynos5_clk_sclk_spi0,
+ &exynos5_clk_mdout_spi1,
+ &exynos5_clk_sclk_spi1,
+ &exynos5_clk_mdout_spi2,
+ &exynos5_clk_sclk_spi2,
};
static struct clk_lookup exynos5_clk_lookup[] = {
@@ -1066,6 +1161,9 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+ CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
+ CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
+ CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 130034d..8ff7d83 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -284,12 +284,14 @@
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
+#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
+#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
@@ -301,6 +303,8 @@
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
+#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
+#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 10/10] spi: s3c64xx: add device tree support
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-08 22:04 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim, jaswinder.singh
Add support for device based discovery.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
.../devicetree/bindings/spi/spi-samsung.txt | 113 ++++++++
drivers/spi/spi-s3c64xx.c | 277 +++++++++++++++++---
2 files changed, 358 insertions(+), 32 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
new file mode 100644
index 0000000..2046c30
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -0,0 +1,113 @@
+* Samsung SPI Controller
+
+The Samsung SPI controller is used to interface with various devices such as flash
+and display controllers using the SPI communication interface.
+
+Required SoC Specific Properties:
+
+- compatible: should be one of the following.
+ - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
+ - samsung,s3c6410-spi: for s3c6410 platforms
+ - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms
+ - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
+ - samsung,exynos4210-spi: for exynos4 and exynos5 platforms
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- interrupts: The interrupt number to the cpu. The interrupt specifier format
+ depends on the interrupt controller.
+
+- tx-dma-channel: The dma channel specifier for tx operations. The format of
+ the dma specifier depends on the dma controller.
+
+- rx-dma-channel: The dma channel specifier for rx operations. The format of
+ the dma specifier depends on the dma controller.
+
+Required Board Specific Properties:
+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
+ particular order). The format of the gpio specifier depends on the gpio
+ controller.
+
+Optional Board Specific Properties:
+
+- samsung,spi-src-clk: If the spi controller includes a internal clock mux to
+ select the clock source for the spi bus clock, this property can be used to
+ indicate the clock to be used for driving the spi bus clock. If not specified,
+ the clock number 0 is used as default.
+
+- samsung,spi-num-cs: Specifies the number of chip select lines supported. If
+ not specified, the default number of chip select lines is set to 1.
+
+SPI Controller specific data in SPI slave nodes:
+
+- The spi slave nodes should provide the following information which is required
+ by the spi controller.
+
+ - samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
+ the slave select line by the spi controller. The format of the gpio
+ specifier depends on the gpio controller.
+
+ - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
+ miso line (to account for any lag in the miso line). The following are the
+ valid values.
+
+ - 0: No phase shift.
+ - 1: 90 degree phase shift sampling.
+ - 2: 180 degree phase shift sampling.
+ - 3: 270 degree phase shift sampling.
+
+Aliases:
+
+- All the SPI controller nodes should be represented in the aliases node using
+ the following format 'spi{n}' where n is a unique number for the alias.
+
+
+Example:
+
+- SoC Specific Portion:
+
+ spi_0: spi@12d20000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x12d20000 0x100>;
+ interrupts = <0 66 0>;
+ tx-dma-channel = <&pdma0 5>;
+ rx-dma-channel = <&pdma0 4>;
+ };
+
+- Board Specific Portion:
+
+ spi_0: spi@12d20000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&gpa2 4 2 3 0>,
+ <&gpa2 6 2 3 0>,
+ <&gpa2 7 2 3 0>;
+
+ w25q80bw@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "w25x80";
+ reg = <0>;
+ spi-max-frequency = <10000>;
+
+ controller-data {
+ samsung,spi-cs-gpio = <&gpa2 5 1 0 3>;
+ samsung,spi-feedback-delay = <0>;
+ };
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "Kernel";
+ reg = <0x40000 0xc0000>;
+ };
+ };
+ };
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index d84ce7f..8bc838d 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -27,6 +27,8 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
#include <mach/dma.h>
#include <plat/s3c64xx-spi.h>
@@ -136,6 +138,7 @@ struct s3c64xx_spi_dma_data {
unsigned ch;
enum dma_data_direction direction;
enum dma_ch dmach;
+ struct property *dma_prop;
};
/**
@@ -200,6 +203,7 @@ struct s3c64xx_spi_driver_data {
struct samsung_dma_ops *ops;
struct s3c64xx_spi_port_config *port_conf;
unsigned port_id;
+ unsigned long gpios[4];
};
static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
@@ -318,9 +322,11 @@ static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
info.direction = sdd->rx_dma.direction;
info.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
+ info.dt_dmach_prop = sdd->rx_dma.dma_prop;
sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &info);
info.direction = sdd->tx_dma.direction;
info.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
+ info.dt_dmach_prop = sdd->tx_dma.dma_prop;
sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &info);
return 1;
@@ -813,6 +819,50 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
return 0;
}
+static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
+ struct s3c64xx_spi_driver_data *sdd,
+ struct spi_device *spi)
+{
+ struct s3c64xx_spi_csinfo *cs;
+ struct device_node *slave_np, *data_np;
+ u32 fb_delay = 0;
+
+ slave_np = spi->dev.of_node;
+ if (!slave_np) {
+ dev_err(&spi->dev, "device node not found\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ for_each_child_of_node(slave_np, data_np)
+ if (!strcmp(data_np->name, "controller-data"))
+ break;
+ if (!data_np) {
+ dev_err(&spi->dev, "child node 'controller-data' not found\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
+ if (!cs) {
+ dev_err(&spi->dev, "could not allocate memory for controller"
+ " data\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ cs->line = of_get_named_gpio(data_np, "samsung,spi-cs-gpio", 0);
+ if (!gpio_is_valid(cs->line)) {
+ dev_err(&spi->dev, "chip select gpio is invalid\n");
+ return ERR_PTR(-EINVAL);
+ }
+ if (devm_gpio_request(&spi->dev, cs->line, "spi-cs")) {
+ dev_err(&spi->dev, "gpio [%d] request failed\n", cs->line);
+ return ERR_PTR(-EBUSY);
+ }
+
+ of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
+ cs->fb_delay = fb_delay;
+ return cs;
+}
+
/*
* Here we only check the validity of requested configuration
* and save the configuration in a local data-structure.
@@ -828,7 +878,12 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
unsigned long flags;
int err = 0;
- if (cs == NULL || cs->set_level == NULL) {
+ if (!cs && spi->dev.of_node) {
+ cs = s3c64xx_get_slave_ctrldata(sdd, spi);
+ spi->controller_data = cs;
+ }
+
+ if (IS_ERR_OR_NULL(cs)) {
dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
return -ENODEV;
}
@@ -964,49 +1019,166 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
flush_fifo(sdd);
}
+static int __devinit s3c64xx_spi_get_dmares(
+ struct s3c64xx_spi_driver_data *sdd, bool tx)
+{
+ struct platform_device *pdev = sdd->pdev;
+ struct s3c64xx_spi_dma_data *dma_data;
+ struct property *prop;
+ struct resource *res;
+ char prop_name[15], *chan_str;
+
+ if (tx) {
+ dma_data = &sdd->tx_dma;
+ dma_data->direction = DMA_TO_DEVICE;
+ chan_str = "tx";
+ } else {
+ dma_data = &sdd->rx_dma;
+ dma_data->direction = DMA_FROM_DEVICE;
+ chan_str = "rx";
+ }
+
+ if (!sdd->pdev->dev.of_node) {
+ res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get SPI-%s dma "
+ "resource\n", chan_str);
+ return -ENXIO;
+ }
+ dma_data->dmach = res->start;
+ return 0;
+ }
+
+ sprintf(prop_name, "%s-dma-channel", chan_str);
+ prop = of_find_property(pdev->dev.of_node, prop_name, NULL);
+ if (!prop) {
+ dev_err(&pdev->dev, "%s dma channel property not specified\n",
+ chan_str);
+ return -ENXIO;
+ }
+
+ dma_data->dmach = DMACH_DT_PROP;
+ dma_data->dma_prop = prop;
+ return 0;
+}
+
+#ifdef CONFIG_OF
+static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
+{
+ struct device *dev = &sdd->pdev->dev;
+ int idx, gpio, ret;
+
+ /* find gpios for mosi, miso and clock lines */
+ for (idx = 0; idx < 3; idx++) {
+ gpio = of_get_gpio(dev->of_node, idx);
+ if (!gpio_is_valid(gpio)) {
+ dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
+ goto free_gpio;
+ }
+
+ ret = gpio_request(gpio, "spi-bus");
+ if (ret) {
+ dev_err(dev, "gpio [%d] request failed\n", gpio);
+ goto free_gpio;
+ }
+ }
+ return 0;
+
+free_gpio:
+ while (--idx >= 0)
+ gpio_free(sdd->gpios[idx]);
+ return -EINVAL;
+}
+
+static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
+{
+ unsigned int idx;
+ for (idx = 0; idx < 3; idx++)
+ gpio_free(sdd->gpios[idx]);
+}
+
+static struct __devinit s3c64xx_spi_info * s3c64xx_spi_parse_dt(
+ struct device *dev)
+{
+ struct s3c64xx_spi_info *sci;
+ u32 temp;
+
+ sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
+ if (!sci) {
+ dev_err(dev, "memory allocation for spi_info failed\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
+ dev_warn(dev, "spi bus clock parent not specified, using "
+ "clock at index 0 as parent\n");
+ sci->src_clk_nr = 0;
+ } else {
+ sci->src_clk_nr = temp;
+ }
+
+ if (of_property_read_u32(dev->of_node, "samsung,spi-num-cs", &temp)) {
+ dev_warn(dev, "number of chip select lines not specified, "
+ "assuming 1 chip select line\n");
+ sci->num_cs = 1;
+ } else {
+ sci->num_cs = temp;
+ }
+
+ return sci;
+}
+#else
+static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
+{
+ return dev->platform_data;
+}
+
+static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
+{
+ return -EINVAL;
+}
+
+static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
+{
+}
+#endif
+
+static const struct of_device_id s3c64xx_spi_dt_match[];
+
static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
struct platform_device *pdev)
{
+#ifdef CONFIG_OF
+ if (pdev->dev.of_node) {
+ const struct of_device_id *match;
+ match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
+ return (struct s3c64xx_spi_port_config *)match->data;
+ }
+#endif
return (struct s3c64xx_spi_port_config *)
platform_get_device_id(pdev)->driver_data;
}
static int __init s3c64xx_spi_probe(struct platform_device *pdev)
{
- struct resource *mem_res, *dmatx_res, *dmarx_res;
+ struct resource *mem_res;
struct s3c64xx_spi_driver_data *sdd;
- struct s3c64xx_spi_info *sci;
+ struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
struct spi_master *master;
int ret, irq;
char clk_name[16];
- if (pdev->id < 0) {
- dev_err(&pdev->dev,
- "Invalid platform device id-%d\n", pdev->id);
- return -ENODEV;
+ if (!sci && pdev->dev.of_node) {
+ sci = s3c64xx_spi_parse_dt(&pdev->dev);
+ if (IS_ERR(sci))
+ return PTR_ERR(sci);
}
- if (pdev->dev.platform_data == NULL) {
+ if (!sci) {
dev_err(&pdev->dev, "platform_data missing!\n");
return -ENODEV;
}
- sci = pdev->dev.platform_data;
-
- /* Check for availability of necessary resource */
-
- dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (dmatx_res == NULL) {
- dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
- return -ENXIO;
- }
-
- dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
- if (dmarx_res == NULL) {
- dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
- return -ENXIO;
- }
-
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (mem_res == NULL) {
dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
@@ -1030,18 +1202,34 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
sdd = spi_master_get_devdata(master);
sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
+
sdd->master = master;
sdd->cntrlr_info = sci;
sdd->pdev = pdev;
sdd->sfr_start = mem_res->start;
- sdd->tx_dma.dmach = dmatx_res->start;
- sdd->tx_dma.direction = DMA_MEM_TO_DEV;
- sdd->rx_dma.dmach = dmarx_res->start;
- sdd->rx_dma.direction = DMA_DEV_TO_MEM;
- sdd->port_id = pdev->id;
+ if (pdev->dev.of_node) {
+ ret = of_alias_get_id(pdev->dev.of_node, "spi");
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to get alias id, "
+ "errno %d\n", ret);
+ goto err0;
+ }
+ sdd->port_id = ret;
+ } else {
+ sdd->port_id = pdev->id;
+ }
sdd->cur_bpw = 8;
+ ret = s3c64xx_spi_get_dmares(sdd, true);
+ if (ret)
+ goto err0;
+
+ ret = s3c64xx_spi_get_dmares(sdd, false);
+ if (ret)
+ goto err0;
+
+ master->dev.of_node = pdev->dev.of_node;
master->bus_num = sdd->port_id;
master->setup = s3c64xx_spi_setup;
master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
@@ -1066,7 +1254,10 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
goto err1;
}
- if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
+ if (!sci->cfg_gpio && pdev->dev.of_node) {
+ if (s3c64xx_spi_parse_dt_gpio(sdd))
+ return -EBUSY;
+ } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
dev_err(&pdev->dev, "Unable to config gpio\n");
ret = -EBUSY;
goto err2;
@@ -1147,6 +1338,8 @@ err5:
err4:
clk_put(sdd->clk);
err3:
+ if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
+ s3c64xx_spi_dt_gpio_free(sdd);
err2:
iounmap((void *) sdd->regs);
err1:
@@ -1178,6 +1371,9 @@ static int s3c64xx_spi_remove(struct platform_device *pdev)
clk_disable(sdd->clk);
clk_put(sdd->clk);
+ if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
+ s3c64xx_spi_dt_gpio_free(sdd);
+
iounmap((void *) sdd->regs);
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1202,6 +1398,9 @@ static int s3c64xx_spi_suspend(struct device *dev)
clk_disable(sdd->src_clk);
clk_disable(sdd->clk);
+ if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
+ s3c64xx_spi_dt_gpio_free(sdd);
+
sdd->cur_speed = 0; /* Output Clock is stopped */
return 0;
@@ -1209,12 +1408,15 @@ static int s3c64xx_spi_suspend(struct device *dev)
static int s3c64xx_spi_resume(struct device *dev)
{
- struct platform_device *pdev = to_platform_device(dev);
struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
- sci->cfg_gpio(pdev);
+ if (!sci->cfg_gpio && dev->of_node)
+ s3c64xx_spi_parse_dt_gpio(sdd);
+ else
+ sci->cfg_gpio();
+
/* Enable the clock */
clk_enable(sdd->src_clk);
@@ -1352,11 +1554,22 @@ static struct platform_device_id s3c64xx_spi_driver_ids[] = {
{ },
};
+#ifdef CONFIG_OF
+static const struct of_device_id s3c64xx_spi_dt_match[] = {
+ { .compatible = "samsung,exynos4210-spi",
+ .data = (void *)EXYNOS4_SPI_PORT_CONFIG,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
+#endif /* CONFIG_OF */
+
static struct platform_driver s3c64xx_spi_driver = {
.driver = {
.name = "s3c64xx-spi",
.owner = THIS_MODULE,
.pm = &s3c64xx_spi_pm,
+ .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
},
.remove = s3c64xx_spi_remove,
.id_table = s3c64xx_spi_driver_ids,
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* [PATCH 10/10] spi: s3c64xx: add device tree support
@ 2012-05-08 22:04 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-08 22:04 UTC (permalink / raw)
To: linux-arm-kernel
Add support for device based discovery.
Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
.../devicetree/bindings/spi/spi-samsung.txt | 113 ++++++++
drivers/spi/spi-s3c64xx.c | 277 +++++++++++++++++---
2 files changed, 358 insertions(+), 32 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
new file mode 100644
index 0000000..2046c30
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -0,0 +1,113 @@
+* Samsung SPI Controller
+
+The Samsung SPI controller is used to interface with various devices such as flash
+and display controllers using the SPI communication interface.
+
+Required SoC Specific Properties:
+
+- compatible: should be one of the following.
+ - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
+ - samsung,s3c6410-spi: for s3c6410 platforms
+ - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms
+ - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
+ - samsung,exynos4210-spi: for exynos4 and exynos5 platforms
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- interrupts: The interrupt number to the cpu. The interrupt specifier format
+ depends on the interrupt controller.
+
+- tx-dma-channel: The dma channel specifier for tx operations. The format of
+ the dma specifier depends on the dma controller.
+
+- rx-dma-channel: The dma channel specifier for rx operations. The format of
+ the dma specifier depends on the dma controller.
+
+Required Board Specific Properties:
+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
+ particular order). The format of the gpio specifier depends on the gpio
+ controller.
+
+Optional Board Specific Properties:
+
+- samsung,spi-src-clk: If the spi controller includes a internal clock mux to
+ select the clock source for the spi bus clock, this property can be used to
+ indicate the clock to be used for driving the spi bus clock. If not specified,
+ the clock number 0 is used as default.
+
+- samsung,spi-num-cs: Specifies the number of chip select lines supported. If
+ not specified, the default number of chip select lines is set to 1.
+
+SPI Controller specific data in SPI slave nodes:
+
+- The spi slave nodes should provide the following information which is required
+ by the spi controller.
+
+ - samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
+ the slave select line by the spi controller. The format of the gpio
+ specifier depends on the gpio controller.
+
+ - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
+ miso line (to account for any lag in the miso line). The following are the
+ valid values.
+
+ - 0: No phase shift.
+ - 1: 90 degree phase shift sampling.
+ - 2: 180 degree phase shift sampling.
+ - 3: 270 degree phase shift sampling.
+
+Aliases:
+
+- All the SPI controller nodes should be represented in the aliases node using
+ the following format 'spi{n}' where n is a unique number for the alias.
+
+
+Example:
+
+- SoC Specific Portion:
+
+ spi_0: spi at 12d20000 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x12d20000 0x100>;
+ interrupts = <0 66 0>;
+ tx-dma-channel = <&pdma0 5>;
+ rx-dma-channel = <&pdma0 4>;
+ };
+
+- Board Specific Portion:
+
+ spi_0: spi at 12d20000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&gpa2 4 2 3 0>,
+ <&gpa2 6 2 3 0>,
+ <&gpa2 7 2 3 0>;
+
+ w25q80bw at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "w25x80";
+ reg = <0>;
+ spi-max-frequency = <10000>;
+
+ controller-data {
+ samsung,spi-cs-gpio = <&gpa2 5 1 0 3>;
+ samsung,spi-feedback-delay = <0>;
+ };
+
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition at 40000 {
+ label = "Kernel";
+ reg = <0x40000 0xc0000>;
+ };
+ };
+ };
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index d84ce7f..8bc838d 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -27,6 +27,8 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
#include <mach/dma.h>
#include <plat/s3c64xx-spi.h>
@@ -136,6 +138,7 @@ struct s3c64xx_spi_dma_data {
unsigned ch;
enum dma_data_direction direction;
enum dma_ch dmach;
+ struct property *dma_prop;
};
/**
@@ -200,6 +203,7 @@ struct s3c64xx_spi_driver_data {
struct samsung_dma_ops *ops;
struct s3c64xx_spi_port_config *port_conf;
unsigned port_id;
+ unsigned long gpios[4];
};
static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
@@ -318,9 +322,11 @@ static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
info.direction = sdd->rx_dma.direction;
info.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
+ info.dt_dmach_prop = sdd->rx_dma.dma_prop;
sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &info);
info.direction = sdd->tx_dma.direction;
info.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
+ info.dt_dmach_prop = sdd->tx_dma.dma_prop;
sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &info);
return 1;
@@ -813,6 +819,50 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
return 0;
}
+static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
+ struct s3c64xx_spi_driver_data *sdd,
+ struct spi_device *spi)
+{
+ struct s3c64xx_spi_csinfo *cs;
+ struct device_node *slave_np, *data_np;
+ u32 fb_delay = 0;
+
+ slave_np = spi->dev.of_node;
+ if (!slave_np) {
+ dev_err(&spi->dev, "device node not found\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ for_each_child_of_node(slave_np, data_np)
+ if (!strcmp(data_np->name, "controller-data"))
+ break;
+ if (!data_np) {
+ dev_err(&spi->dev, "child node 'controller-data' not found\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
+ if (!cs) {
+ dev_err(&spi->dev, "could not allocate memory for controller"
+ " data\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ cs->line = of_get_named_gpio(data_np, "samsung,spi-cs-gpio", 0);
+ if (!gpio_is_valid(cs->line)) {
+ dev_err(&spi->dev, "chip select gpio is invalid\n");
+ return ERR_PTR(-EINVAL);
+ }
+ if (devm_gpio_request(&spi->dev, cs->line, "spi-cs")) {
+ dev_err(&spi->dev, "gpio [%d] request failed\n", cs->line);
+ return ERR_PTR(-EBUSY);
+ }
+
+ of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
+ cs->fb_delay = fb_delay;
+ return cs;
+}
+
/*
* Here we only check the validity of requested configuration
* and save the configuration in a local data-structure.
@@ -828,7 +878,12 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
unsigned long flags;
int err = 0;
- if (cs == NULL || cs->set_level == NULL) {
+ if (!cs && spi->dev.of_node) {
+ cs = s3c64xx_get_slave_ctrldata(sdd, spi);
+ spi->controller_data = cs;
+ }
+
+ if (IS_ERR_OR_NULL(cs)) {
dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
return -ENODEV;
}
@@ -964,49 +1019,166 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
flush_fifo(sdd);
}
+static int __devinit s3c64xx_spi_get_dmares(
+ struct s3c64xx_spi_driver_data *sdd, bool tx)
+{
+ struct platform_device *pdev = sdd->pdev;
+ struct s3c64xx_spi_dma_data *dma_data;
+ struct property *prop;
+ struct resource *res;
+ char prop_name[15], *chan_str;
+
+ if (tx) {
+ dma_data = &sdd->tx_dma;
+ dma_data->direction = DMA_TO_DEVICE;
+ chan_str = "tx";
+ } else {
+ dma_data = &sdd->rx_dma;
+ dma_data->direction = DMA_FROM_DEVICE;
+ chan_str = "rx";
+ }
+
+ if (!sdd->pdev->dev.of_node) {
+ res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get SPI-%s dma "
+ "resource\n", chan_str);
+ return -ENXIO;
+ }
+ dma_data->dmach = res->start;
+ return 0;
+ }
+
+ sprintf(prop_name, "%s-dma-channel", chan_str);
+ prop = of_find_property(pdev->dev.of_node, prop_name, NULL);
+ if (!prop) {
+ dev_err(&pdev->dev, "%s dma channel property not specified\n",
+ chan_str);
+ return -ENXIO;
+ }
+
+ dma_data->dmach = DMACH_DT_PROP;
+ dma_data->dma_prop = prop;
+ return 0;
+}
+
+#ifdef CONFIG_OF
+static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
+{
+ struct device *dev = &sdd->pdev->dev;
+ int idx, gpio, ret;
+
+ /* find gpios for mosi, miso and clock lines */
+ for (idx = 0; idx < 3; idx++) {
+ gpio = of_get_gpio(dev->of_node, idx);
+ if (!gpio_is_valid(gpio)) {
+ dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
+ goto free_gpio;
+ }
+
+ ret = gpio_request(gpio, "spi-bus");
+ if (ret) {
+ dev_err(dev, "gpio [%d] request failed\n", gpio);
+ goto free_gpio;
+ }
+ }
+ return 0;
+
+free_gpio:
+ while (--idx >= 0)
+ gpio_free(sdd->gpios[idx]);
+ return -EINVAL;
+}
+
+static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
+{
+ unsigned int idx;
+ for (idx = 0; idx < 3; idx++)
+ gpio_free(sdd->gpios[idx]);
+}
+
+static struct __devinit s3c64xx_spi_info * s3c64xx_spi_parse_dt(
+ struct device *dev)
+{
+ struct s3c64xx_spi_info *sci;
+ u32 temp;
+
+ sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
+ if (!sci) {
+ dev_err(dev, "memory allocation for spi_info failed\n");
+ return ERR_PTR(-ENOMEM);
+ }
+
+ if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
+ dev_warn(dev, "spi bus clock parent not specified, using "
+ "clock at index 0 as parent\n");
+ sci->src_clk_nr = 0;
+ } else {
+ sci->src_clk_nr = temp;
+ }
+
+ if (of_property_read_u32(dev->of_node, "samsung,spi-num-cs", &temp)) {
+ dev_warn(dev, "number of chip select lines not specified, "
+ "assuming 1 chip select line\n");
+ sci->num_cs = 1;
+ } else {
+ sci->num_cs = temp;
+ }
+
+ return sci;
+}
+#else
+static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
+{
+ return dev->platform_data;
+}
+
+static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
+{
+ return -EINVAL;
+}
+
+static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
+{
+}
+#endif
+
+static const struct of_device_id s3c64xx_spi_dt_match[];
+
static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
struct platform_device *pdev)
{
+#ifdef CONFIG_OF
+ if (pdev->dev.of_node) {
+ const struct of_device_id *match;
+ match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
+ return (struct s3c64xx_spi_port_config *)match->data;
+ }
+#endif
return (struct s3c64xx_spi_port_config *)
platform_get_device_id(pdev)->driver_data;
}
static int __init s3c64xx_spi_probe(struct platform_device *pdev)
{
- struct resource *mem_res, *dmatx_res, *dmarx_res;
+ struct resource *mem_res;
struct s3c64xx_spi_driver_data *sdd;
- struct s3c64xx_spi_info *sci;
+ struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
struct spi_master *master;
int ret, irq;
char clk_name[16];
- if (pdev->id < 0) {
- dev_err(&pdev->dev,
- "Invalid platform device id-%d\n", pdev->id);
- return -ENODEV;
+ if (!sci && pdev->dev.of_node) {
+ sci = s3c64xx_spi_parse_dt(&pdev->dev);
+ if (IS_ERR(sci))
+ return PTR_ERR(sci);
}
- if (pdev->dev.platform_data == NULL) {
+ if (!sci) {
dev_err(&pdev->dev, "platform_data missing!\n");
return -ENODEV;
}
- sci = pdev->dev.platform_data;
-
- /* Check for availability of necessary resource */
-
- dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
- if (dmatx_res == NULL) {
- dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
- return -ENXIO;
- }
-
- dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
- if (dmarx_res == NULL) {
- dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
- return -ENXIO;
- }
-
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (mem_res == NULL) {
dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
@@ -1030,18 +1202,34 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
sdd = spi_master_get_devdata(master);
sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
+
sdd->master = master;
sdd->cntrlr_info = sci;
sdd->pdev = pdev;
sdd->sfr_start = mem_res->start;
- sdd->tx_dma.dmach = dmatx_res->start;
- sdd->tx_dma.direction = DMA_MEM_TO_DEV;
- sdd->rx_dma.dmach = dmarx_res->start;
- sdd->rx_dma.direction = DMA_DEV_TO_MEM;
- sdd->port_id = pdev->id;
+ if (pdev->dev.of_node) {
+ ret = of_alias_get_id(pdev->dev.of_node, "spi");
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to get alias id, "
+ "errno %d\n", ret);
+ goto err0;
+ }
+ sdd->port_id = ret;
+ } else {
+ sdd->port_id = pdev->id;
+ }
sdd->cur_bpw = 8;
+ ret = s3c64xx_spi_get_dmares(sdd, true);
+ if (ret)
+ goto err0;
+
+ ret = s3c64xx_spi_get_dmares(sdd, false);
+ if (ret)
+ goto err0;
+
+ master->dev.of_node = pdev->dev.of_node;
master->bus_num = sdd->port_id;
master->setup = s3c64xx_spi_setup;
master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
@@ -1066,7 +1254,10 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
goto err1;
}
- if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
+ if (!sci->cfg_gpio && pdev->dev.of_node) {
+ if (s3c64xx_spi_parse_dt_gpio(sdd))
+ return -EBUSY;
+ } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
dev_err(&pdev->dev, "Unable to config gpio\n");
ret = -EBUSY;
goto err2;
@@ -1147,6 +1338,8 @@ err5:
err4:
clk_put(sdd->clk);
err3:
+ if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
+ s3c64xx_spi_dt_gpio_free(sdd);
err2:
iounmap((void *) sdd->regs);
err1:
@@ -1178,6 +1371,9 @@ static int s3c64xx_spi_remove(struct platform_device *pdev)
clk_disable(sdd->clk);
clk_put(sdd->clk);
+ if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node)
+ s3c64xx_spi_dt_gpio_free(sdd);
+
iounmap((void *) sdd->regs);
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1202,6 +1398,9 @@ static int s3c64xx_spi_suspend(struct device *dev)
clk_disable(sdd->src_clk);
clk_disable(sdd->clk);
+ if (!sdd->cntrlr_info->cfg_gpio && dev->of_node)
+ s3c64xx_spi_dt_gpio_free(sdd);
+
sdd->cur_speed = 0; /* Output Clock is stopped */
return 0;
@@ -1209,12 +1408,15 @@ static int s3c64xx_spi_suspend(struct device *dev)
static int s3c64xx_spi_resume(struct device *dev)
{
- struct platform_device *pdev = to_platform_device(dev);
struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
- sci->cfg_gpio(pdev);
+ if (!sci->cfg_gpio && dev->of_node)
+ s3c64xx_spi_parse_dt_gpio(sdd);
+ else
+ sci->cfg_gpio();
+
/* Enable the clock */
clk_enable(sdd->src_clk);
@@ -1352,11 +1554,22 @@ static struct platform_device_id s3c64xx_spi_driver_ids[] = {
{ },
};
+#ifdef CONFIG_OF
+static const struct of_device_id s3c64xx_spi_dt_match[] = {
+ { .compatible = "samsung,exynos4210-spi",
+ .data = (void *)EXYNOS4_SPI_PORT_CONFIG,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
+#endif /* CONFIG_OF */
+
static struct platform_driver s3c64xx_spi_driver = {
.driver = {
.name = "s3c64xx-spi",
.owner = THIS_MODULE,
.pm = &s3c64xx_spi_pm,
+ .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
},
.remove = s3c64xx_spi_remove,
.id_table = s3c64xx_spi_driver_ids,
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 78+ messages in thread
* Re: [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-09 8:03 ` Jassi Brar
-1 siblings, 0 replies; 78+ messages in thread
From: Jassi Brar @ 2012-05-09 8:03 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
On Wed, May 9, 2012 at 3:34 AM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
>
> The set_level callback in the controller data, which is used to configure
> the slave select line, cannot be supported when migrating the driver to
> device tree based discovery. Since all the platforms currently use gpio
> as the slave select line, this callback can be removed from the
> controller data and replaced with call to gpio_set_value in the driver.
>
This patch is ok.
Separately, you might also want to see if we really need the air-tight
protection of spin_lock_irqsave around enable_cs - IIRC someone
had a CS coming out of an gpio extender connected over I2C
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
@ 2012-05-09 8:03 ` Jassi Brar
0 siblings, 0 replies; 78+ messages in thread
From: Jassi Brar @ 2012-05-09 8:03 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 9, 2012 at 3:34 AM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
>
> The set_level callback in the controller data, which is used to configure
> the slave select line, cannot be supported when migrating the driver to
> device tree based discovery. Since all the platforms currently use gpio
> as the slave select line, this callback can be removed from the
> controller data and replaced with call to gpio_set_value in the driver.
>
This patch is ok.
Separately, you might also want to see if we really need the air-tight
protection of spin_lock_irqsave around enable_cs - IIRC someone
had a CS coming out of an gpio extender connected over I2C
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 00/10] spi: s3c64xx: add support for device tree
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-09 8:17 ` Jassi Brar
-1 siblings, 0 replies; 78+ messages in thread
From: Jassi Brar @ 2012-05-09 8:17 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
On Wed, May 9, 2012 at 3:34 AM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> This patch series adds device tree based discovery support for Samsung's
> s3c64xx compatible spi controller. This is mainly tested for Exynos4210
> and Exynos5250 with onboard spi nor flash device.
>
> This patch series is based on Linux 3.4-rc5 with the following two
> patch series applied.
>
> [1] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg10494.html
> [PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0
>
> [2] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg09640.html
> [PATCH 0/6] S3C24XX: Add support for HSSPI on S3C2416/S3C2443
>
> Thomas Abraham (10):
> spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
> spi: s3c64xx: move controller information into driver data
> ARM: Samsung: Remove spi hardware controller information from platform data
> ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions
> ARM: Samsung: Update the device names for spi clock lookup
> ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
> spi: s3c64xx: Remove the 'set_level' callback from controller data
> ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
> ARM: Exynos5: Add spi clock support
> spi: s3c64xx: add device tree support
>
Look ok to me. FWIW, Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 00/10] spi: s3c64xx: add support for device tree
@ 2012-05-09 8:17 ` Jassi Brar
0 siblings, 0 replies; 78+ messages in thread
From: Jassi Brar @ 2012-05-09 8:17 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 9, 2012 at 3:34 AM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> This patch series adds device tree based discovery support for Samsung's
> s3c64xx compatible spi controller. This is mainly tested for Exynos4210
> and Exynos5250 with onboard spi nor flash device.
>
> This patch series is based on Linux 3.4-rc5 with the following two
> patch series applied.
>
> [1] http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg10494.html
> ? ?[PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0
>
> [2] http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg09640.html
> ? ?[PATCH 0/6] S3C24XX: Add support for HSSPI on S3C2416/S3C2443
>
> Thomas Abraham (10):
> ?spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
> ?spi: s3c64xx: move controller information into driver data
> ?ARM: Samsung: Remove spi hardware controller information from platform data
> ?ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions
> ?ARM: Samsung: Update the device names for spi clock lookup
> ?ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
> ?spi: s3c64xx: Remove the 'set_level' callback from controller data
> ?ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
> ?ARM: Exynos5: Add spi clock support
> ?spi: s3c64xx: add device tree support
>
Look ok to me. FWIW, Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-09 8:52 ` Mark Brown
-1 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 8:52 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
On Wed, May 09, 2012 at 03:34:49AM +0530, Thomas Abraham wrote:
> With the addition of platform specific driver data in the spi-s3c64xx
> driver, the device name of spi controllers are changed. Accordingly,
> update the device name of spi clocks instances.
This should've been squashed into the patch that updated to use driver
data in order to avoid breaking bisection.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
@ 2012-05-09 8:52 ` Mark Brown
0 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 8:52 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 09, 2012 at 03:34:49AM +0530, Thomas Abraham wrote:
> With the addition of platform specific driver data in the spi-s3c64xx
> driver, the device name of spi controllers are changed. Accordingly,
> update the device name of spi clocks instances.
This should've been squashed into the patch that updated to use driver
data in order to avoid breaking bisection.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-09 8:56 ` Mark Brown
-1 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 8:56 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
On Wed, May 09, 2012 at 03:34:50AM +0530, Thomas Abraham wrote:
> + s3c64xx_spi0_set_platdata("s3c6410-spi", NULL, 0, 1);
Shouldn't we just set the name in the struct platform_device rather than
requiring the machine to pass it through by hand?
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
@ 2012-05-09 8:56 ` Mark Brown
0 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 8:56 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 09, 2012 at 03:34:50AM +0530, Thomas Abraham wrote:
> + s3c64xx_spi0_set_platdata("s3c6410-spi", NULL, 0, 1);
Shouldn't we just set the name in the struct platform_device rather than
requiring the machine to pass it through by hand?
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 10/10] spi: s3c64xx: add device tree support
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-09 9:07 ` Mark Brown
-1 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 9:07 UTC (permalink / raw)
To: Thomas Abraham
Cc: kgene.kim-Sze3O3UU22JBDgjK7y7TUQ,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Wed, May 09, 2012 at 03:34:54AM +0530, Thomas Abraham wrote:
> +- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
> + particular order). The format of the gpio specifier depends on the gpio
> + controller.
This seems odd... This isn't a bitbanging controller, and surely the
driver will need to know which signal is which? I suspect this is
actually for pinmux rather than to identify the signals but that should
at least be made clear and really should be being done using the pinmux
API.
> + - samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
> + the slave select line by the spi controller. The format of the gpio
> + specifier depends on the gpio controller.
We should really have a binding for this at the SPI level (and ideally
some code to manage setting the GPIO too) - it's pretty common to use a
GPIO as /CS.
------------------------------------------------------------------------------
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and
threat landscape has changed and how IT managers can respond. Discussions
will include endpoint security, mobile security and the latest in malware
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 10/10] spi: s3c64xx: add device tree support
@ 2012-05-09 9:07 ` Mark Brown
0 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 9:07 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 09, 2012 at 03:34:54AM +0530, Thomas Abraham wrote:
> +- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
> + particular order). The format of the gpio specifier depends on the gpio
> + controller.
This seems odd... This isn't a bitbanging controller, and surely the
driver will need to know which signal is which? I suspect this is
actually for pinmux rather than to identify the signals but that should
at least be made clear and really should be being done using the pinmux
API.
> + - samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
> + the slave select line by the spi controller. The format of the gpio
> + specifier depends on the gpio controller.
We should really have a binding for this at the SPI level (and ideally
some code to manage setting the GPIO too) - it's pretty common to use a
GPIO as /CS.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
2012-05-09 8:56 ` Mark Brown
@ 2012-05-09 9:10 ` Heiko Stübner
-1 siblings, 0 replies; 78+ messages in thread
From: Heiko Stübner @ 2012-05-09 9:10 UTC (permalink / raw)
To: Mark Brown
Cc: kgene.kim-Sze3O3UU22JBDgjK7y7TUQ,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Thomas Abraham,
spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Am Mittwoch, 9. Mai 2012, 10:56:17 schrieb Mark Brown:
> On Wed, May 09, 2012 at 03:34:50AM +0530, Thomas Abraham wrote:
> > + s3c64xx_spi0_set_platdata("s3c6410-spi", NULL, 0, 1);
>
> Shouldn't we just set the name in the struct platform_device rather than
> requiring the machine to pass it through by hand?
Similar to the adc and rtc driver, all Samsung platforms reuse a common
platform-device definition for the s3c64xx-spi and simply will set the correct
name when the machine type is determined during boot.
I.e. I will also have to change my out-of-tree machine stuff to set the
s3c2443-spi name using this method.
The alternative is creating a mulitude of platform devices for each possible
machine type using this driver.
Heiko
------------------------------------------------------------------------------
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and
threat landscape has changed and how IT managers can respond. Discussions
will include endpoint security, mobile security and the latest in malware
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
@ 2012-05-09 9:10 ` Heiko Stübner
0 siblings, 0 replies; 78+ messages in thread
From: Heiko Stübner @ 2012-05-09 9:10 UTC (permalink / raw)
To: linux-arm-kernel
Am Mittwoch, 9. Mai 2012, 10:56:17 schrieb Mark Brown:
> On Wed, May 09, 2012 at 03:34:50AM +0530, Thomas Abraham wrote:
> > + s3c64xx_spi0_set_platdata("s3c6410-spi", NULL, 0, 1);
>
> Shouldn't we just set the name in the struct platform_device rather than
> requiring the machine to pass it through by hand?
Similar to the adc and rtc driver, all Samsung platforms reuse a common
platform-device definition for the s3c64xx-spi and simply will set the correct
name when the machine type is determined during boot.
I.e. I will also have to change my out-of-tree machine stuff to set the
s3c2443-spi name using this method.
The alternative is creating a mulitude of platform devices for each possible
machine type using this driver.
Heiko
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-09 9:20 ` Heiko Stübner
-1 siblings, 0 replies; 78+ messages in thread
From: Heiko Stübner @ 2012-05-09 9:20 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, linux-arm-kernel,
linux-samsung-soc, rob.herring, grant.likely, kgene.kim,
jaswinder.singh
Am Mittwoch, 9. Mai 2012, 00:04:51 schrieb Thomas Abraham:
> The set_level callback in the controller data, which is used to configure
> the slave select line, cannot be supported when migrating the driver to
> device tree based discovery. Since all the platforms currently use gpio
> as the slave select line, this callback can be removed from the
> controller data and replaced with call to gpio_set_value in the driver.
I was quite fond of the set_level callback. On one of the machines I'm working
on there is some sort of multiplexer (TI-sn74cbtlv3257) sitting between the
controller and spi devices to provide support for more than one device.
So I was doing the switch to the correct device in the set_level callback,
which worked quite well.
In the end, I'm still ok with this consolidation, as the device line has
reached it's end of life and the second device (an epaper controller)
provides another form of access to it through the display controller of the
s3c2416.
Heiko
[1] https://github.com/mmind/linux-es600/blob/topic/es600-devel/arch/arm/mach-s3c24xx/common-es600.c#L1155
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 2 --
> drivers/spi/spi-s3c64xx.c | 8 ++++----
> 2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index a733ce9..48a6495
> 100644
> --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> @@ -18,7 +18,6 @@ struct platform_device;
> * @fb_delay: Slave specific feedback delay.
> * Refer to FB_CLK_SEL register definition in SPI chapter.
> * @line: Custom 'identity' of the CS line.
> - * @set_level: CS line control.
> *
> * This is per SPI-Slave Chipselect information.
> * Allocate and initialize one in machine init code and make the
> @@ -27,7 +26,6 @@ struct platform_device;
> struct s3c64xx_spi_csinfo {
> u8 fb_delay;
> unsigned line;
> - void (*set_level)(unsigned line_id, int lvl);
> };
>
> /**
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index f6bc0e3..d84ce7f 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -406,14 +406,14 @@ static inline void enable_cs(struct
> s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi != spi) { /* if last mssg
> on diff device */
> /* Deselect the last toggled device */
> cs = sdd->tgl_spi->controller_data;
> - cs->set_level(cs->line,
> - spi->mode & SPI_CS_HIGH ? 0 : 1);
> + gpio_set_value(cs->line,
> + spi->mode & SPI_CS_HIGH ? 0 : 1);
> }
> sdd->tgl_spi = NULL;
> }
>
> cs = spi->controller_data;
> - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
> + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
> }
>
> static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> @@ -499,7 +499,7 @@ static inline void disable_cs(struct
> s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi == spi)
> sdd->tgl_spi = NULL;
>
> - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
> + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
> }
>
> static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
@ 2012-05-09 9:20 ` Heiko Stübner
0 siblings, 0 replies; 78+ messages in thread
From: Heiko Stübner @ 2012-05-09 9:20 UTC (permalink / raw)
To: linux-arm-kernel
Am Mittwoch, 9. Mai 2012, 00:04:51 schrieb Thomas Abraham:
> The set_level callback in the controller data, which is used to configure
> the slave select line, cannot be supported when migrating the driver to
> device tree based discovery. Since all the platforms currently use gpio
> as the slave select line, this callback can be removed from the
> controller data and replaced with call to gpio_set_value in the driver.
I was quite fond of the set_level callback. On one of the machines I'm working
on there is some sort of multiplexer (TI-sn74cbtlv3257) sitting between the
controller and spi devices to provide support for more than one device.
So I was doing the switch to the correct device in the set_level callback,
which worked quite well.
In the end, I'm still ok with this consolidation, as the device line has
reached it's end of life and the second device (an epaper controller)
provides another form of access to it through the display controller of the
s3c2416.
Heiko
[1] https://github.com/mmind/linux-es600/blob/topic/es600-devel/arch/arm/mach-s3c24xx/common-es600.c#L1155
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 2 --
> drivers/spi/spi-s3c64xx.c | 8 ++++----
> 2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index a733ce9..48a6495
> 100644
> --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> @@ -18,7 +18,6 @@ struct platform_device;
> * @fb_delay: Slave specific feedback delay.
> * Refer to FB_CLK_SEL register definition in SPI chapter.
> * @line: Custom 'identity' of the CS line.
> - * @set_level: CS line control.
> *
> * This is per SPI-Slave Chipselect information.
> * Allocate and initialize one in machine init code and make the
> @@ -27,7 +26,6 @@ struct platform_device;
> struct s3c64xx_spi_csinfo {
> u8 fb_delay;
> unsigned line;
> - void (*set_level)(unsigned line_id, int lvl);
> };
>
> /**
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index f6bc0e3..d84ce7f 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -406,14 +406,14 @@ static inline void enable_cs(struct
> s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi != spi) { /* if last mssg
> on diff device */
> /* Deselect the last toggled device */
> cs = sdd->tgl_spi->controller_data;
> - cs->set_level(cs->line,
> - spi->mode & SPI_CS_HIGH ? 0 : 1);
> + gpio_set_value(cs->line,
> + spi->mode & SPI_CS_HIGH ? 0 : 1);
> }
> sdd->tgl_spi = NULL;
> }
>
> cs = spi->controller_data;
> - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
> + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
> }
>
> static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> @@ -499,7 +499,7 @@ static inline void disable_cs(struct
> s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi == spi)
> sdd->tgl_spi = NULL;
>
> - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
> + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
> }
>
> static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
2012-05-09 9:20 ` Heiko Stübner
@ 2012-05-09 10:31 ` Jassi Brar
-1 siblings, 0 replies; 78+ messages in thread
From: Jassi Brar @ 2012-05-09 10:31 UTC (permalink / raw)
To: Heiko Stübner
Cc: Thomas Abraham, spi-devel-general, devicetree-discuss,
linux-arm-kernel, linux-samsung-soc, rob.herring, grant.likely,
kgene.kim
On 9 May 2012 14:50, Heiko Stübner <heiko@sntech.de> wrote:
> Am Mittwoch, 9. Mai 2012, 00:04:51 schrieb Thomas Abraham:
>> The set_level callback in the controller data, which is used to configure
>> the slave select line, cannot be supported when migrating the driver to
>> device tree based discovery. Since all the platforms currently use gpio
>> as the slave select line, this callback can be removed from the
>> controller data and replaced with call to gpio_set_value in the driver.
>
> I was quite fond of the set_level callback. On one of the machines I'm working
> on there is some sort of multiplexer (TI-sn74cbtlv3257) sitting between the
> controller and spi devices to provide support for more than one device.
> So I was doing the switch to the correct device in the set_level callback,
> which worked quite well.
>
I suppose you should still be able to do that defining virtual gpios backed
by appropriate physical mux'ing of lines ?
-jassi
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
@ 2012-05-09 10:31 ` Jassi Brar
0 siblings, 0 replies; 78+ messages in thread
From: Jassi Brar @ 2012-05-09 10:31 UTC (permalink / raw)
To: linux-arm-kernel
On 9 May 2012 14:50, Heiko St?bner <heiko@sntech.de> wrote:
> Am Mittwoch, 9. Mai 2012, 00:04:51 schrieb Thomas Abraham:
>> The set_level callback in the controller data, which is used to configure
>> the slave select line, cannot be supported when migrating the driver to
>> device tree based discovery. Since all the platforms currently use gpio
>> as the slave select line, this callback can be removed from the
>> controller data and replaced with call to gpio_set_value in the driver.
>
> I was quite fond of the set_level callback. On one of the machines I'm working
> on there is some sort of multiplexer (TI-sn74cbtlv3257) sitting between the
> controller and spi devices to provide support for more than one device.
> So I was doing the switch to the correct device in the set_level callback,
> which worked quite well.
>
I suppose you should still be able to do that defining virtual gpios backed
by appropriate physical mux'ing of lines ?
-jassi
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
2012-05-09 9:10 ` Heiko Stübner
@ 2012-05-09 10:55 ` Mark Brown
-1 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 10:55 UTC (permalink / raw)
To: Heiko Stübner
Cc: Thomas Abraham, spi-devel-general, devicetree-discuss, kgene.kim,
rob.herring, grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
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On Wed, May 09, 2012 at 11:10:14AM +0200, Heiko Stübner wrote:
> Similar to the adc and rtc driver, all Samsung platforms reuse a common
> platform-device definition for the s3c64xx-spi and simply will set the correct
> name when the machine type is determined during boot.
Right, that doesn't mean this is a great way of doing things, though -
it's been a frequent source of errors in the past and is painful to
debug as the data structures get rewritten during boot which is a bit of
a surprise.
> The alternative is creating a mulitude of platform devices for each possible
> machine type using this driver.
Yes, that's the normal way of handling this and is actually what the
code was originally doing - there's a bunch of ifdefed devices in
plat-samsung/devs.c. You usually have to do this anyway as the IPs move
about so the resources need changing.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
@ 2012-05-09 10:55 ` Mark Brown
0 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 10:55 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 09, 2012 at 11:10:14AM +0200, Heiko St?bner wrote:
> Similar to the adc and rtc driver, all Samsung platforms reuse a common
> platform-device definition for the s3c64xx-spi and simply will set the correct
> name when the machine type is determined during boot.
Right, that doesn't mean this is a great way of doing things, though -
it's been a frequent source of errors in the past and is painful to
debug as the data structures get rewritten during boot which is a bit of
a surprise.
> The alternative is creating a mulitude of platform devices for each possible
> machine type using this driver.
Yes, that's the normal way of handling this and is actually what the
code was originally doing - there's a bunch of ifdefed devices in
plat-samsung/devs.c. You usually have to do this anyway as the IPs move
about so the resources need changing.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
2012-05-09 8:52 ` Mark Brown
@ 2012-05-09 13:40 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 13:40 UTC (permalink / raw)
To: Mark Brown
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
On 9 May 2012 16:52, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 03:34:49AM +0530, Thomas Abraham wrote:
>> With the addition of platform specific driver data in the spi-s3c64xx
>> driver, the device name of spi controllers are changed. Accordingly,
>> update the device name of spi clocks instances.
>
> This should've been squashed into the patch that updated to use driver
> data in order to avoid breaking bisection.
This patch updates clock devname in the platform code and the
modifications to use driver data is in the driver file. So these two
changes are kept separate to allow them to be applied to their
respective trees.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
@ 2012-05-09 13:40 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 13:40 UTC (permalink / raw)
To: linux-arm-kernel
On 9 May 2012 16:52, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 03:34:49AM +0530, Thomas Abraham wrote:
>> With the addition of platform specific driver data in the spi-s3c64xx
>> driver, the device name of spi controllers are changed. Accordingly,
>> update the device name of spi clocks instances.
>
> This should've been squashed into the patch that updated to use driver
> data in order to avoid breaking bisection.
This patch updates clock devname in the platform code and the
modifications to use driver data is in the driver file. So these two
changes are kept separate to allow them to be applied to their
respective trees.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 10/10] spi: s3c64xx: add device tree support
2012-05-09 9:07 ` Mark Brown
@ 2012-05-09 14:13 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 14:13 UTC (permalink / raw)
To: Mark Brown
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
On 9 May 2012 17:07, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 03:34:54AM +0530, Thomas Abraham wrote:
>
>> +- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
>> + particular order). The format of the gpio specifier depends on the gpio
>> + controller.
>
> This seems odd... This isn't a bitbanging controller, and surely the
> driver will need to know which signal is which? I suspect this is
> actually for pinmux rather than to identify the signals but that should
> at least be made clear and really should be being done using the pinmux
> API.
The driver retrieves the list of gpio's that it is allowed to use. The
gpio numbers for miso, mosi and clk are mandatory but the order in
which they are specified is not important since the driver never needs
to which gpio is which interface line. I agree the pinmux api should
be used here, but the call to pinmux api would be a incremental change
here, not changing the code this patch is adding.
>
>> + - samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
>> + the slave select line by the spi controller. The format of the gpio
>> + specifier depends on the gpio controller.
>
> We should really have a binding for this at the SPI level (and ideally
> some code to manage setting the GPIO too) - it's pretty common to use a
> GPIO as /CS.
The existing implementations vary in the way the nCS gpio lines are
specified. For some controllers, the nCS gpio's are included in the
spi device node whereas in this implementation, the nCS gpio is listed
in the spi slave device node.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 10/10] spi: s3c64xx: add device tree support
@ 2012-05-09 14:13 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 14:13 UTC (permalink / raw)
To: linux-arm-kernel
On 9 May 2012 17:07, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 03:34:54AM +0530, Thomas Abraham wrote:
>
>> +- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
>> + ?particular order). The format of the gpio specifier depends on the gpio
>> + ?controller.
>
> This seems odd... ?This isn't a bitbanging controller, and surely the
> driver will need to know which signal is which? ?I suspect this is
> actually for pinmux rather than to identify the signals but that should
> at least be made clear and really should be being done using the pinmux
> API.
The driver retrieves the list of gpio's that it is allowed to use. The
gpio numbers for miso, mosi and clk are mandatory but the order in
which they are specified is not important since the driver never needs
to which gpio is which interface line. I agree the pinmux api should
be used here, but the call to pinmux api would be a incremental change
here, not changing the code this patch is adding.
>
>> + ?- samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
>> + ? ?the slave select line by the spi controller. The format of the gpio
>> + ? ?specifier depends on the gpio controller.
>
> We should really have a binding for this at the SPI level (and ideally
> some code to manage setting the GPIO too) - it's pretty common to use a
> GPIO as /CS.
The existing implementations vary in the way the nCS gpio lines are
specified. For some controllers, the nCS gpio's are included in the
spi device node whereas in this implementation, the nCS gpio is listed
in the spi slave device node.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
2012-05-09 10:55 ` Mark Brown
@ 2012-05-09 14:22 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 14:22 UTC (permalink / raw)
To: Mark Brown
Cc: Heiko Stübner, spi-devel-general, devicetree-discuss,
kgene.kim, rob.herring, grant.likely, jaswinder.singh,
linux-samsung-soc, linux-arm-kernel
On 9 May 2012 18:55, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 11:10:14AM +0200, Heiko Stübner wrote:
>
>> Similar to the adc and rtc driver, all Samsung platforms reuse a common
>> platform-device definition for the s3c64xx-spi and simply will set the correct
>> name when the machine type is determined during boot.
>
> Right, that doesn't mean this is a great way of doing things, though -
> it's been a frequent source of errors in the past and is painful to
> debug as the data structures get rewritten during boot which is a bit of
> a surprise.
>
>> The alternative is creating a mulitude of platform devices for each possible
>> machine type using this driver.
>
> Yes, that's the normal way of handling this and is actually what the
> code was originally doing - there's a bunch of ifdefed devices in
> plat-samsung/devs.c. You usually have to do this anyway as the IPs move
> about so the resources need changing.
In addition to the setting the name, the platform data is also
assigned at runtime. Adding multiple platform devices means that we
add lot more code in setting up the platform data. And since we are
moving towards adopting dt, these would anyway go away when we have
all the platforms migrated to dt.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
@ 2012-05-09 14:22 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 14:22 UTC (permalink / raw)
To: linux-arm-kernel
On 9 May 2012 18:55, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 11:10:14AM +0200, Heiko St?bner wrote:
>
>> Similar to the adc and rtc driver, all Samsung platforms reuse a common
>> platform-device definition for the s3c64xx-spi and simply will set the correct
>> name when the machine type is determined during boot.
>
> Right, that doesn't mean this is a great way of doing things, though -
> it's been a frequent source of errors in the past and is painful to
> debug as the data structures get rewritten during boot which is a bit of
> a surprise.
>
>> The alternative is creating a mulitude of platform devices for each possible
>> machine type using this driver.
>
> Yes, that's the normal way of handling this and is actually what the
> code was originally doing - there's a bunch of ifdefed devices in
> plat-samsung/devs.c. ?You usually have to do this anyway as the IPs move
> about so the resources need changing.
In addition to the setting the name, the platform data is also
assigned at runtime. Adding multiple platform devices means that we
add lot more code in setting up the platform data. And since we are
moving towards adopting dt, these would anyway go away when we have
all the platforms migrated to dt.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
2012-05-09 13:40 ` Thomas Abraham
@ 2012-05-09 14:28 ` Mark Brown
-1 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 14:28 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
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On Wed, May 09, 2012 at 09:40:26PM +0800, Thomas Abraham wrote:
> On 9 May 2012 16:52, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > This should've been squashed into the patch that updated to use driver
> > data in order to avoid breaking bisection.
> This patch updates clock devname in the platform code and the
> modifications to use driver data is in the driver file. So these two
> changes are kept separate to allow them to be applied to their
> respective trees.
This means that bisection will be broken - anything with only one tree
won't be able to load the SPI driver successfully until it's merged
with the other which isn't ideal.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
@ 2012-05-09 14:28 ` Mark Brown
0 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 14:28 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 09, 2012 at 09:40:26PM +0800, Thomas Abraham wrote:
> On 9 May 2012 16:52, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > This should've been squashed into the patch that updated to use driver
> > data in order to avoid breaking bisection.
> This patch updates clock devname in the platform code and the
> modifications to use driver data is in the driver file. So these two
> changes are kept separate to allow them to be applied to their
> respective trees.
This means that bisection will be broken - anything with only one tree
won't be able to load the SPI driver successfully until it's merged
with the other which isn't ideal.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 10/10] spi: s3c64xx: add device tree support
2012-05-09 14:13 ` Thomas Abraham
@ 2012-05-09 14:32 ` Mark Brown
-1 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 14:32 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
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On Wed, May 09, 2012 at 10:13:28PM +0800, Thomas Abraham wrote:
> On 9 May 2012 17:07, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > On Wed, May 09, 2012 at 03:34:54AM +0530, Thomas Abraham wrote:
> >> +- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
> >> + particular order). The format of the gpio specifier depends on the gpio
> >> + controller.
> > This seems odd... This isn't a bitbanging controller, and surely the
> > driver will need to know which signal is which? I suspect this is
> > actually for pinmux rather than to identify the signals but that should
> > at least be made clear and really should be being done using the pinmux
> > API.
> The driver retrieves the list of gpio's that it is allowed to use. The
> gpio numbers for miso, mosi and clk are mandatory but the order in
> which they are specified is not important since the driver never needs
> to which gpio is which interface line. I agree the pinmux api should
> be used here, but the call to pinmux api would be a incremental change
> here, not changing the code this patch is adding.
I'd suggest just specifying the order - someone might want to use it
later for some reason and it's not really a hardship for someone to use
it. Avoids any "how does that work?" questions like I had.
> >> + - samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
> >> + the slave select line by the spi controller. The format of the gpio
> >> + specifier depends on the gpio controller.
> > We should really have a binding for this at the SPI level (and ideally
> > some code to manage setting the GPIO too) - it's pretty common to use a
> > GPIO as /CS.
> The existing implementations vary in the way the nCS gpio lines are
> specified. For some controllers, the nCS gpio's are included in the
> spi device node whereas in this implementation, the nCS gpio is listed
> in the spi slave device node.
Yeah, I know. I'm saying we should try to come up with a binding for
this that can be used by new SPI contollers going forward so things are
consistent.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 10/10] spi: s3c64xx: add device tree support
@ 2012-05-09 14:32 ` Mark Brown
0 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 14:32 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 09, 2012 at 10:13:28PM +0800, Thomas Abraham wrote:
> On 9 May 2012 17:07, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > On Wed, May 09, 2012 at 03:34:54AM +0530, Thomas Abraham wrote:
> >> +- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
> >> + ?particular order). The format of the gpio specifier depends on the gpio
> >> + ?controller.
> > This seems odd... ?This isn't a bitbanging controller, and surely the
> > driver will need to know which signal is which? ?I suspect this is
> > actually for pinmux rather than to identify the signals but that should
> > at least be made clear and really should be being done using the pinmux
> > API.
> The driver retrieves the list of gpio's that it is allowed to use. The
> gpio numbers for miso, mosi and clk are mandatory but the order in
> which they are specified is not important since the driver never needs
> to which gpio is which interface line. I agree the pinmux api should
> be used here, but the call to pinmux api would be a incremental change
> here, not changing the code this patch is adding.
I'd suggest just specifying the order - someone might want to use it
later for some reason and it's not really a hardship for someone to use
it. Avoids any "how does that work?" questions like I had.
> >> + ?- samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
> >> + ? ?the slave select line by the spi controller. The format of the gpio
> >> + ? ?specifier depends on the gpio controller.
> > We should really have a binding for this at the SPI level (and ideally
> > some code to manage setting the GPIO too) - it's pretty common to use a
> > GPIO as /CS.
> The existing implementations vary in the way the nCS gpio lines are
> specified. For some controllers, the nCS gpio's are included in the
> spi device node whereas in this implementation, the nCS gpio is listed
> in the spi slave device node.
Yeah, I know. I'm saying we should try to come up with a binding for
this that can be used by new SPI contollers going forward so things are
consistent.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
2012-05-09 14:22 ` Thomas Abraham
@ 2012-05-09 14:33 ` Mark Brown
-1 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 14:33 UTC (permalink / raw)
To: Thomas Abraham
Cc: Heiko Stübner, spi-devel-general, devicetree-discuss,
kgene.kim, rob.herring, grant.likely, jaswinder.singh,
linux-samsung-soc, linux-arm-kernel
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On Wed, May 09, 2012 at 10:22:26PM +0800, Thomas Abraham wrote:
> On 9 May 2012 18:55, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > Yes, that's the normal way of handling this and is actually what the
> > code was originally doing - there's a bunch of ifdefed devices in
> > plat-samsung/devs.c. You usually have to do this anyway as the IPs move
> > about so the resources need changing.
> In addition to the setting the name, the platform data is also
> assigned at runtime. Adding multiple platform devices means that we
> add lot more code in setting up the platform data. And since we are
> moving towards adopting dt, these would anyway go away when we have
> all the platforms migrated to dt.
With your refactoring the only platform data that's left is the /CS?
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^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
@ 2012-05-09 14:33 ` Mark Brown
0 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 14:33 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 09, 2012 at 10:22:26PM +0800, Thomas Abraham wrote:
> On 9 May 2012 18:55, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > Yes, that's the normal way of handling this and is actually what the
> > code was originally doing - there's a bunch of ifdefed devices in
> > plat-samsung/devs.c. ?You usually have to do this anyway as the IPs move
> > about so the resources need changing.
> In addition to the setting the name, the platform data is also
> assigned at runtime. Adding multiple platform devices means that we
> add lot more code in setting up the platform data. And since we are
> moving towards adopting dt, these would anyway go away when we have
> all the platforms migrated to dt.
With your refactoring the only platform data that's left is the /CS?
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^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
2012-05-09 14:33 ` Mark Brown
@ 2012-05-09 15:06 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 15:06 UTC (permalink / raw)
To: Mark Brown
Cc: Heiko Stübner, spi-devel-general, devicetree-discuss,
kgene.kim, rob.herring, grant.likely, jaswinder.singh,
linux-samsung-soc, linux-arm-kernel
On 9 May 2012 22:33, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 10:22:26PM +0800, Thomas Abraham wrote:
>> On 9 May 2012 18:55, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
>
>> > Yes, that's the normal way of handling this and is actually what the
>> > code was originally doing - there's a bunch of ifdefed devices in
>> > plat-samsung/devs.c. You usually have to do this anyway as the IPs move
>> > about so the resources need changing.
>
>> In addition to the setting the name, the platform data is also
>> assigned at runtime. Adding multiple platform devices means that we
>> add lot more code in setting up the platform data. And since we are
>> moving towards adopting dt, these would anyway go away when we have
>> all the platforms migrated to dt.
>
> With your refactoring the only platform data that's left is the /CS?
The nCS line is not part of the platform data. It is part of the spi
board info. There are three elements in the platform data after the
re-factoring which is used on only non-dt platforms - (a) the clock
source number to be selected as the bus clock in the spi controller's
clock mux, (b) the number of nCS lines emulated by the controller and
(c) the gpio setup callback function. With device tree, all this
information is obtained from the device tree.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
@ 2012-05-09 15:06 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 15:06 UTC (permalink / raw)
To: linux-arm-kernel
On 9 May 2012 22:33, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 10:22:26PM +0800, Thomas Abraham wrote:
>> On 9 May 2012 18:55, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
>
>> > Yes, that's the normal way of handling this and is actually what the
>> > code was originally doing - there's a bunch of ifdefed devices in
>> > plat-samsung/devs.c. ?You usually have to do this anyway as the IPs move
>> > about so the resources need changing.
>
>> In addition to the setting the name, the platform data is also
>> assigned at runtime. Adding multiple platform devices means that we
>> add lot more code in setting up the platform data. And since we are
>> moving towards adopting dt, these would anyway go away when we have
>> all the platforms migrated to dt.
>
> With your refactoring the only platform data that's left is the /CS?
The nCS line is not part of the platform data. It is part of the spi
board info. There are three elements in the platform data after the
re-factoring which is used on only non-dt platforms - (a) the clock
source number to be selected as the bus clock in the spi controller's
clock mux, (b) the number of nCS lines emulated by the controller and
(c) the gpio setup callback function. With device tree, all this
information is obtained from the device tree.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 10/10] spi: s3c64xx: add device tree support
2012-05-09 14:32 ` Mark Brown
@ 2012-05-09 16:39 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 16:39 UTC (permalink / raw)
To: Mark Brown
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
On 9 May 2012 22:32, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 10:13:28PM +0800, Thomas Abraham wrote:
>> On 9 May 2012 17:07, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
>> > On Wed, May 09, 2012 at 03:34:54AM +0530, Thomas Abraham wrote:
>
>> >> +- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
>> >> + particular order). The format of the gpio specifier depends on the gpio
>> >> + controller.
>
>> > This seems odd... This isn't a bitbanging controller, and surely the
>> > driver will need to know which signal is which? I suspect this is
>> > actually for pinmux rather than to identify the signals but that should
>> > at least be made clear and really should be being done using the pinmux
>> > API.
>
>> The driver retrieves the list of gpio's that it is allowed to use. The
>> gpio numbers for miso, mosi and clk are mandatory but the order in
>> which they are specified is not important since the driver never needs
>> to which gpio is which interface line. I agree the pinmux api should
>> be used here, but the call to pinmux api would be a incremental change
>> here, not changing the code this patch is adding.
>
> I'd suggest just specifying the order - someone might want to use it
> later for some reason and it's not really a hardship for someone to use
> it. Avoids any "how does that work?" questions like I had.
Ok. I will add the order of the gpios as you have suggested.
>
>> >> + - samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
>> >> + the slave select line by the spi controller. The format of the gpio
>> >> + specifier depends on the gpio controller.
>
>> > We should really have a binding for this at the SPI level (and ideally
>> > some code to manage setting the GPIO too) - it's pretty common to use a
>> > GPIO as /CS.
>
>> The existing implementations vary in the way the nCS gpio lines are
>> specified. For some controllers, the nCS gpio's are included in the
>> spi device node whereas in this implementation, the nCS gpio is listed
>> in the spi slave device node.
>
> Yeah, I know. I'm saying we should try to come up with a binding for
> this that can be used by new SPI contollers going forward so things are
> consistent.
Ok. For this patch series, I will continue with the samsung specific
binding for the nCS line.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 10/10] spi: s3c64xx: add device tree support
@ 2012-05-09 16:39 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 16:39 UTC (permalink / raw)
To: linux-arm-kernel
On 9 May 2012 22:32, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 10:13:28PM +0800, Thomas Abraham wrote:
>> On 9 May 2012 17:07, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
>> > On Wed, May 09, 2012 at 03:34:54AM +0530, Thomas Abraham wrote:
>
>> >> +- gpios: The gpio specifier for clock, mosi and miso interface lines (in no
>> >> + ?particular order). The format of the gpio specifier depends on the gpio
>> >> + ?controller.
>
>> > This seems odd... ?This isn't a bitbanging controller, and surely the
>> > driver will need to know which signal is which? ?I suspect this is
>> > actually for pinmux rather than to identify the signals but that should
>> > at least be made clear and really should be being done using the pinmux
>> > API.
>
>> The driver retrieves the list of gpio's that it is allowed to use. The
>> gpio numbers for miso, mosi and clk are mandatory but the order in
>> which they are specified is not important since the driver never needs
>> to which gpio is which interface line. I agree the pinmux api should
>> be used here, but the call to pinmux api would be a incremental change
>> here, not changing the code this patch is adding.
>
> I'd suggest just specifying the order - someone might want to use it
> later for some reason and it's not really a hardship for someone to use
> it. ?Avoids any "how does that work?" questions like I had.
Ok. I will add the order of the gpios as you have suggested.
>
>> >> + ?- samsung,spi-cs-gpio: A gpio specifier that specifies the gpio line used as
>> >> + ? ?the slave select line by the spi controller. The format of the gpio
>> >> + ? ?specifier depends on the gpio controller.
>
>> > We should really have a binding for this at the SPI level (and ideally
>> > some code to manage setting the GPIO too) - it's pretty common to use a
>> > GPIO as /CS.
>
>> The existing implementations vary in the way the nCS gpio lines are
>> specified. For some controllers, the nCS gpio's are included in the
>> spi device node whereas in this implementation, the nCS gpio is listed
>> in the spi slave device node.
>
> Yeah, I know. ?I'm saying we should try to come up with a binding for
> this that can be used by new SPI contollers going forward so things are
> consistent.
Ok. For this patch series, I will continue with the samsung specific
binding for the nCS line.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 10/10] spi: s3c64xx: add device tree support
2012-05-09 16:39 ` Thomas Abraham
@ 2012-05-09 16:47 ` Mark Brown
-1 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 16:47 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 629 bytes --]
On Thu, May 10, 2012 at 12:39:29AM +0800, Thomas Abraham wrote:
> On 9 May 2012 22:32, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > Yeah, I know. I'm saying we should try to come up with a binding for
> > this that can be used by new SPI contollers going forward so things are
> > consistent.
> Ok. For this patch series, I will continue with the samsung specific
> binding for the nCS line.
How about just renaming your binding to a generic one and documenting it
separately? It looks like a sensible binding which other people should
be able to use so may as well have something there already.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 10/10] spi: s3c64xx: add device tree support
@ 2012-05-09 16:47 ` Mark Brown
0 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-09 16:47 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 10, 2012 at 12:39:29AM +0800, Thomas Abraham wrote:
> On 9 May 2012 22:32, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > Yeah, I know. ?I'm saying we should try to come up with a binding for
> > this that can be used by new SPI contollers going forward so things are
> > consistent.
> Ok. For this patch series, I will continue with the samsung specific
> binding for the nCS line.
How about just renaming your binding to a generic one and documenting it
separately? It looks like a sensible binding which other people should
be able to use so may as well have something there already.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
2012-05-09 14:28 ` Mark Brown
@ 2012-05-09 17:17 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 17:17 UTC (permalink / raw)
To: Mark Brown
Cc: kgene.kim-Sze3O3UU22JBDgjK7y7TUQ,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 9 May 2012 22:28, Mark Brown <broonie-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org> wrote:
> On Wed, May 09, 2012 at 09:40:26PM +0800, Thomas Abraham wrote:
>> On 9 May 2012 16:52, Mark Brown <broonie-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org> wrote:
>
>> > This should've been squashed into the patch that updated to use driver
>> > data in order to avoid breaking bisection.
>
>> This patch updates clock devname in the platform code and the
>> modifications to use driver data is in the driver file. So these two
>> changes are kept separate to allow them to be applied to their
>> respective trees.
>
> This means that bisection will be broken - anything with only one tree
> won't be able to load the SPI driver successfully until it's merged
> with the other which isn't ideal.
Yes, we would have that problem until the two trees are merged. But I
still prefer not to squash the two patches which already contain huge
diff.
Thanks,
Thomas.
------------------------------------------------------------------------------
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^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
@ 2012-05-09 17:17 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 17:17 UTC (permalink / raw)
To: linux-arm-kernel
On 9 May 2012 22:28, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Wed, May 09, 2012 at 09:40:26PM +0800, Thomas Abraham wrote:
>> On 9 May 2012 16:52, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
>
>> > This should've been squashed into the patch that updated to use driver
>> > data in order to avoid breaking bisection.
>
>> This patch updates clock devname in the platform code and the
>> modifications to use driver data is in the driver file. So these two
>> changes are kept separate to allow them to be applied to their
>> respective trees.
>
> This means that bisection will be broken - anything with only one tree
> won't be able to load the SPI driver successfully until it's merged
> with the other which isn't ideal.
Yes, we would have that problem until the two trees are merged. But I
still prefer not to squash the two patches which already contain huge
diff.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 10/10] spi: s3c64xx: add device tree support
2012-05-09 16:47 ` Mark Brown
@ 2012-05-09 17:19 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 17:19 UTC (permalink / raw)
To: Mark Brown
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
On 10 May 2012 00:47, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Thu, May 10, 2012 at 12:39:29AM +0800, Thomas Abraham wrote:
>> On 9 May 2012 22:32, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
>
>> > Yeah, I know. I'm saying we should try to come up with a binding for
>> > this that can be used by new SPI contollers going forward so things are
>> > consistent.
>
>> Ok. For this patch series, I will continue with the samsung specific
>> binding for the nCS line.
>
> How about just renaming your binding to a generic one and documenting it
> separately? It looks like a sensible binding which other people should
> be able to use so may as well have something there already.
Ok. I will replace the samsung specific binding with a generic binding
in the next version of this patch series.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 10/10] spi: s3c64xx: add device tree support
@ 2012-05-09 17:19 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-09 17:19 UTC (permalink / raw)
To: linux-arm-kernel
On 10 May 2012 00:47, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Thu, May 10, 2012 at 12:39:29AM +0800, Thomas Abraham wrote:
>> On 9 May 2012 22:32, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
>
>> > Yeah, I know. ?I'm saying we should try to come up with a binding for
>> > this that can be used by new SPI contollers going forward so things are
>> > consistent.
>
>> Ok. For this patch series, I will continue with the samsung specific
>> binding for the nCS line.
>
> How about just renaming your binding to a generic one and documenting it
> separately? ?It looks like a sensible binding which other people should
> be able to use so may as well have something there already.
Ok. I will replace the samsung specific binding with a generic binding
in the next version of this patch series.
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
2012-05-09 17:17 ` Thomas Abraham
@ 2012-05-13 14:51 ` Mark Brown
-1 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-13 14:51 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
grant.likely, jaswinder.singh, linux-samsung-soc,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 740 bytes --]
On Thu, May 10, 2012 at 01:17:32AM +0800, Thomas Abraham wrote:
> On 9 May 2012 22:28, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > This means that bisection will be broken - anything with only one tree
> > won't be able to load the SPI driver successfully until it's merged
> > with the other which isn't ideal.
> Yes, we would have that problem until the two trees are merged. But I
> still prefer not to squash the two patches which already contain huge
> diff.
I'd not say the diff is *that* big (and most of what's there is simple
and repetitive), and bisection is a very useful tool. I know I
frequently find it enormously painful trying to figure out breakage when
large chunks of the history don't work usefully.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
@ 2012-05-13 14:51 ` Mark Brown
0 siblings, 0 replies; 78+ messages in thread
From: Mark Brown @ 2012-05-13 14:51 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, May 10, 2012 at 01:17:32AM +0800, Thomas Abraham wrote:
> On 9 May 2012 22:28, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> > This means that bisection will be broken - anything with only one tree
> > won't be able to load the SPI driver successfully until it's merged
> > with the other which isn't ideal.
> Yes, we would have that problem until the two trees are merged. But I
> still prefer not to squash the two patches which already contain huge
> diff.
I'd not say the diff is *that* big (and most of what's there is simple
and repetitive), and bisection is a very useful tool. I know I
frequently find it enormously painful trying to figure out breakage when
large chunks of the history don't work usefully.
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^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 01/10] spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-20 4:41 ` Grant Likely
-1 siblings, 0 replies; 78+ messages in thread
From: Grant Likely @ 2012-05-20 4:41 UTC (permalink / raw)
To: Thomas Abraham, spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, kgene.kim,
jaswinder.singh
On Wed, 09 May 2012 03:34:45 +0530, Thomas Abraham <thomas.abraham@linaro.org> wrote:
> The macro S3C64XX_SPI_ST_TRLCNTZ is not used and hence it is removed.
>
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Since this series has dependencies, I'm fine with it going via another
tree.
g.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 01/10] spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
@ 2012-05-20 4:41 ` Grant Likely
0 siblings, 0 replies; 78+ messages in thread
From: Grant Likely @ 2012-05-20 4:41 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 09 May 2012 03:34:45 +0530, Thomas Abraham <thomas.abraham@linaro.org> wrote:
> The macro S3C64XX_SPI_ST_TRLCNTZ is not used and hence it is removed.
>
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Since this series has dependencies, I'm fine with it going via another
tree.
g.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 02/10] spi: s3c64xx: move controller information into driver data
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-20 4:42 ` Grant Likely
-1 siblings, 0 replies; 78+ messages in thread
From: Grant Likely @ 2012-05-20 4:42 UTC (permalink / raw)
To: Thomas Abraham, spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, kgene.kim,
jaswinder.singh
On Wed, 09 May 2012 03:34:46 +0530, Thomas Abraham <thomas.abraham@linaro.org> wrote:
> Platform data is used to specify controller hardware specific information
> such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
> information is not suitable to be supplied from device tree. Instead,
> it can be moved into the driver data and removed from platform data.
>
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> drivers/spi/spi-s3c64xx.c | 180 ++++++++++++++++++++++++++++++++++++++-------
> 1 files changed, 153 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 6a3d51a..f6bc0e3 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -31,6 +31,8 @@
> #include <mach/dma.h>
> #include <plat/s3c64xx-spi.h>
>
> +#define MAX_SPI_PORTS 3
> +
> /* Registers and bit-fields */
>
> #define S3C64XX_SPI_CH_CFG 0x00
> @@ -113,9 +115,12 @@
>
> #define S3C64XX_SPI_FBCLK_MSK (3<<0)
>
> -#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
> -#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
> -#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
> +#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
> +#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
> + (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
> +#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
> +#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
> + FIFO_LVL_MASK(i))
>
> #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
> #define S3C64XX_SPI_TRAILCNT_OFF 19
> @@ -134,6 +139,28 @@ struct s3c64xx_spi_dma_data {
> };
>
> /**
> + * struct s3c64xx_spi_info - SPI Controller hardware info
> + * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
> + * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
> + * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
> + * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
> + * @clk_from_cmu: True, if the controller does not include a clock mux and
> + * prescaler unit.
> + *
> + * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
> + * differ in some aspects such as the size of the fifo and spi bus clock
> + * setup. Such differences are specified to the driver using this structure
> + * which is provided as driver data to the driver.
> + */
> +struct s3c64xx_spi_port_config {
> + int fifo_lvl_mask[MAX_SPI_PORTS];
> + int rx_lvl_offset;
> + int tx_st_done;
> + bool high_speed;
> + bool clk_from_cmu;
> +};
> +
> +/**
> * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
> * @clk: Pointer to the spi clock.
> * @src_clk: Pointer to the clock used to generate SPI signals.
> @@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data {
> struct s3c64xx_spi_dma_data rx_dma;
> struct s3c64xx_spi_dma_data tx_dma;
> struct samsung_dma_ops *ops;
> + struct s3c64xx_spi_port_config *port_conf;
> + unsigned port_id;
> };
>
> static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
> @@ -179,7 +208,6 @@ static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
>
> static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> void __iomem *regs = sdd->regs;
> unsigned long loops;
> u32 val;
> @@ -195,7 +223,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
> loops = msecs_to_loops(1);
> do {
> val = readl(regs + S3C64XX_SPI_STATUS);
> - } while (TX_FIFO_LVL(val, sci) && loops--);
> + } while (TX_FIFO_LVL(val, sdd) && loops--);
>
> if (loops == 0)
> dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
> @@ -204,7 +232,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
> loops = msecs_to_loops(1);
> do {
> val = readl(regs + S3C64XX_SPI_STATUS);
> - if (RX_FIFO_LVL(val, sci))
> + if (RX_FIFO_LVL(val, sdd))
> readl(regs + S3C64XX_SPI_RX_DATA);
> else
> break;
> @@ -302,7 +330,6 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
> struct spi_device *spi,
> struct spi_transfer *xfer, int dma_mode)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> void __iomem *regs = sdd->regs;
> u32 modecfg, chcfg;
>
> @@ -352,7 +379,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
> if (xfer->rx_buf != NULL) {
> sdd->state |= RXBUSY;
>
> - if (sci->high_speed && sdd->cur_speed >= 30000000UL
> + if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
> && !(sdd->cur_mode & SPI_CPHA))
> chcfg |= S3C64XX_SPI_CH_HS_EN;
>
> @@ -392,7 +419,6 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
> static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> struct spi_transfer *xfer, int dma_mode)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> void __iomem *regs = sdd->regs;
> unsigned long val;
> int ms;
> @@ -409,7 +435,7 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> val = msecs_to_loops(ms);
> do {
> status = readl(regs + S3C64XX_SPI_STATUS);
> - } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
> + } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
> }
>
> if (!val)
> @@ -428,8 +454,8 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> if (xfer->rx_buf == NULL) {
> val = msecs_to_loops(10);
> status = readl(regs + S3C64XX_SPI_STATUS);
> - while ((TX_FIFO_LVL(status, sci)
> - || !S3C64XX_SPI_ST_TX_DONE(status, sci))
> + while ((TX_FIFO_LVL(status, sdd)
> + || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
> && --val) {
> cpu_relax();
> status = readl(regs + S3C64XX_SPI_STATUS);
> @@ -478,12 +504,11 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
>
> static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> void __iomem *regs = sdd->regs;
> u32 val;
>
> /* Disable Clock */
> - if (sci->clk_from_cmu) {
> + if (sdd->port_conf->clk_from_cmu) {
> clk_disable(sdd->src_clk);
> } else {
> val = readl(regs + S3C64XX_SPI_CLK_CFG);
> @@ -527,7 +552,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
>
> writel(val, regs + S3C64XX_SPI_MODE_CFG);
>
> - if (sci->clk_from_cmu) {
> + if (sdd->port_conf->clk_from_cmu) {
> /* Configure Clock */
> /* There is half-multiplier before the SPI */
> clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
> @@ -553,7 +578,6 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
> static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
> struct spi_message *msg)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> struct device *dev = &sdd->pdev->dev;
> struct spi_transfer *xfer;
>
> @@ -569,7 +593,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
> /* Map until end or first fail */
> list_for_each_entry(xfer, &msg->transfers, transfer_list) {
>
> - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
> + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
> continue;
>
> if (xfer->tx_buf != NULL) {
> @@ -603,7 +627,6 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
> static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
> struct spi_message *msg)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> struct device *dev = &sdd->pdev->dev;
> struct spi_transfer *xfer;
>
> @@ -612,7 +635,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
>
> list_for_each_entry(xfer, &msg->transfers, transfer_list) {
>
> - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
> + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
> continue;
>
> if (xfer->rx_buf != NULL
> @@ -631,7 +654,6 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
> struct spi_message *msg)
> {
> struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> struct spi_device *spi = msg->spi;
> struct s3c64xx_spi_csinfo *cs = spi->controller_data;
> struct spi_transfer *xfer;
> @@ -686,7 +708,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
> }
>
> /* Polling method for xfers not bigger than FIFO capacity */
> - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
> + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
> use_dma = 0;
> else
> use_dma = 1;
> @@ -840,7 +862,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
> pm_runtime_get_sync(&sdd->pdev->dev);
>
> /* Check if we can provide the requested rate */
> - if (!sci->clk_from_cmu) {
> + if (!sdd->port_conf->clk_from_cmu) {
> u32 psr, speed;
>
> /* Max possible */
> @@ -921,7 +943,7 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
> /* Disable Interrupts - we use Polling if not DMA mode */
> writel(0, regs + S3C64XX_SPI_INT_EN);
>
> - if (!sci->clk_from_cmu)
> + if (!sdd->port_conf->clk_from_cmu)
> writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
> regs + S3C64XX_SPI_CLK_CFG);
> writel(0, regs + S3C64XX_SPI_MODE_CFG);
> @@ -942,6 +964,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
> flush_fifo(sdd);
> }
>
> +static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
> + struct platform_device *pdev)
> +{
> + return (struct s3c64xx_spi_port_config *)
> + platform_get_device_id(pdev)->driver_data;
> +}
> +
> static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> {
> struct resource *mem_res, *dmatx_res, *dmarx_res;
> @@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> platform_set_drvdata(pdev, master);
>
> sdd = spi_master_get_devdata(master);
> + sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
> sdd->master = master;
> sdd->cntrlr_info = sci;
> sdd->pdev = pdev;
> @@ -1008,10 +1038,11 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> sdd->tx_dma.direction = DMA_MEM_TO_DEV;
> sdd->rx_dma.dmach = dmarx_res->start;
> sdd->rx_dma.direction = DMA_DEV_TO_MEM;
> + sdd->port_id = pdev->id;
>
> sdd->cur_bpw = 8;
>
> - master->bus_num = pdev->id;
> + master->bus_num = sdd->port_id;
> master->setup = s3c64xx_spi_setup;
> master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
> master->transfer_one_message = s3c64xx_spi_transfer_one_message;
> @@ -1071,7 +1102,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> }
>
> /* Setup Deufult Mode */
> - s3c64xx_spi_hwinit(sdd, pdev->id);
> + s3c64xx_spi_hwinit(sdd, sdd->port_id);
>
> spin_lock_init(&sdd->lock);
> init_completion(&sdd->xfer_completion);
> @@ -1096,7 +1127,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
>
> dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
> "with %d Slaves attached\n",
> - pdev->id, master->num_chipselect);
> + sdd->port_id, master->num_chipselect);
> dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
> mem_res->end, mem_res->start,
> sdd->rx_dma.dmach, sdd->tx_dma.dmach);
> @@ -1189,7 +1220,7 @@ static int s3c64xx_spi_resume(struct device *dev)
> clk_enable(sdd->src_clk);
> clk_enable(sdd->clk);
>
> - s3c64xx_spi_hwinit(sdd, pdev->id);
> + s3c64xx_spi_hwinit(sdd, sdd->port_id);
>
> spi_master_resume(master);
>
> @@ -1227,6 +1258,100 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
> s3c64xx_spi_runtime_resume, NULL)
> };
>
> +#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
> +struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f },
> + .rx_lvl_offset = 13,
> + .tx_st_done = 21,
> + .high_speed = true,
> +};
> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c2443_spi_port_config)
> +#else
> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif
> +
> +#ifdef CONFIG_ARCH_S3C64XX
> +struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f, 0x7F },
> + .rx_lvl_offset = 13,
> + .tx_st_done = 21,
> +};
> +#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c6410_spi_port_config)
> +#else
> +#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S3C64XX */
> +
> +#ifdef CONFIG_ARCH_S5P64X0
> +struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
> + .fifo_lvl_mask = { 0x1ff, 0x7F },
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> +};
> +#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)&s5p64x0_spi_port_config)
> +#else
> +#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S5P64X0 */
> +
> +#ifdef CONFIG_ARCH_S5PC100
> +struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f, 0x7F },
> + .rx_lvl_offset = 13,
> + .tx_st_done = 21,
> + .high_speed = true,
> +};
> +#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pc100_spi_port_config)
> +#else
> +#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S5PC100 */
> +
> +#ifdef CONFIG_ARCH_S5PV210
> +struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
> + .fifo_lvl_mask = { 0x1ff, 0x7F },
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .high_speed = 1,
> +};
> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pv210_spi_port_config)
> +#else
> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S5PV210 */
> +
> +#ifdef CONFIG_ARCH_EXYNOS4
> +struct s3c64xx_spi_port_config exynos4_spi_port_config = {
> + .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .high_speed = 1,
> + .clk_from_cmu = true,
> +};
> +#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)&exynos4_spi_port_config)
> +#else
> +#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_EXYNOS4 */
> +
> +static struct platform_device_id s3c64xx_spi_driver_ids[] = {
> + {
> + .name = "s3c2443-spi",
> + .driver_data = S3C2443_SPI_PORT_CONFIG,
> + }, {
> + .name = "s3c6410-spi",
> + .driver_data = S3C6410_SPI_PORT_CONFIG,
> + }, {
> + .name = "s5p64x0-spi",
> + .driver_data = S5P64X0_SPI_PORT_CONFIG,
> + }, {
> + .name = "s5pc100-spi",
> + .driver_data = S5PC100_SPI_PORT_CONFIG,
> + }, {
> + .name = "s5pv210-spi",
> + .driver_data = S5PV210_SPI_PORT_CONFIG,
> + }, {
> + .name = "exynos4210-spi",
> + .driver_data = EXYNOS4_SPI_PORT_CONFIG,
> + },
> + { },
> +};
> +
> static struct platform_driver s3c64xx_spi_driver = {
> .driver = {
> .name = "s3c64xx-spi",
> @@ -1234,6 +1359,7 @@ static struct platform_driver s3c64xx_spi_driver = {
> .pm = &s3c64xx_spi_pm,
> },
> .remove = s3c64xx_spi_remove,
> + .id_table = s3c64xx_spi_driver_ids,
> };
> MODULE_ALIAS("platform:s3c64xx-spi");
>
> --
> 1.6.6.rc2
>
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 02/10] spi: s3c64xx: move controller information into driver data
@ 2012-05-20 4:42 ` Grant Likely
0 siblings, 0 replies; 78+ messages in thread
From: Grant Likely @ 2012-05-20 4:42 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 09 May 2012 03:34:46 +0530, Thomas Abraham <thomas.abraham@linaro.org> wrote:
> Platform data is used to specify controller hardware specific information
> such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
> information is not suitable to be supplied from device tree. Instead,
> it can be moved into the driver data and removed from platform data.
>
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> drivers/spi/spi-s3c64xx.c | 180 ++++++++++++++++++++++++++++++++++++++-------
> 1 files changed, 153 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 6a3d51a..f6bc0e3 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -31,6 +31,8 @@
> #include <mach/dma.h>
> #include <plat/s3c64xx-spi.h>
>
> +#define MAX_SPI_PORTS 3
> +
> /* Registers and bit-fields */
>
> #define S3C64XX_SPI_CH_CFG 0x00
> @@ -113,9 +115,12 @@
>
> #define S3C64XX_SPI_FBCLK_MSK (3<<0)
>
> -#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
> -#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
> -#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
> +#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
> +#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
> + (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
> +#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
> +#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
> + FIFO_LVL_MASK(i))
>
> #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
> #define S3C64XX_SPI_TRAILCNT_OFF 19
> @@ -134,6 +139,28 @@ struct s3c64xx_spi_dma_data {
> };
>
> /**
> + * struct s3c64xx_spi_info - SPI Controller hardware info
> + * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
> + * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
> + * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
> + * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
> + * @clk_from_cmu: True, if the controller does not include a clock mux and
> + * prescaler unit.
> + *
> + * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
> + * differ in some aspects such as the size of the fifo and spi bus clock
> + * setup. Such differences are specified to the driver using this structure
> + * which is provided as driver data to the driver.
> + */
> +struct s3c64xx_spi_port_config {
> + int fifo_lvl_mask[MAX_SPI_PORTS];
> + int rx_lvl_offset;
> + int tx_st_done;
> + bool high_speed;
> + bool clk_from_cmu;
> +};
> +
> +/**
> * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
> * @clk: Pointer to the spi clock.
> * @src_clk: Pointer to the clock used to generate SPI signals.
> @@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data {
> struct s3c64xx_spi_dma_data rx_dma;
> struct s3c64xx_spi_dma_data tx_dma;
> struct samsung_dma_ops *ops;
> + struct s3c64xx_spi_port_config *port_conf;
> + unsigned port_id;
> };
>
> static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
> @@ -179,7 +208,6 @@ static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
>
> static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> void __iomem *regs = sdd->regs;
> unsigned long loops;
> u32 val;
> @@ -195,7 +223,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
> loops = msecs_to_loops(1);
> do {
> val = readl(regs + S3C64XX_SPI_STATUS);
> - } while (TX_FIFO_LVL(val, sci) && loops--);
> + } while (TX_FIFO_LVL(val, sdd) && loops--);
>
> if (loops == 0)
> dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
> @@ -204,7 +232,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
> loops = msecs_to_loops(1);
> do {
> val = readl(regs + S3C64XX_SPI_STATUS);
> - if (RX_FIFO_LVL(val, sci))
> + if (RX_FIFO_LVL(val, sdd))
> readl(regs + S3C64XX_SPI_RX_DATA);
> else
> break;
> @@ -302,7 +330,6 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
> struct spi_device *spi,
> struct spi_transfer *xfer, int dma_mode)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> void __iomem *regs = sdd->regs;
> u32 modecfg, chcfg;
>
> @@ -352,7 +379,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
> if (xfer->rx_buf != NULL) {
> sdd->state |= RXBUSY;
>
> - if (sci->high_speed && sdd->cur_speed >= 30000000UL
> + if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
> && !(sdd->cur_mode & SPI_CPHA))
> chcfg |= S3C64XX_SPI_CH_HS_EN;
>
> @@ -392,7 +419,6 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
> static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> struct spi_transfer *xfer, int dma_mode)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> void __iomem *regs = sdd->regs;
> unsigned long val;
> int ms;
> @@ -409,7 +435,7 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> val = msecs_to_loops(ms);
> do {
> status = readl(regs + S3C64XX_SPI_STATUS);
> - } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
> + } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
> }
>
> if (!val)
> @@ -428,8 +454,8 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> if (xfer->rx_buf == NULL) {
> val = msecs_to_loops(10);
> status = readl(regs + S3C64XX_SPI_STATUS);
> - while ((TX_FIFO_LVL(status, sci)
> - || !S3C64XX_SPI_ST_TX_DONE(status, sci))
> + while ((TX_FIFO_LVL(status, sdd)
> + || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
> && --val) {
> cpu_relax();
> status = readl(regs + S3C64XX_SPI_STATUS);
> @@ -478,12 +504,11 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
>
> static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> void __iomem *regs = sdd->regs;
> u32 val;
>
> /* Disable Clock */
> - if (sci->clk_from_cmu) {
> + if (sdd->port_conf->clk_from_cmu) {
> clk_disable(sdd->src_clk);
> } else {
> val = readl(regs + S3C64XX_SPI_CLK_CFG);
> @@ -527,7 +552,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
>
> writel(val, regs + S3C64XX_SPI_MODE_CFG);
>
> - if (sci->clk_from_cmu) {
> + if (sdd->port_conf->clk_from_cmu) {
> /* Configure Clock */
> /* There is half-multiplier before the SPI */
> clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
> @@ -553,7 +578,6 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
> static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
> struct spi_message *msg)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> struct device *dev = &sdd->pdev->dev;
> struct spi_transfer *xfer;
>
> @@ -569,7 +593,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
> /* Map until end or first fail */
> list_for_each_entry(xfer, &msg->transfers, transfer_list) {
>
> - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
> + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
> continue;
>
> if (xfer->tx_buf != NULL) {
> @@ -603,7 +627,6 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
> static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
> struct spi_message *msg)
> {
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> struct device *dev = &sdd->pdev->dev;
> struct spi_transfer *xfer;
>
> @@ -612,7 +635,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
>
> list_for_each_entry(xfer, &msg->transfers, transfer_list) {
>
> - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
> + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
> continue;
>
> if (xfer->rx_buf != NULL
> @@ -631,7 +654,6 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
> struct spi_message *msg)
> {
> struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
> - struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
> struct spi_device *spi = msg->spi;
> struct s3c64xx_spi_csinfo *cs = spi->controller_data;
> struct spi_transfer *xfer;
> @@ -686,7 +708,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
> }
>
> /* Polling method for xfers not bigger than FIFO capacity */
> - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
> + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
> use_dma = 0;
> else
> use_dma = 1;
> @@ -840,7 +862,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
> pm_runtime_get_sync(&sdd->pdev->dev);
>
> /* Check if we can provide the requested rate */
> - if (!sci->clk_from_cmu) {
> + if (!sdd->port_conf->clk_from_cmu) {
> u32 psr, speed;
>
> /* Max possible */
> @@ -921,7 +943,7 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
> /* Disable Interrupts - we use Polling if not DMA mode */
> writel(0, regs + S3C64XX_SPI_INT_EN);
>
> - if (!sci->clk_from_cmu)
> + if (!sdd->port_conf->clk_from_cmu)
> writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
> regs + S3C64XX_SPI_CLK_CFG);
> writel(0, regs + S3C64XX_SPI_MODE_CFG);
> @@ -942,6 +964,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
> flush_fifo(sdd);
> }
>
> +static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
> + struct platform_device *pdev)
> +{
> + return (struct s3c64xx_spi_port_config *)
> + platform_get_device_id(pdev)->driver_data;
> +}
> +
> static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> {
> struct resource *mem_res, *dmatx_res, *dmarx_res;
> @@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> platform_set_drvdata(pdev, master);
>
> sdd = spi_master_get_devdata(master);
> + sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
> sdd->master = master;
> sdd->cntrlr_info = sci;
> sdd->pdev = pdev;
> @@ -1008,10 +1038,11 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> sdd->tx_dma.direction = DMA_MEM_TO_DEV;
> sdd->rx_dma.dmach = dmarx_res->start;
> sdd->rx_dma.direction = DMA_DEV_TO_MEM;
> + sdd->port_id = pdev->id;
>
> sdd->cur_bpw = 8;
>
> - master->bus_num = pdev->id;
> + master->bus_num = sdd->port_id;
> master->setup = s3c64xx_spi_setup;
> master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
> master->transfer_one_message = s3c64xx_spi_transfer_one_message;
> @@ -1071,7 +1102,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> }
>
> /* Setup Deufult Mode */
> - s3c64xx_spi_hwinit(sdd, pdev->id);
> + s3c64xx_spi_hwinit(sdd, sdd->port_id);
>
> spin_lock_init(&sdd->lock);
> init_completion(&sdd->xfer_completion);
> @@ -1096,7 +1127,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
>
> dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
> "with %d Slaves attached\n",
> - pdev->id, master->num_chipselect);
> + sdd->port_id, master->num_chipselect);
> dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
> mem_res->end, mem_res->start,
> sdd->rx_dma.dmach, sdd->tx_dma.dmach);
> @@ -1189,7 +1220,7 @@ static int s3c64xx_spi_resume(struct device *dev)
> clk_enable(sdd->src_clk);
> clk_enable(sdd->clk);
>
> - s3c64xx_spi_hwinit(sdd, pdev->id);
> + s3c64xx_spi_hwinit(sdd, sdd->port_id);
>
> spi_master_resume(master);
>
> @@ -1227,6 +1258,100 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
> s3c64xx_spi_runtime_resume, NULL)
> };
>
> +#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
> +struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f },
> + .rx_lvl_offset = 13,
> + .tx_st_done = 21,
> + .high_speed = true,
> +};
> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c2443_spi_port_config)
> +#else
> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif
> +
> +#ifdef CONFIG_ARCH_S3C64XX
> +struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f, 0x7F },
> + .rx_lvl_offset = 13,
> + .tx_st_done = 21,
> +};
> +#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c6410_spi_port_config)
> +#else
> +#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S3C64XX */
> +
> +#ifdef CONFIG_ARCH_S5P64X0
> +struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
> + .fifo_lvl_mask = { 0x1ff, 0x7F },
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> +};
> +#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)&s5p64x0_spi_port_config)
> +#else
> +#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S5P64X0 */
> +
> +#ifdef CONFIG_ARCH_S5PC100
> +struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f, 0x7F },
> + .rx_lvl_offset = 13,
> + .tx_st_done = 21,
> + .high_speed = true,
> +};
> +#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pc100_spi_port_config)
> +#else
> +#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S5PC100 */
> +
> +#ifdef CONFIG_ARCH_S5PV210
> +struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
> + .fifo_lvl_mask = { 0x1ff, 0x7F },
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .high_speed = 1,
> +};
> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pv210_spi_port_config)
> +#else
> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S5PV210 */
> +
> +#ifdef CONFIG_ARCH_EXYNOS4
> +struct s3c64xx_spi_port_config exynos4_spi_port_config = {
> + .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .high_speed = 1,
> + .clk_from_cmu = true,
> +};
> +#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)&exynos4_spi_port_config)
> +#else
> +#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_EXYNOS4 */
> +
> +static struct platform_device_id s3c64xx_spi_driver_ids[] = {
> + {
> + .name = "s3c2443-spi",
> + .driver_data = S3C2443_SPI_PORT_CONFIG,
> + }, {
> + .name = "s3c6410-spi",
> + .driver_data = S3C6410_SPI_PORT_CONFIG,
> + }, {
> + .name = "s5p64x0-spi",
> + .driver_data = S5P64X0_SPI_PORT_CONFIG,
> + }, {
> + .name = "s5pc100-spi",
> + .driver_data = S5PC100_SPI_PORT_CONFIG,
> + }, {
> + .name = "s5pv210-spi",
> + .driver_data = S5PV210_SPI_PORT_CONFIG,
> + }, {
> + .name = "exynos4210-spi",
> + .driver_data = EXYNOS4_SPI_PORT_CONFIG,
> + },
> + { },
> +};
> +
> static struct platform_driver s3c64xx_spi_driver = {
> .driver = {
> .name = "s3c64xx-spi",
> @@ -1234,6 +1359,7 @@ static struct platform_driver s3c64xx_spi_driver = {
> .pm = &s3c64xx_spi_pm,
> },
> .remove = s3c64xx_spi_remove,
> + .id_table = s3c64xx_spi_driver_ids,
> };
> MODULE_ALIAS("platform:s3c64xx-spi");
>
> --
> 1.6.6.rc2
>
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
2012-05-13 14:51 ` Mark Brown
@ 2012-05-20 4:43 ` Grant Likely
-1 siblings, 0 replies; 78+ messages in thread
From: Grant Likely @ 2012-05-20 4:43 UTC (permalink / raw)
To: Mark Brown, Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, kgene.kim, rob.herring,
jaswinder.singh, linux-samsung-soc, linux-arm-kernel
On Sun, 13 May 2012 15:51:35 +0100, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Thu, May 10, 2012 at 01:17:32AM +0800, Thomas Abraham wrote:
> > On 9 May 2012 22:28, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
>
> > > This means that bisection will be broken - anything with only one tree
> > > won't be able to load the SPI driver successfully until it's merged
> > > with the other which isn't ideal.
>
> > Yes, we would have that problem until the two trees are merged. But I
> > still prefer not to squash the two patches which already contain huge
> > diff.
>
> I'd not say the diff is *that* big (and most of what's there is simple
> and repetitive), and bisection is a very useful tool. I know I
> frequently find it enormously painful trying to figure out breakage when
> large chunks of the history don't work usefully.
I agree. Squash them!
g.
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup
@ 2012-05-20 4:43 ` Grant Likely
0 siblings, 0 replies; 78+ messages in thread
From: Grant Likely @ 2012-05-20 4:43 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, 13 May 2012 15:51:35 +0100, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
> On Thu, May 10, 2012 at 01:17:32AM +0800, Thomas Abraham wrote:
> > On 9 May 2012 22:28, Mark Brown <broonie@opensource.wolfsonmicro.com> wrote:
>
> > > This means that bisection will be broken - anything with only one tree
> > > won't be able to load the SPI driver successfully until it's merged
> > > with the other which isn't ideal.
>
> > Yes, we would have that problem until the two trees are merged. But I
> > still prefer not to squash the two patches which already contain huge
> > diff.
>
> I'd not say the diff is *that* big (and most of what's there is simple
> and repetitive), and bisection is a very useful tool. I know I
> frequently find it enormously painful trying to figure out breakage when
> large chunks of the history don't work usefully.
I agree. Squash them!
g.
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-20 4:45 ` Grant Likely
-1 siblings, 0 replies; 78+ messages in thread
From: Grant Likely @ 2012-05-20 4:45 UTC (permalink / raw)
To: Thomas Abraham, spi-devel-general, devicetree-discuss
Cc: linux-arm-kernel, linux-samsung-soc, rob.herring, kgene.kim,
jaswinder.singh
On Wed, 09 May 2012 03:34:51 +0530, Thomas Abraham <thomas.abraham@linaro.org> wrote:
> The set_level callback in the controller data, which is used to configure
> the slave select line, cannot be supported when migrating the driver to
> device tree based discovery. Since all the platforms currently use gpio
> as the slave select line, this callback can be removed from the
> controller data and replaced with call to gpio_set_value in the driver.
>
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 2 --
> drivers/spi/spi-s3c64xx.c | 8 ++++----
> 2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> index a733ce9..48a6495 100644
> --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> @@ -18,7 +18,6 @@ struct platform_device;
> * @fb_delay: Slave specific feedback delay.
> * Refer to FB_CLK_SEL register definition in SPI chapter.
> * @line: Custom 'identity' of the CS line.
> - * @set_level: CS line control.
> *
> * This is per SPI-Slave Chipselect information.
> * Allocate and initialize one in machine init code and make the
> @@ -27,7 +26,6 @@ struct platform_device;
> struct s3c64xx_spi_csinfo {
> u8 fb_delay;
> unsigned line;
> - void (*set_level)(unsigned line_id, int lvl);
> };
>
> /**
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index f6bc0e3..d84ce7f 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -406,14 +406,14 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
> if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
> /* Deselect the last toggled device */
> cs = sdd->tgl_spi->controller_data;
> - cs->set_level(cs->line,
> - spi->mode & SPI_CS_HIGH ? 0 : 1);
> + gpio_set_value(cs->line,
> + spi->mode & SPI_CS_HIGH ? 0 : 1);
> }
> sdd->tgl_spi = NULL;
> }
>
> cs = spi->controller_data;
> - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
> + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
> }
>
> static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> @@ -499,7 +499,7 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
> if (sdd->tgl_spi == spi)
> sdd->tgl_spi = NULL;
>
> - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
> + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
> }
>
> static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
> --
> 1.6.6.rc2
>
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data
@ 2012-05-20 4:45 ` Grant Likely
0 siblings, 0 replies; 78+ messages in thread
From: Grant Likely @ 2012-05-20 4:45 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 09 May 2012 03:34:51 +0530, Thomas Abraham <thomas.abraham@linaro.org> wrote:
> The set_level callback in the controller data, which is used to configure
> the slave select line, cannot be supported when migrating the driver to
> device tree based discovery. Since all the platforms currently use gpio
> as the slave select line, this callback can be removed from the
> controller data and replaced with call to gpio_set_value in the driver.
>
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 2 --
> drivers/spi/spi-s3c64xx.c | 8 ++++----
> 2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> index a733ce9..48a6495 100644
> --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
> @@ -18,7 +18,6 @@ struct platform_device;
> * @fb_delay: Slave specific feedback delay.
> * Refer to FB_CLK_SEL register definition in SPI chapter.
> * @line: Custom 'identity' of the CS line.
> - * @set_level: CS line control.
> *
> * This is per SPI-Slave Chipselect information.
> * Allocate and initialize one in machine init code and make the
> @@ -27,7 +26,6 @@ struct platform_device;
> struct s3c64xx_spi_csinfo {
> u8 fb_delay;
> unsigned line;
> - void (*set_level)(unsigned line_id, int lvl);
> };
>
> /**
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index f6bc0e3..d84ce7f 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -406,14 +406,14 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
> if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
> /* Deselect the last toggled device */
> cs = sdd->tgl_spi->controller_data;
> - cs->set_level(cs->line,
> - spi->mode & SPI_CS_HIGH ? 0 : 1);
> + gpio_set_value(cs->line,
> + spi->mode & SPI_CS_HIGH ? 0 : 1);
> }
> sdd->tgl_spi = NULL;
> }
>
> cs = spi->controller_data;
> - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
> + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
> }
>
> static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
> @@ -499,7 +499,7 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
> if (sdd->tgl_spi == spi)
> sdd->tgl_spi = NULL;
>
> - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
> + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
> }
>
> static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
> --
> 1.6.6.rc2
>
--
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies, Ltd.
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 00/10] spi: s3c64xx: add support for device tree
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-22 12:35 ` padma venkat
-1 siblings, 0 replies; 78+ messages in thread
From: padma venkat @ 2012-05-22 12:35 UTC (permalink / raw)
To: Thomas Abraham
Cc: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ,
rob.herring-bsGFqQB8/DxBDgjK7y7TUQ,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A,
kgene.kim-Sze3O3UU22JBDgjK7y7TUQ,
spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi Thomas,
On Wed, May 9, 2012 at 3:34 AM, Thomas Abraham <thomas.abraham-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
wrote:
> This patch series adds device tree based discovery support for Samsung's
> s3c64xx compatible spi controller. This is mainly tested for Exynos4210
> and Exynos5250 with onboard spi nor flash device.
>
> This patch series is based on Linux 3.4-rc5 with the following two
> patch series applied.
>
> [1]
http://www.mail-archive.com/linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg10494.html
> [PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0
>
> [2]
http://www.mail-archive.com/linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg09640.html
> [PATCH 0/6] S3C24XX: Add support for HSSPI on S3C2416/S3C2443
>
> Thomas Abraham (10):
> spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
> spi: s3c64xx: move controller information into driver data
> ARM: Samsung: Remove spi hardware controller information from platform
data
> ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions
> ARM: Samsung: Update the device names for spi clock lookup
> ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
> spi: s3c64xx: Remove the 'set_level' callback from controller data
> ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
> ARM: Exynos5: Add spi clock support
> spi: s3c64xx: add device tree support
>
> .../devicetree/bindings/spi/spi-samsung.txt | 113 +++++
> arch/arm/mach-exynos/clock-exynos4.c | 66 ++-
> arch/arm/mach-exynos/clock-exynos5.c | 98 ++++
> arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
> arch/arm/mach-exynos/setup-spi.c | 33 +--
> arch/arm/mach-s3c24xx/clock-s3c2416.c | 2 +-
> arch/arm/mach-s3c24xx/clock-s3c2443.c | 2 +-
> arch/arm/mach-s3c24xx/common-s3c2443.c | 4 +-
> arch/arm/mach-s3c24xx/setup-spi.c | 10 +-
> arch/arm/mach-s3c64xx/clock.c | 20 +-
> arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
> arch/arm/mach-s3c64xx/setup-spi.c | 19 +-
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 12 +-
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 12 +-
> arch/arm/mach-s5p64x0/setup-spi.c | 21 +-
> arch/arm/mach-s5pc100/clock.c | 30 +-
> arch/arm/mach-s5pc100/setup-spi.c | 30 +--
> arch/arm/mach-s5pv210/clock.c | 14 +-
> arch/arm/mach-s5pv210/setup-spi.c | 21 +-
> arch/arm/plat-samsung/devs.c | 50 +--
> arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 31 +-
> drivers/spi/spi-s3c64xx.c | 467
+++++++++++++++++---
> 22 files changed, 753 insertions(+), 308 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt
>
>
After applying this patchset, there is a build warning in the boot log.
Below is the warning..
------------[ cut here ]------------
WARNING: at drivers/base/dd.c:257 driver_probe_device+0x1ac/0x218()
Modules linked in:
[<c00159fc>] (unwind_backtrace+0x0/0xfc) from [<c0023e5c>]
(warn_slowpath_common+0x54/0x64)
[<c0023e5c>] (warn_slowpath_common+0x54/0x64) from [<c0023e88>]
(warn_slowpath_null+0x1c/0x24)
[<c0023e88>] (warn_slowpath_null+0x1c/0x24) from [<c02b6670>]
(driver_probe_device+0x1ac/0x218)
[<c02b6670>] (driver_probe_device+0x1ac/0x218) from [<c02b6768>]
(__driver_attach+0x8c/0x90)
[<c02b6768>] (__driver_attach+0x8c/0x90) from [<c02b4ddc>]
(bus_for_each_dev+0x54/0x80)
[<c02b4ddc>] (bus_for_each_dev+0x54/0x80) from [<c02b564c>]
(bus_add_driver+0x1f4/0x2c0)
[<c02b564c>] (bus_add_driver+0x1f4/0x2c0) from [<c02b6d5c>]
(driver_register+0x78/0x180)
[<c02b6d5c>] (driver_register+0x78/0x180) from [<c00085f8>]
(do_one_initcall+0x34/0x180)
[<c00085f8>] (do_one_initcall+0x34/0x180) from [<c069139c>]
(kernel_init+0x114/0x1c0)
[<c069139c>] (kernel_init+0x114/0x1c0) from [<c000ffec>]
(kernel_thread_exit+0x0/0x8)
---[ end trace 6227d56b6a736442 ]---
m25p80 spi1.0: found w25q80, expected w25x80
m25p80 spi1.0: w25q80 (1024 Kbytes)
2 ofpart partitions found on MTD device spi1.0
Creating 2 MTD partitions on "spi1.0":
0x000000000000-0x000000040000 : "U-Boot"
0x000000040000-0x000000100000 : "Kernel"
Thanks&Regards
Padma
> --
> To unsubscribe from this list: send the line "unsubscribe
linux-samsung-soc" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
------------------------------------------------------------------------------
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and
threat landscape has changed and how IT managers can respond. Discussions
will include endpoint security, mobile security and the latest in malware
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 00/10] spi: s3c64xx: add support for device tree
@ 2012-05-22 12:35 ` padma venkat
0 siblings, 0 replies; 78+ messages in thread
From: padma venkat @ 2012-05-22 12:35 UTC (permalink / raw)
To: linux-arm-kernel
Hi Thomas,
On Wed, May 9, 2012 at 3:34 AM, Thomas Abraham <thomas.abraham@linaro.org>
wrote:
> This patch series adds device tree based discovery support for Samsung's
> s3c64xx compatible spi controller. This is mainly tested for Exynos4210
> and Exynos5250 with onboard spi nor flash device.
>
> This patch series is based on Linux 3.4-rc5 with the following two
> patch series applied.
>
> [1]
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg10494.html
> [PATCH 00/20] ARM: Samsung: Add support for Exynos5250 Rev1.0
>
> [2]
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg09640.html
> [PATCH 0/6] S3C24XX: Add support for HSSPI on S3C2416/S3C2443
>
> Thomas Abraham (10):
> spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
> spi: s3c64xx: move controller information into driver data
> ARM: Samsung: Remove spi hardware controller information from platform
data
> ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions
> ARM: Samsung: Update the device names for spi clock lookup
> ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
> spi: s3c64xx: Remove the 'set_level' callback from controller data
> ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock
> ARM: Exynos5: Add spi clock support
> spi: s3c64xx: add device tree support
>
> .../devicetree/bindings/spi/spi-samsung.txt | 113 +++++
> arch/arm/mach-exynos/clock-exynos4.c | 66 ++-
> arch/arm/mach-exynos/clock-exynos5.c | 98 ++++
> arch/arm/mach-exynos/include/mach/regs-clock.h | 4 +
> arch/arm/mach-exynos/setup-spi.c | 33 +--
> arch/arm/mach-s3c24xx/clock-s3c2416.c | 2 +-
> arch/arm/mach-s3c24xx/clock-s3c2443.c | 2 +-
> arch/arm/mach-s3c24xx/common-s3c2443.c | 4 +-
> arch/arm/mach-s3c24xx/setup-spi.c | 10 +-
> arch/arm/mach-s3c64xx/clock.c | 20 +-
> arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
> arch/arm/mach-s3c64xx/setup-spi.c | 19 +-
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 12 +-
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 12 +-
> arch/arm/mach-s5p64x0/setup-spi.c | 21 +-
> arch/arm/mach-s5pc100/clock.c | 30 +-
> arch/arm/mach-s5pc100/setup-spi.c | 30 +--
> arch/arm/mach-s5pv210/clock.c | 14 +-
> arch/arm/mach-s5pv210/setup-spi.c | 21 +-
> arch/arm/plat-samsung/devs.c | 50 +--
> arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 31 +-
> drivers/spi/spi-s3c64xx.c | 467
+++++++++++++++++---
> 22 files changed, 753 insertions(+), 308 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt
>
>
After applying this patchset, there is a build warning in the boot log.
Below is the warning..
------------[ cut here ]------------
WARNING: at drivers/base/dd.c:257 driver_probe_device+0x1ac/0x218()
Modules linked in:
[<c00159fc>] (unwind_backtrace+0x0/0xfc) from [<c0023e5c>]
(warn_slowpath_common+0x54/0x64)
[<c0023e5c>] (warn_slowpath_common+0x54/0x64) from [<c0023e88>]
(warn_slowpath_null+0x1c/0x24)
[<c0023e88>] (warn_slowpath_null+0x1c/0x24) from [<c02b6670>]
(driver_probe_device+0x1ac/0x218)
[<c02b6670>] (driver_probe_device+0x1ac/0x218) from [<c02b6768>]
(__driver_attach+0x8c/0x90)
[<c02b6768>] (__driver_attach+0x8c/0x90) from [<c02b4ddc>]
(bus_for_each_dev+0x54/0x80)
[<c02b4ddc>] (bus_for_each_dev+0x54/0x80) from [<c02b564c>]
(bus_add_driver+0x1f4/0x2c0)
[<c02b564c>] (bus_add_driver+0x1f4/0x2c0) from [<c02b6d5c>]
(driver_register+0x78/0x180)
[<c02b6d5c>] (driver_register+0x78/0x180) from [<c00085f8>]
(do_one_initcall+0x34/0x180)
[<c00085f8>] (do_one_initcall+0x34/0x180) from [<c069139c>]
(kernel_init+0x114/0x1c0)
[<c069139c>] (kernel_init+0x114/0x1c0) from [<c000ffec>]
(kernel_thread_exit+0x0/0x8)
---[ end trace 6227d56b6a736442 ]---
m25p80 spi1.0: found w25q80, expected w25x80
m25p80 spi1.0: w25q80 (1024 Kbytes)
2 ofpart partitions found on MTD device spi1.0
Creating 2 MTD partitions on "spi1.0":
0x000000000000-0x000000040000 : "U-Boot"
0x000000040000-0x000000100000 : "Kernel"
Thanks&Regards
Padma
> --
> To unsubscribe from this list: send the line "unsubscribe
linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
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^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 02/10] spi: s3c64xx: move controller information into driver data
2012-05-08 22:04 ` Thomas Abraham
@ 2012-05-30 7:23 ` Olof Johansson
-1 siblings, 0 replies; 78+ messages in thread
From: Olof Johansson @ 2012-05-30 7:23 UTC (permalink / raw)
To: Thomas Abraham
Cc: spi-devel-general, devicetree-discuss, linux-arm-kernel,
linux-samsung-soc, rob.herring, grant.likely, kgene.kim,
jaswinder.singh
Hi,
Some comments below.
On Tue, May 8, 2012 at 3:04 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> Platform data is used to specify controller hardware specific information
> such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
> information is not suitable to be supplied from device tree. Instead,
> it can be moved into the driver data and removed from platform data.
>
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> drivers/spi/spi-s3c64xx.c | 180 ++++++++++++++++++++++++++++++++++++++-------
> 1 files changed, 153 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 6a3d51a..f6bc0e3 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data {
> struct s3c64xx_spi_dma_data rx_dma;
> struct s3c64xx_spi_dma_data tx_dma;
> struct samsung_dma_ops *ops;
> + struct s3c64xx_spi_port_config *port_conf;
> + unsigned port_id;
unsigned int
> @@ -942,6 +964,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
> flush_fifo(sdd);
> }
>
> +static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
> + struct platform_device *pdev)
> +{
> + return (struct s3c64xx_spi_port_config *)
> + platform_get_device_id(pdev)->driver_data;
> +}
> +
> static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> {
> struct resource *mem_res, *dmatx_res, *dmarx_res;
> @@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> platform_set_drvdata(pdev, master);
>
> sdd = spi_master_get_devdata(master);
> + sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
> sdd->master = master;
> sdd->cntrlr_info = sci;
> sdd->pdev = pdev;
Single-use helper? Might as well open code it in this case.
> @@ -1227,6 +1258,100 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
> s3c64xx_spi_runtime_resume, NULL)
> };
>
> +#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
> +struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f },
> + .rx_lvl_offset = 13,
> + .tx_st_done = 21,
> + .high_speed = true,
> +};
> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c2443_spi_port_config)
> +#else
> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif
Is it really worth it to do the ifdefs here for just 16 bytes of data
per entry? The table itself below takes more space.
[..]
> +#ifdef CONFIG_ARCH_S5PV210
> +struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
> + .fifo_lvl_mask = { 0x1ff, 0x7F },
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .high_speed = 1,
high_speed = true
> +};
> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pv210_spi_port_config)
> +#else
> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S5PV210 */
> +
> +#ifdef CONFIG_ARCH_EXYNOS4
> +struct s3c64xx_spi_port_config exynos4_spi_port_config = {
> + .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .high_speed = 1,
high_speed = true
-Olof
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 02/10] spi: s3c64xx: move controller information into driver data
@ 2012-05-30 7:23 ` Olof Johansson
0 siblings, 0 replies; 78+ messages in thread
From: Olof Johansson @ 2012-05-30 7:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Some comments below.
On Tue, May 8, 2012 at 3:04 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> Platform data is used to specify controller hardware specific information
> such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
> information is not suitable to be supplied from device tree. Instead,
> it can be moved into the driver data and removed from platform data.
>
> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> ?drivers/spi/spi-s3c64xx.c | ?180 ++++++++++++++++++++++++++++++++++++++-------
> ?1 files changed, 153 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 6a3d51a..f6bc0e3 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data {
> ? ? ? ?struct s3c64xx_spi_dma_data ? ? rx_dma;
> ? ? ? ?struct s3c64xx_spi_dma_data ? ? tx_dma;
> ? ? ? ?struct samsung_dma_ops ? ? ? ? ?*ops;
> + ? ? ? struct s3c64xx_spi_port_config ?*port_conf;
> + ? ? ? unsigned ? ? ? ? ? ? ? ? ? ? ? ?port_id;
unsigned int
> @@ -942,6 +964,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
> ? ? ? ?flush_fifo(sdd);
> ?}
>
> +static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct platform_device *pdev)
> +{
> + ? ? ? return (struct s3c64xx_spi_port_config *)
> + ? ? ? ? ? ? ? ? ? ? ? ?platform_get_device_id(pdev)->driver_data;
> +}
> +
> ?static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> ?{
> ? ? ? ?struct resource *mem_res, *dmatx_res, *dmarx_res;
> @@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
> ? ? ? ?platform_set_drvdata(pdev, master);
>
> ? ? ? ?sdd = spi_master_get_devdata(master);
> + ? ? ? sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
> ? ? ? ?sdd->master = master;
> ? ? ? ?sdd->cntrlr_info = sci;
> ? ? ? ?sdd->pdev = pdev;
Single-use helper? Might as well open code it in this case.
> @@ -1227,6 +1258,100 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
> ? ? ? ? ? ? ? ? ? ? ? ? ? s3c64xx_spi_runtime_resume, NULL)
> ?};
>
> +#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
> +struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
> + ? ? ? .fifo_lvl_mask ?= { 0x7f },
> + ? ? ? .rx_lvl_offset ?= 13,
> + ? ? ? .tx_st_done ? ? = 21,
> + ? ? ? .high_speed ? ? = true,
> +};
> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c2443_spi_port_config)
> +#else
> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif
Is it really worth it to do the ifdefs here for just 16 bytes of data
per entry? The table itself below takes more space.
[..]
> +#ifdef CONFIG_ARCH_S5PV210
> +struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
> + ? ? ? .fifo_lvl_mask ?= { 0x1ff, 0x7F },
> + ? ? ? .rx_lvl_offset ?= 15,
> + ? ? ? .tx_st_done ? ? = 25,
> + ? ? ? .high_speed ? ? = 1,
high_speed = true
> +};
> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pv210_spi_port_config)
> +#else
> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_ARCH_S5PV210 */
> +
> +#ifdef CONFIG_ARCH_EXYNOS4
> +struct s3c64xx_spi_port_config exynos4_spi_port_config = {
> + ? ? ? .fifo_lvl_mask ?= { 0x1ff, 0x7F, 0x7F },
> + ? ? ? .rx_lvl_offset ?= 15,
> + ? ? ? .tx_st_done ? ? = 25,
> + ? ? ? .high_speed ? ? = 1,
high_speed = true
-Olof
^ permalink raw reply [flat|nested] 78+ messages in thread
* Re: [PATCH 02/10] spi: s3c64xx: move controller information into driver data
2012-05-30 7:23 ` Olof Johansson
@ 2012-05-30 8:00 ` Thomas Abraham
-1 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-30 8:00 UTC (permalink / raw)
To: Olof Johansson
Cc: spi-devel-general, devicetree-discuss, linux-arm-kernel,
linux-samsung-soc, rob.herring, grant.likely, kgene.kim,
jaswinder.singh
Hi Olof,
On 30 May 2012 15:23, Olof Johansson <olof@lixom.net> wrote:
> Hi,
>
> Some comments below.
>
> On Tue, May 8, 2012 at 3:04 PM, Thomas Abraham
> <thomas.abraham@linaro.org> wrote:
>> Platform data is used to specify controller hardware specific information
>> such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
>> information is not suitable to be supplied from device tree. Instead,
>> it can be moved into the driver data and removed from platform data.
>>
>> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> drivers/spi/spi-s3c64xx.c | 180 ++++++++++++++++++++++++++++++++++++++-------
>> 1 files changed, 153 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
>> index 6a3d51a..f6bc0e3 100644
>> --- a/drivers/spi/spi-s3c64xx.c
>> +++ b/drivers/spi/spi-s3c64xx.c
>
>> @@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data {
>> struct s3c64xx_spi_dma_data rx_dma;
>> struct s3c64xx_spi_dma_data tx_dma;
>> struct samsung_dma_ops *ops;
>> + struct s3c64xx_spi_port_config *port_conf;
>> + unsigned port_id;
>
> unsigned int
Ok.
>
>
>> @@ -942,6 +964,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
>> flush_fifo(sdd);
>> }
>>
>> +static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
>> + struct platform_device *pdev)
>> +{
>> + return (struct s3c64xx_spi_port_config *)
>> + platform_get_device_id(pdev)->driver_data;
>> +}
>> +
>> static int __init s3c64xx_spi_probe(struct platform_device *pdev)
>> {
>> struct resource *mem_res, *dmatx_res, *dmarx_res;
>> @@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
>> platform_set_drvdata(pdev, master);
>>
>> sdd = spi_master_get_devdata(master);
>> + sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
>> sdd->master = master;
>> sdd->cntrlr_info = sci;
>> sdd->pdev = pdev;
>
> Single-use helper? Might as well open code it in this case.
This helper function 's3c64xx_spi_get_port_config' is populated with
more code later in the 'add spi support' patch. Which simplifies the
code flow here. So I prefer to maintain this as a separate function.
>
>
>> @@ -1227,6 +1258,100 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
>> s3c64xx_spi_runtime_resume, NULL)
>> };
>>
>> +#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
>> +struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
>> + .fifo_lvl_mask = { 0x7f },
>> + .rx_lvl_offset = 13,
>> + .tx_st_done = 21,
>> + .high_speed = true,
>> +};
>> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c2443_spi_port_config)
>> +#else
>> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
>> +#endif
>
> Is it really worth it to do the ifdefs here for just 16 bytes of data
> per entry? The table itself below takes more space.
Ok. The ifdefs do reduce the readability of this code. So I will leave
the ifdefs in this patch.
>
>
> [..]
>
>> +#ifdef CONFIG_ARCH_S5PV210
>> +struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
>> + .fifo_lvl_mask = { 0x1ff, 0x7F },
>> + .rx_lvl_offset = 15,
>> + .tx_st_done = 25,
>> + .high_speed = 1,
>
> high_speed = true
>
>> +};
>> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pv210_spi_port_config)
>> +#else
>> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
>> +#endif /* CONFIG_ARCH_S5PV210 */
>> +
>> +#ifdef CONFIG_ARCH_EXYNOS4
>> +struct s3c64xx_spi_port_config exynos4_spi_port_config = {
>> + .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
>> + .rx_lvl_offset = 15,
>> + .tx_st_done = 25,
>> + .high_speed = 1,
>
> high_speed = true
Ok.
Thanks for your comments.
Regards,
Thomas.
>
>
>
> -Olof
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH 02/10] spi: s3c64xx: move controller information into driver data
@ 2012-05-30 8:00 ` Thomas Abraham
0 siblings, 0 replies; 78+ messages in thread
From: Thomas Abraham @ 2012-05-30 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof,
On 30 May 2012 15:23, Olof Johansson <olof@lixom.net> wrote:
> Hi,
>
> Some comments below.
>
> On Tue, May 8, 2012 at 3:04 PM, Thomas Abraham
> <thomas.abraham@linaro.org> wrote:
>> Platform data is used to specify controller hardware specific information
>> such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
>> information is not suitable to be supplied from device tree. Instead,
>> it can be moved into the driver data and removed from platform data.
>>
>> Cc: Jaswinder Singh <jaswinder.singh@linaro.org>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> ?drivers/spi/spi-s3c64xx.c | ?180 ++++++++++++++++++++++++++++++++++++++-------
>> ?1 files changed, 153 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
>> index 6a3d51a..f6bc0e3 100644
>> --- a/drivers/spi/spi-s3c64xx.c
>> +++ b/drivers/spi/spi-s3c64xx.c
>
>> @@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data {
>> ? ? ? ?struct s3c64xx_spi_dma_data ? ? rx_dma;
>> ? ? ? ?struct s3c64xx_spi_dma_data ? ? tx_dma;
>> ? ? ? ?struct samsung_dma_ops ? ? ? ? ?*ops;
>> + ? ? ? struct s3c64xx_spi_port_config ?*port_conf;
>> + ? ? ? unsigned ? ? ? ? ? ? ? ? ? ? ? ?port_id;
>
> unsigned int
Ok.
>
>
>> @@ -942,6 +964,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
>> ? ? ? ?flush_fifo(sdd);
>> ?}
>>
>> +static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct platform_device *pdev)
>> +{
>> + ? ? ? return (struct s3c64xx_spi_port_config *)
>> + ? ? ? ? ? ? ? ? ? ? ? ?platform_get_device_id(pdev)->driver_data;
>> +}
>> +
>> ?static int __init s3c64xx_spi_probe(struct platform_device *pdev)
>> ?{
>> ? ? ? ?struct resource *mem_res, *dmatx_res, *dmarx_res;
>> @@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
>> ? ? ? ?platform_set_drvdata(pdev, master);
>>
>> ? ? ? ?sdd = spi_master_get_devdata(master);
>> + ? ? ? sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
>> ? ? ? ?sdd->master = master;
>> ? ? ? ?sdd->cntrlr_info = sci;
>> ? ? ? ?sdd->pdev = pdev;
>
> Single-use helper? Might as well open code it in this case.
This helper function 's3c64xx_spi_get_port_config' is populated with
more code later in the 'add spi support' patch. Which simplifies the
code flow here. So I prefer to maintain this as a separate function.
>
>
>> @@ -1227,6 +1258,100 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
>> ? ? ? ? ? ? ? ? ? ? ? ? ? s3c64xx_spi_runtime_resume, NULL)
>> ?};
>>
>> +#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
>> +struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
>> + ? ? ? .fifo_lvl_mask ?= { 0x7f },
>> + ? ? ? .rx_lvl_offset ?= 13,
>> + ? ? ? .tx_st_done ? ? = 21,
>> + ? ? ? .high_speed ? ? = true,
>> +};
>> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c2443_spi_port_config)
>> +#else
>> +#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
>> +#endif
>
> Is it really worth it to do the ifdefs here for just 16 bytes of data
> per entry? The table itself below takes more space.
Ok. The ifdefs do reduce the readability of this code. So I will leave
the ifdefs in this patch.
>
>
> [..]
>
>> +#ifdef CONFIG_ARCH_S5PV210
>> +struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
>> + ? ? ? .fifo_lvl_mask ?= { 0x1ff, 0x7F },
>> + ? ? ? .rx_lvl_offset ?= 15,
>> + ? ? ? .tx_st_done ? ? = 25,
>> + ? ? ? .high_speed ? ? = 1,
>
> high_speed = true
>
>> +};
>> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pv210_spi_port_config)
>> +#else
>> +#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
>> +#endif /* CONFIG_ARCH_S5PV210 */
>> +
>> +#ifdef CONFIG_ARCH_EXYNOS4
>> +struct s3c64xx_spi_port_config exynos4_spi_port_config = {
>> + ? ? ? .fifo_lvl_mask ?= { 0x1ff, 0x7F, 0x7F },
>> + ? ? ? .rx_lvl_offset ?= 15,
>> + ? ? ? .tx_st_done ? ? = 25,
>> + ? ? ? .high_speed ? ? = 1,
>
> high_speed = true
Ok.
Thanks for your comments.
Regards,
Thomas.
>
>
>
> -Olof
^ permalink raw reply [flat|nested] 78+ messages in thread
end of thread, other threads:[~2012-05-30 8:00 UTC | newest]
Thread overview: 78+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-05-08 22:04 [PATCH 00/10] spi: s3c64xx: add support for device tree Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-08 22:04 ` [PATCH 01/10] spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-20 4:41 ` Grant Likely
2012-05-20 4:41 ` Grant Likely
2012-05-08 22:04 ` [PATCH 02/10] spi: s3c64xx: move controller information into driver data Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-20 4:42 ` Grant Likely
2012-05-20 4:42 ` Grant Likely
2012-05-30 7:23 ` Olof Johansson
2012-05-30 7:23 ` Olof Johansson
2012-05-30 8:00 ` Thomas Abraham
2012-05-30 8:00 ` Thomas Abraham
2012-05-08 22:04 ` [PATCH 03/10] ARM: Samsung: Remove spi hardware controller information from platform data Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-08 22:04 ` [PATCH 04/10] ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-08 22:04 ` [PATCH 05/10] ARM: Samsung: Update the device names for spi clock lookup Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-09 8:52 ` Mark Brown
2012-05-09 8:52 ` Mark Brown
2012-05-09 13:40 ` Thomas Abraham
2012-05-09 13:40 ` Thomas Abraham
2012-05-09 14:28 ` Mark Brown
2012-05-09 14:28 ` Mark Brown
[not found] ` <20120509142836.GT3955-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org>
2012-05-09 17:17 ` Thomas Abraham
2012-05-09 17:17 ` Thomas Abraham
2012-05-13 14:51 ` Mark Brown
2012-05-13 14:51 ` Mark Brown
2012-05-20 4:43 ` Grant Likely
2012-05-20 4:43 ` Grant Likely
2012-05-08 22:04 ` [PATCH 06/10] ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-09 8:56 ` Mark Brown
2012-05-09 8:56 ` Mark Brown
[not found] ` <20120509085617.GB28702-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2012-05-09 9:10 ` Heiko Stübner
2012-05-09 9:10 ` Heiko Stübner
2012-05-09 10:55 ` Mark Brown
2012-05-09 10:55 ` Mark Brown
2012-05-09 14:22 ` Thomas Abraham
2012-05-09 14:22 ` Thomas Abraham
2012-05-09 14:33 ` Mark Brown
2012-05-09 14:33 ` Mark Brown
2012-05-09 15:06 ` Thomas Abraham
2012-05-09 15:06 ` Thomas Abraham
2012-05-08 22:04 ` [PATCH 07/10] spi: s3c64xx: Remove the 'set_level' callback from controller data Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-09 8:03 ` Jassi Brar
2012-05-09 8:03 ` Jassi Brar
2012-05-09 9:20 ` Heiko Stübner
2012-05-09 9:20 ` Heiko Stübner
2012-05-09 10:31 ` Jassi Brar
2012-05-09 10:31 ` Jassi Brar
2012-05-20 4:45 ` Grant Likely
2012-05-20 4:45 ` Grant Likely
2012-05-08 22:04 ` [PATCH 08/10] ARM: Exynos4: Fix the incorrect hierarchy of spi controller bus clock Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-08 22:04 ` [PATCH 09/10] ARM: Exynos5: Add spi clock support Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
2012-05-08 22:04 ` [PATCH 10/10] spi: s3c64xx: add device tree support Thomas Abraham
2012-05-08 22:04 ` Thomas Abraham
[not found] ` <1336514694-22393-11-git-send-email-thomas.abraham-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2012-05-09 9:07 ` Mark Brown
2012-05-09 9:07 ` Mark Brown
2012-05-09 14:13 ` Thomas Abraham
2012-05-09 14:13 ` Thomas Abraham
2012-05-09 14:32 ` Mark Brown
2012-05-09 14:32 ` Mark Brown
2012-05-09 16:39 ` Thomas Abraham
2012-05-09 16:39 ` Thomas Abraham
2012-05-09 16:47 ` Mark Brown
2012-05-09 16:47 ` Mark Brown
2012-05-09 17:19 ` Thomas Abraham
2012-05-09 17:19 ` Thomas Abraham
2012-05-09 8:17 ` [PATCH 00/10] spi: s3c64xx: add support for device tree Jassi Brar
2012-05-09 8:17 ` Jassi Brar
[not found] ` <1336514694-22393-1-git-send-email-thomas.abraham-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2012-05-22 12:35 ` padma venkat
2012-05-22 12:35 ` padma venkat
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