* [PATCH 00/16] Enable SPARSE_IRQ support for imx
@ 2012-06-14 5:59 ` Shawn Guo
0 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
It seems that the lack of SPARSE_IRQ support becomes the last blocker
for imx being built with multi-platform. The series is to enable
SPARSE_IRQ for imx by having all the irqchips allocate their irq_descs.
Along with the change, a legacy irqdomain is added for each of these
irqchips (except ipu_irq) to help the mapping between hardware irq and
Linux irq number, which is required by DT boot but also benefits non-DT.
Based on v3.5-rc2. Boot tested on imx3, imx5 and imx6, and compile
tested with imx_v4_v5_defconfig.
Shawn Guo (16):
ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
ARM: imx: eliminate macro IOMUX_TO_IRQ()
ARM: imx: eliminate macro IRQ_GPIOx()
gpio/mxc: move irq_domain_add_legacy call into gpio driver
ARM: imx: move irq_domain_add_legacy call into tzic driver
ARM: imx: move irq_domain_add_legacy call into avic driver
dma: ipu: remove the use of ipu_platform_data
ARM: imx: leave irq_base of wm8350_platform_data uninitialized
ARM: imx: pass gpio than irq number into mxc_expio_init
ARM: imx: add a legacy irqdomain for 3ds_debugboard
ARM: imx: add a legacy irqdomain for mx31ads
i2c: imx: remove unneeded mach/irqs.h inclusion
ARM: imx: remove unneeded mach/irq.h inclusion
tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
ARM: fiq: save FIQ_START by passing absolute fiq number
ARM: imx: enable SPARSE_IRQ for imx platform
arch/arm/Kconfig | 1 +
arch/arm/kernel/fiq.c | 4 +-
arch/arm/mach-imx/devices-imx31.h | 4 +-
arch/arm/mach-imx/devices-imx35.h | 4 +-
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 3 +-
arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c | 6 +-
arch/arm/mach-imx/imx27-dt.c | 28 ---
arch/arm/mach-imx/imx51-dt.c | 27 ---
arch/arm/mach-imx/imx53-dt.c | 27 ---
arch/arm/mach-imx/mach-apf9328.c | 7 +-
arch/arm/mach-imx/mach-armadillo5x0.c | 18 +-
arch/arm/mach-imx/mach-cpuimx27.c | 12 +-
arch/arm/mach-imx/mach-cpuimx35.c | 3 +-
arch/arm/mach-imx/mach-cpuimx51sd.c | 3 +-
arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 9 +-
arch/arm/mach-imx/mach-imx6q.c | 14 --
arch/arm/mach-imx/mach-kzm_arm11_01.c | 20 ++-
arch/arm/mach-imx/mach-mx1ads.c | 1 -
arch/arm/mach-imx/mach-mx21ads.c | 16 ++-
arch/arm/mach-imx/mach-mx27_3ds.c | 7 +-
arch/arm/mach-imx/mach-mx27ads.c | 12 +-
arch/arm/mach-imx/mach-mx31_3ds.c | 18 +--
arch/arm/mach-imx/mach-mx31ads.c | 63 ++++---
arch/arm/mach-imx/mach-mx31lilly.c | 10 +-
arch/arm/mach-imx/mach-mx31lite.c | 11 +-
arch/arm/mach-imx/mach-mx31moboard.c | 10 +-
arch/arm/mach-imx/mach-mx35_3ds.c | 18 +--
arch/arm/mach-imx/mach-mx51_3ds.c | 3 +-
arch/arm/mach-imx/mach-mx53_ard.c | 5 +-
arch/arm/mach-imx/mach-mxt_td60.c | 6 +-
arch/arm/mach-imx/mach-pca100.c | 5 +-
arch/arm/mach-imx/mach-pcm037.c | 24 ++--
arch/arm/mach-imx/mach-pcm038.c | 4 +-
arch/arm/mach-imx/mach-pcm043.c | 6 +-
arch/arm/mach-imx/mach-qong.c | 10 +-
arch/arm/mach-imx/mach-scb9328.c | 7 +-
arch/arm/mach-imx/mach-vpr200.c | 10 +-
arch/arm/mach-imx/mm-imx1.c | 1 -
arch/arm/mach-imx/mm-imx21.c | 1 -
arch/arm/mach-imx/mm-imx25.c | 1 -
arch/arm/mach-imx/mm-imx27.c | 1 -
arch/arm/mach-imx/mm-imx3.c | 1 -
arch/arm/mach-imx/mx31lilly-db.c | 11 +-
arch/arm/mach-imx/mx31lite-db.c | 5 +-
arch/arm/mach-imx/mx51_efika.c | 3 +-
arch/arm/mach-imx/pcm970-baseboard.c | 13 +-
arch/arm/mach-rpc/include/mach/irqs.h | 12 +-
arch/arm/plat-mxc/3ds_debugboard.c | 50 +++---
arch/arm/plat-mxc/avic.c | 26 ++-
arch/arm/plat-mxc/devices/platform-ipu-core.c | 5 +-
arch/arm/plat-mxc/include/mach/3ds_debugboard.h | 2 +-
arch/arm/plat-mxc/include/mach/devices-common.h | 4 +-
arch/arm/plat-mxc/include/mach/hardware.h | 2 -
arch/arm/plat-mxc/include/mach/iomux-mx3.h | 3 -
arch/arm/plat-mxc/include/mach/iomux-v1.h | 7 -
arch/arm/plat-mxc/include/mach/ipu.h | 4 -
arch/arm/plat-mxc/include/mach/irqs.h | 44 -----
arch/arm/plat-mxc/include/mach/mx1.h | 111 ++++++------
arch/arm/plat-mxc/include/mach/mx21.h | 107 ++++++------
arch/arm/plat-mxc/include/mach/mx25.h | 72 ++++----
arch/arm/plat-mxc/include/mach/mx27.h | 127 +++++++-------
arch/arm/plat-mxc/include/mach/mx2x.h | 87 +++++-----
arch/arm/plat-mxc/include/mach/mx31.h | 118 +++++++------
arch/arm/plat-mxc/include/mach/mx35.h | 109 ++++++------
arch/arm/plat-mxc/include/mach/mx3x.h | 77 ++++----
arch/arm/plat-mxc/include/mach/mx50.h | 187 ++++++++++----------
arch/arm/plat-mxc/include/mach/mx51.h | 209 +++++++++++-----------
arch/arm/plat-mxc/include/mach/mx53.h | 217 ++++++++++++-----------
arch/arm/plat-mxc/tzic.c | 28 ++-
drivers/dma/ipu/ipu_idmac.c | 8 +-
drivers/dma/ipu/ipu_irq.c | 14 +-
drivers/gpio/gpio-mxc.c | 56 ++++---
drivers/i2c/busses/i2c-imx.c | 1 -
drivers/media/video/mx1_camera.c | 1 +
drivers/tty/serial/imx.c | 6 +-
sound/soc/fsl/imx-pcm-fiq.c | 1 +
76 files changed, 1041 insertions(+), 1127 deletions(-)
--
1.7.5.4
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 01/16] ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
2012-06-14 5:59 ` Shawn Guo
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-14 7:31 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
This patch changes all the static gpio irq number assigning with
IMX_GPIO_TO_IRQ() to run-time assigning with gpio_to_irq call, and
in turn eliminates the macro IMX_GPIO_TO_IRQ().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/mach-cpuimx35.c | 3 ++-
arch/arm/mach-imx/mach-cpuimx51sd.c | 3 ++-
arch/arm/mach-imx/mach-mx27_3ds.c | 3 ++-
arch/arm/mach-imx/mach-mx35_3ds.c | 3 ++-
arch/arm/mach-imx/mach-mx53_ard.c | 5 +++--
arch/arm/mach-imx/mach-vpr200.c | 3 ++-
arch/arm/mach-imx/mx51_efika.c | 3 ++-
arch/arm/plat-mxc/include/mach/hardware.h | 2 --
8 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index c515f8e..73c4b65 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -72,7 +72,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
I2C_BOARD_INFO("tsc2007", 0x48),
.type = "tsc2007",
.platform_data = &tsc2007_info,
- .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
+ /* irq number is run-time assigned */
},
};
@@ -173,6 +173,7 @@ static void __init eukrea_cpuimx35_init(void)
imx35_add_imx_uart0(&uart_pdata);
imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
+ eukrea_cpuimx35_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO);
i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index ac50f16..e42c6f8 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -259,7 +259,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
.mode = SPI_MODE_0,
.chip_select = 0,
.platform_data = &mcp251x_info,
- .irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
+ /* irq number is run-time assigned */
},
};
@@ -310,6 +310,7 @@ static void __init eukrea_cpuimx51sd_init(void)
msleep(20);
gpio_set_value(CAN_RST, 1);
imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
+ cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
spi_register_board_info(cpuimx51sd_spi_device,
ARRAY_SIZE(cpuimx51sd_spi_device));
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index c6d385c..18b9bca 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -445,7 +445,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
.bus_num = 1,
.chip_select = 0, /* SS0 */
.platform_data = &mc13783_pdata,
- .irq = IMX_GPIO_TO_IRQ(PMIC_INT),
+ /* irq number is run-time assigned */
.mode = SPI_CS_HIGH,
}, {
.modalias = "l4f00242t03",
@@ -496,6 +496,7 @@ static void __init mx27pdk_init(void)
imx27_add_spi_imx1(&spi2_pdata);
imx27_add_spi_imx0(&spi1_pdata);
+ mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 28aa194..fa1ea74 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -492,7 +492,7 @@ static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
I2C_BOARD_INFO("mc13892", 0x08),
.platform_data = &mx35_3ds_mc13892_data,
- .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+ /* irq number is run-time assigned */
};
static void __init imx35_3ds_init_mc13892(void)
@@ -504,6 +504,7 @@ static void __init imx35_3ds_init_mc13892(void)
return;
}
+ mx35_3ds_i2c_mc13892.irq = gpio_to_irq(GPIO_PMIC_INT);
i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
}
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
index 0564198..fe3f396 100644
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ b/arch/arm/mach-imx/mach-mx53_ard.c
@@ -135,8 +135,7 @@ static struct resource ard_smsc911x_resources[] = {
.flags = IORESOURCE_MEM,
},
{
- .start = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
- .end = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ,
},
};
@@ -240,6 +239,8 @@ static void __init mx53_ard_board_init(void)
imx53_ard_common_init();
mx53_ard_io_init();
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
+ ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index add8c69..e36eb2c 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -162,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
}, {
I2C_BOARD_INFO("mc13892", 0x08),
.platform_data = &vpr200_pmic,
- .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+ /* irq number is run-time assigned */
}
};
@@ -299,6 +299,7 @@ static void __init vpr200_board_init(void)
imx35_add_mxc_nand(&vpr200_nand_board_info);
imx35_add_sdhci_esdhc_imx(0, NULL);
+ vpr200_i2c_devices[1].irq = gpio_to_irq(GPIO_PMIC_INT);
i2c_register_board_info(0, vpr200_i2c_devices,
ARRAY_SIZE(vpr200_i2c_devices));
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
index ec6ca91..ee870c4 100644
--- a/arch/arm/mach-imx/mx51_efika.c
+++ b/arch/arm/mach-imx/mx51_efika.c
@@ -587,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
.bus_num = 0,
.chip_select = 0,
.platform_data = &mx51_efika_mc13892_data,
- .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
+ /* irq number is run-time assigned */
},
};
@@ -620,6 +620,7 @@ void __init efika_board_common_init(void)
gpio_request(EFIKAMX_PMIC, "pmic irq");
gpio_direction_input(EFIKAMX_PMIC);
+ mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
spi_register_board_info(mx51_efika_spi_board_info,
ARRAY_SIZE(mx51_efika_spi_board_info));
imx51_add_ecspi(0, &mx51_efika_spi_pdata);
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 0630513..1d432a7 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -128,6 +128,4 @@
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
-#define IMX_GPIO_TO_IRQ(gpio) (MXC_GPIO_IRQ_START + (gpio))
-
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 01/16] ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
2012-06-14 5:59 ` [PATCH 01/16] ARM: imx: eliminate macro IMX_GPIO_TO_IRQ() Shawn Guo
@ 2012-06-14 7:31 ` Dong Aisheng
2012-06-14 7:39 ` Shawn Guo
0 siblings, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-14 7:31 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:32PM +0800, Shawn Guo wrote:
> This patch changes all the static gpio irq number assigning with
> IMX_GPIO_TO_IRQ() to run-time assigning with gpio_to_irq call, and
> in turn eliminates the macro IMX_GPIO_TO_IRQ().
>
Good clean up.
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> arch/arm/mach-imx/mach-cpuimx35.c | 3 ++-
> arch/arm/mach-imx/mach-cpuimx51sd.c | 3 ++-
> arch/arm/mach-imx/mach-mx27_3ds.c | 3 ++-
> arch/arm/mach-imx/mach-mx35_3ds.c | 3 ++-
> arch/arm/mach-imx/mach-mx53_ard.c | 5 +++--
> arch/arm/mach-imx/mach-vpr200.c | 3 ++-
> arch/arm/mach-imx/mx51_efika.c | 3 ++-
> arch/arm/plat-mxc/include/mach/hardware.h | 2 --
> 8 files changed, 15 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
> index c515f8e..73c4b65 100644
> --- a/arch/arm/mach-imx/mach-cpuimx35.c
> +++ b/arch/arm/mach-imx/mach-cpuimx35.c
> @@ -72,7 +72,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
> I2C_BOARD_INFO("tsc2007", 0x48),
> .type = "tsc2007",
> .platform_data = &tsc2007_info,
> - .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
> + /* irq number is run-time assigned */
Maybe this line is not need.
Otherwise,
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
> },
> };
>
> @@ -173,6 +173,7 @@ static void __init eukrea_cpuimx35_init(void)
> imx35_add_imx_uart0(&uart_pdata);
> imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
>
> + eukrea_cpuimx35_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO);
> i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
> ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
> imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
> diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
> index ac50f16..e42c6f8 100644
> --- a/arch/arm/mach-imx/mach-cpuimx51sd.c
> +++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
> @@ -259,7 +259,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
> .mode = SPI_MODE_0,
> .chip_select = 0,
> .platform_data = &mcp251x_info,
> - .irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
> + /* irq number is run-time assigned */
> },
> };
>
> @@ -310,6 +310,7 @@ static void __init eukrea_cpuimx51sd_init(void)
> msleep(20);
> gpio_set_value(CAN_RST, 1);
> imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
> + cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
> spi_register_board_info(cpuimx51sd_spi_device,
> ARRAY_SIZE(cpuimx51sd_spi_device));
>
> diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
> index c6d385c..18b9bca 100644
> --- a/arch/arm/mach-imx/mach-mx27_3ds.c
> +++ b/arch/arm/mach-imx/mach-mx27_3ds.c
> @@ -445,7 +445,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
> .bus_num = 1,
> .chip_select = 0, /* SS0 */
> .platform_data = &mc13783_pdata,
> - .irq = IMX_GPIO_TO_IRQ(PMIC_INT),
> + /* irq number is run-time assigned */
> .mode = SPI_CS_HIGH,
> }, {
> .modalias = "l4f00242t03",
> @@ -496,6 +496,7 @@ static void __init mx27pdk_init(void)
>
> imx27_add_spi_imx1(&spi2_pdata);
> imx27_add_spi_imx0(&spi1_pdata);
> + mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
> spi_register_board_info(mx27_3ds_spi_devs,
> ARRAY_SIZE(mx27_3ds_spi_devs));
>
> diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
> index 28aa194..fa1ea74 100644
> --- a/arch/arm/mach-imx/mach-mx35_3ds.c
> +++ b/arch/arm/mach-imx/mach-mx35_3ds.c
> @@ -492,7 +492,7 @@ static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
>
> I2C_BOARD_INFO("mc13892", 0x08),
> .platform_data = &mx35_3ds_mc13892_data,
> - .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
> + /* irq number is run-time assigned */
> };
>
> static void __init imx35_3ds_init_mc13892(void)
> @@ -504,6 +504,7 @@ static void __init imx35_3ds_init_mc13892(void)
> return;
> }
>
> + mx35_3ds_i2c_mc13892.irq = gpio_to_irq(GPIO_PMIC_INT);
> i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
> }
>
> diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
> index 0564198..fe3f396 100644
> --- a/arch/arm/mach-imx/mach-mx53_ard.c
> +++ b/arch/arm/mach-imx/mach-mx53_ard.c
> @@ -135,8 +135,7 @@ static struct resource ard_smsc911x_resources[] = {
> .flags = IORESOURCE_MEM,
> },
> {
> - .start = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
> - .end = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
> + /* irq number is run-time assigned */
> .flags = IORESOURCE_IRQ,
> },
> };
> @@ -240,6 +239,8 @@ static void __init mx53_ard_board_init(void)
> imx53_ard_common_init();
> mx53_ard_io_init();
> regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
> + ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
> + ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
> platform_add_devices(devices, ARRAY_SIZE(devices));
>
> imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
> diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
> index add8c69..e36eb2c 100644
> --- a/arch/arm/mach-imx/mach-vpr200.c
> +++ b/arch/arm/mach-imx/mach-vpr200.c
> @@ -162,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
> }, {
> I2C_BOARD_INFO("mc13892", 0x08),
> .platform_data = &vpr200_pmic,
> - .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
> + /* irq number is run-time assigned */
> }
> };
>
> @@ -299,6 +299,7 @@ static void __init vpr200_board_init(void)
> imx35_add_mxc_nand(&vpr200_nand_board_info);
> imx35_add_sdhci_esdhc_imx(0, NULL);
>
> + vpr200_i2c_devices[1].irq = gpio_to_irq(GPIO_PMIC_INT);
> i2c_register_board_info(0, vpr200_i2c_devices,
> ARRAY_SIZE(vpr200_i2c_devices));
>
> diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
> index ec6ca91..ee870c4 100644
> --- a/arch/arm/mach-imx/mx51_efika.c
> +++ b/arch/arm/mach-imx/mx51_efika.c
> @@ -587,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
> .bus_num = 0,
> .chip_select = 0,
> .platform_data = &mx51_efika_mc13892_data,
> - .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
> + /* irq number is run-time assigned */
> },
> };
>
> @@ -620,6 +620,7 @@ void __init efika_board_common_init(void)
>
> gpio_request(EFIKAMX_PMIC, "pmic irq");
> gpio_direction_input(EFIKAMX_PMIC);
> + mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
> spi_register_board_info(mx51_efika_spi_board_info,
> ARRAY_SIZE(mx51_efika_spi_board_info));
> imx51_add_ecspi(0, &mx51_efika_spi_pdata);
> diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
> index 0630513..1d432a7 100644
> --- a/arch/arm/plat-mxc/include/mach/hardware.h
> +++ b/arch/arm/plat-mxc/include/mach/hardware.h
> @@ -128,6 +128,4 @@
> /* range e.g. GPIO_1_5 is gpio 5 under linux */
> #define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
>
> -#define IMX_GPIO_TO_IRQ(gpio) (MXC_GPIO_IRQ_START + (gpio))
> -
> #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
> --
> 1.7.5.4
>
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 01/16] ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
2012-06-14 7:31 ` Dong Aisheng
@ 2012-06-14 7:39 ` Shawn Guo
2012-06-14 8:04 ` Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 7:39 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 03:31:46PM +0800, Dong Aisheng wrote:
> > - .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
> > + /* irq number is run-time assigned */
> Maybe this line is not need.
>
Documentation never harms.
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 01/16] ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
2012-06-14 7:39 ` Shawn Guo
@ 2012-06-14 8:04 ` Dong Aisheng
0 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-14 8:04 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 03:39:58PM +0800, Shawn Guo wrote:
> On Thu, Jun 14, 2012 at 03:31:46PM +0800, Dong Aisheng wrote:
> > > - .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
> > > + /* irq number is run-time assigned */
> > Maybe this line is not need.
> >
> Documentation never harms.
>
Hmm, you may see in the patch, this comment is added in every places
where need change even in the same file, so totally we added a lot
duplicated lines.
IMHO for this common sense bits, we may not have to document it.
User can refer to common document or code.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 02/16] ARM: imx: eliminate macro IOMUX_TO_IRQ()
2012-06-14 5:59 ` Shawn Guo
(?)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-14 7:59 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
This patch changes all the static gpio irq number assigning with
IOMUX_TO_IRQ() to run-time assigning with gpio_to_irq call, and
in turn eliminates the macro IOMUX_TO_IRQ().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/mach-armadillo5x0.c | 12 ++++++++----
arch/arm/mach-imx/mach-kzm_arm11_01.c | 20 +++++++++++++++-----
arch/arm/mach-imx/mach-mx31_3ds.c | 13 ++++++-------
arch/arm/mach-imx/mach-mx31ads.c | 14 +++++++++-----
arch/arm/mach-imx/mach-mx31lilly.c | 10 +++++++---
arch/arm/mach-imx/mach-mx31lite.c | 10 +++++++---
arch/arm/mach-imx/mach-mx31moboard.c | 4 +++-
arch/arm/mach-imx/mach-pcm037.c | 18 ++++++++++++------
arch/arm/mach-imx/mach-qong.c | 9 +++++----
arch/arm/mach-imx/mx31lilly-db.c | 5 +++--
arch/arm/mach-imx/mx31lite-db.c | 5 +++--
arch/arm/plat-mxc/include/mach/iomux-mx3.h | 3 ---
12 files changed, 78 insertions(+), 45 deletions(-)
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index c650145..f83c5c6 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -408,7 +408,8 @@ static int armadillo5x0_sdhc1_init(struct device *dev,
gpio_direction_input(gpio_wp);
/* When supported the trigger type have to be BOTH */
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq,
+ ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)),
+ detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"sdhc-detect", data);
@@ -429,7 +430,7 @@ err_gpio_free:
static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
{
- free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data);
+ free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), data);
gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
}
@@ -450,8 +451,7 @@ static struct resource armadillo5x0_smc911x_resources[] = {
.end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
@@ -498,6 +498,10 @@ static void __init armadillo5x0_init(void)
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ armadillo5x0_smc911x_resources[1].start =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
+ armadillo5x0_smc911x_resources[1].end =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
platform_add_devices(devices, ARRAY_SIZE(devices));
imx_add_gpio_keys(&armadillo5x0_button_data);
imx31_add_imx_i2c1(NULL);
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 15a26e9..5d08533 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -73,7 +73,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
.mapbase = KZM_ARM11_16550,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+ /* irq number is run-time assigned */
.irqflags = IRQ_TYPE_EDGE_RISING,
.uartclk = 14745600,
.regshift = 0,
@@ -91,8 +91,7 @@ static struct resource serial8250_resources[] = {
.flags = IORESOURCE_MEM,
},
{
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ,
},
};
@@ -125,6 +124,13 @@ static int __init kzm_init_ext_uart(void)
tmp |= 0x2;
__raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
+ serial_platform_data[0].irq =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+ serial8250_resources[1].start =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+ serial8250_resources[1].end =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+
return platform_device_register(&serial_device);
}
#else
@@ -152,8 +158,7 @@ static struct resource kzm_smsc9118_resources[] = {
.flags = IORESOURCE_MEM,
},
{
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};
@@ -184,6 +189,11 @@ static int __init kzm_init_smsc9118(void)
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ kzm_smsc9118_resources[1].start =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
+ kzm_smsc9118_resources[1].end =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
+
return platform_device_register(&kzm_smsc9118_device);
}
#else
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 4eafdf2..ecdba04 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -44,9 +44,6 @@
#include "devices-imx31.h"
-/* CPLD IRQ line for external uart, external ethernet etc */
-#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-
static int mx31_3ds_pins[] = {
/* UART1 */
MX31_PIN_CTS1__CTS1,
@@ -317,7 +314,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
return ret;
}
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+ ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
detect_irq, IRQF_DISABLED |
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
"sdhc1-detect", data);
@@ -336,7 +333,7 @@ gpio_free:
static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
{
- free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
+ free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
gpio_free_array(mx31_3ds_sdhc1_gpios,
ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
}
@@ -539,7 +536,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
.bus_num = 1,
.chip_select = 1, /* SS2 */
.platform_data = &mc13783_pdata,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+ /* irq number is run-time assigned */
.mode = SPI_CS_HIGH,
}, {
.modalias = "l4f00242t03",
@@ -714,6 +711,7 @@ static void __init mx31_3ds_init(void)
imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
imx31_add_spi_imx1(&spi1_pdata);
+ mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(mx31_3ds_spi_devs,
ARRAY_SIZE(mx31_3ds_spi_devs));
@@ -736,7 +734,8 @@ static void __init mx31_3ds_init(void)
if (!otg_mode_host)
imx31_add_fsl_usb2_udc(&usbotg_pdata);
- if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+ if (mxc_expio_init(MX31_CS5_BASE_ADDR,
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1))))
printk(KERN_WARNING "Init of the debug board failed, all "
"devices on the debug board are unusable.\n");
imx31_add_imx2_wdt(NULL);
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 4518e54..6f19f98 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -62,7 +62,6 @@
#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
#define MXC_EXP_IO_BASE MXC_BOARD_IRQ_START
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
@@ -209,7 +208,7 @@ static struct irq_chip expio_irq_chip = {
static void __init mx31ads_init_expio(void)
{
- int i;
+ int i, irq;
printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
@@ -226,8 +225,9 @@ static void __init mx31ads_init_expio(void)
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
- irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
- irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
+ irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
+ irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+ irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
}
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -488,13 +488,17 @@ static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
{
I2C_BOARD_INFO("wm8350", 0x1a),
.platform_data = &mx31_wm8350_pdata,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+ /* irq number is run-time assigned */
},
#endif
};
static void __init mxc_init_i2c(void)
{
+#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+ mx31ads_i2c1_devices[0].irq =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
+#endif
i2c_register_board_info(1, mx31ads_i2c1_devices,
ARRAY_SIZE(mx31ads_i2c1_devices));
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 83714b0..34b9bf0 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -65,8 +65,7 @@ static struct resource smsc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
{
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
}
};
@@ -233,7 +232,7 @@ static struct spi_board_info mc13783_dev __initdata = {
.bus_num = 1,
.chip_select = 0,
.platform_data = &mc13783_pdata,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+ /* irq number is run-time assigned */
};
static struct platform_device *devices[] __initdata = {
@@ -285,10 +284,15 @@ static void __init mx31lilly_board_init(void)
imx31_add_spi_imx0(&spi0_pdata);
imx31_add_spi_imx1(&spi1_pdata);
+ mc13783_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(&mc13783_dev, 1);
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ smsc91x_resources[1].start =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
+ smsc91x_resources[1].end =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
platform_add_devices(devices, ARRAY_SIZE(devices));
/* USB */
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 686c605..4977378 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -83,8 +83,7 @@ static struct resource smsc911x_resources[] = {
.end = MX31_CS4_BASE_ADDR + 0x100,
.flags = IORESOURCE_MEM,
}, {
- .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
- .end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ,
},
};
@@ -124,7 +123,7 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
.bus_num = 1,
.chip_select = 0,
.platform_data = &mc13783_pdata,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+ /* irq number is run-time assigned */
};
/*
@@ -258,6 +257,7 @@ static void __init mx31lite_init(void)
imx31_add_mxc_nand(&mx31lite_nand_board_info);
imx31_add_spi_imx1(&spi1_pdata);
+ mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(&mc13783_spi_dev, 1);
/* USB */
@@ -274,6 +274,10 @@ static void __init mx31lite_init(void)
pr_warning("could not get LAN irq gpio\n");
else {
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
+ smsc911x_resources[1].start =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
+ smsc911x_resources[1].end =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
platform_device_register(&smsc911x_device);
}
}
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 016791f..f0d26db 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -303,7 +303,7 @@ static struct imx_ssi_platform_data moboard_ssi_pdata = {
static struct spi_board_info moboard_spi_board_info[] __initdata = {
{
.modalias = "mc13783",
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+ /* irq number is run-time assigned */
.max_speed_hz = 300000,
.bus_num = 1,
.chip_select = 0,
@@ -557,6 +557,8 @@ static void __init mx31moboard_init(void)
gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
+ moboard_spi_board_info[0].irq =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(moboard_spi_board_info,
ARRAY_SIZE(moboard_spi_board_info));
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 0a40004..551a035 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -225,8 +225,7 @@ static struct resource smsc911x_resources[] = {
.end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
@@ -371,7 +370,7 @@ static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
gpio_direction_input(SDHC1_GPIO_WP);
#endif
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
+ ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"sdhc-detect", data);
if (ret)
@@ -391,7 +390,7 @@ err_gpio_free:
static void pcm970_sdhc1_exit(struct device *dev, void *data)
{
- free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
+ free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
gpio_free(SDHC1_GPIO_DET);
gpio_free(SDHC1_GPIO_WP);
}
@@ -511,8 +510,7 @@ static struct resource pcm970_sja1000_resources[] = {
.end = MX31_CS5_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
- .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
@@ -633,6 +631,10 @@ static void __init pcm037_init(void)
pr_warning("could not get LAN irq gpio\n");
else {
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
+ smsc911x_resources[1].start =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
+ smsc911x_resources[1].end =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
platform_device_register(&pcm037_eth);
}
@@ -659,6 +661,10 @@ static void __init pcm037_init(void)
pcm037_init_camera();
+ pcm970_sja1000_resources[1].start =
+ gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
+ pcm970_sja1000_resources[1].end =
+ gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
platform_device_register(&pcm970_sja1000);
if (otg_mode_host) {
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 2606210..b6f11d2 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -51,8 +51,6 @@
(QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
#define QONG_DNET_SIZE 0x00001000
-#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
-
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
@@ -78,8 +76,7 @@ static struct resource dnet_resources[] = {
.end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = QONG_FPGA_IRQ,
- .end = QONG_FPGA_IRQ,
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ,
},
};
@@ -95,6 +92,10 @@ static int __init qong_init_dnet(void)
{
int ret;
+ dnet_resources[1].start =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
+ dnet_resources[1].end =
+ gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
ret = platform_device_register(&dnet_device);
return ret;
}
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index 7d26f76..2df625b 100644
--- a/arch/arm/mach-imx/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -130,7 +130,8 @@ static int mxc_mmc1_init(struct device *dev,
gpio_direction_input(gpio_det);
gpio_direction_input(gpio_wp);
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq,
+ ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)),
+ detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"MMC detect", data);
if (ret)
@@ -151,7 +152,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
{
gpio_free(gpio_det);
gpio_free(gpio_wp);
- free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
+ free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data);
}
static const struct imxmmc_platform_data mmc_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index bf0fb87..d639391 100644
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -116,7 +116,8 @@ static int mxc_mmc1_init(struct device *dev,
gpio_direction_input(gpio_det);
gpio_direction_input(gpio_wp);
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
+ ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)),
+ detect_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC detect", data);
if (ret)
@@ -137,7 +138,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
{
gpio_free(gpio_det);
gpio_free(gpio_wp);
- free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
+ free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), data);
}
static const struct imxmmc_platform_data mmc_pdata __initconst = {
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 63f22a0..d8b65b5 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -160,9 +160,6 @@ int mxc_iomux_mode(unsigned int pin_mode);
#define IOMUX_TO_GPIO(iomux_pin) \
((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
-#define IOMUX_TO_IRQ(iomux_pin) \
- (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
- MXC_GPIO_IRQ_START)
/*
* This enumeration is constructed based on the Section
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 03/16] ARM: imx: eliminate macro IRQ_GPIOx()
2012-06-14 5:59 ` Shawn Guo
` (2 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-15 9:23 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
This patch changes all the static gpio irq number assigning with
IRQ_GPIOA() ... IRQ_GPIOF() to run-time assigning with gpio_to_irq
call, and in turn eliminates these macros.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 3 ++-
arch/arm/mach-imx/mach-apf9328.c | 6 ++++--
arch/arm/mach-imx/mach-cpuimx27.c | 12 ++++++++----
arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 9 +++++----
arch/arm/mach-imx/mach-mx21ads.c | 16 +++++++++++-----
arch/arm/mach-imx/mach-mx27ads.c | 12 ++++++------
arch/arm/mach-imx/mach-mxt_td60.c | 6 +++---
arch/arm/mach-imx/mach-pca100.c | 4 ++--
arch/arm/mach-imx/mach-pcm038.c | 4 +++-
arch/arm/mach-imx/mach-scb9328.c | 6 ++++--
arch/arm/mach-imx/pcm970-baseboard.c | 13 +++++++------
arch/arm/plat-mxc/include/mach/iomux-v1.h | 7 -------
12 files changed, 55 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index b46cab0..fd3177f 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -266,7 +266,7 @@ static struct spi_board_info __maybe_unused
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 1500000,
- .irq = IRQ_GPIOD(25),
+ /* irq number is run-time assigned */
.platform_data = &ads7846_config,
.mode = SPI_MODE_2,
},
@@ -329,6 +329,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
/* SPI_CS0 init */
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
+ eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25));
spi_register_board_info(eukrea_mbimx27_spi_board_info,
ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index f4a63ee..5062fcb 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -18,6 +18,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/dm9000.h>
+#include <linux/gpio.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
@@ -87,8 +88,7 @@ static struct resource dm9000_resources[] = {
.end = MX1_CS4_PHYS + 0x00C00003,
.flags = IORESOURCE_MEM,
}, {
- .start = IRQ_GPIOB(14),
- .end = IRQ_GPIOB(14),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
@@ -129,6 +129,8 @@ static void __init apf9328_init(void)
imx1_add_imx_i2c(&apf9328_i2c_data);
+ dm9000_resources[2].start = gpio_to_irq(IMX_GPIO_NR(2, 14));
+ dm9000_resources[2].end = gpio_to_irq(IMX_GPIO_NR(2, 14));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index d085aea..fe74c84 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -169,28 +169,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
static struct plat_serial8250_port serial_platform_data[] = {
{
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
- .irq = IRQ_GPIOB(23),
+ /* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
- .irq = IRQ_GPIOB(22),
+ /* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
- .irq = IRQ_GPIOB(27),
+ /* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
- .irq = IRQ_GPIOB(30),
+ /* irq number is run-time assigned */
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
@@ -279,6 +279,10 @@ static void __init eukrea_cpuimx27_init(void)
#endif
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ serial_platform_data[0].irq = IMX_GPIO_NR(2, 23);
+ serial_platform_data[1].irq = IMX_GPIO_NR(2, 22);
+ serial_platform_data[2].irq = IMX_GPIO_NR(2, 27);
+ serial_platform_data[3].irq = IMX_GPIO_NR(2, 30);
platform_device_register(&serial_device);
#endif
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index dff82eb..54c34a6 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -40,6 +40,7 @@
#include <asm/mach/time.h>
#include <asm/system.h>
#include <mach/common.h>
+#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include "devices-imx27.h"
@@ -47,7 +48,7 @@
#define TVP5150_RSTN (GPIO_PORTC + 18)
#define TVP5150_PWDN (GPIO_PORTC + 19)
#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
-#define SDHC1_IRQ IRQ_GPIOB(25)
+#define SDHC1_IRQ_GPIO IMX_GPIO_NR(2, 25)
#define MOTHERBOARD_BIT2 (GPIO_PORTD + 31)
#define MOTHERBOARD_BIT1 (GPIO_PORTD + 30)
@@ -294,14 +295,14 @@ static int visstrim_m10_sdhc1_init(struct device *dev,
{
int ret;
- ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING,
- "mmc-detect", data);
+ ret = request_irq(gpio_to_irq(SDHC1_IRQ_GPIO), detect_irq,
+ IRQF_TRIGGER_FALLING, "mmc-detect", data);
return ret;
}
static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
{
- free_irq(SDHC1_IRQ, data);
+ free_irq(gpio_to_irq(SDHC1_IRQ_GPIO), data);
}
static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index d14bbe9..ab3bdf7 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -38,7 +38,7 @@
(MX21ADS_MMIO_BASE_ADDR + (offset))
#define MX21ADS_CS8900A_MMIO_SIZE 0x200000
-#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
+#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11)
#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
@@ -159,9 +159,10 @@ static struct platform_device mx21ads_nor_mtd_device = {
.resource = &mx21ads_flash_resource,
};
-static const struct resource mx21ads_cs8900_resources[] __initconst = {
+static struct resource mx21ads_cs8900_resources[] __initdata = {
DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
- DEFINE_RES_IRQ(MX21ADS_CS8900A_IRQ),
+ /* irq number is run-time assigned */
+ DEFINE_RES_IRQ(-1),
};
static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
@@ -241,13 +242,13 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
- return request_irq(IRQ_GPIOD(25), detect_irq,
+ return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq,
IRQF_TRIGGER_FALLING, "mmc-detect", data);
}
static void mx21ads_sdhc_exit(struct device *dev, void *data)
{
- free_irq(IRQ_GPIOD(25), data);
+ free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data);
}
static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
@@ -304,6 +305,11 @@ static void __init mx21ads_board_init(void)
imx21_add_mxc_nand(&mx21ads_nand_board_info);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+ mx21ads_cs8900_resources[1].start =
+ gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
+ mx21ads_cs8900_resources[1].end =
+ gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
platform_device_register_full(&mx21ads_cs8900_devinfo);
}
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 0228d2e..78b6bb5 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -246,25 +246,25 @@ static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
- return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
- "sdhc1-card-detect", data);
+ return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
+ IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
}
static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
- return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
- "sdhc2-card-detect", data);
+ return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
+ IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
}
static void mx27ads_sdhc1_exit(struct device *dev, void *data)
{
- free_irq(IRQ_GPIOE(21), data);
+ free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
}
static void mx27ads_sdhc2_exit(struct device *dev, void *data)
{
- free_irq(IRQ_GPIOB(7), data);
+ free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
}
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 8b3d3f0..0bf6d30 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -213,13 +213,13 @@ static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
- return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING,
- "sdhc1-card-detect", data);
+ return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq,
+ IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
}
static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
{
- free_irq(IRQ_GPIOF(8), data);
+ free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data);
}
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 541152e..8b1dfa2 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -245,7 +245,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
{
int ret;
- ret = request_irq(IRQ_GPIOC(29), detect_irq,
+ ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"imx-mmc-detect", data);
if (ret)
@@ -257,7 +257,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
static void pca100_sdhc2_exit(struct device *dev, void *data)
{
- free_irq(IRQ_GPIOC(29), data);
+ free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
}
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 2f3debe..cfb3903 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -27,6 +27,7 @@
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
+#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -274,7 +275,7 @@ static struct mc13xxx_platform_data pcm038_pmic = {
static struct spi_board_info pcm038_spi_board_info[] __initdata = {
{
.modalias = "mc13783",
- .irq = IRQ_GPIOB(23),
+ /* irq number is run-time assigned */
.max_speed_hz = 300000,
.bus_num = 0,
.chip_select = 0,
@@ -325,6 +326,7 @@ static void __init pcm038_init(void)
mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
imx27_add_spi_imx0(&pcm038_spi0_data);
+ pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
spi_register_board_info(pcm038_spi_board_info,
ARRAY_SIZE(pcm038_spi_board_info));
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index cb9ceae..5001164 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -14,6 +14,7 @@
#include <linux/mtd/physmap.h>
#include <linux/interrupt.h>
#include <linux/dm9000.h>
+#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -78,8 +79,7 @@ static struct resource dm9000x_resources[] = {
.end = MX1_CS5_PHYS + 5,
.flags = IORESOURCE_MEM, /* data access */
}, {
- .start = IRQ_GPIOC(3),
- .end = IRQ_GPIOC(3),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
@@ -123,6 +123,8 @@ static void __init scb9328_init(void)
imx1_add_imx_uart0(&uart_pdata);
printk(KERN_INFO"Scb9328: Adding devices\n");
+ dm9000x_resources[2].start = gpio_to_irq(IMX_GPIO_NR(3, 3));
+ dm9000x_resources[2].end = gpio_to_irq(IMX_GPIO_NR(3, 3));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index 99afbc3..9917e2f 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -95,14 +95,14 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
{
int ret;
- ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING,
- "imx-mmc-detect", data);
+ ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
+ IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
if (ret)
return ret;
ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
if (ret) {
- free_irq(IRQ_GPIOC(29), data);
+ free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
return ret;
}
@@ -113,7 +113,7 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
static void pcm970_sdhc2_exit(struct device *dev, void *data)
{
- free_irq(IRQ_GPIOC(29), data);
+ free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
gpio_free(GPIO_PORTC + 28);
}
@@ -192,8 +192,7 @@ static struct resource pcm970_sja1000_resources[] = {
.end = MX27_CS4_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IRQ_GPIOE(19),
- .end = IRQ_GPIOE(19),
+ /* irq number is run-time assigned */
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
@@ -227,5 +226,7 @@ void __init pcm970_baseboard_init(void)
imx27_add_imx_fb(&pcm038_fb_data);
mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
imx27_add_mxc_mmc(1, &sdhc_pdata);
+ pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19));
+ pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19));
platform_device_register(&pcm970_sja1000);
}
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index f7d1804..02651a4 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -85,13 +85,6 @@
#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
-#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
-#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
-#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
-#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
-#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
-#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
-
extern int mxc_gpio_mode(int gpio_mode);
extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label);
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 04/16] gpio/mxc: move irq_domain_add_legacy call into gpio driver
2012-06-14 5:59 ` Shawn Guo
` (3 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-15 9:26 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Move irq_domain_add_legacy call from imx*-dt.c into gpio driver and
have the gpio driver adopt irqdomain support for both DT and non-DT
boot.
With all imx platform code converted from static gpio irq number
computation to use run-time gpio_to_irq call, we can now use
irq_alloc_descs and irqdomain support to dynamically get irq_base
and have the mapping between gpio and irq number available without
using virtual_irq_start and MXC_GPIO_IRQ_START.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
---
arch/arm/mach-imx/imx27-dt.c | 13 ---------
arch/arm/mach-imx/imx51-dt.c | 12 --------
arch/arm/mach-imx/imx53-dt.c | 12 --------
arch/arm/mach-imx/mach-imx6q.c | 14 ----------
drivers/gpio/gpio-mxc.c | 56 ++++++++++++++++++++++-----------------
5 files changed, 32 insertions(+), 75 deletions(-)
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index eee0cc8..c734e56 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -40,21 +40,8 @@ static int __init imx27_avic_add_irq_domain(struct device_node *np,
return 0;
}
-static int __init imx27_gpio_add_irq_domain(struct device_node *np,
- struct device_node *interrupt_parent)
-{
- static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
- gpio_irq_base -= 32;
- irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
- NULL);
-
- return 0;
-}
-
static const struct of_device_id imx27_irq_match[] __initconst = {
{ .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, },
- { .compatible = "fsl,imx27-gpio", .data = imx27_gpio_add_irq_domain, },
{ /* sentinel */ }
};
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 18e78db..3bdabbc 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -52,20 +52,8 @@ static int __init imx51_tzic_add_irq_domain(struct device_node *np,
return 0;
}
-static int __init imx51_gpio_add_irq_domain(struct device_node *np,
- struct device_node *interrupt_parent)
-{
- static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
- gpio_irq_base -= 32;
- irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
-
- return 0;
-}
-
static const struct of_device_id imx51_irq_match[] __initconst = {
{ .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
- { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
{ /* sentinel */ }
};
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index eb04b62..17fca3c 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -59,20 +59,8 @@ static int __init imx53_tzic_add_irq_domain(struct device_node *np,
return 0;
}
-static int __init imx53_gpio_add_irq_domain(struct device_node *np,
- struct device_node *interrupt_parent)
-{
- static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
- gpio_irq_base -= 32;
- irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
-
- return 0;
-}
-
static const struct of_device_id imx53_irq_match[] __initconst = {
{ .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
- { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
{ /* sentinel */ }
};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index b47e98b..8c2a649 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -16,7 +16,6 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
-#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@@ -136,21 +135,8 @@ static void __init imx6q_map_io(void)
imx6q_clock_map_io();
}
-static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
- struct device_node *interrupt_parent)
-{
- static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
- gpio_irq_base -= 32;
- irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
- NULL);
-
- return 0;
-}
-
static const struct of_device_id imx6q_irq_match[] __initconst = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
- { .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
{ /* sentinel */ }
};
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index c337143..e5db670 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -23,6 +23,7 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
+#include <linux/irqdomain.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -33,8 +34,6 @@
#include <asm-generic/bug.h>
#include <asm/mach/irq.h>
-#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
-
enum mxc_gpio_hwtype {
IMX1_GPIO, /* runs on i.mx1 */
IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
@@ -61,7 +60,7 @@ struct mxc_gpio_port {
void __iomem *base;
int irq;
int irq_high;
- int virtual_irq_start;
+ struct irq_domain *domain;
struct bgpio_chip bgc;
u32 both_edges;
};
@@ -144,14 +143,15 @@ static LIST_HEAD(mxc_gpio_ports);
static int gpio_set_irq_type(struct irq_data *d, u32 type)
{
- u32 gpio = irq_to_gpio(d->irq);
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mxc_gpio_port *port = gc->private;
u32 bit, val;
+ u32 gpio_idx = d->hwirq;
+ u32 gpio = port->bgc.gc.base + gpio_idx;
int edge;
void __iomem *reg = port->base;
- port->both_edges &= ~(1 << (gpio & 31));
+ port->both_edges &= ~(1 << gpio_idx);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
edge = GPIO_INT_RISE_EDGE;
@@ -168,7 +168,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
edge = GPIO_INT_HIGH_LEV;
pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
}
- port->both_edges |= 1 << (gpio & 31);
+ port->both_edges |= 1 << gpio_idx;
break;
case IRQ_TYPE_LEVEL_LOW:
edge = GPIO_INT_LOW_LEV;
@@ -180,11 +180,11 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
return -EINVAL;
}
- reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
- bit = gpio & 0xf;
+ reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* ICR1 or ICR2 */
+ bit = gpio_idx & 0xf;
val = readl(reg) & ~(0x3 << (bit << 1));
writel(val | (edge << (bit << 1)), reg);
- writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
+ writel(1 << gpio_idx, port->base + GPIO_ISR);
return 0;
}
@@ -217,15 +217,13 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
/* handle 32 interrupts in one status register */
static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
{
- u32 gpio_irq_no_base = port->virtual_irq_start;
-
while (irq_stat != 0) {
int irqoffset = fls(irq_stat) - 1;
if (port->both_edges & (1 << irqoffset))
mxc_flip_edge(port, irqoffset);
- generic_handle_irq(gpio_irq_no_base + irqoffset);
+ generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
irq_stat &= ~(1 << irqoffset);
}
@@ -276,10 +274,9 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
*/
static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
{
- u32 gpio = irq_to_gpio(d->irq);
- u32 gpio_idx = gpio & 0x1F;
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct mxc_gpio_port *port = gc->private;
+ u32 gpio_idx = d->hwirq;
if (enable) {
if (port->irq_high && (gpio_idx >= 16))
@@ -296,12 +293,12 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
return 0;
}
-static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
+static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
- gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
+ gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
port->base, handle_level_irq);
gc->private = port;
@@ -352,7 +349,7 @@ static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
struct mxc_gpio_port *port =
container_of(bgc, struct mxc_gpio_port, bgc);
- return port->virtual_irq_start + offset;
+ return irq_find_mapping(port->domain, offset);
}
static int __devinit mxc_gpio_probe(struct platform_device *pdev)
@@ -360,6 +357,7 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node;
struct mxc_gpio_port *port;
struct resource *iores;
+ int irq_base;
int err;
mxc_gpio_get_hw(pdev);
@@ -430,20 +428,30 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
if (err)
goto out_bgpio_remove;
- /*
- * In dt case, we use gpio number range dynamically
- * allocated by gpio core.
- */
- port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
- pdev->id * 32);
+ irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
+ if (irq_base < 0) {
+ err = irq_base;
+ goto out_gpiochip_remove;
+ }
+
+ port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
+ &irq_domain_simple_ops, NULL);
+ if (!port->domain) {
+ err = -ENODEV;
+ goto out_irqdesc_free;
+ }
/* gpio-mxc can be a generic irq chip */
- mxc_gpio_init_gc(port);
+ mxc_gpio_init_gc(port, irq_base);
list_add_tail(&port->node, &mxc_gpio_ports);
return 0;
+out_irqdesc_free:
+ irq_free_descs(irq_base, 32);
+out_gpiochip_remove:
+ WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
out_bgpio_remove:
bgpio_remove(&port->bgc);
out_iounmap:
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 04/16] gpio/mxc: move irq_domain_add_legacy call into gpio driver
2012-06-14 5:59 ` [PATCH 04/16] gpio/mxc: move irq_domain_add_legacy call into gpio driver Shawn Guo
@ 2012-06-15 9:26 ` Dong Aisheng
0 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-15 9:26 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:35PM +0800, Shawn Guo wrote:
> Move irq_domain_add_legacy call from imx*-dt.c into gpio driver and
> have the gpio driver adopt irqdomain support for both DT and non-DT
> boot.
>
> With all imx platform code converted from static gpio irq number
> computation to use run-time gpio_to_irq call, we can now use
> irq_alloc_descs and irqdomain support to dynamically get irq_base
> and have the mapping between gpio and irq number available without
> using virtual_irq_start and MXC_GPIO_IRQ_START.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: Grant Likely <grant.likely@secretlab.ca>
Nice move.
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 05/16] ARM: imx: move irq_domain_add_legacy call into tzic driver
2012-06-14 5:59 ` Shawn Guo
` (4 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-15 9:29 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Move irq_domain_add_legacy call from imx5*-dt.c into tzic init function
and have the tzic driver adopt irqdomain support for both DT and non-DT
boot.
Now tzic init function calls irq_alloc_descs to get irq_base and adds
a lenacy irqdomain with the irq_base, so that the mapping between tzic
irq and Linux irq number can be handled by irqdomain.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/imx51-dt.c | 15 ---------------
arch/arm/mach-imx/imx53-dt.c | 15 ---------------
arch/arm/plat-mxc/tzic.c | 28 ++++++++++++++++++++--------
3 files changed, 20 insertions(+), 38 deletions(-)
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 3bdabbc..d4067fe 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -11,7 +11,6 @@
*/
#include <linux/irq.h>
-#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
@@ -45,18 +44,6 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
{ /* sentinel */ }
};
-static int __init imx51_tzic_add_irq_domain(struct device_node *np,
- struct device_node *interrupt_parent)
-{
- irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
- return 0;
-}
-
-static const struct of_device_id imx51_irq_match[] __initconst = {
- { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
- { /* sentinel */ }
-};
-
static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
{ .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
{ /* sentinel */ }
@@ -68,8 +55,6 @@ static void __init imx51_dt_init(void)
const struct of_device_id *of_id;
void (*func)(void);
- of_irq_init(imx51_irq_match);
-
pinctrl_provide_dummies();
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 17fca3c..fdd9080 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -15,7 +15,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
-#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
@@ -52,18 +51,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
{ /* sentinel */ }
};
-static int __init imx53_tzic_add_irq_domain(struct device_node *np,
- struct device_node *interrupt_parent)
-{
- irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
- return 0;
-}
-
-static const struct of_device_id imx53_irq_match[] __initconst = {
- { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
- { /* sentinel */ }
-};
-
static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
{ .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
{ .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
@@ -91,8 +78,6 @@ static void __init imx53_dt_init(void)
const struct of_device_id *of_id;
void (*func)(void);
- of_irq_init(imx53_irq_match);
-
pinctrl_provide_dummies();
node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 98308ec..abc90e4 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -15,6 +15,8 @@
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
@@ -49,6 +51,7 @@
#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
+static struct irq_domain *domain;
#define TZIC_NUM_IRQS 128
@@ -77,15 +80,14 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
static void tzic_irq_suspend(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- int idx = gc->irq_base >> 5;
+ int idx = d->hwirq >> 5;
__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
}
static void tzic_irq_resume(struct irq_data *d)
{
- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- int idx = gc->irq_base >> 5;
+ int idx = d->hwirq >> 5;
__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
tzic_base + TZIC_WAKEUP0(idx));
@@ -102,11 +104,10 @@ static struct mxc_extra_irq tzic_extra_irq = {
#endif
};
-static __init void tzic_init_gc(unsigned int irq_start)
+static __init void tzic_init_gc(int idx, unsigned int irq_start)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
- int idx = irq_start >> 5;
gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
handle_level_irq);
@@ -140,7 +141,8 @@ asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
while (stat) {
handled = 1;
irqofs = fls(stat) - 1;
- handle_IRQ(irqofs + i * 32, regs);
+ handle_IRQ(irq_find_mapping(domain,
+ irqofs + i * 32), regs);
stat &= ~(1 << irqofs);
}
}
@@ -154,6 +156,8 @@ asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
*/
void __init tzic_init_irq(void __iomem *irqbase)
{
+ struct device_node *np;
+ int irq_base;
int i;
tzic_base = irqbase;
@@ -175,8 +179,16 @@ void __init tzic_init_irq(void __iomem *irqbase)
/* all IRQ no FIQ Warning :: No selection */
- for (i = 0; i < TZIC_NUM_IRQS; i += 32)
- tzic_init_gc(i);
+ irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
+ WARN_ON(irq_base < 0);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
+ domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
+ &irq_domain_simple_ops, NULL);
+ WARN_ON(!domain);
+
+ for (i = 0; i < 4; i++, irq_base += 32)
+ tzic_init_gc(i, irq_base);
#ifdef CONFIG_FIQ
/* Initialize FIQ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 05/16] ARM: imx: move irq_domain_add_legacy call into tzic driver
2012-06-14 5:59 ` [PATCH 05/16] ARM: imx: move irq_domain_add_legacy call into tzic driver Shawn Guo
@ 2012-06-15 9:29 ` Dong Aisheng
0 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-15 9:29 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:36PM +0800, Shawn Guo wrote:
> Move irq_domain_add_legacy call from imx5*-dt.c into tzic init function
> and have the tzic driver adopt irqdomain support for both DT and non-DT
> boot.
>
> Now tzic init function calls irq_alloc_descs to get irq_base and adds
> a lenacy irqdomain with the irq_base, so that the mapping between tzic
> irq and Linux irq number can be handled by irqdomain.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
...
> @@ -77,15 +80,14 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
> static void tzic_irq_suspend(struct irq_data *d)
> {
> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
> - int idx = gc->irq_base >> 5;
> + int idx = d->hwirq >> 5;
Good idea to address the virt irq_base issue.
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 06/16] ARM: imx: move irq_domain_add_legacy call into avic driver
2012-06-14 5:59 ` Shawn Guo
` (5 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-14 7:13 ` Shawn Guo
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Move irq_domain_add_legacy call from imx27-dt.c into avic init function
and have the avic driver adopt irqdomain support for both DT and non-DT
boot.
Now avic init function calls irq_alloc_descs to get irq_base and adds
a lenacy irqdomain with the irq_base, so that the mapping between avic
irq and Linux irq number can be handled by irqdomain.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/imx27-dt.c | 15 ---------------
arch/arm/plat-mxc/avic.c | 26 +++++++++++++++++++-------
2 files changed, 19 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index c734e56..5142ef0 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -10,7 +10,6 @@
*/
#include <linux/irq.h>
-#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
@@ -33,22 +32,8 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
{ /* sentinel */ }
};
-static int __init imx27_avic_add_irq_domain(struct device_node *np,
- struct device_node *interrupt_parent)
-{
- irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
- return 0;
-}
-
-static const struct of_device_id imx27_irq_match[] __initconst = {
- { .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, },
- { /* sentinel */ }
-};
-
static void __init imx27_dt_init(void)
{
- of_irq_init(imx27_irq_match);
-
of_platform_populate(NULL, of_default_bus_match_table,
imx27_auxdata_lookup, NULL);
}
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 689f81f..4fe1d9b 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -19,7 +19,9 @@
#include <linux/module.h>
#include <linux/irq.h>
+#include <linux/irqdomain.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <mach/common.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
@@ -50,6 +52,7 @@
#define AVIC_NUM_IRQS 64
void __iomem *avic_base;
+static struct irq_domain *domain;
static u32 avic_saved_mask_reg[2];
@@ -108,7 +111,7 @@ static void avic_irq_suspend(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = gc->chip_types;
- int idx = gc->irq_base >> 5;
+ int idx = d->hwirq >> 5;
avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
__raw_writel(gc->wake_active, avic_base + ct->regs.mask);
@@ -118,7 +121,7 @@ static void avic_irq_resume(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = gc->chip_types;
- int idx = gc->irq_base >> 5;
+ int idx = d->hwirq >> 5;
__raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
}
@@ -128,11 +131,10 @@ static void avic_irq_resume(struct irq_data *d)
#define avic_irq_resume NULL
#endif
-static __init void avic_init_gc(unsigned int irq_start)
+static __init void avic_init_gc(int idx, unsigned int irq_start)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
- int idx = irq_start >> 5;
gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
handle_level_irq);
@@ -161,7 +163,7 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
if (nivector == 0xffff)
break;
- handle_IRQ(nivector, regs);
+ handle_IRQ(irq_find_mapping(domain, nivector), regs);
} while (1);
}
@@ -172,6 +174,8 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
*/
void __init mxc_init_irq(void __iomem *irqbase)
{
+ struct device_node *np;
+ int irq_base;
int i;
avic_base = irqbase;
@@ -190,8 +194,16 @@ void __init mxc_init_irq(void __iomem *irqbase)
__raw_writel(0, avic_base + AVIC_INTTYPEH);
__raw_writel(0, avic_base + AVIC_INTTYPEL);
- for (i = 0; i < AVIC_NUM_IRQS; i += 32)
- avic_init_gc(i);
+ irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
+ WARN_ON(irq_base < 0);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,avic");
+ domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
+ &irq_domain_simple_ops, NULL);
+ WARN_ON(!domain);
+
+ for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
+ avic_init_gc(i, irq_base);
/* Set default priority value (0) for all IRQ's */
for (i = 0; i < 8; i++)
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 06/16] ARM: imx: move irq_domain_add_legacy call into avic driver
2012-06-14 5:59 ` [PATCH 06/16] ARM: imx: move irq_domain_add_legacy call into avic driver Shawn Guo
@ 2012-06-14 7:13 ` Shawn Guo
2012-06-15 9:30 ` Dong Aisheng
2012-07-06 6:26 ` [PATCH] ARM: imx: select IRQ_DOMAIN Uwe Kleine-König
0 siblings, 2 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 7:13 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:37PM +0800, Shawn Guo wrote:
> Move irq_domain_add_legacy call from imx27-dt.c into avic init function
> and have the avic driver adopt irqdomain support for both DT and non-DT
> boot.
>
> Now avic init function calls irq_alloc_descs to get irq_base and adds
> a lenacy irqdomain with the irq_base, so that the mapping between avic
> irq and Linux irq number can be handled by irqdomain.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> arch/arm/mach-imx/imx27-dt.c | 15 ---------------
> arch/arm/plat-mxc/avic.c | 26 +++++++++++++++++++-------
> 2 files changed, 19 insertions(+), 22 deletions(-)
>
The following changes should be amended.
Regards,
Shawn
--8<---
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 4fe1d9b..e612cc1 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -59,9 +59,12 @@ static u32 avic_saved_mask_reg[2];
#ifdef CONFIG_MXC_IRQ_PRIOR
static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
{
+ struct irq_data *d = irq_get_irq_data(irq);
unsigned int temp;
unsigned int mask = 0x0F << irq % 8 * 4;
+ irq = d->hwirq;
+
if (irq >= AVIC_NUM_IRQS)
return -EINVAL;
@@ -78,8 +81,11 @@ static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
#ifdef CONFIG_FIQ
static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
{
+ struct irq_data *d = irq_get_irq_data(irq);
unsigned int irqt;
+ irq = d->hwirq;
+
if (irq >= AVIC_NUM_IRQS)
return -EINVAL;
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 06/16] ARM: imx: move irq_domain_add_legacy call into avic driver
2012-06-14 7:13 ` Shawn Guo
@ 2012-06-15 9:30 ` Dong Aisheng
2012-07-06 6:26 ` [PATCH] ARM: imx: select IRQ_DOMAIN Uwe Kleine-König
1 sibling, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-15 9:30 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 03:13:28PM +0800, Shawn Guo wrote:
> On Thu, Jun 14, 2012 at 01:59:37PM +0800, Shawn Guo wrote:
> > Move irq_domain_add_legacy call from imx27-dt.c into avic init function
> > and have the avic driver adopt irqdomain support for both DT and non-DT
> > boot.
> >
> > Now avic init function calls irq_alloc_descs to get irq_base and adds
> > a lenacy irqdomain with the irq_base, so that the mapping between avic
> > irq and Linux irq number can be handled by irqdomain.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> > ---
> > arch/arm/mach-imx/imx27-dt.c | 15 ---------------
> > arch/arm/plat-mxc/avic.c | 26 +++++++++++++++++++-------
> > 2 files changed, 19 insertions(+), 22 deletions(-)
> >
> The following changes should be amended.
>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH] ARM: imx: select IRQ_DOMAIN
2012-06-14 7:13 ` Shawn Guo
2012-06-15 9:30 ` Dong Aisheng
@ 2012-07-06 6:26 ` Uwe Kleine-König
2012-07-06 7:05 ` Shawn Guo
1 sibling, 1 reply; 85+ messages in thread
From: Uwe Kleine-König @ 2012-07-06 6:26 UTC (permalink / raw)
To: linux-arm-kernel
Commit
544496a (ARM: imx: move irq_domain_add_legacy call into avic driver)
introduced unconditional calls to irq_find_mapping and
irq_domain_add_legacy, but it's still possible to have a .config without
CONFIG_IRQ_DOMAIN=y resulting in
CC arch/arm/plat-mxc/avic.o
arch/arm/plat-mxc/avic.c: In function 'avic_handle_irq':
arch/arm/plat-mxc/avic.c:172: error: implicit declaration of function 'irq_find_mapping'
arch/arm/plat-mxc/avic.c: In function 'mxc_init_irq':
arch/arm/plat-mxc/avic.c:207: error: implicit declaration of function 'irq_domain_add_legacy'
arch/arm/plat-mxc/avic.c:208: error: 'irq_domain_simple_ops' undeclared (first use in this function)
arch/arm/plat-mxc/avic.c:208: error: (Each undeclared identifier is reported only once
arch/arm/plat-mxc/avic.c:208: error: for each function it appears in.)
arch/arm/plat-mxc/avic.c:208: warning: assignment makes pointer from integer without a cast
make[3]: *** [arch/arm/plat-mxc/avic.o] Error 1
make[2]: *** [arch/arm/plat-mxc/avic.o] Error 2
make[1]: *** [sub-make] Error 2
make: *** [all] Error 2
Fix that by selecting CONFIG_IRQ_DOMAIN for ARCH_MXC.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 84449dd..38b6b90 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -446,6 +446,7 @@ config ARCH_MXC
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select MULTI_IRQ_HANDLER
+ select IRQ_DOMAIN
help
Support for Freescale MXC/iMX-based family of processors
--
1.7.10
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH] ARM: imx: select IRQ_DOMAIN
2012-07-06 6:26 ` [PATCH] ARM: imx: select IRQ_DOMAIN Uwe Kleine-König
@ 2012-07-06 7:05 ` Shawn Guo
2012-07-06 7:07 ` Uwe Kleine-König
2012-07-06 7:12 ` Sascha Hauer
0 siblings, 2 replies; 85+ messages in thread
From: Shawn Guo @ 2012-07-06 7:05 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 06, 2012 at 08:26:34AM +0200, Uwe Kleine-K?nig wrote:
> Commit
>
> 544496a (ARM: imx: move irq_domain_add_legacy call into avic driver)
>
> introduced unconditional calls to irq_find_mapping and
> irq_domain_add_legacy, but it's still possible to have a .config without
> CONFIG_IRQ_DOMAIN=y resulting in
>
> CC arch/arm/plat-mxc/avic.o
> arch/arm/plat-mxc/avic.c: In function 'avic_handle_irq':
> arch/arm/plat-mxc/avic.c:172: error: implicit declaration of function 'irq_find_mapping'
> arch/arm/plat-mxc/avic.c: In function 'mxc_init_irq':
> arch/arm/plat-mxc/avic.c:207: error: implicit declaration of function 'irq_domain_add_legacy'
> arch/arm/plat-mxc/avic.c:208: error: 'irq_domain_simple_ops' undeclared (first use in this function)
> arch/arm/plat-mxc/avic.c:208: error: (Each undeclared identifier is reported only once
> arch/arm/plat-mxc/avic.c:208: error: for each function it appears in.)
> arch/arm/plat-mxc/avic.c:208: warning: assignment makes pointer from integer without a cast
> make[3]: *** [arch/arm/plat-mxc/avic.o] Error 1
> make[2]: *** [arch/arm/plat-mxc/avic.o] Error 2
> make[1]: *** [sub-make] Error 2
> make: *** [all] Error 2
>
> Fix that by selecting CONFIG_IRQ_DOMAIN for ARCH_MXC.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> ---
> arch/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 84449dd..38b6b90 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -446,6 +446,7 @@ config ARCH_MXC
> select CLKSRC_MMIO
> select GENERIC_IRQ_CHIP
> select MULTI_IRQ_HANDLER
> + select IRQ_DOMAIN
Right, I forgot that we haven't selected USE_OF for ARCH_MXC. Can we
do that instead of selecting IRQ_DOMAIN, since we are on the way to
device tree? Selecting USE_OF will save us a lot of #ifdef CONFIG_OF
checks later when we add device tree support into more codes.
Regards,
Shawn
> help
> Support for Freescale MXC/iMX-based family of processors
>
> --
> 1.7.10
>
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH] ARM: imx: select IRQ_DOMAIN
2012-07-06 7:05 ` Shawn Guo
@ 2012-07-06 7:07 ` Uwe Kleine-König
2012-07-06 7:12 ` Sascha Hauer
1 sibling, 0 replies; 85+ messages in thread
From: Uwe Kleine-König @ 2012-07-06 7:07 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Fri, Jul 06, 2012 at 03:05:01PM +0800, Shawn Guo wrote:
> On Fri, Jul 06, 2012 at 08:26:34AM +0200, Uwe Kleine-K?nig wrote:
> > Commit
> >
> > 544496a (ARM: imx: move irq_domain_add_legacy call into avic driver)
> >
> > introduced unconditional calls to irq_find_mapping and
> > irq_domain_add_legacy, but it's still possible to have a .config without
> > CONFIG_IRQ_DOMAIN=y resulting in
> >
> > CC arch/arm/plat-mxc/avic.o
> > arch/arm/plat-mxc/avic.c: In function 'avic_handle_irq':
> > arch/arm/plat-mxc/avic.c:172: error: implicit declaration of function 'irq_find_mapping'
> > arch/arm/plat-mxc/avic.c: In function 'mxc_init_irq':
> > arch/arm/plat-mxc/avic.c:207: error: implicit declaration of function 'irq_domain_add_legacy'
> > arch/arm/plat-mxc/avic.c:208: error: 'irq_domain_simple_ops' undeclared (first use in this function)
> > arch/arm/plat-mxc/avic.c:208: error: (Each undeclared identifier is reported only once
> > arch/arm/plat-mxc/avic.c:208: error: for each function it appears in.)
> > arch/arm/plat-mxc/avic.c:208: warning: assignment makes pointer from integer without a cast
> > make[3]: *** [arch/arm/plat-mxc/avic.o] Error 1
> > make[2]: *** [arch/arm/plat-mxc/avic.o] Error 2
> > make[1]: *** [sub-make] Error 2
> > make: *** [all] Error 2
> >
> > Fix that by selecting CONFIG_IRQ_DOMAIN for ARCH_MXC.
> >
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> > ---
> > arch/arm/Kconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 84449dd..38b6b90 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -446,6 +446,7 @@ config ARCH_MXC
> > select CLKSRC_MMIO
> > select GENERIC_IRQ_CHIP
> > select MULTI_IRQ_HANDLER
> > + select IRQ_DOMAIN
>
> Right, I forgot that we haven't selected USE_OF for ARCH_MXC. Can we
> do that instead of selecting IRQ_DOMAIN, since we are on the way to
> device tree? Selecting USE_OF will save us a lot of #ifdef CONFIG_OF
> checks later when we add device tree support into more codes.
IMHO it's not up to me to decide that. Sascha?
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH] ARM: imx: select IRQ_DOMAIN
2012-07-06 7:05 ` Shawn Guo
2012-07-06 7:07 ` Uwe Kleine-König
@ 2012-07-06 7:12 ` Sascha Hauer
2012-07-06 7:18 ` [PATCH] ARM: imx: select USE_OF Uwe Kleine-König
2012-07-06 7:47 ` [PATCH v2] " Uwe Kleine-König
1 sibling, 2 replies; 85+ messages in thread
From: Sascha Hauer @ 2012-07-06 7:12 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 06, 2012 at 03:05:01PM +0800, Shawn Guo wrote:
> On Fri, Jul 06, 2012 at 08:26:34AM +0200, Uwe Kleine-K?nig wrote:
> > ---
> > arch/arm/Kconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 84449dd..38b6b90 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -446,6 +446,7 @@ config ARCH_MXC
> > select CLKSRC_MMIO
> > select GENERIC_IRQ_CHIP
> > select MULTI_IRQ_HANDLER
> > + select IRQ_DOMAIN
>
> Right, I forgot that we haven't selected USE_OF for ARCH_MXC. Can we
> do that instead of selecting IRQ_DOMAIN, since we are on the way to
> device tree? Selecting USE_OF will save us a lot of #ifdef CONFIG_OF
> checks later when we add device tree support into more codes.
Fine with me.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH] ARM: imx: select USE_OF
2012-07-06 7:12 ` Sascha Hauer
@ 2012-07-06 7:18 ` Uwe Kleine-König
2012-07-06 7:31 ` Shawn Guo
2012-07-06 7:47 ` [PATCH v2] " Uwe Kleine-König
1 sibling, 1 reply; 85+ messages in thread
From: Uwe Kleine-König @ 2012-07-06 7:18 UTC (permalink / raw)
To: linux-arm-kernel
Commit
544496a (ARM: imx: move irq_domain_add_legacy call into avic driver)
introduced unconditional calls to irq_find_mapping and
irq_domain_add_legacy, but it's still possible to have a .config without
CONFIG_IRQ_DOMAIN=y resulting in
CC arch/arm/plat-mxc/avic.o
arch/arm/plat-mxc/avic.c: In function 'avic_handle_irq':
arch/arm/plat-mxc/avic.c:172: error: implicit declaration of function 'irq_find_mapping'
arch/arm/plat-mxc/avic.c: In function 'mxc_init_irq':
arch/arm/plat-mxc/avic.c:207: error: implicit declaration of function 'irq_domain_add_legacy'
arch/arm/plat-mxc/avic.c:208: error: 'irq_domain_simple_ops' undeclared (first use in this function)
arch/arm/plat-mxc/avic.c:208: error: (Each undeclared identifier is reported only once
arch/arm/plat-mxc/avic.c:208: error: for each function it appears in.)
arch/arm/plat-mxc/avic.c:208: warning: assignment makes pointer from integer without a cast
make[3]: *** [arch/arm/plat-mxc/avic.o] Error 1
make[2]: *** [arch/arm/plat-mxc/avic.o] Error 2
make[1]: *** [sub-make] Error 2
make: *** [all] Error 2
While selecting CONFIG_IRQ_DOMAIN would be enough, USE_OF is the future
and implies CONFIG_IRQ_DOMAIN. So select USE_OF for ARCH_MXC.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 84449dd..97a33c5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -446,6 +446,7 @@ config ARCH_MXC
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select MULTI_IRQ_HANDLER
+ select USE_OF
help
Support for Freescale MXC/iMX-based family of processors
--
1.7.10
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH] ARM: imx: select USE_OF
2012-07-06 7:18 ` [PATCH] ARM: imx: select USE_OF Uwe Kleine-König
@ 2012-07-06 7:31 ` Shawn Guo
0 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-07-06 7:31 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 06, 2012 at 09:18:05AM +0200, Uwe Kleine-K?nig wrote:
> Commit
>
> 544496a (ARM: imx: move irq_domain_add_legacy call into avic driver)
>
> introduced unconditional calls to irq_find_mapping and
> irq_domain_add_legacy, but it's still possible to have a .config without
> CONFIG_IRQ_DOMAIN=y resulting in
>
> CC arch/arm/plat-mxc/avic.o
> arch/arm/plat-mxc/avic.c: In function 'avic_handle_irq':
> arch/arm/plat-mxc/avic.c:172: error: implicit declaration of function 'irq_find_mapping'
> arch/arm/plat-mxc/avic.c: In function 'mxc_init_irq':
> arch/arm/plat-mxc/avic.c:207: error: implicit declaration of function 'irq_domain_add_legacy'
> arch/arm/plat-mxc/avic.c:208: error: 'irq_domain_simple_ops' undeclared (first use in this function)
> arch/arm/plat-mxc/avic.c:208: error: (Each undeclared identifier is reported only once
> arch/arm/plat-mxc/avic.c:208: error: for each function it appears in.)
> arch/arm/plat-mxc/avic.c:208: warning: assignment makes pointer from integer without a cast
> make[3]: *** [arch/arm/plat-mxc/avic.o] Error 1
> make[2]: *** [arch/arm/plat-mxc/avic.o] Error 2
> make[1]: *** [sub-make] Error 2
> make: *** [all] Error 2
>
> While selecting CONFIG_IRQ_DOMAIN would be enough, USE_OF is the future
> and implies CONFIG_IRQ_DOMAIN. So select USE_OF for ARCH_MXC.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
> ---
> arch/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 84449dd..97a33c5 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -446,6 +446,7 @@ config ARCH_MXC
> select CLKSRC_MMIO
> select GENERIC_IRQ_CHIP
> select MULTI_IRQ_HANDLER
> + select USE_OF
Thanks for the quick turn-around, Uwe.
With the change here, these "select USE_OF" in arch/arm/mach-imx/Kconfig
can be removed altogether, I think.
Regards,
Shawn
> help
> Support for Freescale MXC/iMX-based family of processors
>
> --
> 1.7.10
>
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v2] ARM: imx: select USE_OF
2012-07-06 7:12 ` Sascha Hauer
2012-07-06 7:18 ` [PATCH] ARM: imx: select USE_OF Uwe Kleine-König
@ 2012-07-06 7:47 ` Uwe Kleine-König
2012-07-06 8:04 ` Shawn Guo
1 sibling, 1 reply; 85+ messages in thread
From: Uwe Kleine-König @ 2012-07-06 7:47 UTC (permalink / raw)
To: linux-arm-kernel
Commit
544496a (ARM: imx: move irq_domain_add_legacy call into avic driver)
introduced unconditional calls to irq_find_mapping and
irq_domain_add_legacy, but it's still possible to have a .config without
CONFIG_IRQ_DOMAIN=y resulting in
CC arch/arm/plat-mxc/avic.o
arch/arm/plat-mxc/avic.c: In function 'avic_handle_irq':
arch/arm/plat-mxc/avic.c:172: error: implicit declaration of function 'irq_find_mapping'
arch/arm/plat-mxc/avic.c: In function 'mxc_init_irq':
arch/arm/plat-mxc/avic.c:207: error: implicit declaration of function 'irq_domain_add_legacy'
arch/arm/plat-mxc/avic.c:208: error: 'irq_domain_simple_ops' undeclared (first use in this function)
arch/arm/plat-mxc/avic.c:208: error: (Each undeclared identifier is reported only once
arch/arm/plat-mxc/avic.c:208: error: for each function it appears in.)
arch/arm/plat-mxc/avic.c:208: warning: assignment makes pointer from integer without a cast
make[3]: *** [arch/arm/plat-mxc/avic.o] Error 1
make[2]: *** [arch/arm/plat-mxc/avic.o] Error 2
make[1]: *** [sub-make] Error 2
make: *** [all] Error 2
While selecting CONFIG_IRQ_DOMAIN would be enough, USE_OF is the future
and implies CONFIG_IRQ_DOMAIN. So select USE_OF for ARCH_MXC and drop
other explicit selects that are superflous now.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-imx/Kconfig | 4 ----
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 84449dd..97a33c5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -446,6 +446,7 @@ config ARCH_MXC
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select MULTI_IRQ_HANDLER
+ select USE_OF
help
Support for Freescale MXC/iMX-based family of processors
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0021f72..7793c63 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -380,7 +380,6 @@ config MACH_IMX27IPCAM
config MACH_IMX27_DT
bool "Support i.MX27 platforms from device tree"
select SOC_IMX27
- select USE_OF
help
Include support for Freescale i.MX27 based platforms
using the device tree for discovery
@@ -662,7 +661,6 @@ comment "i.MX51 machines:"
config MACH_IMX51_DT
bool "Support i.MX51 platforms from device tree"
select SOC_IMX51
- select USE_OF
select MACH_MX51_BABBAGE
help
Include support for Freescale i.MX51 based platforms
@@ -758,7 +756,6 @@ comment "i.MX53 machines:"
config MACH_IMX53_DT
bool "Support i.MX53 platforms from device tree"
select SOC_IMX53
- select USE_OF
select MACH_MX53_ARD
select MACH_MX53_EVK
select MACH_MX53_LOCO
@@ -831,7 +828,6 @@ config SOC_IMX6Q
select HAVE_SMP
select PINCTRL
select PINCTRL_IMX6Q
- select USE_OF
help
This enables support for Freescale i.MX6 Quad processor.
--
1.7.10
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH v2] ARM: imx: select USE_OF
2012-07-06 7:47 ` [PATCH v2] " Uwe Kleine-König
@ 2012-07-06 8:04 ` Shawn Guo
2012-07-06 19:15 ` Arnd Bergmann
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-07-06 8:04 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 06, 2012 at 09:47:20AM +0200, Uwe Kleine-K?nig wrote:
> Commit
>
> 544496a (ARM: imx: move irq_domain_add_legacy call into avic driver)
>
> introduced unconditional calls to irq_find_mapping and
> irq_domain_add_legacy, but it's still possible to have a .config without
> CONFIG_IRQ_DOMAIN=y resulting in
>
> CC arch/arm/plat-mxc/avic.o
> arch/arm/plat-mxc/avic.c: In function 'avic_handle_irq':
> arch/arm/plat-mxc/avic.c:172: error: implicit declaration of function 'irq_find_mapping'
> arch/arm/plat-mxc/avic.c: In function 'mxc_init_irq':
> arch/arm/plat-mxc/avic.c:207: error: implicit declaration of function 'irq_domain_add_legacy'
> arch/arm/plat-mxc/avic.c:208: error: 'irq_domain_simple_ops' undeclared (first use in this function)
> arch/arm/plat-mxc/avic.c:208: error: (Each undeclared identifier is reported only once
> arch/arm/plat-mxc/avic.c:208: error: for each function it appears in.)
> arch/arm/plat-mxc/avic.c:208: warning: assignment makes pointer from integer without a cast
> make[3]: *** [arch/arm/plat-mxc/avic.o] Error 1
> make[2]: *** [arch/arm/plat-mxc/avic.o] Error 2
> make[1]: *** [sub-make] Error 2
> make: *** [all] Error 2
>
> While selecting CONFIG_IRQ_DOMAIN would be enough, USE_OF is the future
> and implies CONFIG_IRQ_DOMAIN. So select USE_OF for ARCH_MXC and drop
> other explicit selects that are superflous now.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
Applied on top of imx/sparse-irq branch. Thanks, Uwe.
Arnd,
One more fix, sorry. Can you please pull it?
Regards,
Shawn
The following changes since commit 6684294d27abb24e61916871c4ecfdaccc14eb03:
ARM: imx: Fix build error due to missing irqs.h include (2012-07-04 11:19:40 +0800)
are available in the git repository at:
git://git.linaro.org/people/shawnguo/linux-2.6.git imx/sparse-irq
Uwe Kleine-K?nig (1):
ARM: imx: select USE_OF
arch/arm/Kconfig | 1 +
arch/arm/mach-imx/Kconfig | 4 ----
2 files changed, 1 insertions(+), 4 deletions(-)
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH v2] ARM: imx: select USE_OF
2012-07-06 8:04 ` Shawn Guo
@ 2012-07-06 19:15 ` Arnd Bergmann
0 siblings, 0 replies; 85+ messages in thread
From: Arnd Bergmann @ 2012-07-06 19:15 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 06 July 2012, Shawn Guo wrote:
> The following changes since commit 6684294d27abb24e61916871c4ecfdaccc14eb03:
>
> ARM: imx: Fix build error due to missing irqs.h include (2012-07-04 11:19:40 +0800)
>
> are available in the git repository at:
> git://git.linaro.org/people/shawnguo/linux-2.6.git imx/sparse-irq
>
Pulled, thanks!
Arnd
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 07/16] dma: ipu: remove the use of ipu_platform_data
2012-06-14 5:59 ` Shawn Guo
` (6 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-14 10:26 ` Vinod Koul
2012-06-15 9:37 ` Dong Aisheng
-1 siblings, 2 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
The struct ipu_platform_data is used by platform code to pass
MXC_IPU_IRQ_START to ipu-core driver. We can save it by having
ipu-core driver call irq_alloc_descs to get the irq_base.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Vinod Koul <vinod.koul@intel.com>
---
arch/arm/mach-imx/devices-imx31.h | 4 ++--
arch/arm/mach-imx/devices-imx35.h | 4 ++--
arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c | 6 +-----
arch/arm/mach-imx/mach-armadillo5x0.c | 6 +-----
arch/arm/mach-imx/mach-mx31_3ds.c | 6 +-----
arch/arm/mach-imx/mach-mx31moboard.c | 6 +-----
arch/arm/mach-imx/mach-mx35_3ds.c | 10 +---------
arch/arm/mach-imx/mach-pcm037.c | 6 +-----
arch/arm/mach-imx/mach-pcm043.c | 6 +-----
arch/arm/mach-imx/mach-vpr200.c | 6 +-----
arch/arm/mach-imx/mx31lilly-db.c | 6 +-----
arch/arm/plat-mxc/devices/platform-ipu-core.c | 5 ++---
arch/arm/plat-mxc/include/mach/devices-common.h | 4 +---
arch/arm/plat-mxc/include/mach/ipu.h | 4 ----
drivers/dma/ipu/ipu_idmac.c | 8 +++-----
drivers/dma/ipu/ipu_irq.c | 14 +++++++++-----
16 files changed, 28 insertions(+), 73 deletions(-)
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
index 488e241..911c2da 100644
--- a/arch/arm/mach-imx/devices-imx31.h
+++ b/arch/arm/mach-imx/devices-imx31.h
@@ -42,8 +42,8 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
extern const struct imx_ipu_core_data imx31_ipu_core_data;
-#define imx31_add_ipu_core(pdata) \
- imx_add_ipu_core(&imx31_ipu_core_data, pdata)
+#define imx31_add_ipu_core() \
+ imx_add_ipu_core(&imx31_ipu_core_data)
#define imx31_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
#define imx31_add_mx3_sdc_fb(pdata) \
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
index 7b99ef0..6fb9072 100644
--- a/arch/arm/mach-imx/devices-imx35.h
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -50,8 +50,8 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
extern const struct imx_ipu_core_data imx35_ipu_core_data;
-#define imx35_add_ipu_core(pdata) \
- imx_add_ipu_core(&imx35_ipu_core_data, pdata)
+#define imx35_add_ipu_core() \
+ imx_add_ipu_core(&imx35_ipu_core_data)
#define imx35_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
#define imx35_add_mx3_sdc_fb(pdata) \
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 557f6c4..6e9dd12 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -95,10 +95,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "CMO-QVGA",
.mode = fb_modedb,
@@ -287,7 +283,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
printk(KERN_ERR "error setting mbimxsd pads !\n");
imx35_add_imx_uart1(&uart_pdata);
- imx35_add_ipu_core(&mx3_ipu_data);
+ imx35_add_ipu_core();
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index f83c5c6..2c6ab32 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -367,10 +367,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "CRT-VGA",
.mode = fb_modedb,
@@ -517,7 +513,7 @@ static void __init armadillo5x0_init(void)
imx31_add_mxc_mmc(0, &sdhc_pdata);
/* Register FB */
- imx31_add_ipu_core(&mx3_ipu_data);
+ imx31_add_ipu_core();
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* Register NOR Flash */
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index ecdba04..618935e 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -274,10 +274,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
-static struct ipu_platform_data mx3_ipu_data = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Epson-VGA",
.mode = fb_modedb,
@@ -743,7 +739,7 @@ static void __init mx31_3ds_init(void)
imx31_add_mxc_mmc(0, &sdhc1_pdata);
imx31_add_spi_imx0(&spi0_pdata);
- imx31_add_ipu_core(&mx3_ipu_data);
+ imx31_add_ipu_core();
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* CSI */
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index f0d26db..54d9e5d 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -473,10 +473,6 @@ static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = {
.leds = mx31moboard_leds,
};
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static struct platform_device *devices[] __initdata = {
&mx31moboard_flash,
};
@@ -494,7 +490,7 @@ static int __init mx31moboard_init_cam(void)
int dma, ret = -ENOMEM;
struct platform_device *pdev;
- imx31_add_ipu_core(&mx3_ipu_data);
+ imx31_add_ipu_core();
pdev = imx31_alloc_mx3_camera(&camera_pdata);
if (IS_ERR(pdev))
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index fa1ea74..ad63e6e 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -80,10 +80,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Ceramate-CLAA070VC01",
.mode = fb_modedb,
@@ -297,10 +293,6 @@ err:
return ret;
}
-static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static struct i2c_board_info mx35_3ds_i2c_camera = {
I2C_BOARD_INFO("ov2640", 0x30),
};
@@ -596,7 +588,7 @@ static void __init mx35_3ds_init(void)
i2c_register_board_info(
0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
- imx35_add_ipu_core(&mx35_3ds_ipu_data);
+ imx35_add_ipu_core();
platform_device_register(&mx35_3ds_ov2640);
imx35_3ds_init_camera();
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 551a035..ded4ed9 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -441,10 +441,6 @@ static struct platform_device *devices[] __initdata = {
&pcm037_mt9v022,
};
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static const struct fb_videomode fb_modedb[] = {
{
/* 240x320 @ 60 Hz Sharp */
@@ -648,7 +644,7 @@ static void __init pcm037_init(void)
imx31_add_mxc_nand(&pcm037_nand_board_info);
imx31_add_mxc_mmc(0, &sdhc_pdata);
- imx31_add_ipu_core(&mx3_ipu_data);
+ imx31_add_ipu_core();
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* CSI */
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 73585f5..133908f 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -76,10 +76,6 @@ static const struct fb_videomode fb_modedb[] = {
},
};
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Sharp-LQ035Q7",
.mode = fb_modedb,
@@ -376,7 +372,7 @@ static void __init pcm043_init(void)
imx35_add_imx_i2c0(&pcm043_i2c0_data);
- imx35_add_ipu_core(&mx3_ipu_data);
+ imx35_add_ipu_core();
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
if (otg_mode_host) {
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index e36eb2c..1aa5622 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -87,10 +87,6 @@ static const struct fb_videomode fb_modedb[] = {
}
};
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "PT0708048",
.mode = fb_modedb,
@@ -290,7 +286,7 @@ static void __init vpr200_board_init(void)
imx35_add_imx_uart0(NULL);
imx35_add_imx_uart2(NULL);
- imx35_add_ipu_core(&mx3_ipu_data);
+ imx35_add_ipu_core();
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
imx35_add_fsl_usb2_udc(&otg_device_pdata);
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index 2df625b..29e890f 100644
--- a/arch/arm/mach-imx/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -162,10 +162,6 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = {
};
/* Framebuffer support */
-static const struct ipu_platform_data ipu_data __initconst = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
static const struct fb_videomode fb_modedb = {
/* 640x480 TFT panel (IPS-056T) */
.name = "CRT-VGA",
@@ -199,7 +195,7 @@ static void __init mx31lilly_init_fb(void)
return;
}
- imx31_add_ipu_core(&ipu_data);
+ imx31_add_ipu_core();
imx31_add_mx3_sdc_fb(&fb_pdata);
gpio_direction_output(LCD_VCC_EN_GPIO, 1);
}
diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c
index 79d340a..d1e33cc 100644
--- a/arch/arm/plat-mxc/devices/platform-ipu-core.c
+++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c
@@ -30,8 +30,7 @@ const struct imx_ipu_core_data imx35_ipu_core_data __initconst =
static struct platform_device *imx_ipu_coredev __initdata;
struct platform_device *__init imx_add_ipu_core(
- const struct imx_ipu_core_data *data,
- const struct ipu_platform_data *pdata)
+ const struct imx_ipu_core_data *data)
{
/* The resource order is important! */
struct resource res[] = {
@@ -55,7 +54,7 @@ struct platform_device *__init imx_add_ipu_core(
};
return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1,
- res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+ res, ARRAY_SIZE(res), NULL, 0);
}
struct platform_device *__init imx_alloc_mx3_camera(
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 1b2258d..a7f5bb1 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -183,7 +183,6 @@ struct platform_device *__init imx_add_imx_udc(
const struct imx_imx_udc_data *data,
const struct imxusb_platform_data *pdata);
-#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mx3_camera.h>
struct imx_ipu_core_data {
@@ -192,8 +191,7 @@ struct imx_ipu_core_data {
resource_size_t errirq;
};
struct platform_device *__init imx_add_ipu_core(
- const struct imx_ipu_core_data *data,
- const struct ipu_platform_data *pdata);
+ const struct imx_ipu_core_data *data);
struct platform_device *__init imx_alloc_mx3_camera(
const struct imx_ipu_core_data *data,
const struct mx3_camera_pdata *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h
index a9221f1..539e559 100644
--- a/arch/arm/plat-mxc/include/mach/ipu.h
+++ b/arch/arm/plat-mxc/include/mach/ipu.h
@@ -110,10 +110,6 @@ enum ipu_rotate_mode {
IPU_ROTATE_90_LEFT = 7,
};
-struct ipu_platform_data {
- unsigned int irq_base;
-};
-
/*
* Enumeration of DI ports for ADC.
*/
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 5ec7204..c7573e5 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1663,7 +1663,6 @@ static void __exit ipu_idmac_exit(struct ipu *ipu)
static int __init ipu_probe(struct platform_device *pdev)
{
- struct ipu_platform_data *pdata = pdev->dev.platform_data;
struct resource *mem_ipu, *mem_ic;
int ret;
@@ -1671,7 +1670,7 @@ static int __init ipu_probe(struct platform_device *pdev)
mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (!pdata || !mem_ipu || !mem_ic)
+ if (!mem_ipu || !mem_ic)
return -EINVAL;
ipu_data.dev = &pdev->dev;
@@ -1688,10 +1687,9 @@ static int __init ipu_probe(struct platform_device *pdev)
goto err_noirq;
ipu_data.irq_err = ret;
- ipu_data.irq_base = pdata->irq_base;
- dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
- ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
+ dev_dbg(&pdev->dev, "fn irq %u, err irq %u\n",
+ ipu_data.irq_fn, ipu_data.irq_err);
/* Remap IPU common registers */
ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));
diff --git a/drivers/dma/ipu/ipu_irq.c b/drivers/dma/ipu/ipu_irq.c
index a71f55e..fa95bcc 100644
--- a/drivers/dma/ipu/ipu_irq.c
+++ b/drivers/dma/ipu/ipu_irq.c
@@ -14,6 +14,7 @@
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/io.h>
+#include <linux/module.h>
#include <mach/ipu.h>
@@ -354,10 +355,12 @@ static struct irq_chip ipu_irq_chip = {
/* Install the IRQ handler */
int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
{
- struct ipu_platform_data *pdata = dev->dev.platform_data;
- unsigned int irq, irq_base, i;
+ unsigned int irq, i;
+ int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
+ numa_node_id());
- irq_base = pdata->irq_base;
+ if (irq_base < 0)
+ return irq_base;
for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
irq_bank[i].ipu = ipu;
@@ -387,15 +390,16 @@ int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
irq_set_handler_data(ipu->irq_err, ipu);
irq_set_chained_handler(ipu->irq_err, ipu_irq_err);
+ ipu->irq_base = irq_base;
+
return 0;
}
void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
{
- struct ipu_platform_data *pdata = dev->dev.platform_data;
unsigned int irq, irq_base;
- irq_base = pdata->irq_base;
+ irq_base = ipu->irq_base;
irq_set_chained_handler(ipu->irq_fn, NULL);
irq_set_handler_data(ipu->irq_fn, NULL);
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 07/16] dma: ipu: remove the use of ipu_platform_data
2012-06-14 5:59 ` [PATCH 07/16] dma: ipu: remove the use of ipu_platform_data Shawn Guo
@ 2012-06-14 10:26 ` Vinod Koul
2012-06-15 9:37 ` Dong Aisheng
1 sibling, 0 replies; 85+ messages in thread
From: Vinod Koul @ 2012-06-14 10:26 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2012-06-14 at 13:59 +0800, Shawn Guo wrote:
> The struct ipu_platform_data is used by platform code to pass
> MXC_IPU_IRQ_START to ipu-core driver. We can save it by having
> ipu-core driver call irq_alloc_descs to get the irq_base.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: Vinod Koul <vinod.koul@intel.com>
> ---
> arch/arm/mach-imx/devices-imx31.h | 4 ++--
> arch/arm/mach-imx/devices-imx35.h | 4 ++--
> arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c | 6 +-----
> arch/arm/mach-imx/mach-armadillo5x0.c | 6 +-----
> arch/arm/mach-imx/mach-mx31_3ds.c | 6 +-----
> arch/arm/mach-imx/mach-mx31moboard.c | 6 +-----
> arch/arm/mach-imx/mach-mx35_3ds.c | 10 +---------
> arch/arm/mach-imx/mach-pcm037.c | 6 +-----
> arch/arm/mach-imx/mach-pcm043.c | 6 +-----
> arch/arm/mach-imx/mach-vpr200.c | 6 +-----
> arch/arm/mach-imx/mx31lilly-db.c | 6 +-----
> arch/arm/plat-mxc/devices/platform-ipu-core.c | 5 ++---
> arch/arm/plat-mxc/include/mach/devices-common.h | 4 +---
> arch/arm/plat-mxc/include/mach/ipu.h | 4 ----
> drivers/dma/ipu/ipu_idmac.c | 8 +++-----
> drivers/dma/ipu/ipu_irq.c | 14 +++++++++-----
for drivers/dma/ipu*
Acked by: Vinod Koul <vinod.koul@linux.intel.com>
> 16 files changed, 28 insertions(+), 73 deletions(-)
>
> diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
> index 488e241..911c2da 100644
> --- a/arch/arm/mach-imx/devices-imx31.h
> +++ b/arch/arm/mach-imx/devices-imx31.h
> @@ -42,8 +42,8 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
> #define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
>
> extern const struct imx_ipu_core_data imx31_ipu_core_data;
> -#define imx31_add_ipu_core(pdata) \
> - imx_add_ipu_core(&imx31_ipu_core_data, pdata)
> +#define imx31_add_ipu_core() \
> + imx_add_ipu_core(&imx31_ipu_core_data)
> #define imx31_alloc_mx3_camera(pdata) \
> imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
> #define imx31_add_mx3_sdc_fb(pdata) \
> diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
> index 7b99ef0..6fb9072 100644
> --- a/arch/arm/mach-imx/devices-imx35.h
> +++ b/arch/arm/mach-imx/devices-imx35.h
> @@ -50,8 +50,8 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
> #define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
>
> extern const struct imx_ipu_core_data imx35_ipu_core_data;
> -#define imx35_add_ipu_core(pdata) \
> - imx_add_ipu_core(&imx35_ipu_core_data, pdata)
> +#define imx35_add_ipu_core() \
> + imx_add_ipu_core(&imx35_ipu_core_data)
> #define imx35_alloc_mx3_camera(pdata) \
> imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
> #define imx35_add_mx3_sdc_fb(pdata) \
> diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
> index 557f6c4..6e9dd12 100644
> --- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
> +++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
> @@ -95,10 +95,6 @@ static const struct fb_videomode fb_modedb[] = {
> },
> };
>
> -static const struct ipu_platform_data mx3_ipu_data __initconst = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static struct mx3fb_platform_data mx3fb_pdata __initdata = {
> .name = "CMO-QVGA",
> .mode = fb_modedb,
> @@ -287,7 +283,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
> printk(KERN_ERR "error setting mbimxsd pads !\n");
>
> imx35_add_imx_uart1(&uart_pdata);
> - imx35_add_ipu_core(&mx3_ipu_data);
> + imx35_add_ipu_core();
> imx35_add_mx3_sdc_fb(&mx3fb_pdata);
>
> imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
> diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
> index f83c5c6..2c6ab32 100644
> --- a/arch/arm/mach-imx/mach-armadillo5x0.c
> +++ b/arch/arm/mach-imx/mach-armadillo5x0.c
> @@ -367,10 +367,6 @@ static const struct fb_videomode fb_modedb[] = {
> },
> };
>
> -static const struct ipu_platform_data mx3_ipu_data __initconst = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static struct mx3fb_platform_data mx3fb_pdata __initdata = {
> .name = "CRT-VGA",
> .mode = fb_modedb,
> @@ -517,7 +513,7 @@ static void __init armadillo5x0_init(void)
> imx31_add_mxc_mmc(0, &sdhc_pdata);
>
> /* Register FB */
> - imx31_add_ipu_core(&mx3_ipu_data);
> + imx31_add_ipu_core();
> imx31_add_mx3_sdc_fb(&mx3fb_pdata);
>
> /* Register NOR Flash */
> diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
> index ecdba04..618935e 100644
> --- a/arch/arm/mach-imx/mach-mx31_3ds.c
> +++ b/arch/arm/mach-imx/mach-mx31_3ds.c
> @@ -274,10 +274,6 @@ static const struct fb_videomode fb_modedb[] = {
> },
> };
>
> -static struct ipu_platform_data mx3_ipu_data = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static struct mx3fb_platform_data mx3fb_pdata __initdata = {
> .name = "Epson-VGA",
> .mode = fb_modedb,
> @@ -743,7 +739,7 @@ static void __init mx31_3ds_init(void)
> imx31_add_mxc_mmc(0, &sdhc1_pdata);
>
> imx31_add_spi_imx0(&spi0_pdata);
> - imx31_add_ipu_core(&mx3_ipu_data);
> + imx31_add_ipu_core();
> imx31_add_mx3_sdc_fb(&mx3fb_pdata);
>
> /* CSI */
> diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
> index f0d26db..54d9e5d 100644
> --- a/arch/arm/mach-imx/mach-mx31moboard.c
> +++ b/arch/arm/mach-imx/mach-mx31moboard.c
> @@ -473,10 +473,6 @@ static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = {
> .leds = mx31moboard_leds,
> };
>
> -static const struct ipu_platform_data mx3_ipu_data __initconst = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static struct platform_device *devices[] __initdata = {
> &mx31moboard_flash,
> };
> @@ -494,7 +490,7 @@ static int __init mx31moboard_init_cam(void)
> int dma, ret = -ENOMEM;
> struct platform_device *pdev;
>
> - imx31_add_ipu_core(&mx3_ipu_data);
> + imx31_add_ipu_core();
>
> pdev = imx31_alloc_mx3_camera(&camera_pdata);
> if (IS_ERR(pdev))
> diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
> index fa1ea74..ad63e6e 100644
> --- a/arch/arm/mach-imx/mach-mx35_3ds.c
> +++ b/arch/arm/mach-imx/mach-mx35_3ds.c
> @@ -80,10 +80,6 @@ static const struct fb_videomode fb_modedb[] = {
> },
> };
>
> -static const struct ipu_platform_data mx3_ipu_data __initconst = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static struct mx3fb_platform_data mx3fb_pdata __initdata = {
> .name = "Ceramate-CLAA070VC01",
> .mode = fb_modedb,
> @@ -297,10 +293,6 @@ err:
> return ret;
> }
>
> -static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static struct i2c_board_info mx35_3ds_i2c_camera = {
> I2C_BOARD_INFO("ov2640", 0x30),
> };
> @@ -596,7 +588,7 @@ static void __init mx35_3ds_init(void)
> i2c_register_board_info(
> 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
>
> - imx35_add_ipu_core(&mx35_3ds_ipu_data);
> + imx35_add_ipu_core();
> platform_device_register(&mx35_3ds_ov2640);
> imx35_3ds_init_camera();
>
> diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
> index 551a035..ded4ed9 100644
> --- a/arch/arm/mach-imx/mach-pcm037.c
> +++ b/arch/arm/mach-imx/mach-pcm037.c
> @@ -441,10 +441,6 @@ static struct platform_device *devices[] __initdata = {
> &pcm037_mt9v022,
> };
>
> -static const struct ipu_platform_data mx3_ipu_data __initconst = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static const struct fb_videomode fb_modedb[] = {
> {
> /* 240x320 @ 60 Hz Sharp */
> @@ -648,7 +644,7 @@ static void __init pcm037_init(void)
>
> imx31_add_mxc_nand(&pcm037_nand_board_info);
> imx31_add_mxc_mmc(0, &sdhc_pdata);
> - imx31_add_ipu_core(&mx3_ipu_data);
> + imx31_add_ipu_core();
> imx31_add_mx3_sdc_fb(&mx3fb_pdata);
>
> /* CSI */
> diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
> index 73585f5..133908f 100644
> --- a/arch/arm/mach-imx/mach-pcm043.c
> +++ b/arch/arm/mach-imx/mach-pcm043.c
> @@ -76,10 +76,6 @@ static const struct fb_videomode fb_modedb[] = {
> },
> };
>
> -static const struct ipu_platform_data mx3_ipu_data __initconst = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static struct mx3fb_platform_data mx3fb_pdata __initdata = {
> .name = "Sharp-LQ035Q7",
> .mode = fb_modedb,
> @@ -376,7 +372,7 @@ static void __init pcm043_init(void)
>
> imx35_add_imx_i2c0(&pcm043_i2c0_data);
>
> - imx35_add_ipu_core(&mx3_ipu_data);
> + imx35_add_ipu_core();
> imx35_add_mx3_sdc_fb(&mx3fb_pdata);
>
> if (otg_mode_host) {
> diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
> index e36eb2c..1aa5622 100644
> --- a/arch/arm/mach-imx/mach-vpr200.c
> +++ b/arch/arm/mach-imx/mach-vpr200.c
> @@ -87,10 +87,6 @@ static const struct fb_videomode fb_modedb[] = {
> }
> };
>
> -static const struct ipu_platform_data mx3_ipu_data __initconst = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static struct mx3fb_platform_data mx3fb_pdata __initdata = {
> .name = "PT0708048",
> .mode = fb_modedb,
> @@ -290,7 +286,7 @@ static void __init vpr200_board_init(void)
> imx35_add_imx_uart0(NULL);
> imx35_add_imx_uart2(NULL);
>
> - imx35_add_ipu_core(&mx3_ipu_data);
> + imx35_add_ipu_core();
> imx35_add_mx3_sdc_fb(&mx3fb_pdata);
>
> imx35_add_fsl_usb2_udc(&otg_device_pdata);
> diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
> index 2df625b..29e890f 100644
> --- a/arch/arm/mach-imx/mx31lilly-db.c
> +++ b/arch/arm/mach-imx/mx31lilly-db.c
> @@ -162,10 +162,6 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = {
> };
>
> /* Framebuffer support */
> -static const struct ipu_platform_data ipu_data __initconst = {
> - .irq_base = MXC_IPU_IRQ_START,
> -};
> -
> static const struct fb_videomode fb_modedb = {
> /* 640x480 TFT panel (IPS-056T) */
> .name = "CRT-VGA",
> @@ -199,7 +195,7 @@ static void __init mx31lilly_init_fb(void)
> return;
> }
>
> - imx31_add_ipu_core(&ipu_data);
> + imx31_add_ipu_core();
> imx31_add_mx3_sdc_fb(&fb_pdata);
> gpio_direction_output(LCD_VCC_EN_GPIO, 1);
> }
> diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c
> index 79d340a..d1e33cc 100644
> --- a/arch/arm/plat-mxc/devices/platform-ipu-core.c
> +++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c
> @@ -30,8 +30,7 @@ const struct imx_ipu_core_data imx35_ipu_core_data __initconst =
> static struct platform_device *imx_ipu_coredev __initdata;
>
> struct platform_device *__init imx_add_ipu_core(
> - const struct imx_ipu_core_data *data,
> - const struct ipu_platform_data *pdata)
> + const struct imx_ipu_core_data *data)
> {
> /* The resource order is important! */
> struct resource res[] = {
> @@ -55,7 +54,7 @@ struct platform_device *__init imx_add_ipu_core(
> };
>
> return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1,
> - res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
> + res, ARRAY_SIZE(res), NULL, 0);
> }
>
> struct platform_device *__init imx_alloc_mx3_camera(
> diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
> index 1b2258d..a7f5bb1 100644
> --- a/arch/arm/plat-mxc/include/mach/devices-common.h
> +++ b/arch/arm/plat-mxc/include/mach/devices-common.h
> @@ -183,7 +183,6 @@ struct platform_device *__init imx_add_imx_udc(
> const struct imx_imx_udc_data *data,
> const struct imxusb_platform_data *pdata);
>
> -#include <mach/ipu.h>
> #include <mach/mx3fb.h>
> #include <mach/mx3_camera.h>
> struct imx_ipu_core_data {
> @@ -192,8 +191,7 @@ struct imx_ipu_core_data {
> resource_size_t errirq;
> };
> struct platform_device *__init imx_add_ipu_core(
> - const struct imx_ipu_core_data *data,
> - const struct ipu_platform_data *pdata);
> + const struct imx_ipu_core_data *data);
> struct platform_device *__init imx_alloc_mx3_camera(
> const struct imx_ipu_core_data *data,
> const struct mx3_camera_pdata *pdata);
> diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h
> index a9221f1..539e559 100644
> --- a/arch/arm/plat-mxc/include/mach/ipu.h
> +++ b/arch/arm/plat-mxc/include/mach/ipu.h
> @@ -110,10 +110,6 @@ enum ipu_rotate_mode {
> IPU_ROTATE_90_LEFT = 7,
> };
>
> -struct ipu_platform_data {
> - unsigned int irq_base;
> -};
> -
> /*
> * Enumeration of DI ports for ADC.
> */
> diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
> index 5ec7204..c7573e5 100644
> --- a/drivers/dma/ipu/ipu_idmac.c
> +++ b/drivers/dma/ipu/ipu_idmac.c
> @@ -1663,7 +1663,6 @@ static void __exit ipu_idmac_exit(struct ipu *ipu)
>
> static int __init ipu_probe(struct platform_device *pdev)
> {
> - struct ipu_platform_data *pdata = pdev->dev.platform_data;
> struct resource *mem_ipu, *mem_ic;
> int ret;
>
> @@ -1671,7 +1670,7 @@ static int __init ipu_probe(struct platform_device *pdev)
>
> mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> - if (!pdata || !mem_ipu || !mem_ic)
> + if (!mem_ipu || !mem_ic)
> return -EINVAL;
>
> ipu_data.dev = &pdev->dev;
> @@ -1688,10 +1687,9 @@ static int __init ipu_probe(struct platform_device *pdev)
> goto err_noirq;
>
> ipu_data.irq_err = ret;
> - ipu_data.irq_base = pdata->irq_base;
>
> - dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
> - ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
> + dev_dbg(&pdev->dev, "fn irq %u, err irq %u\n",
> + ipu_data.irq_fn, ipu_data.irq_err);
>
> /* Remap IPU common registers */
> ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));
> diff --git a/drivers/dma/ipu/ipu_irq.c b/drivers/dma/ipu/ipu_irq.c
> index a71f55e..fa95bcc 100644
> --- a/drivers/dma/ipu/ipu_irq.c
> +++ b/drivers/dma/ipu/ipu_irq.c
> @@ -14,6 +14,7 @@
> #include <linux/clk.h>
> #include <linux/irq.h>
> #include <linux/io.h>
> +#include <linux/module.h>
>
> #include <mach/ipu.h>
>
> @@ -354,10 +355,12 @@ static struct irq_chip ipu_irq_chip = {
> /* Install the IRQ handler */
> int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
> {
> - struct ipu_platform_data *pdata = dev->dev.platform_data;
> - unsigned int irq, irq_base, i;
> + unsigned int irq, i;
> + int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
> + numa_node_id());
>
> - irq_base = pdata->irq_base;
> + if (irq_base < 0)
> + return irq_base;
>
> for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
> irq_bank[i].ipu = ipu;
> @@ -387,15 +390,16 @@ int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
> irq_set_handler_data(ipu->irq_err, ipu);
> irq_set_chained_handler(ipu->irq_err, ipu_irq_err);
>
> + ipu->irq_base = irq_base;
> +
> return 0;
> }
>
> void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
> {
> - struct ipu_platform_data *pdata = dev->dev.platform_data;
> unsigned int irq, irq_base;
>
> - irq_base = pdata->irq_base;
> + irq_base = ipu->irq_base;
>
> irq_set_chained_handler(ipu->irq_fn, NULL);
> irq_set_handler_data(ipu->irq_fn, NULL);
--
~Vinod
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 07/16] dma: ipu: remove the use of ipu_platform_data
2012-06-14 5:59 ` [PATCH 07/16] dma: ipu: remove the use of ipu_platform_data Shawn Guo
2012-06-14 10:26 ` Vinod Koul
@ 2012-06-15 9:37 ` Dong Aisheng
2012-06-16 3:01 ` Shawn Guo
1 sibling, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-15 9:37 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:38PM +0800, Shawn Guo wrote:
.......
> @@ -354,10 +355,12 @@ static struct irq_chip ipu_irq_chip = {
> /* Install the IRQ handler */
> int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
> {
> - struct ipu_platform_data *pdata = dev->dev.platform_data;
> - unsigned int irq, irq_base, i;
> + unsigned int irq, i;
> + int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
> + numa_node_id());
>
> - irq_base = pdata->irq_base;
> + if (irq_base < 0)
> + return irq_base;
>
Need not add irqdomain for this irq range?
Can we still service this irq properly without irqdomain mapping?
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 07/16] dma: ipu: remove the use of ipu_platform_data
2012-06-15 9:37 ` Dong Aisheng
@ 2012-06-16 3:01 ` Shawn Guo
2012-06-18 8:19 ` Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-16 3:01 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jun 15, 2012 at 05:37:14PM +0800, Dong Aisheng wrote:
> On Thu, Jun 14, 2012 at 01:59:38PM +0800, Shawn Guo wrote:
> .......
> > @@ -354,10 +355,12 @@ static struct irq_chip ipu_irq_chip = {
> > /* Install the IRQ handler */
> > int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
> > {
> > - struct ipu_platform_data *pdata = dev->dev.platform_data;
> > - unsigned int irq, irq_base, i;
> > + unsigned int irq, i;
> > + int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
> > + numa_node_id());
> >
> > - irq_base = pdata->irq_base;
> > + if (irq_base < 0)
> > + return irq_base;
> >
> Need not add irqdomain for this irq range?
> Can we still service this irq properly without irqdomain mapping?
>
Yes, I think it should still work, because the driver has the mapping
management on its own, though someday we need to replace its own
mapping with irqdomain anyway when we move the driver to device tree.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 07/16] dma: ipu: remove the use of ipu_platform_data
2012-06-16 3:01 ` Shawn Guo
@ 2012-06-18 8:19 ` Dong Aisheng
2012-06-18 14:02 ` Shawn Guo
0 siblings, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-18 8:19 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Jun 16, 2012 at 11:01:08AM +0800, Shawn Guo wrote:
> On Fri, Jun 15, 2012 at 05:37:14PM +0800, Dong Aisheng wrote:
> > On Thu, Jun 14, 2012 at 01:59:38PM +0800, Shawn Guo wrote:
> > .......
> > > @@ -354,10 +355,12 @@ static struct irq_chip ipu_irq_chip = {
> > > /* Install the IRQ handler */
> > > int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
> > > {
> > > - struct ipu_platform_data *pdata = dev->dev.platform_data;
> > > - unsigned int irq, irq_base, i;
> > > + unsigned int irq, i;
> > > + int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
> > > + numa_node_id());
> > >
> > > - irq_base = pdata->irq_base;
> > > + if (irq_base < 0)
> > > + return irq_base;
> > >
> > Need not add irqdomain for this irq range?
> > Can we still service this irq properly without irqdomain mapping?
> >
> Yes, I think it should still work, because the driver has the mapping
> management on its own, though someday we need to replace its own
> mapping with irqdomain anyway when we move the driver to device tree.
>
Hmm, i'm wondering it may not make too much sense to alloc_descs without
using irqdomain since the allocated irqs are all virtual irqs.
Using private mapping is not recommended.
Maybe we can do it together with this patch since irqdomain support
does not depend on device tree.
What do you think?
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 07/16] dma: ipu: remove the use of ipu_platform_data
2012-06-18 8:19 ` Dong Aisheng
@ 2012-06-18 14:02 ` Shawn Guo
2012-06-19 5:51 ` Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-18 14:02 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jun 18, 2012 at 04:19:44PM +0800, Dong Aisheng wrote:
> Hmm, i'm wondering it may not make too much sense to alloc_descs without
> using irqdomain since the allocated irqs are all virtual irqs.
It still makes much sense, because we are killing all those static
IRQ_START definitions here, so we need to get irq_base by calling
alloc_descs anyway.
> Using private mapping is not recommended.
> Maybe we can do it together with this patch since irqdomain support
> does not depend on device tree.
> What do you think?
>
At this point, I would be conservative on that, since I do not have
the setup to test all the IPU irq handling.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 07/16] dma: ipu: remove the use of ipu_platform_data
2012-06-18 14:02 ` Shawn Guo
@ 2012-06-19 5:51 ` Dong Aisheng
0 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-19 5:51 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jun 18, 2012 at 10:02:23PM +0800, Shawn Guo wrote:
> On Mon, Jun 18, 2012 at 04:19:44PM +0800, Dong Aisheng wrote:
...
> > Using private mapping is not recommended.
> > Maybe we can do it together with this patch since irqdomain support
> > does not depend on device tree.
> > What do you think?
> >
> At this point, I would be conservative on that, since I do not have
> the setup to test all the IPU irq handling.
>
I looked into the code a bit more, it seems ipu uses its own special irq mapping
between virt irq and hw/dma_chan irq itself and the mapping is dynamically
and limited to how many CONFIG_MX3_IPU_IRQS defined.
No sure it's so suitable to convert to irqdomain.
With adding irqdomain, i wonder we may need change this mechanism a bit.
For now, i'm ok to put that work in another patch later and using the original
way first since the later patch may need to do more things, so
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 08/16] ARM: imx: leave irq_base of wm8350_platform_data uninitialized
2012-06-14 5:59 ` Shawn Guo
` (7 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-15 12:20 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
With commit d1738ae (mfd: Allocate wm835x irq descs dynamically) being
in the tree, there is no need to initialize irq_base field of struct
wm8350_platform_data. Remove it to save one reference to macro
MXC_BOARD_IRQ_START.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/mach-mx31ads.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 6f19f98..a27a854 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -479,7 +479,6 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
.init = mx31_wm8350_init,
- .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
};
#endif
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 09/16] ARM: imx: pass gpio than irq number into mxc_expio_init
2012-06-14 5:59 ` Shawn Guo
` (8 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-15 12:21 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Change mxc_expio_init interface a little bit to have gpio than irq
number passed in. With the change, gpio_to_irq can be called inside
mxc_expio_init to get irq number, so that MXC_IRQ_TO_GPIO can be
removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/mach-mx27_3ds.c | 3 +--
arch/arm/mach-imx/mach-mx31_3ds.c | 3 +--
arch/arm/mach-imx/mach-mx35_3ds.c | 4 +---
arch/arm/mach-imx/mach-mx51_3ds.c | 3 +--
arch/arm/plat-mxc/3ds_debugboard.c | 8 ++++----
arch/arm/plat-mxc/include/mach/3ds_debugboard.h | 2 +-
6 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 18b9bca..eeff0b6 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -48,7 +48,6 @@
#define SD1_EN_GPIO IMX_GPIO_NR(2, 25)
#define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23)
#define SPI2_SS0 IMX_GPIO_NR(4, 21)
-#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28))
#define PMIC_INT IMX_GPIO_NR(3, 14)
#define SPI1_SS0 IMX_GPIO_NR(4, 28)
#define SD1_CD IMX_GPIO_NR(2, 26)
@@ -500,7 +499,7 @@ static void __init mx27pdk_init(void)
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
- if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+ if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 618935e..f37d9b5 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -730,8 +730,7 @@ static void __init mx31_3ds_init(void)
if (!otg_mode_host)
imx31_add_fsl_usb2_udc(&usbotg_pdata);
- if (mxc_expio_init(MX31_CS5_BASE_ADDR,
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1))))
+ if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)))
printk(KERN_WARNING "Init of the debug board failed, all "
"devices on the debug board are unusable.\n");
imx31_add_imx2_wdt(NULL);
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index ad63e6e..596f237 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -132,8 +132,6 @@ static struct platform_device mx35_3ds_lcd = {
.dev.platform_data = &mx35_3ds_lcd_data,
};
-#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 1))
-
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
@@ -580,7 +578,7 @@ static void __init mx35_3ds_init(void)
imx35_add_mxc_nand(&mx35pdk_nand_board_info);
imx35_add_sdhci_esdhc_imx(0, NULL);
- if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+ if (mxc_expio_init(MX35_CS5_BASE_ADDR, IMX_GPIO_NR(1, 1)))
pr_warn("Init of the debugboard failed, all "
"devices on the debugboard are unusable.\n");
imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
index 3c5b163..ebb9188 100644
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ b/arch/arm/mach-imx/mach-mx51_3ds.c
@@ -26,7 +26,6 @@
#include "devices-imx51.h"
-#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6))
#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
static iomux_v3_cfg_t mx51_3ds_pads[] = {
@@ -148,7 +147,7 @@ static void __init mx51_3ds_init(void)
spi_register_board_info(mx51_3ds_spi_nor_device,
ARRAY_SIZE(mx51_3ds_spi_nor_device));
- if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+ if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6)))
printk(KERN_WARNING "Init of the debugboard failed, all "
"devices on the board are unusable.\n");
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index 5cac2c5..3b48a08 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -49,7 +49,6 @@
#define MCU_BOARD_ID_REG 0x68
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_INTERNAL_IRQS)
#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_MAX_EXP_IO_LINES 16
@@ -155,8 +154,9 @@ static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x"),
};
-int __init mxc_expio_init(u32 base, u32 p_irq)
+int __init mxc_expio_init(u32 base, u32 intr_gpio)
{
+ u32 p_irq = gpio_to_irq(intr_gpio);
int i;
brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
@@ -178,8 +178,8 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
/*
* Configure INT line as GPIO input
*/
- gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
- gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+ gpio_request(intr_gpio, "expio_pirq");
+ gpio_direction_input(intr_gpio);
/* disable the interrupt and clear the status */
__raw_writew(0, brd_io + INTR_MASK_REG);
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
index a384fdd..9fd6cb3 100644
--- a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -13,6 +13,6 @@
#ifndef __ASM_ARCH_MXC_3DS_DB_H__
#define __ASM_ARCH_MXC_3DS_DB_H__
-extern int __init mxc_expio_init(u32 base, u32 p_irq);
+extern int __init mxc_expio_init(u32 base, u32 intr_gpio);
#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 10/16] ARM: imx: add a legacy irqdomain for 3ds_debugboard
2012-06-14 5:59 ` Shawn Guo
` (9 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-15 12:22 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Call irq_alloc_descs to get the irq_base for 3ds_debugboard, and add
a legacy irqdomain using the irq_base, so that the mapping between
3ds_debugboard hardware irq and Linux irq number can be dynamically
handled by irqdomain. As the result, the use of MXC_BOARD_IRQ_START
can be completely removed from 3ds_debugboard.c.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/plat-mxc/3ds_debugboard.c | 42 +++++++++++++++++++++--------------
1 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index 3b48a08..5c10ad0 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -12,9 +12,11 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
+#include <linux/module.h>
#include <linux/smsc911x.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
@@ -48,26 +50,22 @@
/* CPU ID and Personality ID */
#define MCU_BOARD_ID_REG 0x68
-#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_BOARD_IRQ_START)
-
-#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_MAX_EXP_IO_LINES 16
/* interrupts like external uart , external ethernet etc*/
-#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0)
-#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1)
-#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2)
-#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3)
-#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4)
+#define EXPIO_INT_ENET 0
+#define EXPIO_INT_XUART_A 1
+#define EXPIO_INT_XUART_B 2
+#define EXPIO_INT_BUTTON_A 3
+#define EXPIO_INT_BUTTON_B 4
static void __iomem *brd_io;
+static struct irq_domain *domain;
static struct resource smsc911x_resources[] = {
{
.flags = IORESOURCE_MEM,
} , {
- .start = EXPIO_INT_ENET,
- .end = EXPIO_INT_ENET,
.flags = IORESOURCE_IRQ,
},
};
@@ -99,11 +97,11 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
imr_val = __raw_readw(brd_io + INTR_MASK_REG);
int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
- expio_irq = MXC_BOARD_IRQ_START;
+ expio_irq = 0;
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
if ((int_valid & 1) == 0)
continue;
- generic_handle_irq(expio_irq);
+ generic_handle_irq(irq_find_mapping(domain, expio_irq));
}
desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -117,7 +115,7 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
static void expio_mask_irq(struct irq_data *d)
{
u16 reg;
- u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+ u32 expio = d->hwirq;
reg = __raw_readw(brd_io + INTR_MASK_REG);
reg |= (1 << expio);
@@ -126,7 +124,7 @@ static void expio_mask_irq(struct irq_data *d)
static void expio_ack_irq(struct irq_data *d)
{
- u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+ u32 expio = d->hwirq;
__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
__raw_writew(0, brd_io + INTR_RESET_REG);
@@ -136,7 +134,7 @@ static void expio_ack_irq(struct irq_data *d)
static void expio_unmask_irq(struct irq_data *d)
{
u16 reg;
- u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+ u32 expio = d->hwirq;
reg = __raw_readw(brd_io + INTR_MASK_REG);
reg &= ~(1 << expio);
@@ -157,6 +155,7 @@ static struct regulator_consumer_supply dummy_supplies[] = {
int __init mxc_expio_init(u32 base, u32 intr_gpio)
{
u32 p_irq = gpio_to_irq(intr_gpio);
+ int irq_base;
int i;
brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
@@ -186,8 +185,15 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio)
__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
__raw_writew(0, brd_io + INTR_RESET_REG);
__raw_writew(0x1F, brd_io + INTR_MASK_REG);
- for (i = MXC_EXP_IO_BASE;
- i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+
+ irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
+ WARN_ON(irq_base < 0);
+
+ domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
+ &irq_domain_simple_ops, NULL);
+ WARN_ON(!domain);
+
+ for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
@@ -199,6 +205,8 @@ int __init mxc_expio_init(u32 base, u32 intr_gpio)
smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+ smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET);
+ smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET);
platform_device_register(&smsc_lan9217_device);
return 0;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 10/16] ARM: imx: add a legacy irqdomain for 3ds_debugboard
2012-06-14 5:59 ` [PATCH 10/16] ARM: imx: add a legacy irqdomain for 3ds_debugboard Shawn Guo
@ 2012-06-15 12:22 ` Dong Aisheng
0 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-15 12:22 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:41PM +0800, Shawn Guo wrote:
> Call irq_alloc_descs to get the irq_base for 3ds_debugboard, and add
> a legacy irqdomain using the irq_base, so that the mapping between
> 3ds_debugboard hardware irq and Linux irq number can be dynamically
> handled by irqdomain. As the result, the use of MXC_BOARD_IRQ_START
> can be completely removed from 3ds_debugboard.c.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> arch/arm/plat-mxc/3ds_debugboard.c | 42 +++++++++++++++++++++--------------
> 1 files changed, 25 insertions(+), 17 deletions(-)
>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 11/16] ARM: imx: add a legacy irqdomain for mx31ads
2012-06-14 5:59 ` Shawn Guo
` (10 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-18 8:20 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Call irq_alloc_descs to get the irq_base for mx31ads, and add a legacy
irqdomain using the irq_base, so that the mapping between mx31ads
hardware irq and Linux irq number can be dynamically handled by
irqdomain. As the result, the use of MXC_BOARD_IRQ_START can be
completely removed from mach-mx31ads.c.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/mach-mx31ads.c | 48 ++++++++++++++++++++++++-------------
1 files changed, 31 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index a27a854..d37f480 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -21,6 +21,7 @@
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/irq.h>
+#include <linux/irqdomain.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -63,18 +64,17 @@
#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-#define MXC_EXP_IO_BASE MXC_BOARD_IRQ_START
-#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_XUART_INTA 10
+#define EXPIO_INT_XUART_INTB 11
#define MXC_MAX_EXP_IO_LINES 16
/* CS8900 */
-#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_ENET_INT 8
#define CS4_CS8900_MMIO_START 0x20000
+static struct irq_domain *domain;
+
/*
* The serial port definition structure.
*/
@@ -82,7 +82,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
- .irq = EXPIO_INT_XUART_INTA,
.uartclk = 14745600,
.regshift = 0,
.iotype = UPIO_MEM,
@@ -90,7 +89,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
}, {
.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
- .irq = EXPIO_INT_XUART_INTB,
.uartclk = 14745600,
.regshift = 0,
.iotype = UPIO_MEM,
@@ -107,9 +105,9 @@ static struct platform_device serial_device = {
},
};
-static const struct resource mx31ads_cs8900_resources[] __initconst = {
+static struct resource mx31ads_cs8900_resources[] __initdata = {
DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
- DEFINE_RES_IRQ(EXPIO_INT_ENET_INT),
+ DEFINE_RES_IRQ(-1),
};
static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
@@ -121,11 +119,19 @@ static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
static int __init mxc_init_extuart(void)
{
+ serial_platform_data[0].irq = irq_find_mapping(domain,
+ EXPIO_INT_XUART_INTA);
+ serial_platform_data[1].irq = irq_find_mapping(domain,
+ EXPIO_INT_XUART_INTB);
return platform_device_register(&serial_device);
}
static void __init mxc_init_ext_ethernet(void)
{
+ mx31ads_cs8900_resources[1].start =
+ irq_find_mapping(domain, EXPIO_INT_ENET_INT);
+ mx31ads_cs8900_resources[1].end =
+ irq_find_mapping(domain, EXPIO_INT_ENET_INT);
platform_device_register_full(
(struct platform_device_info *)&mx31ads_cs8900_devinfo);
}
@@ -156,12 +162,12 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
imr_val = __raw_readw(PBC_INTMASK_SET_REG);
int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
- expio_irq = MXC_EXP_IO_BASE;
+ expio_irq = 0;
for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
if ((int_valid & 1) == 0)
continue;
- generic_handle_irq(expio_irq);
+ generic_handle_irq(irq_find_mapping(domain, expio_irq));
}
}
@@ -171,7 +177,7 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
*/
static void expio_mask_irq(struct irq_data *d)
{
- u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+ u32 expio = d->hwirq;
/* mask the interrupt */
__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
__raw_readw(PBC_INTMASK_CLEAR_REG);
@@ -183,7 +189,7 @@ static void expio_mask_irq(struct irq_data *d)
*/
static void expio_ack_irq(struct irq_data *d)
{
- u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+ u32 expio = d->hwirq;
/* clear the interrupt status */
__raw_writew(1 << expio, PBC_INTSTATUS_REG);
}
@@ -194,7 +200,7 @@ static void expio_ack_irq(struct irq_data *d)
*/
static void expio_unmask_irq(struct irq_data *d)
{
- u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+ u32 expio = d->hwirq;
/* unmask the interrupt */
__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
}
@@ -208,6 +214,7 @@ static struct irq_chip expio_irq_chip = {
static void __init mx31ads_init_expio(void)
{
+ int irq_base;
int i, irq;
printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
@@ -220,8 +227,15 @@ static void __init mx31ads_init_expio(void)
/* disable the interrupt and clear the status */
__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
- for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
- i++) {
+
+ irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
+ WARN_ON(irq_base < 0);
+
+ domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
+ &irq_domain_simple_ops, NULL);
+ WARN_ON(!domain);
+
+ for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 11/16] ARM: imx: add a legacy irqdomain for mx31ads
2012-06-14 5:59 ` [PATCH 11/16] ARM: imx: add a legacy irqdomain for mx31ads Shawn Guo
@ 2012-06-18 8:20 ` Dong Aisheng
0 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-18 8:20 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:42PM +0800, Shawn Guo wrote:
> Call irq_alloc_descs to get the irq_base for mx31ads, and add a legacy
> irqdomain using the irq_base, so that the mapping between mx31ads
> hardware irq and Linux irq number can be dynamically handled by
> irqdomain. As the result, the use of MXC_BOARD_IRQ_START can be
> completely removed from mach-mx31ads.c.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> arch/arm/mach-imx/mach-mx31ads.c | 48 ++++++++++++++++++++++++-------------
> 1 files changed, 31 insertions(+), 17 deletions(-)
>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <1339653587-4832-1-git-send-email-shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>]
* [PATCH 12/16] i2c: imx: remove unneeded mach/irqs.h inclusion
2012-06-14 5:59 ` Shawn Guo
@ 2012-06-14 5:59 ` Shawn Guo
-1 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Sascha Hauer, Arnd Bergmann, Rob Herring, Grant Likely,
Dong Aisheng, Shawn Guo, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
Wolfram Sang
Remove unneeded mach/irq.h inclusion from i2c-imx driver.
Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Wolfram Sang <w.sang-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
drivers/i2c/busses/i2c-imx.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 8d6b504..370031a 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -53,7 +53,6 @@
#include <linux/of_i2c.h>
#include <linux/pinctrl/consumer.h>
-#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/i2c.h>
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH 12/16] i2c: imx: remove unneeded mach/irqs.h inclusion
@ 2012-06-14 5:59 ` Shawn Guo
0 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Remove unneeded mach/irq.h inclusion from i2c-imx driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: linux-i2c at vger.kernel.org
Cc: Wolfram Sang <w.sang@pengutronix.de>
---
drivers/i2c/busses/i2c-imx.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 8d6b504..370031a 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -53,7 +53,6 @@
#include <linux/of_i2c.h>
#include <linux/pinctrl/consumer.h>
-#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/i2c.h>
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
[parent not found: <1339653587-4832-13-git-send-email-shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>]
* Re: [PATCH 12/16] i2c: imx: remove unneeded mach/irqs.h inclusion
2012-06-14 5:59 ` Shawn Guo
@ 2012-06-14 7:30 ` Wolfram Sang
-1 siblings, 0 replies; 85+ messages in thread
From: Wolfram Sang @ 2012-06-14 7:30 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sascha Hauer,
Arnd Bergmann, Rob Herring, Grant Likely, Dong Aisheng,
linux-i2c-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 576 bytes --]
On Thu, Jun 14, 2012 at 01:59:43PM +0800, Shawn Guo wrote:
> Remove unneeded mach/irq.h inclusion from i2c-imx driver.
>
> Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: Wolfram Sang <w.sang-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Acked-by: Wolfram Sang <w.sang-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Thanks!
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 12/16] i2c: imx: remove unneeded mach/irqs.h inclusion
2012-06-14 5:59 ` Shawn Guo
@ 2012-06-18 8:20 ` Dong Aisheng
-1 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-18 8:20 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sascha Hauer,
Arnd Bergmann, Rob Herring, Grant Likely, Dong Aisheng-B29396,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, Wolfram Sang
On Thu, Jun 14, 2012 at 01:59:43PM +0800, Shawn Guo wrote:
> Remove unneeded mach/irq.h inclusion from i2c-imx driver.
>
> Signed-off-by: Shawn Guo <shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: Wolfram Sang <w.sang-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> drivers/i2c/busses/i2c-imx.c | 1 -
> 1 files changed, 0 insertions(+), 1 deletions(-)
>
Acked-by: Dong Aisheng <dong.aisheng-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 12/16] i2c: imx: remove unneeded mach/irqs.h inclusion
@ 2012-06-18 8:20 ` Dong Aisheng
0 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-18 8:20 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:43PM +0800, Shawn Guo wrote:
> Remove unneeded mach/irq.h inclusion from i2c-imx driver.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: linux-i2c at vger.kernel.org
> Cc: Wolfram Sang <w.sang@pengutronix.de>
> ---
> drivers/i2c/busses/i2c-imx.c | 1 -
> 1 files changed, 0 insertions(+), 1 deletions(-)
>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 13/16] ARM: imx: remove unneeded mach/irq.h inclusion
2012-06-14 5:59 ` Shawn Guo
` (12 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-18 8:21 ` Dong Aisheng
-1 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Remove unneeded mach/irq.h inclusion from imx platform code.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/mach-apf9328.c | 1 -
arch/arm/mach-imx/mach-mx1ads.c | 1 -
arch/arm/mach-imx/mach-mx27_3ds.c | 1 -
arch/arm/mach-imx/mach-mx31lite.c | 1 -
arch/arm/mach-imx/mach-mx35_3ds.c | 1 -
arch/arm/mach-imx/mach-pca100.c | 1 -
arch/arm/mach-imx/mach-qong.c | 1 -
arch/arm/mach-imx/mach-scb9328.c | 1 -
arch/arm/mach-imx/mach-vpr200.c | 1 -
arch/arm/mach-imx/mm-imx1.c | 1 -
arch/arm/mach-imx/mm-imx21.c | 1 -
arch/arm/mach-imx/mm-imx25.c | 1 -
arch/arm/mach-imx/mm-imx27.c | 1 -
arch/arm/mach-imx/mm-imx3.c | 1 -
14 files changed, 0 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 5062fcb..7b99a79 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -27,7 +27,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/irqs.h>
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 7274e79..667f359 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -26,7 +26,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx1.h>
-#include <mach/irqs.h>
#include "devices-imx1.h"
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index eeff0b6..71f7c58 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -40,7 +40,6 @@
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/ulpi.h>
-#include <mach/irqs.h>
#include <mach/3ds_debugboard.h>
#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 4977378..c8785b3 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -43,7 +43,6 @@
#include <mach/common.h>
#include <mach/board-mx31lite.h>
#include <mach/iomux-mx3.h>
-#include <mach/irqs.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 596f237..e785254 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -46,7 +46,6 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
-#include <mach/irqs.h>
#include <mach/3ds_debugboard.h>
#include <video/platform_lcd.h>
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 8b1dfa2..d620a95 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,7 +36,6 @@
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <asm/mach/time.h>
-#include <mach/irqs.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index b6f11d2..39ceb8c 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -22,7 +22,6 @@
#include <linux/gpio.h>
#include <mach/hardware.h>
-#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 5001164..67ff38e 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -22,7 +22,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/irqs.h>
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 1aa5622..09864bb 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -31,7 +31,6 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
-#include <mach/irqs.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index fcafd3d..6d60d51 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -24,7 +24,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/irqs.h>
#include <mach/iomux-v1.h>
static struct map_desc imx_io_desc[] __initdata = {
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 5f43905..d056dad 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -26,7 +26,6 @@
#include <mach/devices-common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
-#include <mach/irqs.h>
#include <mach/iomux-v1.h>
/* MX21 memory map definition */
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 6ff3714..388928f 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -29,7 +29,6 @@
#include <mach/hardware.h>
#include <mach/mx25.h>
#include <mach/iomux-v3.h>
-#include <mach/irqs.h>
/*
* This table defines static virtual address mappings for I/O regions.
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 2566255..e7e24af 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -26,7 +26,6 @@
#include <mach/devices-common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
-#include <mach/irqs.h>
#include <mach/iomux-v1.h>
/* MX27 memory map definition */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 967ed5b..3ccd167 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -30,7 +30,6 @@
#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
-#include <mach/irqs.h>
#include "crmregs-imx3.h"
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 14/16] tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
2012-06-14 5:59 ` Shawn Guo
@ 2012-06-14 5:59 ` Shawn Guo
-1 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Sascha Hauer, Arnd Bergmann, Rob Herring, Grant Likely,
Dong Aisheng, Shawn Guo, linux-serial, Greg Kroah-Hartman
As the part of the effort to enable SPARE_IRQ for imx platform,
the macro MXC_INTERNAL_IRQS will be removed. The imx serial driver
has a references to it for a decision on flags of request_irq call
based on rtsirq is beyond MXC_INTERNAL_IRQS. However the searching
on imx platform code tells that rtsirq will never be beyond
MXC_INTERNAL_IRQS. That said, the check, consequently the reference
to MXC_INTERNAL_IRQS are not needed, so remove them.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: linux-serial@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/tty/serial/imx.c | 6 +-----
1 files changed, 1 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 4ef7473..d5c689d6 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -169,7 +169,6 @@
#define SERIAL_IMX_MAJOR 207
#define MINOR_START 16
#define DEV_NAME "ttymxc"
-#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
/*
* This determines how often we check the modem status signals
@@ -741,10 +740,7 @@ static int imx_startup(struct uart_port *port)
/* do not use RTS IRQ on IrDA */
if (!USE_IRDA(sport)) {
- retval = request_irq(sport->rtsirq, imx_rtsint,
- (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
- IRQF_TRIGGER_FALLING |
- IRQF_TRIGGER_RISING,
+ retval = request_irq(sport->rtsirq, imx_rtsint, 0,
DRIVER_NAME, sport);
if (retval)
goto error_out3;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 14/16] tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
@ 2012-06-14 5:59 ` Shawn Guo
0 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
As the part of the effort to enable SPARE_IRQ for imx platform,
the macro MXC_INTERNAL_IRQS will be removed. The imx serial driver
has a references to it for a decision on flags of request_irq call
based on rtsirq is beyond MXC_INTERNAL_IRQS. However the searching
on imx platform code tells that rtsirq will never be beyond
MXC_INTERNAL_IRQS. That said, the check, consequently the reference
to MXC_INTERNAL_IRQS are not needed, so remove them.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: linux-serial at vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/tty/serial/imx.c | 6 +-----
1 files changed, 1 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 4ef7473..d5c689d6 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -169,7 +169,6 @@
#define SERIAL_IMX_MAJOR 207
#define MINOR_START 16
#define DEV_NAME "ttymxc"
-#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
/*
* This determines how often we check the modem status signals
@@ -741,10 +740,7 @@ static int imx_startup(struct uart_port *port)
/* do not use RTS IRQ on IrDA */
if (!USE_IRDA(sport)) {
- retval = request_irq(sport->rtsirq, imx_rtsint,
- (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
- IRQF_TRIGGER_FALLING |
- IRQF_TRIGGER_RISING,
+ retval = request_irq(sport->rtsirq, imx_rtsint, 0,
DRIVER_NAME, sport);
if (retval)
goto error_out3;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* Re: [PATCH 14/16] tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
2012-06-14 5:59 ` Shawn Guo
@ 2012-06-14 15:37 ` Greg Kroah-Hartman
-1 siblings, 0 replies; 85+ messages in thread
From: Greg Kroah-Hartman @ 2012-06-14 15:37 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel, Sascha Hauer, Arnd Bergmann, Rob Herring,
Grant Likely, Dong Aisheng, linux-serial
On Thu, Jun 14, 2012 at 01:59:45PM +0800, Shawn Guo wrote:
> As the part of the effort to enable SPARE_IRQ for imx platform,
> the macro MXC_INTERNAL_IRQS will be removed. The imx serial driver
> has a references to it for a decision on flags of request_irq call
> based on rtsirq is beyond MXC_INTERNAL_IRQS. However the searching
> on imx platform code tells that rtsirq will never be beyond
> MXC_INTERNAL_IRQS. That said, the check, consequently the reference
> to MXC_INTERNAL_IRQS are not needed, so remove them.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: linux-serial@vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 14/16] tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
@ 2012-06-14 15:37 ` Greg Kroah-Hartman
0 siblings, 0 replies; 85+ messages in thread
From: Greg Kroah-Hartman @ 2012-06-14 15:37 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:45PM +0800, Shawn Guo wrote:
> As the part of the effort to enable SPARE_IRQ for imx platform,
> the macro MXC_INTERNAL_IRQS will be removed. The imx serial driver
> has a references to it for a decision on flags of request_irq call
> based on rtsirq is beyond MXC_INTERNAL_IRQS. However the searching
> on imx platform code tells that rtsirq will never be beyond
> MXC_INTERNAL_IRQS. That said, the check, consequently the reference
> to MXC_INTERNAL_IRQS are not needed, so remove them.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: linux-serial at vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 14/16] tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
2012-06-14 5:59 ` Shawn Guo
@ 2012-06-18 8:22 ` Dong Aisheng
-1 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-18 8:22 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel, Sascha Hauer, Arnd Bergmann, Rob Herring,
Grant Likely, Dong Aisheng-B29396, linux-serial,
Greg Kroah-Hartman
On Thu, Jun 14, 2012 at 01:59:45PM +0800, Shawn Guo wrote:
> As the part of the effort to enable SPARE_IRQ for imx platform,
> the macro MXC_INTERNAL_IRQS will be removed. The imx serial driver
> has a references to it for a decision on flags of request_irq call
> based on rtsirq is beyond MXC_INTERNAL_IRQS. However the searching
> on imx platform code tells that rtsirq will never be beyond
> MXC_INTERNAL_IRQS. That said, the check, consequently the reference
> to MXC_INTERNAL_IRQS are not needed, so remove them.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: linux-serial@vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 14/16] tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
@ 2012-06-18 8:22 ` Dong Aisheng
0 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-18 8:22 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:45PM +0800, Shawn Guo wrote:
> As the part of the effort to enable SPARE_IRQ for imx platform,
> the macro MXC_INTERNAL_IRQS will be removed. The imx serial driver
> has a references to it for a decision on flags of request_irq call
> based on rtsirq is beyond MXC_INTERNAL_IRQS. However the searching
> on imx platform code tells that rtsirq will never be beyond
> MXC_INTERNAL_IRQS. That said, the check, consequently the reference
> to MXC_INTERNAL_IRQS are not needed, so remove them.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: linux-serial at vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-14 5:59 ` Shawn Guo
` (14 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-18 8:39 ` Dong Aisheng
2012-06-18 14:31 ` Shawn Guo
-1 siblings, 2 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
The commit a2be01b (ARM: only include mach/irqs.h for !SPARSE_IRQ)
makes mach/irqs.h only be included for !SPARSE_IRQ build. There are
a nubmer of platforms have FIQ_START defined in mach/irqs.h.
arch/arm/mach-at91/include/mach/irqs.h:#define FIQ_START AT91_ID_FIQ
arch/arm/mach-rpc/include/mach/irqs.h:#define FIQ_START 64
arch/arm/mach-s3c24xx/include/mach/irqs.h:#define FIQ_START IRQ_EINT0
arch/arm/plat-mxc/include/mach/irqs.h:#define FIQ_START 0
arch/arm/plat-omap/include/plat/irqs.h:#define FIQ_START 1024
If SPARSE_IRQ is enabled for any of these platforms, the following
compile error will be seen.
arch/arm/kernel/fiq.c: In function ?enable_fiq?:
arch/arm/kernel/fiq.c:127:19: error: ?FIQ_START? undeclared (first use in this function)
arch/arm/kernel/fiq.c:127:19: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/kernel/fiq.c: In function ?disable_fiq?:
arch/arm/kernel/fiq.c:132:20: error: ?FIQ_START? undeclared (first use in this function)
Though FIQ_START is defined in above 5 platforms, a grep on the whole
tree only reports the following users of enable_fiq/disable_fiq.
arch/arm/mach-rpc/dma.c
drivers/media/video/mx1_camera.c
sound/soc/fsl/imx-pcm-fiq.c
That said, only rpc and imx are actually using enable_fiq/disable_fiq.
The patch changes enable_fiq/disable_fiq a little bit to have the
absolute fiq number than offset passed into by parameter "fiq". While
fiq on imx starts from 0, only rpc needs a fix-up to adapt the change.
With this change, all those FIQ_START definitions in platform irqs.h
can be removed now, but we chose to leave the decision to platform
maintainers, it should be removed or just left there as a document
on where fiq starts on the platform.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/kernel/fiq.c | 4 ++--
arch/arm/mach-rpc/include/mach/irqs.h | 12 ++++++------
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index c32f845..5953bea 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -124,12 +124,12 @@ void release_fiq(struct fiq_handler *f)
void enable_fiq(int fiq)
{
- enable_irq(fiq + FIQ_START);
+ enable_irq(fiq);
}
void disable_fiq(int fiq)
{
- disable_irq(fiq + FIQ_START);
+ disable_irq(fiq);
}
EXPORT_SYMBOL(set_fiq_handler);
diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
index 6868e17..4962bdd 100644
--- a/arch/arm/mach-rpc/include/mach/irqs.h
+++ b/arch/arm/mach-rpc/include/mach/irqs.h
@@ -31,15 +31,15 @@
#define IRQ_DMAS0 20
#define IRQ_DMAS1 21
-#define FIQ_FLOPPYDATA 0
-#define FIQ_ECONET 2
-#define FIQ_SERIALPORT 4
-#define FIQ_EXPANSIONCARD 6
-#define FIQ_FORCE 7
-
/*
* This is the offset of the FIQ "IRQ" numbers
*/
#define FIQ_START 64
+#define FIQ_FLOPPYDATA (FIQ_START + 0)
+#define FIQ_ECONET (FIQ_START + 2)
+#define FIQ_SERIALPORT (FIQ_START + 4)
+#define FIQ_EXPANSIONCARD (FIQ_START + 6)
+#define FIQ_FORCE (FIQ_START + 7)
+
#define NR_IRQS 128
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-14 5:59 ` [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number Shawn Guo
@ 2012-06-18 8:39 ` Dong Aisheng
2012-06-18 14:31 ` Shawn Guo
1 sibling, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-18 8:39 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:46PM +0800, Shawn Guo wrote:
> The commit a2be01b (ARM: only include mach/irqs.h for !SPARSE_IRQ)
> makes mach/irqs.h only be included for !SPARSE_IRQ build. There are
> a nubmer of platforms have FIQ_START defined in mach/irqs.h.
>
> arch/arm/mach-at91/include/mach/irqs.h:#define FIQ_START AT91_ID_FIQ
> arch/arm/mach-rpc/include/mach/irqs.h:#define FIQ_START 64
> arch/arm/mach-s3c24xx/include/mach/irqs.h:#define FIQ_START IRQ_EINT0
> arch/arm/plat-mxc/include/mach/irqs.h:#define FIQ_START 0
> arch/arm/plat-omap/include/plat/irqs.h:#define FIQ_START 1024
>
> If SPARSE_IRQ is enabled for any of these platforms, the following
> compile error will be seen.
>
> arch/arm/kernel/fiq.c: In function ?enable_fiq?:
> arch/arm/kernel/fiq.c:127:19: error: ?FIQ_START? undeclared (first use in this function)
> arch/arm/kernel/fiq.c:127:19: note: each undeclared identifier is reported only once for each function it appears in
> arch/arm/kernel/fiq.c: In function ?disable_fiq?:
> arch/arm/kernel/fiq.c:132:20: error: ?FIQ_START? undeclared (first use in this function)
>
> Though FIQ_START is defined in above 5 platforms, a grep on the whole
> tree only reports the following users of enable_fiq/disable_fiq.
>
> arch/arm/mach-rpc/dma.c
> drivers/media/video/mx1_camera.c
> sound/soc/fsl/imx-pcm-fiq.c
>
> That said, only rpc and imx are actually using enable_fiq/disable_fiq.
>
> The patch changes enable_fiq/disable_fiq a little bit to have the
> absolute fiq number than offset passed into by parameter "fiq". While
> fiq on imx starts from 0, only rpc needs a fix-up to adapt the change.
>
> With this change, all those FIQ_START definitions in platform irqs.h
> can be removed now, but we chose to leave the decision to platform
> maintainers, it should be removed or just left there as a document
> on where fiq starts on the platform.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> ---
> arch/arm/kernel/fiq.c | 4 ++--
> arch/arm/mach-rpc/include/mach/irqs.h | 12 ++++++------
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
> index c32f845..5953bea 100644
> --- a/arch/arm/kernel/fiq.c
> +++ b/arch/arm/kernel/fiq.c
> @@ -124,12 +124,12 @@ void release_fiq(struct fiq_handler *f)
>
> void enable_fiq(int fiq)
> {
> - enable_irq(fiq + FIQ_START);
> + enable_irq(fiq);
> }
>
> void disable_fiq(int fiq)
> {
> - disable_irq(fiq + FIQ_START);
> + disable_irq(fiq);
> }
>
I don't know why we put FIQ_START in fiq.c, but this looks like a reasonable
solution, so:
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Also waiting for other people's comments.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-14 5:59 ` [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number Shawn Guo
2012-06-18 8:39 ` Dong Aisheng
@ 2012-06-18 14:31 ` Shawn Guo
2012-06-18 16:44 ` Russell King - ARM Linux
1 sibling, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-18 14:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi Russell,
Do you have any comment, or may I have your ack on this patch?
Regards,
Shawn
On Thu, Jun 14, 2012 at 01:59:46PM +0800, Shawn Guo wrote:
> The commit a2be01b (ARM: only include mach/irqs.h for !SPARSE_IRQ)
> makes mach/irqs.h only be included for !SPARSE_IRQ build. There are
> a nubmer of platforms have FIQ_START defined in mach/irqs.h.
>
> arch/arm/mach-at91/include/mach/irqs.h:#define FIQ_START AT91_ID_FIQ
> arch/arm/mach-rpc/include/mach/irqs.h:#define FIQ_START 64
> arch/arm/mach-s3c24xx/include/mach/irqs.h:#define FIQ_START IRQ_EINT0
> arch/arm/plat-mxc/include/mach/irqs.h:#define FIQ_START 0
> arch/arm/plat-omap/include/plat/irqs.h:#define FIQ_START 1024
>
> If SPARSE_IRQ is enabled for any of these platforms, the following
> compile error will be seen.
>
> arch/arm/kernel/fiq.c: In function ?enable_fiq?:
> arch/arm/kernel/fiq.c:127:19: error: ?FIQ_START? undeclared (first use in this function)
> arch/arm/kernel/fiq.c:127:19: note: each undeclared identifier is reported only once for each function it appears in
> arch/arm/kernel/fiq.c: In function ?disable_fiq?:
> arch/arm/kernel/fiq.c:132:20: error: ?FIQ_START? undeclared (first use in this function)
>
> Though FIQ_START is defined in above 5 platforms, a grep on the whole
> tree only reports the following users of enable_fiq/disable_fiq.
>
> arch/arm/mach-rpc/dma.c
> drivers/media/video/mx1_camera.c
> sound/soc/fsl/imx-pcm-fiq.c
>
> That said, only rpc and imx are actually using enable_fiq/disable_fiq.
>
> The patch changes enable_fiq/disable_fiq a little bit to have the
> absolute fiq number than offset passed into by parameter "fiq". While
> fiq on imx starts from 0, only rpc needs a fix-up to adapt the change.
>
> With this change, all those FIQ_START definitions in platform irqs.h
> can be removed now, but we chose to leave the decision to platform
> maintainers, it should be removed or just left there as a document
> on where fiq starts on the platform.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> ---
> arch/arm/kernel/fiq.c | 4 ++--
> arch/arm/mach-rpc/include/mach/irqs.h | 12 ++++++------
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
> index c32f845..5953bea 100644
> --- a/arch/arm/kernel/fiq.c
> +++ b/arch/arm/kernel/fiq.c
> @@ -124,12 +124,12 @@ void release_fiq(struct fiq_handler *f)
>
> void enable_fiq(int fiq)
> {
> - enable_irq(fiq + FIQ_START);
> + enable_irq(fiq);
> }
>
> void disable_fiq(int fiq)
> {
> - disable_irq(fiq + FIQ_START);
> + disable_irq(fiq);
> }
>
> EXPORT_SYMBOL(set_fiq_handler);
> diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
> index 6868e17..4962bdd 100644
> --- a/arch/arm/mach-rpc/include/mach/irqs.h
> +++ b/arch/arm/mach-rpc/include/mach/irqs.h
> @@ -31,15 +31,15 @@
> #define IRQ_DMAS0 20
> #define IRQ_DMAS1 21
>
> -#define FIQ_FLOPPYDATA 0
> -#define FIQ_ECONET 2
> -#define FIQ_SERIALPORT 4
> -#define FIQ_EXPANSIONCARD 6
> -#define FIQ_FORCE 7
> -
> /*
> * This is the offset of the FIQ "IRQ" numbers
> */
> #define FIQ_START 64
>
> +#define FIQ_FLOPPYDATA (FIQ_START + 0)
> +#define FIQ_ECONET (FIQ_START + 2)
> +#define FIQ_SERIALPORT (FIQ_START + 4)
> +#define FIQ_EXPANSIONCARD (FIQ_START + 6)
> +#define FIQ_FORCE (FIQ_START + 7)
> +
> #define NR_IRQS 128
> --
> 1.7.5.4
>
>
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-18 14:31 ` Shawn Guo
@ 2012-06-18 16:44 ` Russell King - ARM Linux
2012-06-19 5:26 ` Shawn Guo
0 siblings, 1 reply; 85+ messages in thread
From: Russell King - ARM Linux @ 2012-06-18 16:44 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jun 18, 2012 at 10:31:30PM +0800, Shawn Guo wrote:
> Hi Russell,
>
> Do you have any comment, or may I have your ack on this patch?
Yes, I haven't seen it, and now that I have I don't like it.
FIQs should be an entirely separate number space from IRQs, as we
may want to totally decouple them from the IRQ stuff (we probably
should have already done this when genirq came along.)
About the only stuff FIQs use is the enable/disable_irq as a short
cut to dealing with the mask registers.
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-18 16:44 ` Russell King - ARM Linux
@ 2012-06-19 5:26 ` Shawn Guo
2012-06-20 22:55 ` Russell King - ARM Linux
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-19 5:26 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jun 18, 2012 at 05:44:02PM +0100, Russell King - ARM Linux wrote:
> FIQs should be an entirely separate number space from IRQs, as we
> may want to totally decouple them from the IRQ stuff (we probably
> should have already done this when genirq came along.)
>
> About the only stuff FIQs use is the enable/disable_irq as a short
> cut to dealing with the mask registers.
I do not quite understand what you are asking for, but I'm guessing it
with the patch below. Please elaborate it a little bit more if that's
not what you are asking for.
Regards,
Shawn
--8<---
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index c32f845..dce12fb 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -39,6 +39,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
+#include <linux/irq.h>
#include <linux/seq_file.h>
#include <asm/cacheflush.h>
@@ -124,12 +125,20 @@ void release_fiq(struct fiq_handler *f)
void enable_fiq(int fiq)
{
- enable_irq(fiq + FIQ_START);
+ struct irq_data *d = irq_get_irq_data(fiq);
+ struct irq_chip *chip = irq_data_get_irq_chip(d);
+
+ if (chip->irq_unmask)
+ chip->irq_unmask(d);
}
void disable_fiq(int fiq)
{
- disable_irq(fiq + FIQ_START);
+ struct irq_data *d = irq_get_irq_data(fiq);
+ struct irq_chip *chip = irq_data_get_irq_chip(d);
+
+ if (chip->irq_mask)
+ chip->irq_mask(d);
}
EXPORT_SYMBOL(set_fiq_handler);
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-19 5:26 ` Shawn Guo
@ 2012-06-20 22:55 ` Russell King - ARM Linux
2012-06-20 23:40 ` Shawn Guo
` (3 more replies)
0 siblings, 4 replies; 85+ messages in thread
From: Russell King - ARM Linux @ 2012-06-20 22:55 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jun 19, 2012 at 01:26:56PM +0800, Shawn Guo wrote:
> On Mon, Jun 18, 2012 at 05:44:02PM +0100, Russell King - ARM Linux wrote:
> > FIQs should be an entirely separate number space from IRQs, as we
> > may want to totally decouple them from the IRQ stuff (we probably
> > should have already done this when genirq came along.)
> >
> > About the only stuff FIQs use is the enable/disable_irq as a short
> > cut to dealing with the mask registers.
>
> I do not quite understand what you are asking for, but I'm guessing it
> with the patch below. Please elaborate it a little bit more if that's
> not what you are asking for.
I was thinking about moving entirely away from any bits of genirq for
this. We shouldn't really be mixing these two things together by
nabbing some of the IRQ numberspace for this.
Looking at this code, I'm thinking about taking this further, and
santising the whole thing... though that's not going to be a quick
change.
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-20 22:55 ` Russell King - ARM Linux
@ 2012-06-20 23:40 ` Shawn Guo
2012-06-20 23:53 ` Shawn Guo
` (2 subsequent siblings)
3 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-20 23:40 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jun 20, 2012 at 11:55:20PM +0100, Russell King - ARM Linux wrote:
> On Tue, Jun 19, 2012 at 01:26:56PM +0800, Shawn Guo wrote:
> > On Mon, Jun 18, 2012 at 05:44:02PM +0100, Russell King - ARM Linux wrote:
> > > FIQs should be an entirely separate number space from IRQs, as we
> > > may want to totally decouple them from the IRQ stuff (we probably
> > > should have already done this when genirq came along.)
> > >
> > > About the only stuff FIQs use is the enable/disable_irq as a short
> > > cut to dealing with the mask registers.
> >
> > I do not quite understand what you are asking for, but I'm guessing it
> > with the patch below. Please elaborate it a little bit more if that's
> > not what you are asking for.
>
> I was thinking about moving entirely away from any bits of genirq for
> this. We shouldn't really be mixing these two things together by
> nabbing some of the IRQ numberspace for this.
>
> Looking at this code, I'm thinking about taking this further, and
> santising the whole thing... though that's not going to be a quick
> change.
What I'm looking for is a quick and reasonable fixing for a compile
error when SPARSE_IRQ is enabled for imx. Can we take the original
patch as it is and defer the whole cleanup to another series?
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-20 22:55 ` Russell King - ARM Linux
2012-06-20 23:40 ` Shawn Guo
@ 2012-06-20 23:53 ` Shawn Guo
2012-06-21 7:37 ` Russell King - ARM Linux
2012-06-21 8:50 ` Shawn Guo
2012-06-25 16:10 ` Shawn Guo
3 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-20 23:53 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jun 20, 2012 at 11:55:20PM +0100, Russell King - ARM Linux wrote:
> On Tue, Jun 19, 2012 at 01:26:56PM +0800, Shawn Guo wrote:
> > On Mon, Jun 18, 2012 at 05:44:02PM +0100, Russell King - ARM Linux wrote:
> > > FIQs should be an entirely separate number space from IRQs, as we
> > > may want to totally decouple them from the IRQ stuff (we probably
> > > should have already done this when genirq came along.)
> > >
> > > About the only stuff FIQs use is the enable/disable_irq as a short
> > > cut to dealing with the mask registers.
> >
> > I do not quite understand what you are asking for, but I'm guessing it
> > with the patch below. Please elaborate it a little bit more if that's
> > not what you are asking for.
>
> I was thinking about moving entirely away from any bits of genirq for
> this. We shouldn't really be mixing these two things together by
> nabbing some of the IRQ numberspace for this.
>
> Looking at this code, I'm thinking about taking this further, and
> santising the whole thing... though that's not going to be a quick
> change.
What I'm looking for is a quick and safe fixing for a compile error
when SPARSE_IRQ enabled for imx. Can we take the original patch as
it is and defer the whole cleanup to another series?
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-20 23:53 ` Shawn Guo
@ 2012-06-21 7:37 ` Russell King - ARM Linux
0 siblings, 0 replies; 85+ messages in thread
From: Russell King - ARM Linux @ 2012-06-21 7:37 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 21, 2012 at 07:53:20AM +0800, Shawn Guo wrote:
> On Wed, Jun 20, 2012 at 11:55:20PM +0100, Russell King - ARM Linux wrote:
> > On Tue, Jun 19, 2012 at 01:26:56PM +0800, Shawn Guo wrote:
> > > On Mon, Jun 18, 2012 at 05:44:02PM +0100, Russell King - ARM Linux wrote:
> > > > FIQs should be an entirely separate number space from IRQs, as we
> > > > may want to totally decouple them from the IRQ stuff (we probably
> > > > should have already done this when genirq came along.)
> > > >
> > > > About the only stuff FIQs use is the enable/disable_irq as a short
> > > > cut to dealing with the mask registers.
> > >
> > > I do not quite understand what you are asking for, but I'm guessing it
> > > with the patch below. Please elaborate it a little bit more if that's
> > > not what you are asking for.
> >
> > I was thinking about moving entirely away from any bits of genirq for
> > this. We shouldn't really be mixing these two things together by
> > nabbing some of the IRQ numberspace for this.
> >
> > Looking at this code, I'm thinking about taking this further, and
> > santising the whole thing... though that's not going to be a quick
> > change.
>
> What I'm looking for is a quick and safe fixing for a compile error
> when SPARSE_IRQ enabled for imx. Can we take the original patch as
> it is and defer the whole cleanup to another series?
No, I don't want to make FIQ numbers somehow the same as IRQ numbers,
not even "temporarily".
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-20 22:55 ` Russell King - ARM Linux
2012-06-20 23:40 ` Shawn Guo
2012-06-20 23:53 ` Shawn Guo
@ 2012-06-21 8:50 ` Shawn Guo
2012-06-25 16:10 ` Shawn Guo
3 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-21 8:50 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jun 20, 2012 at 11:55:20PM +0100, Russell King - ARM Linux wrote:
> On Tue, Jun 19, 2012 at 01:26:56PM +0800, Shawn Guo wrote:
> > On Mon, Jun 18, 2012 at 05:44:02PM +0100, Russell King - ARM Linux wrote:
> > > FIQs should be an entirely separate number space from IRQs, as we
> > > may want to totally decouple them from the IRQ stuff (we probably
> > > should have already done this when genirq came along.)
> > >
> > > About the only stuff FIQs use is the enable/disable_irq as a short
> > > cut to dealing with the mask registers.
> >
> > I do not quite understand what you are asking for, but I'm guessing it
> > with the patch below. Please elaborate it a little bit more if that's
> > not what you are asking for.
>
> I was thinking about moving entirely away from any bits of genirq for
> this. We shouldn't really be mixing these two things together by
> nabbing some of the IRQ numberspace for this.
>
> Looking at this code, I'm thinking about taking this further, and
> santising the whole thing... though that's not going to be a quick
> change.
Reading the comment, I still do not have any picture about how to
decouple the FIQ from IRQ numberspace. Could you take a few minutes
to educate specifically, so that I do not have to guess what's the
best way to do that?
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 15/16] ARM: fiq: save FIQ_START by passing absolute fiq number
2012-06-20 22:55 ` Russell King - ARM Linux
` (2 preceding siblings ...)
2012-06-21 8:50 ` Shawn Guo
@ 2012-06-25 16:10 ` Shawn Guo
3 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-25 16:10 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jun 20, 2012 at 11:55:20PM +0100, Russell King - ARM Linux wrote:
> I was thinking about moving entirely away from any bits of genirq for
> this. We shouldn't really be mixing these two things together by
> nabbing some of the IRQ numberspace for this.
>
> Looking at this code, I'm thinking about taking this further, and
> santising the whole thing... though that's not going to be a quick
> change.
Would you mind giving a little more hints on how this should be done
properly? Sorry for my dumb head.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-14 5:59 ` Shawn Guo
` (15 preceding siblings ...)
(?)
@ 2012-06-14 5:59 ` Shawn Guo
2012-06-14 7:40 ` Haojian Zhuang
2012-06-18 8:48 ` Dong Aisheng
-1 siblings, 2 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 5:59 UTC (permalink / raw)
To: linux-arm-kernel
As all irqchips on imx have been changed to allocate their irq_descs,
and all unneeded mach/irqs.h inclusions on imx have been cleaned up,
now it's time to select SPARSE_IRQ for imx/mxc.
The SPARSE_IRQ support forces irqs allocation starting from 16. All
those static irq number definition for SoCs need to shift 16 to keep
non-DT boot works.
With all those static IRQ number and start definitions removed from
mach/irqs.h, the header becomes just a container of a couple of
mach-imx specific irq/fiq calls. Since mach/irqs.h is not included
by asm/irq.h now, the users of mxc_set_irq_fiq needs to explicitly
include mach/irqs.h themselves.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/Kconfig | 1 +
arch/arm/plat-mxc/include/mach/irqs.h | 44 -------
arch/arm/plat-mxc/include/mach/mx1.h | 111 +++++++++---------
arch/arm/plat-mxc/include/mach/mx21.h | 107 ++++++++--------
arch/arm/plat-mxc/include/mach/mx25.h | 72 ++++++-----
arch/arm/plat-mxc/include/mach/mx27.h | 127 ++++++++++----------
arch/arm/plat-mxc/include/mach/mx2x.h | 87 +++++++-------
arch/arm/plat-mxc/include/mach/mx31.h | 118 +++++++++---------
arch/arm/plat-mxc/include/mach/mx35.h | 109 +++++++++--------
arch/arm/plat-mxc/include/mach/mx3x.h | 77 ++++++------
arch/arm/plat-mxc/include/mach/mx50.h | 187 ++++++++++++++--------------
arch/arm/plat-mxc/include/mach/mx51.h | 209 ++++++++++++++++----------------
arch/arm/plat-mxc/include/mach/mx53.h | 217 +++++++++++++++++----------------
drivers/media/video/mx1_camera.c | 1 +
sound/soc/fsl/imx-pcm-fiq.c | 1 +
15 files changed, 722 insertions(+), 746 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 84449dd..63f40b4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -446,6 +446,7 @@ config ARCH_MXC
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select MULTI_IRQ_HANDLER
+ select SPARSE_IRQ
help
Support for Freescale MXC/iMX-based family of processors
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index fd9efb0..d73f5e8 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -11,50 +11,6 @@
#ifndef __ASM_ARCH_MXC_IRQS_H__
#define __ASM_ARCH_MXC_IRQS_H__
-#include <asm-generic/gpio.h>
-
-/*
- * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
- * have 128 IRQs, and those with AVIC have 64.
- *
- * To support single image, the biggest number should be defined on
- * top of the list.
- */
-#if defined CONFIG_ARM_GIC
-#define MXC_INTERNAL_IRQS 160
-#elif defined CONFIG_MXC_TZIC
-#define MXC_INTERNAL_IRQS 128
-#else
-#define MXC_INTERNAL_IRQS 64
-#endif
-
-#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
-
-/*
- * The next 16 interrupts are for board specific purposes. Since
- * the kernel can only run on one machine at a time, we can re-use
- * these. If you need more, increase MXC_BOARD_IRQS, but keep it
- * within sensible limits.
- */
-#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
-
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
-#define MXC_BOARD_IRQS 80
-#else
-#define MXC_BOARD_IRQS 16
-#endif
-
-#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
-
-#ifdef CONFIG_MX3_IPU_IRQS
-#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
-#else
-#define MX3_IPU_IRQS 0
-#endif
-/* REVISIT: Add IPU irqs on IMX51 */
-
-#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
-
extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
/* all normal IRQs can be FIQs */
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 2b7c08d..45bd31c 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -78,61 +78,62 @@
#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
/* fixed interrput numbers */
-#define MX1_INT_SOFTINT 0
-#define MX1_INT_CSI 6
-#define MX1_DSPA_MAC_INT 7
-#define MX1_DSPA_INT 8
-#define MX1_COMP_INT 9
-#define MX1_MSHC_XINT 10
-#define MX1_GPIO_INT_PORTA 11
-#define MX1_GPIO_INT_PORTB 12
-#define MX1_GPIO_INT_PORTC 13
-#define MX1_INT_LCDC 14
-#define MX1_SIM_INT 15
-#define MX1_SIM_DATA_INT 16
-#define MX1_RTC_INT 17
-#define MX1_RTC_SAMINT 18
-#define MX1_INT_UART2PFERR 19
-#define MX1_INT_UART2RTS 20
-#define MX1_INT_UART2DTR 21
-#define MX1_INT_UART2UARTC 22
-#define MX1_INT_UART2TX 23
-#define MX1_INT_UART2RX 24
-#define MX1_INT_UART1PFERR 25
-#define MX1_INT_UART1RTS 26
-#define MX1_INT_UART1DTR 27
-#define MX1_INT_UART1UARTC 28
-#define MX1_INT_UART1TX 29
-#define MX1_INT_UART1RX 30
-#define MX1_VOICE_DAC_INT 31
-#define MX1_VOICE_ADC_INT 32
-#define MX1_PEN_DATA_INT 33
-#define MX1_PWM_INT 34
-#define MX1_SDHC_INT 35
-#define MX1_INT_I2C 39
-#define MX1_INT_CSPI2 40
-#define MX1_INT_CSPI1 41
-#define MX1_SSI_TX_INT 42
-#define MX1_SSI_TX_ERR_INT 43
-#define MX1_SSI_RX_INT 44
-#define MX1_SSI_RX_ERR_INT 45
-#define MX1_TOUCH_INT 46
-#define MX1_INT_USBD0 47
-#define MX1_INT_USBD1 48
-#define MX1_INT_USBD2 49
-#define MX1_INT_USBD3 50
-#define MX1_INT_USBD4 51
-#define MX1_INT_USBD5 52
-#define MX1_INT_USBD6 53
-#define MX1_BTSYS_INT 55
-#define MX1_BTTIM_INT 56
-#define MX1_BTWUI_INT 57
-#define MX1_TIM2_INT 58
-#define MX1_TIM1_INT 59
-#define MX1_DMA_ERR 60
-#define MX1_DMA_INT 61
-#define MX1_GPIO_INT_PORTD 62
-#define MX1_WDT_INT 63
+#include <asm/irq.h>
+#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
+#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
+#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
+#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
+#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
+#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
+#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
+#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
+#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
+#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
+#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
+#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
+#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
+#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
+#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
+#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
+#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
+#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
+#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
+#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
+#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
+#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
+#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
+#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
+#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
+#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
+#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
+#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
+#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
+#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
+#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
+#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
+#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
+#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
+#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
+#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
+#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
+#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
+#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
+#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
+#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
+#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
+#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
+#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
+#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
+#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
+#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
+#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
+#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
+#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
+#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
+#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
+#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
+#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
+#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
/* DMA */
#define MX1_DMA_REQ_UART3_T 2
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 6cd049e..468738a 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -99,59 +99,60 @@
#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
/* fixed interrupt numbers */
-#define MX21_INT_CSPI3 6
-#define MX21_INT_GPIO 8
-#define MX21_INT_FIRI 9
-#define MX21_INT_SDHC2 10
-#define MX21_INT_SDHC1 11
-#define MX21_INT_I2C 12
-#define MX21_INT_SSI2 13
-#define MX21_INT_SSI1 14
-#define MX21_INT_CSPI2 15
-#define MX21_INT_CSPI1 16
-#define MX21_INT_UART4 17
-#define MX21_INT_UART3 18
-#define MX21_INT_UART2 19
-#define MX21_INT_UART1 20
-#define MX21_INT_KPP 21
-#define MX21_INT_RTC 22
-#define MX21_INT_PWM 23
-#define MX21_INT_GPT3 24
-#define MX21_INT_GPT2 25
-#define MX21_INT_GPT1 26
-#define MX21_INT_WDOG 27
-#define MX21_INT_PCMCIA 28
-#define MX21_INT_NFC 29
-#define MX21_INT_BMI 30
-#define MX21_INT_CSI 31
-#define MX21_INT_DMACH0 32
-#define MX21_INT_DMACH1 33
-#define MX21_INT_DMACH2 34
-#define MX21_INT_DMACH3 35
-#define MX21_INT_DMACH4 36
-#define MX21_INT_DMACH5 37
-#define MX21_INT_DMACH6 38
-#define MX21_INT_DMACH7 39
-#define MX21_INT_DMACH8 40
-#define MX21_INT_DMACH9 41
-#define MX21_INT_DMACH10 42
-#define MX21_INT_DMACH11 43
-#define MX21_INT_DMACH12 44
-#define MX21_INT_DMACH13 45
-#define MX21_INT_DMACH14 46
-#define MX21_INT_DMACH15 47
-#define MX21_INT_EMMAENC 49
-#define MX21_INT_EMMADEC 50
-#define MX21_INT_EMMAPRP 51
-#define MX21_INT_EMMAPP 52
-#define MX21_INT_USBWKUP 53
-#define MX21_INT_USBDMA 54
-#define MX21_INT_USBHOST 55
-#define MX21_INT_USBFUNC 56
-#define MX21_INT_USBMNP 57
-#define MX21_INT_USBCTRL 58
-#define MX21_INT_SLCDC 60
-#define MX21_INT_LCDC 61
+#include <asm/irq.h>
+#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
+#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
+#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
+#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
+#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
+#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
+#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
+#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
+#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
+#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
+#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
+#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
+#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
+#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
+#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
+#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
+#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
+#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
+#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
+#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
+#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
+#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
+#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
+#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
+#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
+#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
+#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
+#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
+#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
+#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
+#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
+#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
+#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
+#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
+#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
+#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
+#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
+#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
+#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
+#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
+#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
+#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
+#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
+#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
+#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
+#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
+#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
+#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
+#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
+#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
+#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
+#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
/* fixed DMA request numbers */
#define MX21_DMA_REQ_CSPI3_RX 1
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index ccebf5b..627d94f 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -61,40 +61,44 @@
#define MX25_IO_P2V(x) IMX_IO_P2V(x)
#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
-#define MX25_INT_CSPI3 0
-#define MX25_INT_I2C1 3
-#define MX25_INT_I2C2 4
-#define MX25_INT_UART4 5
-#define MX25_INT_ESDHC2 8
-#define MX25_INT_ESDHC1 9
-#define MX25_INT_I2C3 10
-#define MX25_INT_SSI2 11
-#define MX25_INT_SSI1 12
-#define MX25_INT_CSPI2 13
-#define MX25_INT_CSPI1 14
-#define MX25_INT_GPIO3 16
-#define MX25_INT_CSI 17
-#define MX25_INT_UART3 18
-#define MX25_INT_GPIO4 23
-#define MX25_INT_KPP 24
-#define MX25_INT_DRYICE 25
-#define MX25_INT_PWM1 26
-#define MX25_INT_UART2 32
-#define MX25_INT_NFC 33
-#define MX25_INT_SDMA 34
-#define MX25_INT_USB_HS 35
-#define MX25_INT_PWM2 36
-#define MX25_INT_USB_OTG 37
-#define MX25_INT_LCDC 39
-#define MX25_INT_UART5 40
-#define MX25_INT_PWM3 41
-#define MX25_INT_PWM4 42
-#define MX25_INT_CAN1 43
-#define MX25_INT_CAN2 44
-#define MX25_INT_UART1 45
-#define MX25_INT_GPIO2 51
-#define MX25_INT_GPIO1 52
-#define MX25_INT_FEC 57
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
+#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
+#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
+#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
+#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
+#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
+#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
+#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
+#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
+#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
+#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
+#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
+#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
+#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
+#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
+#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
+#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
+#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
+#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
+#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
+#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
+#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
+#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
+#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
+#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
+#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
+#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
+#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
+#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
+#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
+#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
+#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
#define MX25_DMA_REQ_SSI2_RX1 22
#define MX25_DMA_REQ_SSI2_TX1 23
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 6265357..e074616 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -128,69 +128,70 @@
#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
/* fixed interrupt numbers */
-#define MX27_INT_I2C2 1
-#define MX27_INT_GPT6 2
-#define MX27_INT_GPT5 3
-#define MX27_INT_GPT4 4
-#define MX27_INT_RTIC 5
-#define MX27_INT_CSPI3 6
-#define MX27_INT_SDHC 7
-#define MX27_INT_GPIO 8
-#define MX27_INT_SDHC3 9
-#define MX27_INT_SDHC2 10
-#define MX27_INT_SDHC1 11
-#define MX27_INT_I2C1 12
-#define MX27_INT_SSI2 13
-#define MX27_INT_SSI1 14
-#define MX27_INT_CSPI2 15
-#define MX27_INT_CSPI1 16
-#define MX27_INT_UART4 17
-#define MX27_INT_UART3 18
-#define MX27_INT_UART2 19
-#define MX27_INT_UART1 20
-#define MX27_INT_KPP 21
-#define MX27_INT_RTC 22
-#define MX27_INT_PWM 23
-#define MX27_INT_GPT3 24
-#define MX27_INT_GPT2 25
-#define MX27_INT_GPT1 26
-#define MX27_INT_WDOG 27
-#define MX27_INT_PCMCIA 28
-#define MX27_INT_NFC 29
-#define MX27_INT_ATA 30
-#define MX27_INT_CSI 31
-#define MX27_INT_DMACH0 32
-#define MX27_INT_DMACH1 33
-#define MX27_INT_DMACH2 34
-#define MX27_INT_DMACH3 35
-#define MX27_INT_DMACH4 36
-#define MX27_INT_DMACH5 37
-#define MX27_INT_DMACH6 38
-#define MX27_INT_DMACH7 39
-#define MX27_INT_DMACH8 40
-#define MX27_INT_DMACH9 41
-#define MX27_INT_DMACH10 42
-#define MX27_INT_DMACH11 43
-#define MX27_INT_DMACH12 44
-#define MX27_INT_DMACH13 45
-#define MX27_INT_DMACH14 46
-#define MX27_INT_DMACH15 47
-#define MX27_INT_UART6 48
-#define MX27_INT_UART5 49
-#define MX27_INT_FEC 50
-#define MX27_INT_EMMAPRP 51
-#define MX27_INT_EMMAPP 52
-#define MX27_INT_VPU 53
-#define MX27_INT_USB_HS1 54
-#define MX27_INT_USB_HS2 55
-#define MX27_INT_USB_OTG 56
-#define MX27_INT_SCC_SMN 57
-#define MX27_INT_SCC_SCM 58
-#define MX27_INT_SAHARA 59
-#define MX27_INT_SLCDC 60
-#define MX27_INT_LCDC 61
-#define MX27_INT_IIM 62
-#define MX27_INT_CCM 63
+#include <asm/irq.h>
+#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
+#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
+#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
+#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
+#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
+#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
+#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
+#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
+#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
+#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
+#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
+#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
+#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
+#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
+#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
+#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
+#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
+#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
+#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
+#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
+#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
+#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
+#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
+#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
+#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
+#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
+#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
+#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
+#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
+#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
+#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
+#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
+#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
+#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
+#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
+#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
+#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
+#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
+#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
+#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
+#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
+#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
+#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
+#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
+#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
+#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
+#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
+#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
+#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
+#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
+#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
+#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
+#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
+#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
+#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
+#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
+#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
+#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
+#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
+#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
+#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
+#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
/* fixed DMA request numbers */
#define MX27_DMA_REQ_CSPI3_RX 1
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index 6d07839..11642f5 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -68,49 +68,50 @@
#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
/* fixed interrupt numbers */
-#define MX2x_INT_CSPI3 6
-#define MX2x_INT_GPIO 8
-#define MX2x_INT_SDHC2 10
-#define MX2x_INT_SDHC1 11
-#define MX2x_INT_I2C 12
-#define MX2x_INT_SSI2 13
-#define MX2x_INT_SSI1 14
-#define MX2x_INT_CSPI2 15
-#define MX2x_INT_CSPI1 16
-#define MX2x_INT_UART4 17
-#define MX2x_INT_UART3 18
-#define MX2x_INT_UART2 19
-#define MX2x_INT_UART1 20
-#define MX2x_INT_KPP 21
-#define MX2x_INT_RTC 22
-#define MX2x_INT_PWM 23
-#define MX2x_INT_GPT3 24
-#define MX2x_INT_GPT2 25
-#define MX2x_INT_GPT1 26
-#define MX2x_INT_WDOG 27
-#define MX2x_INT_PCMCIA 28
-#define MX2x_INT_NANDFC 29
-#define MX2x_INT_CSI 31
-#define MX2x_INT_DMACH0 32
-#define MX2x_INT_DMACH1 33
-#define MX2x_INT_DMACH2 34
-#define MX2x_INT_DMACH3 35
-#define MX2x_INT_DMACH4 36
-#define MX2x_INT_DMACH5 37
-#define MX2x_INT_DMACH6 38
-#define MX2x_INT_DMACH7 39
-#define MX2x_INT_DMACH8 40
-#define MX2x_INT_DMACH9 41
-#define MX2x_INT_DMACH10 42
-#define MX2x_INT_DMACH11 43
-#define MX2x_INT_DMACH12 44
-#define MX2x_INT_DMACH13 45
-#define MX2x_INT_DMACH14 46
-#define MX2x_INT_DMACH15 47
-#define MX2x_INT_EMMAPRP 51
-#define MX2x_INT_EMMAPP 52
-#define MX2x_INT_SLCDC 60
-#define MX2x_INT_LCDC 61
+#include <asm/irq.h>
+#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
+#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
+#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
+#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
+#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
+#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
+#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
+#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
+#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
+#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
+#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
+#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
+#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
+#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
+#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
+#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
+#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
+#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
+#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
+#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
+#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
+#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
+#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
+#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
+#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
+#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
+#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
+#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
+#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
+#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
+#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
+#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
+#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
+#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
+#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
+#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
+#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
+#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
+#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
+#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
+#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
+#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
/* fixed DMA request numbers */
#define MX2x_DMA_REQ_CSPI3_RX 1
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index e27619e..dbced61 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -118,63 +118,67 @@
#define MX31_IO_P2V(x) IMX_IO_P2V(x)
#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
-#define MX31_INT_I2C3 3
-#define MX31_INT_I2C2 4
-#define MX31_INT_MPEG4_ENCODER 5
-#define MX31_INT_RTIC 6
-#define MX31_INT_FIRI 7
-#define MX31_INT_SDHC2 8
-#define MX31_INT_SDHC1 9
-#define MX31_INT_I2C1 10
-#define MX31_INT_SSI2 11
-#define MX31_INT_SSI1 12
-#define MX31_INT_CSPI2 13
-#define MX31_INT_CSPI1 14
-#define MX31_INT_ATA 15
-#define MX31_INT_MBX 16
-#define MX31_INT_CSPI3 17
-#define MX31_INT_UART3 18
-#define MX31_INT_IIM 19
-#define MX31_INT_SIM2 20
-#define MX31_INT_SIM1 21
-#define MX31_INT_RNGA 22
-#define MX31_INT_EVTMON 23
-#define MX31_INT_KPP 24
-#define MX31_INT_RTC 25
-#define MX31_INT_PWM 26
-#define MX31_INT_EPIT2 27
-#define MX31_INT_EPIT1 28
-#define MX31_INT_GPT 29
-#define MX31_INT_POWER_FAIL 30
-#define MX31_INT_CCM_DVFS 31
-#define MX31_INT_UART2 32
-#define MX31_INT_NFC 33
-#define MX31_INT_SDMA 34
-#define MX31_INT_USB_HS1 35
-#define MX31_INT_USB_HS2 36
-#define MX31_INT_USB_OTG 37
-#define MX31_INT_MSHC1 39
-#define MX31_INT_MSHC2 40
-#define MX31_INT_IPU_ERR 41
-#define MX31_INT_IPU_SYN 42
-#define MX31_INT_UART1 45
-#define MX31_INT_UART4 46
-#define MX31_INT_UART5 47
-#define MX31_INT_ECT 48
-#define MX31_INT_SCC_SCM 49
-#define MX31_INT_SCC_SMN 50
-#define MX31_INT_GPIO2 51
-#define MX31_INT_GPIO1 52
-#define MX31_INT_CCM 53
-#define MX31_INT_PCMCIA 54
-#define MX31_INT_WDOG 55
-#define MX31_INT_GPIO3 56
-#define MX31_INT_EXT_POWER 58
-#define MX31_INT_EXT_TEMPER 59
-#define MX31_INT_EXT_SENSOR60 60
-#define MX31_INT_EXT_SENSOR61 61
-#define MX31_INT_EXT_WDOG 62
-#define MX31_INT_EXT_TV 63
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
+#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
+#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
+#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
+#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
+#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
+#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
+#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
+#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
+#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
+#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
+#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
+#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
+#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
+#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
+#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
+#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
+#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
+#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
+#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
+#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
+#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
+#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
+#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
+#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
+#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
+#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
+#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
+#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
+#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
+#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
+#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
+#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
+#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
+#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
+#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
+#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
+#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
+#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
+#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
+#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
+#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
+#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
+#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
+#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
+#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
+#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
+#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
+#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
+#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
+#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
+#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
+#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
+#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
+#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
#define MX31_DMA_REQ_SDHC1 20
#define MX31_DMA_REQ_SDHC2 21
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 80965a9..2af5d3a 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -120,60 +120,61 @@
/*
* Interrupt numbers
*/
-#define MX35_INT_OWIRE 2
-#define MX35_INT_I2C3 3
-#define MX35_INT_I2C2 4
-#define MX35_INT_RTIC 6
-#define MX35_INT_ESDHC1 7
-#define MX35_INT_ESDHC2 8
-#define MX35_INT_ESDHC3 9
-#define MX35_INT_I2C1 10
-#define MX35_INT_SSI1 11
-#define MX35_INT_SSI2 12
-#define MX35_INT_CSPI2 13
-#define MX35_INT_CSPI1 14
-#define MX35_INT_ATA 15
-#define MX35_INT_GPU2D 16
-#define MX35_INT_ASRC 17
-#define MX35_INT_UART3 18
-#define MX35_INT_IIM 19
-#define MX35_INT_RNGA 22
-#define MX35_INT_EVTMON 23
-#define MX35_INT_KPP 24
-#define MX35_INT_RTC 25
-#define MX35_INT_PWM 26
-#define MX35_INT_EPIT2 27
-#define MX35_INT_EPIT1 28
-#define MX35_INT_GPT 29
-#define MX35_INT_POWER_FAIL 30
-#define MX35_INT_UART2 32
-#define MX35_INT_NFC 33
-#define MX35_INT_SDMA 34
-#define MX35_INT_USB_HS 35
-#define MX35_INT_USB_OTG 37
-#define MX35_INT_MSHC1 39
-#define MX35_INT_ESAI 40
-#define MX35_INT_IPU_ERR 41
-#define MX35_INT_IPU_SYN 42
-#define MX35_INT_CAN1 43
-#define MX35_INT_CAN2 44
-#define MX35_INT_UART1 45
-#define MX35_INT_MLB 46
-#define MX35_INT_SPDIF 47
-#define MX35_INT_ECT 48
-#define MX35_INT_SCC_SCM 49
-#define MX35_INT_SCC_SMN 50
-#define MX35_INT_GPIO2 51
-#define MX35_INT_GPIO1 52
-#define MX35_INT_WDOG 55
-#define MX35_INT_GPIO3 56
-#define MX35_INT_FEC 57
-#define MX35_INT_EXT_POWER 58
-#define MX35_INT_EXT_TEMPER 59
-#define MX35_INT_EXT_SENSOR60 60
-#define MX35_INT_EXT_SENSOR61 61
-#define MX35_INT_EXT_WDOG 62
-#define MX35_INT_EXT_TV 63
+#include <asm/irq.h>
+#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
+#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
+#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
+#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
+#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
+#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
+#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
+#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
+#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
+#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
+#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
+#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
+#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
+#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
+#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
+#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
+#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
+#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
+#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
+#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
+#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
+#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
+#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
+#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
+#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
+#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
+#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
+#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
+#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
+#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
+#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
+#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
+#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
+#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
+#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
+#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
+#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
+#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
+#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
+#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
+#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
+#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
+#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
+#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
+#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
+#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
+#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
+#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
+#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
+#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
+#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
+#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
#define MX35_DMA_REQ_SSI2_RX1 22
#define MX35_DMA_REQ_SSI2_TX1 23
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 30dbf42..96fb4fb 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -143,44 +143,45 @@
/*
* Interrupt numbers
*/
-#define MX3x_INT_I2C3 3
-#define MX3x_INT_I2C2 4
-#define MX3x_INT_RTIC 6
-#define MX3x_INT_I2C 10
-#define MX3x_INT_CSPI2 13
-#define MX3x_INT_CSPI1 14
-#define MX3x_INT_ATA 15
-#define MX3x_INT_UART3 18
-#define MX3x_INT_IIM 19
-#define MX3x_INT_RNGA 22
-#define MX3x_INT_EVTMON 23
-#define MX3x_INT_KPP 24
-#define MX3x_INT_RTC 25
-#define MX3x_INT_PWM 26
-#define MX3x_INT_EPIT2 27
-#define MX3x_INT_EPIT1 28
-#define MX3x_INT_GPT 29
-#define MX3x_INT_POWER_FAIL 30
-#define MX3x_INT_UART2 32
-#define MX3x_INT_NANDFC 33
-#define MX3x_INT_SDMA 34
-#define MX3x_INT_MSHC1 39
-#define MX3x_INT_IPU_ERR 41
-#define MX3x_INT_IPU_SYN 42
-#define MX3x_INT_UART1 45
-#define MX3x_INT_ECT 48
-#define MX3x_INT_SCC_SCM 49
-#define MX3x_INT_SCC_SMN 50
-#define MX3x_INT_GPIO2 51
-#define MX3x_INT_GPIO1 52
-#define MX3x_INT_WDOG 55
-#define MX3x_INT_GPIO3 56
-#define MX3x_INT_EXT_POWER 58
-#define MX3x_INT_EXT_TEMPER 59
-#define MX3x_INT_EXT_SENSOR60 60
-#define MX3x_INT_EXT_SENSOR61 61
-#define MX3x_INT_EXT_WDOG 62
-#define MX3x_INT_EXT_TV 63
+#include <asm/irq.h>
+#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)
+#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)
+#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)
+#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)
+#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)
+#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)
+#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)
+#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)
+#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)
+#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23)
+#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24)
+#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25)
+#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26)
+#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27)
+#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28)
+#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29)
+#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
+#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33)
+#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34)
+#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39)
+#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
+#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
+#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45)
+#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48)
+#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
+#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
+#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51)
+#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52)
+#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55)
+#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56)
+#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
+#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
+#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
+#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
+#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
+#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63)
#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
index 5f2da75a..09ac19c 100644
--- a/arch/arm/plat-mxc/include/mach/mx50.h
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -188,99 +188,100 @@
/*
* Interrupt numbers
*/
-#define MX50_INT_MMC_SDHC1 1
-#define MX50_INT_MMC_SDHC2 2
-#define MX50_INT_MMC_SDHC3 3
-#define MX50_INT_MMC_SDHC4 4
-#define MX50_INT_DAP 5
-#define MX50_INT_SDMA 6
-#define MX50_INT_IOMUX 7
-#define MX50_INT_UART4 13
-#define MX50_INT_USB_H1 14
-#define MX50_INT_USB_OTG 18
-#define MX50_INT_DATABAHN 19
-#define MX50_INT_ELCDIF 20
-#define MX50_INT_EPXP 21
-#define MX50_INT_SRTC_NTZ 24
-#define MX50_INT_SRTC_TZ 25
-#define MX50_INT_EPDC 27
-#define MX50_INT_NIC 28
-#define MX50_INT_SSI1 29
-#define MX50_INT_SSI2 30
-#define MX50_INT_UART1 31
-#define MX50_INT_UART2 32
-#define MX50_INT_UART3 33
-#define MX50_INT_RESV34 34
-#define MX50_INT_RESV35 35
-#define MX50_INT_CSPI1 36
-#define MX50_INT_CSPI2 37
-#define MX50_INT_CSPI 38
-#define MX50_INT_GPT 39
-#define MX50_INT_EPIT1 40
-#define MX50_INT_GPIO1_INT7 42
-#define MX50_INT_GPIO1_INT6 43
-#define MX50_INT_GPIO1_INT5 44
-#define MX50_INT_GPIO1_INT4 45
-#define MX50_INT_GPIO1_INT3 46
-#define MX50_INT_GPIO1_INT2 47
-#define MX50_INT_GPIO1_INT1 48
-#define MX50_INT_GPIO1_INT0 49
-#define MX50_INT_GPIO1_LOW 50
-#define MX50_INT_GPIO1_HIGH 51
-#define MX50_INT_GPIO2_LOW 52
-#define MX50_INT_GPIO2_HIGH 53
-#define MX50_INT_GPIO3_LOW 54
-#define MX50_INT_GPIO3_HIGH 55
-#define MX50_INT_GPIO4_LOW 56
-#define MX50_INT_GPIO4_HIGH 57
-#define MX50_INT_WDOG1 58
-#define MX50_INT_KPP 60
-#define MX50_INT_PWM1 61
-#define MX50_INT_I2C1 62
-#define MX50_INT_I2C2 63
-#define MX50_INT_I2C3 64
-#define MX50_INT_RESV65 65
-#define MX50_INT_DCDC 66
-#define MX50_INT_THERMAL_ALARM 67
-#define MX50_INT_ANA3 68
-#define MX50_INT_ANA4 69
-#define MX50_INT_CCM1 71
-#define MX50_INT_CCM2 72
-#define MX50_INT_GPC1 73
-#define MX50_INT_GPC2 74
-#define MX50_INT_SRC 75
-#define MX50_INT_NM 76
-#define MX50_INT_PMU 77
-#define MX50_INT_CTI_IRQ 78
-#define MX50_INT_CTI1_TG0 79
-#define MX50_INT_CTI1_TG1 80
-#define MX50_INT_GPU2_IRQ 84
-#define MX50_INT_GPU2_BUSY 85
-#define MX50_INT_UART5 86
-#define MX50_INT_FEC 87
-#define MX50_INT_OWIRE 88
-#define MX50_INT_CTI1_TG2 89
-#define MX50_INT_SJC 90
-#define MX50_INT_DCP_CHAN1_3 91
-#define MX50_INT_DCP_CHAN0 92
-#define MX50_INT_PWM2 94
-#define MX50_INT_RNGB 97
-#define MX50_INT_CTI1_TG3 98
-#define MX50_INT_RAWNAND_BCH 100
-#define MX50_INT_RAWNAND_GPMI 102
-#define MX50_INT_GPIO5_LOW 103
-#define MX50_INT_GPIO5_HIGH 104
-#define MX50_INT_GPIO6_LOW 105
-#define MX50_INT_GPIO6_HIGH 106
-#define MX50_INT_MSHC 109
-#define MX50_INT_APBHDMA_CHAN0 110
-#define MX50_INT_APBHDMA_CHAN1 111
-#define MX50_INT_APBHDMA_CHAN2 112
-#define MX50_INT_APBHDMA_CHAN3 113
-#define MX50_INT_APBHDMA_CHAN4 114
-#define MX50_INT_APBHDMA_CHAN5 115
-#define MX50_INT_APBHDMA_CHAN6 116
-#define MX50_INT_APBHDMA_CHAN7 117
+#include <asm/irq.h>
+#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
+#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
+#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
+#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
+#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
+#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
+#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
+#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
+#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
+#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
+#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
+#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
+#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
+#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
+#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
+#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
+#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
+#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
+#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
+#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
+#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
+#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
+#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
+#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
+#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
+#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
+#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
+#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
+#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
+#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
+#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
+#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
+#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
+#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
+#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
+#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
+#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
+#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
+#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
+#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
+#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
+#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
+#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
+#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
+#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
+#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
+#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
+#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
+#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
+#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
+#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
+#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
+#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
+#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
+#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
+#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
+#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
+#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
+#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
+#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
+#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
+#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
+#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
+#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
+#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
+#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
+#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
+#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
+#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
+#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
+#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
+#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
+#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
+#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
+#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
+#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
+#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
+#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
+#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
+#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
+#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
+#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
+#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
+#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
+#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
+#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
+#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
+#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
+#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
+#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
+#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
+#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern int mx50_revision(void);
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index cdf07c6..af844f7 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -232,110 +232,111 @@
/*
* Interrupt numbers
*/
-#define MX51_INT_BASE 0
-#define MX51_INT_RESV0 0
-#define MX51_INT_ESDHC1 1
-#define MX51_INT_ESDHC2 2
-#define MX51_INT_ESDHC3 3
-#define MX51_INT_ESDHC4 4
-#define MX51_INT_RESV5 5
-#define MX51_INT_SDMA 6
-#define MX51_INT_IOMUX 7
-#define MX51_INT_NFC 8
-#define MX51_INT_VPU 9
-#define MX51_INT_IPU_ERR 10
-#define MX51_INT_IPU_SYN 11
-#define MX51_INT_GPU 12
-#define MX51_INT_RESV13 13
-#define MX51_INT_USB_HS1 14
-#define MX51_INT_EMI 15
-#define MX51_INT_USB_HS2 16
-#define MX51_INT_USB_HS3 17
-#define MX51_INT_USB_OTG 18
-#define MX51_INT_SAHARA_H0 19
-#define MX51_INT_SAHARA_H1 20
-#define MX51_INT_SCC_SMN 21
-#define MX51_INT_SCC_STZ 22
-#define MX51_INT_SCC_SCM 23
-#define MX51_INT_SRTC_NTZ 24
-#define MX51_INT_SRTC_TZ 25
-#define MX51_INT_RTIC 26
-#define MX51_INT_CSU 27
-#define MX51_INT_SLIM_B 28
-#define MX51_INT_SSI1 29
-#define MX51_INT_SSI2 30
-#define MX51_INT_UART1 31
-#define MX51_INT_UART2 32
-#define MX51_INT_UART3 33
-#define MX51_INT_RESV34 34
-#define MX51_INT_RESV35 35
-#define MX51_INT_ECSPI1 36
-#define MX51_INT_ECSPI2 37
-#define MX51_INT_CSPI 38
-#define MX51_INT_GPT 39
-#define MX51_INT_EPIT1 40
-#define MX51_INT_EPIT2 41
-#define MX51_INT_GPIO1_INT7 42
-#define MX51_INT_GPIO1_INT6 43
-#define MX51_INT_GPIO1_INT5 44
-#define MX51_INT_GPIO1_INT4 45
-#define MX51_INT_GPIO1_INT3 46
-#define MX51_INT_GPIO1_INT2 47
-#define MX51_INT_GPIO1_INT1 48
-#define MX51_INT_GPIO1_INT0 49
-#define MX51_INT_GPIO1_LOW 50
-#define MX51_INT_GPIO1_HIGH 51
-#define MX51_INT_GPIO2_LOW 52
-#define MX51_INT_GPIO2_HIGH 53
-#define MX51_INT_GPIO3_LOW 54
-#define MX51_INT_GPIO3_HIGH 55
-#define MX51_INT_GPIO4_LOW 56
-#define MX51_INT_GPIO4_HIGH 57
-#define MX51_INT_WDOG1 58
-#define MX51_INT_WDOG2 59
-#define MX51_INT_KPP 60
-#define MX51_INT_PWM1 61
-#define MX51_INT_I2C1 62
-#define MX51_INT_I2C2 63
-#define MX51_INT_HS_I2C 64
-#define MX51_INT_RESV65 65
-#define MX51_INT_RESV66 66
-#define MX51_INT_SIM_IPB 67
-#define MX51_INT_SIM_DAT 68
-#define MX51_INT_IIM 69
-#define MX51_INT_ATA 70
-#define MX51_INT_CCM1 71
-#define MX51_INT_CCM2 72
-#define MX51_INT_GPC1 73
-#define MX51_INT_GPC2 74
-#define MX51_INT_SRC 75
-#define MX51_INT_NM 76
-#define MX51_INT_PMU 77
-#define MX51_INT_CTI_IRQ 78
-#define MX51_INT_CTI1_TG0 79
-#define MX51_INT_CTI1_TG1 80
-#define MX51_INT_MCG_ERR 81
-#define MX51_INT_MCG_TMR 82
-#define MX51_INT_MCG_FUNC 83
-#define MX51_INT_GPU2_IRQ 84
-#define MX51_INT_GPU2_BUSY 85
-#define MX51_INT_RESV86 86
-#define MX51_INT_FEC 87
-#define MX51_INT_OWIRE 88
-#define MX51_INT_CTI1_TG2 89
-#define MX51_INT_SJC 90
-#define MX51_INT_SPDIF 91
-#define MX51_INT_TVE 92
-#define MX51_INT_FIRI 93
-#define MX51_INT_PWM2 94
-#define MX51_INT_SLIM_EXP 95
-#define MX51_INT_SSI3 96
-#define MX51_INT_EMI_BOOT 97
-#define MX51_INT_CTI1_TG3 98
-#define MX51_INT_SMC_RX 99
-#define MX51_INT_VPU_IDLE 100
-#define MX51_INT_EMI_NFC 101
-#define MX51_INT_GPU_IDLE 102
+#include <asm/irq.h>
+#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
+#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
+#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
+#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
+#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
+#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
+#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
+#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
+#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
+#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
+#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
+#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
+#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
+#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
+#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
+#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
+#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
+#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
+#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
+#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
+#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
+#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
+#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
+#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
+#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
+#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
+#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
+#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
+#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
+#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
+#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
+#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
+#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
+#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
+#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
+#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
+#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
+#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
+#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
+#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
+#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
+#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
+#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
+#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
+#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
+#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
+#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
+#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
+#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
+#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
+#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
+#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
+#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
+#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
+#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
+#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
+#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
+#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
+#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
+#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
+#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
+#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
+#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
+#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
+#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
+#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
+#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
+#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
+#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
+#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
+#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
+#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
+#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
+#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
+#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
+#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
+#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
+#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
+#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
+#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
+#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
+#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
+#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
+#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
+#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
+#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
+#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
+#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
+#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
+#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
+#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
+#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
+#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
+#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
+#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
+#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
+#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
+#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
+#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
+#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
+#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
+#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
+#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern int mx51_revision(void);
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index a37e8c3..f829d1c 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -229,113 +229,114 @@
/*
* Interrupt numbers
*/
-#define MX53_INT_RESV0 0
-#define MX53_INT_ESDHC1 1
-#define MX53_INT_ESDHC2 2
-#define MX53_INT_ESDHC3 3
-#define MX53_INT_ESDHC4 4
-#define MX53_INT_DAP 5
-#define MX53_INT_SDMA 6
-#define MX53_INT_IOMUX 7
-#define MX53_INT_NFC 8
-#define MX53_INT_VPU 9
-#define MX53_INT_IPU_ERR 10
-#define MX53_INT_IPU_SYN 11
-#define MX53_INT_GPU 12
-#define MX53_INT_UART4 13
-#define MX53_INT_USB_H1 14
-#define MX53_INT_EMI 15
-#define MX53_INT_USB_H2 16
-#define MX53_INT_USB_H3 17
-#define MX53_INT_USB_OTG 18
-#define MX53_INT_SAHARA_H0 19
-#define MX53_INT_SAHARA_H1 20
-#define MX53_INT_SCC_SMN 21
-#define MX53_INT_SCC_STZ 22
-#define MX53_INT_SCC_SCM 23
-#define MX53_INT_SRTC_NTZ 24
-#define MX53_INT_SRTC_TZ 25
-#define MX53_INT_RTIC 26
-#define MX53_INT_CSU 27
-#define MX53_INT_SATA 28
-#define MX53_INT_SSI1 29
-#define MX53_INT_SSI2 30
-#define MX53_INT_UART1 31
-#define MX53_INT_UART2 32
-#define MX53_INT_UART3 33
-#define MX53_INT_RTC 34
-#define MX53_INT_PTP 35
-#define MX53_INT_ECSPI1 36
-#define MX53_INT_ECSPI2 37
-#define MX53_INT_CSPI 38
-#define MX53_INT_GPT 39
-#define MX53_INT_EPIT1 40
-#define MX53_INT_EPIT2 41
-#define MX53_INT_GPIO1_INT7 42
-#define MX53_INT_GPIO1_INT6 43
-#define MX53_INT_GPIO1_INT5 44
-#define MX53_INT_GPIO1_INT4 45
-#define MX53_INT_GPIO1_INT3 46
-#define MX53_INT_GPIO1_INT2 47
-#define MX53_INT_GPIO1_INT1 48
-#define MX53_INT_GPIO1_INT0 49
-#define MX53_INT_GPIO1_LOW 50
-#define MX53_INT_GPIO1_HIGH 51
-#define MX53_INT_GPIO2_LOW 52
-#define MX53_INT_GPIO2_HIGH 53
-#define MX53_INT_GPIO3_LOW 54
-#define MX53_INT_GPIO3_HIGH 55
-#define MX53_INT_GPIO4_LOW 56
-#define MX53_INT_GPIO4_HIGH 57
-#define MX53_INT_WDOG1 58
-#define MX53_INT_WDOG2 59
-#define MX53_INT_KPP 60
-#define MX53_INT_PWM1 61
-#define MX53_INT_I2C1 62
-#define MX53_INT_I2C2 63
-#define MX53_INT_I2C3 64
-#define MX53_INT_MLB 65
-#define MX53_INT_ASRC 66
-#define MX53_INT_SPDIF 67
-#define MX53_INT_SIM_DAT 68
-#define MX53_INT_IIM 69
-#define MX53_INT_ATA 70
-#define MX53_INT_CCM1 71
-#define MX53_INT_CCM2 72
-#define MX53_INT_GPC1 73
-#define MX53_INT_GPC2 74
-#define MX53_INT_SRC 75
-#define MX53_INT_NM 76
-#define MX53_INT_PMU 77
-#define MX53_INT_CTI_IRQ 78
-#define MX53_INT_CTI1_TG0 79
-#define MX53_INT_CTI1_TG1 80
-#define MX53_INT_ESAI 81
-#define MX53_INT_CAN1 82
-#define MX53_INT_CAN2 83
-#define MX53_INT_GPU2_IRQ 84
-#define MX53_INT_GPU2_BUSY 85
-#define MX53_INT_UART5 86
-#define MX53_INT_FEC 87
-#define MX53_INT_OWIRE 88
-#define MX53_INT_CTI1_TG2 89
-#define MX53_INT_SJC 90
-#define MX53_INT_TVE 92
-#define MX53_INT_FIRI 93
-#define MX53_INT_PWM2 94
-#define MX53_INT_SLIM_EXP 95
-#define MX53_INT_SSI3 96
-#define MX53_INT_EMI_BOOT 97
-#define MX53_INT_CTI1_TG3 98
-#define MX53_INT_SMC_RX 99
-#define MX53_INT_VPU_IDLE 100
-#define MX53_INT_EMI_NFC 101
-#define MX53_INT_GPU_IDLE 102
-#define MX53_INT_GPIO5_LOW 103
-#define MX53_INT_GPIO5_HIGH 104
-#define MX53_INT_GPIO6_LOW 105
-#define MX53_INT_GPIO6_HIGH 106
-#define MX53_INT_GPIO7_LOW 107
-#define MX53_INT_GPIO7_HIGH 108
+#include <asm/irq.h>
+#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0)
+#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
+#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
+#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
+#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
+#define MX53_INT_DAP (NR_IRQS_LEGACY + 5)
+#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6)
+#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7)
+#define MX53_INT_NFC (NR_IRQS_LEGACY + 8)
+#define MX53_INT_VPU (NR_IRQS_LEGACY + 9)
+#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
+#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
+#define MX53_INT_GPU (NR_IRQS_LEGACY + 12)
+#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13)
+#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14)
+#define MX53_INT_EMI (NR_IRQS_LEGACY + 15)
+#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16)
+#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17)
+#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18)
+#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
+#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
+#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
+#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
+#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
+#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
+#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
+#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26)
+#define MX53_INT_CSU (NR_IRQS_LEGACY + 27)
+#define MX53_INT_SATA (NR_IRQS_LEGACY + 28)
+#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29)
+#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30)
+#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31)
+#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33)
+#define MX53_INT_RTC (NR_IRQS_LEGACY + 34)
+#define MX53_INT_PTP (NR_IRQS_LEGACY + 35)
+#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
+#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
+#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38)
+#define MX53_INT_GPT (NR_IRQS_LEGACY + 39)
+#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40)
+#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41)
+#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
+#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
+#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
+#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
+#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
+#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
+#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
+#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
+#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
+#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
+#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
+#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
+#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
+#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
+#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
+#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
+#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58)
+#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59)
+#define MX53_INT_KPP (NR_IRQS_LEGACY + 60)
+#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61)
+#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62)
+#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63)
+#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64)
+#define MX53_INT_MLB (NR_IRQS_LEGACY + 65)
+#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66)
+#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67)
+#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
+#define MX53_INT_IIM (NR_IRQS_LEGACY + 69)
+#define MX53_INT_ATA (NR_IRQS_LEGACY + 70)
+#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71)
+#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72)
+#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73)
+#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74)
+#define MX53_INT_SRC (NR_IRQS_LEGACY + 75)
+#define MX53_INT_NM (NR_IRQS_LEGACY + 76)
+#define MX53_INT_PMU (NR_IRQS_LEGACY + 77)
+#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
+#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
+#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
+#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81)
+#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82)
+#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83)
+#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
+#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
+#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86)
+#define MX53_INT_FEC (NR_IRQS_LEGACY + 87)
+#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88)
+#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
+#define MX53_INT_SJC (NR_IRQS_LEGACY + 90)
+#define MX53_INT_TVE (NR_IRQS_LEGACY + 92)
+#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93)
+#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94)
+#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
+#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96)
+#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
+#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
+#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99)
+#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
+#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
+#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
+#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
+#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
+#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
+#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
+#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107)
+#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108)
#endif /* ifndef __MACH_MX53_H__ */
diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
index 4296a83..d2e6f82 100644
--- a/drivers/media/video/mx1_camera.c
+++ b/drivers/media/video/mx1_camera.c
@@ -43,6 +43,7 @@
#include <asm/fiq.h>
#include <mach/dma-mx1-mx2.h>
#include <mach/hardware.h>
+#include <mach/irqs.h>
#include <mach/mx1_camera.h>
/*
diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
index 456b7d7..ee27ba3 100644
--- a/sound/soc/fsl/imx-pcm-fiq.c
+++ b/sound/soc/fsl/imx-pcm-fiq.c
@@ -29,6 +29,7 @@
#include <asm/fiq.h>
+#include <mach/irqs.h>
#include <mach/ssi.h>
#include "imx-ssi.h"
--
1.7.5.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-14 5:59 ` [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform Shawn Guo
@ 2012-06-14 7:40 ` Haojian Zhuang
2012-06-14 7:55 ` Shawn Guo
2012-06-18 8:48 ` Dong Aisheng
1 sibling, 1 reply; 85+ messages in thread
From: Haojian Zhuang @ 2012-06-14 7:40 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 1:59 PM, Shawn Guo <shawn.guo@linaro.org> wrote:
> As all irqchips on imx have been changed to allocate their irq_descs,
> and all unneeded mach/irqs.h inclusions on imx have been cleaned up,
> now it's time to select SPARSE_IRQ for imx/mxc.
>
> The SPARSE_IRQ support forces irqs allocation starting from 16. ?All
> those static irq number definition for SoCs need to shift 16 to keep
> non-DT boot works.
>
Do we really need to shift 16 to keep non-DT boot works?
I think that we can allocate "new irq numbers - NR_IRQS_LEGACY" in interrupt
controller in DT mode. And we needn't shift NR_IRQS_LEGACY in non-DT mode,
since irq numbers are already specified in .nr_irqs of machine description.
Maybe you can reference code in arch/arm/mach-mm/irq.c &
arch/arm/mach-mm/brownstone.c.
Regards
Haojian
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-14 7:40 ` Haojian Zhuang
@ 2012-06-14 7:55 ` Shawn Guo
0 siblings, 0 replies; 85+ messages in thread
From: Shawn Guo @ 2012-06-14 7:55 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 03:40:09PM +0800, Haojian Zhuang wrote:
> On Thu, Jun 14, 2012 at 1:59 PM, Shawn Guo <shawn.guo@linaro.org> wrote:
> > As all irqchips on imx have been changed to allocate their irq_descs,
> > and all unneeded mach/irqs.h inclusions on imx have been cleaned up,
> > now it's time to select SPARSE_IRQ for imx/mxc.
> >
> > The SPARSE_IRQ support forces irqs allocation starting from 16. ?All
> > those static irq number definition for SoCs need to shift 16 to keep
> > non-DT boot works.
> >
> Do we really need to shift 16 to keep non-DT boot works?
>
Yes, for my case.
> I think that we can allocate "new irq numbers - NR_IRQS_LEGACY" in interrupt
> controller in DT mode.
In DT mode, I need to do nothing about it, because with irqdomain
support, DT core will translate the hardware irq number encoded in
device tree to Linux irq. That said, platform_get_irq will
automatically return me Linux irq number.
> And we needn't shift NR_IRQS_LEGACY in non-DT mode,
> since irq numbers are already specified in .nr_irqs of machine description.
>
I took a different (IMO, cleaner) approach than setting .nr_irqs in
mach_desc. With all irqdescs dynamically allocated, I do not need
to set .nr_irqs to have irq core preallocate all these irqs. IMO,
that's the point of SPARSE_IRQ. To me, the .nr_irqs approach is just a
quick and dirty path to SPARSE_IRQ, but we gain nothing from that
except getting rid of platform NR_IRQS definition.
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-14 5:59 ` [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform Shawn Guo
2012-06-14 7:40 ` Haojian Zhuang
@ 2012-06-18 8:48 ` Dong Aisheng
2012-06-18 15:04 ` Shawn Guo
1 sibling, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-18 8:48 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:47PM +0800, Shawn Guo wrote:
> As all irqchips on imx have been changed to allocate their irq_descs,
> and all unneeded mach/irqs.h inclusions on imx have been cleaned up,
> now it's time to select SPARSE_IRQ for imx/mxc.
>
> The SPARSE_IRQ support forces irqs allocation starting from 16. All
> those static irq number definition for SoCs need to shift 16 to keep
> non-DT boot works.
>
It seems shift 16 is to get the correct linux virt irq, right?
If yes, i do not like this approach very much since it's an implicit way
based on users know how legacy irqdomain works internally.
Ideally i would see we keep the code as before that still using hw irqs
for device resource definition, but convert to linux virt irq in a standard
irqdomain map way when adding devices by calling imx_add_platform_device.
Regards
Dong Aisheng
> With all those static IRQ number and start definitions removed from
> mach/irqs.h, the header becomes just a container of a couple of
> mach-imx specific irq/fiq calls. Since mach/irqs.h is not included
> by asm/irq.h now, the users of mxc_set_irq_fiq needs to explicitly
> include mach/irqs.h themselves.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/plat-mxc/include/mach/irqs.h | 44 -------
> arch/arm/plat-mxc/include/mach/mx1.h | 111 +++++++++---------
> arch/arm/plat-mxc/include/mach/mx21.h | 107 ++++++++--------
> arch/arm/plat-mxc/include/mach/mx25.h | 72 ++++++-----
> arch/arm/plat-mxc/include/mach/mx27.h | 127 ++++++++++----------
> arch/arm/plat-mxc/include/mach/mx2x.h | 87 +++++++-------
> arch/arm/plat-mxc/include/mach/mx31.h | 118 +++++++++---------
> arch/arm/plat-mxc/include/mach/mx35.h | 109 +++++++++--------
> arch/arm/plat-mxc/include/mach/mx3x.h | 77 ++++++------
> arch/arm/plat-mxc/include/mach/mx50.h | 187 ++++++++++++++--------------
> arch/arm/plat-mxc/include/mach/mx51.h | 209 ++++++++++++++++----------------
> arch/arm/plat-mxc/include/mach/mx53.h | 217 +++++++++++++++++----------------
> drivers/media/video/mx1_camera.c | 1 +
> sound/soc/fsl/imx-pcm-fiq.c | 1 +
> 15 files changed, 722 insertions(+), 746 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 84449dd..63f40b4 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -446,6 +446,7 @@ config ARCH_MXC
> select CLKSRC_MMIO
> select GENERIC_IRQ_CHIP
> select MULTI_IRQ_HANDLER
> + select SPARSE_IRQ
> help
> Support for Freescale MXC/iMX-based family of processors
>
> diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
> index fd9efb0..d73f5e8 100644
> --- a/arch/arm/plat-mxc/include/mach/irqs.h
> +++ b/arch/arm/plat-mxc/include/mach/irqs.h
> @@ -11,50 +11,6 @@
> #ifndef __ASM_ARCH_MXC_IRQS_H__
> #define __ASM_ARCH_MXC_IRQS_H__
>
> -#include <asm-generic/gpio.h>
> -
> -/*
> - * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
> - * have 128 IRQs, and those with AVIC have 64.
> - *
> - * To support single image, the biggest number should be defined on
> - * top of the list.
> - */
> -#if defined CONFIG_ARM_GIC
> -#define MXC_INTERNAL_IRQS 160
> -#elif defined CONFIG_MXC_TZIC
> -#define MXC_INTERNAL_IRQS 128
> -#else
> -#define MXC_INTERNAL_IRQS 64
> -#endif
> -
> -#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
> -
> -/*
> - * The next 16 interrupts are for board specific purposes. Since
> - * the kernel can only run on one machine at a time, we can re-use
> - * these. If you need more, increase MXC_BOARD_IRQS, but keep it
> - * within sensible limits.
> - */
> -#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
> -
> -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
> -#define MXC_BOARD_IRQS 80
> -#else
> -#define MXC_BOARD_IRQS 16
> -#endif
> -
> -#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
> -
> -#ifdef CONFIG_MX3_IPU_IRQS
> -#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
> -#else
> -#define MX3_IPU_IRQS 0
> -#endif
> -/* REVISIT: Add IPU irqs on IMX51 */
> -
> -#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
> -
> extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
>
> /* all normal IRQs can be FIQs */
> diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
> index 2b7c08d..45bd31c 100644
> --- a/arch/arm/plat-mxc/include/mach/mx1.h
> +++ b/arch/arm/plat-mxc/include/mach/mx1.h
> @@ -78,61 +78,62 @@
> #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
>
> /* fixed interrput numbers */
> -#define MX1_INT_SOFTINT 0
> -#define MX1_INT_CSI 6
> -#define MX1_DSPA_MAC_INT 7
> -#define MX1_DSPA_INT 8
> -#define MX1_COMP_INT 9
> -#define MX1_MSHC_XINT 10
> -#define MX1_GPIO_INT_PORTA 11
> -#define MX1_GPIO_INT_PORTB 12
> -#define MX1_GPIO_INT_PORTC 13
> -#define MX1_INT_LCDC 14
> -#define MX1_SIM_INT 15
> -#define MX1_SIM_DATA_INT 16
> -#define MX1_RTC_INT 17
> -#define MX1_RTC_SAMINT 18
> -#define MX1_INT_UART2PFERR 19
> -#define MX1_INT_UART2RTS 20
> -#define MX1_INT_UART2DTR 21
> -#define MX1_INT_UART2UARTC 22
> -#define MX1_INT_UART2TX 23
> -#define MX1_INT_UART2RX 24
> -#define MX1_INT_UART1PFERR 25
> -#define MX1_INT_UART1RTS 26
> -#define MX1_INT_UART1DTR 27
> -#define MX1_INT_UART1UARTC 28
> -#define MX1_INT_UART1TX 29
> -#define MX1_INT_UART1RX 30
> -#define MX1_VOICE_DAC_INT 31
> -#define MX1_VOICE_ADC_INT 32
> -#define MX1_PEN_DATA_INT 33
> -#define MX1_PWM_INT 34
> -#define MX1_SDHC_INT 35
> -#define MX1_INT_I2C 39
> -#define MX1_INT_CSPI2 40
> -#define MX1_INT_CSPI1 41
> -#define MX1_SSI_TX_INT 42
> -#define MX1_SSI_TX_ERR_INT 43
> -#define MX1_SSI_RX_INT 44
> -#define MX1_SSI_RX_ERR_INT 45
> -#define MX1_TOUCH_INT 46
> -#define MX1_INT_USBD0 47
> -#define MX1_INT_USBD1 48
> -#define MX1_INT_USBD2 49
> -#define MX1_INT_USBD3 50
> -#define MX1_INT_USBD4 51
> -#define MX1_INT_USBD5 52
> -#define MX1_INT_USBD6 53
> -#define MX1_BTSYS_INT 55
> -#define MX1_BTTIM_INT 56
> -#define MX1_BTWUI_INT 57
> -#define MX1_TIM2_INT 58
> -#define MX1_TIM1_INT 59
> -#define MX1_DMA_ERR 60
> -#define MX1_DMA_INT 61
> -#define MX1_GPIO_INT_PORTD 62
> -#define MX1_WDT_INT 63
> +#include <asm/irq.h>
> +#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
> +#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
> +#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
> +#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
> +#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
> +#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
> +#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
> +#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
> +#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
> +#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
> +#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
> +#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
> +#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
> +#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
> +#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
> +#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
> +#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
> +#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
> +#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
> +#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
> +#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
> +#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
> +#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
> +#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
> +#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
> +#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
> +#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
> +#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
> +#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
> +#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
> +#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
> +#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
> +#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
> +#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
> +#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
> +#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
> +#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
> +#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
> +#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
> +#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
> +#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
> +#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
> +#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
> +#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
> +#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
> +#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
> +#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
> +#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
> +#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
> +#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
> +#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
> +#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
> +#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
> +#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
> +#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
>
> /* DMA */
> #define MX1_DMA_REQ_UART3_T 2
> diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
> index 6cd049e..468738a 100644
> --- a/arch/arm/plat-mxc/include/mach/mx21.h
> +++ b/arch/arm/plat-mxc/include/mach/mx21.h
> @@ -99,59 +99,60 @@
> #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
>
> /* fixed interrupt numbers */
> -#define MX21_INT_CSPI3 6
> -#define MX21_INT_GPIO 8
> -#define MX21_INT_FIRI 9
> -#define MX21_INT_SDHC2 10
> -#define MX21_INT_SDHC1 11
> -#define MX21_INT_I2C 12
> -#define MX21_INT_SSI2 13
> -#define MX21_INT_SSI1 14
> -#define MX21_INT_CSPI2 15
> -#define MX21_INT_CSPI1 16
> -#define MX21_INT_UART4 17
> -#define MX21_INT_UART3 18
> -#define MX21_INT_UART2 19
> -#define MX21_INT_UART1 20
> -#define MX21_INT_KPP 21
> -#define MX21_INT_RTC 22
> -#define MX21_INT_PWM 23
> -#define MX21_INT_GPT3 24
> -#define MX21_INT_GPT2 25
> -#define MX21_INT_GPT1 26
> -#define MX21_INT_WDOG 27
> -#define MX21_INT_PCMCIA 28
> -#define MX21_INT_NFC 29
> -#define MX21_INT_BMI 30
> -#define MX21_INT_CSI 31
> -#define MX21_INT_DMACH0 32
> -#define MX21_INT_DMACH1 33
> -#define MX21_INT_DMACH2 34
> -#define MX21_INT_DMACH3 35
> -#define MX21_INT_DMACH4 36
> -#define MX21_INT_DMACH5 37
> -#define MX21_INT_DMACH6 38
> -#define MX21_INT_DMACH7 39
> -#define MX21_INT_DMACH8 40
> -#define MX21_INT_DMACH9 41
> -#define MX21_INT_DMACH10 42
> -#define MX21_INT_DMACH11 43
> -#define MX21_INT_DMACH12 44
> -#define MX21_INT_DMACH13 45
> -#define MX21_INT_DMACH14 46
> -#define MX21_INT_DMACH15 47
> -#define MX21_INT_EMMAENC 49
> -#define MX21_INT_EMMADEC 50
> -#define MX21_INT_EMMAPRP 51
> -#define MX21_INT_EMMAPP 52
> -#define MX21_INT_USBWKUP 53
> -#define MX21_INT_USBDMA 54
> -#define MX21_INT_USBHOST 55
> -#define MX21_INT_USBFUNC 56
> -#define MX21_INT_USBMNP 57
> -#define MX21_INT_USBCTRL 58
> -#define MX21_INT_SLCDC 60
> -#define MX21_INT_LCDC 61
> +#include <asm/irq.h>
> +#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
> +#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
> +#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
> +#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
> +#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
> +#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
> +#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
> +#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
> +#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
> +#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
> +#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
> +#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
> +#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
> +#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
> +#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
> +#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
> +#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
> +#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
> +#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
> +#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
> +#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
> +#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
> +#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
> +#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
> +#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
> +#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
> +#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
> +#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
> +#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
> +#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
> +#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
> +#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
> +#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
> +#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
> +#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
> +#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
> +#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
> +#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
> +#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
> +#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
> +#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
> +#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
> +#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
> +#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
> +#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
> +#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
> +#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
> +#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
> +#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
> +#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
> +#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
> +#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
> +#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
>
> /* fixed DMA request numbers */
> #define MX21_DMA_REQ_CSPI3_RX 1
> diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
> index ccebf5b..627d94f 100644
> --- a/arch/arm/plat-mxc/include/mach/mx25.h
> +++ b/arch/arm/plat-mxc/include/mach/mx25.h
> @@ -61,40 +61,44 @@
> #define MX25_IO_P2V(x) IMX_IO_P2V(x)
> #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
>
> -#define MX25_INT_CSPI3 0
> -#define MX25_INT_I2C1 3
> -#define MX25_INT_I2C2 4
> -#define MX25_INT_UART4 5
> -#define MX25_INT_ESDHC2 8
> -#define MX25_INT_ESDHC1 9
> -#define MX25_INT_I2C3 10
> -#define MX25_INT_SSI2 11
> -#define MX25_INT_SSI1 12
> -#define MX25_INT_CSPI2 13
> -#define MX25_INT_CSPI1 14
> -#define MX25_INT_GPIO3 16
> -#define MX25_INT_CSI 17
> -#define MX25_INT_UART3 18
> -#define MX25_INT_GPIO4 23
> -#define MX25_INT_KPP 24
> -#define MX25_INT_DRYICE 25
> -#define MX25_INT_PWM1 26
> -#define MX25_INT_UART2 32
> -#define MX25_INT_NFC 33
> -#define MX25_INT_SDMA 34
> -#define MX25_INT_USB_HS 35
> -#define MX25_INT_PWM2 36
> -#define MX25_INT_USB_OTG 37
> -#define MX25_INT_LCDC 39
> -#define MX25_INT_UART5 40
> -#define MX25_INT_PWM3 41
> -#define MX25_INT_PWM4 42
> -#define MX25_INT_CAN1 43
> -#define MX25_INT_CAN2 44
> -#define MX25_INT_UART1 45
> -#define MX25_INT_GPIO2 51
> -#define MX25_INT_GPIO1 52
> -#define MX25_INT_FEC 57
> +/*
> + * Interrupt numbers
> + */
> +#include <asm/irq.h>
> +#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
> +#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
> +#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
> +#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
> +#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
> +#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
> +#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
> +#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
> +#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
> +#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
> +#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
> +#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
> +#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
> +#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
> +#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
> +#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
> +#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
> +#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
> +#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
> +#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
> +#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
> +#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
> +#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
> +#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
> +#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
> +#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
> +#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
> +#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
> +#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
> +#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
> +#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
> +#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
> +#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
> +#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
>
> #define MX25_DMA_REQ_SSI2_RX1 22
> #define MX25_DMA_REQ_SSI2_TX1 23
> diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
> index 6265357..e074616 100644
> --- a/arch/arm/plat-mxc/include/mach/mx27.h
> +++ b/arch/arm/plat-mxc/include/mach/mx27.h
> @@ -128,69 +128,70 @@
> #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
>
> /* fixed interrupt numbers */
> -#define MX27_INT_I2C2 1
> -#define MX27_INT_GPT6 2
> -#define MX27_INT_GPT5 3
> -#define MX27_INT_GPT4 4
> -#define MX27_INT_RTIC 5
> -#define MX27_INT_CSPI3 6
> -#define MX27_INT_SDHC 7
> -#define MX27_INT_GPIO 8
> -#define MX27_INT_SDHC3 9
> -#define MX27_INT_SDHC2 10
> -#define MX27_INT_SDHC1 11
> -#define MX27_INT_I2C1 12
> -#define MX27_INT_SSI2 13
> -#define MX27_INT_SSI1 14
> -#define MX27_INT_CSPI2 15
> -#define MX27_INT_CSPI1 16
> -#define MX27_INT_UART4 17
> -#define MX27_INT_UART3 18
> -#define MX27_INT_UART2 19
> -#define MX27_INT_UART1 20
> -#define MX27_INT_KPP 21
> -#define MX27_INT_RTC 22
> -#define MX27_INT_PWM 23
> -#define MX27_INT_GPT3 24
> -#define MX27_INT_GPT2 25
> -#define MX27_INT_GPT1 26
> -#define MX27_INT_WDOG 27
> -#define MX27_INT_PCMCIA 28
> -#define MX27_INT_NFC 29
> -#define MX27_INT_ATA 30
> -#define MX27_INT_CSI 31
> -#define MX27_INT_DMACH0 32
> -#define MX27_INT_DMACH1 33
> -#define MX27_INT_DMACH2 34
> -#define MX27_INT_DMACH3 35
> -#define MX27_INT_DMACH4 36
> -#define MX27_INT_DMACH5 37
> -#define MX27_INT_DMACH6 38
> -#define MX27_INT_DMACH7 39
> -#define MX27_INT_DMACH8 40
> -#define MX27_INT_DMACH9 41
> -#define MX27_INT_DMACH10 42
> -#define MX27_INT_DMACH11 43
> -#define MX27_INT_DMACH12 44
> -#define MX27_INT_DMACH13 45
> -#define MX27_INT_DMACH14 46
> -#define MX27_INT_DMACH15 47
> -#define MX27_INT_UART6 48
> -#define MX27_INT_UART5 49
> -#define MX27_INT_FEC 50
> -#define MX27_INT_EMMAPRP 51
> -#define MX27_INT_EMMAPP 52
> -#define MX27_INT_VPU 53
> -#define MX27_INT_USB_HS1 54
> -#define MX27_INT_USB_HS2 55
> -#define MX27_INT_USB_OTG 56
> -#define MX27_INT_SCC_SMN 57
> -#define MX27_INT_SCC_SCM 58
> -#define MX27_INT_SAHARA 59
> -#define MX27_INT_SLCDC 60
> -#define MX27_INT_LCDC 61
> -#define MX27_INT_IIM 62
> -#define MX27_INT_CCM 63
> +#include <asm/irq.h>
> +#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
> +#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
> +#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
> +#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
> +#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
> +#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
> +#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
> +#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
> +#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
> +#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
> +#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
> +#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
> +#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
> +#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
> +#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
> +#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
> +#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
> +#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
> +#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
> +#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
> +#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
> +#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
> +#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
> +#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
> +#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
> +#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
> +#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
> +#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
> +#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
> +#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
> +#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
> +#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
> +#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
> +#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
> +#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
> +#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
> +#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
> +#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
> +#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
> +#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
> +#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
> +#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
> +#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
> +#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
> +#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
> +#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
> +#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
> +#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
> +#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
> +#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
> +#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
> +#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
> +#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
> +#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
> +#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
> +#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
> +#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
> +#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
> +#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
> +#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
> +#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
> +#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
> +#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
>
> /* fixed DMA request numbers */
> #define MX27_DMA_REQ_CSPI3_RX 1
> diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
> index 6d07839..11642f5 100644
> --- a/arch/arm/plat-mxc/include/mach/mx2x.h
> +++ b/arch/arm/plat-mxc/include/mach/mx2x.h
> @@ -68,49 +68,50 @@
> #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
>
> /* fixed interrupt numbers */
> -#define MX2x_INT_CSPI3 6
> -#define MX2x_INT_GPIO 8
> -#define MX2x_INT_SDHC2 10
> -#define MX2x_INT_SDHC1 11
> -#define MX2x_INT_I2C 12
> -#define MX2x_INT_SSI2 13
> -#define MX2x_INT_SSI1 14
> -#define MX2x_INT_CSPI2 15
> -#define MX2x_INT_CSPI1 16
> -#define MX2x_INT_UART4 17
> -#define MX2x_INT_UART3 18
> -#define MX2x_INT_UART2 19
> -#define MX2x_INT_UART1 20
> -#define MX2x_INT_KPP 21
> -#define MX2x_INT_RTC 22
> -#define MX2x_INT_PWM 23
> -#define MX2x_INT_GPT3 24
> -#define MX2x_INT_GPT2 25
> -#define MX2x_INT_GPT1 26
> -#define MX2x_INT_WDOG 27
> -#define MX2x_INT_PCMCIA 28
> -#define MX2x_INT_NANDFC 29
> -#define MX2x_INT_CSI 31
> -#define MX2x_INT_DMACH0 32
> -#define MX2x_INT_DMACH1 33
> -#define MX2x_INT_DMACH2 34
> -#define MX2x_INT_DMACH3 35
> -#define MX2x_INT_DMACH4 36
> -#define MX2x_INT_DMACH5 37
> -#define MX2x_INT_DMACH6 38
> -#define MX2x_INT_DMACH7 39
> -#define MX2x_INT_DMACH8 40
> -#define MX2x_INT_DMACH9 41
> -#define MX2x_INT_DMACH10 42
> -#define MX2x_INT_DMACH11 43
> -#define MX2x_INT_DMACH12 44
> -#define MX2x_INT_DMACH13 45
> -#define MX2x_INT_DMACH14 46
> -#define MX2x_INT_DMACH15 47
> -#define MX2x_INT_EMMAPRP 51
> -#define MX2x_INT_EMMAPP 52
> -#define MX2x_INT_SLCDC 60
> -#define MX2x_INT_LCDC 61
> +#include <asm/irq.h>
> +#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
> +#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
> +#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
> +#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
> +#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
> +#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
> +#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
> +#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
> +#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
> +#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
> +#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
> +#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
> +#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
> +#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
> +#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
> +#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
> +#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
> +#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
> +#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
> +#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
> +#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
> +#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
> +#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
> +#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
> +#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
> +#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
> +#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
> +#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
> +#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
> +#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
> +#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
> +#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
> +#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
> +#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
> +#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
> +#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
> +#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
> +#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
> +#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
> +#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
> +#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
> +#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
> +#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
>
> /* fixed DMA request numbers */
> #define MX2x_DMA_REQ_CSPI3_RX 1
> diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
> index e27619e..dbced61 100644
> --- a/arch/arm/plat-mxc/include/mach/mx31.h
> +++ b/arch/arm/plat-mxc/include/mach/mx31.h
> @@ -118,63 +118,67 @@
> #define MX31_IO_P2V(x) IMX_IO_P2V(x)
> #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
>
> -#define MX31_INT_I2C3 3
> -#define MX31_INT_I2C2 4
> -#define MX31_INT_MPEG4_ENCODER 5
> -#define MX31_INT_RTIC 6
> -#define MX31_INT_FIRI 7
> -#define MX31_INT_SDHC2 8
> -#define MX31_INT_SDHC1 9
> -#define MX31_INT_I2C1 10
> -#define MX31_INT_SSI2 11
> -#define MX31_INT_SSI1 12
> -#define MX31_INT_CSPI2 13
> -#define MX31_INT_CSPI1 14
> -#define MX31_INT_ATA 15
> -#define MX31_INT_MBX 16
> -#define MX31_INT_CSPI3 17
> -#define MX31_INT_UART3 18
> -#define MX31_INT_IIM 19
> -#define MX31_INT_SIM2 20
> -#define MX31_INT_SIM1 21
> -#define MX31_INT_RNGA 22
> -#define MX31_INT_EVTMON 23
> -#define MX31_INT_KPP 24
> -#define MX31_INT_RTC 25
> -#define MX31_INT_PWM 26
> -#define MX31_INT_EPIT2 27
> -#define MX31_INT_EPIT1 28
> -#define MX31_INT_GPT 29
> -#define MX31_INT_POWER_FAIL 30
> -#define MX31_INT_CCM_DVFS 31
> -#define MX31_INT_UART2 32
> -#define MX31_INT_NFC 33
> -#define MX31_INT_SDMA 34
> -#define MX31_INT_USB_HS1 35
> -#define MX31_INT_USB_HS2 36
> -#define MX31_INT_USB_OTG 37
> -#define MX31_INT_MSHC1 39
> -#define MX31_INT_MSHC2 40
> -#define MX31_INT_IPU_ERR 41
> -#define MX31_INT_IPU_SYN 42
> -#define MX31_INT_UART1 45
> -#define MX31_INT_UART4 46
> -#define MX31_INT_UART5 47
> -#define MX31_INT_ECT 48
> -#define MX31_INT_SCC_SCM 49
> -#define MX31_INT_SCC_SMN 50
> -#define MX31_INT_GPIO2 51
> -#define MX31_INT_GPIO1 52
> -#define MX31_INT_CCM 53
> -#define MX31_INT_PCMCIA 54
> -#define MX31_INT_WDOG 55
> -#define MX31_INT_GPIO3 56
> -#define MX31_INT_EXT_POWER 58
> -#define MX31_INT_EXT_TEMPER 59
> -#define MX31_INT_EXT_SENSOR60 60
> -#define MX31_INT_EXT_SENSOR61 61
> -#define MX31_INT_EXT_WDOG 62
> -#define MX31_INT_EXT_TV 63
> +/*
> + * Interrupt numbers
> + */
> +#include <asm/irq.h>
> +#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
> +#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
> +#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
> +#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
> +#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
> +#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
> +#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
> +#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
> +#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
> +#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
> +#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
> +#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
> +#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
> +#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
> +#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
> +#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
> +#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
> +#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
> +#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
> +#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
> +#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
> +#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
> +#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
> +#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
> +#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
> +#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
> +#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
> +#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
> +#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
> +#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
> +#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
> +#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
> +#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
> +#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
> +#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
> +#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
> +#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
> +#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
> +#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
> +#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
> +#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
> +#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
> +#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
> +#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
> +#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
> +#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
> +#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
> +#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
> +#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
> +#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
> +#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
> +#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
> +#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
> +#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
> +#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
> +#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
> +#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
>
> #define MX31_DMA_REQ_SDHC1 20
> #define MX31_DMA_REQ_SDHC2 21
> diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
> index 80965a9..2af5d3a 100644
> --- a/arch/arm/plat-mxc/include/mach/mx35.h
> +++ b/arch/arm/plat-mxc/include/mach/mx35.h
> @@ -120,60 +120,61 @@
> /*
> * Interrupt numbers
> */
> -#define MX35_INT_OWIRE 2
> -#define MX35_INT_I2C3 3
> -#define MX35_INT_I2C2 4
> -#define MX35_INT_RTIC 6
> -#define MX35_INT_ESDHC1 7
> -#define MX35_INT_ESDHC2 8
> -#define MX35_INT_ESDHC3 9
> -#define MX35_INT_I2C1 10
> -#define MX35_INT_SSI1 11
> -#define MX35_INT_SSI2 12
> -#define MX35_INT_CSPI2 13
> -#define MX35_INT_CSPI1 14
> -#define MX35_INT_ATA 15
> -#define MX35_INT_GPU2D 16
> -#define MX35_INT_ASRC 17
> -#define MX35_INT_UART3 18
> -#define MX35_INT_IIM 19
> -#define MX35_INT_RNGA 22
> -#define MX35_INT_EVTMON 23
> -#define MX35_INT_KPP 24
> -#define MX35_INT_RTC 25
> -#define MX35_INT_PWM 26
> -#define MX35_INT_EPIT2 27
> -#define MX35_INT_EPIT1 28
> -#define MX35_INT_GPT 29
> -#define MX35_INT_POWER_FAIL 30
> -#define MX35_INT_UART2 32
> -#define MX35_INT_NFC 33
> -#define MX35_INT_SDMA 34
> -#define MX35_INT_USB_HS 35
> -#define MX35_INT_USB_OTG 37
> -#define MX35_INT_MSHC1 39
> -#define MX35_INT_ESAI 40
> -#define MX35_INT_IPU_ERR 41
> -#define MX35_INT_IPU_SYN 42
> -#define MX35_INT_CAN1 43
> -#define MX35_INT_CAN2 44
> -#define MX35_INT_UART1 45
> -#define MX35_INT_MLB 46
> -#define MX35_INT_SPDIF 47
> -#define MX35_INT_ECT 48
> -#define MX35_INT_SCC_SCM 49
> -#define MX35_INT_SCC_SMN 50
> -#define MX35_INT_GPIO2 51
> -#define MX35_INT_GPIO1 52
> -#define MX35_INT_WDOG 55
> -#define MX35_INT_GPIO3 56
> -#define MX35_INT_FEC 57
> -#define MX35_INT_EXT_POWER 58
> -#define MX35_INT_EXT_TEMPER 59
> -#define MX35_INT_EXT_SENSOR60 60
> -#define MX35_INT_EXT_SENSOR61 61
> -#define MX35_INT_EXT_WDOG 62
> -#define MX35_INT_EXT_TV 63
> +#include <asm/irq.h>
> +#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
> +#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
> +#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
> +#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
> +#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
> +#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
> +#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
> +#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
> +#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
> +#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
> +#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
> +#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
> +#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
> +#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
> +#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
> +#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
> +#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
> +#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
> +#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
> +#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
> +#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
> +#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
> +#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
> +#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
> +#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
> +#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
> +#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
> +#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
> +#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
> +#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
> +#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
> +#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
> +#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
> +#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
> +#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
> +#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
> +#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
> +#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
> +#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
> +#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
> +#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
> +#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
> +#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
> +#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
> +#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
> +#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
> +#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
> +#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
> +#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
> +#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
> +#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
> +#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
> +#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
> +#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
>
> #define MX35_DMA_REQ_SSI2_RX1 22
> #define MX35_DMA_REQ_SSI2_TX1 23
> diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
> index 30dbf42..96fb4fb 100644
> --- a/arch/arm/plat-mxc/include/mach/mx3x.h
> +++ b/arch/arm/plat-mxc/include/mach/mx3x.h
> @@ -143,44 +143,45 @@
> /*
> * Interrupt numbers
> */
> -#define MX3x_INT_I2C3 3
> -#define MX3x_INT_I2C2 4
> -#define MX3x_INT_RTIC 6
> -#define MX3x_INT_I2C 10
> -#define MX3x_INT_CSPI2 13
> -#define MX3x_INT_CSPI1 14
> -#define MX3x_INT_ATA 15
> -#define MX3x_INT_UART3 18
> -#define MX3x_INT_IIM 19
> -#define MX3x_INT_RNGA 22
> -#define MX3x_INT_EVTMON 23
> -#define MX3x_INT_KPP 24
> -#define MX3x_INT_RTC 25
> -#define MX3x_INT_PWM 26
> -#define MX3x_INT_EPIT2 27
> -#define MX3x_INT_EPIT1 28
> -#define MX3x_INT_GPT 29
> -#define MX3x_INT_POWER_FAIL 30
> -#define MX3x_INT_UART2 32
> -#define MX3x_INT_NANDFC 33
> -#define MX3x_INT_SDMA 34
> -#define MX3x_INT_MSHC1 39
> -#define MX3x_INT_IPU_ERR 41
> -#define MX3x_INT_IPU_SYN 42
> -#define MX3x_INT_UART1 45
> -#define MX3x_INT_ECT 48
> -#define MX3x_INT_SCC_SCM 49
> -#define MX3x_INT_SCC_SMN 50
> -#define MX3x_INT_GPIO2 51
> -#define MX3x_INT_GPIO1 52
> -#define MX3x_INT_WDOG 55
> -#define MX3x_INT_GPIO3 56
> -#define MX3x_INT_EXT_POWER 58
> -#define MX3x_INT_EXT_TEMPER 59
> -#define MX3x_INT_EXT_SENSOR60 60
> -#define MX3x_INT_EXT_SENSOR61 61
> -#define MX3x_INT_EXT_WDOG 62
> -#define MX3x_INT_EXT_TV 63
> +#include <asm/irq.h>
> +#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)
> +#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)
> +#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)
> +#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)
> +#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)
> +#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)
> +#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)
> +#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)
> +#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)
> +#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)
> +#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23)
> +#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24)
> +#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25)
> +#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26)
> +#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27)
> +#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28)
> +#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29)
> +#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
> +#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32)
> +#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33)
> +#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34)
> +#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39)
> +#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
> +#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
> +#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45)
> +#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48)
> +#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
> +#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
> +#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51)
> +#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52)
> +#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55)
> +#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56)
> +#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
> +#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
> +#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
> +#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
> +#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
> +#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63)
>
> #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
>
> diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
> index 5f2da75a..09ac19c 100644
> --- a/arch/arm/plat-mxc/include/mach/mx50.h
> +++ b/arch/arm/plat-mxc/include/mach/mx50.h
> @@ -188,99 +188,100 @@
> /*
> * Interrupt numbers
> */
> -#define MX50_INT_MMC_SDHC1 1
> -#define MX50_INT_MMC_SDHC2 2
> -#define MX50_INT_MMC_SDHC3 3
> -#define MX50_INT_MMC_SDHC4 4
> -#define MX50_INT_DAP 5
> -#define MX50_INT_SDMA 6
> -#define MX50_INT_IOMUX 7
> -#define MX50_INT_UART4 13
> -#define MX50_INT_USB_H1 14
> -#define MX50_INT_USB_OTG 18
> -#define MX50_INT_DATABAHN 19
> -#define MX50_INT_ELCDIF 20
> -#define MX50_INT_EPXP 21
> -#define MX50_INT_SRTC_NTZ 24
> -#define MX50_INT_SRTC_TZ 25
> -#define MX50_INT_EPDC 27
> -#define MX50_INT_NIC 28
> -#define MX50_INT_SSI1 29
> -#define MX50_INT_SSI2 30
> -#define MX50_INT_UART1 31
> -#define MX50_INT_UART2 32
> -#define MX50_INT_UART3 33
> -#define MX50_INT_RESV34 34
> -#define MX50_INT_RESV35 35
> -#define MX50_INT_CSPI1 36
> -#define MX50_INT_CSPI2 37
> -#define MX50_INT_CSPI 38
> -#define MX50_INT_GPT 39
> -#define MX50_INT_EPIT1 40
> -#define MX50_INT_GPIO1_INT7 42
> -#define MX50_INT_GPIO1_INT6 43
> -#define MX50_INT_GPIO1_INT5 44
> -#define MX50_INT_GPIO1_INT4 45
> -#define MX50_INT_GPIO1_INT3 46
> -#define MX50_INT_GPIO1_INT2 47
> -#define MX50_INT_GPIO1_INT1 48
> -#define MX50_INT_GPIO1_INT0 49
> -#define MX50_INT_GPIO1_LOW 50
> -#define MX50_INT_GPIO1_HIGH 51
> -#define MX50_INT_GPIO2_LOW 52
> -#define MX50_INT_GPIO2_HIGH 53
> -#define MX50_INT_GPIO3_LOW 54
> -#define MX50_INT_GPIO3_HIGH 55
> -#define MX50_INT_GPIO4_LOW 56
> -#define MX50_INT_GPIO4_HIGH 57
> -#define MX50_INT_WDOG1 58
> -#define MX50_INT_KPP 60
> -#define MX50_INT_PWM1 61
> -#define MX50_INT_I2C1 62
> -#define MX50_INT_I2C2 63
> -#define MX50_INT_I2C3 64
> -#define MX50_INT_RESV65 65
> -#define MX50_INT_DCDC 66
> -#define MX50_INT_THERMAL_ALARM 67
> -#define MX50_INT_ANA3 68
> -#define MX50_INT_ANA4 69
> -#define MX50_INT_CCM1 71
> -#define MX50_INT_CCM2 72
> -#define MX50_INT_GPC1 73
> -#define MX50_INT_GPC2 74
> -#define MX50_INT_SRC 75
> -#define MX50_INT_NM 76
> -#define MX50_INT_PMU 77
> -#define MX50_INT_CTI_IRQ 78
> -#define MX50_INT_CTI1_TG0 79
> -#define MX50_INT_CTI1_TG1 80
> -#define MX50_INT_GPU2_IRQ 84
> -#define MX50_INT_GPU2_BUSY 85
> -#define MX50_INT_UART5 86
> -#define MX50_INT_FEC 87
> -#define MX50_INT_OWIRE 88
> -#define MX50_INT_CTI1_TG2 89
> -#define MX50_INT_SJC 90
> -#define MX50_INT_DCP_CHAN1_3 91
> -#define MX50_INT_DCP_CHAN0 92
> -#define MX50_INT_PWM2 94
> -#define MX50_INT_RNGB 97
> -#define MX50_INT_CTI1_TG3 98
> -#define MX50_INT_RAWNAND_BCH 100
> -#define MX50_INT_RAWNAND_GPMI 102
> -#define MX50_INT_GPIO5_LOW 103
> -#define MX50_INT_GPIO5_HIGH 104
> -#define MX50_INT_GPIO6_LOW 105
> -#define MX50_INT_GPIO6_HIGH 106
> -#define MX50_INT_MSHC 109
> -#define MX50_INT_APBHDMA_CHAN0 110
> -#define MX50_INT_APBHDMA_CHAN1 111
> -#define MX50_INT_APBHDMA_CHAN2 112
> -#define MX50_INT_APBHDMA_CHAN3 113
> -#define MX50_INT_APBHDMA_CHAN4 114
> -#define MX50_INT_APBHDMA_CHAN5 115
> -#define MX50_INT_APBHDMA_CHAN6 116
> -#define MX50_INT_APBHDMA_CHAN7 117
> +#include <asm/irq.h>
> +#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
> +#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
> +#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
> +#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
> +#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
> +#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
> +#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
> +#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
> +#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
> +#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
> +#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
> +#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
> +#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
> +#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
> +#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
> +#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
> +#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
> +#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
> +#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
> +#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
> +#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
> +#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
> +#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
> +#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
> +#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
> +#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
> +#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
> +#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
> +#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
> +#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
> +#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
> +#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
> +#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
> +#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
> +#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
> +#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
> +#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
> +#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
> +#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
> +#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
> +#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
> +#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
> +#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
> +#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
> +#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
> +#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
> +#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
> +#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
> +#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
> +#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
> +#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
> +#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
> +#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
> +#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
> +#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
> +#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
> +#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
> +#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
> +#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
> +#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
> +#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
> +#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
> +#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
> +#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
> +#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
> +#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
> +#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
> +#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
> +#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
> +#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
> +#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
> +#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
> +#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
> +#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
> +#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
> +#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
> +#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
> +#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
> +#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
> +#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
> +#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
> +#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
> +#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
> +#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
> +#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
> +#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
> +#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
> +#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
> +#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
> +#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
> +#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
> +#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
> +#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
>
> #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
> extern int mx50_revision(void);
> diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
> index cdf07c6..af844f7 100644
> --- a/arch/arm/plat-mxc/include/mach/mx51.h
> +++ b/arch/arm/plat-mxc/include/mach/mx51.h
> @@ -232,110 +232,111 @@
> /*
> * Interrupt numbers
> */
> -#define MX51_INT_BASE 0
> -#define MX51_INT_RESV0 0
> -#define MX51_INT_ESDHC1 1
> -#define MX51_INT_ESDHC2 2
> -#define MX51_INT_ESDHC3 3
> -#define MX51_INT_ESDHC4 4
> -#define MX51_INT_RESV5 5
> -#define MX51_INT_SDMA 6
> -#define MX51_INT_IOMUX 7
> -#define MX51_INT_NFC 8
> -#define MX51_INT_VPU 9
> -#define MX51_INT_IPU_ERR 10
> -#define MX51_INT_IPU_SYN 11
> -#define MX51_INT_GPU 12
> -#define MX51_INT_RESV13 13
> -#define MX51_INT_USB_HS1 14
> -#define MX51_INT_EMI 15
> -#define MX51_INT_USB_HS2 16
> -#define MX51_INT_USB_HS3 17
> -#define MX51_INT_USB_OTG 18
> -#define MX51_INT_SAHARA_H0 19
> -#define MX51_INT_SAHARA_H1 20
> -#define MX51_INT_SCC_SMN 21
> -#define MX51_INT_SCC_STZ 22
> -#define MX51_INT_SCC_SCM 23
> -#define MX51_INT_SRTC_NTZ 24
> -#define MX51_INT_SRTC_TZ 25
> -#define MX51_INT_RTIC 26
> -#define MX51_INT_CSU 27
> -#define MX51_INT_SLIM_B 28
> -#define MX51_INT_SSI1 29
> -#define MX51_INT_SSI2 30
> -#define MX51_INT_UART1 31
> -#define MX51_INT_UART2 32
> -#define MX51_INT_UART3 33
> -#define MX51_INT_RESV34 34
> -#define MX51_INT_RESV35 35
> -#define MX51_INT_ECSPI1 36
> -#define MX51_INT_ECSPI2 37
> -#define MX51_INT_CSPI 38
> -#define MX51_INT_GPT 39
> -#define MX51_INT_EPIT1 40
> -#define MX51_INT_EPIT2 41
> -#define MX51_INT_GPIO1_INT7 42
> -#define MX51_INT_GPIO1_INT6 43
> -#define MX51_INT_GPIO1_INT5 44
> -#define MX51_INT_GPIO1_INT4 45
> -#define MX51_INT_GPIO1_INT3 46
> -#define MX51_INT_GPIO1_INT2 47
> -#define MX51_INT_GPIO1_INT1 48
> -#define MX51_INT_GPIO1_INT0 49
> -#define MX51_INT_GPIO1_LOW 50
> -#define MX51_INT_GPIO1_HIGH 51
> -#define MX51_INT_GPIO2_LOW 52
> -#define MX51_INT_GPIO2_HIGH 53
> -#define MX51_INT_GPIO3_LOW 54
> -#define MX51_INT_GPIO3_HIGH 55
> -#define MX51_INT_GPIO4_LOW 56
> -#define MX51_INT_GPIO4_HIGH 57
> -#define MX51_INT_WDOG1 58
> -#define MX51_INT_WDOG2 59
> -#define MX51_INT_KPP 60
> -#define MX51_INT_PWM1 61
> -#define MX51_INT_I2C1 62
> -#define MX51_INT_I2C2 63
> -#define MX51_INT_HS_I2C 64
> -#define MX51_INT_RESV65 65
> -#define MX51_INT_RESV66 66
> -#define MX51_INT_SIM_IPB 67
> -#define MX51_INT_SIM_DAT 68
> -#define MX51_INT_IIM 69
> -#define MX51_INT_ATA 70
> -#define MX51_INT_CCM1 71
> -#define MX51_INT_CCM2 72
> -#define MX51_INT_GPC1 73
> -#define MX51_INT_GPC2 74
> -#define MX51_INT_SRC 75
> -#define MX51_INT_NM 76
> -#define MX51_INT_PMU 77
> -#define MX51_INT_CTI_IRQ 78
> -#define MX51_INT_CTI1_TG0 79
> -#define MX51_INT_CTI1_TG1 80
> -#define MX51_INT_MCG_ERR 81
> -#define MX51_INT_MCG_TMR 82
> -#define MX51_INT_MCG_FUNC 83
> -#define MX51_INT_GPU2_IRQ 84
> -#define MX51_INT_GPU2_BUSY 85
> -#define MX51_INT_RESV86 86
> -#define MX51_INT_FEC 87
> -#define MX51_INT_OWIRE 88
> -#define MX51_INT_CTI1_TG2 89
> -#define MX51_INT_SJC 90
> -#define MX51_INT_SPDIF 91
> -#define MX51_INT_TVE 92
> -#define MX51_INT_FIRI 93
> -#define MX51_INT_PWM2 94
> -#define MX51_INT_SLIM_EXP 95
> -#define MX51_INT_SSI3 96
> -#define MX51_INT_EMI_BOOT 97
> -#define MX51_INT_CTI1_TG3 98
> -#define MX51_INT_SMC_RX 99
> -#define MX51_INT_VPU_IDLE 100
> -#define MX51_INT_EMI_NFC 101
> -#define MX51_INT_GPU_IDLE 102
> +#include <asm/irq.h>
> +#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
> +#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
> +#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
> +#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
> +#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
> +#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
> +#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
> +#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
> +#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
> +#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
> +#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
> +#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
> +#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
> +#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
> +#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
> +#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
> +#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
> +#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
> +#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
> +#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
> +#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
> +#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
> +#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
> +#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
> +#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
> +#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
> +#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
> +#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
> +#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
> +#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
> +#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
> +#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
> +#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
> +#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
> +#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
> +#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
> +#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
> +#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
> +#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
> +#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
> +#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
> +#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
> +#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
> +#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
> +#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
> +#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
> +#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
> +#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
> +#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
> +#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
> +#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
> +#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
> +#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
> +#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
> +#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
> +#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
> +#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
> +#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
> +#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
> +#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
> +#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
> +#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
> +#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
> +#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
> +#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
> +#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
> +#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
> +#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
> +#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
> +#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
> +#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
> +#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
> +#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
> +#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
> +#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
> +#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
> +#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
> +#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
> +#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
> +#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
> +#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
> +#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
> +#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
> +#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
> +#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
> +#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
> +#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
> +#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
> +#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
> +#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
> +#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
> +#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
> +#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
> +#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
> +#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
> +#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
> +#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
> +#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
> +#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
> +#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
> +#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
> +#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
> +#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
> +#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
>
> #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
> extern int mx51_revision(void);
> diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
> index a37e8c3..f829d1c 100644
> --- a/arch/arm/plat-mxc/include/mach/mx53.h
> +++ b/arch/arm/plat-mxc/include/mach/mx53.h
> @@ -229,113 +229,114 @@
> /*
> * Interrupt numbers
> */
> -#define MX53_INT_RESV0 0
> -#define MX53_INT_ESDHC1 1
> -#define MX53_INT_ESDHC2 2
> -#define MX53_INT_ESDHC3 3
> -#define MX53_INT_ESDHC4 4
> -#define MX53_INT_DAP 5
> -#define MX53_INT_SDMA 6
> -#define MX53_INT_IOMUX 7
> -#define MX53_INT_NFC 8
> -#define MX53_INT_VPU 9
> -#define MX53_INT_IPU_ERR 10
> -#define MX53_INT_IPU_SYN 11
> -#define MX53_INT_GPU 12
> -#define MX53_INT_UART4 13
> -#define MX53_INT_USB_H1 14
> -#define MX53_INT_EMI 15
> -#define MX53_INT_USB_H2 16
> -#define MX53_INT_USB_H3 17
> -#define MX53_INT_USB_OTG 18
> -#define MX53_INT_SAHARA_H0 19
> -#define MX53_INT_SAHARA_H1 20
> -#define MX53_INT_SCC_SMN 21
> -#define MX53_INT_SCC_STZ 22
> -#define MX53_INT_SCC_SCM 23
> -#define MX53_INT_SRTC_NTZ 24
> -#define MX53_INT_SRTC_TZ 25
> -#define MX53_INT_RTIC 26
> -#define MX53_INT_CSU 27
> -#define MX53_INT_SATA 28
> -#define MX53_INT_SSI1 29
> -#define MX53_INT_SSI2 30
> -#define MX53_INT_UART1 31
> -#define MX53_INT_UART2 32
> -#define MX53_INT_UART3 33
> -#define MX53_INT_RTC 34
> -#define MX53_INT_PTP 35
> -#define MX53_INT_ECSPI1 36
> -#define MX53_INT_ECSPI2 37
> -#define MX53_INT_CSPI 38
> -#define MX53_INT_GPT 39
> -#define MX53_INT_EPIT1 40
> -#define MX53_INT_EPIT2 41
> -#define MX53_INT_GPIO1_INT7 42
> -#define MX53_INT_GPIO1_INT6 43
> -#define MX53_INT_GPIO1_INT5 44
> -#define MX53_INT_GPIO1_INT4 45
> -#define MX53_INT_GPIO1_INT3 46
> -#define MX53_INT_GPIO1_INT2 47
> -#define MX53_INT_GPIO1_INT1 48
> -#define MX53_INT_GPIO1_INT0 49
> -#define MX53_INT_GPIO1_LOW 50
> -#define MX53_INT_GPIO1_HIGH 51
> -#define MX53_INT_GPIO2_LOW 52
> -#define MX53_INT_GPIO2_HIGH 53
> -#define MX53_INT_GPIO3_LOW 54
> -#define MX53_INT_GPIO3_HIGH 55
> -#define MX53_INT_GPIO4_LOW 56
> -#define MX53_INT_GPIO4_HIGH 57
> -#define MX53_INT_WDOG1 58
> -#define MX53_INT_WDOG2 59
> -#define MX53_INT_KPP 60
> -#define MX53_INT_PWM1 61
> -#define MX53_INT_I2C1 62
> -#define MX53_INT_I2C2 63
> -#define MX53_INT_I2C3 64
> -#define MX53_INT_MLB 65
> -#define MX53_INT_ASRC 66
> -#define MX53_INT_SPDIF 67
> -#define MX53_INT_SIM_DAT 68
> -#define MX53_INT_IIM 69
> -#define MX53_INT_ATA 70
> -#define MX53_INT_CCM1 71
> -#define MX53_INT_CCM2 72
> -#define MX53_INT_GPC1 73
> -#define MX53_INT_GPC2 74
> -#define MX53_INT_SRC 75
> -#define MX53_INT_NM 76
> -#define MX53_INT_PMU 77
> -#define MX53_INT_CTI_IRQ 78
> -#define MX53_INT_CTI1_TG0 79
> -#define MX53_INT_CTI1_TG1 80
> -#define MX53_INT_ESAI 81
> -#define MX53_INT_CAN1 82
> -#define MX53_INT_CAN2 83
> -#define MX53_INT_GPU2_IRQ 84
> -#define MX53_INT_GPU2_BUSY 85
> -#define MX53_INT_UART5 86
> -#define MX53_INT_FEC 87
> -#define MX53_INT_OWIRE 88
> -#define MX53_INT_CTI1_TG2 89
> -#define MX53_INT_SJC 90
> -#define MX53_INT_TVE 92
> -#define MX53_INT_FIRI 93
> -#define MX53_INT_PWM2 94
> -#define MX53_INT_SLIM_EXP 95
> -#define MX53_INT_SSI3 96
> -#define MX53_INT_EMI_BOOT 97
> -#define MX53_INT_CTI1_TG3 98
> -#define MX53_INT_SMC_RX 99
> -#define MX53_INT_VPU_IDLE 100
> -#define MX53_INT_EMI_NFC 101
> -#define MX53_INT_GPU_IDLE 102
> -#define MX53_INT_GPIO5_LOW 103
> -#define MX53_INT_GPIO5_HIGH 104
> -#define MX53_INT_GPIO6_LOW 105
> -#define MX53_INT_GPIO6_HIGH 106
> -#define MX53_INT_GPIO7_LOW 107
> -#define MX53_INT_GPIO7_HIGH 108
> +#include <asm/irq.h>
> +#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0)
> +#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
> +#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
> +#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
> +#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
> +#define MX53_INT_DAP (NR_IRQS_LEGACY + 5)
> +#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6)
> +#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7)
> +#define MX53_INT_NFC (NR_IRQS_LEGACY + 8)
> +#define MX53_INT_VPU (NR_IRQS_LEGACY + 9)
> +#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
> +#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
> +#define MX53_INT_GPU (NR_IRQS_LEGACY + 12)
> +#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13)
> +#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14)
> +#define MX53_INT_EMI (NR_IRQS_LEGACY + 15)
> +#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16)
> +#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17)
> +#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18)
> +#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
> +#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
> +#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
> +#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
> +#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
> +#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
> +#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
> +#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26)
> +#define MX53_INT_CSU (NR_IRQS_LEGACY + 27)
> +#define MX53_INT_SATA (NR_IRQS_LEGACY + 28)
> +#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29)
> +#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30)
> +#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31)
> +#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32)
> +#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33)
> +#define MX53_INT_RTC (NR_IRQS_LEGACY + 34)
> +#define MX53_INT_PTP (NR_IRQS_LEGACY + 35)
> +#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
> +#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
> +#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38)
> +#define MX53_INT_GPT (NR_IRQS_LEGACY + 39)
> +#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40)
> +#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41)
> +#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
> +#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
> +#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
> +#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
> +#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
> +#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
> +#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
> +#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
> +#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
> +#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
> +#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
> +#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
> +#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
> +#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
> +#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
> +#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
> +#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58)
> +#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59)
> +#define MX53_INT_KPP (NR_IRQS_LEGACY + 60)
> +#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61)
> +#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62)
> +#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63)
> +#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64)
> +#define MX53_INT_MLB (NR_IRQS_LEGACY + 65)
> +#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66)
> +#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67)
> +#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
> +#define MX53_INT_IIM (NR_IRQS_LEGACY + 69)
> +#define MX53_INT_ATA (NR_IRQS_LEGACY + 70)
> +#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71)
> +#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72)
> +#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73)
> +#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74)
> +#define MX53_INT_SRC (NR_IRQS_LEGACY + 75)
> +#define MX53_INT_NM (NR_IRQS_LEGACY + 76)
> +#define MX53_INT_PMU (NR_IRQS_LEGACY + 77)
> +#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
> +#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
> +#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
> +#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81)
> +#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82)
> +#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83)
> +#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
> +#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
> +#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86)
> +#define MX53_INT_FEC (NR_IRQS_LEGACY + 87)
> +#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88)
> +#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
> +#define MX53_INT_SJC (NR_IRQS_LEGACY + 90)
> +#define MX53_INT_TVE (NR_IRQS_LEGACY + 92)
> +#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93)
> +#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94)
> +#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
> +#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96)
> +#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
> +#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
> +#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99)
> +#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
> +#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
> +#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
> +#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
> +#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
> +#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
> +#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
> +#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107)
> +#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108)
>
> #endif /* ifndef __MACH_MX53_H__ */
> diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
> index 4296a83..d2e6f82 100644
> --- a/drivers/media/video/mx1_camera.c
> +++ b/drivers/media/video/mx1_camera.c
> @@ -43,6 +43,7 @@
> #include <asm/fiq.h>
> #include <mach/dma-mx1-mx2.h>
> #include <mach/hardware.h>
> +#include <mach/irqs.h>
> #include <mach/mx1_camera.h>
>
> /*
> diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
> index 456b7d7..ee27ba3 100644
> --- a/sound/soc/fsl/imx-pcm-fiq.c
> +++ b/sound/soc/fsl/imx-pcm-fiq.c
> @@ -29,6 +29,7 @@
>
> #include <asm/fiq.h>
>
> +#include <mach/irqs.h>
> #include <mach/ssi.h>
>
> #include "imx-ssi.h"
> --
> 1.7.5.4
>
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-18 8:48 ` Dong Aisheng
@ 2012-06-18 15:04 ` Shawn Guo
2012-06-19 6:16 ` Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-18 15:04 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jun 18, 2012 at 04:48:53PM +0800, Dong Aisheng wrote:
> On Thu, Jun 14, 2012 at 01:59:47PM +0800, Shawn Guo wrote:
> > As all irqchips on imx have been changed to allocate their irq_descs,
> > and all unneeded mach/irqs.h inclusions on imx have been cleaned up,
> > now it's time to select SPARSE_IRQ for imx/mxc.
> >
> > The SPARSE_IRQ support forces irqs allocation starting from 16. All
> > those static irq number definition for SoCs need to shift 16 to keep
> > non-DT boot works.
> >
> It seems shift 16 is to get the correct linux virt irq, right?
Yes.
> If yes, i do not like this approach very much since it's an implicit way
> based on users know how legacy irqdomain works internally.
>
I do not quite follow on this. Users do not need to know how legacy
irqdomain works internally. They are still using those static MX*_INT_*
macros. All they need to know is there is a 16 shift between hardware
irq and Linux irq number when they look at /proc/interrupts.
> Ideally i would see we keep the code as before that still using hw irqs
> for device resource definition, but convert to linux virt irq in a standard
> irqdomain map way when adding devices by calling imx_add_platform_device.
>
What's the point of hiding this irq number conversion in
imx_add_platform_device? The irq number used in resource definition
should simply just be Linux irq. Doing what you suggest here will
only confuse users when they look at /proc/interrupts and those static
IRQ definitions.
BTW, not all the platform_devices are added by calling
imx_add_platform_device on imx.
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-18 15:04 ` Shawn Guo
@ 2012-06-19 6:16 ` Dong Aisheng
2012-06-19 6:47 ` Shawn Guo
0 siblings, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-19 6:16 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jun 18, 2012 at 11:04:24PM +0800, Shawn Guo wrote:
> On Mon, Jun 18, 2012 at 04:48:53PM +0800, Dong Aisheng wrote:
> > On Thu, Jun 14, 2012 at 01:59:47PM +0800, Shawn Guo wrote:
> > > As all irqchips on imx have been changed to allocate their irq_descs,
> > > and all unneeded mach/irqs.h inclusions on imx have been cleaned up,
> > > now it's time to select SPARSE_IRQ for imx/mxc.
> > >
> > > The SPARSE_IRQ support forces irqs allocation starting from 16. All
> > > those static irq number definition for SoCs need to shift 16 to keep
> > > non-DT boot works.
> > >
> > It seems shift 16 is to get the correct linux virt irq, right?
> Yes.
>
> > If yes, i do not like this approach very much since it's an implicit way
> > based on users know how legacy irqdomain works internally.
> >
> I do not quite follow on this. Users do not need to know how legacy
> irqdomain works internally. They are still using those static MX*_INT_*
> macros. All they need to know is there is a 16 shift between hardware
> irq and Linux irq number when they look at /proc/interrupts.
>
Hmm, i mean 'users' driver onwers here.
You shift 16 because you know after irqdomain map the virt irq will be shifting 16
according current status.
It may not always correct if something changes.
For example, if more irq ranges were pre-allocated except NR_IRQS_LEGACY by
someone else or if the irq domain type is changed by the driver.
In above case, i wonder the manual shifting may not work anymore.
With irqdomain support, i think we should always using the standard way
to get the virt irq number rather than assuming how virt irq ranges is used and what's the
irqdomain reverse map type is and using the virt irq directly.
> > Ideally i would see we keep the code as before that still using hw irqs
> > for device resource definition, but convert to linux virt irq in a standard
> > irqdomain map way when adding devices by calling imx_add_platform_device.
> >
> What's the point of hiding this irq number conversion in
> imx_add_platform_device?
It's standard and safe way.
> The irq number used in resource definition
> should simply just be Linux irq. Doing what you suggest here will
No, it's should be hw irq.
Like you did for gpio driver:
generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
Using irq_find_mapping to get the correct linux virt irq number.
> only confuse users when they look at /proc/interrupts and those static
> IRQ definitions.
I think we may need more information about irqdomain in /proc/inerrupts
or some where else to make people understand easily when have irq domain
support.
>
> BTW, not all the platform_devices are added by calling
> imx_add_platform_device on imx.
>
Then, we may need find way to do same thing for them too.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-19 6:16 ` Dong Aisheng
@ 2012-06-19 6:47 ` Shawn Guo
2012-06-19 7:21 ` Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-19 6:47 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jun 19, 2012 at 02:16:38PM +0800, Dong Aisheng wrote:
> > > Ideally i would see we keep the code as before that still using hw irqs
> > > for device resource definition, but convert to linux virt irq in a standard
> > > irqdomain map way when adding devices by calling imx_add_platform_device.
> > >
> > What's the point of hiding this irq number conversion in
> > imx_add_platform_device?
> It's standard and safe way.
>
Why do you think it's standard? Care to show me a couple of examples
that make this conversion when adding platform device?
> > The irq number used in resource definition
> > should simply just be Linux irq. Doing what you suggest here will
> No, it's should be hw irq.
You are simply wrong here. Nothing more to respond on this.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-19 6:47 ` Shawn Guo
@ 2012-06-19 7:21 ` Dong Aisheng
2012-06-19 7:43 ` Shawn Guo
0 siblings, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-19 7:21 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jun 19, 2012 at 02:47:44PM +0800, Shawn Guo wrote:
> On Tue, Jun 19, 2012 at 02:16:38PM +0800, Dong Aisheng wrote:
> > > > Ideally i would see we keep the code as before that still using hw irqs
> > > > for device resource definition, but convert to linux virt irq in a standard
> > > > irqdomain map way when adding devices by calling imx_add_platform_device.
> > > >
> > > What's the point of hiding this irq number conversion in
> > > imx_add_platform_device?
> > It's standard and safe way.
> >
> Why do you think it's standard?
Why do you think using irq_find_mapping to get the linux virt irq is not
standard way?
> Care to show me a couple of examples
> that make this conversion when adding platform device?
>
I did not search any example, currently it's just my idea based on my understanding
on irq domain design. Maybe i should give a patch to describe my idea,
then we can discuss on the patch.
Or did you see any example on using shift way to define device irq resource?
Then i can look at it.
> > > The irq number used in resource definition
> > > should simply just be Linux irq. Doing what you suggest here will
> > No, it's should be hw irq.
>
> You are simply wrong here. Nothing more to respond on this.
>
If using linux virt irq, how do we avoid the issues i said in my last reply?
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-19 7:21 ` Dong Aisheng
@ 2012-06-19 7:43 ` Shawn Guo
2012-06-19 13:01 ` Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-19 7:43 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jun 19, 2012 at 03:21:11PM +0800, Dong Aisheng wrote:
> On Tue, Jun 19, 2012 at 02:47:44PM +0800, Shawn Guo wrote:
> > On Tue, Jun 19, 2012 at 02:16:38PM +0800, Dong Aisheng wrote:
> > > > > Ideally i would see we keep the code as before that still using hw irqs
> > > > > for device resource definition, but convert to linux virt irq in a standard
> > > > > irqdomain map way when adding devices by calling imx_add_platform_device.
> > > > >
> > > > What's the point of hiding this irq number conversion in
> > > > imx_add_platform_device?
> > > It's standard and safe way.
> > >
> > Why do you think it's standard?
> Why do you think using irq_find_mapping to get the linux virt irq is not
> standard way?
>
I never said using irq_find_mapping to get the linux irq is not
standard way. What I said is using it during adding platform_device
is nothing standard.
> > Care to show me a couple of examples
> > that make this conversion when adding platform device?
> >
> I did not search any example, currently it's just my idea based on my understanding
> on irq domain design. Maybe i should give a patch to describe my idea,
> then we can discuss on the patch.
>
I understand your idea, and I just do not think it's a good/right one.
> Or did you see any example on using shift way to define device irq resource?
> Then i can look at it.
>
http://thread.gmane.org/gmane.linux.ports.arm.kernel/171075
> > > > The irq number used in resource definition
> > > > should simply just be Linux irq. Doing what you suggest here will
> > > No, it's should be hw irq.
> >
> > You are simply wrong here. Nothing more to respond on this.
> >
> If using linux virt irq, how do we avoid the issues i said in my last reply?
>
Do not make up any issue. I'm only interesting in the practical issues.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 16/16] ARM: imx: enable SPARSE_IRQ for imx platform
2012-06-19 7:43 ` Shawn Guo
@ 2012-06-19 13:01 ` Dong Aisheng
2012-06-19 13:19 ` [RFC PATCH 1/1] ARM: imx: enable SPARSE_IRQ for imx Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-19 13:01 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jun 19, 2012 at 03:43:00PM +0800, Shawn Guo wrote:
> On Tue, Jun 19, 2012 at 03:21:11PM +0800, Dong Aisheng wrote:
> > On Tue, Jun 19, 2012 at 02:47:44PM +0800, Shawn Guo wrote:
> > > On Tue, Jun 19, 2012 at 02:16:38PM +0800, Dong Aisheng wrote:
> > > > > > Ideally i would see we keep the code as before that still using hw irqs
> > > > > > for device resource definition, but convert to linux virt irq in a standard
> > > > > > irqdomain map way when adding devices by calling imx_add_platform_device.
> > > > > >
> > > > > What's the point of hiding this irq number conversion in
> > > > > imx_add_platform_device?
> > > > It's standard and safe way.
> > > >
> > > Why do you think it's standard?
> > Why do you think using irq_find_mapping to get the linux virt irq is not
> > standard way?
> >
> I never said using irq_find_mapping to get the linux irq is not
> standard way. What I said is using it during adding platform_device
> is nothing standard.
>
> > > Care to show me a couple of examples
> > > that make this conversion when adding platform device?
> > >
> > I did not search any example, currently it's just my idea based on my understanding
> > on irq domain design. Maybe i should give a patch to describe my idea,
> > then we can discuss on the patch.
> >
> I understand your idea, and I just do not think it's a good/right one.
>
Can you tell the reasons?
> > Or did you see any example on using shift way to define device irq resource?
> > Then i can look at it.
> >
> http://thread.gmane.org/gmane.linux.ports.arm.kernel/171075
>
Hmm, i didn't know the history
Do you know the reason why we decide to do that way?
> > > > > The irq number used in resource definition
> > > > > should simply just be Linux irq. Doing what you suggest here will
> > > > No, it's should be hw irq.
> > >
> > > You are simply wrong here. Nothing more to respond on this.
> > >
> > If using linux virt irq, how do we avoid the issues i said in my last reply?
> >
> Do not make up any issue. I'm only interesting in the practical issues.
>
Aren't they really exist potential issues?
Shouldn't we take care of it?
I'm afraid the solution you adopted is a bit weak and we may need change it again and again
in the future. The irq number defined definitely should be stable and not easily change
since they're hw properties.
I made a patch for the method i prefered, will send out in this thread for discuss.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [RFC PATCH 1/1] ARM: imx: enable SPARSE_IRQ for imx
2012-06-19 13:01 ` Dong Aisheng
@ 2012-06-19 13:19 ` Dong Aisheng
2012-06-19 14:06 ` Shawn Guo
0 siblings, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-19 13:19 UTC (permalink / raw)
To: linux-arm-kernel
After adding irqdomain support for both tzic and avic irq chip,
the original defined hw irq number in <soc>.h file like mx53.h
can not be directly used by the driver anymore.
This issue can be found when enable SPARSE_IRQ because when
SPARSE_IRQ is enabled the linux virtual irq and hw irq is not the same
anymore even using legacy irqdomain after mapping.
User should always call irq_find_mapping() to get the correct linux virtual
irq number to use in driver level.
Tested on i.MX53 LOCO.
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-imx/clk-imx21.c | 3 +-
arch/arm/mach-imx/clk-imx27.c | 3 +-
arch/arm/mach-imx/clk-imx31.c | 3 +-
arch/arm/mach-imx/clk-imx35.c | 6 +-
arch/arm/mach-imx/clk-imx51-imx53.c | 7 +-
arch/arm/mach-imx/mm-imx1.c | 8 +-
arch/arm/mach-imx/mm-imx21.c | 14 +++--
arch/arm/mach-imx/mm-imx25.c | 15 +++--
arch/arm/mach-imx/mm-imx27.c | 14 +++--
arch/arm/mach-imx/mm-imx3.c | 24 +++++---
arch/arm/mach-imx/mm-imx5.c | 74 +++++++++++++++++------
arch/arm/plat-mxc/avic.c | 13 +++-
arch/arm/plat-mxc/include/mach/common.h | 3 +
arch/arm/plat-mxc/include/mach/devices-common.h | 28 ++++++++-
arch/arm/plat-mxc/include/mach/irqs.h | 44 -------------
arch/arm/plat-mxc/irq-common.h | 3 +
arch/arm/plat-mxc/tzic.c | 13 +++-
drivers/media/video/mx1_camera.c | 1 +
sound/soc/fsl/imx-pcm-fiq.c | 1 +
20 files changed, 168 insertions(+), 110 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b1b2752..c9c28c6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -447,6 +447,7 @@ config ARCH_MXC
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select MULTI_IRQ_HANDLER
+ select SPARSE_IRQ
help
Support for Freescale MXC/iMX-based family of processors
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index ea13e61..0c3aeb9 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -180,7 +180,8 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
- mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
+ mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
+ avic_irq_find_mapping(MX21_INT_GPT1));
return 0;
}
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 295cbd7..49b3446 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -263,7 +263,8 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
- mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
+ mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
+ avic_irq_find_mapping(MX27_INT_GPT1));
clk_prepare_enable(clk[emi_ahb_gate]);
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index c9a06d8..119ae4e 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -175,7 +175,8 @@ int __init mx31_clocks_init(unsigned long fref)
mx31_revision();
clk_disable_unprepare(clk[iim_gate]);
- mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
+ mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
+ avic_irq_find_mapping(MX31_INT_GPT));
return 0;
}
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 920a8cc..cb48dd9 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -267,9 +267,11 @@ int __init mx35_clocks_init()
imx_print_silicon_rev("i.MX35", mx35_revision());
#ifdef CONFIG_MXC_USE_EPIT
- epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
+ epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR),
+ avic_irq_find_mapping(MX35_INT_EPIT1));
#else
- mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
+ mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR),
+ avic_irq_find_mapping(MX35_INT_GPT));
#endif
return 0;
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index a2200c7..387d595 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -366,7 +366,8 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_set_rate(clk[esdhc_b_podf], 166250000);
/* System timer */
- mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
+ mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
+ tzic_irq_find_mapping(MX53_INT_GPT));
clk_prepare_enable(clk[iim_gate]);
imx_print_silicon_rev("i.MX51", mx51_revision());
@@ -451,8 +452,8 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_set_rate(clk[esdhc_b_podf], 200000000);
/* System timer */
- mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
-
+ mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
+ tzic_irq_find_mapping(MX53_INT_GPT));
clk_prepare_enable(clk[iim_gate]);
imx_print_silicon_rev("i.MX53", mx53_revision());
clk_disable_unprepare(clk[iim_gate]);
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 6d60d51..332f8c8 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -51,12 +51,12 @@ void __init mx1_init_irq(void)
void __init imx1_soc_init(void)
{
mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
- MX1_GPIO_INT_PORTA, 0);
+ avic_irq_find_mapping(MX1_GPIO_INT_PORTA), 0);
mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256,
- MX1_GPIO_INT_PORTB, 0);
+ avic_irq_find_mapping(MX1_GPIO_INT_PORTB), 0);
mxc_register_gpio("imx1-gpio", 2, MX1_GPIO3_BASE_ADDR, SZ_256,
- MX1_GPIO_INT_PORTC, 0);
+ avic_irq_find_mapping(MX1_GPIO_INT_PORTC), 0);
mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
- MX1_GPIO_INT_PORTD, 0);
+ avic_irq_find_mapping(MX1_GPIO_INT_PORTD), 0);
pinctrl_provide_dummies();
}
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index d056dad..de42bf5 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -81,12 +81,14 @@ static const struct resource imx21_audmux_res[] __initconst = {
void __init imx21_soc_init(void)
{
- mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+ int int_gpio = avic_irq_find_mapping(MX21_INT_GPIO);
+
+ mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, int_gpio , 0);
+ mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, int_gpio , 0);
+ mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, int_gpio , 0);
+ mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, int_gpio , 0);
+ mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, int_gpio , 0);
+ mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, int_gpio , 0);
pinctrl_provide_dummies();
imx_add_imx_dma();
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 388928f..6338bd0 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -90,14 +90,19 @@ static const struct resource imx25_audmux_res[] __initconst = {
void __init imx25_soc_init(void)
{
/* i.mx25 has the i.mx31 type gpio */
- mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
- mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
- mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
- mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
+ mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX25_INT_GPIO1), 0);
+ mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX25_INT_GPIO2), 0);
+ mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX25_INT_GPIO3), 0);
+ mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX25_INT_GPIO4), 0);
pinctrl_provide_dummies();
/* i.mx25 has the i.mx35 type sdma */
- imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
+ imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR,
+ avic_irq_find_mapping(MX25_INT_SDMA), &imx25_sdma_pdata);
/* i.mx25 has the i.mx31 type audmux */
platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
ARRAY_SIZE(imx25_audmux_res));
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index e7e24af..2710fdf 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -81,13 +81,15 @@ static const struct resource imx27_audmux_res[] __initconst = {
void __init imx27_soc_init(void)
{
+ int int_gpio = avic_irq_find_mapping(MX27_INT_GPIO);
+
/* i.mx27 has the i.mx21 type gpio */
- mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
+ mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, int_gpio, 0);
+ mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, int_gpio, 0);
+ mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, int_gpio, 0);
+ mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, int_gpio, 0);
+ mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, int_gpio, 0);
+ mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, int_gpio, 0);
pinctrl_provide_dummies();
imx_add_imx_dma();
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index fe96105..3525634 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -176,9 +176,12 @@ void __init imx31_soc_init(void)
imx3_init_l2x0();
- mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
- mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
- mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
+ mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX31_INT_GPIO1), 0);
+ mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX31_INT_GPIO2), 0);
+ mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX31_INT_GPIO3), 0);
pinctrl_provide_dummies();
@@ -188,7 +191,8 @@ void __init imx31_soc_init(void)
imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
}
- imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+ imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR,
+ avic_irq_find_mapping(MX31_INT_SDMA), &imx31_sdma_pdata);
imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
@@ -273,9 +277,12 @@ void __init imx35_soc_init(void)
imx3_init_l2x0();
/* i.mx35 has the i.mx31 type gpio */
- mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
- mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
- mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
+ mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX35_INT_GPIO1), 0);
+ mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX35_INT_GPIO2), 0);
+ mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K,
+ avic_irq_find_mapping(MX35_INT_GPIO3), 0);
pinctrl_provide_dummies();
if (to_version == 1) {
@@ -284,7 +291,8 @@ void __init imx35_soc_init(void)
imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
}
- imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+ imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR,
+ avic_irq_find_mapping(MX35_INT_SDMA), &imx35_sdma_pdata);
/* Setup AIPS registers */
imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 1d00305..d5b067f 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -182,12 +182,24 @@ static const struct resource imx53_audmux_res[] __initconst = {
void __init imx50_soc_init(void)
{
/* i.mx50 has the i.mx31 type gpio */
- mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
- mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
- mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
- mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
- mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
- mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
+ mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX50_INT_GPIO1_LOW),
+ tzic_irq_find_mapping(MX50_INT_GPIO1_HIGH));
+ mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX50_INT_GPIO2_LOW),
+ tzic_irq_find_mapping(MX50_INT_GPIO2_HIGH));
+ mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX50_INT_GPIO3_LOW),
+ tzic_irq_find_mapping(MX50_INT_GPIO3_HIGH));
+ mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX50_INT_GPIO4_LOW),
+ tzic_irq_find_mapping(MX50_INT_GPIO4_HIGH));
+ mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX50_INT_GPIO5_LOW),
+ tzic_irq_find_mapping(MX50_INT_GPIO5_HIGH));
+ mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX50_INT_GPIO6_LOW),
+ tzic_irq_find_mapping(MX50_INT_GPIO6_HIGH));
/* i.mx50 has the i.mx31 type audmux */
platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
@@ -197,15 +209,24 @@ void __init imx50_soc_init(void)
void __init imx51_soc_init(void)
{
/* i.mx51 has the i.mx31 type gpio */
- mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
- mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
- mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
- mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
+ mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX51_INT_GPIO1_LOW),
+ tzic_irq_find_mapping(MX51_INT_GPIO1_HIGH));
+ mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX51_INT_GPIO2_LOW),
+ tzic_irq_find_mapping(MX51_INT_GPIO2_HIGH));
+ mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX51_INT_GPIO3_LOW),
+ tzic_irq_find_mapping(MX51_INT_GPIO3_HIGH));
+ mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX51_INT_GPIO4_LOW),
+ tzic_irq_find_mapping(MX51_INT_GPIO4_HIGH));
pinctrl_provide_dummies();
/* i.mx51 has the i.mx35 type sdma */
- imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+ imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR,
+ tzic_irq_find_mapping(MX51_INT_SDMA), &imx51_sdma_pdata);
/* Setup AIPS registers */
imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
@@ -219,17 +240,32 @@ void __init imx51_soc_init(void)
void __init imx53_soc_init(void)
{
/* i.mx53 has the i.mx31 type gpio */
- mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
- mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
- mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
- mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
- mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
- mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
- mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
+ mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX53_INT_GPIO1_LOW),
+ tzic_irq_find_mapping(MX53_INT_GPIO1_HIGH));
+ mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX53_INT_GPIO2_LOW),
+ tzic_irq_find_mapping(MX53_INT_GPIO2_HIGH));
+ mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX53_INT_GPIO3_LOW),
+ tzic_irq_find_mapping(MX53_INT_GPIO3_HIGH));
+ mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX53_INT_GPIO4_LOW),
+ tzic_irq_find_mapping(MX53_INT_GPIO4_HIGH));
+ mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX53_INT_GPIO5_LOW),
+ tzic_irq_find_mapping(MX53_INT_GPIO5_HIGH));
+ mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX53_INT_GPIO6_LOW),
+ tzic_irq_find_mapping(MX53_INT_GPIO6_HIGH));
+ mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K,
+ tzic_irq_find_mapping(MX53_INT_GPIO7_LOW),
+ tzic_irq_find_mapping(MX53_INT_GPIO7_HIGH));
pinctrl_provide_dummies();
/* i.mx53 has the i.mx35 type sdma */
- imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+ imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR,
+ tzic_irq_find_mapping(MX53_INT_SDMA), &imx53_sdma_pdata);
/* Setup AIPS registers */
imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 4fe1d9b..cac7fd5 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -52,10 +52,15 @@
#define AVIC_NUM_IRQS 64
void __iomem *avic_base;
-static struct irq_domain *domain;
+struct irq_domain *avic_domain;
static u32 avic_saved_mask_reg[2];
+int avic_irq_find_mapping(unsigned int irq)
+{
+ return irq_find_mapping(avic_domain, irq);
+}
+
#ifdef CONFIG_MXC_IRQ_PRIOR
static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
{
@@ -163,7 +168,7 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
if (nivector == 0xffff)
break;
- handle_IRQ(irq_find_mapping(domain, nivector), regs);
+ handle_IRQ(irq_find_mapping(avic_domain, nivector), regs);
} while (1);
}
@@ -198,9 +203,9 @@ void __init mxc_init_irq(void __iomem *irqbase)
WARN_ON(irq_base < 0);
np = of_find_compatible_node(NULL, NULL, "fsl,avic");
- domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
+ avic_domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
&irq_domain_simple_ops, NULL);
- WARN_ON(!domain);
+ WARN_ON(!avic_domain);
for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
avic_init_gc(i, irq_base);
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index e429ca1..dbe14d6 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -98,6 +98,9 @@ extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
extern void imx_print_silicon_rev(const char *cpu, int srev);
+extern int avic_irq_find_mapping(unsigned int irq);
+extern int tzic_irq_find_mapping(unsigned int irq);
+
void avic_handle_irq(struct pt_regs *);
void tzic_handle_irq(struct pt_regs *);
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index a7f5bb1..2a84cbb 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -9,6 +9,8 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/init.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
#include <mach/sdma.h>
extern struct device mxc_aips_bus;
@@ -16,7 +18,7 @@ extern struct device mxc_ahb_bus;
static inline struct platform_device *imx_add_platform_device_dmamask(
const char *name, int id,
- const struct resource *res, unsigned int num_resources,
+ struct resource *res, unsigned int num_resources,
const void *data, size_t size_data, u64 dmamask)
{
struct platform_device_info pdevinfo = {
@@ -28,12 +30,34 @@ static inline struct platform_device *imx_add_platform_device_dmamask(
.size_data = size_data,
.dma_mask = dmamask,
};
+
+ int i;
+
+ /* convert to linux virtual irq for driver to use */
+ for (i = 0; i < num_resources; i++) {
+ if (res[i].flags & IORESOURCE_IRQ) {
+#ifdef CONFIG_MXC_AVIC
+ if (cpu_is_mx1() || cpu_is_mx21()
+ || cpu_is_mx25() || cpu_is_mx27()
+ || cpu_is_mx31() || cpu_is_mx35())
+ res[i].start = avic_irq_find_mapping(res[i].start);
+#endif
+
+#ifdef CONFIG_MXC_TZIC
+ if (cpu_is_mx50() || cpu_is_mx51() || cpu_is_mx53())
+ res[i].start = tzic_irq_find_mapping(res[i].start);
+#endif
+ WARN_ON(!res[i].start);
+ res[i].end = res[i].start;
+ }
+ }
+
return platform_device_register_full(&pdevinfo);
}
static inline struct platform_device *imx_add_platform_device(
const char *name, int id,
- const struct resource *res, unsigned int num_resources,
+ struct resource *res, unsigned int num_resources,
const void *data, size_t size_data)
{
return imx_add_platform_device_dmamask(
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index fd9efb0..d73f5e8 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -11,50 +11,6 @@
#ifndef __ASM_ARCH_MXC_IRQS_H__
#define __ASM_ARCH_MXC_IRQS_H__
-#include <asm-generic/gpio.h>
-
-/*
- * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
- * have 128 IRQs, and those with AVIC have 64.
- *
- * To support single image, the biggest number should be defined on
- * top of the list.
- */
-#if defined CONFIG_ARM_GIC
-#define MXC_INTERNAL_IRQS 160
-#elif defined CONFIG_MXC_TZIC
-#define MXC_INTERNAL_IRQS 128
-#else
-#define MXC_INTERNAL_IRQS 64
-#endif
-
-#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
-
-/*
- * The next 16 interrupts are for board specific purposes. Since
- * the kernel can only run on one machine at a time, we can re-use
- * these. If you need more, increase MXC_BOARD_IRQS, but keep it
- * within sensible limits.
- */
-#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
-
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
-#define MXC_BOARD_IRQS 80
-#else
-#define MXC_BOARD_IRQS 16
-#endif
-
-#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
-
-#ifdef CONFIG_MX3_IPU_IRQS
-#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
-#else
-#define MX3_IPU_IRQS 0
-#endif
-/* REVISIT: Add IPU irqs on IMX51 */
-
-#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
-
extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
/* all normal IRQs can be FIQs */
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h
index 6ccb3a1..1cc07e4 100644
--- a/arch/arm/plat-mxc/irq-common.h
+++ b/arch/arm/plat-mxc/irq-common.h
@@ -19,6 +19,9 @@
#ifndef __PLAT_MXC_IRQ_COMMON_H__
#define __PLAT_MXC_IRQ_COMMON_H__
+extern struct irq_domain *tzic_domain;
+extern struct irq_domain *avic_domain;
+
struct mxc_extra_irq
{
int (*set_priority)(unsigned char irq, unsigned char prio);
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index abc90e4..e6bb72b 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -51,10 +51,15 @@
#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
-static struct irq_domain *domain;
+struct irq_domain *tzic_domain;
#define TZIC_NUM_IRQS 128
+int tzic_irq_find_mapping(unsigned int irq)
+{
+ return irq_find_mapping(tzic_domain, irq);
+}
+
#ifdef CONFIG_FIQ
static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
{
@@ -141,7 +146,7 @@ asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
while (stat) {
handled = 1;
irqofs = fls(stat) - 1;
- handle_IRQ(irq_find_mapping(domain,
+ handle_IRQ(irq_find_mapping(tzic_domain,
irqofs + i * 32), regs);
stat &= ~(1 << irqofs);
}
@@ -183,9 +188,9 @@ void __init tzic_init_irq(void __iomem *irqbase)
WARN_ON(irq_base < 0);
np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
- domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
+ tzic_domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
&irq_domain_simple_ops, NULL);
- WARN_ON(!domain);
+ WARN_ON(!tzic_domain);
for (i = 0; i < 4; i++, irq_base += 32)
tzic_init_gc(i, irq_base);
diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
index 4296a83..d2e6f82 100644
--- a/drivers/media/video/mx1_camera.c
+++ b/drivers/media/video/mx1_camera.c
@@ -43,6 +43,7 @@
#include <asm/fiq.h>
#include <mach/dma-mx1-mx2.h>
#include <mach/hardware.h>
+#include <mach/irqs.h>
#include <mach/mx1_camera.h>
/*
diff --git a/sound/soc/fsl/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
index 456b7d7..ee27ba3 100644
--- a/sound/soc/fsl/imx-pcm-fiq.c
+++ b/sound/soc/fsl/imx-pcm-fiq.c
@@ -29,6 +29,7 @@
#include <asm/fiq.h>
+#include <mach/irqs.h>
#include <mach/ssi.h>
#include "imx-ssi.h"
--
1.7.0.4
^ permalink raw reply related [flat|nested] 85+ messages in thread* [RFC PATCH 1/1] ARM: imx: enable SPARSE_IRQ for imx
2012-06-19 13:19 ` [RFC PATCH 1/1] ARM: imx: enable SPARSE_IRQ for imx Dong Aisheng
@ 2012-06-19 14:06 ` Shawn Guo
2012-06-20 2:23 ` Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-19 14:06 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jun 19, 2012 at 09:19:53PM +0800, Dong Aisheng wrote:
> After adding irqdomain support for both tzic and avic irq chip,
> the original defined hw irq number in <soc>.h file like mx53.h
> can not be directly used by the driver anymore.
> This issue can be found when enable SPARSE_IRQ because when
> SPARSE_IRQ is enabled the linux virtual irq and hw irq is not the same
> anymore even using legacy irqdomain after mapping.
> User should always call irq_find_mapping() to get the correct linux virtual
> irq number to use in driver level.
>
> Tested on i.MX53 LOCO.
>
> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
NAK.
I have been keeping saying that the irq number used in resource should
always be Linux irq. Unfortunately, you are not listening.
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/mach-imx/clk-imx21.c | 3 +-
> arch/arm/mach-imx/clk-imx27.c | 3 +-
> arch/arm/mach-imx/clk-imx31.c | 3 +-
> arch/arm/mach-imx/clk-imx35.c | 6 +-
> arch/arm/mach-imx/clk-imx51-imx53.c | 7 +-
> arch/arm/mach-imx/mm-imx1.c | 8 +-
> arch/arm/mach-imx/mm-imx21.c | 14 +++--
> arch/arm/mach-imx/mm-imx25.c | 15 +++--
> arch/arm/mach-imx/mm-imx27.c | 14 +++--
> arch/arm/mach-imx/mm-imx3.c | 24 +++++---
> arch/arm/mach-imx/mm-imx5.c | 74 +++++++++++++++++------
> arch/arm/plat-mxc/avic.c | 13 +++-
> arch/arm/plat-mxc/include/mach/common.h | 3 +
> arch/arm/plat-mxc/include/mach/devices-common.h | 28 ++++++++-
> arch/arm/plat-mxc/include/mach/irqs.h | 44 -------------
> arch/arm/plat-mxc/irq-common.h | 3 +
> arch/arm/plat-mxc/tzic.c | 13 +++-
> drivers/media/video/mx1_camera.c | 1 +
> sound/soc/fsl/imx-pcm-fiq.c | 1 +
> 20 files changed, 168 insertions(+), 110 deletions(-)
...
> static inline struct platform_device *imx_add_platform_device_dmamask(
> const char *name, int id,
> - const struct resource *res, unsigned int num_resources,
> + struct resource *res, unsigned int num_resources,
> const void *data, size_t size_data, u64 dmamask)
> {
> struct platform_device_info pdevinfo = {
> @@ -28,12 +30,34 @@ static inline struct platform_device *imx_add_platform_device_dmamask(
> .size_data = size_data,
> .dma_mask = dmamask,
> };
> +
> + int i;
> +
> + /* convert to linux virtual irq for driver to use */
> + for (i = 0; i < num_resources; i++) {
> + if (res[i].flags & IORESOURCE_IRQ) {
> +#ifdef CONFIG_MXC_AVIC
> + if (cpu_is_mx1() || cpu_is_mx21()
> + || cpu_is_mx25() || cpu_is_mx27()
> + || cpu_is_mx31() || cpu_is_mx35())
> + res[i].start = avic_irq_find_mapping(res[i].start);
> +#endif
> +
> +#ifdef CONFIG_MXC_TZIC
> + if (cpu_is_mx50() || cpu_is_mx51() || cpu_is_mx53())
> + res[i].start = tzic_irq_find_mapping(res[i].start);
> +#endif
> + WARN_ON(!res[i].start);
> + res[i].end = res[i].start;
> + }
> + }
> +
What a "beautiful" hacking! I'm so familiar with such kind of code,
because I have been working for long time to kill them.
As I said, not every single imx device is added by calling
imx_add_platform_device. And if you really want to do this conversion,
the right place should be platform_device_add_resources(), so that no
one could possibly be missed, and we do not have imx be so unique on
this conversion. If you can do that, I would be happy to ACK it.
But I guess you will have a "little" problem with doing that.
> return platform_device_register_full(&pdevinfo);
> }
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread* [RFC PATCH 1/1] ARM: imx: enable SPARSE_IRQ for imx
2012-06-19 14:06 ` Shawn Guo
@ 2012-06-20 2:23 ` Dong Aisheng
2012-06-20 5:40 ` Shawn Guo
0 siblings, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-20 2:23 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jun 19, 2012 at 10:06:15PM +0800, Shawn Guo wrote:
> On Tue, Jun 19, 2012 at 09:19:53PM +0800, Dong Aisheng wrote:
> > After adding irqdomain support for both tzic and avic irq chip,
> > the original defined hw irq number in <soc>.h file like mx53.h
> > can not be directly used by the driver anymore.
> > This issue can be found when enable SPARSE_IRQ because when
> > SPARSE_IRQ is enabled the linux virtual irq and hw irq is not the same
> > anymore even using legacy irqdomain after mapping.
> > User should always call irq_find_mapping() to get the correct linux virtual
> > irq number to use in driver level.
> >
> > Tested on i.MX53 LOCO.
> >
> > Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
>
> NAK.
>
> I have been keeping saying that the irq number used in resource should
> always be Linux irq. Unfortunately, you are not listening.
>
I did see what you said, but you did not go with reasons and that was not so
convinced to me
Can you explain more why you choose linux virt irq and how about the real exist
potential issues i raised before?
> > ---
> > arch/arm/Kconfig | 1 +
> > arch/arm/mach-imx/clk-imx21.c | 3 +-
> > arch/arm/mach-imx/clk-imx27.c | 3 +-
> > arch/arm/mach-imx/clk-imx31.c | 3 +-
> > arch/arm/mach-imx/clk-imx35.c | 6 +-
> > arch/arm/mach-imx/clk-imx51-imx53.c | 7 +-
> > arch/arm/mach-imx/mm-imx1.c | 8 +-
> > arch/arm/mach-imx/mm-imx21.c | 14 +++--
> > arch/arm/mach-imx/mm-imx25.c | 15 +++--
> > arch/arm/mach-imx/mm-imx27.c | 14 +++--
> > arch/arm/mach-imx/mm-imx3.c | 24 +++++---
> > arch/arm/mach-imx/mm-imx5.c | 74 +++++++++++++++++------
> > arch/arm/plat-mxc/avic.c | 13 +++-
> > arch/arm/plat-mxc/include/mach/common.h | 3 +
> > arch/arm/plat-mxc/include/mach/devices-common.h | 28 ++++++++-
> > arch/arm/plat-mxc/include/mach/irqs.h | 44 -------------
> > arch/arm/plat-mxc/irq-common.h | 3 +
> > arch/arm/plat-mxc/tzic.c | 13 +++-
> > drivers/media/video/mx1_camera.c | 1 +
> > sound/soc/fsl/imx-pcm-fiq.c | 1 +
> > 20 files changed, 168 insertions(+), 110 deletions(-)
>
> ...
>
> > static inline struct platform_device *imx_add_platform_device_dmamask(
> > const char *name, int id,
> > - const struct resource *res, unsigned int num_resources,
> > + struct resource *res, unsigned int num_resources,
> > const void *data, size_t size_data, u64 dmamask)
> > {
> > struct platform_device_info pdevinfo = {
> > @@ -28,12 +30,34 @@ static inline struct platform_device *imx_add_platform_device_dmamask(
> > .size_data = size_data,
> > .dma_mask = dmamask,
> > };
> > +
> > + int i;
> > +
> > + /* convert to linux virtual irq for driver to use */
> > + for (i = 0; i < num_resources; i++) {
> > + if (res[i].flags & IORESOURCE_IRQ) {
> > +#ifdef CONFIG_MXC_AVIC
> > + if (cpu_is_mx1() || cpu_is_mx21()
> > + || cpu_is_mx25() || cpu_is_mx27()
> > + || cpu_is_mx31() || cpu_is_mx35())
> > + res[i].start = avic_irq_find_mapping(res[i].start);
> > +#endif
> > +
> > +#ifdef CONFIG_MXC_TZIC
> > + if (cpu_is_mx50() || cpu_is_mx51() || cpu_is_mx53())
> > + res[i].start = tzic_irq_find_mapping(res[i].start);
> > +#endif
> > + WARN_ON(!res[i].start);
> > + res[i].end = res[i].start;
> > + }
> > + }
> > +
> What a "beautiful" hacking! I'm so familiar with such kind of code,
> because I have been working for long time to kill them.
>
Hmm, it's not driver code.
And i did see a lot of such code in mach-specific file.
If wrong, any other better way to distinguish the different SoCs?
> As I said, not every single imx device is added by calling
> imx_add_platform_device. And if you really want to do this conversion,
> the right place should be platform_device_add_resources(), so that no
That is a way, but i would prefer to do it in mach-specific code first
since i'm not sure if other people will also like that.
If they will, we definite could discuss on doing it in common device
structure.
> one could possibly be missed, and we do not have imx be so unique on
> this conversion. If you can do that, I would be happy to ACK it.
> But I guess you will have a "little" problem with doing that.
>
I cannot understand, can you say it clearly?
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread* [RFC PATCH 1/1] ARM: imx: enable SPARSE_IRQ for imx
2012-06-20 2:23 ` Dong Aisheng
@ 2012-06-20 5:40 ` Shawn Guo
2012-06-20 6:40 ` Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-20 5:40 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jun 20, 2012 at 10:23:15AM +0800, Dong Aisheng wrote:
> I did see what you said, but you did not go with reasons and that was not so
> convinced to me
> Can you explain more why you choose linux virt irq and how about the real exist
> potential issues i raised before?
>
It's not my choice. Instead, this is how struct resource defined in
Linux. What more reasons do you need to understand that?
I do not take the thing you raised as issues, because in the end all
these static definitions will be removed after we move over to device
tree.
> Hmm, it's not driver code.
> And i did see a lot of such code in mach-specific file.
That does not mean you are encouraged to add more. We are trying to
remove them.
> If wrong, any other better way to distinguish the different SoCs?
>
There are certainly better way, since we have soc specific
initialization to do all the soc specific setup. That said, we do
not have to necessarily use all those ugly cpu_is_xxx and #ifdef.
> That is a way, but i would prefer to do it in mach-specific code first
No. Do not make imx special on this. We would like to use resource
definition in the way how it's defined and how everyone else use it.
> since i'm not sure if other people will also like that.
No one (except yourself) likes it. As I said, we are not supposed to
manipulate resource definition this way.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [RFC PATCH 1/1] ARM: imx: enable SPARSE_IRQ for imx
2012-06-20 5:40 ` Shawn Guo
@ 2012-06-20 6:40 ` Dong Aisheng
2012-06-20 12:57 ` Shawn Guo
0 siblings, 1 reply; 85+ messages in thread
From: Dong Aisheng @ 2012-06-20 6:40 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jun 20, 2012 at 01:40:17PM +0800, Shawn Guo wrote:
> On Wed, Jun 20, 2012 at 10:23:15AM +0800, Dong Aisheng wrote:
> > I did see what you said, but you did not go with reasons and that was not so
> > convinced to me
> > Can you explain more why you choose linux virt irq and how about the real exist
> > potential issues i raised before?
> >
> It's not my choice. Instead, this is how struct resource defined in
> Linux. What more reasons do you need to understand that?
>
It's not about how struct resource defined.
It's about why you directly define linux irq for device rather than
using standard api irq_find_mapping to get the correct linux virt irq
for device after using irqdomain.
> I do not take the thing you raised as issues, because in the end all
> these static definitions will be removed after we move over to device
> tree.
So you agree they're issues for non-dt?
IMHO moving to dt is not an excuse to do wrong things for non-dt.
>
> > Hmm, it's not driver code.
> > And i did see a lot of such code in mach-specific file.
>
> That does not mean you are encouraged to add more. We are trying to
> remove them.
>
> > If wrong, any other better way to distinguish the different SoCs?
> >
> There are certainly better way, since we have soc specific
> initialization to do all the soc specific setup. That said, we do
> not have to necessarily use all those ugly cpu_is_xxx and #ifdef.
>
I did not see your point, for soc specific setup, it definitely does not have
such issue. The issue happens in a common function shared by many SoCs.
And without dev_id as used by drivers, how do we do it in machine code
in a better way than cpu_is_xx for non-dt?
> > That is a way, but i would prefer to do it in mach-specific code first
>
> No. Do not make imx special on this. We would like to use resource
> definition in the way how it's defined and how everyone else use it.
>
> > since i'm not sure if other people will also like that.
>
> No one (except yourself) likes it. As I said, we are not supposed to
> manipulate resource definition this way.
>
Hmm, how can you say NO one?
Looking at my patch, you will see the main difference is i use
irq_find_mapping to get the correct linux irq number not matter
what the type of irqdomain of this irqchip is and how virtual irq
range used,
while you're doing based on the assumption that "i know the irqdomain
type of this chip is legacy and i know how virtual irq range is allocated,
then i konw after irqdomain map the linux virtual irq number
should be x, so i directly define x as the irq number for device without
using irq_find_mapping api",
the later one is obviously non-standard and dangerous.
Why you still think the later one is better?
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* [RFC PATCH 1/1] ARM: imx: enable SPARSE_IRQ for imx
2012-06-20 6:40 ` Dong Aisheng
@ 2012-06-20 12:57 ` Shawn Guo
2012-06-20 14:45 ` Dong Aisheng
0 siblings, 1 reply; 85+ messages in thread
From: Shawn Guo @ 2012-06-20 12:57 UTC (permalink / raw)
To: linux-arm-kernel
The conversation becomes really tedious. I promise this is my last
round reply to this. In any case, what you proposed here is nothing
imx specific. If you want to go this way, please have it supported
at driver core level.
On Wed, Jun 20, 2012 at 02:40:00PM +0800, Dong Aisheng wrote:
> It's not about how struct resource defined.
> It's about why you directly define linux irq for device rather than
> using standard api irq_find_mapping to get the correct linux virt irq
> for device after using irqdomain.
>
It's all about that the irq in resource is defined as Linux irq.
Whether you like it or not, that's a fact of Linux today. I do not
think I can repeat myself any more.
> So you agree they're issues for non-dt?
No, not at all, because:
* non-DT should always use legacy domain.
http://thread.gmane.org/gmane.linux.ports.arm.kernel/151860/focus=152072
* The SoC internal IRQs will always be allocated right after the
preallocated ones.
So the only thing that could impact those Linux irq numbering is the
irqs preallocated by irq core. I do not see why that preallocated
number need to change from time to time. The bottom line is that
all those Linux irqs are not open-coded but macros, which can be
easily updated without any change to the users.
> IMHO moving to dt is not an excuse to do wrong things for non-dt.
>
There is nothing wrong to me, really.
> I did not see your point, for soc specific setup, it definitely does not have
> such issue. The issue happens in a common function shared by many SoCs.
> And without dev_id as used by drivers, how do we do it in machine code
> in a better way than cpu_is_xx for non-dt?
>
You need to think about it a little bit further. You can define
a function pointer and have it assigned to avic_irq_find_mapping or
avic_irq_find_mapping in soc specific init function. Then you use
the function pointer in imx_add_platform_device. Wouldn't that save
you those cpu_is_xxx and #ifdef ugliness?
Or even simpler, you can define a global domain variable and have it
assigned with the avic/tzic domain in their init function.
> Hmm, how can you say NO one?
>
Prove me wrong by proposing the change to driver core then, please.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 85+ messages in thread
* [RFC PATCH 1/1] ARM: imx: enable SPARSE_IRQ for imx
2012-06-20 12:57 ` Shawn Guo
@ 2012-06-20 14:45 ` Dong Aisheng
0 siblings, 0 replies; 85+ messages in thread
From: Dong Aisheng @ 2012-06-20 14:45 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jun 20, 2012 at 08:57:21PM +0800, Shawn Guo wrote:
> The conversation becomes really tedious. I promise this is my last
> round reply to this. In any case, what you proposed here is nothing
> imx specific. If you want to go this way, please have it supported
> at driver core level.
>
Anyway, i appreciate to your replies on my questions.
I will consider support in driver core level.
> On Wed, Jun 20, 2012 at 02:40:00PM +0800, Dong Aisheng wrote:
> > It's not about how struct resource defined.
> > It's about why you directly define linux irq for device rather than
> > using standard api irq_find_mapping to get the correct linux virt irq
> > for device after using irqdomain.
> >
> It's all about that the irq in resource is defined as Linux irq.
> Whether you like it or not, that's a fact of Linux today. I do not
> think I can repeat myself any more.
>
I'm afraid you're missing my point.
I never said the irq in resource shouldn't be defined as linux irq.
My point is that irq number should be get via standard irqdomain api
rather than directly defining it yourself.
> > So you agree they're issues for non-dt?
>
> No, not at all, because:
>
> * non-DT should always use legacy domain.
>
> http://thread.gmane.org/gmane.linux.ports.arm.kernel/151860/focus=152072
>
> * The SoC internal IRQs will always be allocated right after the
> preallocated ones.
>
> So the only thing that could impact those Linux irq numbering is the
> irqs preallocated by irq core. I do not see why that preallocated
> number need to change from time to time. The bottom line is that
We never konw what the future maybe, right?
And you may note even currently the irq core also provides an interface
to machine to define the preallocated irqs in machine_desc->nr_irqs.
That's changeable.
> all those Linux irqs are not open-coded but macros, which can be
> easily updated without any change to the users.
Using NR_IRQS_LEGACY as offset is not safe.
> > Hmm, how can you say NO one?
> >
> Prove me wrong by proposing the change to driver core then, please.
>
We can do it in core, but i still did not find enough reasons to do like that.
IMHO the device core may not want to know the mapping between hw irq and
linux virtual irq, that's all the work of iqr and irqdomain layer.
The device core may only want the user to tell him the linux irq(virtual),
that seems enough.
I would like to see if other people have different options.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH 00/16] Enable SPARSE_IRQ support for imx
2012-06-14 5:59 ` Shawn Guo
@ 2012-06-14 8:00 ` Sascha Hauer
-1 siblings, 0 replies; 85+ messages in thread
From: Sascha Hauer @ 2012-06-14 8:00 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel, Arnd Bergmann, Rob Herring, Grant Likely,
Dong Aisheng, Russell King, Greg Kroah-Hartman, linux-serial,
Wolfram Sang, linux-i2c, Vinod Koul
On Thu, Jun 14, 2012 at 01:59:31PM +0800, Shawn Guo wrote:
> It seems that the lack of SPARSE_IRQ support becomes the last blocker
> for imx being built with multi-platform. The series is to enable
> SPARSE_IRQ for imx by having all the irqchips allocate their irq_descs.
> Along with the change, a legacy irqdomain is added for each of these
> irqchips (except ipu_irq) to help the mapping between hardware irq and
> Linux irq number, which is required by DT boot but also benefits non-DT.
>
> Based on v3.5-rc2. Boot tested on imx3, imx5 and imx6, and compile
> tested with imx_v4_v5_defconfig.
I gave it a test on i.MX1 and i.MX27, so
Tested-by: Sascha Hauer <s.hauer@pengutronix.de>
Also, nice move ;)
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha
>
> Shawn Guo (16):
> ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
> ARM: imx: eliminate macro IOMUX_TO_IRQ()
> ARM: imx: eliminate macro IRQ_GPIOx()
> gpio/mxc: move irq_domain_add_legacy call into gpio driver
> ARM: imx: move irq_domain_add_legacy call into tzic driver
> ARM: imx: move irq_domain_add_legacy call into avic driver
> dma: ipu: remove the use of ipu_platform_data
> ARM: imx: leave irq_base of wm8350_platform_data uninitialized
> ARM: imx: pass gpio than irq number into mxc_expio_init
> ARM: imx: add a legacy irqdomain for 3ds_debugboard
> ARM: imx: add a legacy irqdomain for mx31ads
> i2c: imx: remove unneeded mach/irqs.h inclusion
> ARM: imx: remove unneeded mach/irq.h inclusion
> tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
> ARM: fiq: save FIQ_START by passing absolute fiq number
> ARM: imx: enable SPARSE_IRQ for imx platform
>
> arch/arm/Kconfig | 1 +
> arch/arm/kernel/fiq.c | 4 +-
> arch/arm/mach-imx/devices-imx31.h | 4 +-
> arch/arm/mach-imx/devices-imx35.h | 4 +-
> arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 3 +-
> arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c | 6 +-
> arch/arm/mach-imx/imx27-dt.c | 28 ---
> arch/arm/mach-imx/imx51-dt.c | 27 ---
> arch/arm/mach-imx/imx53-dt.c | 27 ---
> arch/arm/mach-imx/mach-apf9328.c | 7 +-
> arch/arm/mach-imx/mach-armadillo5x0.c | 18 +-
> arch/arm/mach-imx/mach-cpuimx27.c | 12 +-
> arch/arm/mach-imx/mach-cpuimx35.c | 3 +-
> arch/arm/mach-imx/mach-cpuimx51sd.c | 3 +-
> arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 9 +-
> arch/arm/mach-imx/mach-imx6q.c | 14 --
> arch/arm/mach-imx/mach-kzm_arm11_01.c | 20 ++-
> arch/arm/mach-imx/mach-mx1ads.c | 1 -
> arch/arm/mach-imx/mach-mx21ads.c | 16 ++-
> arch/arm/mach-imx/mach-mx27_3ds.c | 7 +-
> arch/arm/mach-imx/mach-mx27ads.c | 12 +-
> arch/arm/mach-imx/mach-mx31_3ds.c | 18 +--
> arch/arm/mach-imx/mach-mx31ads.c | 63 ++++---
> arch/arm/mach-imx/mach-mx31lilly.c | 10 +-
> arch/arm/mach-imx/mach-mx31lite.c | 11 +-
> arch/arm/mach-imx/mach-mx31moboard.c | 10 +-
> arch/arm/mach-imx/mach-mx35_3ds.c | 18 +--
> arch/arm/mach-imx/mach-mx51_3ds.c | 3 +-
> arch/arm/mach-imx/mach-mx53_ard.c | 5 +-
> arch/arm/mach-imx/mach-mxt_td60.c | 6 +-
> arch/arm/mach-imx/mach-pca100.c | 5 +-
> arch/arm/mach-imx/mach-pcm037.c | 24 ++--
> arch/arm/mach-imx/mach-pcm038.c | 4 +-
> arch/arm/mach-imx/mach-pcm043.c | 6 +-
> arch/arm/mach-imx/mach-qong.c | 10 +-
> arch/arm/mach-imx/mach-scb9328.c | 7 +-
> arch/arm/mach-imx/mach-vpr200.c | 10 +-
> arch/arm/mach-imx/mm-imx1.c | 1 -
> arch/arm/mach-imx/mm-imx21.c | 1 -
> arch/arm/mach-imx/mm-imx25.c | 1 -
> arch/arm/mach-imx/mm-imx27.c | 1 -
> arch/arm/mach-imx/mm-imx3.c | 1 -
> arch/arm/mach-imx/mx31lilly-db.c | 11 +-
> arch/arm/mach-imx/mx31lite-db.c | 5 +-
> arch/arm/mach-imx/mx51_efika.c | 3 +-
> arch/arm/mach-imx/pcm970-baseboard.c | 13 +-
> arch/arm/mach-rpc/include/mach/irqs.h | 12 +-
> arch/arm/plat-mxc/3ds_debugboard.c | 50 +++---
> arch/arm/plat-mxc/avic.c | 26 ++-
> arch/arm/plat-mxc/devices/platform-ipu-core.c | 5 +-
> arch/arm/plat-mxc/include/mach/3ds_debugboard.h | 2 +-
> arch/arm/plat-mxc/include/mach/devices-common.h | 4 +-
> arch/arm/plat-mxc/include/mach/hardware.h | 2 -
> arch/arm/plat-mxc/include/mach/iomux-mx3.h | 3 -
> arch/arm/plat-mxc/include/mach/iomux-v1.h | 7 -
> arch/arm/plat-mxc/include/mach/ipu.h | 4 -
> arch/arm/plat-mxc/include/mach/irqs.h | 44 -----
> arch/arm/plat-mxc/include/mach/mx1.h | 111 ++++++------
> arch/arm/plat-mxc/include/mach/mx21.h | 107 ++++++------
> arch/arm/plat-mxc/include/mach/mx25.h | 72 ++++----
> arch/arm/plat-mxc/include/mach/mx27.h | 127 +++++++-------
> arch/arm/plat-mxc/include/mach/mx2x.h | 87 +++++-----
> arch/arm/plat-mxc/include/mach/mx31.h | 118 +++++++------
> arch/arm/plat-mxc/include/mach/mx35.h | 109 ++++++------
> arch/arm/plat-mxc/include/mach/mx3x.h | 77 ++++----
> arch/arm/plat-mxc/include/mach/mx50.h | 187 ++++++++++----------
> arch/arm/plat-mxc/include/mach/mx51.h | 209 +++++++++++-----------
> arch/arm/plat-mxc/include/mach/mx53.h | 217 ++++++++++++-----------
> arch/arm/plat-mxc/tzic.c | 28 ++-
> drivers/dma/ipu/ipu_idmac.c | 8 +-
> drivers/dma/ipu/ipu_irq.c | 14 +-
> drivers/gpio/gpio-mxc.c | 56 ++++---
> drivers/i2c/busses/i2c-imx.c | 1 -
> drivers/media/video/mx1_camera.c | 1 +
> drivers/tty/serial/imx.c | 6 +-
> sound/soc/fsl/imx-pcm-fiq.c | 1 +
> 76 files changed, 1041 insertions(+), 1127 deletions(-)
>
> --
> 1.7.5.4
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH 00/16] Enable SPARSE_IRQ support for imx
@ 2012-06-14 8:00 ` Sascha Hauer
0 siblings, 0 replies; 85+ messages in thread
From: Sascha Hauer @ 2012-06-14 8:00 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 14, 2012 at 01:59:31PM +0800, Shawn Guo wrote:
> It seems that the lack of SPARSE_IRQ support becomes the last blocker
> for imx being built with multi-platform. The series is to enable
> SPARSE_IRQ for imx by having all the irqchips allocate their irq_descs.
> Along with the change, a legacy irqdomain is added for each of these
> irqchips (except ipu_irq) to help the mapping between hardware irq and
> Linux irq number, which is required by DT boot but also benefits non-DT.
>
> Based on v3.5-rc2. Boot tested on imx3, imx5 and imx6, and compile
> tested with imx_v4_v5_defconfig.
I gave it a test on i.MX1 and i.MX27, so
Tested-by: Sascha Hauer <s.hauer@pengutronix.de>
Also, nice move ;)
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha
>
> Shawn Guo (16):
> ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
> ARM: imx: eliminate macro IOMUX_TO_IRQ()
> ARM: imx: eliminate macro IRQ_GPIOx()
> gpio/mxc: move irq_domain_add_legacy call into gpio driver
> ARM: imx: move irq_domain_add_legacy call into tzic driver
> ARM: imx: move irq_domain_add_legacy call into avic driver
> dma: ipu: remove the use of ipu_platform_data
> ARM: imx: leave irq_base of wm8350_platform_data uninitialized
> ARM: imx: pass gpio than irq number into mxc_expio_init
> ARM: imx: add a legacy irqdomain for 3ds_debugboard
> ARM: imx: add a legacy irqdomain for mx31ads
> i2c: imx: remove unneeded mach/irqs.h inclusion
> ARM: imx: remove unneeded mach/irq.h inclusion
> tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
> ARM: fiq: save FIQ_START by passing absolute fiq number
> ARM: imx: enable SPARSE_IRQ for imx platform
>
> arch/arm/Kconfig | 1 +
> arch/arm/kernel/fiq.c | 4 +-
> arch/arm/mach-imx/devices-imx31.h | 4 +-
> arch/arm/mach-imx/devices-imx35.h | 4 +-
> arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 3 +-
> arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c | 6 +-
> arch/arm/mach-imx/imx27-dt.c | 28 ---
> arch/arm/mach-imx/imx51-dt.c | 27 ---
> arch/arm/mach-imx/imx53-dt.c | 27 ---
> arch/arm/mach-imx/mach-apf9328.c | 7 +-
> arch/arm/mach-imx/mach-armadillo5x0.c | 18 +-
> arch/arm/mach-imx/mach-cpuimx27.c | 12 +-
> arch/arm/mach-imx/mach-cpuimx35.c | 3 +-
> arch/arm/mach-imx/mach-cpuimx51sd.c | 3 +-
> arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 9 +-
> arch/arm/mach-imx/mach-imx6q.c | 14 --
> arch/arm/mach-imx/mach-kzm_arm11_01.c | 20 ++-
> arch/arm/mach-imx/mach-mx1ads.c | 1 -
> arch/arm/mach-imx/mach-mx21ads.c | 16 ++-
> arch/arm/mach-imx/mach-mx27_3ds.c | 7 +-
> arch/arm/mach-imx/mach-mx27ads.c | 12 +-
> arch/arm/mach-imx/mach-mx31_3ds.c | 18 +--
> arch/arm/mach-imx/mach-mx31ads.c | 63 ++++---
> arch/arm/mach-imx/mach-mx31lilly.c | 10 +-
> arch/arm/mach-imx/mach-mx31lite.c | 11 +-
> arch/arm/mach-imx/mach-mx31moboard.c | 10 +-
> arch/arm/mach-imx/mach-mx35_3ds.c | 18 +--
> arch/arm/mach-imx/mach-mx51_3ds.c | 3 +-
> arch/arm/mach-imx/mach-mx53_ard.c | 5 +-
> arch/arm/mach-imx/mach-mxt_td60.c | 6 +-
> arch/arm/mach-imx/mach-pca100.c | 5 +-
> arch/arm/mach-imx/mach-pcm037.c | 24 ++--
> arch/arm/mach-imx/mach-pcm038.c | 4 +-
> arch/arm/mach-imx/mach-pcm043.c | 6 +-
> arch/arm/mach-imx/mach-qong.c | 10 +-
> arch/arm/mach-imx/mach-scb9328.c | 7 +-
> arch/arm/mach-imx/mach-vpr200.c | 10 +-
> arch/arm/mach-imx/mm-imx1.c | 1 -
> arch/arm/mach-imx/mm-imx21.c | 1 -
> arch/arm/mach-imx/mm-imx25.c | 1 -
> arch/arm/mach-imx/mm-imx27.c | 1 -
> arch/arm/mach-imx/mm-imx3.c | 1 -
> arch/arm/mach-imx/mx31lilly-db.c | 11 +-
> arch/arm/mach-imx/mx31lite-db.c | 5 +-
> arch/arm/mach-imx/mx51_efika.c | 3 +-
> arch/arm/mach-imx/pcm970-baseboard.c | 13 +-
> arch/arm/mach-rpc/include/mach/irqs.h | 12 +-
> arch/arm/plat-mxc/3ds_debugboard.c | 50 +++---
> arch/arm/plat-mxc/avic.c | 26 ++-
> arch/arm/plat-mxc/devices/platform-ipu-core.c | 5 +-
> arch/arm/plat-mxc/include/mach/3ds_debugboard.h | 2 +-
> arch/arm/plat-mxc/include/mach/devices-common.h | 4 +-
> arch/arm/plat-mxc/include/mach/hardware.h | 2 -
> arch/arm/plat-mxc/include/mach/iomux-mx3.h | 3 -
> arch/arm/plat-mxc/include/mach/iomux-v1.h | 7 -
> arch/arm/plat-mxc/include/mach/ipu.h | 4 -
> arch/arm/plat-mxc/include/mach/irqs.h | 44 -----
> arch/arm/plat-mxc/include/mach/mx1.h | 111 ++++++------
> arch/arm/plat-mxc/include/mach/mx21.h | 107 ++++++------
> arch/arm/plat-mxc/include/mach/mx25.h | 72 ++++----
> arch/arm/plat-mxc/include/mach/mx27.h | 127 +++++++-------
> arch/arm/plat-mxc/include/mach/mx2x.h | 87 +++++-----
> arch/arm/plat-mxc/include/mach/mx31.h | 118 +++++++------
> arch/arm/plat-mxc/include/mach/mx35.h | 109 ++++++------
> arch/arm/plat-mxc/include/mach/mx3x.h | 77 ++++----
> arch/arm/plat-mxc/include/mach/mx50.h | 187 ++++++++++----------
> arch/arm/plat-mxc/include/mach/mx51.h | 209 +++++++++++-----------
> arch/arm/plat-mxc/include/mach/mx53.h | 217 ++++++++++++-----------
> arch/arm/plat-mxc/tzic.c | 28 ++-
> drivers/dma/ipu/ipu_idmac.c | 8 +-
> drivers/dma/ipu/ipu_irq.c | 14 +-
> drivers/gpio/gpio-mxc.c | 56 ++++---
> drivers/i2c/busses/i2c-imx.c | 1 -
> drivers/media/video/mx1_camera.c | 1 +
> drivers/tty/serial/imx.c | 6 +-
> sound/soc/fsl/imx-pcm-fiq.c | 1 +
> 76 files changed, 1041 insertions(+), 1127 deletions(-)
>
> --
> 1.7.5.4
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 85+ messages in thread