* [RFC]Add initial support for Altera's SOCFPGA hardward @ 2012-06-27 13:50 dinguyen at altera.com 2012-06-27 13:50 ` [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform dinguyen at altera.com 2012-06-27 13:50 ` [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW dinguyen at altera.com 0 siblings, 2 replies; 47+ messages in thread From: dinguyen at altera.com @ 2012-06-27 13:50 UTC (permalink / raw) To: linux-arm-kernel Hello, The following 2 patches are initial submissions for Altera's SOCFPGA on ARM platform. Advance and deep appreciation to those who will take the time to review and send comments. [PATCH 1] Add defines for the SOCFPGA hardware MAINTAINERS | 5 arch/arm/Kconfig | 19 + arch/arm/Makefile | 1 arch/arm/mach-socfpga/Kconfig | 21 + arch/arm/mach-socfpga/Makefile | 8 arch/arm/mach-socfpga/Makefile.boot | 3 arch/arm/mach-socfpga/clock.c | 50 +++ arch/arm/mach-socfpga/common.c | 156 ++++++++++ arch/arm/mach-socfpga/common.h | 38 ++ arch/arm/mach-socfpga/dw_apb_timer.c | 164 +++++++++++ arch/arm/mach-socfpga/headsmp.S | 41 ++ arch/arm/mach-socfpga/hotplug.c | 125 ++++++++ arch/arm/mach-socfpga/include/mach/clock.h | 11 arch/arm/mach-socfpga/include/mach/debug-macro.S | 29 + arch/arm/mach-socfpga/include/mach/dw_apb_timer.h | 38 ++ arch/arm/mach-socfpga/include/mach/io.h | 27 + arch/arm/mach-socfpga/include/mach/iomap.h | 37 ++ arch/arm/mach-socfpga/include/mach/irqs.h | 305 +++++++++++++++++++++ arch/arm/mach-socfpga/include/mach/memory.h | 32 ++ arch/arm/mach-socfpga/include/mach/smp.h | 15 + arch/arm/mach-socfpga/include/mach/socfpga-timer.h | 27 + arch/arm/mach-socfpga/include/mach/system.h | 31 ++ arch/arm/mach-socfpga/include/mach/timex.h | 19 + arch/arm/mach-socfpga/include/mach/uncompress.h | 44 +++ arch/arm/mach-socfpga/localtimer.c | 34 ++ arch/arm/mach-socfpga/platsmp.c | 154 ++++++++++ arch/arm/mm/Kconfig | 2 27 files changed, 1435 insertions(+), 1 deletion(-) [PATCH 2] Add support for the SOCFPGA Cyclone V board boot/dts/socfpga.dtsi | 73 ++++++++++++ boot/dts/socfpga_cyclone5.dts | 90 +++++++++++++++ configs/socfpga_defconfig | 84 ++++++++++++++ mach-socfpga/include/mach/clkdev.h | 16 ++ mach-socfpga/include/mach/socfpga_cyclone5.h | 83 +++++++++++++ mach-socfpga/socfpga_cyclone5.c | 161 +++++++++++++++++++++++++++ tools/mach-types | 1 7 files changed, 508 insertions(+) Thanks, Dinh ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 13:50 [RFC]Add initial support for Altera's SOCFPGA hardward dinguyen at altera.com @ 2012-06-27 13:50 ` dinguyen at altera.com 2012-06-27 14:20 ` Thomas Petazzoni 2012-07-04 17:56 ` Rob Herring 2012-06-27 13:50 ` [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW dinguyen at altera.com 1 sibling, 2 replies; 47+ messages in thread From: dinguyen at altera.com @ 2012-06-27 13:50 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> Adding core definitions for Altera's SOCFPGA ARM platform. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> --- MAINTAINERS | 5 + arch/arm/Kconfig | 19 ++ arch/arm/Makefile | 1 + arch/arm/mach-socfpga/Kconfig | 21 ++ arch/arm/mach-socfpga/Makefile | 8 + arch/arm/mach-socfpga/Makefile.boot | 3 + arch/arm/mach-socfpga/clock.c | 50 ++++ arch/arm/mach-socfpga/common.c | 156 ++++++++++ arch/arm/mach-socfpga/common.h | 38 +++ arch/arm/mach-socfpga/dw_apb_timer.c | 164 +++++++++++ arch/arm/mach-socfpga/headsmp.S | 41 +++ arch/arm/mach-socfpga/hotplug.c | 125 ++++++++ arch/arm/mach-socfpga/include/mach/clock.h | 11 + arch/arm/mach-socfpga/include/mach/debug-macro.S | 29 ++ arch/arm/mach-socfpga/include/mach/dw_apb_timer.h | 38 +++ arch/arm/mach-socfpga/include/mach/io.h | 27 ++ arch/arm/mach-socfpga/include/mach/iomap.h | 37 +++ arch/arm/mach-socfpga/include/mach/irqs.h | 305 ++++++++++++++++++++ arch/arm/mach-socfpga/include/mach/memory.h | 32 ++ arch/arm/mach-socfpga/include/mach/smp.h | 15 + arch/arm/mach-socfpga/include/mach/socfpga-timer.h | 27 ++ arch/arm/mach-socfpga/include/mach/system.h | 31 ++ arch/arm/mach-socfpga/include/mach/timex.h | 19 ++ arch/arm/mach-socfpga/include/mach/uncompress.h | 44 +++ arch/arm/mach-socfpga/localtimer.c | 34 +++ arch/arm/mach-socfpga/platsmp.c | 154 ++++++++++ arch/arm/mm/Kconfig | 2 +- 27 files changed, 1435 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-socfpga/Kconfig create mode 100644 arch/arm/mach-socfpga/Makefile create mode 100644 arch/arm/mach-socfpga/Makefile.boot create mode 100644 arch/arm/mach-socfpga/clock.c create mode 100644 arch/arm/mach-socfpga/common.c create mode 100644 arch/arm/mach-socfpga/common.h create mode 100644 arch/arm/mach-socfpga/dw_apb_timer.c create mode 100644 arch/arm/mach-socfpga/headsmp.S create mode 100644 arch/arm/mach-socfpga/hotplug.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock.h create mode 100644 arch/arm/mach-socfpga/include/mach/debug-macro.S create mode 100644 arch/arm/mach-socfpga/include/mach/dw_apb_timer.h create mode 100644 arch/arm/mach-socfpga/include/mach/io.h create mode 100644 arch/arm/mach-socfpga/include/mach/iomap.h create mode 100644 arch/arm/mach-socfpga/include/mach/irqs.h create mode 100644 arch/arm/mach-socfpga/include/mach/memory.h create mode 100644 arch/arm/mach-socfpga/include/mach/smp.h create mode 100644 arch/arm/mach-socfpga/include/mach/socfpga-timer.h create mode 100644 arch/arm/mach-socfpga/include/mach/system.h create mode 100644 arch/arm/mach-socfpga/include/mach/timex.h create mode 100644 arch/arm/mach-socfpga/include/mach/uncompress.h create mode 100644 arch/arm/mach-socfpga/localtimer.c create mode 100644 arch/arm/mach-socfpga/platsmp.c diff --git a/MAINTAINERS b/MAINTAINERS index eb22272..193b4e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1103,6 +1103,11 @@ S: Supported F: arch/arm/mach-shmobile/ F: drivers/sh/ +ARM/SOCFPGA ARCHITECTURE +M: Dinh Nguyen <dinguyen@altera.com> +S: Supported +F: arch/arm/mach-socfpga/ + ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT M: Lennert Buytenhek <kernel@wantstofly.org> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a91009c..b1578e1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -250,6 +250,22 @@ choice prompt "ARM system type" default ARCH_VERSATILE +config ARCH_SOCFPGA + bool "Altera SOCFPGA family" + select CPU_V7 + select ARM_GIC + select ARM_AMBA + select CLKDEV_LOOKUP + select MIGHT_HAVE_CACHE_L2X0 + select HAVE_MACH_CLKDEV + select GENERIC_CLOCKEVENTS + select ARCH_WANT_OPTIONAL_GPIOLIB + select GPIO_PL061 if GPIOLIB + select NEED_MACH_MEMORY_H + select USE_OF + help + This enables support for Altera SOCFPGA Cyclone V platform + config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select ARM_AMBA @@ -1056,6 +1072,8 @@ source "arch/arm/mach-sa1100/Kconfig" source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" +source "arch/arm/mach-socfpga/Kconfig" + source "arch/arm/plat-spear/Kconfig" source "arch/arm/mach-s3c24xx/Kconfig" @@ -1596,6 +1614,7 @@ config HZ default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default AT91_TIMER_HZ if ARCH_AT91 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE + default SOCFPGA_TIMER_HZ if ARCH_SOCFPGA default 100 config THUMB2_KERNEL diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 0298b00..1fe5702 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -193,6 +193,7 @@ machine-$(CONFIG_MACH_SPEAR310) := spear3xx machine-$(CONFIG_MACH_SPEAR320) := spear3xx machine-$(CONFIG_MACH_SPEAR600) := spear6xx machine-$(CONFIG_ARCH_ZYNQ) := zynq +machine-$(CONFIG_ARCH_SOCFPGA) := socfpga # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig new file mode 100644 index 0000000..3fbbd0a --- /dev/null +++ b/arch/arm/mach-socfpga/Kconfig @@ -0,0 +1,21 @@ +choice + prompt "Altera SOCFPGA Platform" + default MACH_SOCFPGA_CYCLONE5 + depends on ARCH_SOCFPGA + help + Select SOCFPGA platform type + +config MACH_SOCFPGA_CYCLONE5 + bool "SOCFPGA Cyclone5 platform" + select HAVE_SMP + select PLAT_SOCFPGA_ETH + help + Include support for the Altera(R) Cyclone5 development platform. +endchoice + +config SOCFPGA_TIMER_HZ + int "Kernel internal timer frequency " + range 20 1024 + default "100" + help + Kernel internal timer frequency should be a divisor of 77161. diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile new file mode 100644 index 0000000..5502add --- /dev/null +++ b/arch/arm/mach-socfpga/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +obj-y := common.o clock.o dw_apb_timer.o +obj-$(CONFIG_MACH_SOCFPGA_CYCLONE5) += socfpga_cyclone5.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o \ No newline at end of file diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot new file mode 100644 index 0000000..7a1f3c0 --- /dev/null +++ b/arch/arm/mach-socfpga/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-socfpga/clock.c b/arch/arm/mach-socfpga/clock.c new file mode 100644 index 0000000..b5a82cd --- /dev/null +++ b/arch/arm/mach-socfpga/clock.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2004 ARM Limited. + * Written by Deep Blue Solutions Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/mutex.h> +#include <mach/clkdev.h> + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + long ret = -EIO; + if (clk->ops && clk->ops->round) + ret = clk->ops->round(clk, rate); + return ret; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EIO; + if (clk->ops && clk->ops->set) + ret = clk->ops->set(clk, rate); + return ret; +} +EXPORT_SYMBOL(clk_set_rate); diff --git a/arch/arm/mach-socfpga/common.c b/arch/arm/mach-socfpga/common.c new file mode 100644 index 0000000..a2c734a --- /dev/null +++ b/arch/arm/mach-socfpga/common.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/clkdev.h> +#include <linux/gfp.h> +#include <linux/of_platform.h> + +#include <mach/iomap.h> +#include <mach/socfpga_cyclone5.h> +#include <asm/irq.h> +#include <asm/mach-types.h> +#include <asm/hardware/arm_timer.h> + +#include <asm/mach/arch.h> +#include <asm/mach/irq.h> +#include <asm/mach/map.h> + +#include <mach/irqs.h> +#include <mach/socfpga-timer.h> + +#include <linux/mmc/dw_mmc.h> +#include <linux/serial_8250.h> + +#include "common.h" + +extern struct dw_mci_board sdmmc_platform_data; +extern struct dma_pl330_platdata dma_platform_data; + +#define DW_APB_UART_OF_COMPATIBLE "snps,dw-apb-uart" + +#define SOCFPGA_MPU_PERIHCLK_FREQ_HZ (800000000 / 4) +#define SOCFPGA_L4_MAIN_CLK (400000000) + +static struct clk dummy_apb_pclk; +static struct clk dummy_i2c_clk = { + .rate = 100000000, +}; +static struct clk dummy_spim_clk = { + .rate = 100000000, +}; +static struct clk mpu_periphclk = { + .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ, +}; + +static struct clk l4_main_clk = { + .rate = SOCFPGA_L4_MAIN_CLK, +}; + +static struct clk_lookup lookups[] = { + { /* Bus clock */ + .con_id = "apb_pclk", + .clk = &dummy_apb_pclk, + }, + { + .dev_id = "ffc04000.i2c", + .clk = &dummy_i2c_clk, + }, + { + .dev_id = "ffc05000.i2c", + .clk = &dummy_i2c_clk, + }, + { + .dev_id = "dw-spi-mmio.0", + .clk = &dummy_spim_clk, + }, + { + .dev_id = "dw-spi-mmio.1", + .clk = &dummy_spim_clk, + }, + { + .dev_id = "smp_twd", + .clk = &mpu_periphclk, + }, + { + .dev_id = "dma-pl330", + .clk = &l4_main_clk, + } +}; + +struct plat_serial8250_port uart_platform_data[] = { + { + .type = PORT_16850, + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | \ + UPF_FIXED_TYPE, + }, +}; + +void __init socfpga_init_early(void) +{ + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +} + +/* + * Where is the timer (VA)? + */ +void __iomem *sp_timer0_va_base; +void __iomem *sp_timer1_va_base; +void __iomem *osc_timer0_va_base; +void __iomem *osc_timer1_va_base; + +/* + * Set up the clock source and clock events devices + */ + +void __init socfpga_timer_init(void __iomem *src_timer_base, + void __iomem *event_timer_base, + unsigned int event_timer_irq) +{ + /* + * Initialise to a known state (all timers off) + */ + writel(0, sp_timer0_va_base + TIMER_CTRL); + writel(0, sp_timer1_va_base + TIMER_CTRL); + writel(0, osc_timer0_va_base + TIMER_CTRL); + writel(0, osc_timer1_va_base + TIMER_CTRL); + + dwapbt_clocksource_init(src_timer_base); + dwapbt_clockevents_init(event_timer_base, event_timer_irq); +} + +/* + * Setup the memory banks. + */ +void socfpga_fixup(struct tag *tags, char **from, struct meminfo *meminfo) +{ + meminfo->bank[0].start = 0x0; + meminfo->bank[0].size = SZ_256M; + meminfo->nr_banks = 1; +} + +int socfpga_notifier(struct device *device) +{ + struct device_node *dn = device->of_node; + + if (of_device_is_compatible(dn, DW_APB_UART_OF_COMPATIBLE)) + device->platform_data = &uart_platform_data; + return 0; +} diff --git a/arch/arm/mach-socfpga/common.h b/arch/arm/mach-socfpga/common.h new file mode 100644 index 0000000..7cad4f1 --- /dev/null +++ b/arch/arm/mach-socfpga/common.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __ASM_ARCH_SOCFPGA_H +#define __ASM_ARCH_SOCFPGA_H + +#include <asm/setup.h> + +struct machine_desc; + +extern void __iomem *sp_timer0_va_base; +extern void __iomem *sp_timer1_va_base; +extern void __iomem *osc_timer0_va_base; +extern void __iomem *osc_timer1_va_base; + +extern void socfpga_init_early(void); +extern void socfpga_fixup(struct tag *tags, char **from, + struct meminfo *meminfo); +extern void socfpga_timer_init(void __iomem *src_timer_base, + void __iomem *event_timer_base, + unsigned int event_timer_irq); +extern int socfpga_notifier(struct device *device); + +#endif diff --git a/arch/arm/mach-socfpga/dw_apb_timer.c b/arch/arm/mach-socfpga/dw_apb_timer.c new file mode 100644 index 0000000..64c8d96 --- /dev/null +++ b/arch/arm/mach-socfpga/dw_apb_timer.c @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/dw_apb_timer.h> +#include <mach/socfpga-timer.h> +#include <mach/iomap.h> +#include <mach/clock.h> + +#define TIMER_SP_FREQ_KHZ (SOCFPGA_SP_TIMER_FREQ_HZ / 1000) +#define TIMER_OSC_FREQ_KHZ (SOCFPGA_OSC_TIMER_FREQ_HZ / 1000) + +#define TIMER_RELOAD (TIMER_OSC_FREQ_KHZ * 1000 / HZ) + +static void __iomem *clksrc_base; + +static cycle_t dwapbt_read(struct clocksource *cs) +{ + return ~readl(clksrc_base + TIMER_VALUE); +} + +static struct clocksource clocksource_dwapbt = { + .name = "SP Timer 0", + .rating = 200, + .read = dwapbt_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void __init dwapbt_clocksource_init(void __iomem *base) +{ + struct clocksource *cs = &clocksource_dwapbt; + + clksrc_base = base; + + /* setup free-running clocksource */ + writel(0, clksrc_base + TIMER_CTRL); + writel(~0, clksrc_base + TIMER_LOAD); + writel(TIMER_CTRL_INTMASK | TIMER_CTRL_ENABLE, + clksrc_base + TIMER_CTRL); + + clocksource_register_khz(cs, TIMER_SP_FREQ_KHZ); +} + + +static void __iomem *clkevt_base; + +/* + * IRQ handler for the timer + */ +static irqreturn_t dwapbt_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + /* clear the interrupt */ + readl(clkevt_base + TIMER_INT_CLEAR); + + /* Ooppss... spurious interrupt */ + if (unlikely(!evt->event_handler)) + return IRQ_NONE; + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static void dwapbt_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long ctrl = 0; + + ctrl = readl(clkevt_base + TIMER_CTRL); + + /* Reset control register and disable the timer */ + writel(0, clkevt_base + TIMER_CTRL); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* Program load register */ + writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD); + + ctrl |= TIMER_CTRL_ENABLE; + ctrl |= TIMER_CTRL_PERIODIC; + ctrl &= ~TIMER_CTRL_INTMASK; + writel(ctrl, clkevt_base + TIMER_CTRL); + break; + + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl &= ~TIMER_CTRL_PERIODIC; + ctrl &= ~TIMER_CTRL_INTMASK; + writel(ctrl, clkevt_base + TIMER_CTRL); + break; + + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + break; + } +} + +static int dwapbt_set_next_event(unsigned long next, + struct clock_event_device *evt) +{ + unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); + + /* Disable timer */ + writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); + + writel(next, clkevt_base + TIMER_LOAD); + writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); + + return 0; +} + +static struct clock_event_device dwapbt_clockevent = { + .name = "OSC Timer 0", + .shift = 32, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = dwapbt_set_mode, + .set_next_event = dwapbt_set_next_event, + .rating = 250, + .cpumask = cpu_all_mask, +}; + +static struct irqaction dwapbt_timer_irq = { + .name = "timer", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = dwapbt_timer_interrupt, + .dev_id = &dwapbt_clockevent, +}; + +void __init dwapbt_clockevents_init(void __iomem *base, unsigned int timer_irq) +{ + struct clock_event_device *evt = &dwapbt_clockevent; + + clkevt_base = base; + + evt->irq = timer_irq; + evt->mult = div_sc(TIMER_OSC_FREQ_KHZ, NSEC_PER_MSEC, evt->shift); + evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); + evt->min_delta_ns = clockevent_delta2ns(0xf, evt); + + setup_irq(timer_irq, &dwapbt_timer_irq); + clockevents_register_device(evt); +} diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S new file mode 100644 index 0000000..e432aec --- /dev/null +++ b/arch/arm/mach-socfpga/headsmp.S @@ -0,0 +1,41 @@ +/* + * Modified from: linux/arch/arm/plat-versatile/headsmp.S + * + * Copyright (c) 2003 ARM Limited + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + + __INIT + +/* + * Entry point for secondary CPUs. + * This provides a "holding pen" into which all secondary cores are held + * until we're ready for them to initialise. + */ +ENTRY(socfpga_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + + .align +1: .long . + .long pen_release +ENDPROC(socfpga_secondary_startup) diff --git a/arch/arm/mach-socfpga/hotplug.c b/arch/arm/mach-socfpga/hotplug.c new file mode 100644 index 0000000..f9fc9ff --- /dev/null +++ b/arch/arm/mach-socfpga/hotplug.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> + +#include <asm/cacheflush.h> +#include <asm/cp15.h> +#include <asm/smp_plat.h> + +extern int pen_release; + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " mcr p15, 0, %1, c7, c10, 4\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C) + : "cc"); +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile("mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C) + : "cc"); +} + +static inline void platform_do_lowpower(unsigned int cpu, int *spurious) +{ + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts + */ + for (;;) { + /* + * here's the WFI + */ + asm volatile(".word 0xe320f003\n" + : : : "memory", "cc"); + + if (pen_release == cpu_logical_map(cpu)) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * Getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * Just note it happening - when we're woken, we can report + * its occurrence. + */ + (*spurious)++; + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return 1; +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ + int spurious = 0; + + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + platform_do_lowpower(cpu, &spurious); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); + + if (spurious) + pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-socfpga/include/mach/clock.h b/arch/arm/mach-socfpga/include/mach/clock.h new file mode 100644 index 0000000..5187064 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock.h @@ -0,0 +1,11 @@ +#ifndef __MACH_CLOCK_H +#define __MACH_CLOCK_H + +struct clk; + +struct clk_ops { + long (*round)(struct clk *, unsigned long); + int (*set)(struct clk *, unsigned long); +}; + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/mach-socfpga/include/mach/debug-macro.S new file mode 100644 index 0000000..d6283f5 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/debug-macro.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef DEBUG_LL_UART_OFFSET +#define DEBUG_LL_UART_OFFSET 0x00002000 +#elif DEBUG_LL_UART_OFFSET != 0x00002000 +#warning "DEBUG_LL_UART_OFFSET already defined to a different value" +#endif + +#ifndef DEBUG_LL_UART_OFFSET +#error "Unknown SOCFPGA platform" +#endif + + .macro addruart, rp, rv, tmp + mov \rp, #DEBUG_LL_UART_OFFSET + orr \rp, \rp, #0x00c00000 + orr \rv, \rp, #0xfe000000 @ virtual base + orr \rp, \rp, #0xff000000 @ physical base + .endm + +#define UART_SHIFT 2 + +#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-socfpga/include/mach/dw_apb_timer.h b/arch/arm/mach-socfpga/include/mach/dw_apb_timer.h new file mode 100644 index 0000000..3c58a56 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/dw_apb_timer.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef __ASM_ARM_HARDWARE_DW_APB_TIMER_H +#define __ASM_ARM_HARDWARE_DW_APB_TIMER_H + +/* Individual timer register */ +#define TIMER_LOAD 0x00 /* Load value rw */ +#define TIMER_VALUE 0x04 /* Current value ro */ +#define TIMER_CTRL 0x08 /* Control register rw */ +#define TIMER_INT_CLEAR 0x0c /* Interrupt clear ro */ +#define TIMER_INT_STAT 0x10 /* Interrupt status ro */ + +/* Shared timer register */ +#define TIMERS_INT_STAT 0xa0 /* Masked interrupt status ro */ +#define TIMERS_INT_CLEAR 0xa4 /* Interrupt clear ro */ +#define TIMERS_INT_STAT_RAW 0xa8 /* Raw interrupt status ro */ +#define TIMERS_VERSION 0xac /* Version */ + +#define TIMER_CTRL_ENABLE (1 << 0) /* Timer Enable = 1 */ +#define TIMER_CTRL_PERIODIC (1 << 1) /* Periodic mode = 0 */ +#define TIMER_CTRL_INTMASK (1 << 2) /* Interrupt mask = 1 */ + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/io.h b/arch/arm/mach-socfpga/include/mach/io.h new file mode 100644 index 0000000..ff150b0 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/io.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __MACH_ARCH_IO_H +#define __MACH_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/iomap.h b/arch/arm/mach-socfpga/include/mach/iomap.h new file mode 100644 index 0000000..656482d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/iomap.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __MACH_SOCFPGA_IOMAP_H +#define __MACH_SOCFPGA_IOMAP_H + +#include <asm/sizes.h> + +/* macro to get at IO space when running virtually */ +#ifdef CONFIG_MMU +/* + * Statically mapped addresses: + * + * 10xx xxxx -> fbxx xxxx + * 1exx xxxx -> fdxx xxxx + * 1fxx xxxx -> fexx xxxx + */ +#define IO_ADDRESS(x) (((x) & 0x03ffffff) + 0xfb000000) +#else +#define IO_ADDRESS(x) (x) +#endif +#define __io_address(n) IOMEM(IO_ADDRESS(n)) + +#endif \ No newline at end of file diff --git a/arch/arm/mach-socfpga/include/mach/irqs.h b/arch/arm/mach-socfpga/include/mach/irqs.h new file mode 100644 index 0000000..65db73a --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/irqs.h @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define IRQ_SOCFPGA_GIC_START 32 +#define IRQ_LOCALWDOG 30 + + +/* + * SOCFPGA interrupt sources + */ +#define IRQ_SOCFPGA_CPU0_PARITY (IRQ_SOCFPGA_GIC_START + 0) /* CPU0 parity */ +#define IRQ_SOCFPGA_CPU0_PARITY_BTAG (IRQ_SOCFPGA_GIC_START + 1) /* CPU0 parity BTAG */ +#define IRQ_SOCFPGA_CPU0_PARITY_GHB (IRQ_SOCFPGA_GIC_START + 2) /* CPU0 parity GHB */ +#define IRQ_SOCFPGA_CPU0_PARITY_ITAG (IRQ_SOCFPGA_GIC_START + 3) /* CPU0 parity ITAG */ +#define IRQ_SOCFPGA_CPU0_PARITY_IDATA (IRQ_SOCFPGA_GIC_START + 4) /* CPU0 parity IDATA */ +#define IRQ_SOCFPGA_CPU0_PARITY_TLB (IRQ_SOCFPGA_GIC_START + 5) /* CPU0 parity TLB */ +#define IRQ_SOCFPGA_CPU0_PARITY_DOUTER (IRQ_SOCFPGA_GIC_START + 6) /* CPU0 parity DOUTER */ +#define IRQ_SOCFPGA_CPU0_PARITY_DTAG (IRQ_SOCFPGA_GIC_START + 7) /* CPU0 parity DTAG */ +#define IRQ_SOCFPGA_CPU0_PARITY_DDATA (IRQ_SOCFPGA_GIC_START + 8) /* CPU0 parity DDATA */ +#define IRQ_SOCFPGA_CPU0_DEFLAGS0 (IRQ_SOCFPGA_GIC_START + 9) /* CPU0 deflasg 0 */ +#define IRQ_SOCFPGA_CPU0_DEFLAGS1 (IRQ_SOCFPGA_GIC_START + 10) /* CPU0 deflags 1 */ +#define IRQ_SOCFPGA_CPU0_DEFLAGS2 (IRQ_SOCFPGA_GIC_START + 11) /* CPU0 deflags 2 */ +#define IRQ_SOCFPGA_CPU0_DEFLAGS3 (IRQ_SOCFPGA_GIC_START + 12) /* CPU0 deflags 3 */ +#define IRQ_SOCFPGA_CPU0_DEFLAGS4 (IRQ_SOCFPGA_GIC_START + 13) /* CPU0 deflags 4 */ +#define IRQ_SOCFPGA_CPU0_DEFLAGS5 (IRQ_SOCFPGA_GIC_START + 14) /* CPU0 deflags 5 */ +#define IRQ_SOCFPGA_CPU0_DEFLAGS6 (IRQ_SOCFPGA_GIC_START + 15) /* CPU0 deflags 6 */ +#define IRQ_SOCFPGA_CPU1_PARITY (IRQ_SOCFPGA_GIC_START + 16) /* CPU1 parity */ +#define IRQ_SOCFPGA_CPU1_PARITY_BTAG (IRQ_SOCFPGA_GIC_START + 17) /* CPU1 parity BTAG */ +#define IRQ_SOCFPGA_CPU1_PARITY_GHB (IRQ_SOCFPGA_GIC_START + 18) /* CPU1 parity GHB */ +#define IRQ_SOCFPGA_CPU1_PARITY_ITAG (IRQ_SOCFPGA_GIC_START + 19) /* CPU1 parity ITAG */ +#define IRQ_SOCFPGA_CPU1_PARITY_IDATA (IRQ_SOCFPGA_GIC_START + 20) /* CPU1 parity IDATA */ +#define IRQ_SOCFPGA_CPU1_PARITY_TLB (IRQ_SOCFPGA_GIC_START + 21) /* CPU1 parity TLB */ +#define IRQ_SOCFPGA_CPU1_PARITY_DOUTER (IRQ_SOCFPGA_GIC_START + 22) /* CPU1 parity DOUTER */ +#define IRQ_SOCFPGA_CPU1_PARITY_DTAG (IRQ_SOCFPGA_GIC_START + 23) /* CPU1 parity DTAG */ +#define IRQ_SOCFPGA_CPU1_PARITY_DDATA (IRQ_SOCFPGA_GIC_START + 24) /* CPU1 parity DDATA */ +#define IRQ_SOCFPGA_CPU1_DEFLAGS0 (IRQ_SOCFPGA_GIC_START + 25) /* CPU1 deflags 0 */ +#define IRQ_SOCFPGA_CPU1_DEFLAGS1 (IRQ_SOCFPGA_GIC_START + 26) /* CPU1 deflags 1 */ +#define IRQ_SOCFPGA_CPU1_DEFLAGS2 (IRQ_SOCFPGA_GIC_START + 27) /* CPU1 deflags 2 */ +#define IRQ_SOCFPGA_CPU1_DEFLAGS3 (IRQ_SOCFPGA_GIC_START + 28) /* CPU1 deflags 3 */ +#define IRQ_SOCFPGA_CPU1_DEFLAGS4 (IRQ_SOCFPGA_GIC_START + 29) /* CPU1 deflags 4 */ +#define IRQ_SOCFPGA_CPU1_DEFLAGS5 (IRQ_SOCFPGA_GIC_START + 30) /* CPU1 deflags 5 */ +#define IRQ_SOCFPGA_CPU1_DEFLAGS6 (IRQ_SOCFPGA_GIC_START + 31) /* CPU1 deflags 6 */ +#define IRQ_SOCFPGA_SCU0_PARITY (IRQ_SOCFPGA_GIC_START + 32) /* SCU0 parity */ +#define IRQ_SOCFPGA_SCU1_PARITY (IRQ_SOCFPGA_GIC_START + 33) /* SCU1 parity */ +#define IRQ_SOCFPGA_SCU_EV_ABORT (IRQ_SOCFPGA_GIC_START + 34) /* SCU EV abort */ +#define IRQ_SOCFPGA_L2_ECC_WRITE (IRQ_SOCFPGA_GIC_START + 35) /* L2 ECC write */ +#define IRQ_SOCFPGA_L2_ECC_CERR (IRQ_SOCFPGA_GIC_START + 36) /* L2 ECC error corrected */ +#define IRQ_SOCFPGA_L2_ECC_UERR (IRQ_SOCFPGA_GIC_START + 37) /* L2 ECC error uncorrected */ +#define IRQ_SOCFPGA_L2 (IRQ_SOCFPGA_GIC_START + 38) /* L2 combined interrupts */ +#define IRQ_SOCFPGA_DDR_ECC_ERR (IRQ_SOCFPGA_GIC_START + 39) /* DDR ECC error */ +#define IRQ_SOCFPGA_F2S_FPGA0 (IRQ_SOCFPGA_GIC_START + 40) /* FPGA IRQ 0 */ +#define IRQ_SOCFPGA_F2S_FPGA1 (IRQ_SOCFPGA_GIC_START + 41) /* FPGA IRQ 1 */ +#define IRQ_SOCFPGA_F2S_FPGA2 (IRQ_SOCFPGA_GIC_START + 42) /* FPGA IRQ 2 */ +#define IRQ_SOCFPGA_F2S_FPGA3 (IRQ_SOCFPGA_GIC_START + 43) /* FPGA IRQ 3 */ +#define IRQ_SOCFPGA_F2S_FPGA4 (IRQ_SOCFPGA_GIC_START + 44) /* FPGA IRQ 4 */ +#define IRQ_SOCFPGA_F2S_FPGA5 (IRQ_SOCFPGA_GIC_START + 45) /* FPGA IRQ 5 */ +#define IRQ_SOCFPGA_F2S_FPGA6 (IRQ_SOCFPGA_GIC_START + 46) /* FPGA IRQ 6 */ +#define IRQ_SOCFPGA_F2S_FPGA7 (IRQ_SOCFPGA_GIC_START + 47) /* FPGA IRQ 7 */ +#define IRQ_SOCFPGA_F2S_FPGA8 (IRQ_SOCFPGA_GIC_START + 48) /* FPGA IRQ 8 */ +#define IRQ_SOCFPGA_F2S_FPGA9 (IRQ_SOCFPGA_GIC_START + 49) /* FPGA IRQ 9 */ +#define IRQ_SOCFPGA_F2S_FPGA10 (IRQ_SOCFPGA_GIC_START + 50) /* FPGA IRQ 10 */ +#define IRQ_SOCFPGA_F2S_FPGA11 (IRQ_SOCFPGA_GIC_START + 51) /* FPGA IRQ 11 */ +#define IRQ_SOCFPGA_F2S_FPGA12 (IRQ_SOCFPGA_GIC_START + 52) /* FPGA IRQ 12 */ +#define IRQ_SOCFPGA_F2S_FPGA13 (IRQ_SOCFPGA_GIC_START + 53) /* FPGA IRQ 13 */ +#define IRQ_SOCFPGA_F2S_FPGA14 (IRQ_SOCFPGA_GIC_START + 54) /* FPGA IRQ 14 */ +#define IRQ_SOCFPGA_F2S_FPGA15 (IRQ_SOCFPGA_GIC_START + 55) /* FPGA IRQ 15 */ +#define IRQ_SOCFPGA_F2S_FPGA16 (IRQ_SOCFPGA_GIC_START + 56) /* FPGA IRQ 16 */ +#define IRQ_SOCFPGA_F2S_FPGA17 (IRQ_SOCFPGA_GIC_START + 57) /* FPGA IRQ 17 */ +#define IRQ_SOCFPGA_F2S_FPGA18 (IRQ_SOCFPGA_GIC_START + 58) /* FPGA IRQ 18 */ +#define IRQ_SOCFPGA_F2S_FPGA19 (IRQ_SOCFPGA_GIC_START + 59) /* FPGA IRQ 19 */ +#define IRQ_SOCFPGA_F2S_FPGA20 (IRQ_SOCFPGA_GIC_START + 60) /* FPGA IRQ 20 */ +#define IRQ_SOCFPGA_F2S_FPGA21 (IRQ_SOCFPGA_GIC_START + 61) /* FPGA IRQ 21 */ +#define IRQ_SOCFPGA_F2S_FPGA22 (IRQ_SOCFPGA_GIC_START + 62) /* FPGA IRQ 22 */ +#define IRQ_SOCFPGA_F2S_FPGA23 (IRQ_SOCFPGA_GIC_START + 63) /* FPGA IRQ 23 */ +#define IRQ_SOCFPGA_F2S_FPGA24 (IRQ_SOCFPGA_GIC_START + 64) /* FPGA IRQ 24 */ +#define IRQ_SOCFPGA_F2S_FPGA25 (IRQ_SOCFPGA_GIC_START + 65) /* FPGA IRQ 25 */ +#define IRQ_SOCFPGA_F2S_FPGA26 (IRQ_SOCFPGA_GIC_START + 66) /* FPGA IRQ 26 */ +#define IRQ_SOCFPGA_F2S_FPGA27 (IRQ_SOCFPGA_GIC_START + 67) /* FPGA IRQ 27 */ +#define IRQ_SOCFPGA_F2S_FPGA28 (IRQ_SOCFPGA_GIC_START + 68) /* FPGA IRQ 28 */ +#define IRQ_SOCFPGA_F2S_FPGA29 (IRQ_SOCFPGA_GIC_START + 69) /* FPGA IRQ 29 */ +#define IRQ_SOCFPGA_F2S_FPGA30 (IRQ_SOCFPGA_GIC_START + 70) /* FPGA IRQ 30 */ +#define IRQ_SOCFPGA_F2S_FPGA31 (IRQ_SOCFPGA_GIC_START + 71) /* FPGA IRQ 31 */ +#define IRQ_SOCFPGA_F2S_FPGA32 (IRQ_SOCFPGA_GIC_START + 72) /* FPGA IRQ 32 */ +#define IRQ_SOCFPGA_F2S_FPGA33 (IRQ_SOCFPGA_GIC_START + 73) /* FPGA IRQ 33 */ +#define IRQ_SOCFPGA_F2S_FPGA34 (IRQ_SOCFPGA_GIC_START + 74) /* FPGA IRQ 34 */ +#define IRQ_SOCFPGA_F2S_FPGA35 (IRQ_SOCFPGA_GIC_START + 75) /* FPGA IRQ 35 */ +#define IRQ_SOCFPGA_F2S_FPGA36 (IRQ_SOCFPGA_GIC_START + 76) /* FPGA IRQ 36 */ +#define IRQ_SOCFPGA_F2S_FPGA37 (IRQ_SOCFPGA_GIC_START + 77) /* FPGA IRQ 37 */ +#define IRQ_SOCFPGA_F2S_FPGA38 (IRQ_SOCFPGA_GIC_START + 78) /* FPGA IRQ 38 */ +#define IRQ_SOCFPGA_F2S_FPGA39 (IRQ_SOCFPGA_GIC_START + 79) /* FPGA IRQ 39 */ +#define IRQ_SOCFPGA_F2S_FPGA40 (IRQ_SOCFPGA_GIC_START + 80) /* FPGA IRQ 40 */ +#define IRQ_SOCFPGA_F2S_FPGA41 (IRQ_SOCFPGA_GIC_START + 81) /* FPGA IRQ 41 */ +#define IRQ_SOCFPGA_F2S_FPGA42 (IRQ_SOCFPGA_GIC_START + 82) /* FPGA IRQ 42 */ +#define IRQ_SOCFPGA_F2S_FPGA43 (IRQ_SOCFPGA_GIC_START + 83) /* FPGA IRQ 43 */ +#define IRQ_SOCFPGA_F2S_FPGA44 (IRQ_SOCFPGA_GIC_START + 84) /* FPGA IRQ 44 */ +#define IRQ_SOCFPGA_F2S_FPGA45 (IRQ_SOCFPGA_GIC_START + 85) /* FPGA IRQ 45 */ +#define IRQ_SOCFPGA_F2S_FPGA46 (IRQ_SOCFPGA_GIC_START + 86) /* FPGA IRQ 46 */ +#define IRQ_SOCFPGA_F2S_FPGA47 (IRQ_SOCFPGA_GIC_START + 87) /* FPGA IRQ 47 */ +#define IRQ_SOCFPGA_F2S_FPGA48 (IRQ_SOCFPGA_GIC_START + 88) /* FPGA IRQ 48 */ +#define IRQ_SOCFPGA_F2S_FPGA49 (IRQ_SOCFPGA_GIC_START + 89) /* FPGA IRQ 49 */ +#define IRQ_SOCFPGA_F2S_FPGA50 (IRQ_SOCFPGA_GIC_START + 90) /* FPGA IRQ 50 */ +#define IRQ_SOCFPGA_F2S_FPGA51 (IRQ_SOCFPGA_GIC_START + 91) /* FPGA IRQ 51 */ +#define IRQ_SOCFPGA_F2S_FPGA52 (IRQ_SOCFPGA_GIC_START + 92) /* FPGA IRQ 52 */ +#define IRQ_SOCFPGA_F2S_FPGA53 (IRQ_SOCFPGA_GIC_START + 93) /* FPGA IRQ 53 */ +#define IRQ_SOCFPGA_F2S_FPGA54 (IRQ_SOCFPGA_GIC_START + 94) /* FPGA IRQ 54 */ +#define IRQ_SOCFPGA_F2S_FPGA55 (IRQ_SOCFPGA_GIC_START + 95) /* FPGA IRQ 55 */ +#define IRQ_SOCFPGA_F2S_FPGA56 (IRQ_SOCFPGA_GIC_START + 96) /* FPGA IRQ 56 */ +#define IRQ_SOCFPGA_F2S_FPGA57 (IRQ_SOCFPGA_GIC_START + 97) /* FPGA IRQ 57 */ +#define IRQ_SOCFPGA_F2S_FPGA58 (IRQ_SOCFPGA_GIC_START + 98) /* FPGA IRQ 58 */ +#define IRQ_SOCFPGA_F2S_FPGA59 (IRQ_SOCFPGA_GIC_START + 99) /* FPGA IRQ 59 */ +#define IRQ_SOCFPGA_F2S_FPGA60 (IRQ_SOCFPGA_GIC_START + 100) /* FPGA IRQ 60 */ +#define IRQ_SOCFPGA_F2S_FPGA61 (IRQ_SOCFPGA_GIC_START + 101) /* FPGA IRQ 61 */ +#define IRQ_SOCFPGA_F2S_FPGA62 (IRQ_SOCFPGA_GIC_START + 102) /* FPGA IRQ 62 */ +#define IRQ_SOCFPGA_F2S_FPGA63 (IRQ_SOCFPGA_GIC_START + 103) /* FPGA IRQ 63 */ +#define IRQ_SOCFPGA_DMA0 (IRQ_SOCFPGA_GIC_START + 104) /* DMA Channel 0 */ +#define IRQ_SOCFPGA_DMA1 (IRQ_SOCFPGA_GIC_START + 105) /* DMA Channel 1 */ +#define IRQ_SOCFPGA_DMA2 (IRQ_SOCFPGA_GIC_START + 106) /* DMA Channel 2 */ +#define IRQ_SOCFPGA_DMA3 (IRQ_SOCFPGA_GIC_START + 107) /* DMA Channel 3 */ +#define IRQ_SOCFPGA_DMA4 (IRQ_SOCFPGA_GIC_START + 108) /* DMA Channel 3 */ +#define IRQ_SOCFPGA_DMA5 (IRQ_SOCFPGA_GIC_START + 109) /* DMA Channel 5 */ +#define IRQ_SOCFPGA_DMA6 (IRQ_SOCFPGA_GIC_START + 110) /* DMA Channel 6 */ +#define IRQ_SOCFPGA_DMA7 (IRQ_SOCFPGA_GIC_START + 111) /* DMA Channel 7 */ +#define IRQ_SOCFPGA_DMA_ABORT (IRQ_SOCFPGA_GIC_START + 112) /* DMA abort */ +#define IRQ_SOCFPGA_DMA_CECC (IRQ_SOCFPGA_GIC_START + 113) /* DMA ECC corrected */ +#define IRQ_SOCFPGA_DMA_UECC (IRQ_SOCFPGA_GIC_START + 114) /* DMA ECC uncorrected */ +#define IRQ_SOCFPGA_EMAC0 (IRQ_SOCFPGA_GIC_START + 115) /* Gb-Ethernet MAC0 */ +#define IRQ_SOCFPGA_EMAC0_TX_CECC (IRQ_SOCFPGA_GIC_START + 116) /* Gb-Ethernet MAC0 ECC corrected */ +#define IRQ_SOCFPGA_EMAC0_TX_UECC (IRQ_SOCFPGA_GIC_START + 117) /* Gb-Ethernet MAC0 ECC uncorrected */ +#define IRQ_SOCFPGA_EMAC0_RX_CECC (IRQ_SOCFPGA_GIC_START + 118) /* Gb-Ethernet MAC0 ECC corrected */ +#define IRQ_SOCFPGA_EMAC0_RX_UECC (IRQ_SOCFPGA_GIC_START + 119) /* Gb-Ethernet MAC0 ECC uncorrected */ +#define IRQ_SOCFPGA_EMAC1 (IRQ_SOCFPGA_GIC_START + 120) /* Gb-Ethernet MAC1 */ +#define IRQ_SOCFPGA_EMAC1_TX_CECC (IRQ_SOCFPGA_GIC_START + 121) /* Gb-Ethernet MAC1 ECC corrected */ +#define IRQ_SOCFPGA_EMAC1_TX_UECC (IRQ_SOCFPGA_GIC_START + 122) /* Gb-Ethernet MAC1 ECC uncorrected */ +#define IRQ_SOCFPGA_EMAC1_RX_CECC (IRQ_SOCFPGA_GIC_START + 123) /* Gb-Ethernet MAC1 ECC corrected */ +#define IRQ_SOCFPGA_EMAC1_RX_UECC (IRQ_SOCFPGA_GIC_START + 124) /* Gb-Ethernet MAC1 ECC uncorrected */ +#define IRQ_SOCFPGA_USB0 (IRQ_SOCFPGA_GIC_START + 125) /* USB 0 generic */ +#define IRQ_SOCFPGA_USB0_CECC (IRQ_SOCFPGA_GIC_START + 126) /* USB 0 ECC corrected */ +#define IRQ_SOCFPGA_USB0_UECC (IRQ_SOCFPGA_GIC_START + 127) /* USB 0 ECC uncorrected */ +#define IRQ_SOCFPGA_USB1 (IRQ_SOCFPGA_GIC_START + 128) /* USB 1 generic */ +#define IRQ_SOCFPGA_USB1_CECC (IRQ_SOCFPGA_GIC_START + 129) /* USB 1 ECC corrected */ +#define IRQ_SOCFPGA_USB1_UECC (IRQ_SOCFPGA_GIC_START + 130) /* USB 1 ECC uncorrected */ +#define IRQ_SOCFPGA_CAN0_STS (IRQ_SOCFPGA_GIC_START + 131) /* CAN0 interrupt 0 */ +#define IRQ_SOCFPGA_CAN0_MO (IRQ_SOCFPGA_GIC_START + 132) /* CAN0 interrupt 1 */ +#define IRQ_SOCFPGA_CAN0_CECC (IRQ_SOCFPGA_GIC_START + 133) /* CAN0 ECC corrected */ +#define IRQ_SOCFPGA_CAN0_UECC (IRQ_SOCFPGA_GIC_START + 134) /* CAN0 ECC uncorrected */ +#define IRQ_SOCFPGA_CAN1_STS (IRQ_SOCFPGA_GIC_START + 135) /* CAN1 interrupt 0 */ +#define IRQ_SOCFPGA_CAN1_MO (IRQ_SOCFPGA_GIC_START + 136) /* CAN1 interrupt 1 */ +#define IRQ_SOCFPGA_CAN1_CECC (IRQ_SOCFPGA_GIC_START + 137) /* CAN1 ECC corrected */ +#define IRQ_SOCFPGA_CAN1_UECC (IRQ_SOCFPGA_GIC_START + 138) /* CAN1 ECC uncorrected */ +#define IRQ_SOCFPGA_SDMMC (IRQ_SOCFPGA_GIC_START + 139) /* SD/MMC */ +#define IRQ_SOCFPGA_SDMMC_PA_CECC (IRQ_SOCFPGA_GIC_START + 140) /* SD/MMC PortA ECC corrected */ +#define IRQ_SOCFPGA_SDMMC_PA_UECC (IRQ_SOCFPGA_GIC_START + 141) /* SD/MMC PortA ECC uncorrected */ +#define IRQ_SOCFPGA_SDMMC_PB_CECC (IRQ_SOCFPGA_GIC_START + 142) /* SD/MMC PortB ECC corrected */ +#define IRQ_SOCFPGA_SDMMC_PB_UECC (IRQ_SOCFPGA_GIC_START + 143) /* SD/MMC PortB ECC uncorrected */ +#define IRQ_SOCFPGA_NAND (IRQ_SOCFPGA_GIC_START + 144) /* NAND */ +#define IRQ_SOCFPGA_NAND_R_CECC (IRQ_SOCFPGA_GIC_START + 145) /* NAND read ECC corrected */ +#define IRQ_SOCFPGA_NAND_R_UECC (IRQ_SOCFPGA_GIC_START + 146) /* NAND read ECC uncorrected */ +#define IRQ_SOCFPGA_NAND_W_CECC (IRQ_SOCFPGA_GIC_START + 147) /* NAND write ECC corrected */ +#define IRQ_SOCFPGA_NAND_W_UECC (IRQ_SOCFPGA_GIC_START + 148) /* NAND write ECC uncorrected */ +#define IRQ_SOCFPGA_NAND_E_CECC (IRQ_SOCFPGA_GIC_START + 149) /* NAND error ECC corrected */ +#define IRQ_SOCFPGA_NAND_E_UECC (IRQ_SOCFPGA_GIC_START + 150) /* NAND error ECC uncorrected */ +#define IRQ_SOCFPGA_QSPI (IRQ_SOCFPGA_GIC_START + 151) /* Quad-SPI */ +#define IRQ_SOCFPGA_QSPI_CECC (IRQ_SOCFPGA_GIC_START + 152) /* Quad-SPI ECC corrected */ +#define IRQ_SOCFPGA_QSPI_UECC (IRQ_SOCFPGA_GIC_START + 153) /* Quad-SPI ECC uncorrected */ +#define IRQ_SOCFPGA_SPI0 (IRQ_SOCFPGA_GIC_START + 154) /* SPI 0 */ +#define IRQ_SOCFPGA_SPI1 (IRQ_SOCFPGA_GIC_START + 155) /* SPI 1 */ +#define IRQ_SOCFPGA_SPI2 (IRQ_SOCFPGA_GIC_START + 156) /* SPI 2 */ +#define IRQ_SOCFPGA_SPI3 (IRQ_SOCFPGA_GIC_START + 157) /* SPI 3 */ +#define IRQ_SOCFPGA_I2C0 (IRQ_SOCFPGA_GIC_START + 158) /* I2C 0 */ +#define IRQ_SOCFPGA_I2C1 (IRQ_SOCFPGA_GIC_START + 159) /* I2C 1 */ +#define IRQ_SOCFPGA_I2C2 (IRQ_SOCFPGA_GIC_START + 160) /* I2C 2 */ +#define IRQ_SOCFPGA_I2C3 (IRQ_SOCFPGA_GIC_START + 161) /* I2C 3 */ +#define IRQ_SOCFPGA_UART0 (IRQ_SOCFPGA_GIC_START + 162) /* UART 0 */ +#define IRQ_SOCFPGA_UART1 (IRQ_SOCFPGA_GIC_START + 163) /* UART 1 */ +#define IRQ_SOCFPGA_GPIO0 (IRQ_SOCFPGA_GIC_START + 164) /* GPIO 0 */ +#define IRQ_SOCFPGA_GPIO1 (IRQ_SOCFPGA_GIC_START + 165) /* GPIO 1 */ +#define IRQ_SOCFPGA_GPIO2 (IRQ_SOCFPGA_GIC_START + 166) /* GPIO 2 */ +#define IRQ_SOCFPGA_L4_SP_TIMER0 (IRQ_SOCFPGA_GIC_START + 167) /* L4 SP timer 0 */ +#define IRQ_SOCFPGA_L4_SP_TIMER1 (IRQ_SOCFPGA_GIC_START + 168) /* L4 SP timer 1 */ +#define IRQ_SOCFPGA_L4_OSC1_TIMER0 (IRQ_SOCFPGA_GIC_START + 169) /* L4 OSC1 timer 0 */ +#define IRQ_SOCFPGA_L4_OSC1_TIMER1 (IRQ_SOCFPGA_GIC_START + 170) /* L4 OSC1 timer 1 */ +#define IRQ_SOCFPGA_WD0 (IRQ_SOCFPGA_GIC_START + 171) /* Watchdog timer 0 */ +#define IRQ_SOCFPGA_WD1 (IRQ_SOCFPGA_GIC_START + 172) /* Watchdog timer 1 */ +#define IRQ_SOCFPGA_CLK_MAN (IRQ_SOCFPGA_GIC_START + 173) /* Clock manager */ +#define IRQ_SOCFPGA_MPU_WAKE (IRQ_SOCFPGA_GIC_START + 174) /* MPU wake */ +#define IRQ_SOCFPGA_FPGA_MON (IRQ_SOCFPGA_GIC_START + 175) /* FPGA monitor */ +#define IRQ_SOCFPGA_CPU0_CTI (IRQ_SOCFPGA_GIC_START + 176) /* Coresight CPU0 CTI */ +#define IRQ_SOCFPGA_CPU1_CTI (IRQ_SOCFPGA_GIC_START + 177) /* Coresight CPU1 CTI */ +#define IRQ_SOCFPGA_OCRAM_CECC (IRQ_SOCFPGA_GIC_START + 178) /* on-chip RAM ECC corrected */ +#define IRQ_SOCFPGA_OCRAM_UECC (IRQ_SOCFPGA_GIC_START + 179) /* on-chip RAM ECC uncorrected */ + +/* Soft IRQ */ +#define SOFTIRQ_SOCFPGA_DMADEV (IRQ_SOCFPGA_GIC_START + 180) +#define SOFTIRQ_SOCFPGA_GPIO_0_0 (IRQ_SOCFPGA_GIC_START + 181) +#define SOFTIRQ_SOCFPGA_GPIO_0_1 (IRQ_SOCFPGA_GIC_START + 182) +#define SOFTIRQ_SOCFPGA_GPIO_0_2 (IRQ_SOCFPGA_GIC_START + 183) +#define SOFTIRQ_SOCFPGA_GPIO_0_3 (IRQ_SOCFPGA_GIC_START + 184) +#define SOFTIRQ_SOCFPGA_GPIO_0_4 (IRQ_SOCFPGA_GIC_START + 185) +#define SOFTIRQ_SOCFPGA_GPIO_0_5 (IRQ_SOCFPGA_GIC_START + 186) +#define SOFTIRQ_SOCFPGA_GPIO_0_6 (IRQ_SOCFPGA_GIC_START + 187) +#define SOFTIRQ_SOCFPGA_GPIO_0_7 (IRQ_SOCFPGA_GIC_START + 188) +#define SOFTIRQ_SOCFPGA_GPIO_0_8 (IRQ_SOCFPGA_GIC_START + 189) +#define SOFTIRQ_SOCFPGA_GPIO_0_9 (IRQ_SOCFPGA_GIC_START + 190) +#define SOFTIRQ_SOCFPGA_GPIO_0_10 (IRQ_SOCFPGA_GIC_START + 191) +#define SOFTIRQ_SOCFPGA_GPIO_0_11 (IRQ_SOCFPGA_GIC_START + 192) +#define SOFTIRQ_SOCFPGA_GPIO_0_12 (IRQ_SOCFPGA_GIC_START + 193) +#define SOFTIRQ_SOCFPGA_GPIO_0_13 (IRQ_SOCFPGA_GIC_START + 194) +#define SOFTIRQ_SOCFPGA_GPIO_0_14 (IRQ_SOCFPGA_GIC_START + 195) +#define SOFTIRQ_SOCFPGA_GPIO_0_15 (IRQ_SOCFPGA_GIC_START + 196) +#define SOFTIRQ_SOCFPGA_GPIO_0_16 (IRQ_SOCFPGA_GIC_START + 197) +#define SOFTIRQ_SOCFPGA_GPIO_0_17 (IRQ_SOCFPGA_GIC_START + 198) +#define SOFTIRQ_SOCFPGA_GPIO_0_18 (IRQ_SOCFPGA_GIC_START + 199) +#define SOFTIRQ_SOCFPGA_GPIO_0_19 (IRQ_SOCFPGA_GIC_START + 200) +#define SOFTIRQ_SOCFPGA_GPIO_0_20 (IRQ_SOCFPGA_GIC_START + 201) +#define SOFTIRQ_SOCFPGA_GPIO_0_21 (IRQ_SOCFPGA_GIC_START + 202) +#define SOFTIRQ_SOCFPGA_GPIO_0_22 (IRQ_SOCFPGA_GIC_START + 203) +#define SOFTIRQ_SOCFPGA_GPIO_0_23 (IRQ_SOCFPGA_GIC_START + 204) +#define SOFTIRQ_SOCFPGA_GPIO_0_24 (IRQ_SOCFPGA_GIC_START + 205) +#define SOFTIRQ_SOCFPGA_GPIO_0_25 (IRQ_SOCFPGA_GIC_START + 206) +#define SOFTIRQ_SOCFPGA_GPIO_0_26 (IRQ_SOCFPGA_GIC_START + 207) +#define SOFTIRQ_SOCFPGA_GPIO_0_27 (IRQ_SOCFPGA_GIC_START + 208) +#define SOFTIRQ_SOCFPGA_GPIO_0_28 (IRQ_SOCFPGA_GIC_START + 209) +#define SOFTIRQ_SOCFPGA_GPIO_0_29 (IRQ_SOCFPGA_GIC_START + 210) +#define SOFTIRQ_SOCFPGA_GPIO_1_0 (IRQ_SOCFPGA_GIC_START + 211) +#define SOFTIRQ_SOCFPGA_GPIO_1_1 (IRQ_SOCFPGA_GIC_START + 212) +#define SOFTIRQ_SOCFPGA_GPIO_1_2 (IRQ_SOCFPGA_GIC_START + 213) +#define SOFTIRQ_SOCFPGA_GPIO_1_3 (IRQ_SOCFPGA_GIC_START + 214) +#define SOFTIRQ_SOCFPGA_GPIO_1_4 (IRQ_SOCFPGA_GIC_START + 215) +#define SOFTIRQ_SOCFPGA_GPIO_1_5 (IRQ_SOCFPGA_GIC_START + 216) +#define SOFTIRQ_SOCFPGA_GPIO_1_6 (IRQ_SOCFPGA_GIC_START + 217) +#define SOFTIRQ_SOCFPGA_GPIO_1_7 (IRQ_SOCFPGA_GIC_START + 218) +#define SOFTIRQ_SOCFPGA_GPIO_1_8 (IRQ_SOCFPGA_GIC_START + 219) +#define SOFTIRQ_SOCFPGA_GPIO_1_9 (IRQ_SOCFPGA_GIC_START + 220) +#define SOFTIRQ_SOCFPGA_GPIO_1_10 (IRQ_SOCFPGA_GIC_START + 221) +#define SOFTIRQ_SOCFPGA_GPIO_1_11 (IRQ_SOCFPGA_GIC_START + 222) +#define SOFTIRQ_SOCFPGA_GPIO_1_12 (IRQ_SOCFPGA_GIC_START + 223) +#define SOFTIRQ_SOCFPGA_GPIO_1_13 (IRQ_SOCFPGA_GIC_START + 224) +#define SOFTIRQ_SOCFPGA_GPIO_1_14 (IRQ_SOCFPGA_GIC_START + 225) +#define SOFTIRQ_SOCFPGA_GPIO_1_15 (IRQ_SOCFPGA_GIC_START + 226) +#define SOFTIRQ_SOCFPGA_GPIO_1_16 (IRQ_SOCFPGA_GIC_START + 227) +#define SOFTIRQ_SOCFPGA_GPIO_1_17 (IRQ_SOCFPGA_GIC_START + 228) +#define SOFTIRQ_SOCFPGA_GPIO_1_18 (IRQ_SOCFPGA_GIC_START + 229) +#define SOFTIRQ_SOCFPGA_GPIO_1_19 (IRQ_SOCFPGA_GIC_START + 230) +#define SOFTIRQ_SOCFPGA_GPIO_1_20 (IRQ_SOCFPGA_GIC_START + 231) +#define SOFTIRQ_SOCFPGA_GPIO_1_21 (IRQ_SOCFPGA_GIC_START + 232) +#define SOFTIRQ_SOCFPGA_GPIO_1_22 (IRQ_SOCFPGA_GIC_START + 233) +#define SOFTIRQ_SOCFPGA_GPIO_1_23 (IRQ_SOCFPGA_GIC_START + 234) +#define SOFTIRQ_SOCFPGA_GPIO_1_24 (IRQ_SOCFPGA_GIC_START + 235) +#define SOFTIRQ_SOCFPGA_GPIO_1_25 (IRQ_SOCFPGA_GIC_START + 236) +#define SOFTIRQ_SOCFPGA_GPIO_1_26 (IRQ_SOCFPGA_GIC_START + 237) +#define SOFTIRQ_SOCFPGA_GPIO_1_27 (IRQ_SOCFPGA_GIC_START + 238) +#define SOFTIRQ_SOCFPGA_GPIO_1_28 (IRQ_SOCFPGA_GIC_START + 239) +#define SOFTIRQ_SOCFPGA_GPIO_1_29 (IRQ_SOCFPGA_GIC_START + 240) +#define SOFTIRQ_SOCFPGA_GPIO_2_0 (IRQ_SOCFPGA_GIC_START + 241) +#define SOFTIRQ_SOCFPGA_GPIO_2_1 (IRQ_SOCFPGA_GIC_START + 242) +#define SOFTIRQ_SOCFPGA_GPIO_2_2 (IRQ_SOCFPGA_GIC_START + 243) +#define SOFTIRQ_SOCFPGA_GPIO_2_3 (IRQ_SOCFPGA_GIC_START + 244) +#define SOFTIRQ_SOCFPGA_GPIO_2_4 (IRQ_SOCFPGA_GIC_START + 245) +#define SOFTIRQ_SOCFPGA_GPIO_2_5 (IRQ_SOCFPGA_GIC_START + 246) +#define SOFTIRQ_SOCFPGA_GPIO_2_6 (IRQ_SOCFPGA_GIC_START + 247) +#define SOFTIRQ_SOCFPGA_GPIO_2_7 (IRQ_SOCFPGA_GIC_START + 248) +#define SOFTIRQ_SOCFPGA_GPIO_2_8 (IRQ_SOCFPGA_GIC_START + 249) +#define SOFTIRQ_SOCFPGA_GPIO_2_9 (IRQ_SOCFPGA_GIC_START + 250) +#define SOFTIRQ_SOCFPGA_GPIO_2_10 (IRQ_SOCFPGA_GIC_START + 251) +#define SOFTIRQ_SOCFPGA_GPIO_2_11 (IRQ_SOCFPGA_GIC_START + 252) +#define SOFTIRQ_SOCFPGA_GPIO_2_12 (IRQ_SOCFPGA_GIC_START + 253) +#define SOFTIRQ_SOCFPGA_GPIO_2_13 (IRQ_SOCFPGA_GIC_START + 254) +#define SOFTIRQ_SOCFPGA_GPIO_2_14 (IRQ_SOCFPGA_GIC_START + 255) +#define SOFTIRQ_SOCFPGA_GPIO_2_15 (IRQ_SOCFPGA_GIC_START + 256) +#define SOFTIRQ_SOCFPGA_GPIO_2_16 (IRQ_SOCFPGA_GIC_START + 257) +#define SOFTIRQ_SOCFPGA_GPIO_2_17 (IRQ_SOCFPGA_GIC_START + 258) +#define SOFTIRQ_SOCFPGA_GPIO_2_18 (IRQ_SOCFPGA_GIC_START + 259) +#define SOFTIRQ_SOCFPGA_GPIO_2_19 (IRQ_SOCFPGA_GIC_START + 260) +#define SOFTIRQ_SOCFPGA_GPIO_2_20 (IRQ_SOCFPGA_GIC_START + 261) +#define SOFTIRQ_SOCFPGA_GPIO_2_21 (IRQ_SOCFPGA_GIC_START + 262) +#define SOFTIRQ_SOCFPGA_GPIO_2_22 (IRQ_SOCFPGA_GIC_START + 263) +#define SOFTIRQ_SOCFPGA_GPIO_2_23 (IRQ_SOCFPGA_GIC_START + 264) +#define SOFTIRQ_SOCFPGA_GPIO_2_24 (IRQ_SOCFPGA_GIC_START + 265) +#define SOFTIRQ_SOCFPGA_GPIO_2_25 (IRQ_SOCFPGA_GIC_START + 266) +#define SOFTIRQ_SOCFPGA_GPIO_2_26 (IRQ_SOCFPGA_GIC_START + 267) +#define SOFTIRQ_SOCFPGA_GPIO_2_27 (IRQ_SOCFPGA_GIC_START + 268) +#define SOFTIRQ_SOCFPGA_GPIO_2_28 (IRQ_SOCFPGA_GIC_START + 269) +#define SOFTIRQ_SOCFPGA_GPIO_2_29 (IRQ_SOCFPGA_GIC_START + 270) + +#define NR_IRQS 512 + +#define MAX_GIC_NR 1 + +#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-socfpga/include/mach/memory.h b/arch/arm/mach-socfpga/include/mach/memory.h new file mode 100644 index 0000000..88e0ae9 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/memory.h @@ -0,0 +1,32 @@ +/* + * + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#define PLAT_PHYS_OFFSET UL(0x00000000) + +#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) + +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) +#endif + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/smp.h b/arch/arm/mach-socfpga/include/mach/smp.h new file mode 100644 index 0000000..07cc087 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/smp.h @@ -0,0 +1,15 @@ +/* + * SMP support + */ + +#ifndef __MACH_SMP_H +#define __MACH_SMP_H + +#include <asm/hardware/gic.h> + +static inline void smp_cross_call(const struct cpumask *mask, int ipi) +{ + gic_raise_softirq(mask, ipi); +} + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/socfpga-timer.h b/arch/arm/mach-socfpga/include/mach/socfpga-timer.h new file mode 100644 index 0000000..9d577f9 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/socfpga-timer.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __SOCFPGA_TIMER +#define __SOCFPGA_TIMER + +#define SOCFPGA_SP_TIMER_FREQ_HZ 2400000 +#define SOCFPGA_OSC_TIMER_FREQ_HZ 2400000 + +void dwapbt_clocksource_init(void __iomem *); +void dwapbt_clockevents_init(void __iomem *, unsigned int); + +#endif /* __SOCFPGA_TIMER */ diff --git a/arch/arm/mach-socfpga/include/mach/system.h b/arch/arm/mach-socfpga/include/mach/system.h new file mode 100644 index 0000000..c76834c --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * Modified from arch/arm/mach-realview/include/mach/system.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/timex.h b/arch/arm/mach-socfpga/include/mach/timex.h new file mode 100644 index 0000000..43df435 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/timex.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2003 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h new file mode 100644 index 0000000..1525dbd --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/uncompress.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#include <linux/serial_reg.h> +#include <mach/socfpga_cyclone5.h> + +#define UART8250_UART_THR(base) (*(unsigned char *)((base) + 0x0)) +#define UART8250_UART_LSR(base) (*(unsigned char *)((base) + 0x14)) + +/* + * This does not append a newline + */ +static inline void putc(int c) +{ + unsigned long base = SOCFPGA_UART0_BASE; + + while ((UART8250_UART_LSR(base) & UART_LSR_THRE) == 0) + barrier(); + + UART8250_UART_THR(base) = c; +} + +/* + * Not implemented + */ +static inline void flush(void) +{ +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-socfpga/localtimer.c b/arch/arm/mach-socfpga/localtimer.c new file mode 100644 index 0000000..4aa9221 --- /dev/null +++ b/arch/arm/mach-socfpga/localtimer.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/clockchips.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> + +#include <asm/smp_twd.h> + +/* + * Setup the local clock events for a CPU. + */ +int __cpuinit socfpga_local_timer_setup(struct clock_event_device *evt) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "arm,smp-twd"); + if (!twd_base) { + twd_base = of_iomap(np, 0); + WARN_ON(!twd_base); + } + evt->irq = irq_of_parse_and_map(np, 0); + twd_timer_setup(evt); + return 0; +} + diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c new file mode 100644 index 0000000..5cd148f --- /dev/null +++ b/arch/arm/mach-socfpga/platsmp.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/smp.h> +#include <linux/io.h> +#include <linux/delay.h> + +#include <mach/iomap.h> +#include <mach/socfpga_cyclone5.h> +#include <asm/hardware/gic.h> +#include <asm/mach-types.h> +#include <asm/smp_scu.h> +#include <asm/cacheflush.h> +#include <asm/smp_plat.h> + +#include "common.h" + +extern void socfpga_secondary_startup(void); + +/* + * control for which core is the next to come out of the secondary + * boot "holding pen" + */ +int __cpuinitdata pen_release = -1; + +/* + * Write pen_release in a way that is guaranteed to be visible to all + * observers, irrespective of whether they're taking part in coherency + * or not. This is necessary for the hotplug code to work reliably. + */ +static void __cpuinit write_pen_release(int val) +{ + pen_release = val; + smp_wmb(); + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); +} + +static DEFINE_SPINLOCK(boot_lock); + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + write_pen_release(-1); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + /* + * Set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * This is really belt and braces; we hold unintended secondary + * CPUs in the holding pen until we're ready for them. However, + * since we haven't sent them a soft interrupt, they shouldn't + * be there. + */ + write_pen_release(cpu_logical_map(cpu)); + + /* + * Send the secondary CPU a soft interrupt, thereby causing + * the boot monitor to read the system wide flags register, + * and branch to the address found there. + */ + gic_raise_softirq(cpumask_of(cpu), 1); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + return pen_release != -1 ? -ENOSYS : 0; +} + +static void __iomem *scu_base_addr(void) +{ + return __io_address(SOCFPGA_MPUSCU_BASE); +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +void __init smp_init_cpus(void) +{ + void __iomem *scu_base = scu_base_addr(); + unsigned int i, ncores; + + ncores = scu_base ? scu_get_core_count(scu_base) : 1; + + /* sanity check */ + if (ncores > nr_cpu_ids) { + pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", + ncores, nr_cpu_ids); + ncores = nr_cpu_ids; + } + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); +} + +void __init platform_smp_prepare_cpus(unsigned int max_cpus) +{ + scu_enable(scu_base_addr()); + + /* + * Write the address of secondary startup into the + * system-wide flags register. The BootMonitor waits + * until it receives a soft interrupt, and then the + * secondary CPU branches to this address. + */ + __raw_writel(virt_to_phys(socfpga_secondary_startup), + __io_address(SOCFPGA_SMP_FLAG)); +} diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 101b968..2f9a81e 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -381,7 +381,7 @@ config CPU_V6K # ARMv7 config CPU_V7 - bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX + bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_SOCFPGA select CPU_32v6K select CPU_32v7 select CPU_ABRT_EV7 -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 13:50 ` [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform dinguyen at altera.com @ 2012-06-27 14:20 ` Thomas Petazzoni 2012-06-27 18:05 ` Pavel Machek ` (4 more replies) 2012-07-04 17:56 ` Rob Herring 1 sibling, 5 replies; 47+ messages in thread From: Thomas Petazzoni @ 2012-06-27 14:20 UTC (permalink / raw) To: linux-arm-kernel Hello Dinh, Below a few comments from my modest experience on the mach-mvebu SoC support. Le Wed, 27 Jun 2012 08:50:06 -0500, <dinguyen@altera.com> a ?crit : > +config ARCH_SOCFPGA Is SOCFPGA a good name? It seems like a very generic name. Shouldn't it be ARCH_ALTERA_SOCFPGA a better name? I suspect other vendors will provide a SoC together with a FPGA. > +choice > + prompt "Altera SOCFPGA Platform" > + default MACH_SOCFPGA_CYCLONE5 > + depends on ARCH_SOCFPGA > + help > + Select SOCFPGA platform type > + > +config MACH_SOCFPGA_CYCLONE5 > + bool "SOCFPGA Cyclone5 platform" > + select HAVE_SMP > + select PLAT_SOCFPGA_ETH > + help > + Include support for the Altera(R) Cyclone5 development platform. > +endchoice Why do you need a "choice" here? The code should be able to support building multiple platforms at once. And even more: for a given SoC variant, we now generally only want one config options, the board-level details being abstracted out by the device tree. > index 0000000..7a1f3c0 > --- /dev/null > +++ b/arch/arm/mach-socfpga/Makefile.boot > @@ -0,0 +1,3 @@ > +zreladdr-y := 0x00008000 > +params_phys-y := 0x00000100 > +initrd_phys-y := 0x00800000 With the device tree, the params_phys-y and initrd_phys-y variables are useless. > +#include <linux/module.h> > +#include <linux/kernel.h> > +#include <linux/errno.h> > +#include <linux/clk.h> > +#include <linux/mutex.h> > +#include <mach/clkdev.h> > + > +int clk_enable(struct clk *clk) > +{ > + return 0; > +} > +EXPORT_SYMBOL(clk_enable); > + > +void clk_disable(struct clk *clk) > +{ > +} > +EXPORT_SYMBOL(clk_disable); > + > +unsigned long clk_get_rate(struct clk *clk) > +{ > + return clk->rate; > +} > +EXPORT_SYMBOL(clk_get_rate); > + > +long clk_round_rate(struct clk *clk, unsigned long rate) > +{ > + long ret = -EIO; > + if (clk->ops && clk->ops->round) > + ret = clk->ops->round(clk, rate); > + return ret; > +} > +EXPORT_SYMBOL(clk_round_rate); > + > +int clk_set_rate(struct clk *clk, unsigned long rate) > +{ > + int ret = -EIO; > + if (clk->ops && clk->ops->set) > + ret = clk->ops->set(clk, rate); > + return ret; > +} > +EXPORT_SYMBOL(clk_set_rate); I don't think the ARM maintainers want more implementations of the clock API. New SoCs should instead use the new clock framework in drivers/clk/. See Documentation/clk.txt for details. You can for example look at the mxs or spear implementations for examples. > +extern struct dw_mci_board sdmmc_platform_data; > +extern struct dma_pl330_platdata dma_platform_data; > + > +#define DW_APB_UART_OF_COMPATIBLE "snps,dw-apb-uart" > + > +#define SOCFPGA_MPU_PERIHCLK_FREQ_HZ (800000000 / 4) > +#define SOCFPGA_L4_MAIN_CLK (400000000) > + > +static struct clk dummy_apb_pclk; > +static struct clk dummy_i2c_clk = { > + .rate = 100000000, > +}; > +static struct clk dummy_spim_clk = { > + .rate = 100000000, > +}; > +static struct clk mpu_periphclk = { > + .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ, > +}; > + > +static struct clk l4_main_clk = { > + .rate = SOCFPGA_L4_MAIN_CLK, > +}; > + > +static struct clk_lookup lookups[] = { > + { /* Bus clock */ > + .con_id = "apb_pclk", > + .clk = &dummy_apb_pclk, > + }, > + { > + .dev_id = "ffc04000.i2c", > + .clk = &dummy_i2c_clk, > + }, > + { > + .dev_id = "ffc05000.i2c", > + .clk = &dummy_i2c_clk, > + }, > + { > + .dev_id = "dw-spi-mmio.0", > + .clk = &dummy_spim_clk, > + }, > + { > + .dev_id = "dw-spi-mmio.1", > + .clk = &dummy_spim_clk, > + }, > + { > + .dev_id = "smp_twd", > + .clk = &mpu_periphclk, > + }, > + { > + .dev_id = "dma-pl330", > + .clk = &l4_main_clk, > + } > +}; These should use the clock framework. > +struct plat_serial8250_port uart_platform_data[] = { > + { > + .type = PORT_16850, > + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | \ > + UPF_FIXED_TYPE, > + }, > +}; This sounds strange. Why aren't you using the ns16850 compatible string to instantiate the UART devices directly from your device tree? > +/* > + * Set up the clock source and clock events devices > + */ > + > +void __init socfpga_timer_init(void __iomem *src_timer_base, > + void __iomem *event_timer_base, > + unsigned int event_timer_irq) > +{ > + /* > + * Initialise to a known state (all timers off) > + */ > + writel(0, sp_timer0_va_base + TIMER_CTRL); > + writel(0, sp_timer1_va_base + TIMER_CTRL); > + writel(0, osc_timer0_va_base + TIMER_CTRL); > + writel(0, osc_timer1_va_base + TIMER_CTRL); Shouldn't this be done within the timer driver itself? > +/* > + * Setup the memory banks. > + */ > +void socfpga_fixup(struct tag *tags, char **from, struct meminfo *meminfo) > +{ > + meminfo->bank[0].start = 0x0; > + meminfo->bank[0].size = SZ_256M; > + meminfo->nr_banks = 1; > +} Looks strange. Those informations are now normally passed in the device tree. > +int socfpga_notifier(struct device *device) > +{ > + struct device_node *dn = device->of_node; > + > + if (of_device_is_compatible(dn, DW_APB_UART_OF_COMPATIBLE)) > + device->platform_data = &uart_platform_data; > + return 0; > +} If using the ns16850 device tree compatible string works to instantiate your UART, you could remove this. > +++ b/arch/arm/mach-socfpga/dw_apb_timer.c The clocksource/clockevents driver now go into drivers/clocksource/, and the corresponding maintainers should be CC'ed (Thomas Gleixner and John Stultz. > +/* > + * SOCFPGA interrupt sources > + */ > +#define IRQ_SOCFPGA_CPU0_PARITY (IRQ_SOCFPGA_GIC_START + 0) /* CPU0 parity */ > +#define IRQ_SOCFPGA_CPU0_PARITY_BTAG (IRQ_SOCFPGA_GIC_START + 1) /* CPU0 parity BTAG */ > +#define IRQ_SOCFPGA_CPU0_PARITY_GHB (IRQ_SOCFPGA_GIC_START + 2) /* CPU0 parity GHB */ > +#define IRQ_SOCFPGA_CPU0_PARITY_ITAG (IRQ_SOCFPGA_GIC_START + 3) /* CPU0 parity ITAG */ > +#define IRQ_SOCFPGA_CPU0_PARITY_IDATA (IRQ_SOCFPGA_GIC_START + 4) /* CPU0 parity IDATA */ > +#define IRQ_SOCFPGA_CPU0_PARITY_TLB (IRQ_SOCFPGA_GIC_START + 5) /* CPU0 parity TLB */ > +#define IRQ_SOCFPGA_CPU0_PARITY_DOUTER (IRQ_SOCFPGA_GIC_START + 6) /* CPU0 parity DOUTER */ > +#define IRQ_SOCFPGA_CPU0_PARITY_DTAG (IRQ_SOCFPGA_GIC_START + 7) /* CPU0 parity DTAG */ > +#define IRQ_SOCFPGA_CPU0_PARITY_DDATA (IRQ_SOCFPGA_GIC_START + 8) /* CPU0 parity DDATA */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS0 (IRQ_SOCFPGA_GIC_START + 9) /* CPU0 deflasg 0 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS1 (IRQ_SOCFPGA_GIC_START + 10) /* CPU0 deflags 1 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS2 (IRQ_SOCFPGA_GIC_START + 11) /* CPU0 deflags 2 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS3 (IRQ_SOCFPGA_GIC_START + 12) /* CPU0 deflags 3 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS4 (IRQ_SOCFPGA_GIC_START + 13) /* CPU0 deflags 4 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS5 (IRQ_SOCFPGA_GIC_START + 14) /* CPU0 deflags 5 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS6 (IRQ_SOCFPGA_GIC_START + 15) /* CPU0 deflags 6 */ > +#define IRQ_SOCFPGA_CPU1_PARITY (IRQ_SOCFPGA_GIC_START + 16) /* CPU1 parity */ > +#define IRQ_SOCFPGA_CPU1_PARITY_BTAG (IRQ_SOCFPGA_GIC_START + 17) /* CPU1 parity BTAG */ > +#define IRQ_SOCFPGA_CPU1_PARITY_GHB (IRQ_SOCFPGA_GIC_START + 18) /* CPU1 parity GHB */ > +#define IRQ_SOCFPGA_CPU1_PARITY_ITAG (IRQ_SOCFPGA_GIC_START + 19) /* CPU1 parity ITAG */ > +#define IRQ_SOCFPGA_CPU1_PARITY_IDATA (IRQ_SOCFPGA_GIC_START + 20) /* CPU1 parity IDATA */ > +#define IRQ_SOCFPGA_CPU1_PARITY_TLB (IRQ_SOCFPGA_GIC_START + 21) /* CPU1 parity TLB */ > +#define IRQ_SOCFPGA_CPU1_PARITY_DOUTER (IRQ_SOCFPGA_GIC_START + 22) /* CPU1 parity DOUTER */ > +#define IRQ_SOCFPGA_CPU1_PARITY_DTAG (IRQ_SOCFPGA_GIC_START + 23) /* CPU1 parity DTAG */ > +#define IRQ_SOCFPGA_CPU1_PARITY_DDATA (IRQ_SOCFPGA_GIC_START + 24) /* CPU1 parity DDATA */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS0 (IRQ_SOCFPGA_GIC_START + 25) /* CPU1 deflags 0 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS1 (IRQ_SOCFPGA_GIC_START + 26) /* CPU1 deflags 1 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS2 (IRQ_SOCFPGA_GIC_START + 27) /* CPU1 deflags 2 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS3 (IRQ_SOCFPGA_GIC_START + 28) /* CPU1 deflags 3 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS4 (IRQ_SOCFPGA_GIC_START + 29) /* CPU1 deflags 4 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS5 (IRQ_SOCFPGA_GIC_START + 30) /* CPU1 deflags 5 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS6 (IRQ_SOCFPGA_GIC_START + 31) /* CPU1 deflags 6 */ > +#define IRQ_SOCFPGA_SCU0_PARITY (IRQ_SOCFPGA_GIC_START + 32) /* SCU0 parity */ > +#define IRQ_SOCFPGA_SCU1_PARITY (IRQ_SOCFPGA_GIC_START + 33) /* SCU1 parity */ > +#define IRQ_SOCFPGA_SCU_EV_ABORT (IRQ_SOCFPGA_GIC_START + 34) /* SCU EV abort */ > +#define IRQ_SOCFPGA_L2_ECC_WRITE (IRQ_SOCFPGA_GIC_START + 35) /* L2 ECC write */ > +#define IRQ_SOCFPGA_L2_ECC_CERR (IRQ_SOCFPGA_GIC_START + 36) /* L2 ECC error corrected */ > +#define IRQ_SOCFPGA_L2_ECC_UERR (IRQ_SOCFPGA_GIC_START + 37) /* L2 ECC error uncorrected */ > +#define IRQ_SOCFPGA_L2 (IRQ_SOCFPGA_GIC_START + 38) /* L2 combined interrupts */ > +#define IRQ_SOCFPGA_DDR_ECC_ERR (IRQ_SOCFPGA_GIC_START + 39) /* DDR ECC error */ > +#define IRQ_SOCFPGA_F2S_FPGA0 (IRQ_SOCFPGA_GIC_START + 40) /* FPGA IRQ 0 */ > +#define IRQ_SOCFPGA_F2S_FPGA1 (IRQ_SOCFPGA_GIC_START + 41) /* FPGA IRQ 1 */ > +#define IRQ_SOCFPGA_F2S_FPGA2 (IRQ_SOCFPGA_GIC_START + 42) /* FPGA IRQ 2 */ > +#define IRQ_SOCFPGA_F2S_FPGA3 (IRQ_SOCFPGA_GIC_START + 43) /* FPGA IRQ 3 */ > +#define IRQ_SOCFPGA_F2S_FPGA4 (IRQ_SOCFPGA_GIC_START + 44) /* FPGA IRQ 4 */ > +#define IRQ_SOCFPGA_F2S_FPGA5 (IRQ_SOCFPGA_GIC_START + 45) /* FPGA IRQ 5 */ > +#define IRQ_SOCFPGA_F2S_FPGA6 (IRQ_SOCFPGA_GIC_START + 46) /* FPGA IRQ 6 */ > +#define IRQ_SOCFPGA_F2S_FPGA7 (IRQ_SOCFPGA_GIC_START + 47) /* FPGA IRQ 7 */ > +#define IRQ_SOCFPGA_F2S_FPGA8 (IRQ_SOCFPGA_GIC_START + 48) /* FPGA IRQ 8 */ > +#define IRQ_SOCFPGA_F2S_FPGA9 (IRQ_SOCFPGA_GIC_START + 49) /* FPGA IRQ 9 */ > +#define IRQ_SOCFPGA_F2S_FPGA10 (IRQ_SOCFPGA_GIC_START + 50) /* FPGA IRQ 10 */ > +#define IRQ_SOCFPGA_F2S_FPGA11 (IRQ_SOCFPGA_GIC_START + 51) /* FPGA IRQ 11 */ > +#define IRQ_SOCFPGA_F2S_FPGA12 (IRQ_SOCFPGA_GIC_START + 52) /* FPGA IRQ 12 */ > +#define IRQ_SOCFPGA_F2S_FPGA13 (IRQ_SOCFPGA_GIC_START + 53) /* FPGA IRQ 13 */ > +#define IRQ_SOCFPGA_F2S_FPGA14 (IRQ_SOCFPGA_GIC_START + 54) /* FPGA IRQ 14 */ > +#define IRQ_SOCFPGA_F2S_FPGA15 (IRQ_SOCFPGA_GIC_START + 55) /* FPGA IRQ 15 */ > +#define IRQ_SOCFPGA_F2S_FPGA16 (IRQ_SOCFPGA_GIC_START + 56) /* FPGA IRQ 16 */ > +#define IRQ_SOCFPGA_F2S_FPGA17 (IRQ_SOCFPGA_GIC_START + 57) /* FPGA IRQ 17 */ > +#define IRQ_SOCFPGA_F2S_FPGA18 (IRQ_SOCFPGA_GIC_START + 58) /* FPGA IRQ 18 */ > +#define IRQ_SOCFPGA_F2S_FPGA19 (IRQ_SOCFPGA_GIC_START + 59) /* FPGA IRQ 19 */ > +#define IRQ_SOCFPGA_F2S_FPGA20 (IRQ_SOCFPGA_GIC_START + 60) /* FPGA IRQ 20 */ > +#define IRQ_SOCFPGA_F2S_FPGA21 (IRQ_SOCFPGA_GIC_START + 61) /* FPGA IRQ 21 */ > +#define IRQ_SOCFPGA_F2S_FPGA22 (IRQ_SOCFPGA_GIC_START + 62) /* FPGA IRQ 22 */ > +#define IRQ_SOCFPGA_F2S_FPGA23 (IRQ_SOCFPGA_GIC_START + 63) /* FPGA IRQ 23 */ > +#define IRQ_SOCFPGA_F2S_FPGA24 (IRQ_SOCFPGA_GIC_START + 64) /* FPGA IRQ 24 */ > +#define IRQ_SOCFPGA_F2S_FPGA25 (IRQ_SOCFPGA_GIC_START + 65) /* FPGA IRQ 25 */ > +#define IRQ_SOCFPGA_F2S_FPGA26 (IRQ_SOCFPGA_GIC_START + 66) /* FPGA IRQ 26 */ > +#define IRQ_SOCFPGA_F2S_FPGA27 (IRQ_SOCFPGA_GIC_START + 67) /* FPGA IRQ 27 */ > +#define IRQ_SOCFPGA_F2S_FPGA28 (IRQ_SOCFPGA_GIC_START + 68) /* FPGA IRQ 28 */ > +#define IRQ_SOCFPGA_F2S_FPGA29 (IRQ_SOCFPGA_GIC_START + 69) /* FPGA IRQ 29 */ > +#define IRQ_SOCFPGA_F2S_FPGA30 (IRQ_SOCFPGA_GIC_START + 70) /* FPGA IRQ 30 */ > +#define IRQ_SOCFPGA_F2S_FPGA31 (IRQ_SOCFPGA_GIC_START + 71) /* FPGA IRQ 31 */ > +#define IRQ_SOCFPGA_F2S_FPGA32 (IRQ_SOCFPGA_GIC_START + 72) /* FPGA IRQ 32 */ > +#define IRQ_SOCFPGA_F2S_FPGA33 (IRQ_SOCFPGA_GIC_START + 73) /* FPGA IRQ 33 */ > +#define IRQ_SOCFPGA_F2S_FPGA34 (IRQ_SOCFPGA_GIC_START + 74) /* FPGA IRQ 34 */ > +#define IRQ_SOCFPGA_F2S_FPGA35 (IRQ_SOCFPGA_GIC_START + 75) /* FPGA IRQ 35 */ > +#define IRQ_SOCFPGA_F2S_FPGA36 (IRQ_SOCFPGA_GIC_START + 76) /* FPGA IRQ 36 */ > +#define IRQ_SOCFPGA_F2S_FPGA37 (IRQ_SOCFPGA_GIC_START + 77) /* FPGA IRQ 37 */ > +#define IRQ_SOCFPGA_F2S_FPGA38 (IRQ_SOCFPGA_GIC_START + 78) /* FPGA IRQ 38 */ > +#define IRQ_SOCFPGA_F2S_FPGA39 (IRQ_SOCFPGA_GIC_START + 79) /* FPGA IRQ 39 */ > +#define IRQ_SOCFPGA_F2S_FPGA40 (IRQ_SOCFPGA_GIC_START + 80) /* FPGA IRQ 40 */ > +#define IRQ_SOCFPGA_F2S_FPGA41 (IRQ_SOCFPGA_GIC_START + 81) /* FPGA IRQ 41 */ > +#define IRQ_SOCFPGA_F2S_FPGA42 (IRQ_SOCFPGA_GIC_START + 82) /* FPGA IRQ 42 */ > +#define IRQ_SOCFPGA_F2S_FPGA43 (IRQ_SOCFPGA_GIC_START + 83) /* FPGA IRQ 43 */ > +#define IRQ_SOCFPGA_F2S_FPGA44 (IRQ_SOCFPGA_GIC_START + 84) /* FPGA IRQ 44 */ > +#define IRQ_SOCFPGA_F2S_FPGA45 (IRQ_SOCFPGA_GIC_START + 85) /* FPGA IRQ 45 */ > +#define IRQ_SOCFPGA_F2S_FPGA46 (IRQ_SOCFPGA_GIC_START + 86) /* FPGA IRQ 46 */ > +#define IRQ_SOCFPGA_F2S_FPGA47 (IRQ_SOCFPGA_GIC_START + 87) /* FPGA IRQ 47 */ > +#define IRQ_SOCFPGA_F2S_FPGA48 (IRQ_SOCFPGA_GIC_START + 88) /* FPGA IRQ 48 */ > +#define IRQ_SOCFPGA_F2S_FPGA49 (IRQ_SOCFPGA_GIC_START + 89) /* FPGA IRQ 49 */ > +#define IRQ_SOCFPGA_F2S_FPGA50 (IRQ_SOCFPGA_GIC_START + 90) /* FPGA IRQ 50 */ > +#define IRQ_SOCFPGA_F2S_FPGA51 (IRQ_SOCFPGA_GIC_START + 91) /* FPGA IRQ 51 */ > +#define IRQ_SOCFPGA_F2S_FPGA52 (IRQ_SOCFPGA_GIC_START + 92) /* FPGA IRQ 52 */ > +#define IRQ_SOCFPGA_F2S_FPGA53 (IRQ_SOCFPGA_GIC_START + 93) /* FPGA IRQ 53 */ > +#define IRQ_SOCFPGA_F2S_FPGA54 (IRQ_SOCFPGA_GIC_START + 94) /* FPGA IRQ 54 */ > +#define IRQ_SOCFPGA_F2S_FPGA55 (IRQ_SOCFPGA_GIC_START + 95) /* FPGA IRQ 55 */ > +#define IRQ_SOCFPGA_F2S_FPGA56 (IRQ_SOCFPGA_GIC_START + 96) /* FPGA IRQ 56 */ > +#define IRQ_SOCFPGA_F2S_FPGA57 (IRQ_SOCFPGA_GIC_START + 97) /* FPGA IRQ 57 */ > +#define IRQ_SOCFPGA_F2S_FPGA58 (IRQ_SOCFPGA_GIC_START + 98) /* FPGA IRQ 58 */ > +#define IRQ_SOCFPGA_F2S_FPGA59 (IRQ_SOCFPGA_GIC_START + 99) /* FPGA IRQ 59 */ > +#define IRQ_SOCFPGA_F2S_FPGA60 (IRQ_SOCFPGA_GIC_START + 100) /* FPGA IRQ 60 */ > +#define IRQ_SOCFPGA_F2S_FPGA61 (IRQ_SOCFPGA_GIC_START + 101) /* FPGA IRQ 61 */ > +#define IRQ_SOCFPGA_F2S_FPGA62 (IRQ_SOCFPGA_GIC_START + 102) /* FPGA IRQ 62 */ > +#define IRQ_SOCFPGA_F2S_FPGA63 (IRQ_SOCFPGA_GIC_START + 103) /* FPGA IRQ 63 */ > +#define IRQ_SOCFPGA_DMA0 (IRQ_SOCFPGA_GIC_START + 104) /* DMA Channel 0 */ > +#define IRQ_SOCFPGA_DMA1 (IRQ_SOCFPGA_GIC_START + 105) /* DMA Channel 1 */ > +#define IRQ_SOCFPGA_DMA2 (IRQ_SOCFPGA_GIC_START + 106) /* DMA Channel 2 */ > +#define IRQ_SOCFPGA_DMA3 (IRQ_SOCFPGA_GIC_START + 107) /* DMA Channel 3 */ > +#define IRQ_SOCFPGA_DMA4 (IRQ_SOCFPGA_GIC_START + 108) /* DMA Channel 3 */ > +#define IRQ_SOCFPGA_DMA5 (IRQ_SOCFPGA_GIC_START + 109) /* DMA Channel 5 */ > +#define IRQ_SOCFPGA_DMA6 (IRQ_SOCFPGA_GIC_START + 110) /* DMA Channel 6 */ > +#define IRQ_SOCFPGA_DMA7 (IRQ_SOCFPGA_GIC_START + 111) /* DMA Channel 7 */ > +#define IRQ_SOCFPGA_DMA_ABORT (IRQ_SOCFPGA_GIC_START + 112) /* DMA abort */ > +#define IRQ_SOCFPGA_DMA_CECC (IRQ_SOCFPGA_GIC_START + 113) /* DMA ECC corrected */ > +#define IRQ_SOCFPGA_DMA_UECC (IRQ_SOCFPGA_GIC_START + 114) /* DMA ECC uncorrected */ > +#define IRQ_SOCFPGA_EMAC0 (IRQ_SOCFPGA_GIC_START + 115) /* Gb-Ethernet MAC0 */ > +#define IRQ_SOCFPGA_EMAC0_TX_CECC (IRQ_SOCFPGA_GIC_START + 116) /* Gb-Ethernet MAC0 ECC corrected */ > +#define IRQ_SOCFPGA_EMAC0_TX_UECC (IRQ_SOCFPGA_GIC_START + 117) /* Gb-Ethernet MAC0 ECC uncorrected */ > +#define IRQ_SOCFPGA_EMAC0_RX_CECC (IRQ_SOCFPGA_GIC_START + 118) /* Gb-Ethernet MAC0 ECC corrected */ > +#define IRQ_SOCFPGA_EMAC0_RX_UECC (IRQ_SOCFPGA_GIC_START + 119) /* Gb-Ethernet MAC0 ECC uncorrected */ > +#define IRQ_SOCFPGA_EMAC1 (IRQ_SOCFPGA_GIC_START + 120) /* Gb-Ethernet MAC1 */ > +#define IRQ_SOCFPGA_EMAC1_TX_CECC (IRQ_SOCFPGA_GIC_START + 121) /* Gb-Ethernet MAC1 ECC corrected */ > +#define IRQ_SOCFPGA_EMAC1_TX_UECC (IRQ_SOCFPGA_GIC_START + 122) /* Gb-Ethernet MAC1 ECC uncorrected */ > +#define IRQ_SOCFPGA_EMAC1_RX_CECC (IRQ_SOCFPGA_GIC_START + 123) /* Gb-Ethernet MAC1 ECC corrected */ > +#define IRQ_SOCFPGA_EMAC1_RX_UECC (IRQ_SOCFPGA_GIC_START + 124) /* Gb-Ethernet MAC1 ECC uncorrected */ > +#define IRQ_SOCFPGA_USB0 (IRQ_SOCFPGA_GIC_START + 125) /* USB 0 generic */ > +#define IRQ_SOCFPGA_USB0_CECC (IRQ_SOCFPGA_GIC_START + 126) /* USB 0 ECC corrected */ > +#define IRQ_SOCFPGA_USB0_UECC (IRQ_SOCFPGA_GIC_START + 127) /* USB 0 ECC uncorrected */ > +#define IRQ_SOCFPGA_USB1 (IRQ_SOCFPGA_GIC_START + 128) /* USB 1 generic */ > +#define IRQ_SOCFPGA_USB1_CECC (IRQ_SOCFPGA_GIC_START + 129) /* USB 1 ECC corrected */ > +#define IRQ_SOCFPGA_USB1_UECC (IRQ_SOCFPGA_GIC_START + 130) /* USB 1 ECC uncorrected */ > +#define IRQ_SOCFPGA_CAN0_STS (IRQ_SOCFPGA_GIC_START + 131) /* CAN0 interrupt 0 */ > +#define IRQ_SOCFPGA_CAN0_MO (IRQ_SOCFPGA_GIC_START + 132) /* CAN0 interrupt 1 */ > +#define IRQ_SOCFPGA_CAN0_CECC (IRQ_SOCFPGA_GIC_START + 133) /* CAN0 ECC corrected */ > +#define IRQ_SOCFPGA_CAN0_UECC (IRQ_SOCFPGA_GIC_START + 134) /* CAN0 ECC uncorrected */ > +#define IRQ_SOCFPGA_CAN1_STS (IRQ_SOCFPGA_GIC_START + 135) /* CAN1 interrupt 0 */ > +#define IRQ_SOCFPGA_CAN1_MO (IRQ_SOCFPGA_GIC_START + 136) /* CAN1 interrupt 1 */ > +#define IRQ_SOCFPGA_CAN1_CECC (IRQ_SOCFPGA_GIC_START + 137) /* CAN1 ECC corrected */ > +#define IRQ_SOCFPGA_CAN1_UECC (IRQ_SOCFPGA_GIC_START + 138) /* CAN1 ECC uncorrected */ > +#define IRQ_SOCFPGA_SDMMC (IRQ_SOCFPGA_GIC_START + 139) /* SD/MMC */ > +#define IRQ_SOCFPGA_SDMMC_PA_CECC (IRQ_SOCFPGA_GIC_START + 140) /* SD/MMC PortA ECC corrected */ > +#define IRQ_SOCFPGA_SDMMC_PA_UECC (IRQ_SOCFPGA_GIC_START + 141) /* SD/MMC PortA ECC uncorrected */ > +#define IRQ_SOCFPGA_SDMMC_PB_CECC (IRQ_SOCFPGA_GIC_START + 142) /* SD/MMC PortB ECC corrected */ > +#define IRQ_SOCFPGA_SDMMC_PB_UECC (IRQ_SOCFPGA_GIC_START + 143) /* SD/MMC PortB ECC uncorrected */ > +#define IRQ_SOCFPGA_NAND (IRQ_SOCFPGA_GIC_START + 144) /* NAND */ > +#define IRQ_SOCFPGA_NAND_R_CECC (IRQ_SOCFPGA_GIC_START + 145) /* NAND read ECC corrected */ > +#define IRQ_SOCFPGA_NAND_R_UECC (IRQ_SOCFPGA_GIC_START + 146) /* NAND read ECC uncorrected */ > +#define IRQ_SOCFPGA_NAND_W_CECC (IRQ_SOCFPGA_GIC_START + 147) /* NAND write ECC corrected */ > +#define IRQ_SOCFPGA_NAND_W_UECC (IRQ_SOCFPGA_GIC_START + 148) /* NAND write ECC uncorrected */ > +#define IRQ_SOCFPGA_NAND_E_CECC (IRQ_SOCFPGA_GIC_START + 149) /* NAND error ECC corrected */ > +#define IRQ_SOCFPGA_NAND_E_UECC (IRQ_SOCFPGA_GIC_START + 150) /* NAND error ECC uncorrected */ > +#define IRQ_SOCFPGA_QSPI (IRQ_SOCFPGA_GIC_START + 151) /* Quad-SPI */ > +#define IRQ_SOCFPGA_QSPI_CECC (IRQ_SOCFPGA_GIC_START + 152) /* Quad-SPI ECC corrected */ > +#define IRQ_SOCFPGA_QSPI_UECC (IRQ_SOCFPGA_GIC_START + 153) /* Quad-SPI ECC uncorrected */ > +#define IRQ_SOCFPGA_SPI0 (IRQ_SOCFPGA_GIC_START + 154) /* SPI 0 */ > +#define IRQ_SOCFPGA_SPI1 (IRQ_SOCFPGA_GIC_START + 155) /* SPI 1 */ > +#define IRQ_SOCFPGA_SPI2 (IRQ_SOCFPGA_GIC_START + 156) /* SPI 2 */ > +#define IRQ_SOCFPGA_SPI3 (IRQ_SOCFPGA_GIC_START + 157) /* SPI 3 */ > +#define IRQ_SOCFPGA_I2C0 (IRQ_SOCFPGA_GIC_START + 158) /* I2C 0 */ > +#define IRQ_SOCFPGA_I2C1 (IRQ_SOCFPGA_GIC_START + 159) /* I2C 1 */ > +#define IRQ_SOCFPGA_I2C2 (IRQ_SOCFPGA_GIC_START + 160) /* I2C 2 */ > +#define IRQ_SOCFPGA_I2C3 (IRQ_SOCFPGA_GIC_START + 161) /* I2C 3 */ > +#define IRQ_SOCFPGA_UART0 (IRQ_SOCFPGA_GIC_START + 162) /* UART 0 */ > +#define IRQ_SOCFPGA_UART1 (IRQ_SOCFPGA_GIC_START + 163) /* UART 1 */ > +#define IRQ_SOCFPGA_GPIO0 (IRQ_SOCFPGA_GIC_START + 164) /* GPIO 0 */ > +#define IRQ_SOCFPGA_GPIO1 (IRQ_SOCFPGA_GIC_START + 165) /* GPIO 1 */ > +#define IRQ_SOCFPGA_GPIO2 (IRQ_SOCFPGA_GIC_START + 166) /* GPIO 2 */ > +#define IRQ_SOCFPGA_L4_SP_TIMER0 (IRQ_SOCFPGA_GIC_START + 167) /* L4 SP timer 0 */ > +#define IRQ_SOCFPGA_L4_SP_TIMER1 (IRQ_SOCFPGA_GIC_START + 168) /* L4 SP timer 1 */ > +#define IRQ_SOCFPGA_L4_OSC1_TIMER0 (IRQ_SOCFPGA_GIC_START + 169) /* L4 OSC1 timer 0 */ > +#define IRQ_SOCFPGA_L4_OSC1_TIMER1 (IRQ_SOCFPGA_GIC_START + 170) /* L4 OSC1 timer 1 */ > +#define IRQ_SOCFPGA_WD0 (IRQ_SOCFPGA_GIC_START + 171) /* Watchdog timer 0 */ > +#define IRQ_SOCFPGA_WD1 (IRQ_SOCFPGA_GIC_START + 172) /* Watchdog timer 1 */ > +#define IRQ_SOCFPGA_CLK_MAN (IRQ_SOCFPGA_GIC_START + 173) /* Clock manager */ > +#define IRQ_SOCFPGA_MPU_WAKE (IRQ_SOCFPGA_GIC_START + 174) /* MPU wake */ > +#define IRQ_SOCFPGA_FPGA_MON (IRQ_SOCFPGA_GIC_START + 175) /* FPGA monitor */ > +#define IRQ_SOCFPGA_CPU0_CTI (IRQ_SOCFPGA_GIC_START + 176) /* Coresight CPU0 CTI */ > +#define IRQ_SOCFPGA_CPU1_CTI (IRQ_SOCFPGA_GIC_START + 177) /* Coresight CPU1 CTI */ > +#define IRQ_SOCFPGA_OCRAM_CECC (IRQ_SOCFPGA_GIC_START + 178) /* on-chip RAM ECC corrected */ > +#define IRQ_SOCFPGA_OCRAM_UECC (IRQ_SOCFPGA_GIC_START + 179) /* on-chip RAM ECC uncorrected */ > + > +/* Soft IRQ */ > +#define SOFTIRQ_SOCFPGA_DMADEV (IRQ_SOCFPGA_GIC_START + 180) > +#define SOFTIRQ_SOCFPGA_GPIO_0_0 (IRQ_SOCFPGA_GIC_START + 181) > +#define SOFTIRQ_SOCFPGA_GPIO_0_1 (IRQ_SOCFPGA_GIC_START + 182) > +#define SOFTIRQ_SOCFPGA_GPIO_0_2 (IRQ_SOCFPGA_GIC_START + 183) > +#define SOFTIRQ_SOCFPGA_GPIO_0_3 (IRQ_SOCFPGA_GIC_START + 184) > +#define SOFTIRQ_SOCFPGA_GPIO_0_4 (IRQ_SOCFPGA_GIC_START + 185) > +#define SOFTIRQ_SOCFPGA_GPIO_0_5 (IRQ_SOCFPGA_GIC_START + 186) > +#define SOFTIRQ_SOCFPGA_GPIO_0_6 (IRQ_SOCFPGA_GIC_START + 187) > +#define SOFTIRQ_SOCFPGA_GPIO_0_7 (IRQ_SOCFPGA_GIC_START + 188) > +#define SOFTIRQ_SOCFPGA_GPIO_0_8 (IRQ_SOCFPGA_GIC_START + 189) > +#define SOFTIRQ_SOCFPGA_GPIO_0_9 (IRQ_SOCFPGA_GIC_START + 190) > +#define SOFTIRQ_SOCFPGA_GPIO_0_10 (IRQ_SOCFPGA_GIC_START + 191) > +#define SOFTIRQ_SOCFPGA_GPIO_0_11 (IRQ_SOCFPGA_GIC_START + 192) > +#define SOFTIRQ_SOCFPGA_GPIO_0_12 (IRQ_SOCFPGA_GIC_START + 193) > +#define SOFTIRQ_SOCFPGA_GPIO_0_13 (IRQ_SOCFPGA_GIC_START + 194) > +#define SOFTIRQ_SOCFPGA_GPIO_0_14 (IRQ_SOCFPGA_GIC_START + 195) > +#define SOFTIRQ_SOCFPGA_GPIO_0_15 (IRQ_SOCFPGA_GIC_START + 196) > +#define SOFTIRQ_SOCFPGA_GPIO_0_16 (IRQ_SOCFPGA_GIC_START + 197) > +#define SOFTIRQ_SOCFPGA_GPIO_0_17 (IRQ_SOCFPGA_GIC_START + 198) > +#define SOFTIRQ_SOCFPGA_GPIO_0_18 (IRQ_SOCFPGA_GIC_START + 199) > +#define SOFTIRQ_SOCFPGA_GPIO_0_19 (IRQ_SOCFPGA_GIC_START + 200) > +#define SOFTIRQ_SOCFPGA_GPIO_0_20 (IRQ_SOCFPGA_GIC_START + 201) > +#define SOFTIRQ_SOCFPGA_GPIO_0_21 (IRQ_SOCFPGA_GIC_START + 202) > +#define SOFTIRQ_SOCFPGA_GPIO_0_22 (IRQ_SOCFPGA_GIC_START + 203) > +#define SOFTIRQ_SOCFPGA_GPIO_0_23 (IRQ_SOCFPGA_GIC_START + 204) > +#define SOFTIRQ_SOCFPGA_GPIO_0_24 (IRQ_SOCFPGA_GIC_START + 205) > +#define SOFTIRQ_SOCFPGA_GPIO_0_25 (IRQ_SOCFPGA_GIC_START + 206) > +#define SOFTIRQ_SOCFPGA_GPIO_0_26 (IRQ_SOCFPGA_GIC_START + 207) > +#define SOFTIRQ_SOCFPGA_GPIO_0_27 (IRQ_SOCFPGA_GIC_START + 208) > +#define SOFTIRQ_SOCFPGA_GPIO_0_28 (IRQ_SOCFPGA_GIC_START + 209) > +#define SOFTIRQ_SOCFPGA_GPIO_0_29 (IRQ_SOCFPGA_GIC_START + 210) > +#define SOFTIRQ_SOCFPGA_GPIO_1_0 (IRQ_SOCFPGA_GIC_START + 211) > +#define SOFTIRQ_SOCFPGA_GPIO_1_1 (IRQ_SOCFPGA_GIC_START + 212) > +#define SOFTIRQ_SOCFPGA_GPIO_1_2 (IRQ_SOCFPGA_GIC_START + 213) > +#define SOFTIRQ_SOCFPGA_GPIO_1_3 (IRQ_SOCFPGA_GIC_START + 214) > +#define SOFTIRQ_SOCFPGA_GPIO_1_4 (IRQ_SOCFPGA_GIC_START + 215) > +#define SOFTIRQ_SOCFPGA_GPIO_1_5 (IRQ_SOCFPGA_GIC_START + 216) > +#define SOFTIRQ_SOCFPGA_GPIO_1_6 (IRQ_SOCFPGA_GIC_START + 217) > +#define SOFTIRQ_SOCFPGA_GPIO_1_7 (IRQ_SOCFPGA_GIC_START + 218) > +#define SOFTIRQ_SOCFPGA_GPIO_1_8 (IRQ_SOCFPGA_GIC_START + 219) > +#define SOFTIRQ_SOCFPGA_GPIO_1_9 (IRQ_SOCFPGA_GIC_START + 220) > +#define SOFTIRQ_SOCFPGA_GPIO_1_10 (IRQ_SOCFPGA_GIC_START + 221) > +#define SOFTIRQ_SOCFPGA_GPIO_1_11 (IRQ_SOCFPGA_GIC_START + 222) > +#define SOFTIRQ_SOCFPGA_GPIO_1_12 (IRQ_SOCFPGA_GIC_START + 223) > +#define SOFTIRQ_SOCFPGA_GPIO_1_13 (IRQ_SOCFPGA_GIC_START + 224) > +#define SOFTIRQ_SOCFPGA_GPIO_1_14 (IRQ_SOCFPGA_GIC_START + 225) > +#define SOFTIRQ_SOCFPGA_GPIO_1_15 (IRQ_SOCFPGA_GIC_START + 226) > +#define SOFTIRQ_SOCFPGA_GPIO_1_16 (IRQ_SOCFPGA_GIC_START + 227) > +#define SOFTIRQ_SOCFPGA_GPIO_1_17 (IRQ_SOCFPGA_GIC_START + 228) > +#define SOFTIRQ_SOCFPGA_GPIO_1_18 (IRQ_SOCFPGA_GIC_START + 229) > +#define SOFTIRQ_SOCFPGA_GPIO_1_19 (IRQ_SOCFPGA_GIC_START + 230) > +#define SOFTIRQ_SOCFPGA_GPIO_1_20 (IRQ_SOCFPGA_GIC_START + 231) > +#define SOFTIRQ_SOCFPGA_GPIO_1_21 (IRQ_SOCFPGA_GIC_START + 232) > +#define SOFTIRQ_SOCFPGA_GPIO_1_22 (IRQ_SOCFPGA_GIC_START + 233) > +#define SOFTIRQ_SOCFPGA_GPIO_1_23 (IRQ_SOCFPGA_GIC_START + 234) > +#define SOFTIRQ_SOCFPGA_GPIO_1_24 (IRQ_SOCFPGA_GIC_START + 235) > +#define SOFTIRQ_SOCFPGA_GPIO_1_25 (IRQ_SOCFPGA_GIC_START + 236) > +#define SOFTIRQ_SOCFPGA_GPIO_1_26 (IRQ_SOCFPGA_GIC_START + 237) > +#define SOFTIRQ_SOCFPGA_GPIO_1_27 (IRQ_SOCFPGA_GIC_START + 238) > +#define SOFTIRQ_SOCFPGA_GPIO_1_28 (IRQ_SOCFPGA_GIC_START + 239) > +#define SOFTIRQ_SOCFPGA_GPIO_1_29 (IRQ_SOCFPGA_GIC_START + 240) > +#define SOFTIRQ_SOCFPGA_GPIO_2_0 (IRQ_SOCFPGA_GIC_START + 241) > +#define SOFTIRQ_SOCFPGA_GPIO_2_1 (IRQ_SOCFPGA_GIC_START + 242) > +#define SOFTIRQ_SOCFPGA_GPIO_2_2 (IRQ_SOCFPGA_GIC_START + 243) > +#define SOFTIRQ_SOCFPGA_GPIO_2_3 (IRQ_SOCFPGA_GIC_START + 244) > +#define SOFTIRQ_SOCFPGA_GPIO_2_4 (IRQ_SOCFPGA_GIC_START + 245) > +#define SOFTIRQ_SOCFPGA_GPIO_2_5 (IRQ_SOCFPGA_GIC_START + 246) > +#define SOFTIRQ_SOCFPGA_GPIO_2_6 (IRQ_SOCFPGA_GIC_START + 247) > +#define SOFTIRQ_SOCFPGA_GPIO_2_7 (IRQ_SOCFPGA_GIC_START + 248) > +#define SOFTIRQ_SOCFPGA_GPIO_2_8 (IRQ_SOCFPGA_GIC_START + 249) > +#define SOFTIRQ_SOCFPGA_GPIO_2_9 (IRQ_SOCFPGA_GIC_START + 250) > +#define SOFTIRQ_SOCFPGA_GPIO_2_10 (IRQ_SOCFPGA_GIC_START + 251) > +#define SOFTIRQ_SOCFPGA_GPIO_2_11 (IRQ_SOCFPGA_GIC_START + 252) > +#define SOFTIRQ_SOCFPGA_GPIO_2_12 (IRQ_SOCFPGA_GIC_START + 253) > +#define SOFTIRQ_SOCFPGA_GPIO_2_13 (IRQ_SOCFPGA_GIC_START + 254) > +#define SOFTIRQ_SOCFPGA_GPIO_2_14 (IRQ_SOCFPGA_GIC_START + 255) > +#define SOFTIRQ_SOCFPGA_GPIO_2_15 (IRQ_SOCFPGA_GIC_START + 256) > +#define SOFTIRQ_SOCFPGA_GPIO_2_16 (IRQ_SOCFPGA_GIC_START + 257) > +#define SOFTIRQ_SOCFPGA_GPIO_2_17 (IRQ_SOCFPGA_GIC_START + 258) > +#define SOFTIRQ_SOCFPGA_GPIO_2_18 (IRQ_SOCFPGA_GIC_START + 259) > +#define SOFTIRQ_SOCFPGA_GPIO_2_19 (IRQ_SOCFPGA_GIC_START + 260) > +#define SOFTIRQ_SOCFPGA_GPIO_2_20 (IRQ_SOCFPGA_GIC_START + 261) > +#define SOFTIRQ_SOCFPGA_GPIO_2_21 (IRQ_SOCFPGA_GIC_START + 262) > +#define SOFTIRQ_SOCFPGA_GPIO_2_22 (IRQ_SOCFPGA_GIC_START + 263) > +#define SOFTIRQ_SOCFPGA_GPIO_2_23 (IRQ_SOCFPGA_GIC_START + 264) > +#define SOFTIRQ_SOCFPGA_GPIO_2_24 (IRQ_SOCFPGA_GIC_START + 265) > +#define SOFTIRQ_SOCFPGA_GPIO_2_25 (IRQ_SOCFPGA_GIC_START + 266) > +#define SOFTIRQ_SOCFPGA_GPIO_2_26 (IRQ_SOCFPGA_GIC_START + 267) > +#define SOFTIRQ_SOCFPGA_GPIO_2_27 (IRQ_SOCFPGA_GIC_START + 268) > +#define SOFTIRQ_SOCFPGA_GPIO_2_28 (IRQ_SOCFPGA_GIC_START + 269) > +#define SOFTIRQ_SOCFPGA_GPIO_2_29 (IRQ_SOCFPGA_GIC_START + 270) Those huge lists of IRQs are no longer useful with the device tree, you can get rid of them. > +#define NR_IRQS 512 You should be looking at using SPARSE_IRQ to avoid having a maximum number of irqs. See for example mach-highbank/. > +++ b/arch/arm/mach-socfpga/include/mach/system.h > @@ -0,0 +1,31 @@ > +/* > + * Copyright (C) 2012 Altera Corporation > + * > + * Modified from arch/arm/mach-realview/include/mach/system.h > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > +*/ > +#ifndef __ASM_ARCH_SYSTEM_H > +#define __ASM_ARCH_SYSTEM_H > + > +static inline void arch_idle(void) > +{ > + /* > + * This should do all the clock switching > + * and wait for interrupt tricks > + */ > + cpu_do_idle(); > +} > + > +#endif This isn't used anywhere, and the system.h header is being removed from sub-architectures, if I understood correctly. > index 101b968..2f9a81e 100644 > --- a/arch/arm/mm/Kconfig > +++ b/arch/arm/mm/Kconfig > @@ -381,7 +381,7 @@ config CPU_V6K > > # ARMv7 > config CPU_V7 > - bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX > + bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_SOCFPGA > select CPU_32v6K > select CPU_32v7 > select CPU_ABRT_EV7 Apparently, your SoC is ARMv7 only at the moment, so you don't need to do this. Just keep the "select CPU_V7" in your ARCH_SOCFPGA option. Regards, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 14:20 ` Thomas Petazzoni @ 2012-06-27 18:05 ` Pavel Machek 2012-06-27 18:40 ` Thomas Petazzoni 2012-06-27 20:27 ` [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform Pavel Machek ` (3 subsequent siblings) 4 siblings, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-06-27 18:05 UTC (permalink / raw) To: linux-arm-kernel Hi! > Below a few comments from my modest experience on the mach-mvebu SoC > support. > > Le Wed, 27 Jun 2012 08:50:06 -0500, > <dinguyen@altera.com> a ?crit : > > > +config ARCH_SOCFPGA > > Is SOCFPGA a good name? It seems like a very generic name. Shouldn't it > be ARCH_ALTERA_SOCFPGA a better name? I suspect other vendors will > provide a SoC together with a FPGA. I guess for config option name, ALTERA_SOCFPGA is okay, but for directory name it would be a little bit long. Would that work? > > +choice > > + prompt "Altera SOCFPGA Platform" > > + default MACH_SOCFPGA_CYCLONE5 > > + depends on ARCH_SOCFPGA > > + help > > + Select SOCFPGA platform type > > + > > +config MACH_SOCFPGA_CYCLONE5 > > + bool "SOCFPGA Cyclone5 platform" > > + select HAVE_SMP > > + select PLAT_SOCFPGA_ETH > > + help > > + Include support for the Altera(R) Cyclone5 development platform. > > +endchoice > > Why do you need a "choice" here? The code should be able to support > building multiple platforms at once. Should be bool, agreed. > And even more: for a given SoC > variant, we now generally only want one config options, the board-level > details being abstracted out by the device tree. Will look into that later. > > index 0000000..7a1f3c0 > > --- /dev/null > > +++ b/arch/arm/mach-socfpga/Makefile.boot > > @@ -0,0 +1,3 @@ > > +zreladdr-y := 0x00008000 > > +params_phys-y := 0x00000100 > > +initrd_phys-y := 0x00800000 > > With the device tree, the params_phys-y and initrd_phys-y variables are > useless. Ok. > > +/* > > + * SOCFPGA interrupt sources > > + */ > > +#define IRQ_SOCFPGA_CPU0_PARITY (IRQ_SOCFPGA_GIC_START + 0) /* CPU0 parity */ > > +#define IRQ_SOCFPGA_CPU0_PARITY_BTAG (IRQ_SOCFPGA_GIC_START + 1) /* CPU0 parity BTAG */ ... > > +#define SOFTIRQ_SOCFPGA_GPIO_2_27 (IRQ_SOCFPGA_GIC_START + 268) > > +#define SOFTIRQ_SOCFPGA_GPIO_2_28 (IRQ_SOCFPGA_GIC_START + 269) > > +#define SOFTIRQ_SOCFPGA_GPIO_2_29 (IRQ_SOCFPGA_GIC_START + 270) > > Those huge lists of IRQs are no longer useful with the device tree, you > can get rid of them. Ok. arch/arm/mach-socfpga/socfpga_cyclone5.c:119: error: 'IRQ_SOCFPGA_L4_OSC1_TIMER0' undeclared (first use in this function) Looks like we'll meed a bit more of dt :-). > > +#define NR_IRQS 512 > > You should be looking at using SPARSE_IRQ to avoid having a maximum > number of irqs. See for example mach-highbank/. Is maximum number of interrupts a problem? 512 does not seem excessive. > > +static inline void arch_idle(void) > > +{ > > + /* > > + * This should do all the clock switching > > + * and wait for interrupt tricks > > + */ > > + cpu_do_idle(); > > +} > > + > > +#endif > > This isn't used anywhere, and the system.h header is being removed > from sub-architectures, if I understood correctly. Ok. > > index 101b968..2f9a81e 100644 > > --- a/arch/arm/mm/Kconfig > > +++ b/arch/arm/mm/Kconfig > > @@ -381,7 +381,7 @@ config CPU_V6K > > > > # ARMv7 > > config CPU_V7 > > - bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX > > + bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_SOCFPGA > > select CPU_32v6K > > select CPU_32v7 > > select CPU_ABRT_EV7 > > Apparently, your SoC is ARMv7 only at the moment, so you don't need to > do this. Just keep the "select CPU_V7" in your ARCH_SOCFPGA option. Will take a look. Thanks, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 18:05 ` Pavel Machek @ 2012-06-27 18:40 ` Thomas Petazzoni 2012-06-29 19:54 ` Dinh Nguyen 2012-06-30 21:04 ` Arnd Bergmann 0 siblings, 2 replies; 47+ messages in thread From: Thomas Petazzoni @ 2012-06-27 18:40 UTC (permalink / raw) To: linux-arm-kernel Le Wed, 27 Jun 2012 20:05:16 +0200, Pavel Machek <pavel@denx.de> a ?crit : > > Is SOCFPGA a good name? It seems like a very generic name. Shouldn't it > > be ARCH_ALTERA_SOCFPGA a better name? I suspect other vendors will > > provide a SoC together with a FPGA. > > I guess for config option name, ALTERA_SOCFPGA is okay, but for > directory name it would be a little bit long. Would that work? Hum, yes, maybe. Maybe just MACH_ALTERA, and mach-altera then? Hopefully others will have better ideas. > > And even more: for a given SoC > > variant, we now generally only want one config options, the board-level > > details being abstracted out by the device tree. > > Will look into that later. Ok. If you look at other platforms, they now typically have only one DT_MACHINE_START, and one configuration option associated to it, for each SoC variant. The different boards are only described using DT. > Ok. > > arch/arm/mach-socfpga/socfpga_cyclone5.c:119: error: > 'IRQ_SOCFPGA_L4_OSC1_TIMER0' undeclared (first use in this function) > > Looks like we'll meed a bit more of dt :-). Yes, you need more DT. You need a DT node for the timer, which will contain all the details like base I/O address and IRQ. > > > +#define NR_IRQS 512 > > > > You should be looking at using SPARSE_IRQ to avoid having a maximum > > number of irqs. See for example mach-highbank/. > > Is maximum number of interrupts a problem? 512 does not seem > excessive. Regardless of the value of NR_IRQS, there is apparently a trend to use SPARSE_IRQ anyway. However, I am not at the best place to explain why SPARSE_IRQ is now considered the right thing to use. Best regards, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 18:40 ` Thomas Petazzoni @ 2012-06-29 19:54 ` Dinh Nguyen 2012-06-29 22:18 ` Thomas Petazzoni 2012-06-30 21:04 ` Arnd Bergmann 1 sibling, 1 reply; 47+ messages in thread From: Dinh Nguyen @ 2012-06-29 19:54 UTC (permalink / raw) To: linux-arm-kernel On Wed, 2012-06-27 at 20:40 +0200, Thomas Petazzoni wrote: > Le Wed, 27 Jun 2012 20:05:16 +0200, > Pavel Machek <pavel@denx.de> a ?crit : > > > > Is SOCFPGA a good name? It seems like a very generic name. Shouldn't it > > > be ARCH_ALTERA_SOCFPGA a better name? I suspect other vendors will > > > provide a SoC together with a FPGA. > > > > I guess for config option name, ALTERA_SOCFPGA is okay, but for > > directory name it would be a little bit long. Would that work? > > Hum, yes, maybe. Maybe just MACH_ALTERA, and mach-altera then? > Hopefully others will have better ideas. First off, thanks for the thoughtful review, its very much appreciated. Unless its a really strong objection, I'd like to stick with mach-socfpga. This is a name that Altera has started to market this hw around and I would like to stick with it. > > > > And even more: for a given SoC > > > variant, we now generally only want one config options, the board-level > > > details being abstracted out by the device tree. > > > > Will look into that later. > > Ok. If you look at other platforms, they now typically have only one > DT_MACHINE_START, and one configuration option associated to it, for > each SoC variant. The different boards are only described using DT. > > > Ok. > > > > arch/arm/mach-socfpga/socfpga_cyclone5.c:119: error: > > 'IRQ_SOCFPGA_L4_OSC1_TIMER0' undeclared (first use in this function) > > > > Looks like we'll meed a bit more of dt :-). > > Yes, you need more DT. You need a DT node for the timer, which will > contain all the details like base I/O address and IRQ. > > > > > +#define NR_IRQS 512 > > > > > > You should be looking at using SPARSE_IRQ to avoid having a maximum > > > number of irqs. See for example mach-highbank/. > > > > Is maximum number of interrupts a problem? 512 does not seem > > excessive. > > Regardless of the value of NR_IRQS, there is apparently a trend to use > SPARSE_IRQ anyway. However, I am not at the best place to explain why > SPARSE_IRQ is now considered the right thing to use. > > Best regards, > > Thomas BR, Dinh ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-29 19:54 ` Dinh Nguyen @ 2012-06-29 22:18 ` Thomas Petazzoni 2012-07-04 16:11 ` Thomas Petazzoni 0 siblings, 1 reply; 47+ messages in thread From: Thomas Petazzoni @ 2012-06-29 22:18 UTC (permalink / raw) To: linux-arm-kernel Le Fri, 29 Jun 2012 14:54:47 -0500, Dinh Nguyen <dinguyen@altera.com> a ?crit : > > Hum, yes, maybe. Maybe just MACH_ALTERA, and mach-altera then? > > Hopefully others will have better ideas. > > First off, thanks for the thoughtful review, its very much appreciated. You're welcome. > Unless its a really strong objection, I'd like to stick with > mach-socfpga. This is a name that Altera has started to market this hwt > around and I would like to stick with it. I am definitely amongst the person who will take that decision, so I can't say what will happen with this choice, but feel free to push it forward, and you'll how it goes. I'll try to make a new review once a second version of your patch set will be posted. Best regards, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-29 22:18 ` Thomas Petazzoni @ 2012-07-04 16:11 ` Thomas Petazzoni 0 siblings, 0 replies; 47+ messages in thread From: Thomas Petazzoni @ 2012-07-04 16:11 UTC (permalink / raw) To: linux-arm-kernel Le Sat, 30 Jun 2012 00:18:20 +0200, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> a ?crit : > > Unless its a really strong objection, I'd like to stick with > > mach-socfpga. This is a name that Altera has started to market this hwt > > around and I would like to stick with it. > > I am definitely amongst the person who will take that decision, so I > can't say what will happen with this choice, but feel free to push it > forward, and you'll how it goes. Re-reading this, I did a mistake, I wanted to say: "I am definitely *not* amongst the person who will take that decision". I guess it was clear by the rest of the e-mail, but I just wanted to be sure. Regards, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 18:40 ` Thomas Petazzoni 2012-06-29 19:54 ` Dinh Nguyen @ 2012-06-30 21:04 ` Arnd Bergmann 2012-07-01 18:41 ` Pavel Machek 1 sibling, 1 reply; 47+ messages in thread From: Arnd Bergmann @ 2012-06-30 21:04 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 27 June 2012, Thomas Petazzoni wrote: > > > > +#define NR_IRQS 512 > > > > > > You should be looking at using SPARSE_IRQ to avoid having a maximum > > > number of irqs. See for example mach-highbank/. > > > > Is maximum number of interrupts a problem? 512 does not seem > > excessive. > > Regardless of the value of NR_IRQS, there is apparently a trend to use > SPARSE_IRQ anyway. However, I am not at the best place to explain why > SPARSE_IRQ is now considered the right thing to use. The main reason for me is to get rid of a hardcoded NR_IRQS constant, whihc is a blocker for multiplatform kernels. New platforms should do all they can to allow being built together with other platforms in the same kernel. While we're not there yet, doing sparse irq is an important step in the right direction and should not be hard to do for new code. Arnd ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-30 21:04 ` Arnd Bergmann @ 2012-07-01 18:41 ` Pavel Machek 2012-07-02 16:52 ` Arnd Bergmann 2012-10-17 18:16 ` [PATCH] Fix socfpga compilation with early_printk() enabled Pavel Machek 0 siblings, 2 replies; 47+ messages in thread From: Pavel Machek @ 2012-07-01 18:41 UTC (permalink / raw) To: linux-arm-kernel On Sat 2012-06-30 21:04:37, Arnd Bergmann wrote: > On Wednesday 27 June 2012, Thomas Petazzoni wrote: > > > > > +#define NR_IRQS 512 > > > > > > > > You should be looking at using SPARSE_IRQ to avoid having a maximum > > > > number of irqs. See for example mach-highbank/. > > > > > > Is maximum number of interrupts a problem? 512 does not seem > > > excessive. > > > > Regardless of the value of NR_IRQS, there is apparently a trend to use > > SPARSE_IRQ anyway. However, I am not at the best place to explain why > > SPARSE_IRQ is now considered the right thing to use. > > The main reason for me is to get rid of a hardcoded NR_IRQS constant, > whihc is a blocker for multiplatform kernels. New platforms should > do all they can to allow being built together with other platforms > in the same kernel. While we're not there yet, doing sparse irq > is an important step in the right direction and should not be hard > to do for new code. Something as easy as this? But it does not seem to boot here :-(. Pavel diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b1578e1..d203253 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -263,6 +263,7 @@ config ARCH_SOCFPGA select GPIO_PL061 if GPIOLIB select NEED_MACH_MEMORY_H select USE_OF + select SPARSE_IRQ help This enables support for Altera SOCFPGA Cyclone V platform diff --git a/arch/arm/mach-socfpga/include/mach/irqs.h b/arch/arm/mach-socfpga/include/mach/irqs.h index da50124..565ca59 100644 --- a/arch/arm/mach-socfpga/include/mach/irqs.h +++ b/arch/arm/mach-socfpga/include/mach/irqs.h @@ -27,8 +27,6 @@ #define IRQ_SOCFPGA_CLK_MAN (IRQ_SOCFPGA_GIC_START + 173) /* Clock manager */ -#define NR_IRQS 512 - #define MAX_GIC_NR 1 #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-socfpga/socfpga_cyclone5.c b/arch/arm/mach-socfpga/socfpga_cyclone5.c index f6498cc..674bac3 100644 --- a/arch/arm/mach-socfpga/socfpga_cyclone5.c +++ b/arch/arm/mach-socfpga/socfpga_cyclone5.c @@ -24,6 +24,7 @@ #include <mach/socfpga-timer.h> #include <mach/dw_apb_timer.h> #include <mach/socfpga_cyclone5.h> +#include <mach/irqs.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -133,6 +134,11 @@ static void socfpga_cyclone5_restart(char mode, const char *cmd) static void __init socfpga_cyclone5_init(void) { + int i; + for (i = 0; i < 512; i++) { + dynamic_irq_init(i); + } + #ifdef CONFIG_CACHE_L2X0 /* 8-way, 64K/way, evmon/parity/share */ l2x0_of_init(0x00760000, 0xfe000fff); -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-01 18:41 ` Pavel Machek @ 2012-07-02 16:52 ` Arnd Bergmann 2012-07-02 21:53 ` Pavel Machek 2012-10-17 18:16 ` [PATCH] Fix socfpga compilation with early_printk() enabled Pavel Machek 1 sibling, 1 reply; 47+ messages in thread From: Arnd Bergmann @ 2012-07-02 16:52 UTC (permalink / raw) To: linux-arm-kernel On Sunday 01 July 2012, Pavel Machek wrote: > @@ -133,6 +134,11 @@ static void socfpga_cyclone5_restart(char mode, const char *cmd) > > static void __init socfpga_cyclone5_init(void) > { > + int i; > + for (i = 0; i < 512; i++) { > + dynamic_irq_init(i); > + } > + > #ifdef CONFIG_CACHE_L2X0 > /* 8-way, 64K/way, evmon/parity/share */ > l2x0_of_init(0x00760000, 0xfe000fff); > This looks wrong, I think what you should do instead is to call irq_domain_add_legacy() for each controller you register as the first step, and then try to convert the controllers to use irq_domain_add_linear() as the second step. See also Documentation/IRQ-domain.txt. Arnd ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-02 16:52 ` Arnd Bergmann @ 2012-07-02 21:53 ` Pavel Machek 0 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-07-02 21:53 UTC (permalink / raw) To: linux-arm-kernel Hi! > > static void __init socfpga_cyclone5_init(void) > > { > > + int i; > > + for (i = 0; i < 512; i++) { > > + dynamic_irq_init(i); > > + } > > + > > #ifdef CONFIG_CACHE_L2X0 > > /* 8-way, 64K/way, evmon/parity/share */ > > l2x0_of_init(0x00760000, 0xfe000fff); > > > > This looks wrong, I think what you should do instead is > to call irq_domain_add_legacy() for each controller you > register as the first step, and then try to convert the > controllers to use irq_domain_add_linear() as the second > step. See also Documentation/IRQ-domain.txt. Stupid me, GIC already has irq_domain support, so the switch to sparse_irq is as simple as: Pavel Signed-off-by: Pavel Machek <pavel@denx.de> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b1578e1..d203253 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -263,6 +263,7 @@ config ARCH_SOCFPGA select GPIO_PL061 if GPIOLIB select NEED_MACH_MEMORY_H select USE_OF + select SPARSE_IRQ help This enables support for Altera SOCFPGA Cyclone V platform diff --git a/arch/arm/mach-socfpga/include/mach/irqs.h b/arch/arm/mach-socfpga/include/mach/irqs.h index da50124..565ca59 100644 --- a/arch/arm/mach-socfpga/include/mach/irqs.h +++ b/arch/arm/mach-socfpga/include/mach/irqs.h @@ -27,8 +27,6 @@ #define IRQ_SOCFPGA_CLK_MAN (IRQ_SOCFPGA_GIC_START + 173) /* Clock manager */ -#define NR_IRQS 512 - #define MAX_GIC_NR 1 #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-socfpga/socfpga_cyclone5.c b/arch/arm/mach-socfpga/socfpga_cyclone5.c index f6498cc..d8cd89b 100644 --- a/arch/arm/mach-socfpga/socfpga_cyclone5.c +++ b/arch/arm/mach-socfpga/socfpga_cyclone5.c @@ -24,6 +24,7 @@ #include <mach/socfpga-timer.h> #include <mach/dw_apb_timer.h> #include <mach/socfpga_cyclone5.h> +#include <mach/irqs.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] Fix socfpga compilation with early_printk() enabled 2012-07-01 18:41 ` Pavel Machek 2012-07-02 16:52 ` Arnd Bergmann @ 2012-10-17 18:16 ` Pavel Machek 2012-10-25 14:58 ` Arnd Bergmann 1 sibling, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-10-17 18:16 UTC (permalink / raw) To: linux-arm-kernel Hi! This fixes early_printk() compilation for socfpga. (senduart/busyuart/waituart were missing). It does that by making Picochip code generic. Signed-off-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Jamie Iles <jamie@jamieiles.com diff --git a/arch/arm/include/debug/8250_32.S b/arch/arm/include/debug/8250_32.S new file mode 100644 index 0000000..8db01ee --- /dev/null +++ b/arch/arm/include/debug/8250_32.S @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2011 Picochip Ltd., Jamie Iles + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit + * accesses to the 8250. + */ + +#include <linux/serial_reg.h> + + .macro senduart,rd,rx + str \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + /* The UART's don't have any flow control IO's wired up. */ + .macro waituart,rd,rx + .endm diff --git a/arch/arm/include/debug/picoxcell.S b/arch/arm/include/debug/picoxcell.S index 7419deb..bc1f07c 100644 --- a/arch/arm/include/debug/picoxcell.S +++ b/arch/arm/include/debug/picoxcell.S @@ -5,10 +5,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit - * accesses to the 8250. */ -#include <linux/serial_reg.h> #define UART_SHIFT 2 #define PICOXCELL_UART1_BASE 0x80230000 @@ -19,17 +16,4 @@ ldr \rp, =PICOXCELL_UART1_BASE .endm - .macro senduart,rd,rx - str \rd, [\rx, #UART_TX << UART_SHIFT] - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE - bne 1002b - .endm - - /* The UART's don't have any flow control IO's wired up. */ - .macro waituart,rd,rx - .endm +#include "8250_32.S" diff --git a/arch/arm/include/debug/socfpga.S b/arch/arm/include/debug/socfpga.S index d6f26d2..966b2f9 100644 --- a/arch/arm/include/debug/socfpga.S +++ b/arch/arm/include/debug/socfpga.S @@ -7,6 +7,9 @@ * published by the Free Software Foundation. */ +#define UART_SHIFT 2 +#define DEBUG_LL_UART_OFFSET 0x00002000 + .macro addruart, rp, rv, tmp mov \rp, #DEBUG_LL_UART_OFFSET orr \rp, \rp, #0x00c00000 @@ -14,3 +17,5 @@ orr \rp, \rp, #0xff000000 @ physical base .endm +#include "8250_32.S" + -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] Fix socfpga compilation with early_printk() enabled 2012-10-17 18:16 ` [PATCH] Fix socfpga compilation with early_printk() enabled Pavel Machek @ 2012-10-25 14:58 ` Arnd Bergmann 2012-10-27 11:56 ` Pavel Machek 0 siblings, 1 reply; 47+ messages in thread From: Arnd Bergmann @ 2012-10-25 14:58 UTC (permalink / raw) To: linux-arm-kernel On Wednesday 17 October 2012, Pavel Machek wrote: > Hi! > > This fixes early_printk() compilation for > socfpga. (senduart/busyuart/waituart were missing). It does that by > making Picochip code generic. > > Signed-off-by: Pavel Machek <pavel@denx.de> > Acked-by: Dinh Nguyen <dinguyen@altera.com> > Acked-by: Jamie Iles <jamie@jamieiles.com Applied to fixes branch of arm-soc, but please be more explicit about what you want to happen with patches in the future. Ideally we would get pull requests for patches on each platform from only one person, so please coordinate with Dinh Nguyen who that should be. Some minor things: * If you include something in the email that should not be part of the git changelog (e.g. "Hi!"), then please put it below the "---" line under the Signed-off list. * you are missing a '>' after Jamies email address * When you submit a patch for inclusion, please always take both Olof and me on Cc on the email, since we are doing this work together and take turns, so you might not always know which one will take the patch. We have an alias "arm at kernel.org" that you can also use. I fixed all of the above now and applied the patch. Arnd ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] Fix socfpga compilation with early_printk() enabled 2012-10-25 14:58 ` Arnd Bergmann @ 2012-10-27 11:56 ` Pavel Machek 2012-10-27 15:39 ` Arnd Bergmann 0 siblings, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-10-27 11:56 UTC (permalink / raw) To: linux-arm-kernel Hi! > > This fixes early_printk() compilation for > > socfpga. (senduart/busyuart/waituart were missing). It does that by > > making Picochip code generic. > > > > Signed-off-by: Pavel Machek <pavel@denx.de> > > Acked-by: Dinh Nguyen <dinguyen@altera.com> > > Acked-by: Jamie Iles <jamie@jamieiles.com > > Applied to fixes branch of arm-soc, but please be more explicit about > what you want to happen with patches in the future. Ideally we would > get pull requests for patches on each platform from only one person, > so please coordinate with Dinh Nguyen who that should be. Dinh is the maintainer, so if we can only send patches from one person, it needs to be him. If you'd be willing to take patches from second person, that would help us... if not, of course I can send all the patches through Dinh. > Some minor things: > > * If you include something in the email that should not be part of > the git changelog (e.g. "Hi!"), then please put it below the "---" > line under the Signed-off list. Ok. > * you are missing a '>' after Jamies email address Sorry. > * When you submit a patch for inclusion, please always take both > Olof and me on Cc on the email, since we are doing this work together > and take turns, so you might not always know which one will take > the patch. We have an alias "arm at kernel.org" that you can also > use. Olof Johansson <olof@lixom.net>? Can do. But... perhaps you should add an entry into MAINTAINERS file explaining all this? arm at kernel.org is not mentioned there, Olof is not mentioned as maintaining arm. (And yes, I did check it before original patch submission). Thanks, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] Fix socfpga compilation with early_printk() enabled 2012-10-27 11:56 ` Pavel Machek @ 2012-10-27 15:39 ` Arnd Bergmann 2012-10-28 23:01 ` arm-soc tree was " Pavel Machek 2012-10-29 0:27 ` [PATCH for soc] socfpga: map uart into virtual address space so that early_printk() works Pavel Machek 0 siblings, 2 replies; 47+ messages in thread From: Arnd Bergmann @ 2012-10-27 15:39 UTC (permalink / raw) To: linux-arm-kernel On Saturday 27 October 2012, Pavel Machek wrote: > > > This fixes early_printk() compilation for > > > socfpga. (senduart/busyuart/waituart were missing). It does that by > > > making Picochip code generic. > > > > > > Signed-off-by: Pavel Machek <pavel@denx.de> > > > Acked-by: Dinh Nguyen <dinguyen@altera.com> > > > Acked-by: Jamie Iles <jamie@jamieiles.com > > > > Applied to fixes branch of arm-soc, but please be more explicit about > > what you want to happen with patches in the future. Ideally we would > > get pull requests for patches on each platform from only one person, > > so please coordinate with Dinh Nguyen who that should be. > > Dinh is the maintainer, so if we can only send patches from one > person, it needs to be him. If you'd be willing to take patches from > second person, that would help us... if not, of course I can send all > the patches through Dinh. You can both send patches, we just need to know what to expect. For most platforms it works best if one person collects the patches from everyone. If you are sending patches with both Dinh and us as the recipients, just make it clear who you want to pick up the patch. > > * When you submit a patch for inclusion, please always take both > > Olof and me on Cc on the email, since we are doing this work together > > and take turns, so you might not always know which one will take > > the patch. We have an alias "arm at kernel.org" that you can also > > use. > > Olof Johansson <olof@lixom.net>? Can do. > > But... perhaps you should add an entry into MAINTAINERS file > explaining all this? arm at kernel.org is not mentioned there, Olof is > not mentioned as maintaining arm. (And yes, I did check it before > original patch submission). We intentionally didn't put our names into the maintainers file because that would mean getting Cc'd on every patch that should actually go to one of the sub-maintainers instead. We are adding an entry pointing to the arm-soc tree now though, just without the arm at kernel.org entry. Arnd ^ permalink raw reply [flat|nested] 47+ messages in thread
* arm-soc tree was Re: [PATCH] Fix socfpga compilation with early_printk() enabled 2012-10-27 15:39 ` Arnd Bergmann @ 2012-10-28 23:01 ` Pavel Machek 2012-10-28 23:13 ` Pavel Machek 2012-10-29 4:45 ` Arnd Bergmann 2012-10-29 0:27 ` [PATCH for soc] socfpga: map uart into virtual address space so that early_printk() works Pavel Machek 1 sibling, 2 replies; 47+ messages in thread From: Pavel Machek @ 2012-10-28 23:01 UTC (permalink / raw) To: linux-arm-kernel Hi! > > > > This fixes early_printk() compilation for > > > > socfpga. (senduart/busyuart/waituart were missing). It does that by > > > > making Picochip code generic. > > > > > > > > Signed-off-by: Pavel Machek <pavel@denx.de> > > > > Acked-by: Dinh Nguyen <dinguyen@altera.com> > > > > Acked-by: Jamie Iles <jamie@jamieiles.com > > > > > > Applied to fixes branch of arm-soc, but please be more explicit about > > > what you want to happen with patches in the future. Ideally we would > > > get pull requests for patches on each platform from only one person, > > > so please coordinate with Dinh Nguyen who that should be. > > > > Dinh is the maintainer, so if we can only send patches from one > > person, it needs to be him. If you'd be willing to take patches from > > second person, that would help us... if not, of course I can send all > > the patches through Dinh. > > You can both send patches, we just need to know what to expect. For most > platforms it works best if one person collects the patches from > everyone. > If you are sending patches with both Dinh and us as the recipients, > just make it clear who you want to pick up the patch. Thanks. Would "[PATCH for soc]" in subject line be suitable markup? BTW current for-next soc tree does not compile for me, with arch/arm/mach-vexpress/built-in.o: In function `v2m_timer_init': hotplug.c:(.init.text+0xd0): undefined reference to `vexpress_clk_init' arch/arm/mach-vexpress/built-in.o: In function `v2m_dt_timer_init': hotplug.c:(.init.text+0x100): undefined reference to `vexpress_clk_of_init' make: *** [vmlinux] Error 1 config attached. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -------------- next part -------------- A non-text attachment was scrubbed... Name: config.bug.gz Type: application/octet-stream Size: 11441 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121029/536fdb2a/attachment-0001.obj> ^ permalink raw reply [flat|nested] 47+ messages in thread
* arm-soc tree was Re: [PATCH] Fix socfpga compilation with early_printk() enabled 2012-10-28 23:01 ` arm-soc tree was " Pavel Machek @ 2012-10-28 23:13 ` Pavel Machek 2012-10-29 4:41 ` Arnd Bergmann 2012-10-29 4:45 ` Arnd Bergmann 1 sibling, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-10-28 23:13 UTC (permalink / raw) To: linux-arm-kernel Hi! > > > > > This fixes early_printk() compilation for > > > > > socfpga. (senduart/busyuart/waituart were missing). It does that by > > > > > making Picochip code generic. > > > > > > > > > > Signed-off-by: Pavel Machek <pavel@denx.de> > > > > > Acked-by: Dinh Nguyen <dinguyen@altera.com> > > > > > Acked-by: Jamie Iles <jamie@jamieiles.com > > > > > > > > Applied to fixes branch of arm-soc, but please be more explicit about > > > > what you want to happen with patches in the future. Ideally we would > > > > get pull requests for patches on each platform from only one person, > > > > so please coordinate with Dinh Nguyen who that should be. > > > > > > Dinh is the maintainer, so if we can only send patches from one > > > person, it needs to be him. If you'd be willing to take patches from > > > second person, that would help us... if not, of course I can send all > > > the patches through Dinh. > > > > You can both send patches, we just need to know what to expect. For most > > platforms it works best if one person collects the patches from > > everyone. > > > If you are sending patches with both Dinh and us as the recipients, > > just make it clear who you want to pick up the patch. > > Thanks. Would "[PATCH for soc]" in subject line be suitable markup? > > BTW current for-next soc tree does not compile for me, with > > arch/arm/mach-vexpress/built-in.o: In function `v2m_timer_init': > hotplug.c:(.init.text+0xd0): undefined reference to > `vexpress_clk_init' > arch/arm/mach-vexpress/built-in.o: In function `v2m_dt_timer_init': > hotplug.c:(.init.text+0x100): undefined reference to > `vexpress_clk_of_init' > make: *** [vmlinux] Error 1 Aha, grep shows: arch/arm/mach-vexpress/v2m.c: vexpress_clk_init(ioremap(V2M_SYSCTL, SZ_4K)); include/linux/vexpress.h:void vexpress_clk_init(void __iomem *sp810_base); ...seems vexpress_clk_init is not there, yet... And what is more serious: pavel at amd:~/mainline-altera/linux$ grep mach-vexpress MAINTAINERS pavel at amd:~/mainline-altera/linux$ vexpress_clk_of_init(); has same problem. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* arm-soc tree was Re: [PATCH] Fix socfpga compilation with early_printk() enabled 2012-10-28 23:13 ` Pavel Machek @ 2012-10-29 4:41 ` Arnd Bergmann 2012-10-30 16:03 ` Pawel Moll 0 siblings, 1 reply; 47+ messages in thread From: Arnd Bergmann @ 2012-10-29 4:41 UTC (permalink / raw) To: linux-arm-kernel On Sunday 28 October 2012, Pavel Machek wrote: > arch/arm/mach-vexpress/v2m.c: vexpress_clk_init(ioremap(V2M_SYSCTL, SZ_4K)); > include/linux/vexpress.h:void vexpress_clk_init(void __iomem *sp810_base); > > ...seems vexpress_clk_init is not there, yet... And what is more > serious: > > pavel at amd:~/mainline-altera/linux$ grep mach-vexpress MAINTAINERS > pavel at amd:~/mainline-altera/linux$ > > vexpress_clk_of_init(); has same problem. I've already reported both to Pawel Moll, and he already came back with a new series, but we're still trying to work out the dependencies. Arnd ^ permalink raw reply [flat|nested] 47+ messages in thread
* arm-soc tree was Re: [PATCH] Fix socfpga compilation with early_printk() enabled 2012-10-29 4:41 ` Arnd Bergmann @ 2012-10-30 16:03 ` Pawel Moll 0 siblings, 0 replies; 47+ messages in thread From: Pawel Moll @ 2012-10-30 16:03 UTC (permalink / raw) To: linux-arm-kernel On Mon, 2012-10-29 at 04:41 +0000, Arnd Bergmann wrote: > On Sunday 28 October 2012, Pavel Machek wrote: > > arch/arm/mach-vexpress/v2m.c: vexpress_clk_init(ioremap(V2M_SYSCTL, SZ_4K)); > > include/linux/vexpress.h:void vexpress_clk_init(void __iomem *sp810_base); > > > > ...seems vexpress_clk_init is not there, yet... And what is more > > serious: > > > > pavel at amd:~/mainline-altera/linux$ grep mach-vexpress MAINTAINERS > > pavel at amd:~/mainline-altera/linux$ > > > > vexpress_clk_of_init(); has same problem. > > I've already reported both to Pawel Moll, and he already came back with > a new series, but we're still trying to work out the dependencies. Yes, it's been a glitch in -next between arm-soc and clk, but it should be fine now (as of next-20121030). Sorry about the hassle Pawel ^ permalink raw reply [flat|nested] 47+ messages in thread
* arm-soc tree was Re: [PATCH] Fix socfpga compilation with early_printk() enabled 2012-10-28 23:01 ` arm-soc tree was " Pavel Machek 2012-10-28 23:13 ` Pavel Machek @ 2012-10-29 4:45 ` Arnd Bergmann 1 sibling, 0 replies; 47+ messages in thread From: Arnd Bergmann @ 2012-10-29 4:45 UTC (permalink / raw) To: linux-arm-kernel On Sunday 28 October 2012, Pavel Machek wrote: > > You can both send patches, we just need to know what to expect. For most > > platforms it works best if one person collects the patches from > > everyone. > > > If you are sending patches with both Dinh and us as the recipients, > > just make it clear who you want to pick up the patch. > > Thanks. Would "[PATCH for soc]" in subject line be suitable markup? > That works for me, but if you are planning to send a lot of patches, please consider grouping them together instead so you can send a git pull request instead, or alternatively use a patch series with an introductory mail to describe the series. Arnd ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH for soc] socfpga: map uart into virtual address space so that early_printk() works 2012-10-27 15:39 ` Arnd Bergmann 2012-10-28 23:01 ` arm-soc tree was " Pavel Machek @ 2012-10-29 0:27 ` Pavel Machek 2012-11-03 11:26 ` Pavel Machek 1 sibling, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-10-29 0:27 UTC (permalink / raw) To: linux-arm-kernel Early printk code needs UART to be mapped early during boot. early_printk() is left there during the start-up; it is useful as our emulators are fairly slow. Signed-off-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index ab81ea9..49fb62b 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -37,6 +37,15 @@ static struct map_desc scu_io_desc __initdata = { .type = MT_DEVICE, }; + + +static struct map_desc uart_io_desc __initdata = { + .virtual = 0xfec02000, + .pfn = __phys_to_pfn(0xffc02000), + .length = SZ_8K, + .type = MT_DEVICE, +}; + static void __init socfpga_scu_map_io(void) { unsigned long base; @@ -51,6 +60,8 @@ static void __init socfpga_scu_map_io(void) static void __init socfpga_map_io(void) { socfpga_scu_map_io(); + iotable_init(&uart_io_desc, 1); + early_printk("Early printk initialized\n"); } const static struct of_device_id irq_match[] = { -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH for soc] socfpga: map uart into virtual address space so that early_printk() works 2012-10-29 0:27 ` [PATCH for soc] socfpga: map uart into virtual address space so that early_printk() works Pavel Machek @ 2012-11-03 11:26 ` Pavel Machek 2012-11-05 17:18 ` Olof Johansson 0 siblings, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-11-03 11:26 UTC (permalink / raw) To: linux-arm-kernel Hi! > Early printk code needs UART to be mapped early during > boot. early_printk() is left there during the start-up; it is useful > as our emulators are fairly slow. > > Signed-off-by: Pavel Machek <pavel@denx.de> > Acked-by: Dinh Nguyen <dinguyen@altera.com> Could we get this one applied? No comments for quite a while... and it is needed for machine not to crash with early_printk used... Pavel > diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c > index ab81ea9..49fb62b 100644 > --- a/arch/arm/mach-socfpga/socfpga.c > +++ b/arch/arm/mach-socfpga/socfpga.c > @@ -37,6 +37,15 @@ static struct map_desc scu_io_desc __initdata = { > .type = MT_DEVICE, > }; > > + > + > +static struct map_desc uart_io_desc __initdata = { > + .virtual = 0xfec02000, > + .pfn = __phys_to_pfn(0xffc02000), > + .length = SZ_8K, > + .type = MT_DEVICE, > +}; > + > static void __init socfpga_scu_map_io(void) > { > unsigned long base; > @@ -51,6 +60,8 @@ static void __init socfpga_scu_map_io(void) > static void __init socfpga_map_io(void) > { > socfpga_scu_map_io(); > + iotable_init(&uart_io_desc, 1); > + early_printk("Early printk initialized\n"); > } > > const static struct of_device_id irq_match[] = { > -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH for soc] socfpga: map uart into virtual address space so that early_printk() works 2012-11-03 11:26 ` Pavel Machek @ 2012-11-05 17:18 ` Olof Johansson 0 siblings, 0 replies; 47+ messages in thread From: Olof Johansson @ 2012-11-05 17:18 UTC (permalink / raw) To: linux-arm-kernel On Sat, Nov 03, 2012 at 12:26:14PM +0100, Pavel Machek wrote: > Hi! > > > Early printk code needs UART to be mapped early during > > boot. early_printk() is left there during the start-up; it is useful > > as our emulators are fairly slow. > > > > Signed-off-by: Pavel Machek <pavel@denx.de> > > Acked-by: Dinh Nguyen <dinguyen@altera.com> > > Could we get this one applied? No comments for quite a while... and it > is needed for machine not to crash with early_printk used... > Pavel Sorry, we've been delayed on applying patches due to Linaro Connect and travel. I've applied this now with a minor edit to remove the extra added lines before the struct. Regards, -Olof ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 14:20 ` Thomas Petazzoni 2012-06-27 18:05 ` Pavel Machek @ 2012-06-27 20:27 ` Pavel Machek 2012-06-30 18:57 ` Pavel Machek ` (2 subsequent siblings) 4 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-06-27 20:27 UTC (permalink / raw) To: linux-arm-kernel Hi! And for the reference, here are simple changes in diff format. It still boots ;-). Signed-off-by: Pavel Machek <pavel@denx.de> Pavel diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 3fbbd0a..37863d1 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,9 +1,3 @@ -choice - prompt "Altera SOCFPGA Platform" - default MACH_SOCFPGA_CYCLONE5 - depends on ARCH_SOCFPGA - help - Select SOCFPGA platform type config MACH_SOCFPGA_CYCLONE5 bool "SOCFPGA Cyclone5 platform" @@ -11,7 +5,6 @@ config MACH_SOCFPGA_CYCLONE5 select PLAT_SOCFPGA_ETH help Include support for the Altera(R) Cyclone5 development platform. -endchoice config SOCFPGA_TIMER_HZ int "Kernel internal timer frequency " diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot index 7a1f3c0..dae9661 100644 --- a/arch/arm/mach-socfpga/Makefile.boot +++ b/arch/arm/mach-socfpga/Makefile.boot @@ -1,3 +1 @@ zreladdr-y := 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-socfpga/include/mach/irqs.h b/arch/arm/mach-socfpga/include/mach/irqs.h index 65db73a..da50124 100644 --- a/arch/arm/mach-socfpga/include/mach/irqs.h +++ b/arch/arm/mach-socfpga/include/mach/irqs.h @@ -20,283 +20,12 @@ #define IRQ_SOCFPGA_GIC_START 32 #define IRQ_LOCALWDOG 30 +#define IRQ_SOCFPGA_L4_OSC1_TIMER0 (IRQ_SOCFPGA_GIC_START + 169) /* L4 OSC1 timer 0 */ +#define IRQ_SOCFPGA_L4_OSC1_TIMER1 (IRQ_SOCFPGA_GIC_START + 170) /* L4 OSC1 timer 1 */ +#define IRQ_SOCFPGA_WD0 (IRQ_SOCFPGA_GIC_START + 171) /* Watchdog timer 0 */ +#define IRQ_SOCFPGA_WD1 (IRQ_SOCFPGA_GIC_START + 172) /* Watchdog timer 1 */ +#define IRQ_SOCFPGA_CLK_MAN (IRQ_SOCFPGA_GIC_START + 173) /* Clock manager */ -/* - * SOCFPGA interrupt sources - */ -#define IRQ_SOCFPGA_CPU0_PARITY (IRQ_SOCFPGA_GIC_START + 0) /* CPU0 parity */ -#define IRQ_SOCFPGA_CPU0_PARITY_BTAG (IRQ_SOCFPGA_GIC_START + 1) /* CPU0 parity BTAG */ -#define IRQ_SOCFPGA_CPU0_PARITY_GHB (IRQ_SOCFPGA_GIC_START + 2) /* CPU0 parity GHB */ -#define IRQ_SOCFPGA_CPU0_PARITY_ITAG (IRQ_SOCFPGA_GIC_START + 3) /* CPU0 parity ITAG */ -#define IRQ_SOCFPGA_CPU0_PARITY_IDATA (IRQ_SOCFPGA_GIC_START + 4) /* CPU0 parity IDATA */ -#define IRQ_SOCFPGA_CPU0_PARITY_TLB (IRQ_SOCFPGA_GIC_START + 5) /* CPU0 parity TLB */ -#define IRQ_SOCFPGA_CPU0_PARITY_DOUTER (IRQ_SOCFPGA_GIC_START + 6) /* CPU0 parity DOUTER */ -#define IRQ_SOCFPGA_CPU0_PARITY_DTAG (IRQ_SOCFPGA_GIC_START + 7) /* CPU0 parity DTAG */ -#define IRQ_SOCFPGA_CPU0_PARITY_DDATA (IRQ_SOCFPGA_GIC_START + 8) /* CPU0 parity DDATA */ -#define IRQ_SOCFPGA_CPU0_DEFLAGS0 (IRQ_SOCFPGA_GIC_START + 9) /* CPU0 deflasg 0 */ -#define IRQ_SOCFPGA_CPU0_DEFLAGS1 (IRQ_SOCFPGA_GIC_START + 10) /* CPU0 deflags 1 */ -#define IRQ_SOCFPGA_CPU0_DEFLAGS2 (IRQ_SOCFPGA_GIC_START + 11) /* CPU0 deflags 2 */ -#define IRQ_SOCFPGA_CPU0_DEFLAGS3 (IRQ_SOCFPGA_GIC_START + 12) /* CPU0 deflags 3 */ -#define IRQ_SOCFPGA_CPU0_DEFLAGS4 (IRQ_SOCFPGA_GIC_START + 13) /* CPU0 deflags 4 */ -#define IRQ_SOCFPGA_CPU0_DEFLAGS5 (IRQ_SOCFPGA_GIC_START + 14) /* CPU0 deflags 5 */ -#define IRQ_SOCFPGA_CPU0_DEFLAGS6 (IRQ_SOCFPGA_GIC_START + 15) /* CPU0 deflags 6 */ -#define IRQ_SOCFPGA_CPU1_PARITY (IRQ_SOCFPGA_GIC_START + 16) /* CPU1 parity */ -#define IRQ_SOCFPGA_CPU1_PARITY_BTAG (IRQ_SOCFPGA_GIC_START + 17) /* CPU1 parity BTAG */ -#define IRQ_SOCFPGA_CPU1_PARITY_GHB (IRQ_SOCFPGA_GIC_START + 18) /* CPU1 parity GHB */ -#define IRQ_SOCFPGA_CPU1_PARITY_ITAG (IRQ_SOCFPGA_GIC_START + 19) /* CPU1 parity ITAG */ -#define IRQ_SOCFPGA_CPU1_PARITY_IDATA (IRQ_SOCFPGA_GIC_START + 20) /* CPU1 parity IDATA */ -#define IRQ_SOCFPGA_CPU1_PARITY_TLB (IRQ_SOCFPGA_GIC_START + 21) /* CPU1 parity TLB */ -#define IRQ_SOCFPGA_CPU1_PARITY_DOUTER (IRQ_SOCFPGA_GIC_START + 22) /* CPU1 parity DOUTER */ -#define IRQ_SOCFPGA_CPU1_PARITY_DTAG (IRQ_SOCFPGA_GIC_START + 23) /* CPU1 parity DTAG */ -#define IRQ_SOCFPGA_CPU1_PARITY_DDATA (IRQ_SOCFPGA_GIC_START + 24) /* CPU1 parity DDATA */ -#define IRQ_SOCFPGA_CPU1_DEFLAGS0 (IRQ_SOCFPGA_GIC_START + 25) /* CPU1 deflags 0 */ -#define IRQ_SOCFPGA_CPU1_DEFLAGS1 (IRQ_SOCFPGA_GIC_START + 26) /* CPU1 deflags 1 */ -#define IRQ_SOCFPGA_CPU1_DEFLAGS2 (IRQ_SOCFPGA_GIC_START + 27) /* CPU1 deflags 2 */ -#define IRQ_SOCFPGA_CPU1_DEFLAGS3 (IRQ_SOCFPGA_GIC_START + 28) /* CPU1 deflags 3 */ -#define IRQ_SOCFPGA_CPU1_DEFLAGS4 (IRQ_SOCFPGA_GIC_START + 29) /* CPU1 deflags 4 */ -#define IRQ_SOCFPGA_CPU1_DEFLAGS5 (IRQ_SOCFPGA_GIC_START + 30) /* CPU1 deflags 5 */ -#define IRQ_SOCFPGA_CPU1_DEFLAGS6 (IRQ_SOCFPGA_GIC_START + 31) /* CPU1 deflags 6 */ -#define IRQ_SOCFPGA_SCU0_PARITY (IRQ_SOCFPGA_GIC_START + 32) /* SCU0 parity */ -#define IRQ_SOCFPGA_SCU1_PARITY (IRQ_SOCFPGA_GIC_START + 33) /* SCU1 parity */ -#define IRQ_SOCFPGA_SCU_EV_ABORT (IRQ_SOCFPGA_GIC_START + 34) /* SCU EV abort */ -#define IRQ_SOCFPGA_L2_ECC_WRITE (IRQ_SOCFPGA_GIC_START + 35) /* L2 ECC write */ -#define IRQ_SOCFPGA_L2_ECC_CERR (IRQ_SOCFPGA_GIC_START + 36) /* L2 ECC error corrected */ -#define IRQ_SOCFPGA_L2_ECC_UERR (IRQ_SOCFPGA_GIC_START + 37) /* L2 ECC error uncorrected */ -#define IRQ_SOCFPGA_L2 (IRQ_SOCFPGA_GIC_START + 38) /* L2 combined interrupts */ -#define IRQ_SOCFPGA_DDR_ECC_ERR (IRQ_SOCFPGA_GIC_START + 39) /* DDR ECC error */ -#define IRQ_SOCFPGA_F2S_FPGA0 (IRQ_SOCFPGA_GIC_START + 40) /* FPGA IRQ 0 */ -#define IRQ_SOCFPGA_F2S_FPGA1 (IRQ_SOCFPGA_GIC_START + 41) /* FPGA IRQ 1 */ -#define IRQ_SOCFPGA_F2S_FPGA2 (IRQ_SOCFPGA_GIC_START + 42) /* FPGA IRQ 2 */ -#define IRQ_SOCFPGA_F2S_FPGA3 (IRQ_SOCFPGA_GIC_START + 43) /* FPGA IRQ 3 */ -#define IRQ_SOCFPGA_F2S_FPGA4 (IRQ_SOCFPGA_GIC_START + 44) /* FPGA IRQ 4 */ -#define IRQ_SOCFPGA_F2S_FPGA5 (IRQ_SOCFPGA_GIC_START + 45) /* FPGA IRQ 5 */ -#define IRQ_SOCFPGA_F2S_FPGA6 (IRQ_SOCFPGA_GIC_START + 46) /* FPGA IRQ 6 */ -#define IRQ_SOCFPGA_F2S_FPGA7 (IRQ_SOCFPGA_GIC_START + 47) /* FPGA IRQ 7 */ -#define IRQ_SOCFPGA_F2S_FPGA8 (IRQ_SOCFPGA_GIC_START + 48) /* FPGA IRQ 8 */ -#define IRQ_SOCFPGA_F2S_FPGA9 (IRQ_SOCFPGA_GIC_START + 49) /* FPGA IRQ 9 */ -#define IRQ_SOCFPGA_F2S_FPGA10 (IRQ_SOCFPGA_GIC_START + 50) /* FPGA IRQ 10 */ -#define IRQ_SOCFPGA_F2S_FPGA11 (IRQ_SOCFPGA_GIC_START + 51) /* FPGA IRQ 11 */ -#define IRQ_SOCFPGA_F2S_FPGA12 (IRQ_SOCFPGA_GIC_START + 52) /* FPGA IRQ 12 */ -#define IRQ_SOCFPGA_F2S_FPGA13 (IRQ_SOCFPGA_GIC_START + 53) /* FPGA IRQ 13 */ -#define IRQ_SOCFPGA_F2S_FPGA14 (IRQ_SOCFPGA_GIC_START + 54) /* FPGA IRQ 14 */ -#define IRQ_SOCFPGA_F2S_FPGA15 (IRQ_SOCFPGA_GIC_START + 55) /* FPGA IRQ 15 */ -#define IRQ_SOCFPGA_F2S_FPGA16 (IRQ_SOCFPGA_GIC_START + 56) /* FPGA IRQ 16 */ -#define IRQ_SOCFPGA_F2S_FPGA17 (IRQ_SOCFPGA_GIC_START + 57) /* FPGA IRQ 17 */ -#define IRQ_SOCFPGA_F2S_FPGA18 (IRQ_SOCFPGA_GIC_START + 58) /* FPGA IRQ 18 */ -#define IRQ_SOCFPGA_F2S_FPGA19 (IRQ_SOCFPGA_GIC_START + 59) /* FPGA IRQ 19 */ -#define IRQ_SOCFPGA_F2S_FPGA20 (IRQ_SOCFPGA_GIC_START + 60) /* FPGA IRQ 20 */ -#define IRQ_SOCFPGA_F2S_FPGA21 (IRQ_SOCFPGA_GIC_START + 61) /* FPGA IRQ 21 */ -#define IRQ_SOCFPGA_F2S_FPGA22 (IRQ_SOCFPGA_GIC_START + 62) /* FPGA IRQ 22 */ -#define IRQ_SOCFPGA_F2S_FPGA23 (IRQ_SOCFPGA_GIC_START + 63) /* FPGA IRQ 23 */ -#define IRQ_SOCFPGA_F2S_FPGA24 (IRQ_SOCFPGA_GIC_START + 64) /* FPGA IRQ 24 */ -#define IRQ_SOCFPGA_F2S_FPGA25 (IRQ_SOCFPGA_GIC_START + 65) /* FPGA IRQ 25 */ -#define IRQ_SOCFPGA_F2S_FPGA26 (IRQ_SOCFPGA_GIC_START + 66) /* FPGA IRQ 26 */ -#define IRQ_SOCFPGA_F2S_FPGA27 (IRQ_SOCFPGA_GIC_START + 67) /* FPGA IRQ 27 */ -#define IRQ_SOCFPGA_F2S_FPGA28 (IRQ_SOCFPGA_GIC_START + 68) /* FPGA IRQ 28 */ -#define IRQ_SOCFPGA_F2S_FPGA29 (IRQ_SOCFPGA_GIC_START + 69) /* FPGA IRQ 29 */ -#define IRQ_SOCFPGA_F2S_FPGA30 (IRQ_SOCFPGA_GIC_START + 70) /* FPGA IRQ 30 */ -#define IRQ_SOCFPGA_F2S_FPGA31 (IRQ_SOCFPGA_GIC_START + 71) /* FPGA IRQ 31 */ -#define IRQ_SOCFPGA_F2S_FPGA32 (IRQ_SOCFPGA_GIC_START + 72) /* FPGA IRQ 32 */ -#define IRQ_SOCFPGA_F2S_FPGA33 (IRQ_SOCFPGA_GIC_START + 73) /* FPGA IRQ 33 */ -#define IRQ_SOCFPGA_F2S_FPGA34 (IRQ_SOCFPGA_GIC_START + 74) /* FPGA IRQ 34 */ -#define IRQ_SOCFPGA_F2S_FPGA35 (IRQ_SOCFPGA_GIC_START + 75) /* FPGA IRQ 35 */ -#define IRQ_SOCFPGA_F2S_FPGA36 (IRQ_SOCFPGA_GIC_START + 76) /* FPGA IRQ 36 */ -#define IRQ_SOCFPGA_F2S_FPGA37 (IRQ_SOCFPGA_GIC_START + 77) /* FPGA IRQ 37 */ -#define IRQ_SOCFPGA_F2S_FPGA38 (IRQ_SOCFPGA_GIC_START + 78) /* FPGA IRQ 38 */ -#define IRQ_SOCFPGA_F2S_FPGA39 (IRQ_SOCFPGA_GIC_START + 79) /* FPGA IRQ 39 */ -#define IRQ_SOCFPGA_F2S_FPGA40 (IRQ_SOCFPGA_GIC_START + 80) /* FPGA IRQ 40 */ -#define IRQ_SOCFPGA_F2S_FPGA41 (IRQ_SOCFPGA_GIC_START + 81) /* FPGA IRQ 41 */ -#define IRQ_SOCFPGA_F2S_FPGA42 (IRQ_SOCFPGA_GIC_START + 82) /* FPGA IRQ 42 */ -#define IRQ_SOCFPGA_F2S_FPGA43 (IRQ_SOCFPGA_GIC_START + 83) /* FPGA IRQ 43 */ -#define IRQ_SOCFPGA_F2S_FPGA44 (IRQ_SOCFPGA_GIC_START + 84) /* FPGA IRQ 44 */ -#define IRQ_SOCFPGA_F2S_FPGA45 (IRQ_SOCFPGA_GIC_START + 85) /* FPGA IRQ 45 */ -#define IRQ_SOCFPGA_F2S_FPGA46 (IRQ_SOCFPGA_GIC_START + 86) /* FPGA IRQ 46 */ -#define IRQ_SOCFPGA_F2S_FPGA47 (IRQ_SOCFPGA_GIC_START + 87) /* FPGA IRQ 47 */ -#define IRQ_SOCFPGA_F2S_FPGA48 (IRQ_SOCFPGA_GIC_START + 88) /* FPGA IRQ 48 */ -#define IRQ_SOCFPGA_F2S_FPGA49 (IRQ_SOCFPGA_GIC_START + 89) /* FPGA IRQ 49 */ -#define IRQ_SOCFPGA_F2S_FPGA50 (IRQ_SOCFPGA_GIC_START + 90) /* FPGA IRQ 50 */ -#define IRQ_SOCFPGA_F2S_FPGA51 (IRQ_SOCFPGA_GIC_START + 91) /* FPGA IRQ 51 */ -#define IRQ_SOCFPGA_F2S_FPGA52 (IRQ_SOCFPGA_GIC_START + 92) /* FPGA IRQ 52 */ -#define IRQ_SOCFPGA_F2S_FPGA53 (IRQ_SOCFPGA_GIC_START + 93) /* FPGA IRQ 53 */ -#define IRQ_SOCFPGA_F2S_FPGA54 (IRQ_SOCFPGA_GIC_START + 94) /* FPGA IRQ 54 */ -#define IRQ_SOCFPGA_F2S_FPGA55 (IRQ_SOCFPGA_GIC_START + 95) /* FPGA IRQ 55 */ -#define IRQ_SOCFPGA_F2S_FPGA56 (IRQ_SOCFPGA_GIC_START + 96) /* FPGA IRQ 56 */ -#define IRQ_SOCFPGA_F2S_FPGA57 (IRQ_SOCFPGA_GIC_START + 97) /* FPGA IRQ 57 */ -#define IRQ_SOCFPGA_F2S_FPGA58 (IRQ_SOCFPGA_GIC_START + 98) /* FPGA IRQ 58 */ -#define IRQ_SOCFPGA_F2S_FPGA59 (IRQ_SOCFPGA_GIC_START + 99) /* FPGA IRQ 59 */ -#define IRQ_SOCFPGA_F2S_FPGA60 (IRQ_SOCFPGA_GIC_START + 100) /* FPGA IRQ 60 */ -#define IRQ_SOCFPGA_F2S_FPGA61 (IRQ_SOCFPGA_GIC_START + 101) /* FPGA IRQ 61 */ -#define IRQ_SOCFPGA_F2S_FPGA62 (IRQ_SOCFPGA_GIC_START + 102) /* FPGA IRQ 62 */ -#define IRQ_SOCFPGA_F2S_FPGA63 (IRQ_SOCFPGA_GIC_START + 103) /* FPGA IRQ 63 */ -#define IRQ_SOCFPGA_DMA0 (IRQ_SOCFPGA_GIC_START + 104) /* DMA Channel 0 */ -#define IRQ_SOCFPGA_DMA1 (IRQ_SOCFPGA_GIC_START + 105) /* DMA Channel 1 */ -#define IRQ_SOCFPGA_DMA2 (IRQ_SOCFPGA_GIC_START + 106) /* DMA Channel 2 */ -#define IRQ_SOCFPGA_DMA3 (IRQ_SOCFPGA_GIC_START + 107) /* DMA Channel 3 */ -#define IRQ_SOCFPGA_DMA4 (IRQ_SOCFPGA_GIC_START + 108) /* DMA Channel 3 */ -#define IRQ_SOCFPGA_DMA5 (IRQ_SOCFPGA_GIC_START + 109) /* DMA Channel 5 */ -#define IRQ_SOCFPGA_DMA6 (IRQ_SOCFPGA_GIC_START + 110) /* DMA Channel 6 */ -#define IRQ_SOCFPGA_DMA7 (IRQ_SOCFPGA_GIC_START + 111) /* DMA Channel 7 */ -#define IRQ_SOCFPGA_DMA_ABORT (IRQ_SOCFPGA_GIC_START + 112) /* DMA abort */ -#define IRQ_SOCFPGA_DMA_CECC (IRQ_SOCFPGA_GIC_START + 113) /* DMA ECC corrected */ -#define IRQ_SOCFPGA_DMA_UECC (IRQ_SOCFPGA_GIC_START + 114) /* DMA ECC uncorrected */ -#define IRQ_SOCFPGA_EMAC0 (IRQ_SOCFPGA_GIC_START + 115) /* Gb-Ethernet MAC0 */ -#define IRQ_SOCFPGA_EMAC0_TX_CECC (IRQ_SOCFPGA_GIC_START + 116) /* Gb-Ethernet MAC0 ECC corrected */ -#define IRQ_SOCFPGA_EMAC0_TX_UECC (IRQ_SOCFPGA_GIC_START + 117) /* Gb-Ethernet MAC0 ECC uncorrected */ -#define IRQ_SOCFPGA_EMAC0_RX_CECC (IRQ_SOCFPGA_GIC_START + 118) /* Gb-Ethernet MAC0 ECC corrected */ -#define IRQ_SOCFPGA_EMAC0_RX_UECC (IRQ_SOCFPGA_GIC_START + 119) /* Gb-Ethernet MAC0 ECC uncorrected */ -#define IRQ_SOCFPGA_EMAC1 (IRQ_SOCFPGA_GIC_START + 120) /* Gb-Ethernet MAC1 */ -#define IRQ_SOCFPGA_EMAC1_TX_CECC (IRQ_SOCFPGA_GIC_START + 121) /* Gb-Ethernet MAC1 ECC corrected */ -#define IRQ_SOCFPGA_EMAC1_TX_UECC (IRQ_SOCFPGA_GIC_START + 122) /* Gb-Ethernet MAC1 ECC uncorrected */ -#define IRQ_SOCFPGA_EMAC1_RX_CECC (IRQ_SOCFPGA_GIC_START + 123) /* Gb-Ethernet MAC1 ECC corrected */ -#define IRQ_SOCFPGA_EMAC1_RX_UECC (IRQ_SOCFPGA_GIC_START + 124) /* Gb-Ethernet MAC1 ECC uncorrected */ -#define IRQ_SOCFPGA_USB0 (IRQ_SOCFPGA_GIC_START + 125) /* USB 0 generic */ -#define IRQ_SOCFPGA_USB0_CECC (IRQ_SOCFPGA_GIC_START + 126) /* USB 0 ECC corrected */ -#define IRQ_SOCFPGA_USB0_UECC (IRQ_SOCFPGA_GIC_START + 127) /* USB 0 ECC uncorrected */ -#define IRQ_SOCFPGA_USB1 (IRQ_SOCFPGA_GIC_START + 128) /* USB 1 generic */ -#define IRQ_SOCFPGA_USB1_CECC (IRQ_SOCFPGA_GIC_START + 129) /* USB 1 ECC corrected */ -#define IRQ_SOCFPGA_USB1_UECC (IRQ_SOCFPGA_GIC_START + 130) /* USB 1 ECC uncorrected */ -#define IRQ_SOCFPGA_CAN0_STS (IRQ_SOCFPGA_GIC_START + 131) /* CAN0 interrupt 0 */ -#define IRQ_SOCFPGA_CAN0_MO (IRQ_SOCFPGA_GIC_START + 132) /* CAN0 interrupt 1 */ -#define IRQ_SOCFPGA_CAN0_CECC (IRQ_SOCFPGA_GIC_START + 133) /* CAN0 ECC corrected */ -#define IRQ_SOCFPGA_CAN0_UECC (IRQ_SOCFPGA_GIC_START + 134) /* CAN0 ECC uncorrected */ -#define IRQ_SOCFPGA_CAN1_STS (IRQ_SOCFPGA_GIC_START + 135) /* CAN1 interrupt 0 */ -#define IRQ_SOCFPGA_CAN1_MO (IRQ_SOCFPGA_GIC_START + 136) /* CAN1 interrupt 1 */ -#define IRQ_SOCFPGA_CAN1_CECC (IRQ_SOCFPGA_GIC_START + 137) /* CAN1 ECC corrected */ -#define IRQ_SOCFPGA_CAN1_UECC (IRQ_SOCFPGA_GIC_START + 138) /* CAN1 ECC uncorrected */ -#define IRQ_SOCFPGA_SDMMC (IRQ_SOCFPGA_GIC_START + 139) /* SD/MMC */ -#define IRQ_SOCFPGA_SDMMC_PA_CECC (IRQ_SOCFPGA_GIC_START + 140) /* SD/MMC PortA ECC corrected */ -#define IRQ_SOCFPGA_SDMMC_PA_UECC (IRQ_SOCFPGA_GIC_START + 141) /* SD/MMC PortA ECC uncorrected */ -#define IRQ_SOCFPGA_SDMMC_PB_CECC (IRQ_SOCFPGA_GIC_START + 142) /* SD/MMC PortB ECC corrected */ -#define IRQ_SOCFPGA_SDMMC_PB_UECC (IRQ_SOCFPGA_GIC_START + 143) /* SD/MMC PortB ECC uncorrected */ -#define IRQ_SOCFPGA_NAND (IRQ_SOCFPGA_GIC_START + 144) /* NAND */ -#define IRQ_SOCFPGA_NAND_R_CECC (IRQ_SOCFPGA_GIC_START + 145) /* NAND read ECC corrected */ -#define IRQ_SOCFPGA_NAND_R_UECC (IRQ_SOCFPGA_GIC_START + 146) /* NAND read ECC uncorrected */ -#define IRQ_SOCFPGA_NAND_W_CECC (IRQ_SOCFPGA_GIC_START + 147) /* NAND write ECC corrected */ -#define IRQ_SOCFPGA_NAND_W_UECC (IRQ_SOCFPGA_GIC_START + 148) /* NAND write ECC uncorrected */ -#define IRQ_SOCFPGA_NAND_E_CECC (IRQ_SOCFPGA_GIC_START + 149) /* NAND error ECC corrected */ -#define IRQ_SOCFPGA_NAND_E_UECC (IRQ_SOCFPGA_GIC_START + 150) /* NAND error ECC uncorrected */ -#define IRQ_SOCFPGA_QSPI (IRQ_SOCFPGA_GIC_START + 151) /* Quad-SPI */ -#define IRQ_SOCFPGA_QSPI_CECC (IRQ_SOCFPGA_GIC_START + 152) /* Quad-SPI ECC corrected */ -#define IRQ_SOCFPGA_QSPI_UECC (IRQ_SOCFPGA_GIC_START + 153) /* Quad-SPI ECC uncorrected */ -#define IRQ_SOCFPGA_SPI0 (IRQ_SOCFPGA_GIC_START + 154) /* SPI 0 */ -#define IRQ_SOCFPGA_SPI1 (IRQ_SOCFPGA_GIC_START + 155) /* SPI 1 */ -#define IRQ_SOCFPGA_SPI2 (IRQ_SOCFPGA_GIC_START + 156) /* SPI 2 */ -#define IRQ_SOCFPGA_SPI3 (IRQ_SOCFPGA_GIC_START + 157) /* SPI 3 */ -#define IRQ_SOCFPGA_I2C0 (IRQ_SOCFPGA_GIC_START + 158) /* I2C 0 */ -#define IRQ_SOCFPGA_I2C1 (IRQ_SOCFPGA_GIC_START + 159) /* I2C 1 */ -#define IRQ_SOCFPGA_I2C2 (IRQ_SOCFPGA_GIC_START + 160) /* I2C 2 */ -#define IRQ_SOCFPGA_I2C3 (IRQ_SOCFPGA_GIC_START + 161) /* I2C 3 */ -#define IRQ_SOCFPGA_UART0 (IRQ_SOCFPGA_GIC_START + 162) /* UART 0 */ -#define IRQ_SOCFPGA_UART1 (IRQ_SOCFPGA_GIC_START + 163) /* UART 1 */ -#define IRQ_SOCFPGA_GPIO0 (IRQ_SOCFPGA_GIC_START + 164) /* GPIO 0 */ -#define IRQ_SOCFPGA_GPIO1 (IRQ_SOCFPGA_GIC_START + 165) /* GPIO 1 */ -#define IRQ_SOCFPGA_GPIO2 (IRQ_SOCFPGA_GIC_START + 166) /* GPIO 2 */ -#define IRQ_SOCFPGA_L4_SP_TIMER0 (IRQ_SOCFPGA_GIC_START + 167) /* L4 SP timer 0 */ -#define IRQ_SOCFPGA_L4_SP_TIMER1 (IRQ_SOCFPGA_GIC_START + 168) /* L4 SP timer 1 */ -#define IRQ_SOCFPGA_L4_OSC1_TIMER0 (IRQ_SOCFPGA_GIC_START + 169) /* L4 OSC1 timer 0 */ -#define IRQ_SOCFPGA_L4_OSC1_TIMER1 (IRQ_SOCFPGA_GIC_START + 170) /* L4 OSC1 timer 1 */ -#define IRQ_SOCFPGA_WD0 (IRQ_SOCFPGA_GIC_START + 171) /* Watchdog timer 0 */ -#define IRQ_SOCFPGA_WD1 (IRQ_SOCFPGA_GIC_START + 172) /* Watchdog timer 1 */ -#define IRQ_SOCFPGA_CLK_MAN (IRQ_SOCFPGA_GIC_START + 173) /* Clock manager */ -#define IRQ_SOCFPGA_MPU_WAKE (IRQ_SOCFPGA_GIC_START + 174) /* MPU wake */ -#define IRQ_SOCFPGA_FPGA_MON (IRQ_SOCFPGA_GIC_START + 175) /* FPGA monitor */ -#define IRQ_SOCFPGA_CPU0_CTI (IRQ_SOCFPGA_GIC_START + 176) /* Coresight CPU0 CTI */ -#define IRQ_SOCFPGA_CPU1_CTI (IRQ_SOCFPGA_GIC_START + 177) /* Coresight CPU1 CTI */ -#define IRQ_SOCFPGA_OCRAM_CECC (IRQ_SOCFPGA_GIC_START + 178) /* on-chip RAM ECC corrected */ -#define IRQ_SOCFPGA_OCRAM_UECC (IRQ_SOCFPGA_GIC_START + 179) /* on-chip RAM ECC uncorrected */ - -/* Soft IRQ */ -#define SOFTIRQ_SOCFPGA_DMADEV (IRQ_SOCFPGA_GIC_START + 180) -#define SOFTIRQ_SOCFPGA_GPIO_0_0 (IRQ_SOCFPGA_GIC_START + 181) -#define SOFTIRQ_SOCFPGA_GPIO_0_1 (IRQ_SOCFPGA_GIC_START + 182) -#define SOFTIRQ_SOCFPGA_GPIO_0_2 (IRQ_SOCFPGA_GIC_START + 183) -#define SOFTIRQ_SOCFPGA_GPIO_0_3 (IRQ_SOCFPGA_GIC_START + 184) -#define SOFTIRQ_SOCFPGA_GPIO_0_4 (IRQ_SOCFPGA_GIC_START + 185) -#define SOFTIRQ_SOCFPGA_GPIO_0_5 (IRQ_SOCFPGA_GIC_START + 186) -#define SOFTIRQ_SOCFPGA_GPIO_0_6 (IRQ_SOCFPGA_GIC_START + 187) -#define SOFTIRQ_SOCFPGA_GPIO_0_7 (IRQ_SOCFPGA_GIC_START + 188) -#define SOFTIRQ_SOCFPGA_GPIO_0_8 (IRQ_SOCFPGA_GIC_START + 189) -#define SOFTIRQ_SOCFPGA_GPIO_0_9 (IRQ_SOCFPGA_GIC_START + 190) -#define SOFTIRQ_SOCFPGA_GPIO_0_10 (IRQ_SOCFPGA_GIC_START + 191) -#define SOFTIRQ_SOCFPGA_GPIO_0_11 (IRQ_SOCFPGA_GIC_START + 192) -#define SOFTIRQ_SOCFPGA_GPIO_0_12 (IRQ_SOCFPGA_GIC_START + 193) -#define SOFTIRQ_SOCFPGA_GPIO_0_13 (IRQ_SOCFPGA_GIC_START + 194) -#define SOFTIRQ_SOCFPGA_GPIO_0_14 (IRQ_SOCFPGA_GIC_START + 195) -#define SOFTIRQ_SOCFPGA_GPIO_0_15 (IRQ_SOCFPGA_GIC_START + 196) -#define SOFTIRQ_SOCFPGA_GPIO_0_16 (IRQ_SOCFPGA_GIC_START + 197) -#define SOFTIRQ_SOCFPGA_GPIO_0_17 (IRQ_SOCFPGA_GIC_START + 198) -#define SOFTIRQ_SOCFPGA_GPIO_0_18 (IRQ_SOCFPGA_GIC_START + 199) -#define SOFTIRQ_SOCFPGA_GPIO_0_19 (IRQ_SOCFPGA_GIC_START + 200) -#define SOFTIRQ_SOCFPGA_GPIO_0_20 (IRQ_SOCFPGA_GIC_START + 201) -#define SOFTIRQ_SOCFPGA_GPIO_0_21 (IRQ_SOCFPGA_GIC_START + 202) -#define SOFTIRQ_SOCFPGA_GPIO_0_22 (IRQ_SOCFPGA_GIC_START + 203) -#define SOFTIRQ_SOCFPGA_GPIO_0_23 (IRQ_SOCFPGA_GIC_START + 204) -#define SOFTIRQ_SOCFPGA_GPIO_0_24 (IRQ_SOCFPGA_GIC_START + 205) -#define SOFTIRQ_SOCFPGA_GPIO_0_25 (IRQ_SOCFPGA_GIC_START + 206) -#define SOFTIRQ_SOCFPGA_GPIO_0_26 (IRQ_SOCFPGA_GIC_START + 207) -#define SOFTIRQ_SOCFPGA_GPIO_0_27 (IRQ_SOCFPGA_GIC_START + 208) -#define SOFTIRQ_SOCFPGA_GPIO_0_28 (IRQ_SOCFPGA_GIC_START + 209) -#define SOFTIRQ_SOCFPGA_GPIO_0_29 (IRQ_SOCFPGA_GIC_START + 210) -#define SOFTIRQ_SOCFPGA_GPIO_1_0 (IRQ_SOCFPGA_GIC_START + 211) -#define SOFTIRQ_SOCFPGA_GPIO_1_1 (IRQ_SOCFPGA_GIC_START + 212) -#define SOFTIRQ_SOCFPGA_GPIO_1_2 (IRQ_SOCFPGA_GIC_START + 213) -#define SOFTIRQ_SOCFPGA_GPIO_1_3 (IRQ_SOCFPGA_GIC_START + 214) -#define SOFTIRQ_SOCFPGA_GPIO_1_4 (IRQ_SOCFPGA_GIC_START + 215) -#define SOFTIRQ_SOCFPGA_GPIO_1_5 (IRQ_SOCFPGA_GIC_START + 216) -#define SOFTIRQ_SOCFPGA_GPIO_1_6 (IRQ_SOCFPGA_GIC_START + 217) -#define SOFTIRQ_SOCFPGA_GPIO_1_7 (IRQ_SOCFPGA_GIC_START + 218) -#define SOFTIRQ_SOCFPGA_GPIO_1_8 (IRQ_SOCFPGA_GIC_START + 219) -#define SOFTIRQ_SOCFPGA_GPIO_1_9 (IRQ_SOCFPGA_GIC_START + 220) -#define SOFTIRQ_SOCFPGA_GPIO_1_10 (IRQ_SOCFPGA_GIC_START + 221) -#define SOFTIRQ_SOCFPGA_GPIO_1_11 (IRQ_SOCFPGA_GIC_START + 222) -#define SOFTIRQ_SOCFPGA_GPIO_1_12 (IRQ_SOCFPGA_GIC_START + 223) -#define SOFTIRQ_SOCFPGA_GPIO_1_13 (IRQ_SOCFPGA_GIC_START + 224) -#define SOFTIRQ_SOCFPGA_GPIO_1_14 (IRQ_SOCFPGA_GIC_START + 225) -#define SOFTIRQ_SOCFPGA_GPIO_1_15 (IRQ_SOCFPGA_GIC_START + 226) -#define SOFTIRQ_SOCFPGA_GPIO_1_16 (IRQ_SOCFPGA_GIC_START + 227) -#define SOFTIRQ_SOCFPGA_GPIO_1_17 (IRQ_SOCFPGA_GIC_START + 228) -#define SOFTIRQ_SOCFPGA_GPIO_1_18 (IRQ_SOCFPGA_GIC_START + 229) -#define SOFTIRQ_SOCFPGA_GPIO_1_19 (IRQ_SOCFPGA_GIC_START + 230) -#define SOFTIRQ_SOCFPGA_GPIO_1_20 (IRQ_SOCFPGA_GIC_START + 231) -#define SOFTIRQ_SOCFPGA_GPIO_1_21 (IRQ_SOCFPGA_GIC_START + 232) -#define SOFTIRQ_SOCFPGA_GPIO_1_22 (IRQ_SOCFPGA_GIC_START + 233) -#define SOFTIRQ_SOCFPGA_GPIO_1_23 (IRQ_SOCFPGA_GIC_START + 234) -#define SOFTIRQ_SOCFPGA_GPIO_1_24 (IRQ_SOCFPGA_GIC_START + 235) -#define SOFTIRQ_SOCFPGA_GPIO_1_25 (IRQ_SOCFPGA_GIC_START + 236) -#define SOFTIRQ_SOCFPGA_GPIO_1_26 (IRQ_SOCFPGA_GIC_START + 237) -#define SOFTIRQ_SOCFPGA_GPIO_1_27 (IRQ_SOCFPGA_GIC_START + 238) -#define SOFTIRQ_SOCFPGA_GPIO_1_28 (IRQ_SOCFPGA_GIC_START + 239) -#define SOFTIRQ_SOCFPGA_GPIO_1_29 (IRQ_SOCFPGA_GIC_START + 240) -#define SOFTIRQ_SOCFPGA_GPIO_2_0 (IRQ_SOCFPGA_GIC_START + 241) -#define SOFTIRQ_SOCFPGA_GPIO_2_1 (IRQ_SOCFPGA_GIC_START + 242) -#define SOFTIRQ_SOCFPGA_GPIO_2_2 (IRQ_SOCFPGA_GIC_START + 243) -#define SOFTIRQ_SOCFPGA_GPIO_2_3 (IRQ_SOCFPGA_GIC_START + 244) -#define SOFTIRQ_SOCFPGA_GPIO_2_4 (IRQ_SOCFPGA_GIC_START + 245) -#define SOFTIRQ_SOCFPGA_GPIO_2_5 (IRQ_SOCFPGA_GIC_START + 246) -#define SOFTIRQ_SOCFPGA_GPIO_2_6 (IRQ_SOCFPGA_GIC_START + 247) -#define SOFTIRQ_SOCFPGA_GPIO_2_7 (IRQ_SOCFPGA_GIC_START + 248) -#define SOFTIRQ_SOCFPGA_GPIO_2_8 (IRQ_SOCFPGA_GIC_START + 249) -#define SOFTIRQ_SOCFPGA_GPIO_2_9 (IRQ_SOCFPGA_GIC_START + 250) -#define SOFTIRQ_SOCFPGA_GPIO_2_10 (IRQ_SOCFPGA_GIC_START + 251) -#define SOFTIRQ_SOCFPGA_GPIO_2_11 (IRQ_SOCFPGA_GIC_START + 252) -#define SOFTIRQ_SOCFPGA_GPIO_2_12 (IRQ_SOCFPGA_GIC_START + 253) -#define SOFTIRQ_SOCFPGA_GPIO_2_13 (IRQ_SOCFPGA_GIC_START + 254) -#define SOFTIRQ_SOCFPGA_GPIO_2_14 (IRQ_SOCFPGA_GIC_START + 255) -#define SOFTIRQ_SOCFPGA_GPIO_2_15 (IRQ_SOCFPGA_GIC_START + 256) -#define SOFTIRQ_SOCFPGA_GPIO_2_16 (IRQ_SOCFPGA_GIC_START + 257) -#define SOFTIRQ_SOCFPGA_GPIO_2_17 (IRQ_SOCFPGA_GIC_START + 258) -#define SOFTIRQ_SOCFPGA_GPIO_2_18 (IRQ_SOCFPGA_GIC_START + 259) -#define SOFTIRQ_SOCFPGA_GPIO_2_19 (IRQ_SOCFPGA_GIC_START + 260) -#define SOFTIRQ_SOCFPGA_GPIO_2_20 (IRQ_SOCFPGA_GIC_START + 261) -#define SOFTIRQ_SOCFPGA_GPIO_2_21 (IRQ_SOCFPGA_GIC_START + 262) -#define SOFTIRQ_SOCFPGA_GPIO_2_22 (IRQ_SOCFPGA_GIC_START + 263) -#define SOFTIRQ_SOCFPGA_GPIO_2_23 (IRQ_SOCFPGA_GIC_START + 264) -#define SOFTIRQ_SOCFPGA_GPIO_2_24 (IRQ_SOCFPGA_GIC_START + 265) -#define SOFTIRQ_SOCFPGA_GPIO_2_25 (IRQ_SOCFPGA_GIC_START + 266) -#define SOFTIRQ_SOCFPGA_GPIO_2_26 (IRQ_SOCFPGA_GIC_START + 267) -#define SOFTIRQ_SOCFPGA_GPIO_2_27 (IRQ_SOCFPGA_GIC_START + 268) -#define SOFTIRQ_SOCFPGA_GPIO_2_28 (IRQ_SOCFPGA_GIC_START + 269) -#define SOFTIRQ_SOCFPGA_GPIO_2_29 (IRQ_SOCFPGA_GIC_START + 270) #define NR_IRQS 512 diff --git a/arch/arm/mach-socfpga/include/mach/system.h b/arch/arm/mach-socfpga/include/mach/system.h index c76834c..e69de29 100644 --- a/arch/arm/mach-socfpga/include/mach/system.h +++ b/arch/arm/mach-socfpga/include/mach/system.h @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * Modified from arch/arm/mach-realview/include/mach/system.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. -*/ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -static inline void arch_idle(void) -{ - /* - * This should do all the clock switching - * and wait for interrupt tricks - */ - cpu_do_idle(); -} - -#endif diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 2f9a81e..101b968 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -381,7 +381,7 @@ config CPU_V6K # ARMv7 config CPU_V7 - bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_SOCFPGA + bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX select CPU_32v6K select CPU_32v7 select CPU_ABRT_EV7 -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 14:20 ` Thomas Petazzoni 2012-06-27 18:05 ` Pavel Machek 2012-06-27 20:27 ` [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform Pavel Machek @ 2012-06-30 18:57 ` Pavel Machek 2012-07-01 18:10 ` Pavel Machek 2012-07-04 10:56 ` Pavel Machek 2012-07-04 11:15 ` Pavel Machek 4 siblings, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-06-30 18:57 UTC (permalink / raw) To: linux-arm-kernel Hi! > > +#include <linux/module.h> > > +#include <linux/kernel.h> > > +#include <linux/errno.h> > > +#include <linux/clk.h> > > +#include <linux/mutex.h> > > +#include <mach/clkdev.h> > > + > > +int clk_enable(struct clk *clk) > > +{ > > + return 0; > > +} > > +EXPORT_SYMBOL(clk_enable); .... > > I don't think the ARM maintainers want more implementations of the > clock API. New SoCs should instead use the new clock framework in > drivers/clk/. See Documentation/clk.txt for details. You can for > example look at the mxs or spear implementations for examples. Agreed. Looks like fixed-rates. > > + { > > + .dev_id = "dma-pl330", > > + .clk = &l4_main_clk, > > + } > > +}; > > These should use the clock framework. Yep. Something like this? (Untested) Pavel diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 37863d1..81358e6 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -3,6 +3,7 @@ config MACH_SOCFPGA_CYCLONE5 bool "SOCFPGA Cyclone5 platform" select HAVE_SMP select PLAT_SOCFPGA_ETH + select COMMON_CLK help Include support for the Altera(R) Cyclone5 development platform. diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 5502add..3e79bb0 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := common.o clock.o dw_apb_timer.o +obj-y := common.o dw_apb_timer.o obj-$(CONFIG_MACH_SOCFPGA_CYCLONE5) += socfpga_cyclone5.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o \ No newline at end of file diff --git a/arch/arm/mach-socfpga/common.c b/arch/arm/mach-socfpga/common.c index 331040e..eac2571 100644 --- a/arch/arm/mach-socfpga/common.c +++ b/arch/arm/mach-socfpga/common.c @@ -22,6 +22,7 @@ #include <linux/clkdev.h> #include <linux/gfp.h> #include <linux/of_platform.h> +#include <linux/clk-provider.h> #include <mach/iomap.h> #include <mach/socfpga_cyclone5.h> @@ -49,51 +50,6 @@ extern struct dma_pl330_platdata dma_platform_data; #define SOCFPGA_MPU_PERIHCLK_FREQ_HZ (800000000 / 4) #define SOCFPGA_L4_MAIN_CLK (400000000) -static struct clk dummy_apb_pclk; -static struct clk dummy_i2c_clk = { - .rate = 100000000, -}; -static struct clk dummy_spim_clk = { - .rate = 100000000, -}; -static struct clk mpu_periphclk = { - .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ, -}; - -static struct clk l4_main_clk = { - .rate = SOCFPGA_L4_MAIN_CLK, -}; - -static struct clk_lookup lookups[] = { - { /* Bus clock */ - .con_id = "apb_pclk", - .clk = &dummy_apb_pclk, - }, - { - .dev_id = "ffc04000.i2c", - .clk = &dummy_i2c_clk, - }, - { - .dev_id = "ffc05000.i2c", - .clk = &dummy_i2c_clk, - }, - { - .dev_id = "dw-spi-mmio.0", - .clk = &dummy_spim_clk, - }, - { - .dev_id = "dw-spi-mmio.1", - .clk = &dummy_spim_clk, - }, - { - .dev_id = "smp_twd", - .clk = &mpu_periphclk, - }, - { - .dev_id = "dma-pl330", - .clk = &l4_main_clk, - } -}; struct plat_serial8250_port uart_platform_data[] = { { @@ -105,7 +61,36 @@ struct plat_serial8250_port uart_platform_data[] = { void __init socfpga_init_early(void) { - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + struct clk *dummy_apb_pclk; + struct clk *dummy_i2c_clk; + struct clk *dummy_spim_clk; + struct clk *mpu_periphclk; + struct clk *l4_main_clk; + + dummy_apb_pclk = clk_register_fixed_rate(NULL, "apb", NULL, 0, 0); + dummy_i2c_clk = clk_register_fixed_rate(NULL, "i2c", NULL, 0, 100000000); + dummy_spim_clk = clk_register_fixed_rate(NULL, "spim", NULL, 0, 100000000); + mpu_periphclk = clk_register_fixed_rate(NULL, "mpu_perih", NULL, 0, SOCFPGA_MPU_PERIHCLK_FREQ_HZ); + l4_main_clk = clk_register_fixed_rate(NULL, "l4_main", NULL, 0, SOCFPGA_L4_MAIN_CLK); + + { + static struct clk_lookup lookups[7]; + lookups[0].con_id = "apb_pclk"; /* Bus clock */ + lookups[0].clk = dummy_apb_pclk; + lookups[1].dev_id = "ffc04000.i2c"; + lookups[1].clk = dummy_i2c_clk; + lookups[2].dev_id = "ffc05000.i2c"; + lookups[2].clk = dummy_i2c_clk; + lookups[3].dev_id = "dw-spi-mmio.0"; + lookups[3].clk = dummy_spim_clk; + lookups[4].dev_id = "dw-spi-mmio.1"; + lookups[4].clk = dummy_spim_clk; + lookups[5].dev_id = "smp_twd"; + lookups[5].clk = mpu_periphclk; + lookups[6].dev_id = "dma-pl330"; + lookups[6].clk = l4_main_clk; + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + } } /* diff --git a/arch/arm/mach-socfpga/include/mach/clock.h b/arch/arm/mach-socfpga/include/mach/clock.h index 5187064..de9d3b2 100644 --- a/arch/arm/mach-socfpga/include/mach/clock.h +++ b/arch/arm/mach-socfpga/include/mach/clock.h @@ -1,11 +1,4 @@ #ifndef __MACH_CLOCK_H #define __MACH_CLOCK_H -struct clk; - -struct clk_ops { - long (*round)(struct clk *, unsigned long); - int (*set)(struct clk *, unsigned long); -}; - #endif -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-30 18:57 ` Pavel Machek @ 2012-07-01 18:10 ` Pavel Machek 0 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-07-01 18:10 UTC (permalink / raw) To: linux-arm-kernel Hi! > > I don't think the ARM maintainers want more implementations of the > > clock API. New SoCs should instead use the new clock framework in > > drivers/clk/. See Documentation/clk.txt for details. You can for > > example look at the mxs or spear implementations for examples. > > Agreed. Looks like fixed-rates. > > > > + { > > > + .dev_id = "dma-pl330", > > > + .clk = &l4_main_clk, > > > + } > > > +}; > > > > These should use the clock framework. > > Yep. Something like this? (Untested) Did not work, apparently socfpga_init_early() is too early to call clk_*(). This one actually finishes kernel boot. Worrying thing is that if I don't call it at all, it also finishes kernel boot. So how does one test this properly? Pavel diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 37863d1..81358e6 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -3,6 +3,7 @@ config MACH_SOCFPGA_CYCLONE5 bool "SOCFPGA Cyclone5 platform" select HAVE_SMP select PLAT_SOCFPGA_ETH + select COMMON_CLK help Include support for the Altera(R) Cyclone5 development platform. diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 5502add..3e79bb0 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := common.o clock.o dw_apb_timer.o +obj-y := common.o dw_apb_timer.o obj-$(CONFIG_MACH_SOCFPGA_CYCLONE5) += socfpga_cyclone5.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o \ No newline at end of file diff --git a/arch/arm/mach-socfpga/common.c b/arch/arm/mach-socfpga/common.c index 331040e..0df10ef 100644 --- a/arch/arm/mach-socfpga/common.c +++ b/arch/arm/mach-socfpga/common.c @@ -22,6 +22,7 @@ #include <linux/clkdev.h> #include <linux/gfp.h> #include <linux/of_platform.h> +#include <linux/clk-provider.h> #include <mach/iomap.h> #include <mach/socfpga_cyclone5.h> @@ -49,51 +50,6 @@ extern struct dma_pl330_platdata dma_platform_data; #define SOCFPGA_MPU_PERIHCLK_FREQ_HZ (800000000 / 4) #define SOCFPGA_L4_MAIN_CLK (400000000) -static struct clk dummy_apb_pclk; -static struct clk dummy_i2c_clk = { - .rate = 100000000, -}; -static struct clk dummy_spim_clk = { - .rate = 100000000, -}; -static struct clk mpu_periphclk = { - .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ, -}; - -static struct clk l4_main_clk = { - .rate = SOCFPGA_L4_MAIN_CLK, -}; - -static struct clk_lookup lookups[] = { - { /* Bus clock */ - .con_id = "apb_pclk", - .clk = &dummy_apb_pclk, - }, - { - .dev_id = "ffc04000.i2c", - .clk = &dummy_i2c_clk, - }, - { - .dev_id = "ffc05000.i2c", - .clk = &dummy_i2c_clk, - }, - { - .dev_id = "dw-spi-mmio.0", - .clk = &dummy_spim_clk, - }, - { - .dev_id = "dw-spi-mmio.1", - .clk = &dummy_spim_clk, - }, - { - .dev_id = "smp_twd", - .clk = &mpu_periphclk, - }, - { - .dev_id = "dma-pl330", - .clk = &l4_main_clk, - } -}; struct plat_serial8250_port uart_platform_data[] = { { @@ -103,11 +59,46 @@ struct plat_serial8250_port uart_platform_data[] = { }, }; +void __init socfpga_init_clocks(void) +{ + struct clk *dummy_apb_pclk; + struct clk *dummy_i2c_clk; + struct clk *dummy_spim_clk; + struct clk *mpu_periphclk; + struct clk *l4_main_clk; + + dummy_apb_pclk = clk_register_fixed_rate(NULL, "apb", NULL, 0, 0); + dummy_i2c_clk = clk_register_fixed_rate(NULL, "i2c", NULL, 0, 100000000); + dummy_spim_clk = clk_register_fixed_rate(NULL, "spim", NULL, 0, 100000000); + mpu_periphclk = clk_register_fixed_rate(NULL, "mpu_periph", NULL, 0, SOCFPGA_MPU_PERIHCLK_FREQ_HZ); + l4_main_clk = clk_register_fixed_rate(NULL, "l4_main", NULL, 0, SOCFPGA_L4_MAIN_CLK); + + { + static struct clk_lookup lookups[7]; + lookups[0].con_id = "apb_pclk"; /* Bus clock */ + lookups[0].clk = dummy_apb_pclk; + lookups[1].dev_id = "ffc04000.i2c"; + lookups[1].clk = dummy_i2c_clk; + lookups[2].dev_id = "ffc05000.i2c"; + lookups[2].clk = dummy_i2c_clk; + lookups[3].dev_id = "dw-spi-mmio.0"; + lookups[3].clk = dummy_spim_clk; + lookups[4].dev_id = "dw-spi-mmio.1"; + lookups[4].clk = dummy_spim_clk; + lookups[5].dev_id = "smp_twd"; + lookups[5].clk = mpu_periphclk; + lookups[6].dev_id = "dma-pl330"; + lookups[6].clk = l4_main_clk; + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + } +} + void __init socfpga_init_early(void) { - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); } +//initcall(socfpga_init_clocks); + /* * Where is the timer (VA)? */ diff --git a/arch/arm/mach-socfpga/include/mach/clock.h b/arch/arm/mach-socfpga/include/mach/clock.h index 5187064..de9d3b2 100644 --- a/arch/arm/mach-socfpga/include/mach/clock.h +++ b/arch/arm/mach-socfpga/include/mach/clock.h @@ -1,11 +1,4 @@ #ifndef __MACH_CLOCK_H #define __MACH_CLOCK_H -struct clk; - -struct clk_ops { - long (*round)(struct clk *, unsigned long); - int (*set)(struct clk *, unsigned long); -}; - #endif -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 14:20 ` Thomas Petazzoni ` (2 preceding siblings ...) 2012-06-30 18:57 ` Pavel Machek @ 2012-07-04 10:56 ` Pavel Machek 2012-07-04 11:10 ` Thomas Petazzoni 2012-07-04 11:15 ` Pavel Machek 4 siblings, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-07-04 10:56 UTC (permalink / raw) To: linux-arm-kernel Hi! > > +struct plat_serial8250_port uart_platform_data[] = { > > + { > > + .type = PORT_16850, > > + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | \ > > + UPF_FIXED_TYPE, > > + }, > > +}; > > This sounds strange. Why aren't you using the ns16850 compatible string > to instantiate the UART devices directly from your device tree? Hmm, strange. I see picoxcell-pc3x2.dtsi using similar dw-apb-uart. According to 8250_dw.c, it is not completely 16550-compatible, and uses slightly modified driver. So it can be driven from dts, but not as ns16850 compatible. This patch does so. Signed-off-by: Pavel Machek <pavel@denx.de> diff --git a/arch/arm/mach-socfpga/common.c b/arch/arm/mach-socfpga/common.c index 0df10ef..ae310a5 100644 --- a/arch/arm/mach-socfpga/common.c +++ b/arch/arm/mach-socfpga/common.c @@ -45,20 +45,9 @@ extern struct dw_mci_board sdmmc_platform_data; extern struct dma_pl330_platdata dma_platform_data; -#define DW_APB_UART_OF_COMPATIBLE "snps,dw-apb-uart" - #define SOCFPGA_MPU_PERIHCLK_FREQ_HZ (800000000 / 4) #define SOCFPGA_L4_MAIN_CLK (400000000) - -struct plat_serial8250_port uart_platform_data[] = { - { - .type = PORT_16850, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | \ - UPF_FIXED_TYPE, - }, -}; - void __init socfpga_init_clocks(void) { struct clk *dummy_apb_pclk; @@ -126,12 +115,3 @@ void __init socfpga_timer_init(void __iomem *src_timer_base, dwapbt_clocksource_init(src_timer_base); dwapbt_clockevents_init(event_timer_base, event_timer_irq); } - -int socfpga_notifier(struct device *device) -{ - struct device_node *dn = device->of_node; - - if (of_device_is_compatible(dn, DW_APB_UART_OF_COMPATIBLE)) - device->platform_data = &uart_platform_data; - return 0; -} diff --git a/arch/arm/mach-socfpga/socfpga_cyclone5.c b/arch/arm/mach-socfpga/socfpga_cyclone5.c index d8cd89b..d67fc92 100644 --- a/arch/arm/mach-socfpga/socfpga_cyclone5.c +++ b/arch/arm/mach-socfpga/socfpga_cyclone5.c @@ -138,7 +138,6 @@ static void __init socfpga_cyclone5_init(void) /* 8-way, 64K/way, evmon/parity/share */ l2x0_of_init(0x00760000, 0xfe000fff); #endif - platform_notify = socfpga_notifier; of_platform_populate(NULL, of_default_bus_match_table, cyclone5_auxdata_lookup, NULL); } -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-04 10:56 ` Pavel Machek @ 2012-07-04 11:10 ` Thomas Petazzoni 2012-07-04 11:23 ` Pavel Machek 0 siblings, 1 reply; 47+ messages in thread From: Thomas Petazzoni @ 2012-07-04 11:10 UTC (permalink / raw) To: linux-arm-kernel Hello, Le Wed, 4 Jul 2012 12:56:53 +0200, Pavel Machek <pavel@denx.de> a ?crit : > Hmm, strange. I see picoxcell-pc3x2.dtsi using similar > dw-apb-uart. According to 8250_dw.c, it is not completely > 16550-compatible, and uses slightly modified driver. > > So it can be driven from dts, but not as ns16850 compatible. This > patch does so. I guess your patch misses the .dts bits, but other than that, looks much better without this bizarre notifier thing. Do you plan to resend a complete v2 with all your patches nicely rebased? It's not that easy to review such a set of small cleanup increments :-) Regards, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-04 11:10 ` Thomas Petazzoni @ 2012-07-04 11:23 ` Pavel Machek 2012-07-04 14:30 ` Dinh Nguyen 0 siblings, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-07-04 11:23 UTC (permalink / raw) To: linux-arm-kernel On Wed 2012-07-04 13:10:24, Thomas Petazzoni wrote: > Hello, > > Le Wed, 4 Jul 2012 12:56:53 +0200, > Pavel Machek <pavel@denx.de> a ?crit : > > > Hmm, strange. I see picoxcell-pc3x2.dtsi using similar > > dw-apb-uart. According to 8250_dw.c, it is not completely > > 16550-compatible, and uses slightly modified driver. > > > > So it can be driven from dts, but not as ns16850 compatible. This > > patch does so. > > I guess your patch misses the .dts bits, but other than that, looks > much better without this bizarre notifier thing. It turned out that dts already does the right thing. > Do you plan to resend a complete v2 with all your patches nicely > rebased? It's not that easy to review such a set of small cleanup > increments :-) Sorry about that. Obviously, complete v2 will follow when major problems are fixed. (We do use git tree for coordination; I guess we should make it public at this point?) Thanks, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-04 11:23 ` Pavel Machek @ 2012-07-04 14:30 ` Dinh Nguyen 2012-07-09 10:58 ` Pavel Machek 0 siblings, 1 reply; 47+ messages in thread From: Dinh Nguyen @ 2012-07-04 14:30 UTC (permalink / raw) To: linux-arm-kernel Hi, > -----Original Message----- > From: Pavel Machek [mailto:pavel at denx.de] > Sent: Wednesday, July 04, 2012 6:24 AM > To: Thomas Petazzoni > Cc: Dinh Nguyen; linux at arm.linux.org.uk; Kenneth Chong Yin Tan; > wd at denx.de; linux-arm-kernel at lists.infradead.org > Subject: Re: [RFC PATCHv1 1/2] ARM: socfpga: initial support for > Altera's SOCFPGA platform. > > On Wed 2012-07-04 13:10:24, Thomas Petazzoni wrote: > > Hello, > > > > Le Wed, 4 Jul 2012 12:56:53 +0200, > > Pavel Machek <pavel@denx.de> a ?crit : > > > > > Hmm, strange. I see picoxcell-pc3x2.dtsi using similar > > > dw-apb-uart. According to 8250_dw.c, it is not completely > > > 16550-compatible, and uses slightly modified driver. > > > > > > So it can be driven from dts, but not as ns16850 compatible. This > > > patch does so. > > > > I guess your patch misses the .dts bits, but other than that, looks > > much better without this bizarre notifier thing. > > It turned out that dts already does the right thing. > > > Do you plan to resend a complete v2 with all your patches nicely > > rebased? It's not that easy to review such a set of small cleanup > > increments :-) > > Sorry about that. Obviously, complete v2 will follow when major > problems are fixed. (We do use git tree for coordination; I guess we > should make it public at this point?) I'm reworking the patch to use the exisiting clocksource/dw_apb_timer driver. I'm hoping to have v2 ready for submission by early next week. Dinh > > Thanks, > Pavel > -- > (english) http://www.livejournal.com/~pavelmachek > (cesky, pictures) > http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html Confidentiality Notice. This message may contain information that is confidential or otherwise protected from disclosure. If you are not the intended recipient, you are hereby notified that any use, disclosure, dissemination, distribution, or copying of this message, or any attachments, is strictly prohibited. If you have received this message in error, please advise the sender by reply e-mail, and delete the message and any attachments. Thank you. ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-04 14:30 ` Dinh Nguyen @ 2012-07-09 10:58 ` Pavel Machek 0 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-07-09 10:58 UTC (permalink / raw) To: linux-arm-kernel Hi! > > > Do you plan to resend a complete v2 with all your patches nicely > > > rebased? It's not that easy to review such a set of small cleanup > > > increments :-) > > > > Sorry about that. Obviously, complete v2 will follow when major > > problems are fixed. (We do use git tree for coordination; I guess we > > should make it public at this point?) > > I'm reworking the patch to use the exisiting > clocksource/dw_apb_timer driver. Any news there? I got up-to attached diff, but could not get it to boot... Pavel diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index 453a7e2..6f22e0e 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -85,6 +85,20 @@ phy-mode = "gmii"; }; + rtc0: rtc at 00000 { + compatible = "not-there-picochip,pc3x2-rtc"; + clock-freq = <200000000>; + reg = <0x00000 0xf>; + interrupts = <8>; + }; + + timer0: timer at ffd00000 { + compatible = "picochip,pc3x2-timer"; + interrupts = <169>; + clock-freq = <200000000>; + reg = <0xffd00000 0x14>; + interrupt-parent = <&intc>; + }; }; }; }; diff --git a/arch/arm/mach-picoxcell/time.c b/arch/arm/mach-picoxcell/time.c index 2ecba67..eeebf2a 100644 --- a/arch/arm/mach-picoxcell/time.c +++ b/arch/arm/mach-picoxcell/time.c @@ -106,14 +106,15 @@ static void __init picoxcell_timer_init(void) panic("No timer for clockevent"); picoxcell_add_clockevent(event_timer); +#if 0 source_timer = of_find_matching_node(event_timer, picoxcell_timer_ids); if (!source_timer) panic("No timer for clocksource"); picoxcell_add_clocksource(source_timer); - +#endif of_node_put(source_timer); - picoxcell_init_sched_clock(); +// picoxcell_init_sched_clock(); } struct sys_timer picoxcell_timer = { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 81358e6..124422d 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -4,6 +4,7 @@ config MACH_SOCFPGA_CYCLONE5 select HAVE_SMP select PLAT_SOCFPGA_ETH select COMMON_CLK + select DW_APB_TIMER help Include support for the Altera(R) Cyclone5 development platform. diff --git a/arch/arm/mach-socfpga/common.c b/arch/arm/mach-socfpga/common.c index ae310a5..7451c6f 100644 --- a/arch/arm/mach-socfpga/common.c +++ b/arch/arm/mach-socfpga/common.c @@ -42,6 +42,8 @@ #include "common.h" +#include "../../../arch/arm/mach-picoxcell/time.c" + extern struct dw_mci_board sdmmc_platform_data; extern struct dma_pl330_platdata dma_platform_data; @@ -112,6 +114,15 @@ void __init socfpga_timer_init(void __iomem *src_timer_base, writel(0, osc_timer0_va_base + TIMER_CTRL); writel(0, osc_timer1_va_base + TIMER_CTRL); +#if 0 + /* Fall back to jiffies? */ dwapbt_clocksource_init(src_timer_base); +#endif + +#if 0 + /* Use dt-based code from picoxcell */ dwapbt_clockevents_init(event_timer_base, event_timer_irq); +#endif + + picoxcell_timer_init(); } diff --git a/arch/arm/mach-socfpga/socfpga_cyclone5.c b/arch/arm/mach-socfpga/socfpga_cyclone5.c index d67fc92..9fc89cc 100644 --- a/arch/arm/mach-socfpga/socfpga_cyclone5.c +++ b/arch/arm/mach-socfpga/socfpga_cyclone5.c @@ -118,6 +118,7 @@ static void __init socfpga_cyclone5_timer_init(void) socfpga_timer_init(sp_timer0_va_base, osc_timer0_va_base, IRQ_SOCFPGA_L4_OSC1_TIMER0); + #ifdef CONFIG_OF twd_local_timer_of_register(); #endif -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 14:20 ` Thomas Petazzoni ` (3 preceding siblings ...) 2012-07-04 10:56 ` Pavel Machek @ 2012-07-04 11:15 ` Pavel Machek 2012-07-04 11:21 ` Thomas Petazzoni 4 siblings, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-07-04 11:15 UTC (permalink / raw) To: linux-arm-kernel Hi! > > +/* > > + * Set up the clock source and clock events devices > > + */ > > + > > +void __init socfpga_timer_init(void __iomem *src_timer_base, > > + void __iomem *event_timer_base, > > + unsigned int event_timer_irq) > > +{ > > + /* > > + * Initialise to a known state (all timers off) > > + */ > > + writel(0, sp_timer0_va_base + TIMER_CTRL); > > + writel(0, sp_timer1_va_base + TIMER_CTRL); > > + writel(0, osc_timer0_va_base + TIMER_CTRL); > > + writel(0, osc_timer1_va_base + TIMER_CTRL); > > Shouldn't this be done within the timer driver itself? > > +++ b/arch/arm/mach-socfpga/dw_apb_timer.c > > The clocksource/clockevents driver now go into drivers/clocksource/, > and the corresponding maintainers should be CC'ed (Thomas Gleixner and > John Stultz. Hmm, fortunately drivers/clocksource already has one such driver. Maybe arch/arm/mach-picoxcell/time.c can be used as a template? Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-04 11:15 ` Pavel Machek @ 2012-07-04 11:21 ` Thomas Petazzoni 0 siblings, 0 replies; 47+ messages in thread From: Thomas Petazzoni @ 2012-07-04 11:21 UTC (permalink / raw) To: linux-arm-kernel Le Wed, 4 Jul 2012 13:15:23 +0200, Pavel Machek <pavel@denx.de> a ?crit : > > The clocksource/clockevents driver now go into drivers/clocksource/, > > and the corresponding maintainers should be CC'ed (Thomas Gleixner and > > John Stultz. > > Hmm, fortunately drivers/clocksource already has one such > driver. Maybe arch/arm/mach-picoxcell/time.c can be used as a > template? I must say I don't know what's the preferred way here. In mach-mvebu, the drivers/clocksource/time-armada-370-xp.c does everything, including the DT parsing. The part in arch/arm/mach-mvebu/ only defines struct sys_timer and points to the initialization function in the drivers/clocksource/ driver. Apparently, in mach-picoxcell, things are organized differently, with the DT parsing happening in arch/arm/mach-picoxcell/time.c, and the driver providing some lower-level functions to separately register the clocksource and the clockevents devices. I have no idea which one should be preferred over the other. Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-06-27 13:50 ` [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform dinguyen at altera.com 2012-06-27 14:20 ` Thomas Petazzoni @ 2012-07-04 17:56 ` Rob Herring 2012-07-09 11:30 ` Pavel Machek ` (3 more replies) 1 sibling, 4 replies; 47+ messages in thread From: Rob Herring @ 2012-07-04 17:56 UTC (permalink / raw) To: linux-arm-kernel On 06/27/2012 08:50 AM, dinguyen at altera.com wrote: > From: Dinh Nguyen <dinguyen@altera.com> > > Adding core definitions for Altera's SOCFPGA ARM platform. > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > Reviewed-by: Pavel Machek <pavel@denx.de> > --- > MAINTAINERS | 5 + > arch/arm/Kconfig | 19 ++ > arch/arm/Makefile | 1 + > arch/arm/mach-socfpga/Kconfig | 21 ++ > arch/arm/mach-socfpga/Makefile | 8 + > arch/arm/mach-socfpga/Makefile.boot | 3 + > arch/arm/mach-socfpga/clock.c | 50 ++++ > arch/arm/mach-socfpga/common.c | 156 ++++++++++ > arch/arm/mach-socfpga/common.h | 38 +++ > arch/arm/mach-socfpga/dw_apb_timer.c | 164 +++++++++++ > arch/arm/mach-socfpga/headsmp.S | 41 +++ > arch/arm/mach-socfpga/hotplug.c | 125 ++++++++ > arch/arm/mach-socfpga/include/mach/clock.h | 11 + > arch/arm/mach-socfpga/include/mach/debug-macro.S | 29 ++ > arch/arm/mach-socfpga/include/mach/dw_apb_timer.h | 38 +++ > arch/arm/mach-socfpga/include/mach/io.h | 27 ++ > arch/arm/mach-socfpga/include/mach/iomap.h | 37 +++ > arch/arm/mach-socfpga/include/mach/irqs.h | 305 ++++++++++++++++++++ > arch/arm/mach-socfpga/include/mach/memory.h | 32 ++ > arch/arm/mach-socfpga/include/mach/smp.h | 15 + > arch/arm/mach-socfpga/include/mach/socfpga-timer.h | 27 ++ > arch/arm/mach-socfpga/include/mach/system.h | 31 ++ > arch/arm/mach-socfpga/include/mach/timex.h | 19 ++ > arch/arm/mach-socfpga/include/mach/uncompress.h | 44 +++ > arch/arm/mach-socfpga/localtimer.c | 34 +++ > arch/arm/mach-socfpga/platsmp.c | 154 ++++++++++ > arch/arm/mm/Kconfig | 2 +- > 27 files changed, 1435 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/mach-socfpga/Kconfig > create mode 100644 arch/arm/mach-socfpga/Makefile > create mode 100644 arch/arm/mach-socfpga/Makefile.boot > create mode 100644 arch/arm/mach-socfpga/clock.c > create mode 100644 arch/arm/mach-socfpga/common.c > create mode 100644 arch/arm/mach-socfpga/common.h > create mode 100644 arch/arm/mach-socfpga/dw_apb_timer.c > create mode 100644 arch/arm/mach-socfpga/headsmp.S > create mode 100644 arch/arm/mach-socfpga/hotplug.c > create mode 100644 arch/arm/mach-socfpga/include/mach/clock.h > create mode 100644 arch/arm/mach-socfpga/include/mach/debug-macro.S > create mode 100644 arch/arm/mach-socfpga/include/mach/dw_apb_timer.h > create mode 100644 arch/arm/mach-socfpga/include/mach/io.h > create mode 100644 arch/arm/mach-socfpga/include/mach/iomap.h > create mode 100644 arch/arm/mach-socfpga/include/mach/irqs.h > create mode 100644 arch/arm/mach-socfpga/include/mach/memory.h > create mode 100644 arch/arm/mach-socfpga/include/mach/smp.h > create mode 100644 arch/arm/mach-socfpga/include/mach/socfpga-timer.h > create mode 100644 arch/arm/mach-socfpga/include/mach/system.h > create mode 100644 arch/arm/mach-socfpga/include/mach/timex.h > create mode 100644 arch/arm/mach-socfpga/include/mach/uncompress.h > create mode 100644 arch/arm/mach-socfpga/localtimer.c > create mode 100644 arch/arm/mach-socfpga/platsmp.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index eb22272..193b4e4 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1103,6 +1103,11 @@ S: Supported > F: arch/arm/mach-shmobile/ > F: drivers/sh/ > > +ARM/SOCFPGA ARCHITECTURE > +M: Dinh Nguyen <dinguyen@altera.com> > +S: Supported > +F: arch/arm/mach-socfpga/ > + > ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT > M: Lennert Buytenhek <kernel@wantstofly.org> > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index a91009c..b1578e1 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -250,6 +250,22 @@ choice > prompt "ARM system type" > default ARCH_VERSATILE > > +config ARCH_SOCFPGA > + bool "Altera SOCFPGA family" > + select CPU_V7 > + select ARM_GIC > + select ARM_AMBA > + select CLKDEV_LOOKUP > + select MIGHT_HAVE_CACHE_L2X0 > + select HAVE_MACH_CLKDEV > + select GENERIC_CLOCKEVENTS > + select ARCH_WANT_OPTIONAL_GPIOLIB > + select GPIO_PL061 if GPIOLIB > + select NEED_MACH_MEMORY_H > + select USE_OF Alphabetize the selects. > + help > + This enables support for Altera SOCFPGA Cyclone V platform > + > config ARCH_INTEGRATOR > bool "ARM Ltd. Integrator family" > select ARM_AMBA > @@ -1056,6 +1072,8 @@ source "arch/arm/mach-sa1100/Kconfig" > source "arch/arm/plat-samsung/Kconfig" > source "arch/arm/plat-s3c24xx/Kconfig" > > +source "arch/arm/mach-socfpga/Kconfig" > + > source "arch/arm/plat-spear/Kconfig" > > source "arch/arm/mach-s3c24xx/Kconfig" > @@ -1596,6 +1614,7 @@ config HZ > default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER > default AT91_TIMER_HZ if ARCH_AT91 > default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE > + default SOCFPGA_TIMER_HZ if ARCH_SOCFPGA Is this really needed? > default 100 > > config THUMB2_KERNEL > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > index 0298b00..1fe5702 100644 > --- a/arch/arm/Makefile > +++ b/arch/arm/Makefile > @@ -193,6 +193,7 @@ machine-$(CONFIG_MACH_SPEAR310) := spear3xx > machine-$(CONFIG_MACH_SPEAR320) := spear3xx > machine-$(CONFIG_MACH_SPEAR600) := spear6xx > machine-$(CONFIG_ARCH_ZYNQ) := zynq > +machine-$(CONFIG_ARCH_SOCFPGA) := socfpga > > # Platform directory name. This list is sorted alphanumerically > # by CONFIG_* macro name. > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig > new file mode 100644 > index 0000000..3fbbd0a > --- /dev/null > +++ b/arch/arm/mach-socfpga/Kconfig > @@ -0,0 +1,21 @@ > +choice > + prompt "Altera SOCFPGA Platform" > + default MACH_SOCFPGA_CYCLONE5 > + depends on ARCH_SOCFPGA > + help > + Select SOCFPGA platform type > + > +config MACH_SOCFPGA_CYCLONE5 > + bool "SOCFPGA Cyclone5 platform" > + select HAVE_SMP > + select PLAT_SOCFPGA_ETH > + help > + Include support for the Altera(R) Cyclone5 development platform. > +endchoice > + > +config SOCFPGA_TIMER_HZ > + int "Kernel internal timer frequency " > + range 20 1024 > + default "100" > + help > + Kernel internal timer frequency should be a divisor of 77161. > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > new file mode 100644 > index 0000000..5502add > --- /dev/null > +++ b/arch/arm/mach-socfpga/Makefile > @@ -0,0 +1,8 @@ > +# > +# Makefile for the linux kernel. > +# > + > +obj-y := common.o clock.o dw_apb_timer.o > +obj-$(CONFIG_MACH_SOCFPGA_CYCLONE5) += socfpga_cyclone5.o > +obj-$(CONFIG_SMP) += platsmp.o headsmp.o > +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o > \ No newline at end of file > diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot > new file mode 100644 > index 0000000..7a1f3c0 > --- /dev/null > +++ b/arch/arm/mach-socfpga/Makefile.boot > @@ -0,0 +1,3 @@ > +zreladdr-y := 0x00008000 > +params_phys-y := 0x00000100 > +initrd_phys-y := 0x00800000 > diff --git a/arch/arm/mach-socfpga/clock.c b/arch/arm/mach-socfpga/clock.c > new file mode 100644 > index 0000000..b5a82cd > --- /dev/null > +++ b/arch/arm/mach-socfpga/clock.c > @@ -0,0 +1,50 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * Copyright (C) 2004 ARM Limited. > + * Written by Deep Blue Solutions Limited. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#include <linux/module.h> > +#include <linux/kernel.h> > +#include <linux/errno.h> > +#include <linux/clk.h> > +#include <linux/mutex.h> > +#include <mach/clkdev.h> > + > +int clk_enable(struct clk *clk) > +{ > + return 0; > +} > +EXPORT_SYMBOL(clk_enable); > + > +void clk_disable(struct clk *clk) > +{ > +} > +EXPORT_SYMBOL(clk_disable); > + > +unsigned long clk_get_rate(struct clk *clk) > +{ > + return clk->rate; > +} > +EXPORT_SYMBOL(clk_get_rate); > + > +long clk_round_rate(struct clk *clk, unsigned long rate) > +{ > + long ret = -EIO; > + if (clk->ops && clk->ops->round) > + ret = clk->ops->round(clk, rate); > + return ret; > +} > +EXPORT_SYMBOL(clk_round_rate); > + > +int clk_set_rate(struct clk *clk, unsigned long rate) > +{ > + int ret = -EIO; > + if (clk->ops && clk->ops->set) > + ret = clk->ops->set(clk, rate); > + return ret; > +} > +EXPORT_SYMBOL(clk_set_rate); > diff --git a/arch/arm/mach-socfpga/common.c b/arch/arm/mach-socfpga/common.c > new file mode 100644 > index 0000000..a2c734a > --- /dev/null > +++ b/arch/arm/mach-socfpga/common.c > @@ -0,0 +1,156 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > +#include <linux/init.h> > +#include <linux/platform_device.h> > +#include <linux/device.h> > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/clkdev.h> > +#include <linux/gfp.h> > +#include <linux/of_platform.h> > + > +#include <mach/iomap.h> > +#include <mach/socfpga_cyclone5.h> > +#include <asm/irq.h> > +#include <asm/mach-types.h> > +#include <asm/hardware/arm_timer.h> > + > +#include <asm/mach/arch.h> > +#include <asm/mach/irq.h> > +#include <asm/mach/map.h> > + > +#include <mach/irqs.h> > +#include <mach/socfpga-timer.h> > + > +#include <linux/mmc/dw_mmc.h> > +#include <linux/serial_8250.h> > + > +#include "common.h" > + > +extern struct dw_mci_board sdmmc_platform_data; > +extern struct dma_pl330_platdata dma_platform_data; > + > +#define DW_APB_UART_OF_COMPATIBLE "snps,dw-apb-uart" > + > +#define SOCFPGA_MPU_PERIHCLK_FREQ_HZ (800000000 / 4) > +#define SOCFPGA_L4_MAIN_CLK (400000000) > + > +static struct clk dummy_apb_pclk; > +static struct clk dummy_i2c_clk = { > + .rate = 100000000, > +}; > +static struct clk dummy_spim_clk = { > + .rate = 100000000, > +}; > +static struct clk mpu_periphclk = { > + .rate = SOCFPGA_MPU_PERIHCLK_FREQ_HZ, > +}; > + > +static struct clk l4_main_clk = { > + .rate = SOCFPGA_L4_MAIN_CLK, > +}; > + > +static struct clk_lookup lookups[] = { > + { /* Bus clock */ > + .con_id = "apb_pclk", > + .clk = &dummy_apb_pclk, > + }, > + { > + .dev_id = "ffc04000.i2c", > + .clk = &dummy_i2c_clk, > + }, > + { > + .dev_id = "ffc05000.i2c", > + .clk = &dummy_i2c_clk, > + }, > + { > + .dev_id = "dw-spi-mmio.0", > + .clk = &dummy_spim_clk, > + }, > + { > + .dev_id = "dw-spi-mmio.1", > + .clk = &dummy_spim_clk, > + }, > + { > + .dev_id = "smp_twd", > + .clk = &mpu_periphclk, > + }, > + { > + .dev_id = "dma-pl330", > + .clk = &l4_main_clk, > + } > +}; > + > +struct plat_serial8250_port uart_platform_data[] = { > + { > + .type = PORT_16850, > + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | \ > + UPF_FIXED_TYPE, > + }, > +}; > + > +void __init socfpga_init_early(void) > +{ > + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); > +} > + > +/* > + * Where is the timer (VA)? > + */ > +void __iomem *sp_timer0_va_base; > +void __iomem *sp_timer1_va_base; > +void __iomem *osc_timer0_va_base; > +void __iomem *osc_timer1_va_base; > + > +/* > + * Set up the clock source and clock events devices > + */ > + > +void __init socfpga_timer_init(void __iomem *src_timer_base, > + void __iomem *event_timer_base, > + unsigned int event_timer_irq) > +{ > + /* > + * Initialise to a known state (all timers off) > + */ > + writel(0, sp_timer0_va_base + TIMER_CTRL); > + writel(0, sp_timer1_va_base + TIMER_CTRL); > + writel(0, osc_timer0_va_base + TIMER_CTRL); > + writel(0, osc_timer1_va_base + TIMER_CTRL); > + > + dwapbt_clocksource_init(src_timer_base); > + dwapbt_clockevents_init(event_timer_base, event_timer_irq); > +} > + > +/* > + * Setup the memory banks. > + */ > +void socfpga_fixup(struct tag *tags, char **from, struct meminfo *meminfo) > +{ > + meminfo->bank[0].start = 0x0; > + meminfo->bank[0].size = SZ_256M; > + meminfo->nr_banks = 1; > +} > + > +int socfpga_notifier(struct device *device) > +{ > + struct device_node *dn = device->of_node; > + > + if (of_device_is_compatible(dn, DW_APB_UART_OF_COMPATIBLE)) > + device->platform_data = &uart_platform_data; > + return 0; > +} > diff --git a/arch/arm/mach-socfpga/common.h b/arch/arm/mach-socfpga/common.h > new file mode 100644 > index 0000000..7cad4f1 > --- /dev/null > +++ b/arch/arm/mach-socfpga/common.h > @@ -0,0 +1,38 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef __ASM_ARCH_SOCFPGA_H > +#define __ASM_ARCH_SOCFPGA_H > + > +#include <asm/setup.h> > + > +struct machine_desc; > + > +extern void __iomem *sp_timer0_va_base; > +extern void __iomem *sp_timer1_va_base; > +extern void __iomem *osc_timer0_va_base; > +extern void __iomem *osc_timer1_va_base; > + > +extern void socfpga_init_early(void); > +extern void socfpga_fixup(struct tag *tags, char **from, > + struct meminfo *meminfo); > +extern void socfpga_timer_init(void __iomem *src_timer_base, > + void __iomem *event_timer_base, > + unsigned int event_timer_irq); > +extern int socfpga_notifier(struct device *device); > + > +#endif > diff --git a/arch/arm/mach-socfpga/dw_apb_timer.c b/arch/arm/mach-socfpga/dw_apb_timer.c > new file mode 100644 > index 0000000..64c8d96 > --- /dev/null > +++ b/arch/arm/mach-socfpga/dw_apb_timer.c > @@ -0,0 +1,164 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > +#include <linux/clocksource.h> > +#include <linux/clockchips.h> > +#include <linux/interrupt.h> > +#include <linux/irq.h> > +#include <linux/io.h> > + > +#include <mach/dw_apb_timer.h> > +#include <mach/socfpga-timer.h> > +#include <mach/iomap.h> > +#include <mach/clock.h> > + > +#define TIMER_SP_FREQ_KHZ (SOCFPGA_SP_TIMER_FREQ_HZ / 1000) > +#define TIMER_OSC_FREQ_KHZ (SOCFPGA_OSC_TIMER_FREQ_HZ / 1000) > + > +#define TIMER_RELOAD (TIMER_OSC_FREQ_KHZ * 1000 / HZ) > + > +static void __iomem *clksrc_base; > + > +static cycle_t dwapbt_read(struct clocksource *cs) > +{ > + return ~readl(clksrc_base + TIMER_VALUE); > +} > + > +static struct clocksource clocksource_dwapbt = { > + .name = "SP Timer 0", > + .rating = 200, > + .read = dwapbt_read, > + .mask = CLOCKSOURCE_MASK(32), > + .flags = CLOCK_SOURCE_IS_CONTINUOUS, > +}; > + > +void __init dwapbt_clocksource_init(void __iomem *base) > +{ > + struct clocksource *cs = &clocksource_dwapbt; > + > + clksrc_base = base; > + > + /* setup free-running clocksource */ > + writel(0, clksrc_base + TIMER_CTRL); > + writel(~0, clksrc_base + TIMER_LOAD); > + writel(TIMER_CTRL_INTMASK | TIMER_CTRL_ENABLE, > + clksrc_base + TIMER_CTRL); > + > + clocksource_register_khz(cs, TIMER_SP_FREQ_KHZ); > +} > + > + > +static void __iomem *clkevt_base; > + > +/* > + * IRQ handler for the timer > + */ > +static irqreturn_t dwapbt_timer_interrupt(int irq, void *dev_id) > +{ > + struct clock_event_device *evt = dev_id; > + > + /* clear the interrupt */ > + readl(clkevt_base + TIMER_INT_CLEAR); > + > + /* Ooppss... spurious interrupt */ > + if (unlikely(!evt->event_handler)) > + return IRQ_NONE; > + > + evt->event_handler(evt); > + > + return IRQ_HANDLED; > +} > + > +static void dwapbt_set_mode(enum clock_event_mode mode, > + struct clock_event_device *evt) > +{ > + unsigned long ctrl = 0; > + > + ctrl = readl(clkevt_base + TIMER_CTRL); > + > + /* Reset control register and disable the timer */ > + writel(0, clkevt_base + TIMER_CTRL); > + > + switch (mode) { > + case CLOCK_EVT_MODE_PERIODIC: > + /* Program load register */ > + writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD); > + > + ctrl |= TIMER_CTRL_ENABLE; > + ctrl |= TIMER_CTRL_PERIODIC; > + ctrl &= ~TIMER_CTRL_INTMASK; > + writel(ctrl, clkevt_base + TIMER_CTRL); > + break; > + > + case CLOCK_EVT_MODE_ONESHOT: > + /* period set, and timer enabled in 'next_event' hook */ > + ctrl &= ~TIMER_CTRL_PERIODIC; > + ctrl &= ~TIMER_CTRL_INTMASK; > + writel(ctrl, clkevt_base + TIMER_CTRL); > + break; > + > + case CLOCK_EVT_MODE_UNUSED: > + case CLOCK_EVT_MODE_SHUTDOWN: > + default: > + break; > + } > +} > + > +static int dwapbt_set_next_event(unsigned long next, > + struct clock_event_device *evt) > +{ > + unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); > + > + /* Disable timer */ > + writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); > + > + writel(next, clkevt_base + TIMER_LOAD); > + writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); > + > + return 0; > +} > + > +static struct clock_event_device dwapbt_clockevent = { > + .name = "OSC Timer 0", > + .shift = 32, > + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, > + .set_mode = dwapbt_set_mode, > + .set_next_event = dwapbt_set_next_event, > + .rating = 250, > + .cpumask = cpu_all_mask, > +}; > + > +static struct irqaction dwapbt_timer_irq = { > + .name = "timer", > + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, > + .handler = dwapbt_timer_interrupt, > + .dev_id = &dwapbt_clockevent, > +}; > + > +void __init dwapbt_clockevents_init(void __iomem *base, unsigned int timer_irq) > +{ > + struct clock_event_device *evt = &dwapbt_clockevent; > + > + clkevt_base = base; > + > + evt->irq = timer_irq; > + evt->mult = div_sc(TIMER_OSC_FREQ_KHZ, NSEC_PER_MSEC, evt->shift); > + evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); > + evt->min_delta_ns = clockevent_delta2ns(0xf, evt); > + > + setup_irq(timer_irq, &dwapbt_timer_irq); > + clockevents_register_device(evt); > +} > diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S > new file mode 100644 > index 0000000..e432aec > --- /dev/null > +++ b/arch/arm/mach-socfpga/headsmp.S > @@ -0,0 +1,41 @@ > +/* > + * Modified from: linux/arch/arm/plat-versatile/headsmp.S > + * > + * Copyright (c) 2003 ARM Limited > + * All Rights Reserved > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#include <linux/linkage.h> > +#include <linux/init.h> > + > + __INIT > + > +/* > + * Entry point for secondary CPUs. > + * This provides a "holding pen" into which all secondary cores are held > + * until we're ready for them to initialise. > + */ > +ENTRY(socfpga_secondary_startup) > + mrc p15, 0, r0, c0, c0, 5 > + and r0, r0, #15 > + adr r4, 1f > + ldmia r4, {r5, r6} > + sub r4, r4, r5 > + add r6, r6, r4 > +pen: ldr r7, [r6] > + cmp r7, r0 > + bne pen > + > + /* > + * we've been released from the holding pen: secondary_stack > + * should now contain the SVC stack for this core > + */ > + b secondary_startup > + > + .align > +1: .long . > + .long pen_release > +ENDPROC(socfpga_secondary_startup) > diff --git a/arch/arm/mach-socfpga/hotplug.c b/arch/arm/mach-socfpga/hotplug.c > new file mode 100644 > index 0000000..f9fc9ff > --- /dev/null > +++ b/arch/arm/mach-socfpga/hotplug.c > @@ -0,0 +1,125 @@ > +/* > + * Copyright (C) 2002 ARM Ltd. > + * All Rights Reserved > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#include <linux/kernel.h> > +#include <linux/errno.h> > +#include <linux/smp.h> > + > +#include <asm/cacheflush.h> > +#include <asm/cp15.h> > +#include <asm/smp_plat.h> > + > +extern int pen_release; > + > +static inline void cpu_enter_lowpower(void) > +{ > + unsigned int v; > + > + flush_cache_all(); > + asm volatile( > + " mcr p15, 0, %1, c7, c5, 0\n" > + " mcr p15, 0, %1, c7, c10, 4\n" > + /* > + * Turn off coherency > + */ > + " mrc p15, 0, %0, c1, c0, 1\n" > + " bic %0, %0, #0x20\n" > + " mcr p15, 0, %0, c1, c0, 1\n" > + " mrc p15, 0, %0, c1, c0, 0\n" > + " bic %0, %0, %2\n" > + " mcr p15, 0, %0, c1, c0, 0\n" > + : "=&r" (v) > + : "r" (0), "Ir" (CR_C) > + : "cc"); > +} > + > +static inline void cpu_leave_lowpower(void) > +{ > + unsigned int v; > + > + asm volatile("mrc p15, 0, %0, c1, c0, 0\n" > + " orr %0, %0, %1\n" > + " mcr p15, 0, %0, c1, c0, 0\n" > + " mrc p15, 0, %0, c1, c0, 1\n" > + " orr %0, %0, #0x20\n" > + " mcr p15, 0, %0, c1, c0, 1\n" > + : "=&r" (v) > + : "Ir" (CR_C) > + : "cc"); > +} > + > +static inline void platform_do_lowpower(unsigned int cpu, int *spurious) > +{ > + /* > + * there is no power-control hardware on this platform, so all > + * we can do is put the core into WFI; this is safe as the calling > + * code will have already disabled interrupts Is this true or just copied from ARM Ltd platforms? > + */ > + for (;;) { > + /* > + * here's the WFI > + */ > + asm volatile(".word 0xe320f003\n" > + : : : "memory", "cc"); > + > + if (pen_release == cpu_logical_map(cpu)) { > + /* > + * OK, proper wakeup, we're done > + */ > + break; > + } > + > + /* > + * Getting here, means that we have come out of WFI without > + * having been woken up - this shouldn't happen > + * > + * Just note it happening - when we're woken, we can report > + * its occurrence. > + */ > + (*spurious)++; > + } > +} > + > +int platform_cpu_kill(unsigned int cpu) > +{ > + return 1; > +} > + > +/* > + * platform-specific code to shutdown a CPU > + * > + * Called with IRQs disabled > + */ > +void platform_cpu_die(unsigned int cpu) > +{ > + int spurious = 0; > + > + /* > + * we're ready for shutdown now, so do it > + */ > + cpu_enter_lowpower(); > + platform_do_lowpower(cpu, &spurious); > + > + /* > + * bring this CPU back into the world of cache > + * coherency, and then restore interrupts > + */ > + cpu_leave_lowpower(); > + > + if (spurious) > + pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); > +} > + > +int platform_cpu_disable(unsigned int cpu) > +{ > + /* > + * we don't allow CPU 0 to be shutdown (it is still too special > + * e.g. clock tick interrupts) > + */ > + return cpu == 0 ? -EPERM : 0; > +} > diff --git a/arch/arm/mach-socfpga/include/mach/clock.h b/arch/arm/mach-socfpga/include/mach/clock.h > new file mode 100644 > index 0000000..5187064 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/clock.h > @@ -0,0 +1,11 @@ > +#ifndef __MACH_CLOCK_H > +#define __MACH_CLOCK_H > + > +struct clk; > + > +struct clk_ops { > + long (*round)(struct clk *, unsigned long); > + int (*set)(struct clk *, unsigned long); > +}; Use common clk infrastructure. > + > +#endif > diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/mach-socfpga/include/mach/debug-macro.S > new file mode 100644 > index 0000000..d6283f5 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/debug-macro.S > @@ -0,0 +1,29 @@ > +/* > + * Copyright (C) 1994-1999 Russell King > + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#ifndef DEBUG_LL_UART_OFFSET > +#define DEBUG_LL_UART_OFFSET 0x00002000 > +#elif DEBUG_LL_UART_OFFSET != 0x00002000 > +#warning "DEBUG_LL_UART_OFFSET already defined to a different value" > +#endif > + > +#ifndef DEBUG_LL_UART_OFFSET > +#error "Unknown SOCFPGA platform" > +#endif > + > + .macro addruart, rp, rv, tmp > + mov \rp, #DEBUG_LL_UART_OFFSET > + orr \rp, \rp, #0x00c00000 > + orr \rv, \rp, #0xfe000000 @ virtual base > + orr \rp, \rp, #0xff000000 @ physical base > + .endm > + > +#define UART_SHIFT 2 > + > +#include <asm/hardware/debug-8250.S> > diff --git a/arch/arm/mach-socfpga/include/mach/dw_apb_timer.h b/arch/arm/mach-socfpga/include/mach/dw_apb_timer.h > new file mode 100644 > index 0000000..3c58a56 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/dw_apb_timer.h > @@ -0,0 +1,38 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > + > +#ifndef __ASM_ARM_HARDWARE_DW_APB_TIMER_H > +#define __ASM_ARM_HARDWARE_DW_APB_TIMER_H > + > +/* Individual timer register */ > +#define TIMER_LOAD 0x00 /* Load value rw */ > +#define TIMER_VALUE 0x04 /* Current value ro */ > +#define TIMER_CTRL 0x08 /* Control register rw */ > +#define TIMER_INT_CLEAR 0x0c /* Interrupt clear ro */ > +#define TIMER_INT_STAT 0x10 /* Interrupt status ro */ > + > +/* Shared timer register */ > +#define TIMERS_INT_STAT 0xa0 /* Masked interrupt status ro */ > +#define TIMERS_INT_CLEAR 0xa4 /* Interrupt clear ro */ > +#define TIMERS_INT_STAT_RAW 0xa8 /* Raw interrupt status ro */ > +#define TIMERS_VERSION 0xac /* Version */ > + > +#define TIMER_CTRL_ENABLE (1 << 0) /* Timer Enable = 1 */ > +#define TIMER_CTRL_PERIODIC (1 << 1) /* Periodic mode = 0 */ > +#define TIMER_CTRL_INTMASK (1 << 2) /* Interrupt mask = 1 */ > + > +#endif > diff --git a/arch/arm/mach-socfpga/include/mach/io.h b/arch/arm/mach-socfpga/include/mach/io.h > new file mode 100644 > index 0000000..ff150b0 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/io.h > @@ -0,0 +1,27 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * Copyright (C) 2003 ARM Limited > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + */ > +#ifndef __MACH_ARCH_IO_H > +#define __MACH_ARCH_IO_H > + > +#define IO_SPACE_LIMIT 0xffffffff > + > +#define __io(a) __typesafe_io(a) > +#define __mem_pci(a) (a) You don't need io.h, remove it. > + > +#endif > diff --git a/arch/arm/mach-socfpga/include/mach/iomap.h b/arch/arm/mach-socfpga/include/mach/iomap.h > new file mode 100644 > index 0000000..656482d > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/iomap.h > @@ -0,0 +1,37 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > +#ifndef __MACH_SOCFPGA_IOMAP_H > +#define __MACH_SOCFPGA_IOMAP_H > + > +#include <asm/sizes.h> > + > +/* macro to get at IO space when running virtually */ > +#ifdef CONFIG_MMU Do you really support !MMU? > +/* > + * Statically mapped addresses: > + * > + * 10xx xxxx -> fbxx xxxx > + * 1exx xxxx -> fdxx xxxx > + * 1fxx xxxx -> fexx xxxx > + */ > +#define IO_ADDRESS(x) (((x) & 0x03ffffff) + 0xfb000000) > +#else > +#define IO_ADDRESS(x) (x) > +#endif > +#define __io_address(n) IOMEM(IO_ADDRESS(n)) > + > +#endif > \ No newline at end of file > diff --git a/arch/arm/mach-socfpga/include/mach/irqs.h b/arch/arm/mach-socfpga/include/mach/irqs.h > new file mode 100644 > index 0000000..65db73a > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/irqs.h > @@ -0,0 +1,305 @@ > +/* > + * Copyright (C) 2012 Altera Corporation > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > +*/ > + > +#ifndef __MACH_IRQS_H > +#define __MACH_IRQS_H > + > +#define IRQ_SOCFPGA_GIC_START 32 > +#define IRQ_LOCALWDOG 30 > + > + > +/* > + * SOCFPGA interrupt sources > + */ > +#define IRQ_SOCFPGA_CPU0_PARITY (IRQ_SOCFPGA_GIC_START + 0) /* CPU0 parity */ > +#define IRQ_SOCFPGA_CPU0_PARITY_BTAG (IRQ_SOCFPGA_GIC_START + 1) /* CPU0 parity BTAG */ > +#define IRQ_SOCFPGA_CPU0_PARITY_GHB (IRQ_SOCFPGA_GIC_START + 2) /* CPU0 parity GHB */ > +#define IRQ_SOCFPGA_CPU0_PARITY_ITAG (IRQ_SOCFPGA_GIC_START + 3) /* CPU0 parity ITAG */ > +#define IRQ_SOCFPGA_CPU0_PARITY_IDATA (IRQ_SOCFPGA_GIC_START + 4) /* CPU0 parity IDATA */ > +#define IRQ_SOCFPGA_CPU0_PARITY_TLB (IRQ_SOCFPGA_GIC_START + 5) /* CPU0 parity TLB */ > +#define IRQ_SOCFPGA_CPU0_PARITY_DOUTER (IRQ_SOCFPGA_GIC_START + 6) /* CPU0 parity DOUTER */ > +#define IRQ_SOCFPGA_CPU0_PARITY_DTAG (IRQ_SOCFPGA_GIC_START + 7) /* CPU0 parity DTAG */ > +#define IRQ_SOCFPGA_CPU0_PARITY_DDATA (IRQ_SOCFPGA_GIC_START + 8) /* CPU0 parity DDATA */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS0 (IRQ_SOCFPGA_GIC_START + 9) /* CPU0 deflasg 0 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS1 (IRQ_SOCFPGA_GIC_START + 10) /* CPU0 deflags 1 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS2 (IRQ_SOCFPGA_GIC_START + 11) /* CPU0 deflags 2 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS3 (IRQ_SOCFPGA_GIC_START + 12) /* CPU0 deflags 3 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS4 (IRQ_SOCFPGA_GIC_START + 13) /* CPU0 deflags 4 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS5 (IRQ_SOCFPGA_GIC_START + 14) /* CPU0 deflags 5 */ > +#define IRQ_SOCFPGA_CPU0_DEFLAGS6 (IRQ_SOCFPGA_GIC_START + 15) /* CPU0 deflags 6 */ > +#define IRQ_SOCFPGA_CPU1_PARITY (IRQ_SOCFPGA_GIC_START + 16) /* CPU1 parity */ > +#define IRQ_SOCFPGA_CPU1_PARITY_BTAG (IRQ_SOCFPGA_GIC_START + 17) /* CPU1 parity BTAG */ > +#define IRQ_SOCFPGA_CPU1_PARITY_GHB (IRQ_SOCFPGA_GIC_START + 18) /* CPU1 parity GHB */ > +#define IRQ_SOCFPGA_CPU1_PARITY_ITAG (IRQ_SOCFPGA_GIC_START + 19) /* CPU1 parity ITAG */ > +#define IRQ_SOCFPGA_CPU1_PARITY_IDATA (IRQ_SOCFPGA_GIC_START + 20) /* CPU1 parity IDATA */ > +#define IRQ_SOCFPGA_CPU1_PARITY_TLB (IRQ_SOCFPGA_GIC_START + 21) /* CPU1 parity TLB */ > +#define IRQ_SOCFPGA_CPU1_PARITY_DOUTER (IRQ_SOCFPGA_GIC_START + 22) /* CPU1 parity DOUTER */ > +#define IRQ_SOCFPGA_CPU1_PARITY_DTAG (IRQ_SOCFPGA_GIC_START + 23) /* CPU1 parity DTAG */ > +#define IRQ_SOCFPGA_CPU1_PARITY_DDATA (IRQ_SOCFPGA_GIC_START + 24) /* CPU1 parity DDATA */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS0 (IRQ_SOCFPGA_GIC_START + 25) /* CPU1 deflags 0 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS1 (IRQ_SOCFPGA_GIC_START + 26) /* CPU1 deflags 1 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS2 (IRQ_SOCFPGA_GIC_START + 27) /* CPU1 deflags 2 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS3 (IRQ_SOCFPGA_GIC_START + 28) /* CPU1 deflags 3 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS4 (IRQ_SOCFPGA_GIC_START + 29) /* CPU1 deflags 4 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS5 (IRQ_SOCFPGA_GIC_START + 30) /* CPU1 deflags 5 */ > +#define IRQ_SOCFPGA_CPU1_DEFLAGS6 (IRQ_SOCFPGA_GIC_START + 31) /* CPU1 deflags 6 */ > +#define IRQ_SOCFPGA_SCU0_PARITY (IRQ_SOCFPGA_GIC_START + 32) /* SCU0 parity */ > +#define IRQ_SOCFPGA_SCU1_PARITY (IRQ_SOCFPGA_GIC_START + 33) /* SCU1 parity */ > +#define IRQ_SOCFPGA_SCU_EV_ABORT (IRQ_SOCFPGA_GIC_START + 34) /* SCU EV abort */ > +#define IRQ_SOCFPGA_L2_ECC_WRITE (IRQ_SOCFPGA_GIC_START + 35) /* L2 ECC write */ > +#define IRQ_SOCFPGA_L2_ECC_CERR (IRQ_SOCFPGA_GIC_START + 36) /* L2 ECC error corrected */ > +#define IRQ_SOCFPGA_L2_ECC_UERR (IRQ_SOCFPGA_GIC_START + 37) /* L2 ECC error uncorrected */ > +#define IRQ_SOCFPGA_L2 (IRQ_SOCFPGA_GIC_START + 38) /* L2 combined interrupts */ > +#define IRQ_SOCFPGA_DDR_ECC_ERR (IRQ_SOCFPGA_GIC_START + 39) /* DDR ECC error */ > +#define IRQ_SOCFPGA_F2S_FPGA0 (IRQ_SOCFPGA_GIC_START + 40) /* FPGA IRQ 0 */ > +#define IRQ_SOCFPGA_F2S_FPGA1 (IRQ_SOCFPGA_GIC_START + 41) /* FPGA IRQ 1 */ > +#define IRQ_SOCFPGA_F2S_FPGA2 (IRQ_SOCFPGA_GIC_START + 42) /* FPGA IRQ 2 */ > +#define IRQ_SOCFPGA_F2S_FPGA3 (IRQ_SOCFPGA_GIC_START + 43) /* FPGA IRQ 3 */ > +#define IRQ_SOCFPGA_F2S_FPGA4 (IRQ_SOCFPGA_GIC_START + 44) /* FPGA IRQ 4 */ > +#define IRQ_SOCFPGA_F2S_FPGA5 (IRQ_SOCFPGA_GIC_START + 45) /* FPGA IRQ 5 */ > +#define IRQ_SOCFPGA_F2S_FPGA6 (IRQ_SOCFPGA_GIC_START + 46) /* FPGA IRQ 6 */ > +#define IRQ_SOCFPGA_F2S_FPGA7 (IRQ_SOCFPGA_GIC_START + 47) /* FPGA IRQ 7 */ > +#define IRQ_SOCFPGA_F2S_FPGA8 (IRQ_SOCFPGA_GIC_START + 48) /* FPGA IRQ 8 */ > +#define IRQ_SOCFPGA_F2S_FPGA9 (IRQ_SOCFPGA_GIC_START + 49) /* FPGA IRQ 9 */ > +#define IRQ_SOCFPGA_F2S_FPGA10 (IRQ_SOCFPGA_GIC_START + 50) /* FPGA IRQ 10 */ > +#define IRQ_SOCFPGA_F2S_FPGA11 (IRQ_SOCFPGA_GIC_START + 51) /* FPGA IRQ 11 */ > +#define IRQ_SOCFPGA_F2S_FPGA12 (IRQ_SOCFPGA_GIC_START + 52) /* FPGA IRQ 12 */ > +#define IRQ_SOCFPGA_F2S_FPGA13 (IRQ_SOCFPGA_GIC_START + 53) /* FPGA IRQ 13 */ > +#define IRQ_SOCFPGA_F2S_FPGA14 (IRQ_SOCFPGA_GIC_START + 54) /* FPGA IRQ 14 */ > +#define IRQ_SOCFPGA_F2S_FPGA15 (IRQ_SOCFPGA_GIC_START + 55) /* FPGA IRQ 15 */ > +#define IRQ_SOCFPGA_F2S_FPGA16 (IRQ_SOCFPGA_GIC_START + 56) /* FPGA IRQ 16 */ > +#define IRQ_SOCFPGA_F2S_FPGA17 (IRQ_SOCFPGA_GIC_START + 57) /* FPGA IRQ 17 */ > +#define IRQ_SOCFPGA_F2S_FPGA18 (IRQ_SOCFPGA_GIC_START + 58) /* FPGA IRQ 18 */ > +#define IRQ_SOCFPGA_F2S_FPGA19 (IRQ_SOCFPGA_GIC_START + 59) /* FPGA IRQ 19 */ > +#define IRQ_SOCFPGA_F2S_FPGA20 (IRQ_SOCFPGA_GIC_START + 60) /* FPGA IRQ 20 */ > +#define IRQ_SOCFPGA_F2S_FPGA21 (IRQ_SOCFPGA_GIC_START + 61) /* FPGA IRQ 21 */ > +#define IRQ_SOCFPGA_F2S_FPGA22 (IRQ_SOCFPGA_GIC_START + 62) /* FPGA IRQ 22 */ > +#define IRQ_SOCFPGA_F2S_FPGA23 (IRQ_SOCFPGA_GIC_START + 63) /* FPGA IRQ 23 */ > +#define IRQ_SOCFPGA_F2S_FPGA24 (IRQ_SOCFPGA_GIC_START + 64) /* FPGA IRQ 24 */ > +#define IRQ_SOCFPGA_F2S_FPGA25 (IRQ_SOCFPGA_GIC_START + 65) /* FPGA IRQ 25 */ > +#define IRQ_SOCFPGA_F2S_FPGA26 (IRQ_SOCFPGA_GIC_START + 66) /* FPGA IRQ 26 */ > +#define IRQ_SOCFPGA_F2S_FPGA27 (IRQ_SOCFPGA_GIC_START + 67) /* FPGA IRQ 27 */ > +#define IRQ_SOCFPGA_F2S_FPGA28 (IRQ_SOCFPGA_GIC_START + 68) /* FPGA IRQ 28 */ > +#define IRQ_SOCFPGA_F2S_FPGA29 (IRQ_SOCFPGA_GIC_START + 69) /* FPGA IRQ 29 */ > +#define IRQ_SOCFPGA_F2S_FPGA30 (IRQ_SOCFPGA_GIC_START + 70) /* FPGA IRQ 30 */ > +#define IRQ_SOCFPGA_F2S_FPGA31 (IRQ_SOCFPGA_GIC_START + 71) /* FPGA IRQ 31 */ > +#define IRQ_SOCFPGA_F2S_FPGA32 (IRQ_SOCFPGA_GIC_START + 72) /* FPGA IRQ 32 */ > +#define IRQ_SOCFPGA_F2S_FPGA33 (IRQ_SOCFPGA_GIC_START + 73) /* FPGA IRQ 33 */ > +#define IRQ_SOCFPGA_F2S_FPGA34 (IRQ_SOCFPGA_GIC_START + 74) /* FPGA IRQ 34 */ > +#define IRQ_SOCFPGA_F2S_FPGA35 (IRQ_SOCFPGA_GIC_START + 75) /* FPGA IRQ 35 */ > +#define IRQ_SOCFPGA_F2S_FPGA36 (IRQ_SOCFPGA_GIC_START + 76) /* FPGA IRQ 36 */ > +#define IRQ_SOCFPGA_F2S_FPGA37 (IRQ_SOCFPGA_GIC_START + 77) /* FPGA IRQ 37 */ > +#define IRQ_SOCFPGA_F2S_FPGA38 (IRQ_SOCFPGA_GIC_START + 78) /* FPGA IRQ 38 */ > +#define IRQ_SOCFPGA_F2S_FPGA39 (IRQ_SOCFPGA_GIC_START + 79) /* FPGA IRQ 39 */ > +#define IRQ_SOCFPGA_F2S_FPGA40 (IRQ_SOCFPGA_GIC_START + 80) /* FPGA IRQ 40 */ > +#define IRQ_SOCFPGA_F2S_FPGA41 (IRQ_SOCFPGA_GIC_START + 81) /* FPGA IRQ 41 */ > +#define IRQ_SOCFPGA_F2S_FPGA42 (IRQ_SOCFPGA_GIC_START + 82) /* FPGA IRQ 42 */ > +#define IRQ_SOCFPGA_F2S_FPGA43 (IRQ_SOCFPGA_GIC_START + 83) /* FPGA IRQ 43 */ > +#define IRQ_SOCFPGA_F2S_FPGA44 (IRQ_SOCFPGA_GIC_START + 84) /* FPGA IRQ 44 */ > +#define IRQ_SOCFPGA_F2S_FPGA45 (IRQ_SOCFPGA_GIC_START + 85) /* FPGA IRQ 45 */ > +#define IRQ_SOCFPGA_F2S_FPGA46 (IRQ_SOCFPGA_GIC_START + 86) /* FPGA IRQ 46 */ > +#define IRQ_SOCFPGA_F2S_FPGA47 (IRQ_SOCFPGA_GIC_START + 87) /* FPGA IRQ 47 */ > +#define IRQ_SOCFPGA_F2S_FPGA48 (IRQ_SOCFPGA_GIC_START + 88) /* FPGA IRQ 48 */ > +#define IRQ_SOCFPGA_F2S_FPGA49 (IRQ_SOCFPGA_GIC_START + 89) /* FPGA IRQ 49 */ > +#define IRQ_SOCFPGA_F2S_FPGA50 (IRQ_SOCFPGA_GIC_START + 90) /* FPGA IRQ 50 */ > +#define IRQ_SOCFPGA_F2S_FPGA51 (IRQ_SOCFPGA_GIC_START + 91) /* FPGA IRQ 51 */ > +#define IRQ_SOCFPGA_F2S_FPGA52 (IRQ_SOCFPGA_GIC_START + 92) /* FPGA IRQ 52 */ > +#define IRQ_SOCFPGA_F2S_FPGA53 (IRQ_SOCFPGA_GIC_START + 93) /* FPGA IRQ 53 */ > +#define IRQ_SOCFPGA_F2S_FPGA54 (IRQ_SOCFPGA_GIC_START + 94) /* FPGA IRQ 54 */ > +#define IRQ_SOCFPGA_F2S_FPGA55 (IRQ_SOCFPGA_GIC_START + 95) /* FPGA IRQ 55 */ > +#define IRQ_SOCFPGA_F2S_FPGA56 (IRQ_SOCFPGA_GIC_START + 96) /* FPGA IRQ 56 */ > +#define IRQ_SOCFPGA_F2S_FPGA57 (IRQ_SOCFPGA_GIC_START + 97) /* FPGA IRQ 57 */ > +#define IRQ_SOCFPGA_F2S_FPGA58 (IRQ_SOCFPGA_GIC_START + 98) /* FPGA IRQ 58 */ > +#define IRQ_SOCFPGA_F2S_FPGA59 (IRQ_SOCFPGA_GIC_START + 99) /* FPGA IRQ 59 */ > +#define IRQ_SOCFPGA_F2S_FPGA60 (IRQ_SOCFPGA_GIC_START + 100) /* FPGA IRQ 60 */ > +#define IRQ_SOCFPGA_F2S_FPGA61 (IRQ_SOCFPGA_GIC_START + 101) /* FPGA IRQ 61 */ > +#define IRQ_SOCFPGA_F2S_FPGA62 (IRQ_SOCFPGA_GIC_START + 102) /* FPGA IRQ 62 */ > +#define IRQ_SOCFPGA_F2S_FPGA63 (IRQ_SOCFPGA_GIC_START + 103) /* FPGA IRQ 63 */ > +#define IRQ_SOCFPGA_DMA0 (IRQ_SOCFPGA_GIC_START + 104) /* DMA Channel 0 */ > +#define IRQ_SOCFPGA_DMA1 (IRQ_SOCFPGA_GIC_START + 105) /* DMA Channel 1 */ > +#define IRQ_SOCFPGA_DMA2 (IRQ_SOCFPGA_GIC_START + 106) /* DMA Channel 2 */ > +#define IRQ_SOCFPGA_DMA3 (IRQ_SOCFPGA_GIC_START + 107) /* DMA Channel 3 */ > +#define IRQ_SOCFPGA_DMA4 (IRQ_SOCFPGA_GIC_START + 108) /* DMA Channel 3 */ > +#define IRQ_SOCFPGA_DMA5 (IRQ_SOCFPGA_GIC_START + 109) /* DMA Channel 5 */ > +#define IRQ_SOCFPGA_DMA6 (IRQ_SOCFPGA_GIC_START + 110) /* DMA Channel 6 */ > +#define IRQ_SOCFPGA_DMA7 (IRQ_SOCFPGA_GIC_START + 111) /* DMA Channel 7 */ > +#define IRQ_SOCFPGA_DMA_ABORT (IRQ_SOCFPGA_GIC_START + 112) /* DMA abort */ > +#define IRQ_SOCFPGA_DMA_CECC (IRQ_SOCFPGA_GIC_START + 113) /* DMA ECC corrected */ > +#define IRQ_SOCFPGA_DMA_UECC (IRQ_SOCFPGA_GIC_START + 114) /* DMA ECC uncorrected */ > +#define IRQ_SOCFPGA_EMAC0 (IRQ_SOCFPGA_GIC_START + 115) /* Gb-Ethernet MAC0 */ > +#define IRQ_SOCFPGA_EMAC0_TX_CECC (IRQ_SOCFPGA_GIC_START + 116) /* Gb-Ethernet MAC0 ECC corrected */ > +#define IRQ_SOCFPGA_EMAC0_TX_UECC (IRQ_SOCFPGA_GIC_START + 117) /* Gb-Ethernet MAC0 ECC uncorrected */ > +#define IRQ_SOCFPGA_EMAC0_RX_CECC (IRQ_SOCFPGA_GIC_START + 118) /* Gb-Ethernet MAC0 ECC corrected */ > +#define IRQ_SOCFPGA_EMAC0_RX_UECC (IRQ_SOCFPGA_GIC_START + 119) /* Gb-Ethernet MAC0 ECC uncorrected */ > +#define IRQ_SOCFPGA_EMAC1 (IRQ_SOCFPGA_GIC_START + 120) /* Gb-Ethernet MAC1 */ > +#define IRQ_SOCFPGA_EMAC1_TX_CECC (IRQ_SOCFPGA_GIC_START + 121) /* Gb-Ethernet MAC1 ECC corrected */ > +#define IRQ_SOCFPGA_EMAC1_TX_UECC (IRQ_SOCFPGA_GIC_START + 122) /* Gb-Ethernet MAC1 ECC uncorrected */ > +#define IRQ_SOCFPGA_EMAC1_RX_CECC (IRQ_SOCFPGA_GIC_START + 123) /* Gb-Ethernet MAC1 ECC corrected */ > +#define IRQ_SOCFPGA_EMAC1_RX_UECC (IRQ_SOCFPGA_GIC_START + 124) /* Gb-Ethernet MAC1 ECC uncorrected */ > +#define IRQ_SOCFPGA_USB0 (IRQ_SOCFPGA_GIC_START + 125) /* USB 0 generic */ > +#define IRQ_SOCFPGA_USB0_CECC (IRQ_SOCFPGA_GIC_START + 126) /* USB 0 ECC corrected */ > +#define IRQ_SOCFPGA_USB0_UECC (IRQ_SOCFPGA_GIC_START + 127) /* USB 0 ECC uncorrected */ > +#define IRQ_SOCFPGA_USB1 (IRQ_SOCFPGA_GIC_START + 128) /* USB 1 generic */ > +#define IRQ_SOCFPGA_USB1_CECC (IRQ_SOCFPGA_GIC_START + 129) /* USB 1 ECC corrected */ > +#define IRQ_SOCFPGA_USB1_UECC (IRQ_SOCFPGA_GIC_START + 130) /* USB 1 ECC uncorrected */ > +#define IRQ_SOCFPGA_CAN0_STS (IRQ_SOCFPGA_GIC_START + 131) /* CAN0 interrupt 0 */ > +#define IRQ_SOCFPGA_CAN0_MO (IRQ_SOCFPGA_GIC_START + 132) /* CAN0 interrupt 1 */ > +#define IRQ_SOCFPGA_CAN0_CECC (IRQ_SOCFPGA_GIC_START + 133) /* CAN0 ECC corrected */ > +#define IRQ_SOCFPGA_CAN0_UECC (IRQ_SOCFPGA_GIC_START + 134) /* CAN0 ECC uncorrected */ > +#define IRQ_SOCFPGA_CAN1_STS (IRQ_SOCFPGA_GIC_START + 135) /* CAN1 interrupt 0 */ > +#define IRQ_SOCFPGA_CAN1_MO (IRQ_SOCFPGA_GIC_START + 136) /* CAN1 interrupt 1 */ > +#define IRQ_SOCFPGA_CAN1_CECC (IRQ_SOCFPGA_GIC_START + 137) /* CAN1 ECC corrected */ > +#define IRQ_SOCFPGA_CAN1_UECC (IRQ_SOCFPGA_GIC_START + 138) /* CAN1 ECC uncorrected */ > +#define IRQ_SOCFPGA_SDMMC (IRQ_SOCFPGA_GIC_START + 139) /* SD/MMC */ > +#define IRQ_SOCFPGA_SDMMC_PA_CECC (IRQ_SOCFPGA_GIC_START + 140) /* SD/MMC PortA ECC corrected */ > +#define IRQ_SOCFPGA_SDMMC_PA_UECC (IRQ_SOCFPGA_GIC_START + 141) /* SD/MMC PortA ECC uncorrected */ > +#define IRQ_SOCFPGA_SDMMC_PB_CECC (IRQ_SOCFPGA_GIC_START + 142) /* SD/MMC PortB ECC corrected */ > +#define IRQ_SOCFPGA_SDMMC_PB_UECC (IRQ_SOCFPGA_GIC_START + 143) /* SD/MMC PortB ECC uncorrected */ > +#define IRQ_SOCFPGA_NAND (IRQ_SOCFPGA_GIC_START + 144) /* NAND */ > +#define IRQ_SOCFPGA_NAND_R_CECC (IRQ_SOCFPGA_GIC_START + 145) /* NAND read ECC corrected */ > +#define IRQ_SOCFPGA_NAND_R_UECC (IRQ_SOCFPGA_GIC_START + 146) /* NAND read ECC uncorrected */ > +#define IRQ_SOCFPGA_NAND_W_CECC (IRQ_SOCFPGA_GIC_START + 147) /* NAND write ECC corrected */ > +#define IRQ_SOCFPGA_NAND_W_UECC (IRQ_SOCFPGA_GIC_START + 148) /* NAND write ECC uncorrected */ > +#define IRQ_SOCFPGA_NAND_E_CECC (IRQ_SOCFPGA_GIC_START + 149) /* NAND error ECC corrected */ > +#define IRQ_SOCFPGA_NAND_E_UECC (IRQ_SOCFPGA_GIC_START + 150) /* NAND error ECC uncorrected */ > +#define IRQ_SOCFPGA_QSPI (IRQ_SOCFPGA_GIC_START + 151) /* Quad-SPI */ > +#define IRQ_SOCFPGA_QSPI_CECC (IRQ_SOCFPGA_GIC_START + 152) /* Quad-SPI ECC corrected */ > +#define IRQ_SOCFPGA_QSPI_UECC (IRQ_SOCFPGA_GIC_START + 153) /* Quad-SPI ECC uncorrected */ > +#define IRQ_SOCFPGA_SPI0 (IRQ_SOCFPGA_GIC_START + 154) /* SPI 0 */ > +#define IRQ_SOCFPGA_SPI1 (IRQ_SOCFPGA_GIC_START + 155) /* SPI 1 */ > +#define IRQ_SOCFPGA_SPI2 (IRQ_SOCFPGA_GIC_START + 156) /* SPI 2 */ > +#define IRQ_SOCFPGA_SPI3 (IRQ_SOCFPGA_GIC_START + 157) /* SPI 3 */ > +#define IRQ_SOCFPGA_I2C0 (IRQ_SOCFPGA_GIC_START + 158) /* I2C 0 */ > +#define IRQ_SOCFPGA_I2C1 (IRQ_SOCFPGA_GIC_START + 159) /* I2C 1 */ > +#define IRQ_SOCFPGA_I2C2 (IRQ_SOCFPGA_GIC_START + 160) /* I2C 2 */ > +#define IRQ_SOCFPGA_I2C3 (IRQ_SOCFPGA_GIC_START + 161) /* I2C 3 */ > +#define IRQ_SOCFPGA_UART0 (IRQ_SOCFPGA_GIC_START + 162) /* UART 0 */ > +#define IRQ_SOCFPGA_UART1 (IRQ_SOCFPGA_GIC_START + 163) /* UART 1 */ > +#define IRQ_SOCFPGA_GPIO0 (IRQ_SOCFPGA_GIC_START + 164) /* GPIO 0 */ > +#define IRQ_SOCFPGA_GPIO1 (IRQ_SOCFPGA_GIC_START + 165) /* GPIO 1 */ > +#define IRQ_SOCFPGA_GPIO2 (IRQ_SOCFPGA_GIC_START + 166) /* GPIO 2 */ > +#define IRQ_SOCFPGA_L4_SP_TIMER0 (IRQ_SOCFPGA_GIC_START + 167) /* L4 SP timer 0 */ > +#define IRQ_SOCFPGA_L4_SP_TIMER1 (IRQ_SOCFPGA_GIC_START + 168) /* L4 SP timer 1 */ > +#define IRQ_SOCFPGA_L4_OSC1_TIMER0 (IRQ_SOCFPGA_GIC_START + 169) /* L4 OSC1 timer 0 */ > +#define IRQ_SOCFPGA_L4_OSC1_TIMER1 (IRQ_SOCFPGA_GIC_START + 170) /* L4 OSC1 timer 1 */ > +#define IRQ_SOCFPGA_WD0 (IRQ_SOCFPGA_GIC_START + 171) /* Watchdog timer 0 */ > +#define IRQ_SOCFPGA_WD1 (IRQ_SOCFPGA_GIC_START + 172) /* Watchdog timer 1 */ > +#define IRQ_SOCFPGA_CLK_MAN (IRQ_SOCFPGA_GIC_START + 173) /* Clock manager */ > +#define IRQ_SOCFPGA_MPU_WAKE (IRQ_SOCFPGA_GIC_START + 174) /* MPU wake */ > +#define IRQ_SOCFPGA_FPGA_MON (IRQ_SOCFPGA_GIC_START + 175) /* FPGA monitor */ > +#define IRQ_SOCFPGA_CPU0_CTI (IRQ_SOCFPGA_GIC_START + 176) /* Coresight CPU0 CTI */ > +#define IRQ_SOCFPGA_CPU1_CTI (IRQ_SOCFPGA_GIC_START + 177) /* Coresight CPU1 CTI */ > +#define IRQ_SOCFPGA_OCRAM_CECC (IRQ_SOCFPGA_GIC_START + 178) /* on-chip RAM ECC corrected */ > +#define IRQ_SOCFPGA_OCRAM_UECC (IRQ_SOCFPGA_GIC_START + 179) /* on-chip RAM ECC uncorrected */ > + > +/* Soft IRQ */ > +#define SOFTIRQ_SOCFPGA_DMADEV (IRQ_SOCFPGA_GIC_START + 180) > +#define SOFTIRQ_SOCFPGA_GPIO_0_0 (IRQ_SOCFPGA_GIC_START + 181) > +#define SOFTIRQ_SOCFPGA_GPIO_0_1 (IRQ_SOCFPGA_GIC_START + 182) > +#define SOFTIRQ_SOCFPGA_GPIO_0_2 (IRQ_SOCFPGA_GIC_START + 183) > +#define SOFTIRQ_SOCFPGA_GPIO_0_3 (IRQ_SOCFPGA_GIC_START + 184) > +#define SOFTIRQ_SOCFPGA_GPIO_0_4 (IRQ_SOCFPGA_GIC_START + 185) > +#define SOFTIRQ_SOCFPGA_GPIO_0_5 (IRQ_SOCFPGA_GIC_START + 186) > +#define SOFTIRQ_SOCFPGA_GPIO_0_6 (IRQ_SOCFPGA_GIC_START + 187) > +#define SOFTIRQ_SOCFPGA_GPIO_0_7 (IRQ_SOCFPGA_GIC_START + 188) > +#define SOFTIRQ_SOCFPGA_GPIO_0_8 (IRQ_SOCFPGA_GIC_START + 189) > +#define SOFTIRQ_SOCFPGA_GPIO_0_9 (IRQ_SOCFPGA_GIC_START + 190) > +#define SOFTIRQ_SOCFPGA_GPIO_0_10 (IRQ_SOCFPGA_GIC_START + 191) > +#define SOFTIRQ_SOCFPGA_GPIO_0_11 (IRQ_SOCFPGA_GIC_START + 192) > +#define SOFTIRQ_SOCFPGA_GPIO_0_12 (IRQ_SOCFPGA_GIC_START + 193) > +#define SOFTIRQ_SOCFPGA_GPIO_0_13 (IRQ_SOCFPGA_GIC_START + 194) > +#define SOFTIRQ_SOCFPGA_GPIO_0_14 (IRQ_SOCFPGA_GIC_START + 195) > +#define SOFTIRQ_SOCFPGA_GPIO_0_15 (IRQ_SOCFPGA_GIC_START + 196) > +#define SOFTIRQ_SOCFPGA_GPIO_0_16 (IRQ_SOCFPGA_GIC_START + 197) > +#define SOFTIRQ_SOCFPGA_GPIO_0_17 (IRQ_SOCFPGA_GIC_START + 198) > +#define SOFTIRQ_SOCFPGA_GPIO_0_18 (IRQ_SOCFPGA_GIC_START + 199) > +#define SOFTIRQ_SOCFPGA_GPIO_0_19 (IRQ_SOCFPGA_GIC_START + 200) > +#define SOFTIRQ_SOCFPGA_GPIO_0_20 (IRQ_SOCFPGA_GIC_START + 201) > +#define SOFTIRQ_SOCFPGA_GPIO_0_21 (IRQ_SOCFPGA_GIC_START + 202) > +#define SOFTIRQ_SOCFPGA_GPIO_0_22 (IRQ_SOCFPGA_GIC_START + 203) > +#define SOFTIRQ_SOCFPGA_GPIO_0_23 (IRQ_SOCFPGA_GIC_START + 204) > +#define SOFTIRQ_SOCFPGA_GPIO_0_24 (IRQ_SOCFPGA_GIC_START + 205) > +#define SOFTIRQ_SOCFPGA_GPIO_0_25 (IRQ_SOCFPGA_GIC_START + 206) > +#define SOFTIRQ_SOCFPGA_GPIO_0_26 (IRQ_SOCFPGA_GIC_START + 207) > +#define SOFTIRQ_SOCFPGA_GPIO_0_27 (IRQ_SOCFPGA_GIC_START + 208) > +#define SOFTIRQ_SOCFPGA_GPIO_0_28 (IRQ_SOCFPGA_GIC_START + 209) > +#define SOFTIRQ_SOCFPGA_GPIO_0_29 (IRQ_SOCFPGA_GIC_START + 210) > +#define SOFTIRQ_SOCFPGA_GPIO_1_0 (IRQ_SOCFPGA_GIC_START + 211) > +#define SOFTIRQ_SOCFPGA_GPIO_1_1 (IRQ_SOCFPGA_GIC_START + 212) > +#define SOFTIRQ_SOCFPGA_GPIO_1_2 (IRQ_SOCFPGA_GIC_START + 213) > +#define SOFTIRQ_SOCFPGA_GPIO_1_3 (IRQ_SOCFPGA_GIC_START + 214) > +#define SOFTIRQ_SOCFPGA_GPIO_1_4 (IRQ_SOCFPGA_GIC_START + 215) > +#define SOFTIRQ_SOCFPGA_GPIO_1_5 (IRQ_SOCFPGA_GIC_START + 216) > +#define SOFTIRQ_SOCFPGA_GPIO_1_6 (IRQ_SOCFPGA_GIC_START + 217) > +#define SOFTIRQ_SOCFPGA_GPIO_1_7 (IRQ_SOCFPGA_GIC_START + 218) > +#define SOFTIRQ_SOCFPGA_GPIO_1_8 (IRQ_SOCFPGA_GIC_START + 219) > +#define SOFTIRQ_SOCFPGA_GPIO_1_9 (IRQ_SOCFPGA_GIC_START + 220) > +#define SOFTIRQ_SOCFPGA_GPIO_1_10 (IRQ_SOCFPGA_GIC_START + 221) > +#define SOFTIRQ_SOCFPGA_GPIO_1_11 (IRQ_SOCFPGA_GIC_START + 222) > +#define SOFTIRQ_SOCFPGA_GPIO_1_12 (IRQ_SOCFPGA_GIC_START + 223) > +#define SOFTIRQ_SOCFPGA_GPIO_1_13 (IRQ_SOCFPGA_GIC_START + 224) > +#define SOFTIRQ_SOCFPGA_GPIO_1_14 (IRQ_SOCFPGA_GIC_START + 225) > +#define SOFTIRQ_SOCFPGA_GPIO_1_15 (IRQ_SOCFPGA_GIC_START + 226) > +#define SOFTIRQ_SOCFPGA_GPIO_1_16 (IRQ_SOCFPGA_GIC_START + 227) > +#define SOFTIRQ_SOCFPGA_GPIO_1_17 (IRQ_SOCFPGA_GIC_START + 228) > +#define SOFTIRQ_SOCFPGA_GPIO_1_18 (IRQ_SOCFPGA_GIC_START + 229) > +#define SOFTIRQ_SOCFPGA_GPIO_1_19 (IRQ_SOCFPGA_GIC_START + 230) > +#define SOFTIRQ_SOCFPGA_GPIO_1_20 (IRQ_SOCFPGA_GIC_START + 231) > +#define SOFTIRQ_SOCFPGA_GPIO_1_21 (IRQ_SOCFPGA_GIC_START + 232) > +#define SOFTIRQ_SOCFPGA_GPIO_1_22 (IRQ_SOCFPGA_GIC_START + 233) > +#define SOFTIRQ_SOCFPGA_GPIO_1_23 (IRQ_SOCFPGA_GIC_START + 234) > +#define SOFTIRQ_SOCFPGA_GPIO_1_24 (IRQ_SOCFPGA_GIC_START + 235) > +#define SOFTIRQ_SOCFPGA_GPIO_1_25 (IRQ_SOCFPGA_GIC_START + 236) > +#define SOFTIRQ_SOCFPGA_GPIO_1_26 (IRQ_SOCFPGA_GIC_START + 237) > +#define SOFTIRQ_SOCFPGA_GPIO_1_27 (IRQ_SOCFPGA_GIC_START + 238) > +#define SOFTIRQ_SOCFPGA_GPIO_1_28 (IRQ_SOCFPGA_GIC_START + 239) > +#define SOFTIRQ_SOCFPGA_GPIO_1_29 (IRQ_SOCFPGA_GIC_START + 240) > +#define SOFTIRQ_SOCFPGA_GPIO_2_0 (IRQ_SOCFPGA_GIC_START + 241) > +#define SOFTIRQ_SOCFPGA_GPIO_2_1 (IRQ_SOCFPGA_GIC_START + 242) > +#define SOFTIRQ_SOCFPGA_GPIO_2_2 (IRQ_SOCFPGA_GIC_START + 243) > +#define SOFTIRQ_SOCFPGA_GPIO_2_3 (IRQ_SOCFPGA_GIC_START + 244) > +#define SOFTIRQ_SOCFPGA_GPIO_2_4 (IRQ_SOCFPGA_GIC_START + 245) > +#define SOFTIRQ_SOCFPGA_GPIO_2_5 (IRQ_SOCFPGA_GIC_START + 246) > +#define SOFTIRQ_SOCFPGA_GPIO_2_6 (IRQ_SOCFPGA_GIC_START + 247) > +#define SOFTIRQ_SOCFPGA_GPIO_2_7 (IRQ_SOCFPGA_GIC_START + 248) > +#define SOFTIRQ_SOCFPGA_GPIO_2_8 (IRQ_SOCFPGA_GIC_START + 249) > +#define SOFTIRQ_SOCFPGA_GPIO_2_9 (IRQ_SOCFPGA_GIC_START + 250) > +#define SOFTIRQ_SOCFPGA_GPIO_2_10 (IRQ_SOCFPGA_GIC_START + 251) > +#define SOFTIRQ_SOCFPGA_GPIO_2_11 (IRQ_SOCFPGA_GIC_START + 252) > +#define SOFTIRQ_SOCFPGA_GPIO_2_12 (IRQ_SOCFPGA_GIC_START + 253) > +#define SOFTIRQ_SOCFPGA_GPIO_2_13 (IRQ_SOCFPGA_GIC_START + 254) > +#define SOFTIRQ_SOCFPGA_GPIO_2_14 (IRQ_SOCFPGA_GIC_START + 255) > +#define SOFTIRQ_SOCFPGA_GPIO_2_15 (IRQ_SOCFPGA_GIC_START + 256) > +#define SOFTIRQ_SOCFPGA_GPIO_2_16 (IRQ_SOCFPGA_GIC_START + 257) > +#define SOFTIRQ_SOCFPGA_GPIO_2_17 (IRQ_SOCFPGA_GIC_START + 258) > +#define SOFTIRQ_SOCFPGA_GPIO_2_18 (IRQ_SOCFPGA_GIC_START + 259) > +#define SOFTIRQ_SOCFPGA_GPIO_2_19 (IRQ_SOCFPGA_GIC_START + 260) > +#define SOFTIRQ_SOCFPGA_GPIO_2_20 (IRQ_SOCFPGA_GIC_START + 261) > +#define SOFTIRQ_SOCFPGA_GPIO_2_21 (IRQ_SOCFPGA_GIC_START + 262) > +#define SOFTIRQ_SOCFPGA_GPIO_2_22 (IRQ_SOCFPGA_GIC_START + 263) > +#define SOFTIRQ_SOCFPGA_GPIO_2_23 (IRQ_SOCFPGA_GIC_START + 264) > +#define SOFTIRQ_SOCFPGA_GPIO_2_24 (IRQ_SOCFPGA_GIC_START + 265) > +#define SOFTIRQ_SOCFPGA_GPIO_2_25 (IRQ_SOCFPGA_GIC_START + 266) > +#define SOFTIRQ_SOCFPGA_GPIO_2_26 (IRQ_SOCFPGA_GIC_START + 267) > +#define SOFTIRQ_SOCFPGA_GPIO_2_27 (IRQ_SOCFPGA_GIC_START + 268) > +#define SOFTIRQ_SOCFPGA_GPIO_2_28 (IRQ_SOCFPGA_GIC_START + 269) > +#define SOFTIRQ_SOCFPGA_GPIO_2_29 (IRQ_SOCFPGA_GIC_START + 270) > + All these defines should come from DT. > +#define NR_IRQS 512 As mentioned, use SPARSE_IRQ. > + > +#define MAX_GIC_NR 1 > + > +#endif /* __MACH_IRQS_H */ > diff --git a/arch/arm/mach-socfpga/include/mach/memory.h b/arch/arm/mach-socfpga/include/mach/memory.h > new file mode 100644 > index 0000000..88e0ae9 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/memory.h > @@ -0,0 +1,32 @@ > +/* > + * > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > +*/ > +#ifndef __ASM_ARCH_MEMORY_H > +#define __ASM_ARCH_MEMORY_H > + > +/* > + * Physical DRAM offset. > + */ > +#define PLAT_PHYS_OFFSET UL(0x00000000) > + > +#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) > + > +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) > +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) > +#endif You shouldn't need memory.h. > + > +#endif > diff --git a/arch/arm/mach-socfpga/include/mach/smp.h b/arch/arm/mach-socfpga/include/mach/smp.h > new file mode 100644 > index 0000000..07cc087 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/smp.h > @@ -0,0 +1,15 @@ > +/* > + * SMP support > + */ > + > +#ifndef __MACH_SMP_H > +#define __MACH_SMP_H > + > +#include <asm/hardware/gic.h> > + > +static inline void smp_cross_call(const struct cpumask *mask, int ipi) > +{ > + gic_raise_softirq(mask, ipi); > +} > + > +#endif > diff --git a/arch/arm/mach-socfpga/include/mach/socfpga-timer.h b/arch/arm/mach-socfpga/include/mach/socfpga-timer.h > new file mode 100644 > index 0000000..9d577f9 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/socfpga-timer.h > @@ -0,0 +1,27 @@ > +/* > + * Copyright (C) 2012 Altera Corporation > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > +*/ > + > +#ifndef __SOCFPGA_TIMER > +#define __SOCFPGA_TIMER > + > +#define SOCFPGA_SP_TIMER_FREQ_HZ 2400000 > +#define SOCFPGA_OSC_TIMER_FREQ_HZ 2400000 > + > +void dwapbt_clocksource_init(void __iomem *); > +void dwapbt_clockevents_init(void __iomem *, unsigned int); > + > +#endif /* __SOCFPGA_TIMER */ > diff --git a/arch/arm/mach-socfpga/include/mach/system.h b/arch/arm/mach-socfpga/include/mach/system.h > new file mode 100644 > index 0000000..c76834c > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/system.h > @@ -0,0 +1,31 @@ > +/* > + * Copyright (C) 2012 Altera Corporation > + * > + * Modified from arch/arm/mach-realview/include/mach/system.h > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > +*/ > +#ifndef __ASM_ARCH_SYSTEM_H > +#define __ASM_ARCH_SYSTEM_H > + > +static inline void arch_idle(void) > +{ > + /* > + * This should do all the clock switching > + * and wait for interrupt tricks > + */ > + cpu_do_idle(); > +} This isn't needed any longer and system.h should be removed. > + > +#endif > diff --git a/arch/arm/mach-socfpga/include/mach/timex.h b/arch/arm/mach-socfpga/include/mach/timex.h > new file mode 100644 > index 0000000..43df435 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/timex.h > @@ -0,0 +1,19 @@ > +/* > + * Copyright (C) 2003 ARM Limited > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > + */ > + > +#define CLOCK_TICK_RATE (50000000 / 16) > diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h > new file mode 100644 > index 0000000..1525dbd > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/uncompress.h > @@ -0,0 +1,44 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > +*/ > +#include <linux/serial_reg.h> > +#include <mach/socfpga_cyclone5.h> > + > +#define UART8250_UART_THR(base) (*(unsigned char *)((base) + 0x0)) > +#define UART8250_UART_LSR(base) (*(unsigned char *)((base) + 0x14)) > + > +/* > + * This does not append a newline > + */ > +static inline void putc(int c) > +{ > + unsigned long base = SOCFPGA_UART0_BASE; > + > + while ((UART8250_UART_LSR(base) & UART_LSR_THRE) == 0) > + barrier(); > + > + UART8250_UART_THR(base) = c; > +} > + > +/* > + * Not implemented > + */ > +static inline void flush(void) > +{ > +} > + > +#define arch_decomp_setup() > +#define arch_decomp_wdog() > diff --git a/arch/arm/mach-socfpga/localtimer.c b/arch/arm/mach-socfpga/localtimer.c > new file mode 100644 > index 0000000..4aa9221 > --- /dev/null > +++ b/arch/arm/mach-socfpga/localtimer.c > @@ -0,0 +1,34 @@ > +/* > + * Copyright (C) 2012 Altera Corporation > + * Copyright (C) 2002 ARM Ltd. > + * All Rights Reserved > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#include <linux/init.h> > +#include <linux/clockchips.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > + > +#include <asm/smp_twd.h> > + > +/* > + * Setup the local clock events for a CPU. > + */ > +int __cpuinit socfpga_local_timer_setup(struct clock_event_device *evt) > +{ > + struct device_node *np; > + > + np = of_find_compatible_node(NULL, NULL, "arm,smp-twd"); This compatible string is wrong (it changed). See the documentation. > + if (!twd_base) { > + twd_base = of_iomap(np, 0); > + WARN_ON(!twd_base); > + } > + evt->irq = irq_of_parse_and_map(np, 0); > + twd_timer_setup(evt); > + return 0; > +} > + > diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c > new file mode 100644 > index 0000000..5cd148f > --- /dev/null > +++ b/arch/arm/mach-socfpga/platsmp.c > @@ -0,0 +1,154 @@ > +/* > + * Copyright (C) 2012 Altera Corporation > + * Copyright (C) 2002 ARM Ltd. > + * All Rights Reserved > + * > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#include <linux/init.h> > +#include <linux/errno.h> > +#include <linux/smp.h> > +#include <linux/io.h> > +#include <linux/delay.h> > + > +#include <mach/iomap.h> > +#include <mach/socfpga_cyclone5.h> > +#include <asm/hardware/gic.h> > +#include <asm/mach-types.h> > +#include <asm/smp_scu.h> > +#include <asm/cacheflush.h> > +#include <asm/smp_plat.h> > + > +#include "common.h" > + > +extern void socfpga_secondary_startup(void); > + > +/* > + * control for which core is the next to come out of the secondary > + * boot "holding pen" > + */ > +int __cpuinitdata pen_release = -1; None of this pen stuff is needed if you properly reset cores when hot-unplugged. All this is only needed if you only go to wfi when hot unplugged. See highbank platsmp.c for an example without pen code. > + > +/* > + * Write pen_release in a way that is guaranteed to be visible to all > + * observers, irrespective of whether they're taking part in coherency > + * or not. This is necessary for the hotplug code to work reliably. > + */ > +static void __cpuinit write_pen_release(int val) > +{ > + pen_release = val; > + smp_wmb(); > + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); > + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); > +} > + > +static DEFINE_SPINLOCK(boot_lock); > + > +void __cpuinit platform_secondary_init(unsigned int cpu) > +{ > + /* > + * if any interrupts are already enabled for the primary > + * core (e.g. timer irq), then they will not have been enabled > + * for us: do so > + */ > + gic_secondary_init(0); > + > + /* > + * let the primary processor know we're out of the > + * pen, then head off into the C entry point > + */ > + write_pen_release(-1); > + > + /* > + * Synchronise with the boot thread. > + */ > + spin_lock(&boot_lock); > + spin_unlock(&boot_lock); > +} > + > +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) > +{ > + unsigned long timeout; > + /* > + * Set synchronisation state between this boot processor > + * and the secondary one > + */ > + spin_lock(&boot_lock); > + > + /* > + * This is really belt and braces; we hold unintended secondary > + * CPUs in the holding pen until we're ready for them. However, > + * since we haven't sent them a soft interrupt, they shouldn't > + * be there. > + */ > + write_pen_release(cpu_logical_map(cpu)); > + > + /* > + * Send the secondary CPU a soft interrupt, thereby causing > + * the boot monitor to read the system wide flags register, > + * and branch to the address found there. > + */ > + gic_raise_softirq(cpumask_of(cpu), 1); > + > + timeout = jiffies + (1 * HZ); > + while (time_before(jiffies, timeout)) { > + smp_rmb(); > + if (pen_release == -1) > + break; > + > + udelay(10); > + } > + > + /* > + * now the secondary core is starting up let it run its > + * calibrations, then wait for it to finish > + */ > + spin_unlock(&boot_lock); > + return pen_release != -1 ? -ENOSYS : 0; > +} > + > +static void __iomem *scu_base_addr(void) > +{ > + return __io_address(SOCFPGA_MPUSCU_BASE); > +} > + > +/* > + * Initialise the CPU possible map early - this describes the CPUs > + * which may be present or become present in the system. > + */ > +void __init smp_init_cpus(void) > +{ > + void __iomem *scu_base = scu_base_addr(); > + unsigned int i, ncores; > + > + ncores = scu_base ? scu_get_core_count(scu_base) : 1; > + > + /* sanity check */ > + if (ncores > nr_cpu_ids) { > + pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", > + ncores, nr_cpu_ids); > + ncores = nr_cpu_ids; > + } > + > + for (i = 0; i < ncores; i++) > + set_cpu_possible(i, true); > + > + set_smp_cross_call(gic_raise_softirq); > +} > + > +void __init platform_smp_prepare_cpus(unsigned int max_cpus) > +{ > + scu_enable(scu_base_addr()); > + > + /* > + * Write the address of secondary startup into the > + * system-wide flags register. The BootMonitor waits > + * until it receives a soft interrupt, and then the > + * secondary CPU branches to this address. > + */ > + __raw_writel(virt_to_phys(socfpga_secondary_startup), > + __io_address(SOCFPGA_SMP_FLAG)); > +} > diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig > index 101b968..2f9a81e 100644 > --- a/arch/arm/mm/Kconfig > +++ b/arch/arm/mm/Kconfig > @@ -381,7 +381,7 @@ config CPU_V6K > > # ARMv7 > config CPU_V7 > - bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX > + bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_SOCFPGA This is not needed. > select CPU_32v6K > select CPU_32v7 > select CPU_ABRT_EV7 > ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-04 17:56 ` Rob Herring @ 2012-07-09 11:30 ` Pavel Machek 2012-07-09 13:25 ` Rob Herring 2012-07-09 11:52 ` Pavel Machek ` (2 subsequent siblings) 3 siblings, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-07-09 11:30 UTC (permalink / raw) To: linux-arm-kernel Hi! > > +config ARCH_SOCFPGA > > + bool "Altera SOCFPGA family" > > + select CPU_V7 > > + select ARM_GIC > > + select ARM_AMBA > > + select CLKDEV_LOOKUP > > + select MIGHT_HAVE_CACHE_L2X0 > > + select HAVE_MACH_CLKDEV > > + select GENERIC_CLOCKEVENTS > > + select ARCH_WANT_OPTIONAL_GPIOLIB > > + select GPIO_PL061 if GPIOLIB > > + select NEED_MACH_MEMORY_H > > + select USE_OF > > Alphabetize the selects. Umm... Others are not alphabetized, either. Something like this to group them logically? > > @@ -1596,6 +1614,7 @@ config HZ > > default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER > > default AT91_TIMER_HZ if ARCH_AT91 > > default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE > > + default SOCFPGA_TIMER_HZ if ARCH_SOCFPGA > > Is this really needed? Probably not. Removed. > > +struct clk_ops { > > + long (*round)(struct clk *, unsigned long); > > + int (*set)(struct clk *, unsigned long); > > +}; > > Use common clk infrastructure. Yep, done already. > > +#define IO_SPACE_LIMIT 0xffffffff > > + > > +#define __io(a) __typesafe_io(a) > > +#define __mem_pci(a) (a) > > You don't need io.h, remove it. Will do, thanks. > > --- /dev/null > > +++ b/arch/arm/mach-socfpga/include/mach/iomap.h > > @@ -0,0 +1,37 @@ > > +#include <asm/sizes.h> > > + > > +/* macro to get at IO space when running virtually */ > > +#ifdef CONFIG_MMU > > Do you really support !MMU? No. Will remove. > > +#define SOFTIRQ_SOCFPGA_GPIO_2_28 (IRQ_SOCFPGA_GIC_START + 269) > > +#define SOFTIRQ_SOCFPGA_GPIO_2_29 (IRQ_SOCFPGA_GIC_START + 270) > > + > > All these defines should come from DT. Yes. Most of them do now, will fix the rest. > > +#define NR_IRQS 512 > > As mentioned, use SPARSE_IRQ. Fixed. As mentioned :-). > > +#define PLAT_PHYS_OFFSET UL(0x00000000) > > + > > +#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) > > + > > +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) > > +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) > > +#endif > > You shouldn't need memory.h. Ok. > > --- /dev/null > > +++ b/arch/arm/mach-socfpga/include/mach/system.h > > @@ -0,0 +1,31 @@ > > +static inline void arch_idle(void) > > +{ > > + /* > > + * This should do all the clock switching > > + * and wait for interrupt tricks > > + */ > > + cpu_do_idle(); > > +} > > This isn't needed any longer and system.h should be removed. Ok. > > --- /dev/null > > +++ b/arch/arm/mach-socfpga/platsmp.c ... > > +/* > > + * control for which core is the next to come out of the secondary > > + * boot "holding pen" > > + */ > > +int __cpuinitdata pen_release = -1; > > None of this pen stuff is needed if you properly reset cores when > hot-unplugged. All this is only needed if you only go to wfi when hot > unplugged. See highbank platsmp.c for an example without pen code. Will take a look, thanks! > > diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig > > index 101b968..2f9a81e 100644 > > --- a/arch/arm/mm/Kconfig > > +++ b/arch/arm/mm/Kconfig > > @@ -381,7 +381,7 @@ config CPU_V6K > > > > # ARMv7 > > config CPU_V7 > > - bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX > > + bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_SOCFPGA > > This is not needed. Already fixed. Thanks for the review. This is the easy stuff, I'll remove the memory.h/system.h next, then address the SMP thing. Pavel diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d203253..ab3b389 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -252,18 +252,18 @@ choice config ARCH_SOCFPGA bool "Altera SOCFPGA family" - select CPU_V7 - select ARM_GIC select ARM_AMBA - select CLKDEV_LOOKUP - select MIGHT_HAVE_CACHE_L2X0 - select HAVE_MACH_CLKDEV - select GENERIC_CLOCKEVENTS + select ARM_GIC + select CPU_V7 select ARCH_WANT_OPTIONAL_GPIOLIB select GPIO_PL061 if GPIOLIB + select CLKDEV_LOOKUP + select GENERIC_CLOCKEVENTS + select HAVE_MACH_CLKDEV + select MIGHT_HAVE_CACHE_L2X0 select NEED_MACH_MEMORY_H - select USE_OF select SPARSE_IRQ + select USE_OF help This enables support for Altera SOCFPGA Cyclone V platform @@ -1615,7 +1615,6 @@ config HZ default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default AT91_TIMER_HZ if ARCH_AT91 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE - default SOCFPGA_TIMER_HZ if ARCH_SOCFPGA default 100 config THUMB2_KERNEL diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 81358e6..7f1b72b 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -6,10 +6,3 @@ config MACH_SOCFPGA_CYCLONE5 select COMMON_CLK help Include support for the Altera(R) Cyclone5 development platform. - -config SOCFPGA_TIMER_HZ - int "Kernel internal timer frequency " - range 20 1024 - default "100" - help - Kernel internal timer frequency should be a divisor of 77161. diff --git a/arch/arm/mach-socfpga/include/mach/iomap.h b/arch/arm/mach-socfpga/include/mach/iomap.h index 656482d..d5f8493 100644 --- a/arch/arm/mach-socfpga/include/mach/iomap.h +++ b/arch/arm/mach-socfpga/include/mach/iomap.h @@ -20,7 +20,6 @@ #include <asm/sizes.h> /* macro to get at IO space when running virtually */ -#ifdef CONFIG_MMU /* * Statically mapped addresses: * @@ -29,9 +28,6 @@ * 1fxx xxxx -> fexx xxxx */ #define IO_ADDRESS(x) (((x) & 0x03ffffff) + 0xfb000000) -#else -#define IO_ADDRESS(x) (x) -#endif #define __io_address(n) IOMEM(IO_ADDRESS(n)) -#endif \ No newline at end of file +#endif -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-09 11:30 ` Pavel Machek @ 2012-07-09 13:25 ` Rob Herring 2012-07-10 9:48 ` Pavel Machek 0 siblings, 1 reply; 47+ messages in thread From: Rob Herring @ 2012-07-09 13:25 UTC (permalink / raw) To: linux-arm-kernel On 07/09/2012 06:30 AM, Pavel Machek wrote: > Hi! > >>> +config ARCH_SOCFPGA >>> + bool "Altera SOCFPGA family" >>> + select CPU_V7 >>> + select ARM_GIC >>> + select ARM_AMBA >>> + select CLKDEV_LOOKUP >>> + select MIGHT_HAVE_CACHE_L2X0 >>> + select HAVE_MACH_CLKDEV >>> + select GENERIC_CLOCKEVENTS >>> + select ARCH_WANT_OPTIONAL_GPIOLIB >>> + select GPIO_PL061 if GPIOLIB >>> + select NEED_MACH_MEMORY_H >>> + select USE_OF >> >> Alphabetize the selects. > > Umm... Others are not alphabetized, either. Something like this to > group them logically? Many are not, but check any relatively new platform like highbank, zynq, picoxcell. Rob >>> @@ -1596,6 +1614,7 @@ config HZ >>> default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER >>> default AT91_TIMER_HZ if ARCH_AT91 >>> default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE >>> + default SOCFPGA_TIMER_HZ if ARCH_SOCFPGA >> >> Is this really needed? > > Probably not. Removed. > >>> +struct clk_ops { >>> + long (*round)(struct clk *, unsigned long); >>> + int (*set)(struct clk *, unsigned long); >>> +}; >> >> Use common clk infrastructure. > > Yep, done already. > >>> +#define IO_SPACE_LIMIT 0xffffffff >>> + >>> +#define __io(a) __typesafe_io(a) >>> +#define __mem_pci(a) (a) >> >> You don't need io.h, remove it. > > Will do, thanks. > >>> --- /dev/null >>> +++ b/arch/arm/mach-socfpga/include/mach/iomap.h >>> @@ -0,0 +1,37 @@ >>> +#include <asm/sizes.h> >>> + >>> +/* macro to get at IO space when running virtually */ >>> +#ifdef CONFIG_MMU >> >> Do you really support !MMU? > > No. Will remove. > >>> +#define SOFTIRQ_SOCFPGA_GPIO_2_28 (IRQ_SOCFPGA_GIC_START + 269) >>> +#define SOFTIRQ_SOCFPGA_GPIO_2_29 (IRQ_SOCFPGA_GIC_START + 270) >>> + >> >> All these defines should come from DT. > > Yes. Most of them do now, will fix the rest. > >>> +#define NR_IRQS 512 >> >> As mentioned, use SPARSE_IRQ. > > Fixed. As mentioned :-). > >>> +#define PLAT_PHYS_OFFSET UL(0x00000000) >>> + >>> +#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) >>> + >>> +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) >>> +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) >>> +#endif >> >> You shouldn't need memory.h. > > Ok. > >>> --- /dev/null >>> +++ b/arch/arm/mach-socfpga/include/mach/system.h >>> @@ -0,0 +1,31 @@ >>> +static inline void arch_idle(void) >>> +{ >>> + /* >>> + * This should do all the clock switching >>> + * and wait for interrupt tricks >>> + */ >>> + cpu_do_idle(); >>> +} >> >> This isn't needed any longer and system.h should be removed. > > Ok. > >>> --- /dev/null >>> +++ b/arch/arm/mach-socfpga/platsmp.c > ... >>> +/* >>> + * control for which core is the next to come out of the secondary >>> + * boot "holding pen" >>> + */ >>> +int __cpuinitdata pen_release = -1; >> >> None of this pen stuff is needed if you properly reset cores when >> hot-unplugged. All this is only needed if you only go to wfi when hot >> unplugged. See highbank platsmp.c for an example without pen code. > > Will take a look, thanks! > >>> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig >>> index 101b968..2f9a81e 100644 >>> --- a/arch/arm/mm/Kconfig >>> +++ b/arch/arm/mm/Kconfig >>> @@ -381,7 +381,7 @@ config CPU_V6K >>> >>> # ARMv7 >>> config CPU_V7 >>> - bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX >>> + bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_SOCFPGA >> >> This is not needed. > > Already fixed. > > Thanks for the review. This is the easy stuff, I'll remove the > memory.h/system.h next, then address the SMP thing. > Pavel > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index d203253..ab3b389 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -252,18 +252,18 @@ choice > > config ARCH_SOCFPGA > bool "Altera SOCFPGA family" > - select CPU_V7 > - select ARM_GIC > select ARM_AMBA > - select CLKDEV_LOOKUP > - select MIGHT_HAVE_CACHE_L2X0 > - select HAVE_MACH_CLKDEV > - select GENERIC_CLOCKEVENTS > + select ARM_GIC > + select CPU_V7 > select ARCH_WANT_OPTIONAL_GPIOLIB > select GPIO_PL061 if GPIOLIB > + select CLKDEV_LOOKUP > + select GENERIC_CLOCKEVENTS > + select HAVE_MACH_CLKDEV > + select MIGHT_HAVE_CACHE_L2X0 > select NEED_MACH_MEMORY_H > - select USE_OF > select SPARSE_IRQ > + select USE_OF > help > This enables support for Altera SOCFPGA Cyclone V platform > > @@ -1615,7 +1615,6 @@ config HZ > default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER > default AT91_TIMER_HZ if ARCH_AT91 > default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE > - default SOCFPGA_TIMER_HZ if ARCH_SOCFPGA > default 100 > > config THUMB2_KERNEL > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig > index 81358e6..7f1b72b 100644 > --- a/arch/arm/mach-socfpga/Kconfig > +++ b/arch/arm/mach-socfpga/Kconfig > @@ -6,10 +6,3 @@ config MACH_SOCFPGA_CYCLONE5 > select COMMON_CLK > help > Include support for the Altera(R) Cyclone5 development platform. > - > -config SOCFPGA_TIMER_HZ > - int "Kernel internal timer frequency " > - range 20 1024 > - default "100" > - help > - Kernel internal timer frequency should be a divisor of 77161. > diff --git a/arch/arm/mach-socfpga/include/mach/iomap.h b/arch/arm/mach-socfpga/include/mach/iomap.h > index 656482d..d5f8493 100644 > --- a/arch/arm/mach-socfpga/include/mach/iomap.h > +++ b/arch/arm/mach-socfpga/include/mach/iomap.h > @@ -20,7 +20,6 @@ > #include <asm/sizes.h> > > /* macro to get at IO space when running virtually */ > -#ifdef CONFIG_MMU > /* > * Statically mapped addresses: > * > @@ -29,9 +28,6 @@ > * 1fxx xxxx -> fexx xxxx > */ > #define IO_ADDRESS(x) (((x) & 0x03ffffff) + 0xfb000000) > -#else > -#define IO_ADDRESS(x) (x) > -#endif > #define __io_address(n) IOMEM(IO_ADDRESS(n)) > > -#endif > \ No newline at end of file > +#endif > ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-09 13:25 ` Rob Herring @ 2012-07-10 9:48 ` Pavel Machek 0 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-07-10 9:48 UTC (permalink / raw) To: linux-arm-kernel On Mon 2012-07-09 08:25:17, Rob Herring wrote: > On 07/09/2012 06:30 AM, Pavel Machek wrote: > > Hi! > > > >>> +config ARCH_SOCFPGA > >>> + bool "Altera SOCFPGA family" > >>> + select CPU_V7 > >>> + select ARM_GIC > >>> + select ARM_AMBA > >>> + select CLKDEV_LOOKUP > >>> + select MIGHT_HAVE_CACHE_L2X0 > >>> + select HAVE_MACH_CLKDEV > >>> + select GENERIC_CLOCKEVENTS > >>> + select ARCH_WANT_OPTIONAL_GPIOLIB > >>> + select GPIO_PL061 if GPIOLIB > >>> + select NEED_MACH_MEMORY_H > >>> + select USE_OF > >> > >> Alphabetize the selects. > > > > Umm... Others are not alphabetized, either. Something like this to > > group them logically? > > Many are not, but check any relatively new platform like highbank, zynq, > picoxcell. Ok, done, thanks. (Will push via git to Dinh, should appear in next version). Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-04 17:56 ` Rob Herring 2012-07-09 11:30 ` Pavel Machek @ 2012-07-09 11:52 ` Pavel Machek 2012-07-09 12:06 ` Pavel Machek 2012-07-09 12:10 ` Pavel Machek 3 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-07-09 11:52 UTC (permalink / raw) To: linux-arm-kernel Hi! > > diff --git a/arch/arm/mach-socfpga/include/mach/memory.h b/arch/arm/mach-socfpga/include/mach/memory.h > > new file mode 100644 > > index 0000000..88e0ae9 > > +#ifndef __ASM_ARCH_MEMORY_H > > +#define __ASM_ARCH_MEMORY_H > > + > > +/* > > + * Physical DRAM offset. > > + */ > > +#define PLAT_PHYS_OFFSET UL(0x00000000) > > + > > +#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) > > + > > +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) > > +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) > > +#endif > > You shouldn't need memory.h. Yep. Deleting it was easier than expected. Thanks. Pavel commit 39edfa179a37d38352b21894fbd9b559e52dcf31 Author: Pavel <pavel@ucw.cz> Date: Mon Jul 9 13:48:27 2012 +0200 Remove memory.h/system.h. Signed-off-by: Pavel Machek <pavel@denx.de> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ab3b389..8e69b05 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -261,7 +261,6 @@ config ARCH_SOCFPGA select GENERIC_CLOCKEVENTS select HAVE_MACH_CLKDEV select MIGHT_HAVE_CACHE_L2X0 - select NEED_MACH_MEMORY_H select SPARSE_IRQ select USE_OF help diff --git a/arch/arm/mach-socfpga/include/mach/memory.h b/arch/arm/mach-socfpga/include/mach/memory.h deleted file mode 100644 index e69de29..0000000 diff --git a/arch/arm/mach-socfpga/include/mach/system.h b/arch/arm/mach-socfpga/include/mach/system.h deleted file mode 100644 index e69de29..0000000 -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-04 17:56 ` Rob Herring 2012-07-09 11:30 ` Pavel Machek 2012-07-09 11:52 ` Pavel Machek @ 2012-07-09 12:06 ` Pavel Machek 2012-07-09 12:10 ` Pavel Machek 3 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-07-09 12:06 UTC (permalink / raw) To: linux-arm-kernel Hi! [Oops, I missed few review comments; hard to see in all the quoted material.] > > +static inline void cpu_leave_lowpower(void) > > +{ > > + unsigned int v; > > + > > + asm volatile("mrc p15, 0, %0, c1, c0, 0\n" > > + " orr %0, %0, %1\n" > > + " mcr p15, 0, %0, c1, c0, 0\n" > > + " mrc p15, 0, %0, c1, c0, 1\n" > > + " orr %0, %0, #0x20\n" > > + " mcr p15, 0, %0, c1, c0, 1\n" > > + : "=&r" (v) > > + : "Ir" (CR_C) > > + : "cc"); > > +} > > + > > +static inline void platform_do_lowpower(unsigned int cpu, int *spurious) > > +{ > > + /* > > + * there is no power-control hardware on this platform, so all > > + * we can do is put the core into WFI; this is safe as the calling > > + * code will have already disabled interrupts > > Is this true or just copied from ARM Ltd platforms? No idea, probably copied. Dinh? But I guess it makes sense to just use the "WFI" for initial merge. > > +++ b/arch/arm/mach-socfpga/localtimer.c > > @@ -0,0 +1,34 @@ > > +/* > > + * Copyright (C) 2012 Altera Corporation > > + * Copyright (C) 2002 ARM Ltd. > > + * All Rights Reserved > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + */ > > +#include <linux/init.h> > > +#include <linux/clockchips.h> > > +#include <linux/of.h> > > +#include <linux/of_address.h> > > +#include <linux/of_irq.h> > > + > > +#include <asm/smp_twd.h> > > + > > +/* > > + * Setup the local clock events for a CPU. > > + */ > > +int __cpuinit socfpga_local_timer_setup(struct clock_event_device *evt) > > +{ > > + struct device_node *np; > > + > > + np = of_find_compatible_node(NULL, NULL, "arm,smp-twd"); > > This compatible string is wrong (it changed). See the documentation. OK, I updated the string (like below), but... should this code be needed at all? Core should call this itself and socfpga_local_timer_setup does not seem to be called at all...? Pavel diff --git a/arch/arm/mach-socfpga/localtimer.c b/arch/arm/mach-socfpga/localtimer.c index 4aa9221..a616488 100644 --- a/arch/arm/mach-socfpga/localtimer.c +++ b/arch/arm/mach-socfpga/localtimer.c @@ -22,7 +22,7 @@ int __cpuinit socfpga_local_timer_setup(struct clock_event_device *evt) { struct device_node *np; - np = of_find_compatible_node(NULL, NULL, "arm,smp-twd"); + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer"); if (!twd_base) { twd_base = of_iomap(np, 0); WARN_ON(!twd_base); -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform. 2012-07-04 17:56 ` Rob Herring ` (2 preceding siblings ...) 2012-07-09 12:06 ` Pavel Machek @ 2012-07-09 12:10 ` Pavel Machek 3 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-07-09 12:10 UTC (permalink / raw) To: linux-arm-kernel Hi! > > diff --git a/arch/arm/mach-socfpga/localtimer.c b/arch/arm/mach-socfpga/localtimer.c > > new file mode 100644 > > index 0000000..4aa9221 > > --- /dev/null > > +++ b/arch/arm/mach-socfpga/localtimer.c > > @@ -0,0 +1,34 @@ > > +/* > > + * Copyright (C) 2012 Altera Corporation > > + * Copyright (C) 2002 ARM Ltd. > > + * All Rights Reserved > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + */ > > +#include <linux/init.h> > > +#include <linux/clockchips.h> > > +#include <linux/of.h> > > +#include <linux/of_address.h> > > +#include <linux/of_irq.h> > > + > > +#include <asm/smp_twd.h> > > + > > +/* > > + * Setup the local clock events for a CPU. > > + */ > > +int __cpuinit socfpga_local_timer_setup(struct clock_event_device *evt) > > +{ > > + struct device_node *np; > > + > > + np = of_find_compatible_node(NULL, NULL, "arm,smp-twd"); > > This compatible string is wrong (it changed). See the documentation. Thanks, Pavel commit 9ca5b68dc73249cc17f296237b81abc2fa82b9fd Author: Pavel <pavel@ucw.cz> Date: Mon Jul 9 14:07:29 2012 +0200 Remove unneccessary localtimer.c. dts bindings already do the right thing. Signed-off-by: Pavel Machek <pavel@denx.de> diff --git a/arch/arm/mach-socfpga/localtimer.c b/arch/arm/mach-socfpga/localtimer.c deleted file mode 100644 index a616488..0000000 --- a/arch/arm/mach-socfpga/localtimer.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/init.h> -#include <linux/clockchips.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> - -#include <asm/smp_twd.h> - -/* - * Setup the local clock events for a CPU. - */ -int __cpuinit socfpga_local_timer_setup(struct clock_event_device *evt) -{ - struct device_node *np; - - np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer"); - if (!twd_base) { - twd_base = of_iomap(np, 0); - WARN_ON(!twd_base); - } - evt->irq = irq_of_parse_and_map(np, 0); - twd_timer_setup(evt); - return 0; -} - -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW 2012-06-27 13:50 [RFC]Add initial support for Altera's SOCFPGA hardward dinguyen at altera.com 2012-06-27 13:50 ` [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform dinguyen at altera.com @ 2012-06-27 13:50 ` dinguyen at altera.com 2012-06-27 14:25 ` Thomas Petazzoni 1 sibling, 1 reply; 47+ messages in thread From: dinguyen at altera.com @ 2012-06-27 13:50 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> - Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> --- arch/arm/boot/dts/socfpga.dtsi | 73 +++++++++ arch/arm/boot/dts/socfpga_cyclone5.dts | 90 +++++++++++ arch/arm/configs/socfpga_defconfig | 84 ++++++++++ arch/arm/mach-socfpga/include/mach/clkdev.h | 16 ++ .../mach-socfpga/include/mach/socfpga_cyclone5.h | 83 ++++++++++ arch/arm/mach-socfpga/socfpga_cyclone5.c | 161 ++++++++++++++++++++ arch/arm/tools/mach-types | 1 + 7 files changed, 508 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga.dtsi create mode 100644 arch/arm/boot/dts/socfpga_cyclone5.dts create mode 100644 arch/arm/configs/socfpga_defconfig create mode 100644 arch/arm/mach-socfpga/include/mach/clkdev.h create mode 100644 arch/arm/mach-socfpga/include/mach/socfpga_cyclone5.h create mode 100644 arch/arm/mach-socfpga/socfpga_cyclone5.c diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi new file mode 100644 index 0000000..54489b5 --- /dev/null +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2012 Altera <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/include/ "skeleton.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu at 1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc at fffed000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffed000 0x1000>, + <0xfffec100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + /* Local timer */ + timer at fffec600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfffec600 0x100>; + interrupts = <1 13 0xf04>; + }; + + L2: l2-cache at fffef000 { + compatible = "arm,pl310-cache"; + reg = <0xfffef000 0x1000>; + interrupts = <0 38 0x04>; + cache-unified; + cache-level = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts new file mode 100644 index 0000000..453a7e2 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +/include/ "socfpga.dtsi" + +/ { + model = "Altera SOCFPGA Cyclone V"; + compatible = "altr,socfpga-cyclone5"; + + aliases { + ethernet0 = &gmac0; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x10000000>; /* 256MB */ + }; + + soc { + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma at ffe01000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffe01000 0x1000>; + interrupts = <0 180 4>; + }; + }; + + apb_periphs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart0: uart at ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x1000>; + clock-frequency = <7372800>; + interrupts = <0 162 4>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1: uart at ffc03000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc03000 0x1000>; + clock-frequency = <7372800>; + interrupts = <0 163 4>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + gmac0: stmmac at ff700000 { + compatible = "st,spear600-gmac"; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + phy-mode = "gmii"; + }; + + }; + }; +}; diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig new file mode 100644 index 0000000..aac8731 --- /dev/null +++ b/arch/arm/configs/socfpga_defconfig @@ -0,0 +1,84 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +CONFIG_CPUSETS=y +CONFIG_NAMESPACES=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_SOCFPGA=y +CONFIG_MACH_SOCFPGA_CYCLONE5=y +CONFIG_ARM_THUMBEE=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_NR_CPUS=2 +CONFIG_AEABI=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,57600 mem=256M at 0x0" +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=2 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_STMMAC_ETH=y +# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_DW=y +# CONFIG_RTC_HCTOSYS is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_INFO=y +CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_DEBUG_USER=y +CONFIG_XZ_DEC=y diff --git a/arch/arm/mach-socfpga/include/mach/clkdev.h b/arch/arm/mach-socfpga/include/mach/clkdev.h new file mode 100644 index 0000000..1eeecc4 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clkdev.h @@ -0,0 +1,16 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#include <mach/clock.h> + +struct clk { + unsigned long rate; + const struct clk_ops *ops; + const struct icst_params *params; + void __iomem *vcoreg; +}; + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-socfpga/include/mach/socfpga_cyclone5.h b/arch/arm/mach-socfpga/include/mach/socfpga_cyclone5.h new file mode 100644 index 0000000..7787f9d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/socfpga_cyclone5.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_ARCH_BOARD_SOCFPGA_CYCLONE5_H +#define __ASM_ARCH_BOARD_SOCFPGA_CYCLONE5_H + +#undef __ASM_ARCH_BOARD_SOCFPGA_CYCLONE5_H + +#define SOCFPGA_LWFPGASLAVES_BASE (0xff200000) +#define SOCFPGA_LWHPS2FPGAREGS_BASE (0xff400000) +#define SOCFPGA_HPS2FPGAREGS_BASE (0xff500000) +#define SOCFPGA_FPGA2HPSREGS_BASE (0xff600000) +#define SOCFPGA_EMAC0_BASE (0xff700000) +#define SOCFPGA_EMAC1_BASE (0xff702000) +#define SOCFPGA_SDMMC_BASE (0xff704000) +#define SOCFPGA_QSPIREGS_BASE (0xff705000) +#define SOCFPGA_FPGAMGRREGS_BASE (0xff706000) +#define SOCFPGA_ACPIDMAP_BASE (0xff707000) +#define SOCFPGA_GPIO0_BASE (0xff708000) +#define SOCFPGA_GPIO1_BASE (0xff709000) +#define SOCFPGA_GPIO2_BASE (0xff70a000) +#define SOCFPGA_L3REGS_BASE (0xff800000) +#define SOCFPGA_NANDDATA_BASE (0xff900000) +#define SOCFPGA_QSPIDATA_BASE (0xffa00000) +#define SOCFPGA_USB0_BASE (0xffb00000) +#define SOCFPGA_USB1_BASE (0xffb40000) +#define SOCFPGA_NANDREGS_BASE (0xffb80000) +#define SOCFPGA_FPGAMGRDATA_BASE (0xffb90000) +#define SOCFPGA_CAN0_BASE (0xffc00000) +#define SOCFPGA_CAN1_BASE (0xffc01000) +#define SOCFPGA_UART0_BASE (0xffc02000) +#define SOCFPGA_UART1_BASE (0xffc03000) +#define SOCFPGA_I2C0_BASE (0xffc04000) +#define SOCFPGA_I2C1_BASE (0xffc05000) +#define SOCFPGA_I2C2MDIO0_BASE (0xffc06000) +#define SOCFPGA_I2C3MDIO1_BASE (0xffc07000) +#define SOCFPGA_SPTIMER0_BASE (0xffc08000) +#define SOCFPGA_SPTIMER1_BASE (0xffc09000) +#define SOCFPGA_SDR_BASE (0xffc20000) +#define SOCFPGA_OSC1TIMER0_BASE (0xffd00000) +#define SOCFPGA_OSC1TIMER1_BASE (0xffd01000) +#define SOCFPGA_L4WD0_BASE (0xffd02000) +#define SOCFPGA_L4WD1_BASE (0xffd03000) +#define SOCFPGA_CLKMGR_BASE (0xffd04000) +#define SOCFPGA_RSTMGR_BASE (0xffd05000) +#define SOCFPGA_SYSMGR_BASE (0xffd08000) +#define SOCFPGA_DMANONSECURE_BASE (0xffe00000) +#define SOCFPGA_DMASECURE_BASE (0xffe01000) +#define SOCFPGA_SPIS0_BASE (0xffe02000) +#define SOCFPGA_SPIS1_BASE (0xffe03000) +#define SOCFPGA_SPIM0_BASE (0xfff00000) +#define SOCFPGA_SPIM1_BASE (0xfff01000) +#define SOCFPGA_SCANMGR_BASE (0xfff02000) +#define SOCFPGA_ROM_BASE (0xfffd0000) +#define SOCFPGA_MPUSCU_BASE (0xfffec000) +#define SOCFPGA_MPUL2_BASE (0xfffef000) +#define SOCFPGA_OCRAM_BASE (0xffff0000) + +#define SOCFPGA_GIC_CPU_BASE (SOCFPGA_MPUSCU_BASE + 0x100) +#define SOCFPGA_TWD_BASE (SOCFPGA_MPUSCU_BASE + 0x600) +#define SOCFPGA_GIC_DIST_BASE (SOCFPGA_MPUSCU_BASE + 0x1000) + +/* System Manager */ +#define SOCFPGA_SMP_FLAG (SOCFPGA_SYSMGR_BASE + 0x10) +#define SOCFPGA_SYSMGR_SDMMCGRP_CTR (SOCFPGA_SYSMGR_BASE + 0x108) + +/* Clock Manager */ +#define SOCFPGA_CLKMGR_PERPLLGRP_EN (SOCFPGA_CLKMGR_BASE + 0xA0) + +#endif /* __ASM_ARCH_BOARD_SOCFPGA_CYCLONE5_H */ diff --git a/arch/arm/mach-socfpga/socfpga_cyclone5.c b/arch/arm/mach-socfpga/socfpga_cyclone5.c new file mode 100644 index 0000000..76429b5 --- /dev/null +++ b/arch/arm/mach-socfpga/socfpga_cyclone5.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/device.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <mach/iomap.h> +#include <mach/socfpga-timer.h> +#include <mach/dw_apb_timer.h> +#include <mach/socfpga_cyclone5.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/hardware/gic.h> +#include <asm/smp_twd.h> + +#include "common.h" + +/* + * Lookup table for attaching a specific name and platform_data pointer to + * devices as they get created by of_platform_populate(). Ideally this table + * would not exist, but the current clock implementation depends on some devices + * having a specific name. + */ +static const struct of_dev_auxdata cyclone5_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("snps,dw-spi-mmio", SOCFPGA_SPIM0_BASE, "dw-spi-mmio.0", NULL), + OF_DEV_AUXDATA("snps,dw-spi-mmio", SOCFPGA_SPIM1_BASE, "dw-spi-mmio.1", NULL), + OF_DEV_AUXDATA("arm,pl330", SOCFPGA_DMASECURE_BASE, "dma-pl330", NULL), + { /* sentinel */ } +}; + +const static struct of_device_id irq_match[] = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + {} +}; + +static struct map_desc cyclone5_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(SOCFPGA_SPTIMER0_BASE), + .pfn = __phys_to_pfn(SOCFPGA_SPTIMER0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(SOCFPGA_SPTIMER1_BASE), + .pfn = __phys_to_pfn(SOCFPGA_SPTIMER1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(SOCFPGA_OSC1TIMER0_BASE), + .pfn = __phys_to_pfn(SOCFPGA_OSC1TIMER0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(SOCFPGA_OSC1TIMER1_BASE), + .pfn = __phys_to_pfn(SOCFPGA_OSC1TIMER1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(SOCFPGA_MPUSCU_BASE), + .pfn = __phys_to_pfn(SOCFPGA_MPUSCU_BASE), + .length = SZ_8K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(SOCFPGA_SYSMGR_BASE), + .pfn = __phys_to_pfn(SOCFPGA_SYSMGR_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(SOCFPGA_MPUL2_BASE), + .pfn = __phys_to_pfn(SOCFPGA_MPUL2_BASE), + .length = SZ_8K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(SOCFPGA_CLKMGR_BASE), + .pfn = __phys_to_pfn(SOCFPGA_CLKMGR_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static void __init cyclone5_map_io(void) +{ + iotable_init(cyclone5_io_desc, ARRAY_SIZE(cyclone5_io_desc)); +} + +static void __init gic_init_irq(void) +{ + of_irq_init(irq_match); +} + +/* + * Set up the clock source and clock events devices + */ +static void __init socfpga_cyclone5_timer_init(void) +{ + sp_timer0_va_base = __io_address(SOCFPGA_SPTIMER0_BASE); + sp_timer1_va_base = __io_address(SOCFPGA_SPTIMER1_BASE); + osc_timer0_va_base = __io_address(SOCFPGA_OSC1TIMER0_BASE); + osc_timer1_va_base = __io_address(SOCFPGA_OSC1TIMER1_BASE); + + socfpga_timer_init(sp_timer0_va_base, osc_timer0_va_base, + IRQ_SOCFPGA_L4_OSC1_TIMER0); +#ifdef CONFIG_OF + twd_local_timer_of_register(); +#endif +} + +static struct sys_timer socfpga_cyclone5_timer = { + .init = socfpga_cyclone5_timer_init, +}; + +static void socfpga_cyclone5_restart(char mode, const char *cmd) +{ + /* TODO: */ +} + +static void __init socfpga_cyclone5_init(void) +{ +#ifdef CONFIG_CACHE_L2X0 + /* 8-way, 64K/way, evmon/parity/share */ + l2x0_of_init(0x00760000, 0xfe000fff); +#endif + platform_notify = socfpga_notifier; + of_platform_populate(NULL, of_default_bus_match_table, + cyclone5_auxdata_lookup, NULL); +} + +static const char *altera_dt_match[] = { + "altr,socfpga-cyclone5", + NULL +}; + +MACHINE_START(SOCFPGA_CYCLONE5, "Altera SOCFPGA Cyclone V") + .atag_offset = 0x100, + .fixup = socfpga_fixup, + .map_io = cyclone5_map_io, + .init_early = socfpga_init_early, + .init_irq = gic_init_irq, + .handle_irq = gic_handle_irq, + .timer = &socfpga_cyclone5_timer, + .init_machine = socfpga_cyclone5_init, + .restart = socfpga_cyclone5_restart, + .dt_compat = altera_dt_match, +MACHINE_END diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 2997e56..c6ed4b1 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1206,3 +1206,4 @@ baileys MACH_BAILEYS BAILEYS 4169 familybox MACH_FAMILYBOX FAMILYBOX 4170 ensemble_mx35 MACH_ENSEMBLE_MX35 ENSEMBLE_MX35 4171 sc_sps_1 MACH_SC_SPS_1 SC_SPS_1 4172 +socfpga_cyclone5 MACH_SOCFPGA_CYCLONE5 SOCFPGA_CYCLONE5 4251 -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW 2012-06-27 13:50 ` [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW dinguyen at altera.com @ 2012-06-27 14:25 ` Thomas Petazzoni 2012-06-27 21:06 ` Pavel Machek ` (2 more replies) 0 siblings, 3 replies; 47+ messages in thread From: Thomas Petazzoni @ 2012-06-27 14:25 UTC (permalink / raw) To: linux-arm-kernel Hello Dinh, Le Wed, 27 Jun 2012 08:50:07 -0500, <dinguyen@altera.com> a ?crit : > +CONFIG_CMDLINE="console=ttyS0,57600 mem=256M at 0x0" Why do you need to specify the memory map here, since it's already passed in the device tree? > diff --git a/arch/arm/mach-socfpga/include/mach/clkdev.h b/arch/arm/mach-socfpga/include/mach/clkdev.h > new file mode 100644 > index 0000000..1eeecc4 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/clkdev.h > @@ -0,0 +1,16 @@ > +#ifndef __ASM_MACH_CLKDEV_H > +#define __ASM_MACH_CLKDEV_H > + > +#include <mach/clock.h> > + > +struct clk { > + unsigned long rate; > + const struct clk_ops *ops; > + const struct icst_params *params; > + void __iomem *vcoreg; > +}; > + > +#define __clk_get(clk) ({ 1; }) > +#define __clk_put(clk) do { } while (0) Why is this in this patch? It should have been in the previous one (adding the SoC support). But anyway, it shouldn't be there at all, you should use the clock framework in drivers/clk/ instead. > +#define SOCFPGA_LWFPGASLAVES_BASE (0xff200000) > +#define SOCFPGA_LWHPS2FPGAREGS_BASE (0xff400000) > +#define SOCFPGA_HPS2FPGAREGS_BASE (0xff500000) > +#define SOCFPGA_FPGA2HPSREGS_BASE (0xff600000) > +#define SOCFPGA_EMAC0_BASE (0xff700000) > +#define SOCFPGA_EMAC1_BASE (0xff702000) > +#define SOCFPGA_SDMMC_BASE (0xff704000) > +#define SOCFPGA_QSPIREGS_BASE (0xff705000) > +#define SOCFPGA_FPGAMGRREGS_BASE (0xff706000) > +#define SOCFPGA_ACPIDMAP_BASE (0xff707000) > +#define SOCFPGA_GPIO0_BASE (0xff708000) > +#define SOCFPGA_GPIO1_BASE (0xff709000) > +#define SOCFPGA_GPIO2_BASE (0xff70a000) > +#define SOCFPGA_L3REGS_BASE (0xff800000) > +#define SOCFPGA_NANDDATA_BASE (0xff900000) > +#define SOCFPGA_QSPIDATA_BASE (0xffa00000) > +#define SOCFPGA_USB0_BASE (0xffb00000) > +#define SOCFPGA_USB1_BASE (0xffb40000) > +#define SOCFPGA_NANDREGS_BASE (0xffb80000) > +#define SOCFPGA_FPGAMGRDATA_BASE (0xffb90000) > +#define SOCFPGA_CAN0_BASE (0xffc00000) > +#define SOCFPGA_CAN1_BASE (0xffc01000) > +#define SOCFPGA_UART0_BASE (0xffc02000) > +#define SOCFPGA_UART1_BASE (0xffc03000) > +#define SOCFPGA_I2C0_BASE (0xffc04000) > +#define SOCFPGA_I2C1_BASE (0xffc05000) > +#define SOCFPGA_I2C2MDIO0_BASE (0xffc06000) > +#define SOCFPGA_I2C3MDIO1_BASE (0xffc07000) > +#define SOCFPGA_SPTIMER0_BASE (0xffc08000) > +#define SOCFPGA_SPTIMER1_BASE (0xffc09000) > +#define SOCFPGA_SDR_BASE (0xffc20000) > +#define SOCFPGA_OSC1TIMER0_BASE (0xffd00000) > +#define SOCFPGA_OSC1TIMER1_BASE (0xffd01000) > +#define SOCFPGA_L4WD0_BASE (0xffd02000) > +#define SOCFPGA_L4WD1_BASE (0xffd03000) > +#define SOCFPGA_CLKMGR_BASE (0xffd04000) > +#define SOCFPGA_RSTMGR_BASE (0xffd05000) > +#define SOCFPGA_SYSMGR_BASE (0xffd08000) > +#define SOCFPGA_DMANONSECURE_BASE (0xffe00000) > +#define SOCFPGA_DMASECURE_BASE (0xffe01000) > +#define SOCFPGA_SPIS0_BASE (0xffe02000) > +#define SOCFPGA_SPIS1_BASE (0xffe03000) > +#define SOCFPGA_SPIM0_BASE (0xfff00000) > +#define SOCFPGA_SPIM1_BASE (0xfff01000) > +#define SOCFPGA_SCANMGR_BASE (0xfff02000) > +#define SOCFPGA_ROM_BASE (0xfffd0000) > +#define SOCFPGA_MPUSCU_BASE (0xfffec000) > +#define SOCFPGA_MPUL2_BASE (0xfffef000) > +#define SOCFPGA_OCRAM_BASE (0xffff0000) > + > +#define SOCFPGA_GIC_CPU_BASE (SOCFPGA_MPUSCU_BASE + 0x100) > +#define SOCFPGA_TWD_BASE (SOCFPGA_MPUSCU_BASE + 0x600) > +#define SOCFPGA_GIC_DIST_BASE (SOCFPGA_MPUSCU_BASE + 0x1000) > + > +/* System Manager */ > +#define SOCFPGA_SMP_FLAG (SOCFPGA_SYSMGR_BASE + 0x10) > +#define SOCFPGA_SYSMGR_SDMMCGRP_CTR (SOCFPGA_SYSMGR_BASE + 0x108) > + > +/* Clock Manager */ > +#define SOCFPGA_CLKMGR_PERPLLGRP_EN (SOCFPGA_CLKMGR_BASE + 0xA0) Just like the IRQ numbers, those defines for I/O registers are no longer needed with the device tree. > +/* > + * Lookup table for attaching a specific name and platform_data pointer to > + * devices as they get created by of_platform_populate(). Ideally this table > + * would not exist, but the current clock implementation depends on some devices > + * having a specific name. > + */ > +static const struct of_dev_auxdata cyclone5_auxdata_lookup[] __initconst = { > + OF_DEV_AUXDATA("snps,dw-spi-mmio", SOCFPGA_SPIM0_BASE, "dw-spi-mmio.0", NULL), > + OF_DEV_AUXDATA("snps,dw-spi-mmio", SOCFPGA_SPIM1_BASE, "dw-spi-mmio.1", NULL), > + OF_DEV_AUXDATA("arm,pl330", SOCFPGA_DMASECURE_BASE, "dma-pl330", NULL), > + { /* sentinel */ } > +}; Huh? I'm not sure to understand what this is useful for. > +const static struct of_device_id irq_match[] = { > + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, > + {} > +}; > + > +static struct map_desc cyclone5_io_desc[] __initdata = { > + { > + .virtual = IO_ADDRESS(SOCFPGA_SPTIMER0_BASE), > + .pfn = __phys_to_pfn(SOCFPGA_SPTIMER0_BASE), > + .length = SZ_4K, > + .type = MT_DEVICE, > + }, { > + .virtual = IO_ADDRESS(SOCFPGA_SPTIMER1_BASE), > + .pfn = __phys_to_pfn(SOCFPGA_SPTIMER1_BASE), > + .length = SZ_4K, > + .type = MT_DEVICE, > + }, { > + .virtual = IO_ADDRESS(SOCFPGA_OSC1TIMER0_BASE), > + .pfn = __phys_to_pfn(SOCFPGA_OSC1TIMER0_BASE), > + .length = SZ_4K, > + .type = MT_DEVICE, > + }, { > + .virtual = IO_ADDRESS(SOCFPGA_OSC1TIMER1_BASE), > + .pfn = __phys_to_pfn(SOCFPGA_OSC1TIMER1_BASE), > + .length = SZ_4K, > + .type = MT_DEVICE, > + }, { > + .virtual = IO_ADDRESS(SOCFPGA_MPUSCU_BASE), > + .pfn = __phys_to_pfn(SOCFPGA_MPUSCU_BASE), > + .length = SZ_8K, > + .type = MT_DEVICE, > + }, { > + .virtual = IO_ADDRESS(SOCFPGA_SYSMGR_BASE), > + .pfn = __phys_to_pfn(SOCFPGA_SYSMGR_BASE), > + .length = SZ_4K, > + .type = MT_DEVICE, > + }, { > + .virtual = IO_ADDRESS(SOCFPGA_MPUL2_BASE), > + .pfn = __phys_to_pfn(SOCFPGA_MPUL2_BASE), > + .length = SZ_8K, > + .type = MT_DEVICE, > + }, { > + .virtual = IO_ADDRESS(SOCFPGA_CLKMGR_BASE), > + .pfn = __phys_to_pfn(SOCFPGA_CLKMGR_BASE), > + .length = SZ_4K, > + .type = MT_DEVICE, > + }, > +}; Most of those static mappings should instead be turned into dynamic mappings created with ioremap(), at least for the timers. > +static const char *altera_dt_match[] = { > + "altr,socfpga-cyclone5", > + NULL > +}; > + > +MACHINE_START(SOCFPGA_CYCLONE5, "Altera SOCFPGA Cyclone V") > + .atag_offset = 0x100, > + .fixup = socfpga_fixup, > + .map_io = cyclone5_map_io, > + .init_early = socfpga_init_early, > + .init_irq = gic_init_irq, > + .handle_irq = gic_handle_irq, > + .timer = &socfpga_cyclone5_timer, > + .init_machine = socfpga_cyclone5_init, > + .restart = socfpga_cyclone5_restart, > + .dt_compat = altera_dt_match, > +MACHINE_END You should use DT_MACHINE_START and not MACHINE_START, since new SoC should only use the Device Tree now. So the .atag_offset and .fixup should no longer be necessary. > diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types > index 2997e56..c6ed4b1 100644 > --- a/arch/arm/tools/mach-types > +++ b/arch/arm/tools/mach-types > @@ -1206,3 +1206,4 @@ baileys MACH_BAILEYS BAILEYS 4169 > familybox MACH_FAMILYBOX FAMILYBOX 4170 > ensemble_mx35 MACH_ENSEMBLE_MX35 ENSEMBLE_MX35 4171 > sc_sps_1 MACH_SC_SPS_1 SC_SPS_1 4172 > +socfpga_cyclone5 MACH_SOCFPGA_CYCLONE5 SOCFPGA_CYCLONE5 4251 A machine ID is no longer needed with the Device Tree. Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW 2012-06-27 14:25 ` Thomas Petazzoni @ 2012-06-27 21:06 ` Pavel Machek 2012-06-27 22:19 ` Thomas Petazzoni 2012-06-28 0:00 ` Pavel Machek 2012-07-10 11:15 ` Pavel Machek 2 siblings, 1 reply; 47+ messages in thread From: Pavel Machek @ 2012-06-27 21:06 UTC (permalink / raw) To: linux-arm-kernel Hi! > > +CONFIG_CMDLINE="console=ttyS0,57600 mem=256M at 0x0" > > Why do you need to specify the memory map here, since it's already > passed in the device tree? Probably old leftover, will check. > > +#define SOCFPGA_GIC_CPU_BASE (SOCFPGA_MPUSCU_BASE + 0x100) > > +#define SOCFPGA_TWD_BASE (SOCFPGA_MPUSCU_BASE + 0x600) > > +#define SOCFPGA_GIC_DIST_BASE (SOCFPGA_MPUSCU_BASE + 0x1000) > > + > > +/* System Manager */ > > +#define SOCFPGA_SMP_FLAG (SOCFPGA_SYSMGR_BASE + 0x10) > > +#define SOCFPGA_SYSMGR_SDMMCGRP_CTR (SOCFPGA_SYSMGR_BASE + 0x108) > > + > > +/* Clock Manager */ > > +#define SOCFPGA_CLKMGR_PERPLLGRP_EN (SOCFPGA_CLKMGR_BASE + 0xA0) > > Just like the IRQ numbers, those defines for I/O registers are no > longer needed with the device tree. Yep. It shows we have more DT-ization to do. arch/arm/mach-socfpga/include/mach/uncompress.h needs UART0 base... but device tree is not easily accessible at that point, right? > > + }, { > > + .virtual = IO_ADDRESS(SOCFPGA_CLKMGR_BASE), > > + .pfn = __phys_to_pfn(SOCFPGA_CLKMGR_BASE), > > + .length = SZ_4K, > > + .type = MT_DEVICE, > > + }, > > +}; > > Most of those static mappings should instead be turned into dynamic > mappings created with ioremap(), at least for the timers. Dynamic mappings so that we can use device tree -- not constants? > > +static const char *altera_dt_match[] = { > > + "altr,socfpga-cyclone5", > > + NULL > > +}; > > + > > +MACHINE_START(SOCFPGA_CYCLONE5, "Altera SOCFPGA Cyclone V") > > + .atag_offset = 0x100, > > + .fixup = socfpga_fixup, > > + .map_io = cyclone5_map_io, > > + .init_early = socfpga_init_early, > > + .init_irq = gic_init_irq, > > + .handle_irq = gic_handle_irq, > > + .timer = &socfpga_cyclone5_timer, > > + .init_machine = socfpga_cyclone5_init, > > + .restart = socfpga_cyclone5_restart, > > + .dt_compat = altera_dt_match, > > +MACHINE_END > > You should use DT_MACHINE_START and not MACHINE_START, since new SoC > should only use the Device Tree now. So the .atag_offset and .fixup > should no longer be necessary. Ok. > > diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types > > index 2997e56..c6ed4b1 100644 > > --- a/arch/arm/tools/mach-types > > +++ b/arch/arm/tools/mach-types > > @@ -1206,3 +1206,4 @@ baileys MACH_BAILEYS BAILEYS 4169 > > familybox MACH_FAMILYBOX FAMILYBOX 4170 > > ensemble_mx35 MACH_ENSEMBLE_MX35 ENSEMBLE_MX35 4171 > > sc_sps_1 MACH_SC_SPS_1 SC_SPS_1 4172 > > +socfpga_cyclone5 MACH_SOCFPGA_CYCLONE5 SOCFPGA_CYCLONE5 4251 > > A machine ID is no longer needed with the Device Tree. Thanks for great review, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW 2012-06-27 21:06 ` Pavel Machek @ 2012-06-27 22:19 ` Thomas Petazzoni 0 siblings, 0 replies; 47+ messages in thread From: Thomas Petazzoni @ 2012-06-27 22:19 UTC (permalink / raw) To: linux-arm-kernel Le Wed, 27 Jun 2012 23:06:00 +0200, Pavel Machek <pavel@denx.de> a ?crit : > > Just like the IRQ numbers, those defines for I/O registers are no > > longer needed with the device tree. > > Yep. It shows we have more DT-ization to do. > > arch/arm/mach-socfpga/include/mach/uncompress.h needs UART0 > base... but device tree is not easily accessible at that point, right? Yes, for those you still need fixed addresses, defined by #define, as the DT is not accessible yet. > > > + }, { > > > + .virtual = IO_ADDRESS(SOCFPGA_CLKMGR_BASE), > > > + .pfn = __phys_to_pfn(SOCFPGA_CLKMGR_BASE), > > > + .length = SZ_4K, > > > + .type = MT_DEVICE, > > > + }, > > > +}; > > > > Most of those static mappings should instead be turned into dynamic > > mappings created with ioremap(), at least for the timers. > > Dynamic mappings so that we can use device tree -- not constants? Yes, that's at least one of the reason. I think there are others, but last time there was a discussion about static vs. dynamic mappings, I'm not sure I understood exactly the arguments on which ones should be used in which situation. > Thanks for great review, You're welcome! Best regards, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW 2012-06-27 14:25 ` Thomas Petazzoni 2012-06-27 21:06 ` Pavel Machek @ 2012-06-28 0:00 ` Pavel Machek 2012-07-10 11:15 ` Pavel Machek 2 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-06-28 0:00 UTC (permalink / raw) To: linux-arm-kernel Hi! Here's suggested patch for the easy stuff. It is currently test booting. Signed-off-by: Pavel Machek <pavel@denx.de> diff --git a/arch/arm/mach-socfpga/common.c b/arch/arm/mach-socfpga/common.c index a2c734a..331040e 100644 --- a/arch/arm/mach-socfpga/common.c +++ b/arch/arm/mach-socfpga/common.c @@ -136,16 +136,6 @@ void __init socfpga_timer_init(void __iomem *src_timer_base, dwapbt_clockevents_init(event_timer_base, event_timer_irq); } -/* - * Setup the memory banks. - */ -void socfpga_fixup(struct tag *tags, char **from, struct meminfo *meminfo) -{ - meminfo->bank[0].start = 0x0; - meminfo->bank[0].size = SZ_256M; - meminfo->nr_banks = 1; -} - int socfpga_notifier(struct device *device) { struct device_node *dn = device->of_node; diff --git a/arch/arm/mach-socfpga/include/mach/socfpga_cyclone5.h b/arch/arm/mach-socfpga/include/mach/socfpga_cyclone5.h index 7787f9d..8f0502e 100644 --- a/arch/arm/mach-socfpga/include/mach/socfpga_cyclone5.h +++ b/arch/arm/mach-socfpga/include/mach/socfpga_cyclone5.h @@ -19,65 +19,22 @@ #undef __ASM_ARCH_BOARD_SOCFPGA_CYCLONE5_H -#define SOCFPGA_LWFPGASLAVES_BASE (0xff200000) -#define SOCFPGA_LWHPS2FPGAREGS_BASE (0xff400000) -#define SOCFPGA_HPS2FPGAREGS_BASE (0xff500000) -#define SOCFPGA_FPGA2HPSREGS_BASE (0xff600000) -#define SOCFPGA_EMAC0_BASE (0xff700000) -#define SOCFPGA_EMAC1_BASE (0xff702000) -#define SOCFPGA_SDMMC_BASE (0xff704000) -#define SOCFPGA_QSPIREGS_BASE (0xff705000) -#define SOCFPGA_FPGAMGRREGS_BASE (0xff706000) -#define SOCFPGA_ACPIDMAP_BASE (0xff707000) -#define SOCFPGA_GPIO0_BASE (0xff708000) -#define SOCFPGA_GPIO1_BASE (0xff709000) -#define SOCFPGA_GPIO2_BASE (0xff70a000) -#define SOCFPGA_L3REGS_BASE (0xff800000) -#define SOCFPGA_NANDDATA_BASE (0xff900000) -#define SOCFPGA_QSPIDATA_BASE (0xffa00000) -#define SOCFPGA_USB0_BASE (0xffb00000) -#define SOCFPGA_USB1_BASE (0xffb40000) -#define SOCFPGA_NANDREGS_BASE (0xffb80000) -#define SOCFPGA_FPGAMGRDATA_BASE (0xffb90000) -#define SOCFPGA_CAN0_BASE (0xffc00000) -#define SOCFPGA_CAN1_BASE (0xffc01000) -#define SOCFPGA_UART0_BASE (0xffc02000) -#define SOCFPGA_UART1_BASE (0xffc03000) -#define SOCFPGA_I2C0_BASE (0xffc04000) -#define SOCFPGA_I2C1_BASE (0xffc05000) -#define SOCFPGA_I2C2MDIO0_BASE (0xffc06000) -#define SOCFPGA_I2C3MDIO1_BASE (0xffc07000) #define SOCFPGA_SPTIMER0_BASE (0xffc08000) #define SOCFPGA_SPTIMER1_BASE (0xffc09000) #define SOCFPGA_SDR_BASE (0xffc20000) #define SOCFPGA_OSC1TIMER0_BASE (0xffd00000) #define SOCFPGA_OSC1TIMER1_BASE (0xffd01000) -#define SOCFPGA_L4WD0_BASE (0xffd02000) -#define SOCFPGA_L4WD1_BASE (0xffd03000) #define SOCFPGA_CLKMGR_BASE (0xffd04000) -#define SOCFPGA_RSTMGR_BASE (0xffd05000) -#define SOCFPGA_SYSMGR_BASE (0xffd08000) +#define SOCFPGA_UART0_BASE (0xffc02000) + +#define SOCFPGA_SYSMGR_BASE (0xffd08000) #define SOCFPGA_DMANONSECURE_BASE (0xffe00000) #define SOCFPGA_DMASECURE_BASE (0xffe01000) -#define SOCFPGA_SPIS0_BASE (0xffe02000) -#define SOCFPGA_SPIS1_BASE (0xffe03000) #define SOCFPGA_SPIM0_BASE (0xfff00000) #define SOCFPGA_SPIM1_BASE (0xfff01000) -#define SOCFPGA_SCANMGR_BASE (0xfff02000) -#define SOCFPGA_ROM_BASE (0xfffd0000) #define SOCFPGA_MPUSCU_BASE (0xfffec000) -#define SOCFPGA_MPUL2_BASE (0xfffef000) -#define SOCFPGA_OCRAM_BASE (0xffff0000) - -#define SOCFPGA_GIC_CPU_BASE (SOCFPGA_MPUSCU_BASE + 0x100) -#define SOCFPGA_TWD_BASE (SOCFPGA_MPUSCU_BASE + 0x600) -#define SOCFPGA_GIC_DIST_BASE (SOCFPGA_MPUSCU_BASE + 0x1000) - -/* System Manager */ -#define SOCFPGA_SMP_FLAG (SOCFPGA_SYSMGR_BASE + 0x10) -#define SOCFPGA_SYSMGR_SDMMCGRP_CTR (SOCFPGA_SYSMGR_BASE + 0x108) +#define SOCFPGA_MPUL2_BASE (0xfffef000) -/* Clock Manager */ -#define SOCFPGA_CLKMGR_PERPLLGRP_EN (SOCFPGA_CLKMGR_BASE + 0xA0) +#define SOCFPGA_SMP_FLAG (SOCFPGA_SYSMGR_BASE + 0x10) #endif /* __ASM_ARCH_BOARD_SOCFPGA_CYCLONE5_H */ diff --git a/arch/arm/mach-socfpga/socfpga_cyclone5.c b/arch/arm/mach-socfpga/socfpga_cyclone5.c index 76429b5..f6498cc 100644 --- a/arch/arm/mach-socfpga/socfpga_cyclone5.c +++ b/arch/arm/mach-socfpga/socfpga_cyclone5.c @@ -147,9 +147,7 @@ static const char *altera_dt_match[] = { NULL }; -MACHINE_START(SOCFPGA_CYCLONE5, "Altera SOCFPGA Cyclone V") - .atag_offset = 0x100, - .fixup = socfpga_fixup, +DT_MACHINE_START(SOCFPGA_CYCLONE5, "Altera SOCFPGA Cyclone V") .map_io = cyclone5_map_io, .init_early = socfpga_init_early, .init_irq = gic_init_irq, diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index c6ed4b1..2997e56 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1206,4 +1206,3 @@ baileys MACH_BAILEYS BAILEYS 4169 familybox MACH_FAMILYBOX FAMILYBOX 4170 ensemble_mx35 MACH_ENSEMBLE_MX35 ENSEMBLE_MX35 4171 sc_sps_1 MACH_SC_SPS_1 SC_SPS_1 4172 -socfpga_cyclone5 MACH_SOCFPGA_CYCLONE5 SOCFPGA_CYCLONE5 4251 -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW 2012-06-27 14:25 ` Thomas Petazzoni 2012-06-27 21:06 ` Pavel Machek 2012-06-28 0:00 ` Pavel Machek @ 2012-07-10 11:15 ` Pavel Machek 2 siblings, 0 replies; 47+ messages in thread From: Pavel Machek @ 2012-07-10 11:15 UTC (permalink / raw) To: linux-arm-kernel Hi! > Le Wed, 27 Jun 2012 08:50:07 -0500, > <dinguyen@altera.com> a ?crit : > > > +CONFIG_CMDLINE="console=ttyS0,57600 mem=256M at 0x0" > > Why do you need to specify the memory map here, since it's already > passed in the device tree? Fixed. > > +const static struct of_device_id irq_match[] = { > > + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, > > + {} > > +}; > > + > > +static struct map_desc cyclone5_io_desc[] __initdata = { > > + { > > + .virtual = IO_ADDRESS(SOCFPGA_SPTIMER0_BASE), > > + .pfn = __phys_to_pfn(SOCFPGA_SPTIMER0_BASE), > > + .length = SZ_4K, > > + .type = MT_DEVICE, > > + }, { > > + .virtual = IO_ADDRESS(SOCFPGA_SPTIMER1_BASE), > > + .pfn = __phys_to_pfn(SOCFPGA_SPTIMER1_BASE), > > + .length = SZ_4K, > > + .type = MT_DEVICE, > > + }, { > > + .virtual = IO_ADDRESS(SOCFPGA_OSC1TIMER0_BASE), > > + .pfn = __phys_to_pfn(SOCFPGA_OSC1TIMER0_BASE), > > + .length = SZ_4K, > > + .type = MT_DEVICE, > > + }, { > > + .virtual = IO_ADDRESS(SOCFPGA_OSC1TIMER1_BASE), > > + .pfn = __phys_to_pfn(SOCFPGA_OSC1TIMER1_BASE), > > + .length = SZ_4K, > > + .type = MT_DEVICE, > > + }, { > > + .virtual = IO_ADDRESS(SOCFPGA_MPUSCU_BASE), > > + .pfn = __phys_to_pfn(SOCFPGA_MPUSCU_BASE), > > + .length = SZ_8K, > > + .type = MT_DEVICE, > > + }, { > > + .virtual = IO_ADDRESS(SOCFPGA_SYSMGR_BASE), > > + .pfn = __phys_to_pfn(SOCFPGA_SYSMGR_BASE), > > + .length = SZ_4K, > > + .type = MT_DEVICE, > > + }, { > > + .virtual = IO_ADDRESS(SOCFPGA_MPUL2_BASE), > > + .pfn = __phys_to_pfn(SOCFPGA_MPUL2_BASE), > > + .length = SZ_8K, > > + .type = MT_DEVICE, > > + }, { > > + .virtual = IO_ADDRESS(SOCFPGA_CLKMGR_BASE), > > + .pfn = __phys_to_pfn(SOCFPGA_CLKMGR_BASE), > > + .length = SZ_4K, > > + .type = MT_DEVICE, > > + }, > > +}; > > Most of those static mappings should instead be turned into dynamic > mappings created with ioremap(), at least for the timers. Now this one is interesting. I just removed these mappings, and it still works. I guess that's good. Pavel commit 5f2d9e152e170a328689e5ab0c3f42851b99a4ec Author: Pavel <pavel@ucw.cz> Date: Tue Jul 10 13:08:54 2012 +0200 cyclone5_map_io seems to be unneccessary. Remove it. Signed-off-by: Pavel Machek <pavel@denx.de> diff --git a/arch/arm/mach-socfpga/socfpga_cyclone5.c b/arch/arm/mach-socfpga/socfpga_cyclone5.c index 459f5a6..0bc0b8b 100644 --- a/arch/arm/mach-socfpga/socfpga_cyclone5.c +++ b/arch/arm/mach-socfpga/socfpga_cyclone5.c @@ -50,30 +50,6 @@ const static struct of_device_id irq_match[] = { {} }; -static struct map_desc cyclone5_io_desc[] __initdata = { - { - .virtual = IO_ADDRESS(SOCFPGA_MPUSCU_BASE), - .pfn = __phys_to_pfn(SOCFPGA_MPUSCU_BASE), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = IO_ADDRESS(SOCFPGA_SYSMGR_BASE), - .pfn = __phys_to_pfn(SOCFPGA_SYSMGR_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = IO_ADDRESS(SOCFPGA_CLKMGR_BASE), - .pfn = __phys_to_pfn(SOCFPGA_CLKMGR_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static void __init cyclone5_map_io(void) -{ - iotable_init(cyclone5_io_desc, ARRAY_SIZE(cyclone5_io_desc)); -} - static void __init gic_init_irq(void) { of_irq_init(irq_match); @@ -100,7 +76,6 @@ static const char *altera_dt_match[] = { }; DT_MACHINE_START(SOCFPGA_CYCLONE5, "Altera SOCFPGA Cyclone V") - .map_io = cyclone5_map_io, .init_early = socfpga_init_early, .init_irq = gic_init_irq, .handle_irq = gic_handle_irq, -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply related [flat|nested] 47+ messages in thread
end of thread, other threads:[~2012-11-05 17:18 UTC | newest] Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-06-27 13:50 [RFC]Add initial support for Altera's SOCFPGA hardward dinguyen at altera.com 2012-06-27 13:50 ` [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform dinguyen at altera.com 2012-06-27 14:20 ` Thomas Petazzoni 2012-06-27 18:05 ` Pavel Machek 2012-06-27 18:40 ` Thomas Petazzoni 2012-06-29 19:54 ` Dinh Nguyen 2012-06-29 22:18 ` Thomas Petazzoni 2012-07-04 16:11 ` Thomas Petazzoni 2012-06-30 21:04 ` Arnd Bergmann 2012-07-01 18:41 ` Pavel Machek 2012-07-02 16:52 ` Arnd Bergmann 2012-07-02 21:53 ` Pavel Machek 2012-10-17 18:16 ` [PATCH] Fix socfpga compilation with early_printk() enabled Pavel Machek 2012-10-25 14:58 ` Arnd Bergmann 2012-10-27 11:56 ` Pavel Machek 2012-10-27 15:39 ` Arnd Bergmann 2012-10-28 23:01 ` arm-soc tree was " Pavel Machek 2012-10-28 23:13 ` Pavel Machek 2012-10-29 4:41 ` Arnd Bergmann 2012-10-30 16:03 ` Pawel Moll 2012-10-29 4:45 ` Arnd Bergmann 2012-10-29 0:27 ` [PATCH for soc] socfpga: map uart into virtual address space so that early_printk() works Pavel Machek 2012-11-03 11:26 ` Pavel Machek 2012-11-05 17:18 ` Olof Johansson 2012-06-27 20:27 ` [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform Pavel Machek 2012-06-30 18:57 ` Pavel Machek 2012-07-01 18:10 ` Pavel Machek 2012-07-04 10:56 ` Pavel Machek 2012-07-04 11:10 ` Thomas Petazzoni 2012-07-04 11:23 ` Pavel Machek 2012-07-04 14:30 ` Dinh Nguyen 2012-07-09 10:58 ` Pavel Machek 2012-07-04 11:15 ` Pavel Machek 2012-07-04 11:21 ` Thomas Petazzoni 2012-07-04 17:56 ` Rob Herring 2012-07-09 11:30 ` Pavel Machek 2012-07-09 13:25 ` Rob Herring 2012-07-10 9:48 ` Pavel Machek 2012-07-09 11:52 ` Pavel Machek 2012-07-09 12:06 ` Pavel Machek 2012-07-09 12:10 ` Pavel Machek 2012-06-27 13:50 ` [RFC PATCHv1 2/2] ARM: socfpga: Add board support for Altera's SOCFPGA Cyclone 5 HW dinguyen at altera.com 2012-06-27 14:25 ` Thomas Petazzoni 2012-06-27 21:06 ` Pavel Machek 2012-06-27 22:19 ` Thomas Petazzoni 2012-06-28 0:00 ` Pavel Machek 2012-07-10 11:15 ` Pavel Machek
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