* 3.6-rc7 boot crash + bisection @ 2012-09-24 19:03 Florian Dazinger 2012-09-25 18:32 ` Alex Williamson 0 siblings, 1 reply; 37+ messages in thread From: Florian Dazinger @ 2012-09-24 19:03 UTC (permalink / raw) To: linux-kernel [-- Attachment #1: Type: text/plain, Size: 8361 bytes --] Hi, I think I've found a regression, which causes an early boot crash, I appended the kernel output via jpg file, since I do not have a serial console or sth. after bisection, it boils down to this commit: 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit commit 9dcd61303af862c279df86aa97fde7ce371be774 Author: Alex Williamson <alex.williamson@redhat.com> Date: Wed May 30 14:19:07 2012 -0600 amd_iommu: Support IOMMU groups Add IOMMU group support to AMD-Vi device init and uninit code. Existing notifiers make sure this gets called for each device. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers bisect log: git bisect start # bad: [0d7614f09c1ebdbaa1599a5aba7593f147bf96ee] Linux 3.6-rc1 git bisect bad 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee # good: [28a33cbc24e4256c143dce96c7d93bf423229f92] Linux 3.5 git bisect good 28a33cbc24e4256c143dce96c7d93bf423229f92 # bad: [614a6d4341b3760ca98a1c2c09141b71db5d1e90] Merge branch 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup git bisect bad 614a6d4341b3760ca98a1c2c09141b71db5d1e90 # good: [320f5ea0cedc08ef65d67e056bcb9d181386ef2c] genetlink: define lockdep_genl_is_held() when CONFIG_LOCKDEP git bisect good 320f5ea0cedc08ef65d67e056bcb9d181386ef2c # good: [a17f29a5e98c0a32a900a773083c719e27f4bc0e] Merge tag 'defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc git bisect good a17f29a5e98c0a32a900a773083c719e27f4bc0e # good: [e8ff13b0bf88b5e696323a1eec877783d965b3c6] Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid git bisect good e8ff13b0bf88b5e696323a1eec877783d965b3c6 # good: [914311c9fb9bc01a215de9d848b72b5449c0e342] Merge tag 'pinctrl-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl git bisect good 914311c9fb9bc01a215de9d848b72b5449c0e342 # good: [6dd53aa4563a2c69e80a24d2cc68d484b5ea2891] Merge tag 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci git bisect good 6dd53aa4563a2c69e80a24d2cc68d484b5ea2891 # bad: [9161c3b796a2841a9a7be3d9c9dd121269ce90e8] Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux git bisect bad 9161c3b796a2841a9a7be3d9c9dd121269ce90e8 # bad: [395e51f18d3b26619c1c462b7a1c0226846ac0a9] Merge branches 'iommu/fixes', 'x86/amd', 'groups', 'arm/tegra' and 'api/domain-attr' into next git bisect bad 395e51f18d3b26619c1c462b7a1c0226846ac0a9 # good: [8ce44a2174c3b07950d7a8d44774e23e60518205] Merge tag 'v3.5-rc7' into arm/tegra git bisect good 8ce44a2174c3b07950d7a8d44774e23e60518205 # good: [2c0ae1720c09c6f8fc8c6bcece29dc80b08ca1af] iommu/amd: Convert iommu initialization to state machine git bisect good 2c0ae1720c09c6f8fc8c6bcece29dc80b08ca1af # bad: [7d43c2e42cb1e436f97c1763150e4e1122ae0d57] iommu: Remove group_mf git bisect bad 7d43c2e42cb1e436f97c1763150e4e1122ae0d57 # bad: [9dcd61303af862c279df86aa97fde7ce371be774] amd_iommu: Support IOMMU groups git bisect bad 9dcd61303af862c279df86aa97fde7ce371be774 # good: [74416e1e07660798379ce10a210bf4fd35b84f9f] driver core: Add iommu_group tracking to struct device git bisect good 74416e1e07660798379ce10a210bf4fd35b84f9f # good: [d72e31c9374627068df29da8085ca18c92ae35d3] iommu: IOMMU Groups git bisect good d72e31c9374627068df29da8085ca18c92ae35d3 some system info: Linux brain 3.5.0-rc3-00008-gd72e31c #14 SMP PREEMPT Mon Sep 24 20:23:45 CEST 2012 x86_64 AMD Phenom(tm) II X4 955 Processor AuthenticAMD GNU/Linux lspci: 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] if you've any questions, pls. CC me, as I am not subscribed! cheers, f. [-- Attachment #2: boot_msg.jpg --] [-- Type: image/jpeg, Size: 282706 bytes --] [-- Attachment #3: bisect.log --] [-- Type: text/x-log, Size: 3028 bytes --] Bisecting: 4579 revisions left to test after this (roughly 12 steps) [614a6d4341b3760ca98a1c2c09141b71db5d1e90] Merge branch 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup Bisecting: 2627 revisions left to test after this (roughly 11 steps) [320f5ea0cedc08ef65d67e056bcb9d181386ef2c] genetlink: define lockdep_genl_is_held() when CONFIG_LOCKDEP Bisecting: 1330 revisions left to test after this (roughly 10 steps) [a17f29a5e98c0a32a900a773083c719e27f4bc0e] Merge tag 'defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Bisecting: 648 revisions left to test after this (roughly 9 steps) [e8ff13b0bf88b5e696323a1eec877783d965b3c6] Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid Bisecting: 320 revisions left to test after this (roughly 8 steps) [914311c9fb9bc01a215de9d848b72b5449c0e342] Merge tag 'pinctrl-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Bisecting: 167 revisions left to test after this (roughly 7 steps) [6dd53aa4563a2c69e80a24d2cc68d484b5ea2891] Merge tag 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Bisecting: 106 revisions left to test after this (roughly 6 steps) [9161c3b796a2841a9a7be3d9c9dd121269ce90e8] Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux Bisecting: 24 revisions left to test after this (roughly 5 steps) [395e51f18d3b26619c1c462b7a1c0226846ac0a9] Merge branches 'iommu/fixes', 'x86/amd', 'groups', 'arm/tegra' and 'api/domain-attr' into next Bisecting: 26 revisions left to test after this (roughly 4 steps) [8ce44a2174c3b07950d7a8d44774e23e60518205] Merge tag 'v3.5-rc7' into arm/tegra Bisecting: 17 revisions left to test after this (roughly 4 steps) [2c0ae1720c09c6f8fc8c6bcece29dc80b08ca1af] iommu/amd: Convert iommu initialization to state machine Bisecting: 9 revisions left to test after this (roughly 3 steps) [7d43c2e42cb1e436f97c1763150e4e1122ae0d57] iommu: Remove group_mf Bisecting: 3 revisions left to test after this (roughly 2 steps) [9dcd61303af862c279df86aa97fde7ce371be774] amd_iommu: Support IOMMU groups Bisecting: 1 revision left to test after this (roughly 1 step) [74416e1e07660798379ce10a210bf4fd35b84f9f] driver core: Add iommu_group tracking to struct device Bisecting: 0 revisions left to test after this (roughly 0 steps) [d72e31c9374627068df29da8085ca18c92ae35d3] iommu: IOMMU Groups 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit commit 9dcd61303af862c279df86aa97fde7ce371be774 Author: Alex Williamson <alex.williamson@redhat.com> Date: Wed May 30 14:19:07 2012 -0600 amd_iommu: Support IOMMU groups Add IOMMU group support to AMD-Vi device init and uninit code. Existing notifiers make sure this gets called for each device. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection 2012-09-24 19:03 3.6-rc7 boot crash + bisection Florian Dazinger @ 2012-09-25 18:32 ` Alex Williamson 2012-09-25 18:42 ` Alex Williamson 2012-09-25 18:54 ` Florian Dazinger 0 siblings, 2 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-25 18:32 UTC (permalink / raw) To: Florian Dazinger; +Cc: linux-kernel, Roedel, Joerg On Mon, 2012-09-24 at 21:03 +0200, Florian Dazinger wrote: > Hi, > I think I've found a regression, which causes an early boot crash, I > appended the kernel output via jpg file, since I do not have a serial > console or sth. > > after bisection, it boils down to this commit: > > 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit > commit 9dcd61303af862c279df86aa97fde7ce371be774 > Author: Alex Williamson <alex.williamson@redhat.com> > Date: Wed May 30 14:19:07 2012 -0600 > > amd_iommu: Support IOMMU groups > > Add IOMMU group support to AMD-Vi device init and uninit code. > Existing notifiers make sure this gets called for each device. > > Signed-off-by: Alex Williamson <alex.williamson@redhat.com> > Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> > > :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 > 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers [switching back to mailing list thread] I asked Florian for dmesg w/ amd_iommu_dump, here's the relevant lines: [ 1.485645] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 [ 1.485683] AMD-Vi: mmio-addr: 00000000feb20000 [ 1.485901] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 [ 1.485935] AMD-Vi: DEV_RANGE_END devid: 00:00.2 [ 1.485969] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 [ 1.486002] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 [ 1.486036] AMD-Vi: DEV_RANGE_END devid: 01:00.1 [ 1.486070] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 [ 1.486103] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 [ 1.486137] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 [ 1.486170] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 [ 1.486204] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 [ 1.486238] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 [ 1.486271] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 [ 1.486305] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 [ 1.486338] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 [ 1.486372] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 [ 1.486406] AMD-Vi: DEV_SELECT devid: 00:0b.0 flags: 00 [ 1.486439] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 [ 1.486548] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 [ 1.486581] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 [ 1.486620] AMD-Vi: DEV_RANGE_END devid: 00:12.2 [ 1.486654] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 [ 1.486688] AMD-Vi: DEV_RANGE_END devid: 00:13.2 [ 1.486721] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 [ 1.486755] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 [ 1.486788] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 [ 1.486822] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 [ 1.486859] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 [ 1.486897] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 [ 1.486931] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 [ 1.486965] AMD-Vi: DEV_RANGE_END devid: 00:16.2 [ 1.487055] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 > lspci: > 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) > 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) > 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) > 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) > 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) > 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) > 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) > 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) > 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) > 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) > 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller > 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration > 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map > 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller > 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control > 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control > 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] > 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] > 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) > 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection > 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 > [Oxygen HD Audio] We can see this is clearly wrong: [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 So the BIOS is telling us to alias everything in the range of 08:00.0 to 08:1f.7 to device id 08:01.0, which doesn't exist :( Can you send lspci -vvv? I suspect we'll find that 07:00.0 sources bus 08 and that alias should really be to 07:00.0 instead of 08:01.0. Please also provide dmidecode for this system, we may need to create a quirk for this box. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection 2012-09-25 18:32 ` Alex Williamson @ 2012-09-25 18:42 ` Alex Williamson 2012-09-25 18:54 ` Florian Dazinger 1 sibling, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-25 18:42 UTC (permalink / raw) To: Florian Dazinger; +Cc: linux-kernel, Roedel, Joerg On Tue, 2012-09-25 at 12:32 -0600, Alex Williamson wrote: > On Mon, 2012-09-24 at 21:03 +0200, Florian Dazinger wrote: > > Hi, > > I think I've found a regression, which causes an early boot crash, I > > appended the kernel output via jpg file, since I do not have a serial > > console or sth. > > > > after bisection, it boils down to this commit: > > > > 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit > > commit 9dcd61303af862c279df86aa97fde7ce371be774 > > Author: Alex Williamson <alex.williamson@redhat.com> > > Date: Wed May 30 14:19:07 2012 -0600 > > > > amd_iommu: Support IOMMU groups > > > > Add IOMMU group support to AMD-Vi device init and uninit code. > > Existing notifiers make sure this gets called for each device. > > > > Signed-off-by: Alex Williamson <alex.williamson@redhat.com> > > Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> > > > > :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 > > 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers > > [switching back to mailing list thread] > > I asked Florian for dmesg w/ amd_iommu_dump, here's the relevant lines: > > [ 1.485645] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 > [ 1.485683] AMD-Vi: mmio-addr: 00000000feb20000 > [ 1.485901] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 > [ 1.485935] AMD-Vi: DEV_RANGE_END devid: 00:00.2 > [ 1.485969] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 > [ 1.486002] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 > [ 1.486036] AMD-Vi: DEV_RANGE_END devid: 01:00.1 > [ 1.486070] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 > [ 1.486103] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 > [ 1.486137] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 > [ 1.486170] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 > [ 1.486204] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 > [ 1.486238] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 > [ 1.486271] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 > [ 1.486305] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 > [ 1.486338] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 > [ 1.486372] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 > [ 1.486406] AMD-Vi: DEV_SELECT devid: 00:0b.0 flags: 00 > [ 1.486439] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > [ 1.486548] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 > [ 1.486581] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 > [ 1.486620] AMD-Vi: DEV_RANGE_END devid: 00:12.2 > [ 1.486654] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 > [ 1.486688] AMD-Vi: DEV_RANGE_END devid: 00:13.2 > [ 1.486721] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 > [ 1.486755] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 > [ 1.486788] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 > [ 1.486822] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 > [ 1.486859] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 > [ 1.486897] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 > [ 1.486931] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 > [ 1.486965] AMD-Vi: DEV_RANGE_END devid: 00:16.2 > [ 1.487055] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 > > > > lspci: > > 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) > > 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) > > 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) > > 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) > > 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) > > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) > > 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) > > 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) > > 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) > > 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) > > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) > > 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) > > 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller > > 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration > > 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map > > 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller > > 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control > > 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control > > 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] > > 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] > > 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) > > 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection > > 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 > > [Oxygen HD Audio] > > We can see this is clearly wrong: > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > So the BIOS is telling us to alias everything in the range of 08:00.0 to > 08:1f.7 to device id 08:01.0, which doesn't exist :( Can you send lspci > -vvv? I suspect we'll find that 07:00.0 sources bus 08 and that alias > should really be to 07:00.0 instead of 08:01.0. Please also provide > dmidecode for this system, we may need to create a quirk for this box. Sorry, messed up the alias, it's aliasing 08:01:0 - 08:1f.7 to 08:00.0, which still doesn't exist. Otherwise it's still broken as described. Joerg, do we have any quirk hooks to fix things like this? Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection 2012-09-25 18:32 ` Alex Williamson 2012-09-25 18:42 ` Alex Williamson @ 2012-09-25 18:54 ` Florian Dazinger 2012-09-25 19:43 ` Alex Williamson 1 sibling, 1 reply; 37+ messages in thread From: Florian Dazinger @ 2012-09-25 18:54 UTC (permalink / raw) To: Alex Williamson; +Cc: linux-kernel, Roedel, Joerg Am Tue, 25 Sep 2012 12:32:50 -0600 schrieb Alex Williamson <alex.williamson@redhat.com>: > On Mon, 2012-09-24 at 21:03 +0200, Florian Dazinger wrote: > > Hi, > > I think I've found a regression, which causes an early boot crash, I > > appended the kernel output via jpg file, since I do not have a serial > > console or sth. > > > > after bisection, it boils down to this commit: > > > > 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit > > commit 9dcd61303af862c279df86aa97fde7ce371be774 > > Author: Alex Williamson <alex.williamson@redhat.com> > > Date: Wed May 30 14:19:07 2012 -0600 > > > > amd_iommu: Support IOMMU groups > > > > Add IOMMU group support to AMD-Vi device init and uninit code. > > Existing notifiers make sure this gets called for each device. > > > > Signed-off-by: Alex Williamson <alex.williamson@redhat.com> > > Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> > > > > :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 > > 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers > > [switching back to mailing list thread] > > I asked Florian for dmesg w/ amd_iommu_dump, here's the relevant lines: > > [ 1.485645] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 > [ 1.485683] AMD-Vi: mmio-addr: 00000000feb20000 > [ 1.485901] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 > [ 1.485935] AMD-Vi: DEV_RANGE_END devid: 00:00.2 > [ 1.485969] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 > [ 1.486002] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 > [ 1.486036] AMD-Vi: DEV_RANGE_END devid: 01:00.1 > [ 1.486070] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 > [ 1.486103] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 > [ 1.486137] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 > [ 1.486170] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 > [ 1.486204] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 > [ 1.486238] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 > [ 1.486271] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 > [ 1.486305] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 > [ 1.486338] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 > [ 1.486372] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 > [ 1.486406] AMD-Vi: DEV_SELECT devid: 00:0b.0 flags: 00 > [ 1.486439] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > [ 1.486548] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 > [ 1.486581] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 > [ 1.486620] AMD-Vi: DEV_RANGE_END devid: 00:12.2 > [ 1.486654] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 > [ 1.486688] AMD-Vi: DEV_RANGE_END devid: 00:13.2 > [ 1.486721] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 > [ 1.486755] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 > [ 1.486788] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 > [ 1.486822] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 > [ 1.486859] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 > [ 1.486897] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 > [ 1.486931] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 > [ 1.486965] AMD-Vi: DEV_RANGE_END devid: 00:16.2 > [ 1.487055] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 > > > > lspci: > > 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) > > 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) > > 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) > > 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) > > 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) > > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) > > 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) > > 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) > > 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) > > 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) > > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) > > 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) > > 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller > > 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration > > 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map > > 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller > > 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control > > 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control > > 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] > > 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] > > 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) > > 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection > > 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 > > [Oxygen HD Audio] > > We can see this is clearly wrong: > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > So the BIOS is telling us to alias everything in the range of 08:00.0 to > 08:1f.7 to device id 08:01.0, which doesn't exist :( Can you send lspci > -vvv? I suspect we'll find that 07:00.0 sources bus 08 and that alias > should really be to 07:00.0 instead of 08:01.0. Please also provide > dmidecode for this system, we may need to create a quirk for this box. > Thanks, > > Alex > lspci -vvv: 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) Subsystem: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Capabilities: [f0] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [c4] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=20 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency 0: [b] Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [40] HyperTransport: Retry Mode Capabilities: [54] HyperTransport: UnitID Clumping Capabilities: [9c] HyperTransport: #1a Capabilities: [70] MSI: Enable- Count=1/4 Maskable- 64bit- Address: 00000000 Data: 0000 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) Subsystem: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 72 Capabilities: [40] Secure device <?> Capabilities: [54] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 41a9 Capabilities: [64] HyperTransport: MSI Mapping Enable+ Fixed+ 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fea00000-feafffff Prefetchable memory behind bridge: 00000000d0000000-00000000dfffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #2, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: fe900000-fe9fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #4, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000c000-0000cfff Memory behind bridge: fe800000-fe8fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #5, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fe700000-fe7fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #6, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fe600000-fe6fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #7, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fe500000-fe5fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #4, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #9, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=07, subordinate=08, sec-latency=0 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #11, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) (prog-if 01 [AHCI 1.0]) Subsystem: ASUSTeK Computer Inc. Device 84dd Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin A routed to IRQ 19 Region 0: I/O ports at f040 [size=8] Region 1: I/O ports at f030 [size=4] Region 2: I/O ports at f020 [size=8] Region 3: I/O ports at f010 [size=4] Region 4: I/O ports at f000 [size=16] Region 5: Memory at feb07000 (32-bit, non-prefetchable) [size=1K] Capabilities: [70] SATA HBA v1.0 InCfgSpace Capabilities: [a4] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ahci 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller (prog-if 10 [OHCI]) Subsystem: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at feb06000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at feb05000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller (prog-if 10 [OHCI]) Subsystem: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 20 Region 0: Memory at feb04000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 21 Region 0: Memory at feb03000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) Subsystem: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) Subsystem: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop+ ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=09, subordinate=09, sec-latency=64 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller (prog-if 10 [OHCI]) Subsystem: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin C routed to IRQ 18 Region 0: Memory at feb02000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller (prog-if 10 [OHCI]) Subsystem: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 22 Region 0: Memory at feb01000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 23 Region 0: Memory at feb00000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 3.00 Link Frequency: [b] Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k10temp 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] (prog-if 00 [VGA controller]) Subsystem: Hightech Information System Ltd. Device 2268 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 73 Region 0: Memory at d0000000 (64-bit, prefetchable) [size=256M] Region 2: Memory at fea20000 (64-bit, non-prefetchable) [size=64K] Region 4: I/O ports at e000 [size=256] Expansion ROM at fea00000 [disabled] [size=128K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 41b9 Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Kernel driver in use: radeon 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] Subsystem: Hightech Information System Ltd. Device aa38 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 7 Region 0: Memory at fea30000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) (prog-if 01 [AHCI 1.0]) Subsystem: ASUSTeK Computer Inc. Device 84b7 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 74 Region 0: I/O ports at d050 [size=8] Region 1: I/O ports at d040 [size=4] Region 2: I/O ports at d030 [size=8] Region 3: I/O ports at d020 [size=4] Region 4: I/O ports at d000 [size=32] Region 5: Memory at fe900000 (32-bit, non-prefetchable) [size=512] Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 41d1 Capabilities: [78] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <1us, L1 <8us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <2us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range ABC, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Kernel driver in use: ahci 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection Subsystem: ASUSTeK Computer Inc. Device 8457 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 75 Region 0: Memory at fe800000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at c000 [size=32] Region 3: Memory at fe820000 (32-bit, non-prefetchable) [size=16K] Capabilities: [c8] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 41b2 Capabilities: [e0] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <128ns, L1 <64us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [a0] MSI-X: Enable- Count=1 Masked- Vector table: BAR=3 offset=00000000 PBA: BAR=3 offset=00002000 Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [140 v1] Device Serial Number f4-6d-04-ff-ff-5b-fb-2c Kernel driver in use: e1000e 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller (prog-if 30 [XHCI]) Subsystem: ASUSTeK Computer Inc. Device 8488 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 51 Region 0: Memory at fe700000 (64-bit, non-prefetchable) [size=32K] Capabilities: [50] MSI: Enable- Count=1/8 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [68] MSI-X: Enable+ Count=8 Masked- Vector table: BAR=0 offset=00002000 PBA: BAR=0 offset=00002080 Capabilities: [78] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <2us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Kernel driver in use: xhci_hcd 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller (prog-if 30 [XHCI]) Subsystem: ASUSTeK Computer Inc. Device 8488 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 50 Region 0: Memory at fe600000 (64-bit, non-prefetchable) [size=32K] Capabilities: [50] MSI: Enable- Count=1/8 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [68] MSI-X: Enable+ Count=8 Masked- Vector table: BAR=0 offset=00002000 PBA: BAR=0 offset=00002080 Capabilities: [78] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <2us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Kernel driver in use: xhci_hcd 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller (prog-if 30 [XHCI]) Subsystem: ASUSTeK Computer Inc. Device 8488 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 48 Region 0: Memory at fe500000 (64-bit, non-prefetchable) [size=32K] Capabilities: [50] MSI: Enable- Count=1/8 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [68] MSI-X: Enable+ Count=8 Masked- Vector table: BAR=0 offset=00002000 PBA: BAR=0 offset=00002080 Capabilities: [78] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <2us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 Status: NegoPending- InProgress- Kernel driver in use: xhci_hcd 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Power Budgeting <?> 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (500ns min, 6000ns max) Interrupt: pin A routed to IRQ 32 Region 0: I/O ports at b000 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: snd_virtuoso dmidecode: # dmidecode 2.10 SMBIOS 2.7 present. 55 structures occupying 2526 bytes. Table at 0x000EED90. Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: American Megatrends Inc. Version: 1402 Release Date: 04/19/2012 Address: 0xF0000 Runtime Size: 64 kB ROM Size: 4096 kB Characteristics: PCI is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 kB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) ACPI is supported USB legacy is supported BIOS boot specification is supported Targeted content distribution is supported BIOS Revision: 4.6 Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: To be filled by O.E.M. Product Name: To be filled by O.E.M. Version: To be filled by O.E.M. Serial Number: To be filled by O.E.M. UUID: 4561AC20-9461-11E0-B610-F46D045BFB2C Wake-up Type: Power Switch SKU Number: To be filled by O.E.M. Family: To be filled by O.E.M. Handle 0x0002, DMI type 2, 15 bytes Base Board Information Manufacturer: ASUSTeK COMPUTER INC. Product Name: Crosshair V Formula Version: Rev 1.xx Serial Number: 110260760002248 Asset Tag: To be filled by O.E.M. Features: Board is a hosting board Board is replaceable Location In Chassis: To be filled by O.E.M. Chassis Handle: 0x0003 Type: Motherboard Contained Object Handles: 0 Handle 0x0003, DMI type 3, 22 bytes Chassis Information Manufacturer: To Be Filled By O.E.M. Type: Desktop Lock: Not Present Version: To Be Filled By O.E.M. Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00000000 Height: Unspecified Number Of Power Cords: 1 Contained Elements: 0 Handle 0x0004, DMI type 4, 42 bytes Processor Information Socket Designation: AM3r2 Type: Central Processor Family: <OUT OF SPEC> Manufacturer: AMD ID: 43 0F 10 00 FF FB 8B 17 Version: AMD Phenom(tm) II X4 955 Processor Voltage: 1.4 V External Clock: 200 MHz Max Speed: 3200 MHz Current Speed: 3200 MHz Status: Populated, Enabled Upgrade: <OUT OF SPEC> L1 Cache Handle: 0x0005 L2 Cache Handle: 0x0006 L3 Cache Handle: 0x0007 Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Part Number: To Be Filled By O.E.M. Core Count: 4 Core Enabled: 4 Thread Count: 4 Characteristics: 64-bit capable Handle 0x0005, DMI type 7, 19 bytes Cache Information Socket Designation: L1-Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 512 kB Maximum Size: 512 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 1 ns Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 2-way Set-associative Handle 0x0006, DMI type 7, 19 bytes Cache Information Socket Designation: L2-Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 2048 kB Maximum Size: 2048 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 1 ns Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 16-way Set-associative Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: L3-Cache Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Write Back Location: Internal Installed Size: 6144 kB Maximum Size: 6144 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 1 ns Error Correction Type: Multi-bit ECC System Type: Unified Associativity: <OUT OF SPEC> Handle 0x0008, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1A1 Internal Connector Type: None External Reference Designator: PS2Mouse External Connector Type: PS/2 Port Type: Mouse Port Handle 0x0009, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1A1 Internal Connector Type: None External Reference Designator: Keyboard External Connector Type: PS/2 Port Type: Keyboard Port Handle 0x000A, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A1 Internal Connector Type: None External Reference Designator: TV Out External Connector Type: Mini Centronics Type-14 Port Type: Other Handle 0x000B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A2A Internal Connector Type: None External Reference Designator: COM A External Connector Type: DB-9 male Port Type: Serial Port 16550A Compatible Handle 0x000C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A2B Internal Connector Type: None External Reference Designator: Video External Connector Type: DB-15 female Port Type: Video Port Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J3A1 Internal Connector Type: None External Reference Designator: USB1 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J3A1 Internal Connector Type: None External Reference Designator: USB2 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J3A1 Internal Connector Type: None External Reference Designator: USB3 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9A1 - TPM HDR Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0011, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9C1 - PCIE DOCKING CONN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0012, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2B3 - CPU FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0013, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6C2 - EXT HDMI Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0014, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J3C1 - GMCH FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0015, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1D1 - ITP Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0016, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9E2 - MDC INTPSR Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0017, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9E4 - MDC INTPSR Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0018, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9E3 - LPC HOT DOCKING Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0019, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9E1 - SCAN MATRIX Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001A, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9G1 - LPC SIDE BAND Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J8F1 - UNIFIED Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6F1 - LVDS Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2F1 - LAI FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2G1 - GFX VID Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1G6 - AC JACK Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0020, DMI type 9, 17 bytes System Slot Information Designation: J6B2 Type: x16 PCI Express Current Usage: In Use Length: Long ID: 0 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Bus Address: 0000:00:01.0 Handle 0x0021, DMI type 9, 17 bytes System Slot Information Designation: J6B1 Type: x1 PCI Express Current Usage: In Use Length: Short ID: 1 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Bus Address: 0000:00:1c.3 Handle 0x0022, DMI type 9, 17 bytes System Slot Information Designation: J6D1 Type: x1 PCI Express Current Usage: In Use Length: Short ID: 2 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Bus Address: 0000:00:1c.4 Handle 0x0023, DMI type 10, 6 bytes On Board Device Information Type: Video Status: Enabled Description: To Be Filled By O.E.M. Handle 0x0024, DMI type 11, 5 bytes OEM Strings String 1: To Be Filled By O.E.M. String 2: To Be Filled By O.E.M. String 3: To Be Filled By O.E.M. String 4: To Be Filled By O.E.M. Handle 0x0025, DMI type 12, 5 bytes System Configuration Options Option 1: To Be Filled By O.E.M. Handle 0x0026, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: Multi-bit ECC Maximum Capacity: 32 GB Error Information Handle: Not Provided Number Of Devices: 4 Handle 0x0027, DMI type 19, 31 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x004300003FF Range Size: 17563649 kB Physical Array Handle: 0x0026 Partition Width: 0 Handle 0x0028, DMI type 17, 34 bytes Memory Device Array Handle: 0x0026 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM0 Bank Locator: BANK0 Type: <OUT OF SPEC> Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Manufacturer0 Serial Number: SerNum0 Asset Tag: AssetTagNum0 Part Number: Array1_PartNumber0 Rank: Unknown Handle 0x0029, DMI type 20, 35 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x001FFFFFFFF Range Size: 8 GB Physical Device Handle: 0x0028 Memory Array Mapped Address Handle: 0x0027 Partition Row Position: <OUT OF SPEC> Interleave Position: Unknown Interleaved Data Depth: Unknown Handle 0x002A, DMI type 17, 34 bytes Memory Device Array Handle: 0x0026 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM1 Bank Locator: BANK1 Type: <OUT OF SPEC> Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Manufacturer1 Serial Number: SerNum1 Asset Tag: AssetTagNum1 Part Number: Array1_PartNumber1 Rank: Unknown Handle 0x002B, DMI type 20, 35 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x001FFFFFFFF Range Size: 8 GB Physical Device Handle: 0x002A Memory Array Mapped Address Handle: 0x0027 Partition Row Position: <OUT OF SPEC> Interleave Position: Unknown Interleaved Data Depth: Unknown Handle 0x002C, DMI type 17, 34 bytes Memory Device Array Handle: 0x0026 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM2 Bank Locator: BANK2 Type: <OUT OF SPEC> Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Manufacturer2 Serial Number: SerNum2 Asset Tag: AssetTagNum2 Part Number: Array1_PartNumber2 Rank: Unknown Handle 0x002D, DMI type 20, 35 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x001FFFFFFFF Range Size: 8 GB Physical Device Handle: 0x002C Memory Array Mapped Address Handle: 0x0027 Partition Row Position: <OUT OF SPEC> Interleave Position: Unknown Interleaved Data Depth: Unknown Handle 0x002E, DMI type 17, 34 bytes Memory Device Array Handle: 0x0026 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM3 Bank Locator: BANK3 Type: <OUT OF SPEC> Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Manufacturer3 Serial Number: SerNum3 Asset Tag: AssetTagNum3 Part Number: Array1_PartNumber3 Rank: Unknown Handle 0x002F, DMI type 20, 35 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x001FFFFFFFF Range Size: 8 GB Physical Device Handle: 0x002E Memory Array Mapped Address Handle: 0x0027 Partition Row Position: <OUT OF SPEC> Interleave Position: Unknown Interleaved Data Depth: Unknown Handle 0x0030, DMI type 32, 20 bytes System Boot Information Status: No errors detected Handle 0x0031, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard IGD Type: Video Status: Enabled Type Instance: 1 Bus Address: 0000:00:02.0 Handle 0x0032, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard LAN Type: Ethernet Status: Enabled Type Instance: 1 Bus Address: 0000:00:19.0 Handle 0x0033, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard 1394 Type: Other Status: Enabled Type Instance: 1 Bus Address: 0000:03:1c.2 Handle 0x0034, DMI type 139, 54 bytes OEM-specific Type Header and Data: 8B 36 34 00 FE DC BA 98 76 54 32 10 04 04 32 55 F8 00 A2 02 A1 00 40 63 06 11 44 30 03 DF 40 B2 00 20 00 73 3C 10 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 Strings: V1394GUID Handle 0x0035, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 8 en|US|iso8859-1 fr|FR|iso8859-1 es|ES|iso8859-1 de|DE|iso8859-1 ru|RU|iso8859-5 zh|TW|unicode zh|CN|unicode ja|JP|unicode Currently Installed Language: en|US|iso8859-1 Handle 0x0037, DMI type 127, 4 bytes End Of Table ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-25 19:43 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-25 19:43 UTC (permalink / raw) To: Florian Dazinger; +Cc: linux-kernel, Roedel, Joerg, iommu On Tue, 2012-09-25 at 20:54 +0200, Florian Dazinger wrote: > Am Tue, 25 Sep 2012 12:32:50 -0600 > schrieb Alex Williamson <alex.williamson@redhat.com>: > > > On Mon, 2012-09-24 at 21:03 +0200, Florian Dazinger wrote: > > > Hi, > > > I think I've found a regression, which causes an early boot crash, I > > > appended the kernel output via jpg file, since I do not have a serial > > > console or sth. > > > > > > after bisection, it boils down to this commit: > > > > > > 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit > > > commit 9dcd61303af862c279df86aa97fde7ce371be774 > > > Author: Alex Williamson <alex.williamson@redhat.com> > > > Date: Wed May 30 14:19:07 2012 -0600 > > > > > > amd_iommu: Support IOMMU groups > > > > > > Add IOMMU group support to AMD-Vi device init and uninit code. > > > Existing notifiers make sure this gets called for each device. > > > > > > Signed-off-by: Alex Williamson <alex.williamson@redhat.com> > > > Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> > > > > > > :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 > > > 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers > > > > [switching back to mailing list thread] > > > > I asked Florian for dmesg w/ amd_iommu_dump, here's the relevant lines: > > > > [ 1.485645] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 > > [ 1.485683] AMD-Vi: mmio-addr: 00000000feb20000 > > [ 1.485901] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 > > [ 1.485935] AMD-Vi: DEV_RANGE_END devid: 00:00.2 > > [ 1.485969] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 > > [ 1.486002] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 > > [ 1.486036] AMD-Vi: DEV_RANGE_END devid: 01:00.1 > > [ 1.486070] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 > > [ 1.486103] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 > > [ 1.486137] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 > > [ 1.486170] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 > > [ 1.486204] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 > > [ 1.486238] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 > > [ 1.486271] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 > > [ 1.486305] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 > > [ 1.486338] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 > > [ 1.486372] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 > > [ 1.486406] AMD-Vi: DEV_SELECT devid: 00:0b.0 flags: 00 > > [ 1.486439] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > [ 1.486548] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 > > [ 1.486581] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 > > [ 1.486620] AMD-Vi: DEV_RANGE_END devid: 00:12.2 > > [ 1.486654] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 > > [ 1.486688] AMD-Vi: DEV_RANGE_END devid: 00:13.2 > > [ 1.486721] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 > > [ 1.486755] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 > > [ 1.486788] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 > > [ 1.486822] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 > > [ 1.486859] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 > > [ 1.486897] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 > > [ 1.486931] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 > > [ 1.486965] AMD-Vi: DEV_RANGE_END devid: 00:16.2 > > [ 1.487055] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 > > > > > > > lspci: > > > 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) > > > 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) > > > 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) > > > 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) > > > 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) > > > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) > > > 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) > > > 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) > > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) > > > 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) > > > 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) > > > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) > > > 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) > > > 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller > > > 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration > > > 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map > > > 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller > > > 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control > > > 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control > > > 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] > > > 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] > > > 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) > > > 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection > > > 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) > > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 > > > [Oxygen HD Audio] > > > > We can see this is clearly wrong: > > > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > > > So the BIOS is telling us to alias everything in the range of 08:01.0 to > > 08:1f.7 to device id 08:00.0, which doesn't exist :( Can you send lspci > > -vvv? I suspect we'll find that 07:00.0 sources bus 08 and that alias > > should really be to 07:00.0 instead of 08:00.0. Please also provide > > dmidecode for this system, we may need to create a quirk for this box. > > Thanks, [corrected alias and range in text above, adding iommu list] > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) (prog-if 00 [Normal decode]) > Bus: primary=00, secondary=07, subordinate=08, sec-latency=0 > Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) > Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 > Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] > Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > Latency: 32 (500ns min, 6000ns max) > Interrupt: pin A routed to IRQ 32 > Region 0: I/O ports at b000 [size=256] > Capabilities: [c0] Power Management version 2 > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Kernel driver in use: snd_virtuoso > Yep, my guess appears correct, the alias should be to device 07:00.0. It looks like this is a x1 PCIe card, so I think that PLX bridge is on the card. The system probably boots fine if you remove the audio card (or of course with amd_iommu=off). It looks like there is one rev newer BIOS for this motherboard; we should probably exhaust the possibility that this bug has already been fixed in BIOS 1503 before we implement a quirk. Can you test this? Joerg, any thoughts on a quirk for this? Unfortunately we can't just skip IOMMU groups when an alias is broken because it puts the other IOMMU groups at risk that might not actually be isolated from this device. It looks like we parse the alias info before PCI is probed, so maybe we'd need to call the quirk from iommu_init_device itself. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-25 19:43 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-25 19:43 UTC (permalink / raw) To: Florian Dazinger; +Cc: iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Tue, 2012-09-25 at 20:54 +0200, Florian Dazinger wrote: > Am Tue, 25 Sep 2012 12:32:50 -0600 > schrieb Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>: > > > On Mon, 2012-09-24 at 21:03 +0200, Florian Dazinger wrote: > > > Hi, > > > I think I've found a regression, which causes an early boot crash, I > > > appended the kernel output via jpg file, since I do not have a serial > > > console or sth. > > > > > > after bisection, it boils down to this commit: > > > > > > 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit > > > commit 9dcd61303af862c279df86aa97fde7ce371be774 > > > Author: Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> > > > Date: Wed May 30 14:19:07 2012 -0600 > > > > > > amd_iommu: Support IOMMU groups > > > > > > Add IOMMU group support to AMD-Vi device init and uninit code. > > > Existing notifiers make sure this gets called for each device. > > > > > > Signed-off-by: Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> > > > Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org> > > > > > > :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 > > > 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers > > > > [switching back to mailing list thread] > > > > I asked Florian for dmesg w/ amd_iommu_dump, here's the relevant lines: > > > > [ 1.485645] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 > > [ 1.485683] AMD-Vi: mmio-addr: 00000000feb20000 > > [ 1.485901] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 > > [ 1.485935] AMD-Vi: DEV_RANGE_END devid: 00:00.2 > > [ 1.485969] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 > > [ 1.486002] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 > > [ 1.486036] AMD-Vi: DEV_RANGE_END devid: 01:00.1 > > [ 1.486070] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 > > [ 1.486103] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 > > [ 1.486137] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 > > [ 1.486170] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 > > [ 1.486204] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 > > [ 1.486238] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 > > [ 1.486271] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 > > [ 1.486305] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 > > [ 1.486338] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 > > [ 1.486372] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 > > [ 1.486406] AMD-Vi: DEV_SELECT devid: 00:0b.0 flags: 00 > > [ 1.486439] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > [ 1.486548] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 > > [ 1.486581] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 > > [ 1.486620] AMD-Vi: DEV_RANGE_END devid: 00:12.2 > > [ 1.486654] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 > > [ 1.486688] AMD-Vi: DEV_RANGE_END devid: 00:13.2 > > [ 1.486721] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 > > [ 1.486755] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 > > [ 1.486788] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 > > [ 1.486822] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 > > [ 1.486859] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 > > [ 1.486897] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 > > [ 1.486931] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 > > [ 1.486965] AMD-Vi: DEV_RANGE_END devid: 00:16.2 > > [ 1.487055] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 > > > > > > > lspci: > > > 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) > > > 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) > > > 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) > > > 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) > > > 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) > > > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) > > > 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) > > > 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) > > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) > > > 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) > > > 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) > > > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) > > > 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) > > > 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller > > > 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration > > > 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map > > > 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller > > > 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control > > > 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control > > > 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] > > > 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] > > > 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) > > > 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection > > > 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) > > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 > > > [Oxygen HD Audio] > > > > We can see this is clearly wrong: > > > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > > > So the BIOS is telling us to alias everything in the range of 08:01.0 to > > 08:1f.7 to device id 08:00.0, which doesn't exist :( Can you send lspci > > -vvv? I suspect we'll find that 07:00.0 sources bus 08 and that alias > > should really be to 07:00.0 instead of 08:00.0. Please also provide > > dmidecode for this system, we may need to create a quirk for this box. > > Thanks, [corrected alias and range in text above, adding iommu list] > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) (prog-if 00 [Normal decode]) > Bus: primary=00, secondary=07, subordinate=08, sec-latency=0 > Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) > Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 > Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] > Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > Latency: 32 (500ns min, 6000ns max) > Interrupt: pin A routed to IRQ 32 > Region 0: I/O ports at b000 [size=256] > Capabilities: [c0] Power Management version 2 > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Kernel driver in use: snd_virtuoso > Yep, my guess appears correct, the alias should be to device 07:00.0. It looks like this is a x1 PCIe card, so I think that PLX bridge is on the card. The system probably boots fine if you remove the audio card (or of course with amd_iommu=off). It looks like there is one rev newer BIOS for this motherboard; we should probably exhaust the possibility that this bug has already been fixed in BIOS 1503 before we implement a quirk. Can you test this? Joerg, any thoughts on a quirk for this? Unfortunately we can't just skip IOMMU groups when an alias is broken because it puts the other IOMMU groups at risk that might not actually be isolated from this device. It looks like we parse the alias info before PCI is probed, so maybe we'd need to call the quirk from iommu_init_device itself. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection 2012-09-25 19:43 ` Alex Williamson (?) @ 2012-09-25 23:01 ` Florian Dazinger 2012-09-26 3:12 ` Alex Williamson 2012-09-26 14:43 ` Roedel, Joerg -1 siblings, 2 replies; 37+ messages in thread From: Florian Dazinger @ 2012-09-25 23:01 UTC (permalink / raw) To: Alex Williamson; +Cc: linux-kernel, Roedel, Joerg, iommu Am Tue, 25 Sep 2012 13:43:46 -0600 schrieb Alex Williamson <alex.williamson@redhat.com>: > On Tue, 2012-09-25 at 20:54 +0200, Florian Dazinger wrote: > > Am Tue, 25 Sep 2012 12:32:50 -0600 > > schrieb Alex Williamson <alex.williamson@redhat.com>: > > > > > On Mon, 2012-09-24 at 21:03 +0200, Florian Dazinger wrote: > > > > Hi, > > > > I think I've found a regression, which causes an early boot crash, I > > > > appended the kernel output via jpg file, since I do not have a serial > > > > console or sth. > > > > > > > > after bisection, it boils down to this commit: > > > > > > > > 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit > > > > commit 9dcd61303af862c279df86aa97fde7ce371be774 > > > > Author: Alex Williamson <alex.williamson@redhat.com> > > > > Date: Wed May 30 14:19:07 2012 -0600 > > > > > > > > amd_iommu: Support IOMMU groups > > > > > > > > Add IOMMU group support to AMD-Vi device init and uninit code. > > > > Existing notifiers make sure this gets called for each device. > > > > > > > > Signed-off-by: Alex Williamson <alex.williamson@redhat.com> > > > > Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> > > > > > > > > :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 > > > > 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers > > > > > > [switching back to mailing list thread] > > > > > > I asked Florian for dmesg w/ amd_iommu_dump, here's the relevant lines: > > > > > > [ 1.485645] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 > > > [ 1.485683] AMD-Vi: mmio-addr: 00000000feb20000 > > > [ 1.485901] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 > > > [ 1.485935] AMD-Vi: DEV_RANGE_END devid: 00:00.2 > > > [ 1.485969] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 > > > [ 1.486002] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 > > > [ 1.486036] AMD-Vi: DEV_RANGE_END devid: 01:00.1 > > > [ 1.486070] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 > > > [ 1.486103] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 > > > [ 1.486137] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 > > > [ 1.486170] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 > > > [ 1.486204] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 > > > [ 1.486238] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 > > > [ 1.486271] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 > > > [ 1.486305] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 > > > [ 1.486338] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 > > > [ 1.486372] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 > > > [ 1.486406] AMD-Vi: DEV_SELECT devid: 00:0b.0 flags: 00 > > > [ 1.486439] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 > > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > > [ 1.486548] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 > > > [ 1.486581] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 > > > [ 1.486620] AMD-Vi: DEV_RANGE_END devid: 00:12.2 > > > [ 1.486654] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 > > > [ 1.486688] AMD-Vi: DEV_RANGE_END devid: 00:13.2 > > > [ 1.486721] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 > > > [ 1.486755] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 > > > [ 1.486788] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 > > > [ 1.486822] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 > > > [ 1.486859] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 > > > [ 1.486897] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 > > > [ 1.486931] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 > > > [ 1.486965] AMD-Vi: DEV_RANGE_END devid: 00:16.2 > > > [ 1.487055] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 > > > > > > > > > > lspci: > > > > 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) > > > > 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) > > > > 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) > > > > 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) > > > > 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) > > > > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) > > > > 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) > > > > 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) > > > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) > > > > 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) > > > > 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > > 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > > 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > > 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > > 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) > > > > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) > > > > 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) > > > > 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller > > > > 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > > 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > > 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration > > > > 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map > > > > 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller > > > > 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control > > > > 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control > > > > 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] > > > > 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] > > > > 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) > > > > 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection > > > > 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > > 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > > 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) > > > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 > > > > [Oxygen HD Audio] > > > > > > We can see this is clearly wrong: > > > > > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > > > > > So the BIOS is telling us to alias everything in the range of 08:01.0 to > > > 08:1f.7 to device id 08:00.0, which doesn't exist :( Can you send lspci > > > -vvv? I suspect we'll find that 07:00.0 sources bus 08 and that alias > > > should really be to 07:00.0 instead of 08:00.0. Please also provide > > > dmidecode for this system, we may need to create a quirk for this box. > > > Thanks, > > [corrected alias and range in text above, adding iommu list] > > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) (prog-if 00 [Normal decode]) > > Bus: primary=00, secondary=07, subordinate=08, sec-latency=0 > > Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 > > > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) > > Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 > > Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 > > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] > > Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) > > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- > > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > > Latency: 32 (500ns min, 6000ns max) > > Interrupt: pin A routed to IRQ 32 > > Region 0: I/O ports at b000 [size=256] > > Capabilities: [c0] Power Management version 2 > > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > > Kernel driver in use: snd_virtuoso > > > > Yep, my guess appears correct, the alias should be to device 07:00.0. > It looks like this is a x1 PCIe card, so I think that PLX bridge is on > the card. The system probably boots fine if you remove the audio card > (or of course with amd_iommu=off). It looks like there is one rev newer > BIOS for this motherboard; we should probably exhaust the possibility > that this bug has already been fixed in BIOS 1503 before we implement a > quirk. Can you test this? > > Joerg, any thoughts on a quirk for this? Unfortunately we can't just > skip IOMMU groups when an alias is broken because it puts the other > IOMMU groups at risk that might not actually be isolated from this > device. It looks like we parse the alias info before PCI is probed, so > maybe we'd need to call the quirk from iommu_init_device itself. > Thanks, > > Alex > > Alex, you're right, either "amd_iommu=off" or removing the audio card makes the failure disappear. I will test the new BIOS rev. tomorrow. thanks, Florian ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 3:12 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 3:12 UTC (permalink / raw) To: Florian Dazinger; +Cc: linux-kernel, Roedel, Joerg, iommu On Wed, 2012-09-26 at 01:01 +0200, Florian Dazinger wrote: > Am Tue, 25 Sep 2012 13:43:46 -0600 > schrieb Alex Williamson <alex.williamson@redhat.com>: > > > On Tue, 2012-09-25 at 20:54 +0200, Florian Dazinger wrote: > > > Am Tue, 25 Sep 2012 12:32:50 -0600 > > > schrieb Alex Williamson <alex.williamson@redhat.com>: > > > > > > > On Mon, 2012-09-24 at 21:03 +0200, Florian Dazinger wrote: > > > > > Hi, > > > > > I think I've found a regression, which causes an early boot crash, I > > > > > appended the kernel output via jpg file, since I do not have a serial > > > > > console or sth. > > > > > > > > > > after bisection, it boils down to this commit: > > > > > > > > > > 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit > > > > > commit 9dcd61303af862c279df86aa97fde7ce371be774 > > > > > Author: Alex Williamson <alex.williamson@redhat.com> > > > > > Date: Wed May 30 14:19:07 2012 -0600 > > > > > > > > > > amd_iommu: Support IOMMU groups > > > > > > > > > > Add IOMMU group support to AMD-Vi device init and uninit code. > > > > > Existing notifiers make sure this gets called for each device. > > > > > > > > > > Signed-off-by: Alex Williamson <alex.williamson@redhat.com> > > > > > Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> > > > > > > > > > > :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 > > > > > 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers > > > > > > > > [switching back to mailing list thread] > > > > > > > > I asked Florian for dmesg w/ amd_iommu_dump, here's the relevant lines: > > > > > > > > [ 1.485645] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 > > > > [ 1.485683] AMD-Vi: mmio-addr: 00000000feb20000 > > > > [ 1.485901] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 > > > > [ 1.485935] AMD-Vi: DEV_RANGE_END devid: 00:00.2 > > > > [ 1.485969] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 > > > > [ 1.486002] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 > > > > [ 1.486036] AMD-Vi: DEV_RANGE_END devid: 01:00.1 > > > > [ 1.486070] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 > > > > [ 1.486103] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 > > > > [ 1.486137] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 > > > > [ 1.486170] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 > > > > [ 1.486204] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 > > > > [ 1.486238] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 > > > > [ 1.486271] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 > > > > [ 1.486305] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 > > > > [ 1.486338] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 > > > > [ 1.486372] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 > > > > [ 1.486406] AMD-Vi: DEV_SELECT devid: 00:0b.0 flags: 00 > > > > [ 1.486439] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 > > > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > > > [ 1.486548] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 > > > > [ 1.486581] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 > > > > [ 1.486620] AMD-Vi: DEV_RANGE_END devid: 00:12.2 > > > > [ 1.486654] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 > > > > [ 1.486688] AMD-Vi: DEV_RANGE_END devid: 00:13.2 > > > > [ 1.486721] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 > > > > [ 1.486755] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 > > > > [ 1.486788] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 > > > > [ 1.486822] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 > > > > [ 1.486859] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 > > > > [ 1.486897] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 > > > > [ 1.486931] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 > > > > [ 1.486965] AMD-Vi: DEV_RANGE_END devid: 00:16.2 > > > > [ 1.487055] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 > > > > > > > > > > > > > lspci: > > > > > 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) > > > > > 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) > > > > > 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) > > > > > 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) > > > > > 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) > > > > > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) > > > > > 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) > > > > > 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) > > > > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) > > > > > 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) > > > > > 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > > > 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > > > 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > > > 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > > > 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) > > > > > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) > > > > > 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) > > > > > 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller > > > > > 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > > > 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > > > 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration > > > > > 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map > > > > > 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller > > > > > 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control > > > > > 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control > > > > > 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] > > > > > 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] > > > > > 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) > > > > > 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection > > > > > 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > > > 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > > > 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) > > > > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 > > > > > [Oxygen HD Audio] > > > > > > > > We can see this is clearly wrong: > > > > > > > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > > > > > > > So the BIOS is telling us to alias everything in the range of 08:01.0 to > > > > 08:1f.7 to device id 08:00.0, which doesn't exist :( Can you send lspci > > > > -vvv? I suspect we'll find that 07:00.0 sources bus 08 and that alias > > > > should really be to 07:00.0 instead of 08:00.0. Please also provide > > > > dmidecode for this system, we may need to create a quirk for this box. > > > > Thanks, > > > > [corrected alias and range in text above, adding iommu list] > > > > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) (prog-if 00 [Normal decode]) > > > Bus: primary=00, secondary=07, subordinate=08, sec-latency=0 > > > Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 > > > > > > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) > > > Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 > > > Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 > > > > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] > > > Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) > > > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- > > > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > > > Latency: 32 (500ns min, 6000ns max) > > > Interrupt: pin A routed to IRQ 32 > > > Region 0: I/O ports at b000 [size=256] > > > Capabilities: [c0] Power Management version 2 > > > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > > > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > > > Kernel driver in use: snd_virtuoso > > > > > > > Yep, my guess appears correct, the alias should be to device 07:00.0. > > It looks like this is a x1 PCIe card, so I think that PLX bridge is on > > the card. The system probably boots fine if you remove the audio card > > (or of course with amd_iommu=off). It looks like there is one rev newer > > BIOS for this motherboard; we should probably exhaust the possibility > > that this bug has already been fixed in BIOS 1503 before we implement a > > quirk. Can you test this? > > > > Joerg, any thoughts on a quirk for this? Unfortunately we can't just > > skip IOMMU groups when an alias is broken because it puts the other > > IOMMU groups at risk that might not actually be isolated from this > > device. It looks like we parse the alias info before PCI is probed, so > > maybe we'd need to call the quirk from iommu_init_device itself. > > Thanks, > > > > Alex > > > > > > Alex, > you're right, either "amd_iommu=off" or removing the audio card makes > the failure disappear. I will test the new BIOS rev. tomorrow. You might also try the sound card in different slots, it's possible the BIOS only generates the wrong entry for the x1 slot. If you do try this, please boot with amd_iommu_dump and report configuration and AMD-Vi dmesg output as above. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 3:12 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 3:12 UTC (permalink / raw) To: Florian Dazinger; +Cc: iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, 2012-09-26 at 01:01 +0200, Florian Dazinger wrote: > Am Tue, 25 Sep 2012 13:43:46 -0600 > schrieb Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>: > > > On Tue, 2012-09-25 at 20:54 +0200, Florian Dazinger wrote: > > > Am Tue, 25 Sep 2012 12:32:50 -0600 > > > schrieb Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>: > > > > > > > On Mon, 2012-09-24 at 21:03 +0200, Florian Dazinger wrote: > > > > > Hi, > > > > > I think I've found a regression, which causes an early boot crash, I > > > > > appended the kernel output via jpg file, since I do not have a serial > > > > > console or sth. > > > > > > > > > > after bisection, it boils down to this commit: > > > > > > > > > > 9dcd61303af862c279df86aa97fde7ce371be774 is the first bad commit > > > > > commit 9dcd61303af862c279df86aa97fde7ce371be774 > > > > > Author: Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> > > > > > Date: Wed May 30 14:19:07 2012 -0600 > > > > > > > > > > amd_iommu: Support IOMMU groups > > > > > > > > > > Add IOMMU group support to AMD-Vi device init and uninit code. > > > > > Existing notifiers make sure this gets called for each device. > > > > > > > > > > Signed-off-by: Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> > > > > > Signed-off-by: Joerg Roedel <joerg.roedel-5C7GfCeVMHo@public.gmane.org> > > > > > > > > > > :040000 040000 2f6b1b8e104d6dfec0abaa9646750f9b5a4f4060 > > > > > 837ae95e84f6d3553457c4df595a9caa56843c03 M drivers > > > > > > > > [switching back to mailing list thread] > > > > > > > > I asked Florian for dmesg w/ amd_iommu_dump, here's the relevant lines: > > > > > > > > [ 1.485645] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 > > > > [ 1.485683] AMD-Vi: mmio-addr: 00000000feb20000 > > > > [ 1.485901] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 > > > > [ 1.485935] AMD-Vi: DEV_RANGE_END devid: 00:00.2 > > > > [ 1.485969] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 > > > > [ 1.486002] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 > > > > [ 1.486036] AMD-Vi: DEV_RANGE_END devid: 01:00.1 > > > > [ 1.486070] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 > > > > [ 1.486103] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 > > > > [ 1.486137] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 > > > > [ 1.486170] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 > > > > [ 1.486204] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 > > > > [ 1.486238] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 > > > > [ 1.486271] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 > > > > [ 1.486305] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 > > > > [ 1.486338] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 > > > > [ 1.486372] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 > > > > [ 1.486406] AMD-Vi: DEV_SELECT devid: 00:0b.0 flags: 00 > > > > [ 1.486439] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 > > > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > > > [ 1.486548] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 > > > > [ 1.486581] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 > > > > [ 1.486620] AMD-Vi: DEV_RANGE_END devid: 00:12.2 > > > > [ 1.486654] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 > > > > [ 1.486688] AMD-Vi: DEV_RANGE_END devid: 00:13.2 > > > > [ 1.486721] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 > > > > [ 1.486755] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 > > > > [ 1.486788] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 > > > > [ 1.486822] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 > > > > [ 1.486859] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 > > > > [ 1.486897] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 > > > > [ 1.486931] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 > > > > [ 1.486965] AMD-Vi: DEV_RANGE_END devid: 00:16.2 > > > > [ 1.487055] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 > > > > > > > > > > > > > lspci: > > > > > 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) > > > > > 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) > > > > > 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) > > > > > 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) > > > > > 00:05.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port E) > > > > > 00:06.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port F) > > > > > 00:07.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port G) > > > > > 00:09.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port H) > > > > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) > > > > > 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) > > > > > 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > > > 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > > > 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > > > 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > > > 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) > > > > > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) > > > > > 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) > > > > > 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller > > > > > 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller > > > > > 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller > > > > > 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration > > > > > 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map > > > > > 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller > > > > > 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control > > > > > 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control > > > > > 01:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI RV730XT [Radeon HD 4670] > > > > > 01:00.1 Audio device: Advanced Micro Devices [AMD] nee ATI RV710/730 HDMI Audio [Radeon HD 4000 series] > > > > > 02:00.0 SATA controller: ASMedia Technology Inc. ASM1062 Serial ATA Controller (rev 01) > > > > > 03:00.0 Ethernet controller: Intel Corporation 82583V Gigabit Network Connection > > > > > 04:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > > > 05:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > > > 06:00.0 USB controller: ASMedia Technology Inc. ASM1042 SuperSpeed USB Host Controller > > > > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) > > > > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 > > > > > [Oxygen HD Audio] > > > > > > > > We can see this is clearly wrong: > > > > > > > > [ 1.486473] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 > > > > [ 1.486510] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 > > > > > > > > So the BIOS is telling us to alias everything in the range of 08:01.0 to > > > > 08:1f.7 to device id 08:00.0, which doesn't exist :( Can you send lspci > > > > -vvv? I suspect we'll find that 07:00.0 sources bus 08 and that alias > > > > should really be to 07:00.0 instead of 08:00.0. Please also provide > > > > dmidecode for this system, we may need to create a quirk for this box. > > > > Thanks, > > > > [corrected alias and range in text above, adding iommu list] > > > > > 00:0b.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (NB-SB link) (prog-if 00 [Normal decode]) > > > Bus: primary=00, secondary=07, subordinate=08, sec-latency=0 > > > Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 > > > > > > > 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) > > > Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 > > > Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 > > > > > 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] > > > Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) > > > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- > > > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > > > Latency: 32 (500ns min, 6000ns max) > > > Interrupt: pin A routed to IRQ 32 > > > Region 0: I/O ports at b000 [size=256] > > > Capabilities: [c0] Power Management version 2 > > > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) > > > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > > > Kernel driver in use: snd_virtuoso > > > > > > > Yep, my guess appears correct, the alias should be to device 07:00.0. > > It looks like this is a x1 PCIe card, so I think that PLX bridge is on > > the card. The system probably boots fine if you remove the audio card > > (or of course with amd_iommu=off). It looks like there is one rev newer > > BIOS for this motherboard; we should probably exhaust the possibility > > that this bug has already been fixed in BIOS 1503 before we implement a > > quirk. Can you test this? > > > > Joerg, any thoughts on a quirk for this? Unfortunately we can't just > > skip IOMMU groups when an alias is broken because it puts the other > > IOMMU groups at risk that might not actually be isolated from this > > device. It looks like we parse the alias info before PCI is probed, so > > maybe we'd need to call the quirk from iommu_init_device itself. > > Thanks, > > > > Alex > > > > > > Alex, > you're right, either "amd_iommu=off" or removing the audio card makes > the failure disappear. I will test the new BIOS rev. tomorrow. You might also try the sound card in different slots, it's possible the BIOS only generates the wrong entry for the x1 slot. If you do try this, please boot with amd_iommu_dump and report configuration and AMD-Vi dmesg output as above. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 14:43 ` Roedel, Joerg 0 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-26 14:43 UTC (permalink / raw) To: Florian Dazinger; +Cc: Alex Williamson, linux-kernel, iommu Florian, On Wed, Sep 26, 2012 at 01:01:54AM +0200, Florian Dazinger wrote: > you're right, either "amd_iommu=off" or removing the audio card makes > the failure disappear. I will test the new BIOS rev. tomorrow. Can you please test this diff and report if it fixes the problem for you? Thanks. diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index b64502d..e89daf1 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -266,7 +266,7 @@ static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) static int iommu_init_device(struct device *dev) { - struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); + struct pci_dev *dma_pdev = NULL, *pdev = to_pci_dev(dev); struct iommu_dev_data *dev_data; struct iommu_group *group; u16 alias; @@ -293,7 +293,9 @@ static int iommu_init_device(struct device *dev) dev_data->alias_data = alias_data; dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); - } else + } + + if (dma_pdev == NULL) dma_pdev = pci_dev_get(pdev); /* Account for quirked devices */ -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 14:43 ` Roedel, Joerg 0 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-26 14:43 UTC (permalink / raw) To: Florian Dazinger; +Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, iommu Florian, On Wed, Sep 26, 2012 at 01:01:54AM +0200, Florian Dazinger wrote: > you're right, either "amd_iommu=off" or removing the audio card makes > the failure disappear. I will test the new BIOS rev. tomorrow. Can you please test this diff and report if it fixes the problem for you? Thanks. diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index b64502d..e89daf1 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -266,7 +266,7 @@ static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) static int iommu_init_device(struct device *dev) { - struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); + struct pci_dev *dma_pdev = NULL, *pdev = to_pci_dev(dev); struct iommu_dev_data *dev_data; struct iommu_group *group; u16 alias; @@ -293,7 +293,9 @@ static int iommu_init_device(struct device *dev) dev_data->alias_data = alias_data; dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); - } else + } + + if (dma_pdev == NULL) dma_pdev = pci_dev_get(pdev); /* Account for quirked devices */ -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 14:52 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 14:52 UTC (permalink / raw) To: Roedel, Joerg; +Cc: Florian Dazinger, linux-kernel, iommu On Wed, 2012-09-26 at 16:43 +0200, Roedel, Joerg wrote: > Florian, > > On Wed, Sep 26, 2012 at 01:01:54AM +0200, Florian Dazinger wrote: > > you're right, either "amd_iommu=off" or removing the audio card makes > > the failure disappear. I will test the new BIOS rev. tomorrow. > > Can you please test this diff and report if it fixes the problem for > you? > > Thanks. > > diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c > index b64502d..e89daf1 100644 > --- a/drivers/iommu/amd_iommu.c > +++ b/drivers/iommu/amd_iommu.c > @@ -266,7 +266,7 @@ static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) > > static int iommu_init_device(struct device *dev) > { > - struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); > + struct pci_dev *dma_pdev = NULL, *pdev = to_pci_dev(dev); > struct iommu_dev_data *dev_data; > struct iommu_group *group; > u16 alias; > @@ -293,7 +293,9 @@ static int iommu_init_device(struct device *dev) > dev_data->alias_data = alias_data; > > dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); > - } else > + } > + > + if (dma_pdev == NULL) > dma_pdev = pci_dev_get(pdev); > > /* Account for quirked devices */ > Assuming this works, it may be ok as a 3.7 fix, but if there was actually more than one device behind the alias we'd expose them as separate iommu groups. I don't think that's what we want. Maybe it should at least get a pr_warn. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 14:52 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 14:52 UTC (permalink / raw) To: Roedel, Joerg Cc: Florian Dazinger, iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, 2012-09-26 at 16:43 +0200, Roedel, Joerg wrote: > Florian, > > On Wed, Sep 26, 2012 at 01:01:54AM +0200, Florian Dazinger wrote: > > you're right, either "amd_iommu=off" or removing the audio card makes > > the failure disappear. I will test the new BIOS rev. tomorrow. > > Can you please test this diff and report if it fixes the problem for > you? > > Thanks. > > diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c > index b64502d..e89daf1 100644 > --- a/drivers/iommu/amd_iommu.c > +++ b/drivers/iommu/amd_iommu.c > @@ -266,7 +266,7 @@ static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) > > static int iommu_init_device(struct device *dev) > { > - struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); > + struct pci_dev *dma_pdev = NULL, *pdev = to_pci_dev(dev); > struct iommu_dev_data *dev_data; > struct iommu_group *group; > u16 alias; > @@ -293,7 +293,9 @@ static int iommu_init_device(struct device *dev) > dev_data->alias_data = alias_data; > > dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); > - } else > + } > + > + if (dma_pdev == NULL) > dma_pdev = pci_dev_get(pdev); > > /* Account for quirked devices */ > Assuming this works, it may be ok as a 3.7 fix, but if there was actually more than one device behind the alias we'd expose them as separate iommu groups. I don't think that's what we want. Maybe it should at least get a pr_warn. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection 2012-09-26 14:52 ` Alex Williamson @ 2012-09-26 15:04 ` Roedel, Joerg -1 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-26 15:04 UTC (permalink / raw) To: Alex Williamson; +Cc: Florian Dazinger, linux-kernel, iommu On Wed, Sep 26, 2012 at 08:52:01AM -0600, Alex Williamson wrote: > Assuming this works, it may be ok as a 3.7 fix, but if there was > actually more than one device behind the alias we'd expose them as > separate iommu groups. I don't think that's what we want. Maybe it > should at least get a pr_warn. Thanks, True, we need something more generic as the real fix. When Florian reports success I'll try to get this still into 3.6, otherwise to -stable. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 15:04 ` Roedel, Joerg 0 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-26 15:04 UTC (permalink / raw) To: Alex Williamson; +Cc: Florian Dazinger, linux-kernel, iommu On Wed, Sep 26, 2012 at 08:52:01AM -0600, Alex Williamson wrote: > Assuming this works, it may be ok as a 3.7 fix, but if there was > actually more than one device behind the alias we'd expose them as > separate iommu groups. I don't think that's what we want. Maybe it > should at least get a pr_warn. Thanks, True, we need something more generic as the real fix. When Florian reports success I'll try to get this still into 3.6, otherwise to -stable. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 16:13 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 16:13 UTC (permalink / raw) To: Roedel, Joerg; +Cc: Florian Dazinger, linux-kernel, iommu On Wed, 2012-09-26 at 17:04 +0200, Roedel, Joerg wrote: > On Wed, Sep 26, 2012 at 08:52:01AM -0600, Alex Williamson wrote: > > Assuming this works, it may be ok as a 3.7 fix, but if there was > > actually more than one device behind the alias we'd expose them as > > separate iommu groups. I don't think that's what we want. Maybe it > > should at least get a pr_warn. Thanks, > > True, we need something more generic as the real fix. When Florian > reports success I'll try to get this still into 3.6, otherwise to > -stable. Yes, 3.6 is what I meant to type. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 16:13 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 16:13 UTC (permalink / raw) To: Roedel, Joerg Cc: Florian Dazinger, iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, 2012-09-26 at 17:04 +0200, Roedel, Joerg wrote: > On Wed, Sep 26, 2012 at 08:52:01AM -0600, Alex Williamson wrote: > > Assuming this works, it may be ok as a 3.7 fix, but if there was > > actually more than one device behind the alias we'd expose them as > > separate iommu groups. I don't think that's what we want. Maybe it > > should at least get a pr_warn. Thanks, > > True, we need something more generic as the real fix. When Florian > reports success I'll try to get this still into 3.6, otherwise to > -stable. Yes, 3.6 is what I meant to type. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 16:43 ` Florian Dazinger 0 siblings, 0 replies; 37+ messages in thread From: Florian Dazinger @ 2012-09-26 16:43 UTC (permalink / raw) To: Roedel, Joerg; +Cc: Alex Williamson, linux-kernel, iommu Am Wed, 26 Sep 2012 17:04:07 +0200 schrieb "Roedel, Joerg" <Joerg.Roedel@amd.com>: > On Wed, Sep 26, 2012 at 08:52:01AM -0600, Alex Williamson wrote: > > Assuming this works, it may be ok as a 3.7 fix, but if there was > > actually more than one device behind the alias we'd expose them as > > separate iommu groups. I don't think that's what we want. Maybe it > > should at least get a pr_warn. Thanks, > > True, we need something more generic as the real fix. When Florian > reports success I'll try to get this still into 3.6, otherwise to > -stable. > > > Joerg > it still fails with the card in a *different* slot. But with the patch applied, everything works, so this fixes it for me! Thanks a lot. Output of the relevant parts of dmesg and lspci see below. I'll still try the newest BIOS rev. and report back. thx, Florian dmesg (kernel-3.5.4): [ 0.448252] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 1.471021] pci 0000:01:00.0: Boot video device [ 1.471118] PCI: CLS 64 bytes, default 64 [ 1.473864] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 [ 1.473902] AMD-Vi: mmio-addr: 00000000feb20000 [ 1.474119] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 [ 1.474153] AMD-Vi: DEV_RANGE_END devid: 00:00.2 [ 1.474187] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 [ 1.474220] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 [ 1.474254] AMD-Vi: DEV_RANGE_END devid: 01:00.1 [ 1.474287] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 [ 1.474321] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 [ 1.474354] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 [ 1.474388] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 [ 1.474421] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 [ 1.474455] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 [ 1.474488] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 [ 1.474522] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 [ 1.474555] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 [ 1.474589] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 [ 1.474622] AMD-Vi: DEV_SELECT devid: 00:0d.0 flags: 00 [ 1.474656] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 [ 1.474689] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 [ 1.474726] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 [ 1.474764] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 [ 1.474798] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 [ 1.474836] AMD-Vi: DEV_RANGE_END devid: 00:12.2 [ 1.474870] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 [ 1.474903] AMD-Vi: DEV_RANGE_END devid: 00:13.2 [ 1.474937] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 [ 1.474970] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 [ 1.475004] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 [ 1.475038] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 [ 1.475074] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 [ 1.475112] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 [ 1.475146] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 [ 1.475180] AMD-Vi: DEV_RANGE_END devid: 00:16.2 [ 1.475271] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 [ 1.529007] pci 0000:00:00.2: irq 72 for MSI/MSI-X [ 1.539126] AMD-Vi: Lazy IO/TLB flushing enabled [ 1.539750] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 1.539787] software IO TLB [mem 0xc9728000-0xcd727fff] (64MB) mapped at [ffff8800c9728000-ffff8800cd727fff] [ 1.539957] kvm: Nested Virtualization enabled lspci (kernel-3.5.4): 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) Subsystem: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Capabilities: [f0] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [c4] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=20 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency 0: [b] Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [40] HyperTransport: Retry Mode Capabilities: [54] HyperTransport: UnitID Clumping Capabilities: [9c] HyperTransport: #1a Capabilities: [70] MSI: Enable- Count=1/4 Maskable- 64bit- Address: 00000000 Data: 0000 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) Subsystem: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 72 Capabilities: [40] Secure device <?> Capabilities: [54] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 41a9 Capabilities: [64] HyperTransport: MSI Mapping Enable+ Fixed+ 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fea00000-feafffff Prefetchable memory behind bridge: 00000000d0000000-00000000dfffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #2, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: fe900000-fe9fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #4, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport [...snip...] 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Power Budgeting <?> 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (500ns min, 6000ns max) Interrupt: pin A routed to IRQ 40 Region 0: I/O ports at b000 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: snd_virtuoso dmesg (rc7 + patch) [ 1.473964] pci 0000:01:00.0: Boot video device [ 1.474061] PCI: CLS 64 bytes, default 64 [ 1.476724] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 [ 1.476762] AMD-Vi: mmio-addr: 00000000feb20000 [ 1.476840] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 [ 1.476875] AMD-Vi: DEV_RANGE_END devid: 00:00.2 [ 1.476908] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 [ 1.476942] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 [ 1.476976] AMD-Vi: DEV_RANGE_END devid: 01:00.1 [ 1.477009] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 [ 1.477043] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 [ 1.477076] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 [ 1.477110] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 [ 1.477143] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 [ 1.477176] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 [ 1.477210] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 [ 1.477244] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 [ 1.477277] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 [ 1.477311] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 [ 1.477344] AMD-Vi: DEV_SELECT devid: 00:0d.0 flags: 00 [ 1.477378] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 [ 1.477412] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 [ 1.477449] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 [ 1.477486] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 [ 1.477520] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 [ 1.477553] AMD-Vi: DEV_RANGE_END devid: 00:12.2 [ 1.477587] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 [ 1.477620] AMD-Vi: DEV_RANGE_END devid: 00:13.2 [ 1.477654] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 [ 1.477688] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 [ 1.477721] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 [ 1.477755] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 [ 1.477801] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 [ 1.477840] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 [ 1.477874] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 [ 1.477908] AMD-Vi: DEV_RANGE_END devid: 00:16.2 [ 1.532188] AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40 [ 1.532224] [ 1.532274] pci 0000:00:00.2: irq 72 for MSI/MSI-X [ 1.542311] AMD-Vi: Lazy IO/TLB flushing enabled [ 1.542349] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 1.542384] software IO TLB [mem 0xc9728000-0xcd727fff] (64MB) mapped at [ffff8800c9728000-ffff8800cd727fff] lspci (rc7 + patch) 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Power Budgeting <?> 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (500ns min, 6000ns max) Interrupt: pin A routed to IRQ 40 Region 0: I/O ports at b000 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: snd_virtuoso ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 16:43 ` Florian Dazinger 0 siblings, 0 replies; 37+ messages in thread From: Florian Dazinger @ 2012-09-26 16:43 UTC (permalink / raw) To: Roedel, Joerg; +Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, iommu Am Wed, 26 Sep 2012 17:04:07 +0200 schrieb "Roedel, Joerg" <Joerg.Roedel-5C7GfCeVMHo@public.gmane.org>: > On Wed, Sep 26, 2012 at 08:52:01AM -0600, Alex Williamson wrote: > > Assuming this works, it may be ok as a 3.7 fix, but if there was > > actually more than one device behind the alias we'd expose them as > > separate iommu groups. I don't think that's what we want. Maybe it > > should at least get a pr_warn. Thanks, > > True, we need something more generic as the real fix. When Florian > reports success I'll try to get this still into 3.6, otherwise to > -stable. > > > Joerg > it still fails with the card in a *different* slot. But with the patch applied, everything works, so this fixes it for me! Thanks a lot. Output of the relevant parts of dmesg and lspci see below. I'll still try the newest BIOS rev. and report back. thx, Florian dmesg (kernel-3.5.4): [ 0.448252] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 1.471021] pci 0000:01:00.0: Boot video device [ 1.471118] PCI: CLS 64 bytes, default 64 [ 1.473864] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 [ 1.473902] AMD-Vi: mmio-addr: 00000000feb20000 [ 1.474119] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 [ 1.474153] AMD-Vi: DEV_RANGE_END devid: 00:00.2 [ 1.474187] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 [ 1.474220] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 [ 1.474254] AMD-Vi: DEV_RANGE_END devid: 01:00.1 [ 1.474287] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 [ 1.474321] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 [ 1.474354] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 [ 1.474388] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 [ 1.474421] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 [ 1.474455] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 [ 1.474488] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 [ 1.474522] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 [ 1.474555] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 [ 1.474589] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 [ 1.474622] AMD-Vi: DEV_SELECT devid: 00:0d.0 flags: 00 [ 1.474656] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 [ 1.474689] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 [ 1.474726] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 [ 1.474764] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 [ 1.474798] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 [ 1.474836] AMD-Vi: DEV_RANGE_END devid: 00:12.2 [ 1.474870] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 [ 1.474903] AMD-Vi: DEV_RANGE_END devid: 00:13.2 [ 1.474937] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 [ 1.474970] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 [ 1.475004] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 [ 1.475038] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 [ 1.475074] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 [ 1.475112] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 [ 1.475146] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 [ 1.475180] AMD-Vi: DEV_RANGE_END devid: 00:16.2 [ 1.475271] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 [ 1.529007] pci 0000:00:00.2: irq 72 for MSI/MSI-X [ 1.539126] AMD-Vi: Lazy IO/TLB flushing enabled [ 1.539750] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 1.539787] software IO TLB [mem 0xc9728000-0xcd727fff] (64MB) mapped at [ffff8800c9728000-ffff8800cd727fff] [ 1.539957] kvm: Nested Virtualization enabled lspci (kernel-3.5.4): 00:00.0 Host bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) (rev 02) Subsystem: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (external gfx0 port B) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Capabilities: [f0] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [c4] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=20 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency 0: [b] Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [40] HyperTransport: Retry Mode Capabilities: [54] HyperTransport: UnitID Clumping Capabilities: [9c] HyperTransport: #1a Capabilities: [70] MSI: Enable- Count=1/4 Maskable- 64bit- Address: 00000000 Data: 0000 00:00.2 IOMMU: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) Subsystem: Advanced Micro Devices [AMD] nee ATI RD990 I/O Memory Management Unit (IOMMU) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 72 Capabilities: [40] Secure device <?> Capabilities: [54] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 41a9 Capabilities: [64] HyperTransport: MSI Mapping Enable+ Fixed+ 00:02.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port B) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fea00000-feafffff Prefetchable memory behind bridge: 00000000d0000000-00000000dfffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #2, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport 00:04.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI RD890 PCI to PCI bridge (PCI express gpp port D) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: fe900000-fe9fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Latency L0 <1us, L1 <8us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #4, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] nee ATI Device 5a14 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [190 v1] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+ ACSCtl: SrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- Kernel driver in use: pcieport [...snip...] 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Power Budgeting <?> 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (500ns min, 6000ns max) Interrupt: pin A routed to IRQ 40 Region 0: I/O ports at b000 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: snd_virtuoso dmesg (rc7 + patch) [ 1.473964] pci 0000:01:00.0: Boot video device [ 1.474061] PCI: CLS 64 bytes, default 64 [ 1.476724] AMD-Vi: device: 00:00.2 cap: 0040 seg: 0 flags: 3e info 1300 [ 1.476762] AMD-Vi: mmio-addr: 00000000feb20000 [ 1.476840] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:00.0 flags: 00 [ 1.476875] AMD-Vi: DEV_RANGE_END devid: 00:00.2 [ 1.476908] AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 [ 1.476942] AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 [ 1.476976] AMD-Vi: DEV_RANGE_END devid: 01:00.1 [ 1.477009] AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 [ 1.477043] AMD-Vi: DEV_SELECT devid: 02:00.0 flags: 00 [ 1.477076] AMD-Vi: DEV_SELECT devid: 00:05.0 flags: 00 [ 1.477110] AMD-Vi: DEV_SELECT devid: 03:00.0 flags: 00 [ 1.477143] AMD-Vi: DEV_SELECT devid: 00:06.0 flags: 00 [ 1.477176] AMD-Vi: DEV_SELECT devid: 04:00.0 flags: 00 [ 1.477210] AMD-Vi: DEV_SELECT devid: 00:07.0 flags: 00 [ 1.477244] AMD-Vi: DEV_SELECT devid: 05:00.0 flags: 00 [ 1.477277] AMD-Vi: DEV_SELECT devid: 00:09.0 flags: 00 [ 1.477311] AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 [ 1.477344] AMD-Vi: DEV_SELECT devid: 00:0d.0 flags: 00 [ 1.477378] AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 [ 1.477412] AMD-Vi: DEV_ALIAS_RANGE devid: 08:01.0 flags: 00 devid_to: 08:00.0 [ 1.477449] AMD-Vi: DEV_RANGE_END devid: 08:1f.7 [ 1.477486] AMD-Vi: DEV_SELECT devid: 00:11.0 flags: 00 [ 1.477520] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:12.0 flags: 00 [ 1.477553] AMD-Vi: DEV_RANGE_END devid: 00:12.2 [ 1.477587] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:13.0 flags: 00 [ 1.477620] AMD-Vi: DEV_RANGE_END devid: 00:13.2 [ 1.477654] AMD-Vi: DEV_SELECT devid: 00:14.0 flags: d7 [ 1.477688] AMD-Vi: DEV_SELECT devid: 00:14.3 flags: 00 [ 1.477721] AMD-Vi: DEV_SELECT devid: 00:14.4 flags: 00 [ 1.477755] AMD-Vi: DEV_ALIAS_RANGE devid: 09:00.0 flags: 00 devid_to: 00:14.4 [ 1.477801] AMD-Vi: DEV_RANGE_END devid: 09:1f.7 [ 1.477840] AMD-Vi: DEV_SELECT devid: 00:14.5 flags: 00 [ 1.477874] AMD-Vi: DEV_SELECT_RANGE_START devid: 00:16.0 flags: 00 [ 1.477908] AMD-Vi: DEV_RANGE_END devid: 00:16.2 [ 1.532188] AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40 [ 1.532224] [ 1.532274] pci 0000:00:00.2: irq 72 for MSI/MSI-X [ 1.542311] AMD-Vi: Lazy IO/TLB flushing enabled [ 1.542349] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 1.542384] software IO TLB [mem 0xc9728000-0xcd727fff] (64MB) mapped at [ffff8800c9728000-ffff8800cd727fff] lspci (rc7 + patch) 07:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=07, secondary=08, subordinate=08, sec-latency=32 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) PCI/PCI-X Bridge, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Power Budgeting <?> 08:04.0 Multimedia audio controller: C-Media Electronics Inc CMI8788 [Oxygen HD Audio] Subsystem: ASUSTeK Computer Inc. Virtuoso 100 (Xonar Essence STX) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (500ns min, 6000ns max) Interrupt: pin A routed to IRQ 40 Region 0: I/O ports at b000 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: snd_virtuoso ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 17:47 ` Florian Dazinger 0 siblings, 0 replies; 37+ messages in thread From: Florian Dazinger @ 2012-09-26 17:47 UTC (permalink / raw) To: Roedel, Joerg; +Cc: Alex Williamson, linux-kernel, iommu Am Wed, 26 Sep 2012 17:04:07 +0200 schrieb "Roedel, Joerg" <Joerg.Roedel@amd.com>: > On Wed, Sep 26, 2012 at 08:52:01AM -0600, Alex Williamson wrote: > > Assuming this works, it may be ok as a 3.7 fix, but if there was > > actually more than one device behind the alias we'd expose them as > > separate iommu groups. I don't think that's what we want. Maybe it > > should at least get a pr_warn. Thanks, > > True, we need something more generic as the real fix. When Florian > reports success I'll try to get this still into 3.6, otherwise to > -stable. > > > Joerg > ... updating to the newest BIOS revision does not make any difference, rc7 is crashing, rc7+patch is not, I definitely need this patch. If there is more you want me to test, pls tell. Florian ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 17:47 ` Florian Dazinger 0 siblings, 0 replies; 37+ messages in thread From: Florian Dazinger @ 2012-09-26 17:47 UTC (permalink / raw) To: Roedel, Joerg; +Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, iommu Am Wed, 26 Sep 2012 17:04:07 +0200 schrieb "Roedel, Joerg" <Joerg.Roedel-5C7GfCeVMHo@public.gmane.org>: > On Wed, Sep 26, 2012 at 08:52:01AM -0600, Alex Williamson wrote: > > Assuming this works, it may be ok as a 3.7 fix, but if there was > > actually more than one device behind the alias we'd expose them as > > separate iommu groups. I don't think that's what we want. Maybe it > > should at least get a pr_warn. Thanks, > > True, we need something more generic as the real fix. When Florian > reports success I'll try to get this still into 3.6, otherwise to > -stable. > > > Joerg > ... updating to the newest BIOS revision does not make any difference, rc7 is crashing, rc7+patch is not, I definitely need this patch. If there is more you want me to test, pls tell. Florian ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 13:20 ` Roedel, Joerg 0 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-26 13:20 UTC (permalink / raw) To: Alex Williamson; +Cc: Florian Dazinger, linux-kernel, iommu On Tue, Sep 25, 2012 at 01:43:46PM -0600, Alex Williamson wrote: > Joerg, any thoughts on a quirk for this? Unfortunately we can't just > skip IOMMU groups when an alias is broken because it puts the other > IOMMU groups at risk that might not actually be isolated from this > device. It looks like we parse the alias info before PCI is probed, so > maybe we'd need to call the quirk from iommu_init_device itself. I fear that the BIOS does everything right and device 08:04.0 is indeed using 08:00.0 as request-id. There are a couple of devices where this happens, usually when the vendor just took the old 32bit PCI chip, added a transparent PCIe-to-PCI bridge to the device and sell it a PCIe. So the assumption that every request-id has a corresponding pci_dev structure does not hold. I also had made that assumption in the AMD IOMMU driver but had to add code which removes that assumption. We should look for a way to remove that assumption from the group-code too. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 13:20 ` Roedel, Joerg 0 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-26 13:20 UTC (permalink / raw) To: Alex Williamson Cc: Florian Dazinger, iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Tue, Sep 25, 2012 at 01:43:46PM -0600, Alex Williamson wrote: > Joerg, any thoughts on a quirk for this? Unfortunately we can't just > skip IOMMU groups when an alias is broken because it puts the other > IOMMU groups at risk that might not actually be isolated from this > device. It looks like we parse the alias info before PCI is probed, so > maybe we'd need to call the quirk from iommu_init_device itself. I fear that the BIOS does everything right and device 08:04.0 is indeed using 08:00.0 as request-id. There are a couple of devices where this happens, usually when the vendor just took the old 32bit PCI chip, added a transparent PCIe-to-PCI bridge to the device and sell it a PCIe. So the assumption that every request-id has a corresponding pci_dev structure does not hold. I also had made that assumption in the AMD IOMMU driver but had to add code which removes that assumption. We should look for a way to remove that assumption from the group-code too. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 14:35 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 14:35 UTC (permalink / raw) To: Roedel, Joerg; +Cc: Florian Dazinger, linux-kernel, iommu On Wed, 2012-09-26 at 15:20 +0200, Roedel, Joerg wrote: > On Tue, Sep 25, 2012 at 01:43:46PM -0600, Alex Williamson wrote: > > Joerg, any thoughts on a quirk for this? Unfortunately we can't just > > skip IOMMU groups when an alias is broken because it puts the other > > IOMMU groups at risk that might not actually be isolated from this > > device. It looks like we parse the alias info before PCI is probed, so > > maybe we'd need to call the quirk from iommu_init_device itself. > > I fear that the BIOS does everything right and device 08:04.0 is indeed > using 08:00.0 as request-id. There are a couple of devices where this > happens, usually when the vendor just took the old 32bit PCI chip, added > a transparent PCIe-to-PCI bridge to the device and sell it a PCIe. > > So the assumption that every request-id has a corresponding pci_dev > structure does not hold. I also had made that assumption in the > AMD IOMMU driver but had to add code which removes that assumption. We > should look for a way to remove that assumption from the group-code too. Hmm, that throws a kink in iommu groups. So perhaps we need to make an alias interface to iommu groups. Seems like this could just be an extra parameter to iommu_group_get and iommu_group_add_device (empty in the typical case). Then we have the problem of what's the type for an alias? For AMI-Vi, it's a u16, but we need to be more generic than that. Maybe iommu groups should just treat it as a void* so iommus can use a pointer to some structure or a fixed value like a u16 bus:slot. Thoughts? Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 14:35 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 14:35 UTC (permalink / raw) To: Roedel, Joerg Cc: Florian Dazinger, iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, 2012-09-26 at 15:20 +0200, Roedel, Joerg wrote: > On Tue, Sep 25, 2012 at 01:43:46PM -0600, Alex Williamson wrote: > > Joerg, any thoughts on a quirk for this? Unfortunately we can't just > > skip IOMMU groups when an alias is broken because it puts the other > > IOMMU groups at risk that might not actually be isolated from this > > device. It looks like we parse the alias info before PCI is probed, so > > maybe we'd need to call the quirk from iommu_init_device itself. > > I fear that the BIOS does everything right and device 08:04.0 is indeed > using 08:00.0 as request-id. There are a couple of devices where this > happens, usually when the vendor just took the old 32bit PCI chip, added > a transparent PCIe-to-PCI bridge to the device and sell it a PCIe. > > So the assumption that every request-id has a corresponding pci_dev > structure does not hold. I also had made that assumption in the > AMD IOMMU driver but had to add code which removes that assumption. We > should look for a way to remove that assumption from the group-code too. Hmm, that throws a kink in iommu groups. So perhaps we need to make an alias interface to iommu groups. Seems like this could just be an extra parameter to iommu_group_get and iommu_group_add_device (empty in the typical case). Then we have the problem of what's the type for an alias? For AMI-Vi, it's a u16, but we need to be more generic than that. Maybe iommu groups should just treat it as a void* so iommus can use a pointer to some structure or a fixed value like a u16 bus:slot. Thoughts? Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 15:10 ` Roedel, Joerg 0 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-26 15:10 UTC (permalink / raw) To: Alex Williamson; +Cc: Florian Dazinger, linux-kernel, iommu On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > alias interface to iommu groups. Seems like this could just be an extra > parameter to iommu_group_get and iommu_group_add_device (empty in the > typical case). Then we have the problem of what's the type for an > alias? For AMI-Vi, it's a u16, but we need to be more generic than > that. Maybe iommu groups should just treat it as a void* so iommus can > use a pointer to some structure or a fixed value like a u16 bus:slot. > Thoughts? Good question. The iommu-groups are part of the IOMMU-API, with an interface to the IOMMU drivers and one to the users of IOMMU-API. So the alias handling itself should be a function of the interface to the IOMMU driver. In general the interface should not be bus specific. So a void pointer seems the only logical choice then. But I would not limit its scope to alias handling. How about making it a bus-private pointer where IOMMU driver store bus-specific information. That way we make sure that there is one struct per bus-type for this pointer, and not one structure per IOMMU driver. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 15:10 ` Roedel, Joerg 0 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-26 15:10 UTC (permalink / raw) To: Alex Williamson Cc: Florian Dazinger, iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > alias interface to iommu groups. Seems like this could just be an extra > parameter to iommu_group_get and iommu_group_add_device (empty in the > typical case). Then we have the problem of what's the type for an > alias? For AMI-Vi, it's a u16, but we need to be more generic than > that. Maybe iommu groups should just treat it as a void* so iommus can > use a pointer to some structure or a fixed value like a u16 bus:slot. > Thoughts? Good question. The iommu-groups are part of the IOMMU-API, with an interface to the IOMMU drivers and one to the users of IOMMU-API. So the alias handling itself should be a function of the interface to the IOMMU driver. In general the interface should not be bus specific. So a void pointer seems the only logical choice then. But I would not limit its scope to alias handling. How about making it a bus-private pointer where IOMMU driver store bus-specific information. That way we make sure that there is one struct per bus-type for this pointer, and not one structure per IOMMU driver. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 16:21 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 16:21 UTC (permalink / raw) To: Roedel, Joerg; +Cc: Florian Dazinger, linux-kernel, iommu On Wed, 2012-09-26 at 17:10 +0200, Roedel, Joerg wrote: > On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > > alias interface to iommu groups. Seems like this could just be an extra > > parameter to iommu_group_get and iommu_group_add_device (empty in the > > typical case). Then we have the problem of what's the type for an > > alias? For AMI-Vi, it's a u16, but we need to be more generic than > > that. Maybe iommu groups should just treat it as a void* so iommus can > > use a pointer to some structure or a fixed value like a u16 bus:slot. > > Thoughts? > > Good question. The iommu-groups are part of the IOMMU-API, with an > interface to the IOMMU drivers and one to the users of IOMMU-API. So the > alias handling itself should be a function of the interface to the IOMMU > driver. In general the interface should not be bus specific. > > So a void pointer seems the only logical choice then. But I would not > limit its scope to alias handling. How about making it a bus-private > pointer where IOMMU driver store bus-specific information. That way we > make sure that there is one struct per bus-type for this pointer, and > not one structure per IOMMU driver. I thought of another approach that may actually be more 3.6 worthy. What if we just make the iommu driver handle it? For instance, amd_iommu can walk the alias table looking for entries that use the same alias and get the device via pci_get_bus_and_slot. If it finds a device with an iommu group, it attaches the new device to the same group, hiding anything about aliases from the group layer. It just groups all devices within the range. I think the only complication is making sure we're safe around device hotplug while we're doing this. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 16:21 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 16:21 UTC (permalink / raw) To: Roedel, Joerg Cc: Florian Dazinger, iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, 2012-09-26 at 17:10 +0200, Roedel, Joerg wrote: > On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > > alias interface to iommu groups. Seems like this could just be an extra > > parameter to iommu_group_get and iommu_group_add_device (empty in the > > typical case). Then we have the problem of what's the type for an > > alias? For AMI-Vi, it's a u16, but we need to be more generic than > > that. Maybe iommu groups should just treat it as a void* so iommus can > > use a pointer to some structure or a fixed value like a u16 bus:slot. > > Thoughts? > > Good question. The iommu-groups are part of the IOMMU-API, with an > interface to the IOMMU drivers and one to the users of IOMMU-API. So the > alias handling itself should be a function of the interface to the IOMMU > driver. In general the interface should not be bus specific. > > So a void pointer seems the only logical choice then. But I would not > limit its scope to alias handling. How about making it a bus-private > pointer where IOMMU driver store bus-specific information. That way we > make sure that there is one struct per bus-type for this pointer, and > not one structure per IOMMU driver. I thought of another approach that may actually be more 3.6 worthy. What if we just make the iommu driver handle it? For instance, amd_iommu can walk the alias table looking for entries that use the same alias and get the device via pci_get_bus_and_slot. If it finds a device with an iommu group, it attaches the new device to the same group, hiding anything about aliases from the group layer. It just groups all devices within the range. I think the only complication is making sure we're safe around device hotplug while we're doing this. Thanks, Alex ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 19:50 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 19:50 UTC (permalink / raw) To: Roedel, Joerg; +Cc: Florian Dazinger, iommu, linux-kernel On Wed, 2012-09-26 at 10:21 -0600, Alex Williamson wrote: > On Wed, 2012-09-26 at 17:10 +0200, Roedel, Joerg wrote: > > On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > > > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > > > alias interface to iommu groups. Seems like this could just be an extra > > > parameter to iommu_group_get and iommu_group_add_device (empty in the > > > typical case). Then we have the problem of what's the type for an > > > alias? For AMI-Vi, it's a u16, but we need to be more generic than > > > that. Maybe iommu groups should just treat it as a void* so iommus can > > > use a pointer to some structure or a fixed value like a u16 bus:slot. > > > Thoughts? > > > > Good question. The iommu-groups are part of the IOMMU-API, with an > > interface to the IOMMU drivers and one to the users of IOMMU-API. So the > > alias handling itself should be a function of the interface to the IOMMU > > driver. In general the interface should not be bus specific. > > > > So a void pointer seems the only logical choice then. But I would not > > limit its scope to alias handling. How about making it a bus-private > > pointer where IOMMU driver store bus-specific information. That way we > > make sure that there is one struct per bus-type for this pointer, and > > not one structure per IOMMU driver. > > I thought of another approach that may actually be more 3.6 worthy. > What if we just make the iommu driver handle it? For instance, > amd_iommu can walk the alias table looking for entries that use the same > alias and get the device via pci_get_bus_and_slot. If it finds a device > with an iommu group, it attaches the new device to the same group, > hiding anything about aliases from the group layer. It just groups all > devices within the range. I think the only complication is making sure > we're safe around device hotplug while we're doing this. Thanks, I think this could work. Instead of searching for other devices, check for or allocate an iommu group on the alias dev_data, any "virtual" aliases use that iommu group. Florian, could you test this as well? Thanks, Alex Signed-off-by: Alex Williamson <alex.williamson@redhat.com> --- diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index b64502d..22879ed 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -126,6 +126,8 @@ static void free_dev_data(struct iommu_dev_data *dev_data) spin_lock_irqsave(&dev_data_list_lock, flags); list_del(&dev_data->dev_data_list); + if (dev_data->group) + iommu_group_put(dev_data->group); spin_unlock_irqrestore(&dev_data_list_lock, flags); kfree(dev_data); @@ -256,6 +258,37 @@ static bool check_device(struct device *dev) return true; } +/* + * Sometimes there's no actual device for an alias. When that happens + * we allocate an iommu group on the iommu_dev_data so that it gets used + * by anything with the same alias. We keep the reference from + * iommu_group_alloc so the group persists with the iommu_dev_data. + */ +static int dev_data_add_iommu_group(struct iommu_dev_data *dev_data, + struct device *dev) +{ + unsigned long flags; + struct iommu_group *group; + int ret = 0; + + spin_lock_irqsave(&dev_data_list_lock, flags); + if (!dev_data->group) { + group = iommu_group_alloc(); + if (IS_ERR(group)) { + ret = PTR_ERR(group); + goto unlock; + } + + dev_data->group = group; + } else + group = dev_data->group; + + ret = iommu_group_add_device(group, dev); +unlock: + spin_unlock_irqrestore(&dev_data_list_lock, flags); + return ret; +} + static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) { pci_dev_put(*from); @@ -264,38 +297,12 @@ static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) -static int iommu_init_device(struct device *dev) +static int pdev_add_iommu_group(struct pci_dev *pdev, struct device *dev) { - struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); - struct iommu_dev_data *dev_data; + struct pci_dev *dma_pdev = pdev; struct iommu_group *group; - u16 alias; int ret; - if (dev->archdata.iommu) - return 0; - - dev_data = find_dev_data(get_device_id(dev)); - if (!dev_data) - return -ENOMEM; - - alias = amd_iommu_alias_table[dev_data->devid]; - if (alias != dev_data->devid) { - struct iommu_dev_data *alias_data; - - alias_data = find_dev_data(alias); - if (alias_data == NULL) { - pr_err("AMD-Vi: Warning: Unhandled device %s\n", - dev_name(dev)); - free_dev_data(dev_data); - return -ENOTSUPP; - } - dev_data->alias_data = alias_data; - - dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); - } else - dma_pdev = pci_dev_get(pdev); - /* Account for quirked devices */ swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); @@ -344,8 +351,61 @@ root_bus: iommu_group_put(group); - if (ret) - return ret; + return ret; +} + +static int iommu_init_device(struct device *dev) +{ + struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); + struct iommu_dev_data *dev_data; + u16 alias; + int ret; + + if (dev->archdata.iommu) + return 0; + + dev_data = find_dev_data(get_device_id(dev)); + if (!dev_data) + return -ENOMEM; + + alias = amd_iommu_alias_table[dev_data->devid]; + if (alias != dev_data->devid) { + struct iommu_dev_data *alias_data; + + alias_data = find_dev_data(alias); + if (alias_data == NULL) { + pr_err("AMD-Vi: Warning: Unhandled device %s\n", + dev_name(dev)); + free_dev_data(dev_data); + return -ENOTSUPP; + } + dev_data->alias_data = alias_data; + + /* + * If the alias device exists, use it as the base dma + * device. This results in all devices aliasing to this + * one to be in the same iommu group. If it doesn't + * actually exist, store the iommu group on the alias + * dev_data and use that for all aliases. + */ + dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); + if (!dma_pdev) { + ret = dev_data_add_iommu_group(alias_data, dev); + if (ret) { + free_dev_data(dev_data); + return ret; + } + } + } else + dma_pdev = pci_dev_get(pdev); + + if (dma_pdev) { + ret = pdev_add_iommu_group(dma_pdev, dev); + if (ret) { + free_dev_data(dev_data); + return ret; + } + } if (pci_iommuv2_capable(pdev)) { struct amd_iommu *iommu; diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index d0dab86..6597d6a 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -404,6 +404,7 @@ struct iommu_dev_data { struct list_head dev_data_list; /* For global dev_data_list */ struct iommu_dev_data *alias_data;/* The alias dev_data */ struct protection_domain *domain; /* Domain the device is bound to */ + struct iommu_group *group; /* IOMMU group for virtual aliases */ atomic_t bind; /* Domain attach reverent count */ u16 devid; /* PCI Device ID */ bool iommu_v2; /* Device can make use of IOMMUv2 */ ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 19:50 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 19:50 UTC (permalink / raw) To: Roedel, Joerg Cc: Florian Dazinger, iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, 2012-09-26 at 10:21 -0600, Alex Williamson wrote: > On Wed, 2012-09-26 at 17:10 +0200, Roedel, Joerg wrote: > > On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > > > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > > > alias interface to iommu groups. Seems like this could just be an extra > > > parameter to iommu_group_get and iommu_group_add_device (empty in the > > > typical case). Then we have the problem of what's the type for an > > > alias? For AMI-Vi, it's a u16, but we need to be more generic than > > > that. Maybe iommu groups should just treat it as a void* so iommus can > > > use a pointer to some structure or a fixed value like a u16 bus:slot. > > > Thoughts? > > > > Good question. The iommu-groups are part of the IOMMU-API, with an > > interface to the IOMMU drivers and one to the users of IOMMU-API. So the > > alias handling itself should be a function of the interface to the IOMMU > > driver. In general the interface should not be bus specific. > > > > So a void pointer seems the only logical choice then. But I would not > > limit its scope to alias handling. How about making it a bus-private > > pointer where IOMMU driver store bus-specific information. That way we > > make sure that there is one struct per bus-type for this pointer, and > > not one structure per IOMMU driver. > > I thought of another approach that may actually be more 3.6 worthy. > What if we just make the iommu driver handle it? For instance, > amd_iommu can walk the alias table looking for entries that use the same > alias and get the device via pci_get_bus_and_slot. If it finds a device > with an iommu group, it attaches the new device to the same group, > hiding anything about aliases from the group layer. It just groups all > devices within the range. I think the only complication is making sure > we're safe around device hotplug while we're doing this. Thanks, I think this could work. Instead of searching for other devices, check for or allocate an iommu group on the alias dev_data, any "virtual" aliases use that iommu group. Florian, could you test this as well? Thanks, Alex Signed-off-by: Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> --- diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index b64502d..22879ed 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -126,6 +126,8 @@ static void free_dev_data(struct iommu_dev_data *dev_data) spin_lock_irqsave(&dev_data_list_lock, flags); list_del(&dev_data->dev_data_list); + if (dev_data->group) + iommu_group_put(dev_data->group); spin_unlock_irqrestore(&dev_data_list_lock, flags); kfree(dev_data); @@ -256,6 +258,37 @@ static bool check_device(struct device *dev) return true; } +/* + * Sometimes there's no actual device for an alias. When that happens + * we allocate an iommu group on the iommu_dev_data so that it gets used + * by anything with the same alias. We keep the reference from + * iommu_group_alloc so the group persists with the iommu_dev_data. + */ +static int dev_data_add_iommu_group(struct iommu_dev_data *dev_data, + struct device *dev) +{ + unsigned long flags; + struct iommu_group *group; + int ret = 0; + + spin_lock_irqsave(&dev_data_list_lock, flags); + if (!dev_data->group) { + group = iommu_group_alloc(); + if (IS_ERR(group)) { + ret = PTR_ERR(group); + goto unlock; + } + + dev_data->group = group; + } else + group = dev_data->group; + + ret = iommu_group_add_device(group, dev); +unlock: + spin_unlock_irqrestore(&dev_data_list_lock, flags); + return ret; +} + static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) { pci_dev_put(*from); @@ -264,38 +297,12 @@ static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) -static int iommu_init_device(struct device *dev) +static int pdev_add_iommu_group(struct pci_dev *pdev, struct device *dev) { - struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); - struct iommu_dev_data *dev_data; + struct pci_dev *dma_pdev = pdev; struct iommu_group *group; - u16 alias; int ret; - if (dev->archdata.iommu) - return 0; - - dev_data = find_dev_data(get_device_id(dev)); - if (!dev_data) - return -ENOMEM; - - alias = amd_iommu_alias_table[dev_data->devid]; - if (alias != dev_data->devid) { - struct iommu_dev_data *alias_data; - - alias_data = find_dev_data(alias); - if (alias_data == NULL) { - pr_err("AMD-Vi: Warning: Unhandled device %s\n", - dev_name(dev)); - free_dev_data(dev_data); - return -ENOTSUPP; - } - dev_data->alias_data = alias_data; - - dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); - } else - dma_pdev = pci_dev_get(pdev); - /* Account for quirked devices */ swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); @@ -344,8 +351,61 @@ root_bus: iommu_group_put(group); - if (ret) - return ret; + return ret; +} + +static int iommu_init_device(struct device *dev) +{ + struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); + struct iommu_dev_data *dev_data; + u16 alias; + int ret; + + if (dev->archdata.iommu) + return 0; + + dev_data = find_dev_data(get_device_id(dev)); + if (!dev_data) + return -ENOMEM; + + alias = amd_iommu_alias_table[dev_data->devid]; + if (alias != dev_data->devid) { + struct iommu_dev_data *alias_data; + + alias_data = find_dev_data(alias); + if (alias_data == NULL) { + pr_err("AMD-Vi: Warning: Unhandled device %s\n", + dev_name(dev)); + free_dev_data(dev_data); + return -ENOTSUPP; + } + dev_data->alias_data = alias_data; + + /* + * If the alias device exists, use it as the base dma + * device. This results in all devices aliasing to this + * one to be in the same iommu group. If it doesn't + * actually exist, store the iommu group on the alias + * dev_data and use that for all aliases. + */ + dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); + if (!dma_pdev) { + ret = dev_data_add_iommu_group(alias_data, dev); + if (ret) { + free_dev_data(dev_data); + return ret; + } + } + } else + dma_pdev = pci_dev_get(pdev); + + if (dma_pdev) { + ret = pdev_add_iommu_group(dma_pdev, dev); + if (ret) { + free_dev_data(dev_data); + return ret; + } + } if (pci_iommuv2_capable(pdev)) { struct amd_iommu *iommu; diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index d0dab86..6597d6a 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -404,6 +404,7 @@ struct iommu_dev_data { struct list_head dev_data_list; /* For global dev_data_list */ struct iommu_dev_data *alias_data;/* The alias dev_data */ struct protection_domain *domain; /* Domain the device is bound to */ + struct iommu_group *group; /* IOMMU group for virtual aliases */ atomic_t bind; /* Domain attach reverent count */ u16 devid; /* PCI Device ID */ bool iommu_v2; /* Device can make use of IOMMUv2 */ ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 22:04 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 22:04 UTC (permalink / raw) To: Roedel, Joerg; +Cc: Florian Dazinger, iommu, linux-kernel On Wed, 2012-09-26 at 13:50 -0600, Alex Williamson wrote: > On Wed, 2012-09-26 at 10:21 -0600, Alex Williamson wrote: > > On Wed, 2012-09-26 at 17:10 +0200, Roedel, Joerg wrote: > > > On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > > > > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > > > > alias interface to iommu groups. Seems like this could just be an extra > > > > parameter to iommu_group_get and iommu_group_add_device (empty in the > > > > typical case). Then we have the problem of what's the type for an > > > > alias? For AMI-Vi, it's a u16, but we need to be more generic than > > > > that. Maybe iommu groups should just treat it as a void* so iommus can > > > > use a pointer to some structure or a fixed value like a u16 bus:slot. > > > > Thoughts? > > > > > > Good question. The iommu-groups are part of the IOMMU-API, with an > > > interface to the IOMMU drivers and one to the users of IOMMU-API. So the > > > alias handling itself should be a function of the interface to the IOMMU > > > driver. In general the interface should not be bus specific. > > > > > > So a void pointer seems the only logical choice then. But I would not > > > limit its scope to alias handling. How about making it a bus-private > > > pointer where IOMMU driver store bus-specific information. That way we > > > make sure that there is one struct per bus-type for this pointer, and > > > not one structure per IOMMU driver. > > > > I thought of another approach that may actually be more 3.6 worthy. > > What if we just make the iommu driver handle it? For instance, > > amd_iommu can walk the alias table looking for entries that use the same > > alias and get the device via pci_get_bus_and_slot. If it finds a device > > with an iommu group, it attaches the new device to the same group, > > hiding anything about aliases from the group layer. It just groups all > > devices within the range. I think the only complication is making sure > > we're safe around device hotplug while we're doing this. Thanks, > > I think this could work. Instead of searching for other devices, check > for or allocate an iommu group on the alias dev_data, any "virtual" > aliases use that iommu group. Florian, could you test this as well? Here's a lockdep clean version of it: amd_iommu: Handle aliases not backed by devices Aliases sometimes don't have a struct pci_dev backing them. This breaks our attempt to figure out the topology and device quirks that may effect IOMMU grouping. When this happens, allocate an IOMMU group on the dev_data for the alias and make use of it for all devices referencing this alias. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> --- diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index b64502d..4eacb17 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(iommu_pd_list_lock); /* List of all available dev_data structures */ static LIST_HEAD(dev_data_list); static DEFINE_SPINLOCK(dev_data_list_lock); +static DEFINE_MUTEX(dev_data_iommu_group_lock); /* * Domain for untranslated devices - only allocated @@ -128,6 +129,9 @@ static void free_dev_data(struct iommu_dev_data *dev_data) list_del(&dev_data->dev_data_list); spin_unlock_irqrestore(&dev_data_list_lock, flags); + if (dev_data->group) + iommu_group_put(dev_data->group); + kfree(dev_data); } @@ -256,6 +260,34 @@ static bool check_device(struct device *dev) return true; } +/* + * Sometimes there's no actual device for an alias. When that happens + * we allocate an iommu group on the dev_data and use it for anything + * aliasing back to this device. This makes sure that multiple devices + * aliased to a non-existent device id all get grouped together. Hold + * on to the reference for the group, it can be static rather than get + * automatically reclaimed if this device later gets removed. + */ +static int dev_data_add_iommu_group(struct iommu_dev_data *dev_data, + struct device *dev) +{ + mutex_lock(&dev_data_iommu_group_lock); + + if (!dev_data->group) { + struct iommu_group *group = iommu_group_alloc(); + if (IS_ERR(group)) { + mutex_unlock(&dev_data_iommu_group_lock); + return PTR_ERR(group); + } + + dev_data->group = group; + } + + mutex_unlock(&dev_data_iommu_group_lock); + + return iommu_group_add_device(dev_data->group, dev); +} + static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) { pci_dev_put(*from); @@ -264,38 +296,17 @@ static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) -static int iommu_init_device(struct device *dev) +/* + * Given a pci device, look at device quirks and topology between it + * and the IOMMU to determine the IOMMU group. Once we've found or + * created an IOMMU group, add the provided device to it. + */ +static int pdev_add_iommu_group(struct pci_dev *pdev, struct device *dev) { - struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); - struct iommu_dev_data *dev_data; + struct pci_dev *dma_pdev = pdev; struct iommu_group *group; - u16 alias; int ret; - if (dev->archdata.iommu) - return 0; - - dev_data = find_dev_data(get_device_id(dev)); - if (!dev_data) - return -ENOMEM; - - alias = amd_iommu_alias_table[dev_data->devid]; - if (alias != dev_data->devid) { - struct iommu_dev_data *alias_data; - - alias_data = find_dev_data(alias); - if (alias_data == NULL) { - pr_err("AMD-Vi: Warning: Unhandled device %s\n", - dev_name(dev)); - free_dev_data(dev_data); - return -ENOTSUPP; - } - dev_data->alias_data = alias_data; - - dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); - } else - dma_pdev = pci_dev_get(pdev); - /* Account for quirked devices */ swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); @@ -344,8 +355,61 @@ root_bus: iommu_group_put(group); - if (ret) - return ret; + return ret; +} + +static int iommu_init_device(struct device *dev) +{ + struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); + struct iommu_dev_data *dev_data; + u16 alias; + int ret; + + if (dev->archdata.iommu) + return 0; + + dev_data = find_dev_data(get_device_id(dev)); + if (!dev_data) + return -ENOMEM; + + alias = amd_iommu_alias_table[dev_data->devid]; + if (alias != dev_data->devid) { + struct iommu_dev_data *alias_data; + + alias_data = find_dev_data(alias); + if (alias_data == NULL) { + pr_err("AMD-Vi: Warning: Unhandled device %s\n", + dev_name(dev)); + free_dev_data(dev_data); + return -ENOTSUPP; + } + dev_data->alias_data = alias_data; + + /* + * If the alias device exists, use it as the base dma + * device. This results in all devices aliasing to this + * one to be in the same iommu group. If it doesn't + * actually exist, store the iommu group on the alias + * dev_data and use that for all aliases. + */ + dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); + if (!dma_pdev) { + ret = dev_data_add_iommu_group(alias_data, dev); + if (ret) { + free_dev_data(dev_data); + return ret; + } + } + } else + dma_pdev = pci_dev_get(pdev); + + if (dma_pdev) { + ret = pdev_add_iommu_group(dma_pdev, dev); + if (ret) { + free_dev_data(dev_data); + return ret; + } + } if (pci_iommuv2_capable(pdev)) { struct amd_iommu *iommu; diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index d0dab86..6597d6a 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -404,6 +404,7 @@ struct iommu_dev_data { struct list_head dev_data_list; /* For global dev_data_list */ struct iommu_dev_data *alias_data;/* The alias dev_data */ struct protection_domain *domain; /* Domain the device is bound to */ + struct iommu_group *group; /* IOMMU group for virtual aliases */ atomic_t bind; /* Domain attach reverent count */ u16 devid; /* PCI Device ID */ bool iommu_v2; /* Device can make use of IOMMUv2 */ ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-26 22:04 ` Alex Williamson 0 siblings, 0 replies; 37+ messages in thread From: Alex Williamson @ 2012-09-26 22:04 UTC (permalink / raw) To: Roedel, Joerg Cc: Florian Dazinger, iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, 2012-09-26 at 13:50 -0600, Alex Williamson wrote: > On Wed, 2012-09-26 at 10:21 -0600, Alex Williamson wrote: > > On Wed, 2012-09-26 at 17:10 +0200, Roedel, Joerg wrote: > > > On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > > > > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > > > > alias interface to iommu groups. Seems like this could just be an extra > > > > parameter to iommu_group_get and iommu_group_add_device (empty in the > > > > typical case). Then we have the problem of what's the type for an > > > > alias? For AMI-Vi, it's a u16, but we need to be more generic than > > > > that. Maybe iommu groups should just treat it as a void* so iommus can > > > > use a pointer to some structure or a fixed value like a u16 bus:slot. > > > > Thoughts? > > > > > > Good question. The iommu-groups are part of the IOMMU-API, with an > > > interface to the IOMMU drivers and one to the users of IOMMU-API. So the > > > alias handling itself should be a function of the interface to the IOMMU > > > driver. In general the interface should not be bus specific. > > > > > > So a void pointer seems the only logical choice then. But I would not > > > limit its scope to alias handling. How about making it a bus-private > > > pointer where IOMMU driver store bus-specific information. That way we > > > make sure that there is one struct per bus-type for this pointer, and > > > not one structure per IOMMU driver. > > > > I thought of another approach that may actually be more 3.6 worthy. > > What if we just make the iommu driver handle it? For instance, > > amd_iommu can walk the alias table looking for entries that use the same > > alias and get the device via pci_get_bus_and_slot. If it finds a device > > with an iommu group, it attaches the new device to the same group, > > hiding anything about aliases from the group layer. It just groups all > > devices within the range. I think the only complication is making sure > > we're safe around device hotplug while we're doing this. Thanks, > > I think this could work. Instead of searching for other devices, check > for or allocate an iommu group on the alias dev_data, any "virtual" > aliases use that iommu group. Florian, could you test this as well? Here's a lockdep clean version of it: amd_iommu: Handle aliases not backed by devices Aliases sometimes don't have a struct pci_dev backing them. This breaks our attempt to figure out the topology and device quirks that may effect IOMMU grouping. When this happens, allocate an IOMMU group on the dev_data for the alias and make use of it for all devices referencing this alias. Signed-off-by: Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> --- diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index b64502d..4eacb17 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(iommu_pd_list_lock); /* List of all available dev_data structures */ static LIST_HEAD(dev_data_list); static DEFINE_SPINLOCK(dev_data_list_lock); +static DEFINE_MUTEX(dev_data_iommu_group_lock); /* * Domain for untranslated devices - only allocated @@ -128,6 +129,9 @@ static void free_dev_data(struct iommu_dev_data *dev_data) list_del(&dev_data->dev_data_list); spin_unlock_irqrestore(&dev_data_list_lock, flags); + if (dev_data->group) + iommu_group_put(dev_data->group); + kfree(dev_data); } @@ -256,6 +260,34 @@ static bool check_device(struct device *dev) return true; } +/* + * Sometimes there's no actual device for an alias. When that happens + * we allocate an iommu group on the dev_data and use it for anything + * aliasing back to this device. This makes sure that multiple devices + * aliased to a non-existent device id all get grouped together. Hold + * on to the reference for the group, it can be static rather than get + * automatically reclaimed if this device later gets removed. + */ +static int dev_data_add_iommu_group(struct iommu_dev_data *dev_data, + struct device *dev) +{ + mutex_lock(&dev_data_iommu_group_lock); + + if (!dev_data->group) { + struct iommu_group *group = iommu_group_alloc(); + if (IS_ERR(group)) { + mutex_unlock(&dev_data_iommu_group_lock); + return PTR_ERR(group); + } + + dev_data->group = group; + } + + mutex_unlock(&dev_data_iommu_group_lock); + + return iommu_group_add_device(dev_data->group, dev); +} + static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) { pci_dev_put(*from); @@ -264,38 +296,17 @@ static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) -static int iommu_init_device(struct device *dev) +/* + * Given a pci device, look at device quirks and topology between it + * and the IOMMU to determine the IOMMU group. Once we've found or + * created an IOMMU group, add the provided device to it. + */ +static int pdev_add_iommu_group(struct pci_dev *pdev, struct device *dev) { - struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); - struct iommu_dev_data *dev_data; + struct pci_dev *dma_pdev = pdev; struct iommu_group *group; - u16 alias; int ret; - if (dev->archdata.iommu) - return 0; - - dev_data = find_dev_data(get_device_id(dev)); - if (!dev_data) - return -ENOMEM; - - alias = amd_iommu_alias_table[dev_data->devid]; - if (alias != dev_data->devid) { - struct iommu_dev_data *alias_data; - - alias_data = find_dev_data(alias); - if (alias_data == NULL) { - pr_err("AMD-Vi: Warning: Unhandled device %s\n", - dev_name(dev)); - free_dev_data(dev_data); - return -ENOTSUPP; - } - dev_data->alias_data = alias_data; - - dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); - } else - dma_pdev = pci_dev_get(pdev); - /* Account for quirked devices */ swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); @@ -344,8 +355,61 @@ root_bus: iommu_group_put(group); - if (ret) - return ret; + return ret; +} + +static int iommu_init_device(struct device *dev) +{ + struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); + struct iommu_dev_data *dev_data; + u16 alias; + int ret; + + if (dev->archdata.iommu) + return 0; + + dev_data = find_dev_data(get_device_id(dev)); + if (!dev_data) + return -ENOMEM; + + alias = amd_iommu_alias_table[dev_data->devid]; + if (alias != dev_data->devid) { + struct iommu_dev_data *alias_data; + + alias_data = find_dev_data(alias); + if (alias_data == NULL) { + pr_err("AMD-Vi: Warning: Unhandled device %s\n", + dev_name(dev)); + free_dev_data(dev_data); + return -ENOTSUPP; + } + dev_data->alias_data = alias_data; + + /* + * If the alias device exists, use it as the base dma + * device. This results in all devices aliasing to this + * one to be in the same iommu group. If it doesn't + * actually exist, store the iommu group on the alias + * dev_data and use that for all aliases. + */ + dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); + if (!dma_pdev) { + ret = dev_data_add_iommu_group(alias_data, dev); + if (ret) { + free_dev_data(dev_data); + return ret; + } + } + } else + dma_pdev = pci_dev_get(pdev); + + if (dma_pdev) { + ret = pdev_add_iommu_group(dma_pdev, dev); + if (ret) { + free_dev_data(dev_data); + return ret; + } + } if (pci_iommuv2_capable(pdev)) { struct amd_iommu *iommu; diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index d0dab86..6597d6a 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -404,6 +404,7 @@ struct iommu_dev_data { struct list_head dev_data_list; /* For global dev_data_list */ struct iommu_dev_data *alias_data;/* The alias dev_data */ struct protection_domain *domain; /* Domain the device is bound to */ + struct iommu_group *group; /* IOMMU group for virtual aliases */ atomic_t bind; /* Domain attach reverent count */ u16 devid; /* PCI Device ID */ bool iommu_v2; /* Device can make use of IOMMUv2 */ ^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-27 16:22 ` Florian Dazinger 0 siblings, 0 replies; 37+ messages in thread From: Florian Dazinger @ 2012-09-27 16:22 UTC (permalink / raw) To: Alex Williamson; +Cc: Roedel, Joerg, iommu, linux-kernel Am Wed, 26 Sep 2012 16:04:03 -0600 schrieb Alex Williamson <alex.williamson@redhat.com>: > On Wed, 2012-09-26 at 13:50 -0600, Alex Williamson wrote: > > On Wed, 2012-09-26 at 10:21 -0600, Alex Williamson wrote: > > > On Wed, 2012-09-26 at 17:10 +0200, Roedel, Joerg wrote: > > > > On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > > > > > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > > > > > alias interface to iommu groups. Seems like this could just be an extra > > > > > parameter to iommu_group_get and iommu_group_add_device (empty in the > > > > > typical case). Then we have the problem of what's the type for an > > > > > alias? For AMI-Vi, it's a u16, but we need to be more generic than > > > > > that. Maybe iommu groups should just treat it as a void* so iommus can > > > > > use a pointer to some structure or a fixed value like a u16 bus:slot. > > > > > Thoughts? > > > > > > > > Good question. The iommu-groups are part of the IOMMU-API, with an > > > > interface to the IOMMU drivers and one to the users of IOMMU-API. So the > > > > alias handling itself should be a function of the interface to the IOMMU > > > > driver. In general the interface should not be bus specific. > > > > > > > > So a void pointer seems the only logical choice then. But I would not > > > > limit its scope to alias handling. How about making it a bus-private > > > > pointer where IOMMU driver store bus-specific information. That way we > > > > make sure that there is one struct per bus-type for this pointer, and > > > > not one structure per IOMMU driver. > > > > > > I thought of another approach that may actually be more 3.6 worthy. > > > What if we just make the iommu driver handle it? For instance, > > > amd_iommu can walk the alias table looking for entries that use the same > > > alias and get the device via pci_get_bus_and_slot. If it finds a device > > > with an iommu group, it attaches the new device to the same group, > > > hiding anything about aliases from the group layer. It just groups all > > > devices within the range. I think the only complication is making sure > > > we're safe around device hotplug while we're doing this. Thanks, > > > > I think this could work. Instead of searching for other devices, check > > for or allocate an iommu group on the alias dev_data, any "virtual" > > aliases use that iommu group. Florian, could you test this as well? > > Here's a lockdep clean version of it: > > amd_iommu: Handle aliases not backed by devices > [ skipped patch ] yes, this patch is working for me, too. I also tested your second patch, it was working as well. thanks, Florian ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-27 16:22 ` Florian Dazinger 0 siblings, 0 replies; 37+ messages in thread From: Florian Dazinger @ 2012-09-27 16:22 UTC (permalink / raw) To: Alex Williamson; +Cc: iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA Am Wed, 26 Sep 2012 16:04:03 -0600 schrieb Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>: > On Wed, 2012-09-26 at 13:50 -0600, Alex Williamson wrote: > > On Wed, 2012-09-26 at 10:21 -0600, Alex Williamson wrote: > > > On Wed, 2012-09-26 at 17:10 +0200, Roedel, Joerg wrote: > > > > On Wed, Sep 26, 2012 at 08:35:59AM -0600, Alex Williamson wrote: > > > > > Hmm, that throws a kink in iommu groups. So perhaps we need to make an > > > > > alias interface to iommu groups. Seems like this could just be an extra > > > > > parameter to iommu_group_get and iommu_group_add_device (empty in the > > > > > typical case). Then we have the problem of what's the type for an > > > > > alias? For AMI-Vi, it's a u16, but we need to be more generic than > > > > > that. Maybe iommu groups should just treat it as a void* so iommus can > > > > > use a pointer to some structure or a fixed value like a u16 bus:slot. > > > > > Thoughts? > > > > > > > > Good question. The iommu-groups are part of the IOMMU-API, with an > > > > interface to the IOMMU drivers and one to the users of IOMMU-API. So the > > > > alias handling itself should be a function of the interface to the IOMMU > > > > driver. In general the interface should not be bus specific. > > > > > > > > So a void pointer seems the only logical choice then. But I would not > > > > limit its scope to alias handling. How about making it a bus-private > > > > pointer where IOMMU driver store bus-specific information. That way we > > > > make sure that there is one struct per bus-type for this pointer, and > > > > not one structure per IOMMU driver. > > > > > > I thought of another approach that may actually be more 3.6 worthy. > > > What if we just make the iommu driver handle it? For instance, > > > amd_iommu can walk the alias table looking for entries that use the same > > > alias and get the device via pci_get_bus_and_slot. If it finds a device > > > with an iommu group, it attaches the new device to the same group, > > > hiding anything about aliases from the group layer. It just groups all > > > devices within the range. I think the only complication is making sure > > > we're safe around device hotplug while we're doing this. Thanks, > > > > I think this could work. Instead of searching for other devices, check > > for or allocate an iommu group on the alias dev_data, any "virtual" > > aliases use that iommu group. Florian, could you test this as well? > > Here's a lockdep clean version of it: > > amd_iommu: Handle aliases not backed by devices > [ skipped patch ] yes, this patch is working for me, too. I also tested your second patch, it was working as well. thanks, Florian ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-28 13:58 ` Roedel, Joerg 0 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-28 13:58 UTC (permalink / raw) To: Alex Williamson; +Cc: Florian Dazinger, iommu, linux-kernel On Wed, Sep 26, 2012 at 04:04:03PM -0600, Alex Williamson wrote: > Here's a lockdep clean version of it: > > amd_iommu: Handle aliases not backed by devices > > Aliases sometimes don't have a struct pci_dev backing them. This breaks > our attempt to figure out the topology and device quirks that may effect > IOMMU grouping. When this happens, allocate an IOMMU group on the > dev_data for the alias and make use of it for all devices referencing > this alias. Yes, this is the real fix. But it is too big for v3.6 at this time, so I'll would take this for 3.7 and use my small fix for 3.6. > Signed-off-by: Alex Williamson <alex.williamson@redhat.com> > --- > > diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c > index b64502d..4eacb17 100644 > --- a/drivers/iommu/amd_iommu.c > +++ b/drivers/iommu/amd_iommu.c > @@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(iommu_pd_list_lock); > /* List of all available dev_data structures */ > static LIST_HEAD(dev_data_list); > static DEFINE_SPINLOCK(dev_data_list_lock); > +static DEFINE_MUTEX(dev_data_iommu_group_lock); I think this lock is not necessary. The iommu_init_device routine does not run multiple times in parallel for the same device. So we should be safe on that side. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: 3.6-rc7 boot crash + bisection @ 2012-09-28 13:58 ` Roedel, Joerg 0 siblings, 0 replies; 37+ messages in thread From: Roedel, Joerg @ 2012-09-28 13:58 UTC (permalink / raw) To: Alex Williamson Cc: Florian Dazinger, iommu, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Wed, Sep 26, 2012 at 04:04:03PM -0600, Alex Williamson wrote: > Here's a lockdep clean version of it: > > amd_iommu: Handle aliases not backed by devices > > Aliases sometimes don't have a struct pci_dev backing them. This breaks > our attempt to figure out the topology and device quirks that may effect > IOMMU grouping. When this happens, allocate an IOMMU group on the > dev_data for the alias and make use of it for all devices referencing > this alias. Yes, this is the real fix. But it is too big for v3.6 at this time, so I'll would take this for 3.7 and use my small fix for 3.6. > Signed-off-by: Alex Williamson <alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> > --- > > diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c > index b64502d..4eacb17 100644 > --- a/drivers/iommu/amd_iommu.c > +++ b/drivers/iommu/amd_iommu.c > @@ -71,6 +71,7 @@ static DEFINE_SPINLOCK(iommu_pd_list_lock); > /* List of all available dev_data structures */ > static LIST_HEAD(dev_data_list); > static DEFINE_SPINLOCK(dev_data_list_lock); > +static DEFINE_MUTEX(dev_data_iommu_group_lock); I think this lock is not necessary. The iommu_init_device routine does not run multiple times in parallel for the same device. So we should be safe on that side. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 ^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2012-09-28 13:58 UTC | newest] Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-09-24 19:03 3.6-rc7 boot crash + bisection Florian Dazinger 2012-09-25 18:32 ` Alex Williamson 2012-09-25 18:42 ` Alex Williamson 2012-09-25 18:54 ` Florian Dazinger 2012-09-25 19:43 ` Alex Williamson 2012-09-25 19:43 ` Alex Williamson 2012-09-25 23:01 ` Florian Dazinger 2012-09-26 3:12 ` Alex Williamson 2012-09-26 3:12 ` Alex Williamson 2012-09-26 14:43 ` Roedel, Joerg 2012-09-26 14:43 ` Roedel, Joerg 2012-09-26 14:52 ` Alex Williamson 2012-09-26 14:52 ` Alex Williamson 2012-09-26 15:04 ` Roedel, Joerg 2012-09-26 15:04 ` Roedel, Joerg 2012-09-26 16:13 ` Alex Williamson 2012-09-26 16:13 ` Alex Williamson 2012-09-26 16:43 ` Florian Dazinger 2012-09-26 16:43 ` Florian Dazinger 2012-09-26 17:47 ` Florian Dazinger 2012-09-26 17:47 ` Florian Dazinger 2012-09-26 13:20 ` Roedel, Joerg 2012-09-26 13:20 ` Roedel, Joerg 2012-09-26 14:35 ` Alex Williamson 2012-09-26 14:35 ` Alex Williamson 2012-09-26 15:10 ` Roedel, Joerg 2012-09-26 15:10 ` Roedel, Joerg 2012-09-26 16:21 ` Alex Williamson 2012-09-26 16:21 ` Alex Williamson 2012-09-26 19:50 ` Alex Williamson 2012-09-26 19:50 ` Alex Williamson 2012-09-26 22:04 ` Alex Williamson 2012-09-26 22:04 ` Alex Williamson 2012-09-27 16:22 ` Florian Dazinger 2012-09-27 16:22 ` Florian Dazinger 2012-09-28 13:58 ` Roedel, Joerg 2012-09-28 13:58 ` Roedel, Joerg
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