* [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-29 21:27 ` Gabriel Huau
2012-04-29 23:29 ` Marek Vasut
2012-04-29 21:27 ` [U-Boot] [PATCH 2/2 v5] Add support for MINI2440 (s3c2440) Gabriel Huau
` (12 subsequent siblings)
13 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-29 21:27 UTC (permalink / raw)
To: u-boot
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
arch/arm/include/asm/arch-s3c24x0/gpio.h | 183 +++++++++++++++++++++++++++
arch/arm/include/asm/arch-s3c24x0/iomux.h | 197 +++++++++++++++++++++++++++++
drivers/gpio/Makefile | 1 +
drivers/gpio/s3c2440_gpio.c | 74 +++++++++++
4 files changed, 455 insertions(+)
create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
create mode 100644 drivers/gpio/s3c2440_gpio.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 0000000..e7fbefe
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2012, Gabriel Huau. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+
+/* 0x4 means that we can DAT and not CON register */
+#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
+#define GPIO_BIT(x) ((x) & 0x3f)
+
+/*
+ * It's how we calculate the full port address
+ * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
+ * We move it at the second digit, and finally we add 0x4 because we want
+ * to modify GPIO DAT and not CON
+ */
+#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) << 1))
+
+typedef enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+} s3c2240_gpio;
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 0000000..2201cd3
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2012, Gabriel Huau. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_IOMUX_H_
+#define _S3C24X0_IOMUX_H_
+
+typedef enum s3c2440_iomux_func {
+ /* PORT A */
+ IOMUXA_ADDR0 = 1,
+ IOMUXA_ADDR16 = (1 << 1),
+ IOMUXA_ADDR17 = (1 << 2),
+ IOMUXA_ADDR18 = (1 << 3),
+ IOMUXA_ADDR19 = (1 << 4),
+ IOMUXA_ADDR20 = (1 << 5),
+ IOMUXA_ADDR21 = (1 << 6),
+ IOMUXA_ADDR22 = (1 << 7),
+ IOMUXA_ADDR23 = (1 << 8),
+ IOMUXA_ADDR24 = (1 << 9),
+ IOMUXA_ADDR25 = (1 << 10),
+ IOMUXA_ADDR26 = (1 << 11),
+ IOMUXA_nGCS1 = (1 << 12),
+ IOMUXA_nGCS2 = (1 << 13),
+ IOMUXA_nGCS3 = (1 << 14),
+ IOMUXA_nGCS4 = (1 << 15),
+ IOMUXA_nGCS5 = (1 << 16),
+ IOMUXA_CLE = (1 << 17),
+ IOMUXA_ALE = (1 << 18),
+ IOMUXA_nFWE = (1 << 19),
+ IOMUXA_nFRE = (1 << 20),
+ IOMUXA_nRSTOUT = (1 << 21),
+ IOMUXA_nFCE = (1 << 22),
+
+ /* PORT B */
+ IOMUXB_nXDREQ0 = (2 << 20),
+ IOMUXB_nXDACK0 = (2 << 18),
+ IOMUXB_nXDREQ1 = (2 << 16),
+ IOMUXB_nXDACK1 = (2 << 14),
+ IOMUXB_nXBREQ = (2 << 12),
+ IOMUXB_nXBACK = (2 << 10),
+ IOMUXB_TCLK0 = (2 << 8),
+ IOMUXB_TOUT3 = (2 << 6),
+ IOMUXB_TOUT2 = (2 << 4),
+ IOMUXB_TOUT1 = (2 << 2),
+ IOMUXB_TOUT0 = 2,
+
+ /* PORT C */
+ IOMUXC_VS7 = (2 << 30),
+ IOMUXC_VS6 = (2 << 28),
+ IOMUXC_VS5 = (2 << 26),
+ IOMUXC_VS4 = (2 << 24),
+ IOMUXC_VS3 = (2 << 22),
+ IOMUXC_VS2 = (2 << 20),
+ IOMUXC_VS1 = (2 << 18),
+ IOMUXC_VS0 = (2 << 16),
+ IOMUXC_LCD_LPCREVB = (2 << 14),
+ IOMUXC_LCD_LPCREV = (2 << 12),
+ IOMUXC_LCD_LPCOE = (2 << 10),
+ IOMUXC_VM = (2 << 8),
+ IOMUXC_VFRAME = (2 << 6),
+ IOMUXC_VLINE = (2 << 4),
+ IOMUXC_VCLK = (2 << 2),
+ IOMUXC_LEND = 2,
+ IOMUXC_I2SSDI = (3 << 8),
+
+ /* PORT D */
+ IOMUXD_VS23 = (2 << 30),
+ IOMUXD_VS22 = (2 << 28),
+ IOMUXD_VS21 = (2 << 26),
+ IOMUXD_VS20 = (2 << 24),
+ IOMUXD_VS19 = (2 << 22),
+ IOMUXD_VS18 = (2 << 20),
+ IOMUXD_VS17 = (2 << 18),
+ IOMUXD_VS16 = (2 << 16),
+ IOMUXD_VS15 = (2 << 14),
+ IOMUXD_VS14 = (2 << 12),
+ IOMUXD_VS13 = (2 << 10),
+ IOMUXD_VS12 = (2 << 8),
+ IOMUXD_VS11 = (2 << 6),
+ IOMUXD_VS10 = (2 << 4),
+ IOMUXD_VS9 = (2 << 2),
+ IOMUXD_VS8 = 2,
+ IOMUXD_nSS0 = (3 << 30),
+ IOMUXD_nSS1 = (3 << 28),
+ IOMUXD_SPICLK1 = (3 << 20),
+ IOMUXD_SPIMOSI1 = (3 << 18),
+ IOMUXD_SPIMISO1 = (3 << 16),
+
+ /* PORT E */
+ IOMUXE_IICSDA = (2 << 30),
+ IOMUXE_IICSCL = (2 << 28),
+ IOMUXE_SPICLK0 = (2 << 26),
+ IOMUXE_SPIMOSI0 = (2 << 24),
+ IOMUXE_SPIMISO0 = (2 << 22),
+ IOMUXE_SDDAT3 = (2 << 20),
+ IOMUXE_SDDAT2 = (2 << 18),
+ IOMUXE_SDDAT1 = (2 << 16),
+ IOMUXE_SDDAT0 = (2 << 14),
+ IOMUXE_SDCMD = (2 << 12),
+ IOMUXE_SDCLK = (2 << 10),
+ IOMUXE_I2SDO = (2 << 8),
+ IOMUXE_I2SDI = (2 << 6),
+ IOMUXE_CDCLK = (2 << 4),
+ IOMUXE_I2SSCLK = (2 << 2),
+ IOMUXE_I2SLRCK = 2,
+ IOMUXE_AC_SDATA_OUT = (3 << 8),
+ IOMUXE_AC_SDATA_IN = (3 << 6),
+ IOMUXE_AC_nRESET = (3 << 4),
+ IOMUXE_AC_BIT_CLK = (3 << 2),
+ IOMUXE_AC_SYNC = 3,
+
+ /* PORT F */
+ IOMUXF_EINT7 = (2 << 14),
+ IOMUXF_EINT6 = (2 << 12),
+ IOMUXF_EINT5 = (2 << 10),
+ IOMUXF_EINT4 = (2 << 8),
+ IOMUXF_EINT3 = (2 << 6),
+ IOMUXF_EINT2 = (2 << 4),
+ IOMUXF_EINT1 = (2 << 2),
+ IOMUXF_EINT0 = 2,
+
+ /* PORT G */
+ IOMUXG_EINT23 = (2 << 30),
+ IOMUXG_EINT22 = (2 << 28),
+ IOMUXG_EINT21 = (2 << 26),
+ IOMUXG_EINT20 = (2 << 24),
+ IOMUXG_EINT19 = (2 << 22),
+ IOMUXG_EINT18 = (2 << 20),
+ IOMUXG_EINT17 = (2 << 18),
+ IOMUXG_EINT16 = (2 << 16),
+ IOMUXG_EINT15 = (2 << 14),
+ IOMUXG_EINT14 = (2 << 12),
+ IOMUXG_EINT13 = (2 << 10),
+ IOMUXG_EINT12 = (2 << 8),
+ IOMUXG_EINT11 = (2 << 6),
+ IOMUXG_EINT10 = (2 << 4),
+ IOMUXG_EINT9 = (2 << 2),
+ IOMUXG_EINT8 = 2,
+ IOMUXG_TCLK1 = (3 << 22),
+ IOMUXG_nCTS1 = (3 << 20),
+ IOMUXG_nRTS1 = (3 << 18),
+ IOMUXG_SPICLK1 = (3 << 14),
+ IOMUXG_SPIMOSI1 = (3 << 12),
+ IOMUXG_SPIMISO1 = (3 << 10),
+ IOMUXG_LCD_PWRDN = (3 << 8),
+ IOMUXG_nSS1 = (3 << 6),
+ IOMUXG_nSS0 = (3 << 4),
+
+ /* PORT H */
+ IOMUXH_CLKOUT1 = (2 << 20),
+ IOMUXH_CLKOUT0 = (2 << 18),
+ IOMUXH_UEXTCLK = (2 << 16),
+ IOMUXH_RXD2 = (2 << 14),
+ IOMUXH_TXD2 = (2 << 12),
+ IOMUXH_RXD1 = (2 << 10),
+ IOMUXH_TXD1 = (2 << 8),
+ IOMUXH_RXD0 = (2 << 6),
+ IOMUXH_TXD0 = (2 << 4),
+ IOMUXH_nRTS0 = (2 << 2),
+ IOMUXH_nCTS0 = 2,
+ IOMUXH_nCTS1 = (3 << 14),
+ IOMUXH_nRTS1 = (3 << 12),
+
+ /* PORT J */
+ IOMUXJ_CAMRESET = (2 << 24),
+ IOMUXJ_CAMCLKOUT = (2 << 22),
+ IOMUXJ_CAMHREF = (2 << 20),
+ IOMUXJ_CAMVSYNC = (2 << 18),
+ IOMUXJ_CAMPCLK = (2 << 16),
+ IOMUXJ_CAMDATA7 = (2 << 14),
+ IOMUXJ_CAMDATA6 = (2 << 12),
+ IOMUXJ_CAMDATA5 = (2 << 10),
+ IOMUXJ_CAMDATA4 = (2 << 8),
+ IOMUXJ_CAMDATA3 = (2 << 6),
+ IOMUXJ_CAMDATA2 = (2 << 4),
+ IOMUXJ_CAMDATA1 = (2 << 2),
+ IOMUXJ_CAMDATA0 = 2
+} s3c2440_gpio_func;
+
+#endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb3b09a..7ae6f84 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
+COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
new file mode 100644
index 0000000..adfa812
--- /dev/null
+++ b/drivers/gpio/s3c2440_gpio.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+ unsigned port = GPIO_FULLPORT(gpio);
+
+ if(value)
+ if(!GPIO_PORT(gpio))
+ l |= (0x1 << GPIO_BIT(gpio));
+ else
+ l |= (0x3 << GPIO_BIT(gpio));
+ else
+ if(!GPIO_PORT(gpio))
+ l &= ~(0x1 << GPIO_BIT(gpio));
+ else
+ l &= ~(0x3 << GPIO_BIT(gpio));
+ return writel(port, l);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+
+ if(GPIO_PORT(gpio) == 0) /* PORT A */
+ return (l >> GPIO_BIT(gpio)) & 0x1;
+ return (l >> GPIO_BIT(gpio)) & 0x3;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
+ return gpio_set_value(gpio, value);
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-29 21:27 ` [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-04-29 23:29 ` Marek Vasut
2012-04-30 11:05 ` Gabriel Huau
0 siblings, 1 reply; 50+ messages in thread
From: Marek Vasut @ 2012-04-29 23:29 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
Commit message got lost ? :p
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> arch/arm/include/asm/arch-s3c24x0/gpio.h | 183
> +++++++++++++++++++++++++++ arch/arm/include/asm/arch-s3c24x0/iomux.h |
> 197 +++++++++++++++++++++++++++++ drivers/gpio/Makefile
> | 1 +
> drivers/gpio/s3c2440_gpio.c | 74 +++++++++++
> 4 files changed, 455 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
> create mode 100644 drivers/gpio/s3c2440_gpio.c
>
> diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h
> b/arch/arm/include/asm/arch-s3c24x0/gpio.h new file mode 100644
> index 0000000..e7fbefe
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
> @@ -0,0 +1,183 @@
> +/*
> + * Copyright (c) 2012, Gabriel Huau. All rights reserved.
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_GPIO_H_
> +#define _S3C24X0_GPIO_H_
> +
> +#define GPIO_INPUT 0x0
> +#define GPIO_OUTPUT 0x1
> +
> +/* 0x4 means that we can DAT and not CON register */
> +#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
> +#define GPIO_BIT(x) ((x) & 0x3f)
Move this to driver?
> +
> +/*
> + * It's how we calculate the full port address
> + * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
> + * We move it at the second digit, and finally we add 0x4 because we want
> + * to modify GPIO DAT and not CON
> + */
> +#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) <<
> 1)) +
> +typedef enum s3c2440_gpio {
> + GPA0,
> + GPA1,
> + GPA2,
> + GPA3,
> + GPA4,
> + GPA5,
> + GPA6,
> + GPA7,
> + GPA8,
> + GPA9,
> + GPA10,
> + GPA11,
> + GPA12,
> + GPA13,
> + GPA14,
> + GPA15,
> + GPA16,
> + GPA17,
> + GPA18,
> + GPA19,
> + GPA20,
> + GPA21,
> + GPA22,
> + GPA23,
> + GPA24,
> +
> + GPB0 = 32,
> + GPB1,
> + GPB2,
> + GPB3,
> + GPB4,
> + GPB5,
> + GPB6,
> + GPB7,
> + GPB8,
> + GPB9,
> + GPB10,
> +
> + GPC0 = 64,
> + GPC1,
> + GPC2,
> + GPC3,
> + GPC4,
> + GPC5,
> + GPC6,
> + GPC7,
> + GPC8,
> + GPC9,
> + GPC10,
> + GPC11,
> + GPC12,
> + GPC13,
> + GPC14,
> + GPC15,
> +
> + GPD0 = 96,
> + GPD1,
> + GPD2,
> + GPD3,
> + GPD4,
> + GPD5,
> + GPD6,
> + GPD7,
> + GPD8,
> + GPD9,
> + GPD10,
> + GPD11,
> + GPD12,
> + GPD13,
> + GPD14,
> + GPD15,
> +
> + GPE0 = 128,
> + GPE1,
> + GPE2,
> + GPE3,
> + GPE4,
> + GPE5,
> + GPE6,
> + GPE7,
> + GPE8,
> + GPE9,
> + GPE10,
> + GPE11,
> + GPE12,
> + GPE13,
> + GPE14,
> + GPE15,
> +
> + GPF0 = 160,
> + GPF1,
> + GPF2,
> + GPF3,
> + GPF4,
> + GPF5,
> + GPF6,
> + GPF7,
> +
> + GPG0 = 192,
> + GPG1,
> + GPG2,
> + GPG3,
> + GPG4,
> + GPG5,
> + GPG6,
> + GPG7,
> + GPG8,
> + GPG9,
> + GPG10,
> + GPG11,
> + GPG12,
> + GPG13,
> + GPG14,
> + GPG15,
> +
> + GPH0 = 224,
> + GPH1,
> + GPH2,
> + GPH3,
> + GPH4,
> + GPH5,
> + GPH6,
> + GPH7,
> + GPH8,
> + GPH9,
> + GPH10,
> +
> + GPJ0 = 256,
> + GPJ1,
> + GPJ2,
> + GPJ3,
> + GPJ4,
> + GPJ5,
> + GPJ6,
> + GPJ7,
> + GPJ8,
> + GPJ9,
> + GPJ10,
> + GPJ11,
> + GPJ12,
> +} s3c2240_gpio;
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h
> b/arch/arm/include/asm/arch-s3c24x0/iomux.h new file mode 100644
> index 0000000..2201cd3
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
> @@ -0,0 +1,197 @@
> +/*
> + * Copyright (c) 2012, Gabriel Huau. All rights reserved.
Add your email address so I know where to send blackmail if this gets broken ;-)
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_IOMUX_H_
> +#define _S3C24X0_IOMUX_H_
> +
> +typedef enum s3c2440_iomux_func {
No typedefs please.
> + /* PORT A */
> + IOMUXA_ADDR0 = 1,
> + IOMUXA_ADDR16 = (1 << 1),
> + IOMUXA_ADDR17 = (1 << 2),
> + IOMUXA_ADDR18 = (1 << 3),
> + IOMUXA_ADDR19 = (1 << 4),
> + IOMUXA_ADDR20 = (1 << 5),
> + IOMUXA_ADDR21 = (1 << 6),
> + IOMUXA_ADDR22 = (1 << 7),
> + IOMUXA_ADDR23 = (1 << 8),
> + IOMUXA_ADDR24 = (1 << 9),
> + IOMUXA_ADDR25 = (1 << 10),
> + IOMUXA_ADDR26 = (1 << 11),
> + IOMUXA_nGCS1 = (1 << 12),
> + IOMUXA_nGCS2 = (1 << 13),
> + IOMUXA_nGCS3 = (1 << 14),
> + IOMUXA_nGCS4 = (1 << 15),
> + IOMUXA_nGCS5 = (1 << 16),
> + IOMUXA_CLE = (1 << 17),
> + IOMUXA_ALE = (1 << 18),
> + IOMUXA_nFWE = (1 << 19),
> + IOMUXA_nFRE = (1 << 20),
> + IOMUXA_nRSTOUT = (1 << 21),
> + IOMUXA_nFCE = (1 << 22),
> +
> + /* PORT B */
> + IOMUXB_nXDREQ0 = (2 << 20),
> + IOMUXB_nXDACK0 = (2 << 18),
> + IOMUXB_nXDREQ1 = (2 << 16),
> + IOMUXB_nXDACK1 = (2 << 14),
> + IOMUXB_nXBREQ = (2 << 12),
> + IOMUXB_nXBACK = (2 << 10),
> + IOMUXB_TCLK0 = (2 << 8),
> + IOMUXB_TOUT3 = (2 << 6),
> + IOMUXB_TOUT2 = (2 << 4),
> + IOMUXB_TOUT1 = (2 << 2),
> + IOMUXB_TOUT0 = 2,
> +
> + /* PORT C */
> + IOMUXC_VS7 = (2 << 30),
> + IOMUXC_VS6 = (2 << 28),
> + IOMUXC_VS5 = (2 << 26),
> + IOMUXC_VS4 = (2 << 24),
> + IOMUXC_VS3 = (2 << 22),
> + IOMUXC_VS2 = (2 << 20),
> + IOMUXC_VS1 = (2 << 18),
> + IOMUXC_VS0 = (2 << 16),
> + IOMUXC_LCD_LPCREVB = (2 << 14),
> + IOMUXC_LCD_LPCREV = (2 << 12),
> + IOMUXC_LCD_LPCOE = (2 << 10),
> + IOMUXC_VM = (2 << 8),
> + IOMUXC_VFRAME = (2 << 6),
> + IOMUXC_VLINE = (2 << 4),
> + IOMUXC_VCLK = (2 << 2),
> + IOMUXC_LEND = 2,
> + IOMUXC_I2SSDI = (3 << 8),
> +
> + /* PORT D */
> + IOMUXD_VS23 = (2 << 30),
> + IOMUXD_VS22 = (2 << 28),
> + IOMUXD_VS21 = (2 << 26),
> + IOMUXD_VS20 = (2 << 24),
> + IOMUXD_VS19 = (2 << 22),
> + IOMUXD_VS18 = (2 << 20),
> + IOMUXD_VS17 = (2 << 18),
> + IOMUXD_VS16 = (2 << 16),
> + IOMUXD_VS15 = (2 << 14),
> + IOMUXD_VS14 = (2 << 12),
> + IOMUXD_VS13 = (2 << 10),
> + IOMUXD_VS12 = (2 << 8),
> + IOMUXD_VS11 = (2 << 6),
> + IOMUXD_VS10 = (2 << 4),
> + IOMUXD_VS9 = (2 << 2),
> + IOMUXD_VS8 = 2,
> + IOMUXD_nSS0 = (3 << 30),
> + IOMUXD_nSS1 = (3 << 28),
The formatting here is shitty, use tabs ;-)
> + IOMUXD_SPICLK1 = (3 << 20),
> + IOMUXD_SPIMOSI1 = (3 << 18),
> + IOMUXD_SPIMISO1 = (3 << 16),
> +
> + /* PORT E */
> + IOMUXE_IICSDA = (2 << 30),
> + IOMUXE_IICSCL = (2 << 28),
> + IOMUXE_SPICLK0 = (2 << 26),
> + IOMUXE_SPIMOSI0 = (2 << 24),
> + IOMUXE_SPIMISO0 = (2 << 22),
> + IOMUXE_SDDAT3 = (2 << 20),
> + IOMUXE_SDDAT2 = (2 << 18),
> + IOMUXE_SDDAT1 = (2 << 16),
> + IOMUXE_SDDAT0 = (2 << 14),
> + IOMUXE_SDCMD = (2 << 12),
> + IOMUXE_SDCLK = (2 << 10),
> + IOMUXE_I2SDO = (2 << 8),
> + IOMUXE_I2SDI = (2 << 6),
> + IOMUXE_CDCLK = (2 << 4),
> + IOMUXE_I2SSCLK = (2 << 2),
> + IOMUXE_I2SLRCK = 2,
> + IOMUXE_AC_SDATA_OUT = (3 << 8),
> + IOMUXE_AC_SDATA_IN = (3 << 6),
> + IOMUXE_AC_nRESET = (3 << 4),
> + IOMUXE_AC_BIT_CLK = (3 << 2),
> + IOMUXE_AC_SYNC = 3,
> +
> + /* PORT F */
> + IOMUXF_EINT7 = (2 << 14),
> + IOMUXF_EINT6 = (2 << 12),
> + IOMUXF_EINT5 = (2 << 10),
> + IOMUXF_EINT4 = (2 << 8),
> + IOMUXF_EINT3 = (2 << 6),
> + IOMUXF_EINT2 = (2 << 4),
> + IOMUXF_EINT1 = (2 << 2),
> + IOMUXF_EINT0 = 2,
> +
> + /* PORT G */
> + IOMUXG_EINT23 = (2 << 30),
> + IOMUXG_EINT22 = (2 << 28),
> + IOMUXG_EINT21 = (2 << 26),
> + IOMUXG_EINT20 = (2 << 24),
> + IOMUXG_EINT19 = (2 << 22),
> + IOMUXG_EINT18 = (2 << 20),
> + IOMUXG_EINT17 = (2 << 18),
> + IOMUXG_EINT16 = (2 << 16),
> + IOMUXG_EINT15 = (2 << 14),
> + IOMUXG_EINT14 = (2 << 12),
> + IOMUXG_EINT13 = (2 << 10),
> + IOMUXG_EINT12 = (2 << 8),
> + IOMUXG_EINT11 = (2 << 6),
> + IOMUXG_EINT10 = (2 << 4),
> + IOMUXG_EINT9 = (2 << 2),
> + IOMUXG_EINT8 = 2,
> + IOMUXG_TCLK1 = (3 << 22),
> + IOMUXG_nCTS1 = (3 << 20),
> + IOMUXG_nRTS1 = (3 << 18),
> + IOMUXG_SPICLK1 = (3 << 14),
> + IOMUXG_SPIMOSI1 = (3 << 12),
> + IOMUXG_SPIMISO1 = (3 << 10),
> + IOMUXG_LCD_PWRDN = (3 << 8),
> + IOMUXG_nSS1 = (3 << 6),
> + IOMUXG_nSS0 = (3 << 4),
> +
> + /* PORT H */
> + IOMUXH_CLKOUT1 = (2 << 20),
> + IOMUXH_CLKOUT0 = (2 << 18),
> + IOMUXH_UEXTCLK = (2 << 16),
> + IOMUXH_RXD2 = (2 << 14),
> + IOMUXH_TXD2 = (2 << 12),
> + IOMUXH_RXD1 = (2 << 10),
> + IOMUXH_TXD1 = (2 << 8),
> + IOMUXH_RXD0 = (2 << 6),
> + IOMUXH_TXD0 = (2 << 4),
> + IOMUXH_nRTS0 = (2 << 2),
> + IOMUXH_nCTS0 = 2,
> + IOMUXH_nCTS1 = (3 << 14),
> + IOMUXH_nRTS1 = (3 << 12),
> +
> + /* PORT J */
> + IOMUXJ_CAMRESET = (2 << 24),
> + IOMUXJ_CAMCLKOUT = (2 << 22),
> + IOMUXJ_CAMHREF = (2 << 20),
> + IOMUXJ_CAMVSYNC = (2 << 18),
> + IOMUXJ_CAMPCLK = (2 << 16),
> + IOMUXJ_CAMDATA7 = (2 << 14),
> + IOMUXJ_CAMDATA6 = (2 << 12),
> + IOMUXJ_CAMDATA5 = (2 << 10),
> + IOMUXJ_CAMDATA4 = (2 << 8),
> + IOMUXJ_CAMDATA3 = (2 << 6),
> + IOMUXJ_CAMDATA2 = (2 << 4),
> + IOMUXJ_CAMDATA1 = (2 << 2),
> + IOMUXJ_CAMDATA0 = 2
> +} s3c2440_gpio_func;
> +
> +#endif
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index fb3b09a..7ae6f84 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
> COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
> COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
> COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
> +COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
>
> COBJS := $(COBJS-y)
> SRCS := $(COBJS:.o=.c)
> diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
> new file mode 100644
> index 0000000..adfa812
> --- /dev/null
> +++ b/drivers/gpio/s3c2440_gpio.c
> @@ -0,0 +1,74 @@
> +/*
> + * Copyright (C) 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +
> +int gpio_set_value(unsigned gpio, int value)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> + unsigned port = GPIO_FULLPORT(gpio);
> +
> + if(value)
> + if(!GPIO_PORT(gpio))
> + l |= (0x1 << GPIO_BIT(gpio));
> + else
> + l |= (0x3 << GPIO_BIT(gpio));
> + else
> + if(!GPIO_PORT(gpio))
> + l &= ~(0x1 << GPIO_BIT(gpio));
> + else
> + l &= ~(0x3 << GPIO_BIT(gpio));
Documentation/comment won't hurt.
> + return writel(port, l);
> +}
> +
> +int gpio_get_value(unsigned gpio)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> +
> + if(GPIO_PORT(gpio) == 0) /* PORT A */
> + return (l >> GPIO_BIT(gpio)) & 0x1;
> + return (l >> GPIO_BIT(gpio)) & 0x3;
> +}
> +
> +int gpio_request(unsigned gpio, const char *label)
> +{
> + return 0;
> +}
> +
> +int gpio_free(unsigned gpio)
> +{
> + return 0;
> +}
> +
> +int gpio_direction_input(unsigned gpio)
> +{
> + return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
> +}
> +
> +int gpio_direction_output(unsigned gpio, int value)
> +{
> + writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
> + return gpio_set_value(gpio, value);
> +}
This wasn't that bad ;-)
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-29 23:29 ` Marek Vasut
@ 2012-04-30 11:05 ` Gabriel Huau
2012-04-30 12:25 ` Marek Vasut
0 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 11:05 UTC (permalink / raw)
To: u-boot
On Mon, Apr 30, 2012 at 01:29:37AM +0200, Marek Vasut wrote:
> Dear Gabriel Huau,
>
> Commit message got lost ? :p
It's strange, I have the commit message in my log, but when I
format-patch, The commit message is set only in the subject, not
in the body.
Any idea ?
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-30 11:05 ` Gabriel Huau
@ 2012-04-30 12:25 ` Marek Vasut
2012-04-30 13:18 ` Gabriel Huau
0 siblings, 1 reply; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 12:25 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> On Mon, Apr 30, 2012 at 01:29:37AM +0200, Marek Vasut wrote:
> > Dear Gabriel Huau,
> >
> > Commit message got lost ? :p
>
> It's strange, I have the commit message in my log, but when I
> format-patch, The commit message is set only in the subject, not
> in the body.
Are you sure you sent the correct patch ? ;-)
>
> Any idea ?
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-30 12:25 ` Marek Vasut
@ 2012-04-30 13:18 ` Gabriel Huau
0 siblings, 0 replies; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 13:18 UTC (permalink / raw)
To: u-boot
On Mon, Apr 30, 2012 at 02:25:20PM +0200, Marek Vasut wrote:
> Dear Gabriel Huau,
>
> > On Mon, Apr 30, 2012 at 01:29:37AM +0200, Marek Vasut wrote:
> > > Dear Gabriel Huau,
> > >
> > > Commit message got lost ? :p
> >
> > It's strange, I have the commit message in my log, but when I
> > format-patch, The commit message is set only in the subject, not
> > in the body.
>
> Are you sure you sent the correct patch ? ;-)
Yeap, I just did some tests, it seems that the commit message in the
body text is only from line 2. The line 1 is in the subject :)
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 2/2 v5] Add support for MINI2440 (s3c2440).
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
2012-04-29 21:27 ` [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-04-29 21:27 ` Gabriel Huau
2012-04-29 23:32 ` Marek Vasut
2012-04-29 21:32 ` [U-Boot] [PATCH 0/2] " Wolfgang Denk
` (11 subsequent siblings)
13 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-29 21:27 UTC (permalink / raw)
To: u-boot
---
Changes for v2:
- Coding style cleanup
- Remove unnecessary files modification
- Remove unnecessary board configuration set
Changes for v3:
- Coding style cleanup
- Move some macro definition from lowlevel_init.S
to a new header
- Remove some "magic bloat" with I/O board initialization
- Add a pll_delay and replace loop by it
- Somme cleanup in the configuration file
- Cancel modifications on an SoC specific header
- Add my name to copyright
Changes for v4:
- Move dram init to dram_init() instead low_levelinit
- Remove u-boot env from configuration file and change
the address of initial SP
- Remove PLL init, now it's SoC specific
Changes fr v5:
- Clean up configuration file
- Add a MAINTAINERS entry
- Add a README.mini2440 file
- Use gpio/iomux interface in case of magic numbers
- Use get_ram_size()
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
MAINTAINERS | 4 +
board/friendlyarm/mini2440/Makefile | 44 +++++++
board/friendlyarm/mini2440/mini2440.c | 135 +++++++++++++++++++++
board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++
boards.cfg | 1 +
doc/README.mini2440 | 28 +++++
include/configs/mini2440.h | 209 +++++++++++++++++++++++++++++++++
7 files changed, 565 insertions(+)
create mode 100644 board/friendlyarm/mini2440/Makefile
create mode 100644 board/friendlyarm/mini2440/mini2440.c
create mode 100644 board/friendlyarm/mini2440/mini2440.h
create mode 100644 doc/README.mini2440
create mode 100644 include/configs/mini2440.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 72f8b64..f1bc316 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -566,6 +566,10 @@ Unknown / orphaned boards:
# Board CPU #
#########################################################################
+Gabriel HUAU <contact@huau-gabriel.fr>
+
+ mini2440 s3c2440
+
Albert ARIBAUD <albert.u.boot@aribaud.net>
edminiv2 ARM926EJS (Orion5x SoC)
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 0000000..b88e569
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2012
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mini2440.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
new file mode 100644
index 0000000..49e66a5
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.c
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include "mini2440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void pll_delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+int board_early_init_f(void) {
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
+ clk_power->clkdivn = CLKDIVN_VAL;
+
+ /* configure UPLL */
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ /* some delay between MPLL and UPLL */
+ pll_delay(100);
+
+ /* configure MPLL */
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay(10000);
+
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* IOMUX Port H : UART Configuration */
+ gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
+ IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
+
+ gpio_direction_output(GPH8, 0);
+ gpio_direction_output(GPH9, 0);
+ gpio_direction_output(GPH10, 0);
+
+ /* Disable PULLUP from bit 0 to 9 */
+ //gpio->gphup = 0x1FF;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct s3c24x0_memctl* memctl = s3c24x0_get_base_memctl();
+
+ /*
+ * Configuring bus width and timing
+ * Initialize clocks for each bank 0..5
+ * Bank 3 and 4 are used for DM9000
+ */
+ writel(BANK_CONF, &memctl->bwscon);
+ writel(B0_CONF, &memctl->bankcon[0]);
+ writel(B1_CONF, &memctl->bankcon[1]);
+ writel(B2_CONF, &memctl->bankcon[2]);
+ writel(B3_CONF, &memctl->bankcon[3]);
+ writel(B4_CONF, &memctl->bankcon[4]);
+ writel(B5_CONF, &memctl->bankcon[5]);
+
+ /* Bank 6 and 7 are used for DRAM */
+ writel(SDRAM_64MB, &memctl->bankcon[6]);
+ writel(SDRAM_64MB, &memctl->bankcon[7]);
+
+ writel(MEM_TIMING, &memctl->refresh);
+ writel(BANKSIZE_CONF, &memctl->banksize);
+ writel(B6_MRSR, &memctl->mrsrb6);
+ writel(B7_MRSR, &memctl->mrsrb7);;
+
+ gd->ram_size = get_ram_size((void*) PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ return dm9000_initialize(bis);
+#else
+ return 0;
+#endif
+}
diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
new file mode 100644
index 0000000..86976fb
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.h
@@ -0,0 +1,144 @@
+#ifndef __MINI2440_BOARD_CONF_H__
+#define __MINI2440_BOARD_CONF_H__
+
+/* PLL Parameters */
+#define CLKDIVN_VAL 7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+
+/* BWSCON */
+#define DW8 0x0
+#define DW16 0x1
+#define DW32 0x2
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16 + WAIT + UBLB)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/*
+ * Bank Configuration
+ */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0 /* 0clk */
+#define B0_PMC 0x0 /* normal */
+
+#define B1_Tacs 0x0
+#define B1_Tcos 0x0
+#define B1_Tacc 0x7
+#define B1_Tcoh 0x0
+#define B1_Tah 0x0
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x3 /* 4clk */
+#define B3_Tacp 0x0
+#define B3_PMC 0x0
+
+#define B4_Tacs 0x0
+#define B4_Tcos 0x3
+#define B4_Tacc 0x7
+#define B4_Tcoh 0x1
+#define B4_Tah 0x3
+#define B4_Tacp 0x0
+#define B4_PMC 0x0
+
+#define B5_Tacs 0x0
+#define B5_Tcos 0x0
+#define B5_Tacc 0x7
+#define B5_Tcoh 0x0
+#define B5_Tah 0x0
+#define B5_Tacp 0x0
+#define B5_PMC 0x0
+
+/*
+ * SDRAM Configuration
+ */
+#define SDRAM_MT 0x3 /* SDRAM */
+#define SDRAM_Trcd 0x0 /* 2clk */
+#define SDRAM_SCAN_9 0x1 /* 9bit */
+#define SDRAM_SCAN_10 0x2 /* 10bit */
+
+#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+
+/*
+ * Refresh Parameter
+ */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x1 /* 3clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x0 /* unused */
+#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
+
+/*
+ * MRSR Parameter
+ */
+#define BL 0x0
+#define BT 0x0
+#define CL 0x3 /* 3 clocks */
+#define TM 0x0
+#define WBL 0x0
+
+/*
+ * BankSize Parameter
+ */
+#define BK76MAP 0x2 /* 128MB/128MB */
+#define SCLK_EN 0x1 /* SCLK active */
+#define SCKE_EN 0x1 /* SDRAM power down mode enable */
+#define BURST_EN 0x1 /* Burst enable */
+
+/*
+ * Register values
+ */
+#define BANK_CONF (0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
+ (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
+ (B7_BWSCON<<28))
+
+#define B0_CONF (B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + (B0_Tcoh<<6) + \
+ (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC)
+#define B1_CONF (B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + (B1_Tcoh<<6) + \
+ (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC)
+#define B2_CONF (B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + (B2_Tcoh<<6) + \
+ (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC)
+#define B3_CONF (B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + (B3_Tcoh<<6) + \
+ (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC)
+#define B4_CONF (B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + (B4_Tcoh<<6) + \
+ (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC)
+#define B5_CONF (B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + (B5_Tcoh<<6) + \
+ (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC)
+
+#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + (Trc<<18) + \
+ (Tchr<<16) + REFCNT
+
+#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
+#define B6_MRSR (CL<<4)
+#define B7_MRSR (CL<<4)
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 3cf75c3..93eeb3c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -61,6 +61,7 @@ mx1ads arm arm920t - -
scb9328 arm arm920t - - imx
cm4008 arm arm920t - - ks8695
cm41xx arm arm920t - - ks8695
+mini2440 arm arm920t mini2440 friendlyarm s3c24x0
VCMA9 arm arm920t vcma9 mpl s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
omap1510inn arm arm925t - ti
diff --git a/doc/README.mini2440 b/doc/README.mini2440
new file mode 100644
index 0000000..ceb4674
--- /dev/null
+++ b/doc/README.mini2440
@@ -0,0 +1,28 @@
+U-Boot for FriendlyARM Mini2440 (s3c2440)
+
+This file contains information for the port of U-Boot to FriendlyARM
+mini2440
+
+All information about the board can be found on :
+http://www.friendlyarm.net/products/mini2440
+
+To build u-boot : ./MAKEALL mini2440
+
+Overview :
+--------
+FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
+ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
+systems. It's a low cost board.
+
+Boot Methods :
+------------
+Mini2440 can boot from NOR, NAND and SD card.
+
+Build :
+-----
+./MAKEALL mini2440
+
+or
+
+make mini2440_config
+make
diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
new file mode 100644
index 0000000..a6ce0b9
--- /dev/null
+++ b/include/configs/mini2440.h
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009-2010
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * Configuation settings for the MINI2440 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_S3C2440_GPIO
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM920T /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 /* in a SAMSUNG S3C2440 SoC */
+#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
+#define CONFIG_MINI2440 /* on a MIN2440 Board */
+
+#define MACH_TYPE_MINI2440 1999
+#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
+
+/*
+ * We don't use lowlevel_init
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+
+/*
+ * It is possible to have u-boot save it's environment in NOR, however,
+ * reember it is incompatible with booting from NAND as the NOR is not
+ * available at that point. So use this only if you use nand as storage
+ * and will never boot from it
+ */
+#define CONFIG_MINI2440_NOR_ENV
+/* allow use of frequencies over 405Mhz */
+#define CONFIG_MINI2440_OVERCLOCK
+
+/*
+ * input clock of PLL
+ */
+/* MINI2440 has 12.0000MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+#define USE_920T_MMU
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_DM9000
+#define CONFIG_DRIVER_DM9000_NO_EEPROM
+#define CONFIG_DM9000_BASE 0x20000300
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+4)
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1
+
+/*
+ * allow to overwrite serial and ethaddr
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_LONGHELP
+#define CONFIG_SYS_PROMPT "MINI2440 => "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x30000000
+#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x32000000
+
+/* boot parameters address */
+#define CONFIG_BOOT_PARAM_ADDR 0x30000100
+
+/*
+ * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
+ * it to wrap 100 times (total 1562500) to get 1 sec.
+ */
+#define CONFIG_SYS_HZ 1562500
+
+/*
+ * valid baudrates
+ */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM 0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+/*
+ * Stack should be on the SRAM because
+ * DRAM is not init
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * When booting from NAND, it is impossible to access the lowest addresses
+ * due to the SteppingStone being in the way. Luckily the NOR doesn't really
+ * care about the highest 16 bits of address, so we set the controlers
+ * registers to go and poke over there, instead.
+ */
+#define PHYS_FLASH_1 0x0
+#define CONFIG_SYS_FLASH_BASE 0x0
+
+/*
+ * NOR FLASH organization
+ * Now uses the standard CFI interface
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE 0x0
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* 512 * 4096 sectors, or 32 * 64k blocks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_FLASH_SHOW_PROGRESS 1
+
+/*
+ * Config for NOR flash
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_MY_ENV_OFFSET 0x40000
+/* addr of environment */
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_MY_ENV_OFFSET)
+/* 16k Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x4000
+
+#define CONFIG_PREBOOT_OVERRIDE
+
+/* ATAG configuration */
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v5] Add support for MINI2440 (s3c2440).
2012-04-29 21:27 ` [U-Boot] [PATCH 2/2 v5] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-29 23:32 ` Marek Vasut
0 siblings, 0 replies; 50+ messages in thread
From: Marek Vasut @ 2012-04-29 23:32 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> ---
> Changes for v2:
> - Coding style cleanup
> - Remove unnecessary files modification
> - Remove unnecessary board configuration set
>
> Changes for v3:
> - Coding style cleanup
> - Move some macro definition from lowlevel_init.S
> to a new header
> - Remove some "magic bloat" with I/O board initialization
> - Add a pll_delay and replace loop by it
> - Somme cleanup in the configuration file
> - Cancel modifications on an SoC specific header
> - Add my name to copyright
>
> Changes for v4:
> - Move dram init to dram_init() instead low_levelinit
> - Remove u-boot env from configuration file and change
> the address of initial SP
> - Remove PLL init, now it's SoC specific
>
> Changes fr v5:
> - Clean up configuration file
> - Add a MAINTAINERS entry
> - Add a README.mini2440 file
> - Use gpio/iomux interface in case of magic numbers
> - Use get_ram_size()
>
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> MAINTAINERS | 4 +
> board/friendlyarm/mini2440/Makefile | 44 +++++++
> board/friendlyarm/mini2440/mini2440.c | 135 +++++++++++++++++++++
> board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.mini2440 | 28 +++++
> include/configs/mini2440.h | 209
> +++++++++++++++++++++++++++++++++ 7 files changed, 565 insertions(+)
> create mode 100644 board/friendlyarm/mini2440/Makefile
> create mode 100644 board/friendlyarm/mini2440/mini2440.c
> create mode 100644 board/friendlyarm/mini2440/mini2440.h
> create mode 100644 doc/README.mini2440
> create mode 100644 include/configs/mini2440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 72f8b64..f1bc316 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -566,6 +566,10 @@ Unknown / orphaned boards:
> # Board CPU #
> #########################################################################
>
> +Gabriel HUAU <contact@huau-gabriel.fr>
> +
> + mini2440 s3c2440
> +
> Albert ARIBAUD <albert.u.boot@aribaud.net>
>
> edminiv2 ARM926EJS (Orion5x SoC)
> diff --git a/board/friendlyarm/mini2440/Makefile
> b/board/friendlyarm/mini2440/Makefile new file mode 100644
> index 0000000..b88e569
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/Makefile
> @@ -0,0 +1,44 @@
> +#
> +# (C) Copyright 2012
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := mini2440.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/friendlyarm/mini2440/mini2440.c
> b/board/friendlyarm/mini2440/mini2440.c new file mode 100644
> index 0000000..49e66a5
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.c
> @@ -0,0 +1,135 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <netdev.h>
> +#include "mini2440.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static inline void pll_delay(unsigned long loops)
> +{
> + __asm__ volatile ("1:\n"
asm volatile(), without underscores
> + "subs %0, %1, #1\n"
> + "bne 1b":"=r" (loops):"0" (loops));
> +}
> +
> +int board_early_init_f(void) {
> + struct s3c24x0_clock_power * const clk_power =
> + s3c24x0_get_base_clock_power();
> +
> + /* to reduce PLL lock time, adjust the LOCKTIME register */
> + clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
> + clk_power->clkdivn = CLKDIVN_VAL;
> +
> + /* configure UPLL */
> + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
> + /* some delay between MPLL and UPLL */
> + pll_delay(100);
> +
> + /* configure MPLL */
> + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
> +
> + /* some delay between MPLL and UPLL */
> + pll_delay(10000);
> +
> + return 0;
> +}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
> +
> + /* IOMUX Port H : UART Configuration */
> + gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
> + IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 |
IOMUXH_RXD2;
> +
> + gpio_direction_output(GPH8, 0);
> + gpio_direction_output(GPH9, 0);
> + gpio_direction_output(GPH10, 0);
> +
> + /* Disable PULLUP from bit 0 to 9 */
> + //gpio->gphup = 0x1FF;
C++ comment, remove :-)
> +
> + /* adress of boot parameters */
> + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + struct s3c24x0_memctl* memctl = s3c24x0_get_base_memctl();
> +
> + /*
> + * Configuring bus width and timing
> + * Initialize clocks for each bank 0..5
> + * Bank 3 and 4 are used for DM9000
> + */
> + writel(BANK_CONF, &memctl->bwscon);
> + writel(B0_CONF, &memctl->bankcon[0]);
> + writel(B1_CONF, &memctl->bankcon[1]);
> + writel(B2_CONF, &memctl->bankcon[2]);
> + writel(B3_CONF, &memctl->bankcon[3]);
> + writel(B4_CONF, &memctl->bankcon[4]);
> + writel(B5_CONF, &memctl->bankcon[5]);
> +
> + /* Bank 6 and 7 are used for DRAM */
> + writel(SDRAM_64MB, &memctl->bankcon[6]);
> + writel(SDRAM_64MB, &memctl->bankcon[7]);
> +
> + writel(MEM_TIMING, &memctl->refresh);
> + writel(BANKSIZE_CONF, &memctl->banksize);
> + writel(B6_MRSR, &memctl->mrsrb6);
> + writel(B7_MRSR, &memctl->mrsrb7);;
> +
> + gd->ram_size = get_ram_size((void*) PHYS_SDRAM, PHYS_SDRAM_SIZE);
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#ifdef CONFIG_DRIVER_DM9000
> + return dm9000_initialize(bis);
> +#else
> + return 0;
> +#endif
> +}
> diff --git a/board/friendlyarm/mini2440/mini2440.h
> b/board/friendlyarm/mini2440/mini2440.h new file mode 100644
> index 0000000..86976fb
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.h
> @@ -0,0 +1,144 @@
> +#ifndef __MINI2440_BOARD_CONF_H__
> +#define __MINI2440_BOARD_CONF_H__
> +
> +/* PLL Parameters */
> +#define CLKDIVN_VAL 7
> +#define M_MDIV 0x7f
> +#define M_PDIV 0x2
> +#define M_SDIV 0x1
> +
> +#define U_M_MDIV 0x38
> +#define U_M_PDIV 0x2
> +#define U_M_SDIV 0x2
> +
> +/* BWSCON */
> +#define DW8 0x0
> +#define DW16 0x1
> +#define DW32 0x2
> +#define WAIT (0x1<<2)
> +#define UBLB (0x1<<3)
> +
> +#define B1_BWSCON (DW32)
> +#define B2_BWSCON (DW16)
> +#define B3_BWSCON (DW16 + WAIT + UBLB)
> +#define B4_BWSCON (DW16 + WAIT + UBLB)
> +#define B5_BWSCON (DW16)
> +#define B6_BWSCON (DW32)
> +#define B7_BWSCON (DW32)
> +
> +/*
> + * Bank Configuration
> + */
> +#define B0_Tacs 0x0 /* 0clk */
> +#define B0_Tcos 0x0 /* 0clk */
> +#define B0_Tacc 0x7 /* 14clk */
> +#define B0_Tcoh 0x0 /* 0clk */
> +#define B0_Tah 0x0 /* 0clk */
> +#define B0_Tacp 0x0 /* 0clk */
> +#define B0_PMC 0x0 /* normal */
> +
> +#define B1_Tacs 0x0
> +#define B1_Tcos 0x0
> +#define B1_Tacc 0x7
> +#define B1_Tcoh 0x0
> +#define B1_Tah 0x0
> +#define B1_Tacp 0x0
> +#define B1_PMC 0x0
> +
> +#define B2_Tacs 0x0
> +#define B2_Tcos 0x0
> +#define B2_Tacc 0x7
> +#define B2_Tcoh 0x0
> +#define B2_Tah 0x0
> +#define B2_Tacp 0x0
> +#define B2_PMC 0x0
> +
> +#define B3_Tacs 0x0
> +#define B3_Tcos 0x3 /* 4clk */
> +#define B3_Tacc 0x7
> +#define B3_Tcoh 0x1 /* 1clk */
> +#define B3_Tah 0x3 /* 4clk */
> +#define B3_Tacp 0x0
> +#define B3_PMC 0x0
> +
> +#define B4_Tacs 0x0
> +#define B4_Tcos 0x3
> +#define B4_Tacc 0x7
> +#define B4_Tcoh 0x1
> +#define B4_Tah 0x3
> +#define B4_Tacp 0x0
> +#define B4_PMC 0x0
> +
> +#define B5_Tacs 0x0
> +#define B5_Tcos 0x0
> +#define B5_Tacc 0x7
> +#define B5_Tcoh 0x0
> +#define B5_Tah 0x0
> +#define B5_Tacp 0x0
> +#define B5_PMC 0x0
> +
> +/*
> + * SDRAM Configuration
> + */
> +#define SDRAM_MT 0x3 /* SDRAM */
> +#define SDRAM_Trcd 0x0 /* 2clk */
> +#define SDRAM_SCAN_9 0x1 /* 9bit */
> +#define SDRAM_SCAN_10 0x2 /* 10bit */
> +
> +#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
> +
> +/*
> + * Refresh Parameter
> + */
> +#define REFEN 0x1 /* Refresh enable */
> +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
> +#define Trp 0x1 /* 3clk */
> +#define Trc 0x3 /* 7clk */
> +#define Tchr 0x0 /* unused */
> +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 +
1-10.37*100)
> */ +
> +/*
> + * MRSR Parameter
> + */
> +#define BL 0x0
> +#define BT 0x0
> +#define CL 0x3 /* 3 clocks */
> +#define TM 0x0
> +#define WBL 0x0
> +
> +/*
> + * BankSize Parameter
> + */
> +#define BK76MAP 0x2 /* 128MB/128MB */
> +#define SCLK_EN 0x1 /* SCLK active */
> +#define SCKE_EN 0x1 /* SDRAM power down mode enable */
> +#define BURST_EN 0x1 /* Burst enable */
> +
> +/*
> + * Register values
> + */
> +#define BANK_CONF (0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) +
> \ + (B4_BWSCON<<16) + (B5_BWSCON<<20) +
(B6_BWSCON<<24) + \
> + (B7_BWSCON<<28))
> +
> +#define B0_CONF (B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) +
> (B0_Tcoh<<6) + \ + (B0_Tah<<4) + (B0_Tacp<<2) +
(B0_PMC)
> +#define B1_CONF (B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) +
> (B1_Tcoh<<6) + \ + (B1_Tah<<4) + (B1_Tacp<<2) +
(B1_PMC)
> +#define B2_CONF (B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) +
> (B2_Tcoh<<6) + \ + (B2_Tah<<4) + (B2_Tacp<<2) +
(B2_PMC)
> +#define B3_CONF (B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) +
> (B3_Tcoh<<6) + \ + (B3_Tah<<4) + (B3_Tacp<<2) +
(B3_PMC)
> +#define B4_CONF (B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) +
> (B4_Tcoh<<6) + \ + (B4_Tah<<4) + (B4_Tacp<<2) +
(B4_PMC)
> +#define B5_CONF (B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) +
> (B5_Tcoh<<6) + \ + (B5_Tah<<4) + (B5_Tacp<<2) +
(B5_PMC)
> +
> +#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + (Trc<<18) + \
> + (Tchr<<16) + REFCNT
> +
> +#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) +
You're missing () parens here in all those macros.
> (BURST_EN<<7) +#define B6_MRSR (CL<<4)
> +#define B7_MRSR (CL<<4)
> +
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 3cf75c3..93eeb3c 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -61,6 +61,7 @@ mx1ads arm arm920t -
> - scb9328 arm arm920t -
> - imx cm4008 arm
> arm920t - - ks8695 cm41xx
> arm arm920t - - ks8695
> +mini2440 arm arm920t mini2440
> friendlyarm s3c24x0 VCMA9 arm arm920t
> vcma9 mpl s3c24x0 smdk2410
> arm arm920t - samsung s3c24x0
> omap1510inn arm arm925t -
> ti diff --git a/doc/README.mini2440 b/doc/README.mini2440
> new file mode 100644
> index 0000000..ceb4674
> --- /dev/null
> +++ b/doc/README.mini2440
> @@ -0,0 +1,28 @@
> +U-Boot for FriendlyARM Mini2440 (s3c2440)
> +
> +This file contains information for the port of U-Boot to FriendlyARM
> +mini2440
> +
> +All information about the board can be found on :
> +http://www.friendlyarm.net/products/mini2440
> +
> +To build u-boot : ./MAKEALL mini2440
> +
> +Overview :
> +--------
> +FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung
> S3C2440 +ARM9 processor. The board measures 100 x 100 mm, ideal for
> learning about ARM9 +systems. It's a low cost board.
> +
> +Boot Methods :
> +------------
> +Mini2440 can boot from NOR, NAND and SD card.
> +
> +Build :
> +-----
> +./MAKEALL mini2440
> +
> +or
> +
> +make mini2440_config
> +make
> diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
> new file mode 100644
> index 0000000..a6ce0b9
> --- /dev/null
> +++ b/include/configs/mini2440.h
> @@ -0,0 +1,209 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + * Gary Jennejohn <gj@denx.de>
> + * David Mueller <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009-2010
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * Configuation settings for the MINI2440 board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_SYS_TEXT_BASE 0x0
> +#define CONFIG_S3C2440_GPIO
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARM920T /* This is an ARM920T Core
*/
> +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C2440 SoC */
> +#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
The comment above is duplicated :p
> +#define CONFIG_MINI2440 /* on a MIN2440 Board */
> +
> +#define MACH_TYPE_MINI2440 1999
> +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
> +
> +/*
> + * We don't use lowlevel_init
> + */
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +
> +/*
> + * It is possible to have u-boot save it's environment in NOR, however,
> + * reember it is incompatible with booting from NAND as the NOR is not
> + * available at that point. So use this only if you use nand as storage
> + * and will never boot from it
> + */
> +#define CONFIG_MINI2440_NOR_ENV
> +/* allow use of frequencies over 405Mhz */
> +#define CONFIG_MINI2440_OVERCLOCK
> +
> +/*
> + * input clock of PLL
> + */
> +/* MINI2440 has 12.0000MHz input clock */
> +#define CONFIG_SYS_CLK_FREQ 12000000
> +
> +#define USE_920T_MMU
> +#define CONFIG_BAUDRATE 115200
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_DRIVER_DM9000
> +#define CONFIG_DRIVER_DM9000_NO_EEPROM
> +#define CONFIG_DM9000_BASE 0x20000300
> +#define DM9000_IO CONFIG_DM9000_BASE
> +#define DM9000_DATA (CONFIG_DM9000_BASE+4)
> +
> +/*
> + * select serial console configuration
> + */
> +#define CONFIG_S3C24X0_SERIAL
> +#define CONFIG_SERIAL1
> +
> +/*
> + * allow to overwrite serial and ethaddr
> + */
> +#define CONFIG_ENV_OVERWRITE
> +
> +/*
> + * Command definition
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PORTIO
> +#define CONFIG_CMD_REGINFO
> +#define CONFIG_CMD_SAVES
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_LONGHELP
> +#define CONFIG_SYS_PROMPT "MINI2440 => "
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16
> ) +#define CONFIG_SYS_MAXARGS 32
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START 0x30000000
> +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM
*/
> +
> +/* default load address */
> +#define CONFIG_SYS_LOAD_ADDR 0x32000000
> +
> +/* boot parameters address */
> +#define CONFIG_BOOT_PARAM_ADDR 0x30000100
> +
> +/*
> + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
> + * it to wrap 100 times (total 1562500) to get 1 sec.
> + */
> +#define CONFIG_SYS_HZ 1562500
> +
> +/*
> + * valid baudrates
> + */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
> +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> +#endif
> +
> +/*
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM
> */ +#define PHYS_SDRAM 0x30000000 /* SDRAM Bank #1 */
> +#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
> +/*
> + * Stack should be on the SRAM because
> + * DRAM is not init
> + */
> +#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 -
GENERATED_GBL_DATA_SIZE)
> +
> +/*
> + * When booting from NAND, it is impossible to access the lowest addresses
> + * due to the SteppingStone being in the way. Luckily the NOR doesn't
> really + * care about the highest 16 bits of address, so we set the
> controlers + * registers to go and poke over there, instead.
> + */
> +#define PHYS_FLASH_1 0x0
> +#define CONFIG_SYS_FLASH_BASE 0x0
> +
> +/*
> + * NOR FLASH organization
> + * Now uses the standard CFI interface
> + * FLASH and environment organization
> + */
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> +#define CONFIG_SYS_MONITOR_BASE 0x0
> +/* max number of memory banks */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +/* 512 * 4096 sectors, or 32 * 64k blocks */
> +#define CONFIG_SYS_MAX_FLASH_SECT 512
> +#define CONFIG_FLASH_SHOW_PROGRESS 1
> +
> +/*
> + * Config for NOR flash
> + */
> +#define CONFIG_ENV_IS_IN_FLASH
> +#define CONFIG_MY_ENV_OFFSET 0x40000
> +/* addr of environment */
> +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_MY_ENV_OFFSET)
> +/* 16k Total Size of Environment Sector */
> +#define CONFIG_ENV_SIZE 0x4000
> +
> +#define CONFIG_PREBOOT_OVERRIDE
> +
> +/* ATAG configuration */
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_AUTO_COMPLETE
> +
> +#endif /* __CONFIG_H */
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
2012-04-29 21:27 ` [U-Boot] [PATCH 1/2] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
2012-04-29 21:27 ` [U-Boot] [PATCH 2/2 v5] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-29 21:32 ` Wolfgang Denk
2012-04-29 21:39 ` Gabriel Huau
2012-04-29 23:26 ` Marek Vasut
` (10 subsequent siblings)
13 siblings, 1 reply; 50+ messages in thread
From: Wolfgang Denk @ 2012-04-29 21:32 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
In message <1335734845-27396-1-git-send-email-contact@huau-gabriel.fr> you wrote:
>
> >> +/*
> >> + * When booting from NAND, it is impossible to access the lowest addresses
> >> + * due to the SteppingStone being in the way. Luckily the NOR doesn't really
> >> + * care about the highest 16 bits of address, so we set the controlers
> >> + * registers to go and poke over there, instead.
> >> + */
> >> +#define PHYS_FLASH_1 0x0
> >> +#define CONFIG_SYS_FLASH_BASE 0x0
> >
> >Urghh... this sounds very much like a serious design issue?
>
> About this point, I ported it from the old version uboot as well. It may need
> some investigation, but I remember it was a big problem with this board. In the
> case of a NAND boot, we don't have access to NOR because the SteppingStone
> (SRAM) is mapped at the same range.
Should this not only affect the SPL part of the code, while you could
use normal mappings for the real U-Boot.
Umm... but I don't even see any reference to SPL files here. Is this
current code supposed to support NAND booting? and if so, why doesn;t
it use SPL?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Genitiv ins Wasser, weil's Dativ ist!
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-04-29 21:32 ` [U-Boot] [PATCH 0/2] " Wolfgang Denk
@ 2012-04-29 21:39 ` Gabriel Huau
2012-04-30 7:32 ` Wolfgang Denk
0 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-29 21:39 UTC (permalink / raw)
To: u-boot
On Sun, Apr 29, 2012 at 11:32:27PM +0200, Wolfgang Denk wrote:
> Dear Gabriel Huau,
>
> In message <1335734845-27396-1-git-send-email-contact@huau-gabriel.fr> you wrote:
> >
> > >> +/*
> > >> + * When booting from NAND, it is impossible to access the lowest addresses
> > >> + * due to the SteppingStone being in the way. Luckily the NOR doesn't really
> > >> + * care about the highest 16 bits of address, so we set the controlers
> > >> + * registers to go and poke over there, instead.
> > >> + */
> > >> +#define PHYS_FLASH_1 0x0
> > >> +#define CONFIG_SYS_FLASH_BASE 0x0
> > >
> > >Urghh... this sounds very much like a serious design issue?
> >
> > About this point, I ported it from the old version uboot as well. It may need
> > some investigation, but I remember it was a big problem with this board. In the
> > case of a NAND boot, we don't have access to NOR because the SteppingStone
> > (SRAM) is mapped at the same range.
>
> Should this not only affect the SPL part of the code, while you could
> use normal mappings for the real U-Boot.
>
> Umm... but I don't even see any reference to SPL files here. Is this
> current code supposed to support NAND booting? and if so, why doesn;t
> it use SPL?
>
Nope, laters. Currently, the code is only supporting boot from NOR.
Should I remove these defines ?
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> Genitiv ins Wasser, weil's Dativ ist!
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-04-29 21:39 ` Gabriel Huau
@ 2012-04-30 7:32 ` Wolfgang Denk
0 siblings, 0 replies; 50+ messages in thread
From: Wolfgang Denk @ 2012-04-30 7:32 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
In message <20120429213859.GA20804@debian> you wrote:
>
> > Should this not only affect the SPL part of the code, while you could
> > use normal mappings for the real U-Boot.
> >
> > Umm... but I don't even see any reference to SPL files here. Is this
> > current code supposed to support NAND booting? and if so, why doesn;t
> > it use SPL?
>
> Nope, laters. Currently, the code is only supporting boot from NOR.
> Should I remove these defines ?
Yes, please do - as is, it's only dead code and confusing to readers
at best. And eventually it will be implemented differently in the
end.
Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"No proper program contains an indication which as an operator-
applied occurrence identifies an operator-defining occurrence which
as an indication-applied occurrence identifies an indication-defining
occurrence different from the one identified by the given indication
as an indication-applied occurrence." - ALGOL 68 Report
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (2 preceding siblings ...)
2012-04-29 21:32 ` [U-Boot] [PATCH 0/2] " Wolfgang Denk
@ 2012-04-29 23:26 ` Marek Vasut
2012-04-30 11:03 ` [U-Boot] [PATCH 1/2 v2] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
` (9 subsequent siblings)
13 siblings, 0 replies; 50+ messages in thread
From: Marek Vasut @ 2012-04-29 23:26 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> From the last time, I removed the patch about the PLL initialization
> because it's board specific. I added a new patch for s3c440 gpio driver.
> Now in the board file we have no more magic bloat.
Even without looking, I sense flaws ... I sense fluctuations in the patch-force
;-)
So let's get to it :-)
>
> >> +/*
> >> + * When booting from NAND, it is impossible to access the lowest
> >> addresses + * due to the SteppingStone being in the way. Luckily the
> >> NOR doesn't really + * care about the highest 16 bits of address, so we
> >> set the controlers + * registers to go and poke over there, instead.
> >> + */
> >> +#define PHYS_FLASH_1 0x0
> >> +#define CONFIG_SYS_FLASH_BASE 0x0
> >
> >Urghh... this sounds very much like a serious design issue?
>
> About this point, I ported it from the old version uboot as well. It may
> need some investigation, but I remember it was a big problem with this
> board. In the case of a NAND boot, we don't have access to NOR because the
> SteppingStone (SRAM) is mapped at the same range.
We discussed it, didn't we ? The SRAM is only mapped at different place. So drop
the support for nand booting altogether and re-add it when you have it fixed.
>
> Gabriel Huau (2):
> Add GPIO Driver and IOMUX definition for S3C2440
> Add support for MINI2440 (s3c2440).
>
> MAINTAINERS | 4 +
> arch/arm/include/asm/arch-s3c24x0/gpio.h | 183 +++++++++++++++++++++++++
> arch/arm/include/asm/arch-s3c24x0/iomux.h | 197
> +++++++++++++++++++++++++++ board/friendlyarm/mini2440/Makefile |
> 44 ++++++
> board/friendlyarm/mini2440/mini2440.c | 135 +++++++++++++++++++
> board/friendlyarm/mini2440/mini2440.h | 144 ++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.mini2440 | 28 ++++
> drivers/gpio/Makefile | 1 +
> drivers/gpio/s3c2440_gpio.c | 74 ++++++++++
> include/configs/mini2440.h | 209
> +++++++++++++++++++++++++++++ 11 files changed, 1020 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
> create mode 100644 board/friendlyarm/mini2440/Makefile
> create mode 100644 board/friendlyarm/mini2440/mini2440.c
> create mode 100644 board/friendlyarm/mini2440/mini2440.h
> create mode 100644 doc/README.mini2440
> create mode 100644 drivers/gpio/s3c2440_gpio.c
> create mode 100644 include/configs/mini2440.h
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v2] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (3 preceding siblings ...)
2012-04-29 23:26 ` Marek Vasut
@ 2012-04-30 11:03 ` Gabriel Huau
2012-04-30 12:26 ` Marek Vasut
2012-04-30 11:07 ` [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (8 subsequent siblings)
13 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 11:03 UTC (permalink / raw)
To: u-boot
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
Changes for v2:
- Modification of the coding style
- Add my email address to copyright
- Remove a typedef
- Move some defines to driver file
---
arch/arm/include/asm/arch-s3c24x0/gpio.h | 171 ++++++++++++++++++++++++
arch/arm/include/asm/arch-s3c24x0/iomux.h | 200 +++++++++++++++++++++++++++++
drivers/gpio/Makefile | 1 +
drivers/gpio/s3c2440_gpio.c | 94 ++++++++++++++
4 files changed, 466 insertions(+)
create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
create mode 100644 drivers/gpio/s3c2440_gpio.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 0000000..baac14c
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+typedef enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+} s3c2240_gpio;
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 0000000..cc4d6b3
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_IOMUX_H_
+#define _S3C24X0_IOMUX_H_
+
+enum s3c2440_iomux_func {
+ /* PORT A */
+ IOMUXA_ADDR0 = 1,
+ IOMUXA_ADDR16 = (1 << 1),
+ IOMUXA_ADDR17 = (1 << 2),
+ IOMUXA_ADDR18 = (1 << 3),
+ IOMUXA_ADDR19 = (1 << 4),
+ IOMUXA_ADDR20 = (1 << 5),
+ IOMUXA_ADDR21 = (1 << 6),
+ IOMUXA_ADDR22 = (1 << 7),
+ IOMUXA_ADDR23 = (1 << 8),
+ IOMUXA_ADDR24 = (1 << 9),
+ IOMUXA_ADDR25 = (1 << 10),
+ IOMUXA_ADDR26 = (1 << 11),
+ IOMUXA_nGCS1 = (1 << 12),
+ IOMUXA_nGCS2 = (1 << 13),
+ IOMUXA_nGCS3 = (1 << 14),
+ IOMUXA_nGCS4 = (1 << 15),
+ IOMUXA_nGCS5 = (1 << 16),
+ IOMUXA_CLE = (1 << 17),
+ IOMUXA_ALE = (1 << 18),
+ IOMUXA_nFWE = (1 << 19),
+ IOMUXA_nFRE = (1 << 20),
+ IOMUXA_nRSTOUT = (1 << 21),
+ IOMUXA_nFCE = (1 << 22),
+
+ /* PORT B */
+ IOMUXB_nXDREQ0 = (2 << 20),
+ IOMUXB_nXDACK0 = (2 << 18),
+ IOMUXB_nXDREQ1 = (2 << 16),
+ IOMUXB_nXDACK1 = (2 << 14),
+ IOMUXB_nXBREQ = (2 << 12),
+ IOMUXB_nXBACK = (2 << 10),
+ IOMUXB_TCLK0 = (2 << 8),
+ IOMUXB_TOUT3 = (2 << 6),
+ IOMUXB_TOUT2 = (2 << 4),
+ IOMUXB_TOUT1 = (2 << 2),
+ IOMUXB_TOUT0 = 2,
+
+ /* PORT C */
+ IOMUXC_VS7 = (2 << 30),
+ IOMUXC_VS6 = (2 << 28),
+ IOMUXC_VS5 = (2 << 26),
+ IOMUXC_VS4 = (2 << 24),
+ IOMUXC_VS3 = (2 << 22),
+ IOMUXC_VS2 = (2 << 20),
+ IOMUXC_VS1 = (2 << 18),
+ IOMUXC_VS0 = (2 << 16),
+ IOMUXC_LCD_LPCREVB = (2 << 14),
+ IOMUXC_LCD_LPCREV = (2 << 12),
+ IOMUXC_LCD_LPCOE = (2 << 10),
+ IOMUXC_VM = (2 << 8),
+ IOMUXC_VFRAME = (2 << 6),
+ IOMUXC_VLINE = (2 << 4),
+ IOMUXC_VCLK = (2 << 2),
+ IOMUXC_LEND = 2,
+ IOMUXC_I2SSDI = (3 << 8),
+
+ /* PORT D */
+ IOMUXD_VS23 = (2 << 30),
+ IOMUXD_VS22 = (2 << 28),
+ IOMUXD_VS21 = (2 << 26),
+ IOMUXD_VS20 = (2 << 24),
+ IOMUXD_VS19 = (2 << 22),
+ IOMUXD_VS18 = (2 << 20),
+ IOMUXD_VS17 = (2 << 18),
+ IOMUXD_VS16 = (2 << 16),
+ IOMUXD_VS15 = (2 << 14),
+ IOMUXD_VS14 = (2 << 12),
+ IOMUXD_VS13 = (2 << 10),
+ IOMUXD_VS12 = (2 << 8),
+ IOMUXD_VS11 = (2 << 6),
+ IOMUXD_VS10 = (2 << 4),
+ IOMUXD_VS9 = (2 << 2),
+ IOMUXD_VS8 = 2,
+ IOMUXD_nSS0 = (3 << 30),
+ IOMUXD_nSS1 = (3 << 28),
+ IOMUXD_SPICLK1 = (3 << 20),
+ IOMUXD_SPIMOSI1 = (3 << 18),
+ IOMUXD_SPIMISO1 = (3 << 16),
+
+ /* PORT E */
+ IOMUXE_IICSDA = (2 << 30),
+ IOMUXE_IICSCL = (2 << 28),
+ IOMUXE_SPICLK0 = (2 << 26),
+ IOMUXE_SPIMOSI0 = (2 << 24),
+ IOMUXE_SPIMISO0 = (2 << 22),
+ IOMUXE_SDDAT3 = (2 << 20),
+ IOMUXE_SDDAT2 = (2 << 18),
+ IOMUXE_SDDAT1 = (2 << 16),
+ IOMUXE_SDDAT0 = (2 << 14),
+ IOMUXE_SDCMD = (2 << 12),
+ IOMUXE_SDCLK = (2 << 10),
+ IOMUXE_I2SDO = (2 << 8),
+ IOMUXE_I2SDI = (2 << 6),
+ IOMUXE_CDCLK = (2 << 4),
+ IOMUXE_I2SSCLK = (2 << 2),
+ IOMUXE_I2SLRCK = 2,
+ IOMUXE_AC_SDATA_OUT = (3 << 8),
+ IOMUXE_AC_SDATA_IN = (3 << 6),
+ IOMUXE_AC_nRESET = (3 << 4),
+ IOMUXE_AC_BIT_CLK = (3 << 2),
+ IOMUXE_AC_SYNC = 3,
+
+ /* PORT F */
+ IOMUXF_EINT7 = (2 << 14),
+ IOMUXF_EINT6 = (2 << 12),
+ IOMUXF_EINT5 = (2 << 10),
+ IOMUXF_EINT4 = (2 << 8),
+ IOMUXF_EINT3 = (2 << 6),
+ IOMUXF_EINT2 = (2 << 4),
+ IOMUXF_EINT1 = (2 << 2),
+ IOMUXF_EINT0 = 2,
+
+ /* PORT G */
+ IOMUXG_EINT23 = (2 << 30),
+ IOMUXG_EINT22 = (2 << 28),
+ IOMUXG_EINT21 = (2 << 26),
+ IOMUXG_EINT20 = (2 << 24),
+ IOMUXG_EINT19 = (2 << 22),
+ IOMUXG_EINT18 = (2 << 20),
+ IOMUXG_EINT17 = (2 << 18),
+ IOMUXG_EINT16 = (2 << 16),
+ IOMUXG_EINT15 = (2 << 14),
+ IOMUXG_EINT14 = (2 << 12),
+ IOMUXG_EINT13 = (2 << 10),
+ IOMUXG_EINT12 = (2 << 8),
+ IOMUXG_EINT11 = (2 << 6),
+ IOMUXG_EINT10 = (2 << 4),
+ IOMUXG_EINT9 = (2 << 2),
+ IOMUXG_EINT8 = 2,
+ IOMUXG_TCLK1 = (3 << 22),
+ IOMUXG_nCTS1 = (3 << 20),
+ IOMUXG_nRTS1 = (3 << 18),
+ IOMUXG_SPICLK1 = (3 << 14),
+ IOMUXG_SPIMOSI1 = (3 << 12),
+ IOMUXG_SPIMISO1 = (3 << 10),
+ IOMUXG_LCD_PWRDN = (3 << 8),
+ IOMUXG_nSS1 = (3 << 6),
+ IOMUXG_nSS0 = (3 << 4),
+
+ /* PORT H */
+ IOMUXH_CLKOUT1 = (2 << 20),
+ IOMUXH_CLKOUT0 = (2 << 18),
+ IOMUXH_UEXTCLK = (2 << 16),
+ IOMUXH_RXD2 = (2 << 14),
+ IOMUXH_TXD2 = (2 << 12),
+ IOMUXH_RXD1 = (2 << 10),
+ IOMUXH_TXD1 = (2 << 8),
+ IOMUXH_RXD0 = (2 << 6),
+ IOMUXH_TXD0 = (2 << 4),
+ IOMUXH_nRTS0 = (2 << 2),
+ IOMUXH_nCTS0 = 2,
+ IOMUXH_nCTS1 = (3 << 14),
+ IOMUXH_nRTS1 = (3 << 12),
+
+ /* PORT J */
+ IOMUXJ_CAMRESET = (2 << 24),
+ IOMUXJ_CAMCLKOUT = (2 << 22),
+ IOMUXJ_CAMHREF = (2 << 20),
+ IOMUXJ_CAMVSYNC = (2 << 18),
+ IOMUXJ_CAMPCLK = (2 << 16),
+ IOMUXJ_CAMDATA7 = (2 << 14),
+ IOMUXJ_CAMDATA6 = (2 << 12),
+ IOMUXJ_CAMDATA5 = (2 << 10),
+ IOMUXJ_CAMDATA4 = (2 << 8),
+ IOMUXJ_CAMDATA3 = (2 << 6),
+ IOMUXJ_CAMDATA2 = (2 << 4),
+ IOMUXJ_CAMDATA1 = (2 << 2),
+ IOMUXJ_CAMDATA0 = 2
+};
+
+#endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb3b09a..7ae6f84 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
+COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
new file mode 100644
index 0000000..5054390
--- /dev/null
+++ b/drivers/gpio/s3c2440_gpio.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+
+/* 0x4 means that we want DAT and not CON register */
+#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
+#define GPIO_BIT(x) ((x) & 0x3f)
+
+/*
+ * It's how we calculate the full port address
+ * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
+ * We move it at the second digit, and finally we add 0x4 because we want
+ * to modify GPIO DAT and not CON
+ */
+#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) << 1))
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+ unsigned port = GPIO_FULLPORT(gpio);
+
+ /*
+ * All GPIO Port have a configuration on
+ * 2 bits excepted the first GPIO (A) which
+ * have only 1 bit of configuration.
+ */
+ if(value)
+ if(!GPIO_PORT(gpio))
+ l |= (0x1 << GPIO_BIT(gpio));
+ else
+ l |= (0x3 << GPIO_BIT(gpio));
+ else
+ if(!GPIO_PORT(gpio))
+ l &= ~(0x1 << GPIO_BIT(gpio));
+ else
+ l &= ~(0x3 << GPIO_BIT(gpio));
+ return writel(port, l);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+
+ if(GPIO_PORT(gpio) == 0) /* PORT A */
+ return (l >> GPIO_BIT(gpio)) & 0x1;
+ return (l >> GPIO_BIT(gpio)) & 0x3;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
+ return gpio_set_value(gpio, value);
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v2] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-30 11:03 ` [U-Boot] [PATCH 1/2 v2] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-04-30 12:26 ` Marek Vasut
0 siblings, 0 replies; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 12:26 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
>
> ---
> Changes for v2:
> - Modification of the coding style
> - Add my email address to copyright
> - Remove a typedef
> - Move some defines to driver file
Acked-by: Marek Vasut <marex@denx.de>
> ---
> arch/arm/include/asm/arch-s3c24x0/gpio.h | 171 ++++++++++++++++++++++++
> arch/arm/include/asm/arch-s3c24x0/iomux.h | 200
> +++++++++++++++++++++++++++++ drivers/gpio/Makefile |
> 1 +
> drivers/gpio/s3c2440_gpio.c | 94 ++++++++++++++
> 4 files changed, 466 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
> create mode 100644 drivers/gpio/s3c2440_gpio.c
>
> diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h
> b/arch/arm/include/asm/arch-s3c24x0/gpio.h new file mode 100644
> index 0000000..baac14c
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
> @@ -0,0 +1,171 @@
> +/*
> + * Copyright (c) 2012.
> + *
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_GPIO_H_
> +#define _S3C24X0_GPIO_H_
> +
> +typedef enum s3c2440_gpio {
> + GPA0,
> + GPA1,
> + GPA2,
> + GPA3,
> + GPA4,
> + GPA5,
> + GPA6,
> + GPA7,
> + GPA8,
> + GPA9,
> + GPA10,
> + GPA11,
> + GPA12,
> + GPA13,
> + GPA14,
> + GPA15,
> + GPA16,
> + GPA17,
> + GPA18,
> + GPA19,
> + GPA20,
> + GPA21,
> + GPA22,
> + GPA23,
> + GPA24,
> +
> + GPB0 = 32,
> + GPB1,
> + GPB2,
> + GPB3,
> + GPB4,
> + GPB5,
> + GPB6,
> + GPB7,
> + GPB8,
> + GPB9,
> + GPB10,
> +
> + GPC0 = 64,
> + GPC1,
> + GPC2,
> + GPC3,
> + GPC4,
> + GPC5,
> + GPC6,
> + GPC7,
> + GPC8,
> + GPC9,
> + GPC10,
> + GPC11,
> + GPC12,
> + GPC13,
> + GPC14,
> + GPC15,
> +
> + GPD0 = 96,
> + GPD1,
> + GPD2,
> + GPD3,
> + GPD4,
> + GPD5,
> + GPD6,
> + GPD7,
> + GPD8,
> + GPD9,
> + GPD10,
> + GPD11,
> + GPD12,
> + GPD13,
> + GPD14,
> + GPD15,
> +
> + GPE0 = 128,
> + GPE1,
> + GPE2,
> + GPE3,
> + GPE4,
> + GPE5,
> + GPE6,
> + GPE7,
> + GPE8,
> + GPE9,
> + GPE10,
> + GPE11,
> + GPE12,
> + GPE13,
> + GPE14,
> + GPE15,
> +
> + GPF0 = 160,
> + GPF1,
> + GPF2,
> + GPF3,
> + GPF4,
> + GPF5,
> + GPF6,
> + GPF7,
> +
> + GPG0 = 192,
> + GPG1,
> + GPG2,
> + GPG3,
> + GPG4,
> + GPG5,
> + GPG6,
> + GPG7,
> + GPG8,
> + GPG9,
> + GPG10,
> + GPG11,
> + GPG12,
> + GPG13,
> + GPG14,
> + GPG15,
> +
> + GPH0 = 224,
> + GPH1,
> + GPH2,
> + GPH3,
> + GPH4,
> + GPH5,
> + GPH6,
> + GPH7,
> + GPH8,
> + GPH9,
> + GPH10,
> +
> + GPJ0 = 256,
> + GPJ1,
> + GPJ2,
> + GPJ3,
> + GPJ4,
> + GPJ5,
> + GPJ6,
> + GPJ7,
> + GPJ8,
> + GPJ9,
> + GPJ10,
> + GPJ11,
> + GPJ12,
> +} s3c2240_gpio;
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h
> b/arch/arm/include/asm/arch-s3c24x0/iomux.h new file mode 100644
> index 0000000..cc4d6b3
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
> @@ -0,0 +1,200 @@
> +/*
> + * Copyright (c) 2012
> + *
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_IOMUX_H_
> +#define _S3C24X0_IOMUX_H_
> +
> +enum s3c2440_iomux_func {
> + /* PORT A */
> + IOMUXA_ADDR0 = 1,
> + IOMUXA_ADDR16 = (1 << 1),
> + IOMUXA_ADDR17 = (1 << 2),
> + IOMUXA_ADDR18 = (1 << 3),
> + IOMUXA_ADDR19 = (1 << 4),
> + IOMUXA_ADDR20 = (1 << 5),
> + IOMUXA_ADDR21 = (1 << 6),
> + IOMUXA_ADDR22 = (1 << 7),
> + IOMUXA_ADDR23 = (1 << 8),
> + IOMUXA_ADDR24 = (1 << 9),
> + IOMUXA_ADDR25 = (1 << 10),
> + IOMUXA_ADDR26 = (1 << 11),
> + IOMUXA_nGCS1 = (1 << 12),
> + IOMUXA_nGCS2 = (1 << 13),
> + IOMUXA_nGCS3 = (1 << 14),
> + IOMUXA_nGCS4 = (1 << 15),
> + IOMUXA_nGCS5 = (1 << 16),
> + IOMUXA_CLE = (1 << 17),
> + IOMUXA_ALE = (1 << 18),
> + IOMUXA_nFWE = (1 << 19),
> + IOMUXA_nFRE = (1 << 20),
> + IOMUXA_nRSTOUT = (1 << 21),
> + IOMUXA_nFCE = (1 << 22),
> +
> + /* PORT B */
> + IOMUXB_nXDREQ0 = (2 << 20),
> + IOMUXB_nXDACK0 = (2 << 18),
> + IOMUXB_nXDREQ1 = (2 << 16),
> + IOMUXB_nXDACK1 = (2 << 14),
> + IOMUXB_nXBREQ = (2 << 12),
> + IOMUXB_nXBACK = (2 << 10),
> + IOMUXB_TCLK0 = (2 << 8),
> + IOMUXB_TOUT3 = (2 << 6),
> + IOMUXB_TOUT2 = (2 << 4),
> + IOMUXB_TOUT1 = (2 << 2),
> + IOMUXB_TOUT0 = 2,
> +
> + /* PORT C */
> + IOMUXC_VS7 = (2 << 30),
> + IOMUXC_VS6 = (2 << 28),
> + IOMUXC_VS5 = (2 << 26),
> + IOMUXC_VS4 = (2 << 24),
> + IOMUXC_VS3 = (2 << 22),
> + IOMUXC_VS2 = (2 << 20),
> + IOMUXC_VS1 = (2 << 18),
> + IOMUXC_VS0 = (2 << 16),
> + IOMUXC_LCD_LPCREVB = (2 << 14),
> + IOMUXC_LCD_LPCREV = (2 << 12),
> + IOMUXC_LCD_LPCOE = (2 << 10),
> + IOMUXC_VM = (2 << 8),
> + IOMUXC_VFRAME = (2 << 6),
> + IOMUXC_VLINE = (2 << 4),
> + IOMUXC_VCLK = (2 << 2),
> + IOMUXC_LEND = 2,
> + IOMUXC_I2SSDI = (3 << 8),
> +
> + /* PORT D */
> + IOMUXD_VS23 = (2 << 30),
> + IOMUXD_VS22 = (2 << 28),
> + IOMUXD_VS21 = (2 << 26),
> + IOMUXD_VS20 = (2 << 24),
> + IOMUXD_VS19 = (2 << 22),
> + IOMUXD_VS18 = (2 << 20),
> + IOMUXD_VS17 = (2 << 18),
> + IOMUXD_VS16 = (2 << 16),
> + IOMUXD_VS15 = (2 << 14),
> + IOMUXD_VS14 = (2 << 12),
> + IOMUXD_VS13 = (2 << 10),
> + IOMUXD_VS12 = (2 << 8),
> + IOMUXD_VS11 = (2 << 6),
> + IOMUXD_VS10 = (2 << 4),
> + IOMUXD_VS9 = (2 << 2),
> + IOMUXD_VS8 = 2,
> + IOMUXD_nSS0 = (3 << 30),
> + IOMUXD_nSS1 = (3 << 28),
> + IOMUXD_SPICLK1 = (3 << 20),
> + IOMUXD_SPIMOSI1 = (3 << 18),
> + IOMUXD_SPIMISO1 = (3 << 16),
> +
> + /* PORT E */
> + IOMUXE_IICSDA = (2 << 30),
> + IOMUXE_IICSCL = (2 << 28),
> + IOMUXE_SPICLK0 = (2 << 26),
> + IOMUXE_SPIMOSI0 = (2 << 24),
> + IOMUXE_SPIMISO0 = (2 << 22),
> + IOMUXE_SDDAT3 = (2 << 20),
> + IOMUXE_SDDAT2 = (2 << 18),
> + IOMUXE_SDDAT1 = (2 << 16),
> + IOMUXE_SDDAT0 = (2 << 14),
> + IOMUXE_SDCMD = (2 << 12),
> + IOMUXE_SDCLK = (2 << 10),
> + IOMUXE_I2SDO = (2 << 8),
> + IOMUXE_I2SDI = (2 << 6),
> + IOMUXE_CDCLK = (2 << 4),
> + IOMUXE_I2SSCLK = (2 << 2),
> + IOMUXE_I2SLRCK = 2,
> + IOMUXE_AC_SDATA_OUT = (3 << 8),
> + IOMUXE_AC_SDATA_IN = (3 << 6),
> + IOMUXE_AC_nRESET = (3 << 4),
> + IOMUXE_AC_BIT_CLK = (3 << 2),
> + IOMUXE_AC_SYNC = 3,
> +
> + /* PORT F */
> + IOMUXF_EINT7 = (2 << 14),
> + IOMUXF_EINT6 = (2 << 12),
> + IOMUXF_EINT5 = (2 << 10),
> + IOMUXF_EINT4 = (2 << 8),
> + IOMUXF_EINT3 = (2 << 6),
> + IOMUXF_EINT2 = (2 << 4),
> + IOMUXF_EINT1 = (2 << 2),
> + IOMUXF_EINT0 = 2,
> +
> + /* PORT G */
> + IOMUXG_EINT23 = (2 << 30),
> + IOMUXG_EINT22 = (2 << 28),
> + IOMUXG_EINT21 = (2 << 26),
> + IOMUXG_EINT20 = (2 << 24),
> + IOMUXG_EINT19 = (2 << 22),
> + IOMUXG_EINT18 = (2 << 20),
> + IOMUXG_EINT17 = (2 << 18),
> + IOMUXG_EINT16 = (2 << 16),
> + IOMUXG_EINT15 = (2 << 14),
> + IOMUXG_EINT14 = (2 << 12),
> + IOMUXG_EINT13 = (2 << 10),
> + IOMUXG_EINT12 = (2 << 8),
> + IOMUXG_EINT11 = (2 << 6),
> + IOMUXG_EINT10 = (2 << 4),
> + IOMUXG_EINT9 = (2 << 2),
> + IOMUXG_EINT8 = 2,
> + IOMUXG_TCLK1 = (3 << 22),
> + IOMUXG_nCTS1 = (3 << 20),
> + IOMUXG_nRTS1 = (3 << 18),
> + IOMUXG_SPICLK1 = (3 << 14),
> + IOMUXG_SPIMOSI1 = (3 << 12),
> + IOMUXG_SPIMISO1 = (3 << 10),
> + IOMUXG_LCD_PWRDN = (3 << 8),
> + IOMUXG_nSS1 = (3 << 6),
> + IOMUXG_nSS0 = (3 << 4),
> +
> + /* PORT H */
> + IOMUXH_CLKOUT1 = (2 << 20),
> + IOMUXH_CLKOUT0 = (2 << 18),
> + IOMUXH_UEXTCLK = (2 << 16),
> + IOMUXH_RXD2 = (2 << 14),
> + IOMUXH_TXD2 = (2 << 12),
> + IOMUXH_RXD1 = (2 << 10),
> + IOMUXH_TXD1 = (2 << 8),
> + IOMUXH_RXD0 = (2 << 6),
> + IOMUXH_TXD0 = (2 << 4),
> + IOMUXH_nRTS0 = (2 << 2),
> + IOMUXH_nCTS0 = 2,
> + IOMUXH_nCTS1 = (3 << 14),
> + IOMUXH_nRTS1 = (3 << 12),
> +
> + /* PORT J */
> + IOMUXJ_CAMRESET = (2 << 24),
> + IOMUXJ_CAMCLKOUT = (2 << 22),
> + IOMUXJ_CAMHREF = (2 << 20),
> + IOMUXJ_CAMVSYNC = (2 << 18),
> + IOMUXJ_CAMPCLK = (2 << 16),
> + IOMUXJ_CAMDATA7 = (2 << 14),
> + IOMUXJ_CAMDATA6 = (2 << 12),
> + IOMUXJ_CAMDATA5 = (2 << 10),
> + IOMUXJ_CAMDATA4 = (2 << 8),
> + IOMUXJ_CAMDATA3 = (2 << 6),
> + IOMUXJ_CAMDATA2 = (2 << 4),
> + IOMUXJ_CAMDATA1 = (2 << 2),
> + IOMUXJ_CAMDATA0 = 2
> +};
> +
> +#endif
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index fb3b09a..7ae6f84 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
> COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
> COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
> COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
> +COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
>
> COBJS := $(COBJS-y)
> SRCS := $(COBJS:.o=.c)
> diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
> new file mode 100644
> index 0000000..5054390
> --- /dev/null
> +++ b/drivers/gpio/s3c2440_gpio.c
> @@ -0,0 +1,94 @@
> +/*
> + * Copyright (C) 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +
> +#define GPIO_INPUT 0x0
> +#define GPIO_OUTPUT 0x1
> +
> +/* 0x4 means that we want DAT and not CON register */
> +#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
> +#define GPIO_BIT(x) ((x) & 0x3f)
> +
> +/*
> + * It's how we calculate the full port address
> + * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
> + * We move it at the second digit, and finally we add 0x4 because we want
> + * to modify GPIO DAT and not CON
> + */
> +#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) <<
> 1)) +
> +int gpio_set_value(unsigned gpio, int value)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> + unsigned port = GPIO_FULLPORT(gpio);
> +
> + /*
> + * All GPIO Port have a configuration on
> + * 2 bits excepted the first GPIO (A) which
> + * have only 1 bit of configuration.
> + */
> + if(value)
> + if(!GPIO_PORT(gpio))
> + l |= (0x1 << GPIO_BIT(gpio));
> + else
> + l |= (0x3 << GPIO_BIT(gpio));
> + else
> + if(!GPIO_PORT(gpio))
> + l &= ~(0x1 << GPIO_BIT(gpio));
> + else
> + l &= ~(0x3 << GPIO_BIT(gpio));
> + return writel(port, l);
> +}
> +
> +int gpio_get_value(unsigned gpio)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> +
> + if(GPIO_PORT(gpio) == 0) /* PORT A */
> + return (l >> GPIO_BIT(gpio)) & 0x1;
> + return (l >> GPIO_BIT(gpio)) & 0x3;
> +}
> +
> +int gpio_request(unsigned gpio, const char *label)
> +{
> + return 0;
> +}
> +
> +int gpio_free(unsigned gpio)
> +{
> + return 0;
> +}
> +
> +int gpio_direction_input(unsigned gpio)
> +{
> + return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
> +}
> +
> +int gpio_direction_output(unsigned gpio, int value)
> +{
> + writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
> + return gpio_set_value(gpio, value);
> +}
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (4 preceding siblings ...)
2012-04-30 11:03 ` [U-Boot] [PATCH 1/2 v2] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-04-30 11:07 ` Gabriel Huau
2012-04-30 11:35 ` Wolfgang Denk
2012-04-30 11:11 ` [U-Boot] [PATCH 2/2 v6] " Gabriel Huau
` (7 subsequent siblings)
13 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 11:07 UTC (permalink / raw)
To: u-boot
Hi,
Just a little question about the ChangeLog. I added the "---" and my
changements after it, but I see this part in "git log", is it normal ?
Will this part be deleted in the merge ?
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-04-30 11:07 ` [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-30 11:35 ` Wolfgang Denk
2012-04-30 11:55 ` Gabriel Huau
0 siblings, 1 reply; 50+ messages in thread
From: Wolfgang Denk @ 2012-04-30 11:35 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
In message <20120430110724.GB4656@debian> you wrote:
>
> Just a little question about the ChangeLog. I added the "---" and my
> changements after it, but I see this part in "git log", is it normal ?
> Will this part be deleted in the merge ?
You should never see this in a git log.
The "---" separator line gets automatically inserted by "git format-patch";
you add your comments manually after creating the patch by inserting
them below this line. "git am" will then ignore this line and
everything below it.
So if you can see this as part of the commit message, something went
wrong.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Punishment becomes ineffective after a certain point. Men become in-
sensitive.
-- Eneg, "Patterns of Force", stardate 2534.7
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-04-30 11:35 ` Wolfgang Denk
@ 2012-04-30 11:55 ` Gabriel Huau
0 siblings, 0 replies; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 11:55 UTC (permalink / raw)
To: u-boot
On Mon, Apr 30, 2012 at 01:35:01PM +0200, Wolfgang Denk wrote:
> Dear Gabriel Huau,
>
> In message <20120430110724.GB4656@debian> you wrote:
> >
> > Just a little question about the ChangeLog. I added the "---" and my
> > changements after it, but I see this part in "git log", is it normal ?
> > Will this part be deleted in the merge ?
>
> You should never see this in a git log.
>
> The "---" separator line gets automatically inserted by "git format-patch";
> you add your comments manually after creating the patch by inserting
> them below this line. "git am" will then ignore this line and
> everything below it.
>
> So if you can see this as part of the commit message, something went
> wrong.
Ok thanks, I misunderstood, I will modify this error after the next review.
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 2/2 v6] Add support for MINI2440 (s3c2440).
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (5 preceding siblings ...)
2012-04-30 11:07 ` [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-30 11:11 ` Gabriel Huau
2012-04-30 12:29 ` Marek Vasut
2012-04-30 13:16 ` [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
` (6 subsequent siblings)
13 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 11:11 UTC (permalink / raw)
To: u-boot
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
Changes for v2:
- Coding style cleanup
- Remove unnecessary files modification
- Remove unnecessary board configuration set
Changes for v3:
- Coding style cleanup
- Move some macro definition from lowlevel_init.S
to a new header
- Remove some "magic bloat" with I/O board initialization
- Add a pll_delay and replace loop by it
- Somme cleanup in the configuration file
- Cancel modifications on an SoC specific header
- Add my name to copyright
Changes for v4:
- Move dram init to dram_init() instead low_levelinit
- Remove u-boot env from configuration file and change
the address of initial SP
- Remove PLL init, now it's SoC specific
Changes for v5:
- Clean up configuration file
- Add a MAINTAINERS entry
- Add a README.mini2440 file
- Use gpio/iomux interface in case of magic numbers
- Use get_ram_size()
Changes for v6:
- Coding style cleanup
- Remove some unused define in the board config
---
MAINTAINERS | 4 +
board/friendlyarm/mini2440/Makefile | 44 ++++++++
board/friendlyarm/mini2440/mini2440.c | 132 +++++++++++++++++++++++
board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.mini2440 | 28 +++++
include/configs/mini2440.h | 186 +++++++++++++++++++++++++++++++++
7 files changed, 539 insertions(+)
create mode 100644 board/friendlyarm/mini2440/Makefile
create mode 100644 board/friendlyarm/mini2440/mini2440.c
create mode 100644 board/friendlyarm/mini2440/mini2440.h
create mode 100644 doc/README.mini2440
create mode 100644 include/configs/mini2440.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 708ded7..2611fb5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -566,6 +566,10 @@ Unknown / orphaned boards:
# Board CPU #
#########################################################################
+Gabriel HUAU <contact@huau-gabriel.fr>
+
+ mini2440 s3c2440
+
Albert ARIBAUD <albert.u.boot@aribaud.net>
edminiv2 ARM926EJS (Orion5x SoC)
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 0000000..b88e569
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2012
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mini2440.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
new file mode 100644
index 0000000..bd726e7
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.c
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include "mini2440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void pll_delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+int board_early_init_f(void) {
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
+ clk_power->clkdivn = CLKDIVN_VAL;
+
+ /* configure UPLL */
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ /* some delay between MPLL and UPLL */
+ pll_delay(100);
+
+ /* configure MPLL */
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay(10000);
+
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* IOMUX Port H : UART Configuration */
+ gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
+ IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
+
+ gpio_direction_output(GPH8, 0);
+ gpio_direction_output(GPH9, 0);
+ gpio_direction_output(GPH10, 0);
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct s3c24x0_memctl* memctl = s3c24x0_get_base_memctl();
+
+ /*
+ * Configuring bus width and timing
+ * Initialize clocks for each bank 0..5
+ * Bank 3 and 4 are used for DM9000
+ */
+ writel(BANK_CONF, &memctl->bwscon);
+ writel(B0_CONF, &memctl->bankcon[0]);
+ writel(B1_CONF, &memctl->bankcon[1]);
+ writel(B2_CONF, &memctl->bankcon[2]);
+ writel(B3_CONF, &memctl->bankcon[3]);
+ writel(B4_CONF, &memctl->bankcon[4]);
+ writel(B5_CONF, &memctl->bankcon[5]);
+
+ /* Bank 6 and 7 are used for DRAM */
+ writel(SDRAM_64MB, &memctl->bankcon[6]);
+ writel(SDRAM_64MB, &memctl->bankcon[7]);
+
+ writel(MEM_TIMING, &memctl->refresh);
+ writel(BANKSIZE_CONF, &memctl->banksize);
+ writel(B6_MRSR, &memctl->mrsrb6);
+ writel(B7_MRSR, &memctl->mrsrb7);;
+
+ gd->ram_size = get_ram_size((void*) CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ return dm9000_initialize(bis);
+#else
+ return 0;
+#endif
+}
diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
new file mode 100644
index 0000000..e33deeb
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.h
@@ -0,0 +1,144 @@
+#ifndef __MINI2440_BOARD_CONF_H__
+#define __MINI2440_BOARD_CONF_H__
+
+/* PLL Parameters */
+#define CLKDIVN_VAL 7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+
+/* BWSCON */
+#define DW8 0x0
+#define DW16 0x1
+#define DW32 0x2
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16 + WAIT + UBLB)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/*
+ * Bank Configuration
+ */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0 /* 0clk */
+#define B0_PMC 0x0 /* normal */
+
+#define B1_Tacs 0x0
+#define B1_Tcos 0x0
+#define B1_Tacc 0x7
+#define B1_Tcoh 0x0
+#define B1_Tah 0x0
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x3 /* 4clk */
+#define B3_Tacp 0x0
+#define B3_PMC 0x0
+
+#define B4_Tacs 0x0
+#define B4_Tcos 0x3
+#define B4_Tacc 0x7
+#define B4_Tcoh 0x1
+#define B4_Tah 0x3
+#define B4_Tacp 0x0
+#define B4_PMC 0x0
+
+#define B5_Tacs 0x0
+#define B5_Tcos 0x0
+#define B5_Tacc 0x7
+#define B5_Tcoh 0x0
+#define B5_Tah 0x0
+#define B5_Tacp 0x0
+#define B5_PMC 0x0
+
+/*
+ * SDRAM Configuration
+ */
+#define SDRAM_MT 0x3 /* SDRAM */
+#define SDRAM_Trcd 0x0 /* 2clk */
+#define SDRAM_SCAN_9 0x1 /* 9bit */
+#define SDRAM_SCAN_10 0x2 /* 10bit */
+
+#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+
+/*
+ * Refresh Parameter
+ */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x1 /* 3clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x0 /* unused */
+#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
+
+/*
+ * MRSR Parameter
+ */
+#define BL 0x0
+#define BT 0x0
+#define CL 0x3 /* 3 clocks */
+#define TM 0x0
+#define WBL 0x0
+
+/*
+ * BankSize Parameter
+ */
+#define BK76MAP 0x2 /* 128MB/128MB */
+#define SCLK_EN 0x1 /* SCLK active */
+#define SCKE_EN 0x1 /* SDRAM power down mode enable */
+#define BURST_EN 0x1 /* Burst enable */
+
+/*
+ * Register values
+ */
+#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
+ (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
+ (B7_BWSCON<<28)))
+
+#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + (B0_Tcoh<<6) + \
+ (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
+#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + (B1_Tcoh<<6) + \
+ (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
+#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + (B2_Tcoh<<6) + \
+ (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
+#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + (B3_Tcoh<<6) + \
+ (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
+#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + (B4_Tcoh<<6) + \
+ (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
+#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + (B5_Tcoh<<6) + \
+ (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
+
+#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + (Trc<<18) + \
+ (Tchr<<16) + REFCNT
+
+#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
+#define B6_MRSR (CL<<4)
+#define B7_MRSR (CL<<4)
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 3cf75c3..93eeb3c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -61,6 +61,7 @@ mx1ads arm arm920t - -
scb9328 arm arm920t - - imx
cm4008 arm arm920t - - ks8695
cm41xx arm arm920t - - ks8695
+mini2440 arm arm920t mini2440 friendlyarm s3c24x0
VCMA9 arm arm920t vcma9 mpl s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
omap1510inn arm arm925t - ti
diff --git a/doc/README.mini2440 b/doc/README.mini2440
new file mode 100644
index 0000000..311ca52
--- /dev/null
+++ b/doc/README.mini2440
@@ -0,0 +1,28 @@
+U-Boot for FriendlyARM Mini2440 (s3c2440)
+
+This file contains information for the port of U-Boot to FriendlyARM
+mini2440
+
+All information about the board can be found on :
+http://www.friendlyarm.net/products/mini2440
+
+To build u-boot : ./MAKEALL mini2440
+
+Overview :
+--------
+FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
+ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
+systems. It's a low cost board.
+
+Boot Methods :
+------------
+Mini2440 can boot from NOR or NAND.
+
+Build :
+-----
+./MAKEALL mini2440
+
+or
+
+make mini2440_config
+make
diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
new file mode 100644
index 0000000..7574146
--- /dev/null
+++ b/include/configs/mini2440.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009-2010
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * Configuation settings for the MINI2440 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_S3C2440_GPIO
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM920T /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
+#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
+#define CONFIG_MINI2440 /* on a MIN2440 Board */
+
+#define MACH_TYPE_MINI2440 1999
+#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
+
+/*
+ * We don't use lowlevel_init
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * input clock of PLL
+ */
+/* MINI2440 has 12.0000MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_DM9000
+#define CONFIG_DRIVER_DM9000_NO_EEPROM
+#define CONFIG_DM9000_BASE 0x20000300
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+4)
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1
+
+/*
+ * allow to overwrite serial and ethaddr
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_LONGHELP
+#define CONFIG_SYS_PROMPT "MINI2440 => "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x30000000
+#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x32000000
+
+/* boot parameters address */
+#define CONFIG_BOOT_PARAM_ADDR 0x30000100
+
+/*
+ * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
+ * it to wrap 100 times (total 1562500) to get 1 sec.
+ */
+#define CONFIG_SYS_HZ 1562500
+
+/*
+ * valid baudrates
+ */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CONFIG_SYS_FLASH_BASE 0x0
+
+/*
+ * Stack should be on the SRAM because
+ * DRAM is not init
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NOR FLASH organization
+ * Now uses the standard CFI interface
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE 0x0
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* 512 * 4096 sectors, or 32 * 64k blocks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_FLASH_SHOW_PROGRESS 1
+
+/*
+ * Config for NOR flash
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_MY_ENV_OFFSET 0x40000
+/* addr of environment */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
+/* 16k Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x4000
+
+/* ATAG configuration */
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v6] Add support for MINI2440 (s3c2440).
2012-04-30 11:11 ` [U-Boot] [PATCH 2/2 v6] " Gabriel Huau
@ 2012-04-30 12:29 ` Marek Vasut
0 siblings, 0 replies; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 12:29 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
I detect line over 80 in the configs/s3c2440.h-whatever file, but just visually,
so you might want to prove me wrong by running checkpatch ;-)
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
>
> ---
> Changes for v2:
> - Coding style cleanup
> - Remove unnecessary files modification
> - Remove unnecessary board configuration set
>
> Changes for v3:
> - Coding style cleanup
> - Move some macro definition from lowlevel_init.S
> to a new header
> - Remove some "magic bloat" with I/O board initialization
> - Add a pll_delay and replace loop by it
> - Somme cleanup in the configuration file
> - Cancel modifications on an SoC specific header
> - Add my name to copyright
>
> Changes for v4:
> - Move dram init to dram_init() instead low_levelinit
> - Remove u-boot env from configuration file and change
> the address of initial SP
> - Remove PLL init, now it's SoC specific
>
> Changes for v5:
> - Clean up configuration file
> - Add a MAINTAINERS entry
> - Add a README.mini2440 file
> - Use gpio/iomux interface in case of magic numbers
> - Use get_ram_size()
>
> Changes for v6:
> - Coding style cleanup
> - Remove some unused define in the board config
> ---
> MAINTAINERS | 4 +
> board/friendlyarm/mini2440/Makefile | 44 ++++++++
> board/friendlyarm/mini2440/mini2440.c | 132 +++++++++++++++++++++++
> board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.mini2440 | 28 +++++
> include/configs/mini2440.h | 186
> +++++++++++++++++++++++++++++++++ 7 files changed, 539 insertions(+)
> create mode 100644 board/friendlyarm/mini2440/Makefile
> create mode 100644 board/friendlyarm/mini2440/mini2440.c
> create mode 100644 board/friendlyarm/mini2440/mini2440.h
> create mode 100644 doc/README.mini2440
> create mode 100644 include/configs/mini2440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 708ded7..2611fb5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -566,6 +566,10 @@ Unknown / orphaned boards:
> # Board CPU #
> #########################################################################
>
> +Gabriel HUAU <contact@huau-gabriel.fr>
> +
> + mini2440 s3c2440
> +
> Albert ARIBAUD <albert.u.boot@aribaud.net>
>
> edminiv2 ARM926EJS (Orion5x SoC)
> diff --git a/board/friendlyarm/mini2440/Makefile
> b/board/friendlyarm/mini2440/Makefile new file mode 100644
> index 0000000..b88e569
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/Makefile
> @@ -0,0 +1,44 @@
> +#
> +# (C) Copyright 2012
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := mini2440.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/friendlyarm/mini2440/mini2440.c
> b/board/friendlyarm/mini2440/mini2440.c new file mode 100644
> index 0000000..bd726e7
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.c
> @@ -0,0 +1,132 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <netdev.h>
> +#include "mini2440.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static inline void pll_delay(unsigned long loops)
> +{
> + __asm__ volatile ("1:\n"
> + "subs %0, %1, #1\n"
> + "bne 1b":"=r" (loops):"0" (loops));
> +}
> +
> +int board_early_init_f(void) {
> + struct s3c24x0_clock_power * const clk_power =
> + s3c24x0_get_base_clock_power();
> +
> + /* to reduce PLL lock time, adjust the LOCKTIME register */
> + clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
> + clk_power->clkdivn = CLKDIVN_VAL;
> +
> + /* configure UPLL */
> + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
> + /* some delay between MPLL and UPLL */
> + pll_delay(100);
> +
> + /* configure MPLL */
> + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
> +
> + /* some delay between MPLL and UPLL */
> + pll_delay(10000);
> +
> + return 0;
> +}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
> +
> + /* IOMUX Port H : UART Configuration */
> + gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
> + IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 |
IOMUXH_RXD2;
> +
> + gpio_direction_output(GPH8, 0);
> + gpio_direction_output(GPH9, 0);
> + gpio_direction_output(GPH10, 0);
> +
> + /* adress of boot parameters */
> + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + struct s3c24x0_memctl* memctl = s3c24x0_get_base_memctl();
> +
> + /*
> + * Configuring bus width and timing
> + * Initialize clocks for each bank 0..5
> + * Bank 3 and 4 are used for DM9000
> + */
> + writel(BANK_CONF, &memctl->bwscon);
> + writel(B0_CONF, &memctl->bankcon[0]);
> + writel(B1_CONF, &memctl->bankcon[1]);
> + writel(B2_CONF, &memctl->bankcon[2]);
> + writel(B3_CONF, &memctl->bankcon[3]);
> + writel(B4_CONF, &memctl->bankcon[4]);
> + writel(B5_CONF, &memctl->bankcon[5]);
> +
> + /* Bank 6 and 7 are used for DRAM */
> + writel(SDRAM_64MB, &memctl->bankcon[6]);
> + writel(SDRAM_64MB, &memctl->bankcon[7]);
> +
> + writel(MEM_TIMING, &memctl->refresh);
> + writel(BANKSIZE_CONF, &memctl->banksize);
> + writel(B6_MRSR, &memctl->mrsrb6);
> + writel(B7_MRSR, &memctl->mrsrb7);;
> +
> + gd->ram_size = get_ram_size((void*) CONFIG_SYS_SDRAM_BASE,
> PHYS_SDRAM_SIZE); + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#ifdef CONFIG_DRIVER_DM9000
> + return dm9000_initialize(bis);
> +#else
> + return 0;
> +#endif
> +}
> diff --git a/board/friendlyarm/mini2440/mini2440.h
> b/board/friendlyarm/mini2440/mini2440.h new file mode 100644
> index 0000000..e33deeb
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.h
> @@ -0,0 +1,144 @@
> +#ifndef __MINI2440_BOARD_CONF_H__
> +#define __MINI2440_BOARD_CONF_H__
> +
> +/* PLL Parameters */
> +#define CLKDIVN_VAL 7
> +#define M_MDIV 0x7f
> +#define M_PDIV 0x2
> +#define M_SDIV 0x1
> +
> +#define U_M_MDIV 0x38
> +#define U_M_PDIV 0x2
> +#define U_M_SDIV 0x2
> +
> +/* BWSCON */
> +#define DW8 0x0
> +#define DW16 0x1
> +#define DW32 0x2
> +#define WAIT (0x1<<2)
> +#define UBLB (0x1<<3)
> +
> +#define B1_BWSCON (DW32)
> +#define B2_BWSCON (DW16)
> +#define B3_BWSCON (DW16 + WAIT + UBLB)
> +#define B4_BWSCON (DW16 + WAIT + UBLB)
> +#define B5_BWSCON (DW16)
> +#define B6_BWSCON (DW32)
> +#define B7_BWSCON (DW32)
> +
> +/*
> + * Bank Configuration
> + */
> +#define B0_Tacs 0x0 /* 0clk */
> +#define B0_Tcos 0x0 /* 0clk */
> +#define B0_Tacc 0x7 /* 14clk */
> +#define B0_Tcoh 0x0 /* 0clk */
> +#define B0_Tah 0x0 /* 0clk */
> +#define B0_Tacp 0x0 /* 0clk */
> +#define B0_PMC 0x0 /* normal */
> +
> +#define B1_Tacs 0x0
> +#define B1_Tcos 0x0
> +#define B1_Tacc 0x7
> +#define B1_Tcoh 0x0
> +#define B1_Tah 0x0
> +#define B1_Tacp 0x0
> +#define B1_PMC 0x0
> +
> +#define B2_Tacs 0x0
> +#define B2_Tcos 0x0
> +#define B2_Tacc 0x7
> +#define B2_Tcoh 0x0
> +#define B2_Tah 0x0
> +#define B2_Tacp 0x0
> +#define B2_PMC 0x0
> +
> +#define B3_Tacs 0x0
> +#define B3_Tcos 0x3 /* 4clk */
> +#define B3_Tacc 0x7
> +#define B3_Tcoh 0x1 /* 1clk */
> +#define B3_Tah 0x3 /* 4clk */
> +#define B3_Tacp 0x0
> +#define B3_PMC 0x0
> +
> +#define B4_Tacs 0x0
> +#define B4_Tcos 0x3
> +#define B4_Tacc 0x7
> +#define B4_Tcoh 0x1
> +#define B4_Tah 0x3
> +#define B4_Tacp 0x0
> +#define B4_PMC 0x0
> +
> +#define B5_Tacs 0x0
> +#define B5_Tcos 0x0
> +#define B5_Tacc 0x7
> +#define B5_Tcoh 0x0
> +#define B5_Tah 0x0
> +#define B5_Tacp 0x0
> +#define B5_PMC 0x0
> +
> +/*
> + * SDRAM Configuration
> + */
> +#define SDRAM_MT 0x3 /* SDRAM */
> +#define SDRAM_Trcd 0x0 /* 2clk */
> +#define SDRAM_SCAN_9 0x1 /* 9bit */
> +#define SDRAM_SCAN_10 0x2 /* 10bit */
> +
> +#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
> +
> +/*
> + * Refresh Parameter
> + */
> +#define REFEN 0x1 /* Refresh enable */
> +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
> +#define Trp 0x1 /* 3clk */
> +#define Trc 0x3 /* 7clk */
> +#define Tchr 0x0 /* unused */
> +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 +
1-10.37*100)
> */ +
> +/*
> + * MRSR Parameter
> + */
> +#define BL 0x0
> +#define BT 0x0
> +#define CL 0x3 /* 3 clocks */
> +#define TM 0x0
> +#define WBL 0x0
> +
> +/*
> + * BankSize Parameter
> + */
> +#define BK76MAP 0x2 /* 128MB/128MB */
> +#define SCLK_EN 0x1 /* SCLK active */
> +#define SCKE_EN 0x1 /* SDRAM power down mode enable */
> +#define BURST_EN 0x1 /* Burst enable */
> +
> +/*
> + * Register values
> + */
> +#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12)
> + \ + (B4_BWSCON<<16) + (B5_BWSCON<<20) +
(B6_BWSCON<<24) + \
> + (B7_BWSCON<<28)))
> +
> +#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) +
> (B0_Tcoh<<6) + \ + (B0_Tah<<4) + (B0_Tacp<<2) +
(B0_PMC))
> +#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) +
> (B1_Tcoh<<6) + \ + (B1_Tah<<4) + (B1_Tacp<<2) +
(B1_PMC))
> +#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) +
> (B2_Tcoh<<6) + \ + (B2_Tah<<4) + (B2_Tacp<<2) +
(B2_PMC))
> +#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) +
> (B3_Tcoh<<6) + \ + (B3_Tah<<4) + (B3_Tacp<<2) +
(B3_PMC))
> +#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) +
> (B4_Tcoh<<6) + \ + (B4_Tah<<4) + (B4_Tacp<<2) +
(B4_PMC))
> +#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) +
> (B5_Tcoh<<6) + \ + (B5_Tah<<4) + (B5_Tacp<<2) +
(B5_PMC))
> +
> +#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + (Trc<<18) + \
> + (Tchr<<16) + REFCNT
> +
> +#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) +
> (BURST_EN<<7) +#define B6_MRSR (CL<<4)
> +#define B7_MRSR (CL<<4)
> +
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 3cf75c3..93eeb3c 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -61,6 +61,7 @@ mx1ads arm arm920t -
> - scb9328 arm arm920t -
> - imx cm4008 arm
> arm920t - - ks8695 cm41xx
> arm arm920t - - ks8695
> +mini2440 arm arm920t mini2440
> friendlyarm s3c24x0 VCMA9 arm arm920t
> vcma9 mpl s3c24x0 smdk2410
> arm arm920t - samsung s3c24x0
> omap1510inn arm arm925t -
> ti diff --git a/doc/README.mini2440 b/doc/README.mini2440
> new file mode 100644
> index 0000000..311ca52
> --- /dev/null
> +++ b/doc/README.mini2440
> @@ -0,0 +1,28 @@
> +U-Boot for FriendlyARM Mini2440 (s3c2440)
> +
> +This file contains information for the port of U-Boot to FriendlyARM
> +mini2440
> +
> +All information about the board can be found on :
> +http://www.friendlyarm.net/products/mini2440
> +
> +To build u-boot : ./MAKEALL mini2440
> +
> +Overview :
> +--------
> +FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung
> S3C2440 +ARM9 processor. The board measures 100 x 100 mm, ideal for
> learning about ARM9 +systems. It's a low cost board.
> +
> +Boot Methods :
> +------------
> +Mini2440 can boot from NOR or NAND.
> +
> +Build :
> +-----
> +./MAKEALL mini2440
> +
> +or
> +
> +make mini2440_config
> +make
> diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
> new file mode 100644
> index 0000000..7574146
> --- /dev/null
> +++ b/include/configs/mini2440.h
> @@ -0,0 +1,186 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + * Gary Jennejohn <gj@denx.de>
> + * David Mueller <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009-2010
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * Configuation settings for the MINI2440 board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_SYS_TEXT_BASE 0x0
> +#define CONFIG_S3C2440_GPIO
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARM920T /* This is an ARM920T Core
*/
> +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
> +#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
> +#define CONFIG_MINI2440 /* on a MIN2440 Board */
> +
> +#define MACH_TYPE_MINI2440 1999
> +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
> +
> +/*
> + * We don't use lowlevel_init
> + */
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +/*
> + * input clock of PLL
> + */
> +/* MINI2440 has 12.0000MHz input clock */
> +#define CONFIG_SYS_CLK_FREQ 12000000
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_DRIVER_DM9000
> +#define CONFIG_DRIVER_DM9000_NO_EEPROM
> +#define CONFIG_DM9000_BASE 0x20000300
> +#define DM9000_IO CONFIG_DM9000_BASE
> +#define DM9000_DATA (CONFIG_DM9000_BASE+4)
> +
> +/*
> + * select serial console configuration
> + */
> +#define CONFIG_S3C24X0_SERIAL
> +#define CONFIG_SERIAL1
> +
> +/*
> + * allow to overwrite serial and ethaddr
> + */
> +#define CONFIG_ENV_OVERWRITE
> +
> +/*
> + * Command definition
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PORTIO
> +#define CONFIG_CMD_REGINFO
> +#define CONFIG_CMD_SAVES
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_LONGHELP
> +#define CONFIG_SYS_PROMPT "MINI2440 => "
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16
> ) +#define CONFIG_SYS_MAXARGS 32
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START 0x30000000
> +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM
*/
> +
> +/* default load address */
> +#define CONFIG_SYS_LOAD_ADDR 0x32000000
> +
> +/* boot parameters address */
> +#define CONFIG_BOOT_PARAM_ADDR 0x30000100
> +
> +/*
> + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
> + * it to wrap 100 times (total 1562500) to get 1 sec.
> + */
> +#define CONFIG_SYS_HZ 1562500
> +
> +/*
> + * valid baudrates
> + */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +#define CONFIG_BAUDRATE 115200
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
> +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> +#endif
> +
> +/*
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM
> */ +#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
> +#define CONFIG_SYS_SDRAM_BASE 0x30000000
> +#define CONFIG_SYS_FLASH_BASE 0x0
> +
> +/*
> + * Stack should be on the SRAM because
> + * DRAM is not init
> + */
> +#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 -
GENERATED_GBL_DATA_SIZE)
> +
> +/*
> + * NOR FLASH organization
> + * Now uses the standard CFI interface
> + * FLASH and environment organization
> + */
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> +#define CONFIG_SYS_MONITOR_BASE 0x0
> +/* max number of memory banks */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +/* 512 * 4096 sectors, or 32 * 64k blocks */
> +#define CONFIG_SYS_MAX_FLASH_SECT 512
> +#define CONFIG_FLASH_SHOW_PROGRESS 1
> +
> +/*
> + * Config for NOR flash
> + */
> +#define CONFIG_ENV_IS_IN_FLASH
> +#define CONFIG_MY_ENV_OFFSET 0x40000
> +/* addr of environment */
> +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE +
CONFIG_MY_ENV_OFFSET)
> +/* 16k Total Size of Environment Sector */
> +#define CONFIG_ENV_SIZE 0x4000
> +
> +/* ATAG configuration */
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_AUTO_COMPLETE
> +
> +#endif /* __CONFIG_H */
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (6 preceding siblings ...)
2012-04-30 11:11 ` [U-Boot] [PATCH 2/2 v6] " Gabriel Huau
@ 2012-04-30 13:16 ` Gabriel Huau
2012-04-30 13:16 ` [U-Boot] [PATCH 2/2 v7] Add support for MINI2440 (s3c2440) Gabriel Huau
2012-04-30 13:20 ` [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440 Marek Vasut
2012-04-30 13:38 ` [U-Boot] [PATCH 2/2 v8] Add support for MINI2440 (s3c2440) Gabriel Huau
` (5 subsequent siblings)
13 siblings, 2 replies; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 13:16 UTC (permalink / raw)
To: u-boot
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
Changes for v2:
- Modification of the coding style
- Add my email address to copyright
- Remove a typedef
- Move some defines to driver file
Changes for v3:
- Cleanup coding style
- Changement of the commit message
arch/arm/include/asm/arch-s3c24x0/gpio.h | 171 ++++++++++++++++++++++++
arch/arm/include/asm/arch-s3c24x0/iomux.h | 200 +++++++++++++++++++++++++++++
drivers/gpio/Makefile | 1 +
drivers/gpio/s3c2440_gpio.c | 94 ++++++++++++++
4 files changed, 466 insertions(+)
create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
create mode 100644 drivers/gpio/s3c2440_gpio.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 0000000..76bc52c
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 0000000..cc22de7
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_IOMUX_H_
+#define _S3C24X0_IOMUX_H_
+
+enum s3c2440_iomux_func {
+ /* PORT A */
+ IOMUXA_ADDR0 = 1,
+ IOMUXA_ADDR16 = (1 << 1),
+ IOMUXA_ADDR17 = (1 << 2),
+ IOMUXA_ADDR18 = (1 << 3),
+ IOMUXA_ADDR19 = (1 << 4),
+ IOMUXA_ADDR20 = (1 << 5),
+ IOMUXA_ADDR21 = (1 << 6),
+ IOMUXA_ADDR22 = (1 << 7),
+ IOMUXA_ADDR23 = (1 << 8),
+ IOMUXA_ADDR24 = (1 << 9),
+ IOMUXA_ADDR25 = (1 << 10),
+ IOMUXA_ADDR26 = (1 << 11),
+ IOMUXA_nGCS1 = (1 << 12),
+ IOMUXA_nGCS2 = (1 << 13),
+ IOMUXA_nGCS3 = (1 << 14),
+ IOMUXA_nGCS4 = (1 << 15),
+ IOMUXA_nGCS5 = (1 << 16),
+ IOMUXA_CLE = (1 << 17),
+ IOMUXA_ALE = (1 << 18),
+ IOMUXA_nFWE = (1 << 19),
+ IOMUXA_nFRE = (1 << 20),
+ IOMUXA_nRSTOUT = (1 << 21),
+ IOMUXA_nFCE = (1 << 22),
+
+ /* PORT B */
+ IOMUXB_nXDREQ0 = (2 << 20),
+ IOMUXB_nXDACK0 = (2 << 18),
+ IOMUXB_nXDREQ1 = (2 << 16),
+ IOMUXB_nXDACK1 = (2 << 14),
+ IOMUXB_nXBREQ = (2 << 12),
+ IOMUXB_nXBACK = (2 << 10),
+ IOMUXB_TCLK0 = (2 << 8),
+ IOMUXB_TOUT3 = (2 << 6),
+ IOMUXB_TOUT2 = (2 << 4),
+ IOMUXB_TOUT1 = (2 << 2),
+ IOMUXB_TOUT0 = 2,
+
+ /* PORT C */
+ IOMUXC_VS7 = (2 << 30),
+ IOMUXC_VS6 = (2 << 28),
+ IOMUXC_VS5 = (2 << 26),
+ IOMUXC_VS4 = (2 << 24),
+ IOMUXC_VS3 = (2 << 22),
+ IOMUXC_VS2 = (2 << 20),
+ IOMUXC_VS1 = (2 << 18),
+ IOMUXC_VS0 = (2 << 16),
+ IOMUXC_LCD_LPCREVB = (2 << 14),
+ IOMUXC_LCD_LPCREV = (2 << 12),
+ IOMUXC_LCD_LPCOE = (2 << 10),
+ IOMUXC_VM = (2 << 8),
+ IOMUXC_VFRAME = (2 << 6),
+ IOMUXC_VLINE = (2 << 4),
+ IOMUXC_VCLK = (2 << 2),
+ IOMUXC_LEND = 2,
+ IOMUXC_I2SSDI = (3 << 8),
+
+ /* PORT D */
+ IOMUXD_VS23 = (2 << 30),
+ IOMUXD_VS22 = (2 << 28),
+ IOMUXD_VS21 = (2 << 26),
+ IOMUXD_VS20 = (2 << 24),
+ IOMUXD_VS19 = (2 << 22),
+ IOMUXD_VS18 = (2 << 20),
+ IOMUXD_VS17 = (2 << 18),
+ IOMUXD_VS16 = (2 << 16),
+ IOMUXD_VS15 = (2 << 14),
+ IOMUXD_VS14 = (2 << 12),
+ IOMUXD_VS13 = (2 << 10),
+ IOMUXD_VS12 = (2 << 8),
+ IOMUXD_VS11 = (2 << 6),
+ IOMUXD_VS10 = (2 << 4),
+ IOMUXD_VS9 = (2 << 2),
+ IOMUXD_VS8 = 2,
+ IOMUXD_nSS0 = (3 << 30),
+ IOMUXD_nSS1 = (3 << 28),
+ IOMUXD_SPICLK1 = (3 << 20),
+ IOMUXD_SPIMOSI1 = (3 << 18),
+ IOMUXD_SPIMISO1 = (3 << 16),
+
+ /* PORT E */
+ IOMUXE_IICSDA = (2 << 30),
+ IOMUXE_IICSCL = (2 << 28),
+ IOMUXE_SPICLK0 = (2 << 26),
+ IOMUXE_SPIMOSI0 = (2 << 24),
+ IOMUXE_SPIMISO0 = (2 << 22),
+ IOMUXE_SDDAT3 = (2 << 20),
+ IOMUXE_SDDAT2 = (2 << 18),
+ IOMUXE_SDDAT1 = (2 << 16),
+ IOMUXE_SDDAT0 = (2 << 14),
+ IOMUXE_SDCMD = (2 << 12),
+ IOMUXE_SDCLK = (2 << 10),
+ IOMUXE_I2SDO = (2 << 8),
+ IOMUXE_I2SDI = (2 << 6),
+ IOMUXE_CDCLK = (2 << 4),
+ IOMUXE_I2SSCLK = (2 << 2),
+ IOMUXE_I2SLRCK = 2,
+ IOMUXE_AC_SDATA_OUT = (3 << 8),
+ IOMUXE_AC_SDATA_IN = (3 << 6),
+ IOMUXE_AC_nRESET = (3 << 4),
+ IOMUXE_AC_BIT_CLK = (3 << 2),
+ IOMUXE_AC_SYNC = 3,
+
+ /* PORT F */
+ IOMUXF_EINT7 = (2 << 14),
+ IOMUXF_EINT6 = (2 << 12),
+ IOMUXF_EINT5 = (2 << 10),
+ IOMUXF_EINT4 = (2 << 8),
+ IOMUXF_EINT3 = (2 << 6),
+ IOMUXF_EINT2 = (2 << 4),
+ IOMUXF_EINT1 = (2 << 2),
+ IOMUXF_EINT0 = 2,
+
+ /* PORT G */
+ IOMUXG_EINT23 = (2 << 30),
+ IOMUXG_EINT22 = (2 << 28),
+ IOMUXG_EINT21 = (2 << 26),
+ IOMUXG_EINT20 = (2 << 24),
+ IOMUXG_EINT19 = (2 << 22),
+ IOMUXG_EINT18 = (2 << 20),
+ IOMUXG_EINT17 = (2 << 18),
+ IOMUXG_EINT16 = (2 << 16),
+ IOMUXG_EINT15 = (2 << 14),
+ IOMUXG_EINT14 = (2 << 12),
+ IOMUXG_EINT13 = (2 << 10),
+ IOMUXG_EINT12 = (2 << 8),
+ IOMUXG_EINT11 = (2 << 6),
+ IOMUXG_EINT10 = (2 << 4),
+ IOMUXG_EINT9 = (2 << 2),
+ IOMUXG_EINT8 = 2,
+ IOMUXG_TCLK1 = (3 << 22),
+ IOMUXG_nCTS1 = (3 << 20),
+ IOMUXG_nRTS1 = (3 << 18),
+ IOMUXG_SPICLK1 = (3 << 14),
+ IOMUXG_SPIMOSI1 = (3 << 12),
+ IOMUXG_SPIMISO1 = (3 << 10),
+ IOMUXG_LCD_PWRDN = (3 << 8),
+ IOMUXG_nSS1 = (3 << 6),
+ IOMUXG_nSS0 = (3 << 4),
+
+ /* PORT H */
+ IOMUXH_CLKOUT1 = (2 << 20),
+ IOMUXH_CLKOUT0 = (2 << 18),
+ IOMUXH_UEXTCLK = (2 << 16),
+ IOMUXH_RXD2 = (2 << 14),
+ IOMUXH_TXD2 = (2 << 12),
+ IOMUXH_RXD1 = (2 << 10),
+ IOMUXH_TXD1 = (2 << 8),
+ IOMUXH_RXD0 = (2 << 6),
+ IOMUXH_TXD0 = (2 << 4),
+ IOMUXH_nRTS0 = (2 << 2),
+ IOMUXH_nCTS0 = 2,
+ IOMUXH_nCTS1 = (3 << 14),
+ IOMUXH_nRTS1 = (3 << 12),
+
+ /* PORT J */
+ IOMUXJ_CAMRESET = (2 << 24),
+ IOMUXJ_CAMCLKOUT = (2 << 22),
+ IOMUXJ_CAMHREF = (2 << 20),
+ IOMUXJ_CAMVSYNC = (2 << 18),
+ IOMUXJ_CAMPCLK = (2 << 16),
+ IOMUXJ_CAMDATA7 = (2 << 14),
+ IOMUXJ_CAMDATA6 = (2 << 12),
+ IOMUXJ_CAMDATA5 = (2 << 10),
+ IOMUXJ_CAMDATA4 = (2 << 8),
+ IOMUXJ_CAMDATA3 = (2 << 6),
+ IOMUXJ_CAMDATA2 = (2 << 4),
+ IOMUXJ_CAMDATA1 = (2 << 2),
+ IOMUXJ_CAMDATA0 = 2
+};
+
+#endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb3b09a..7ae6f84 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
+COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
new file mode 100644
index 0000000..12a9043
--- /dev/null
+++ b/drivers/gpio/s3c2440_gpio.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+
+/* 0x4 means that we want DAT and not CON register */
+#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
+#define GPIO_BIT(x) ((x) & 0x3f)
+
+/*
+ * It's how we calculate the full port address
+ * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
+ * We move it at the second digit, and finally we add 0x4 because we want
+ * to modify GPIO DAT and not CON
+ */
+#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) << 1))
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+ unsigned port = GPIO_FULLPORT(gpio);
+
+ /*
+ * All GPIO Port have a configuration on
+ * 2 bits excepted the first GPIO (A) which
+ * have only 1 bit of configuration.
+ */
+ if (value)
+ if (!GPIO_PORT(gpio))
+ l |= (0x1 << GPIO_BIT(gpio));
+ else
+ l |= (0x3 << GPIO_BIT(gpio));
+ else
+ if (!GPIO_PORT(gpio))
+ l &= ~(0x1 << GPIO_BIT(gpio));
+ else
+ l &= ~(0x3 << GPIO_BIT(gpio));
+ return writel(port, l);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+
+ if (GPIO_PORT(gpio) == 0) /* PORT A */
+ return (l >> GPIO_BIT(gpio)) & 0x1;
+ return (l >> GPIO_BIT(gpio)) & 0x3;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
+ return gpio_set_value(gpio, value);
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v7] Add support for MINI2440 (s3c2440).
2012-04-30 13:16 ` [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-04-30 13:16 ` Gabriel Huau
2012-04-30 13:21 ` Marek Vasut
2012-04-30 13:20 ` [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440 Marek Vasut
1 sibling, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 13:16 UTC (permalink / raw)
To: u-boot
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
Changes for v2:
- Coding style cleanup
- Remove unnecessary files modification
- Remove unnecessary board configuration set
Changes for v3:
- Coding style cleanup
- Move some macro definition from lowlevel_init.S
to a new header
- Remove some "magic bloat" with I/O board initialization
- Add a pll_delay and replace loop by it
- Somme cleanup in the configuration file
- Cancel modifications on an SoC specific header
- Add my name to copyright
Changes for v4:
- Move dram init to dram_init() instead low_levelinit
- Remove u -boot env from configuration file and change
the address of initial SP
- Remove PLL init, now it's SoC specific
Changes for v5:
- Clean up configuration file
- Add a MAINTAINERS entry
- Add a README.mini2440 file
- Use gpio/iomux interface in case of magic numbers
- Use get_ram_size()
Changes for v6:
- Coding style cleanup
- Remove some unused define in the board config
Changes for v7:
- Cleanup coding style
- Changement of the commit message
MAINTAINERS | 4 +
board/friendlyarm/mini2440/Makefile | 44 ++++++++
board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++
board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.mini2440 | 28 +++++
include/configs/mini2440.h | 186 +++++++++++++++++++++++++++++++++
7 files changed, 541 insertions(+)
create mode 100644 board/friendlyarm/mini2440/Makefile
create mode 100644 board/friendlyarm/mini2440/mini2440.c
create mode 100644 board/friendlyarm/mini2440/mini2440.h
create mode 100644 doc/README.mini2440
create mode 100644 include/configs/mini2440.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 708ded7..2611fb5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -566,6 +566,10 @@ Unknown / orphaned boards:
# Board CPU #
#########################################################################
+Gabriel HUAU <contact@huau-gabriel.fr>
+
+ mini2440 s3c2440
+
Albert ARIBAUD <albert.u.boot@aribaud.net>
edminiv2 ARM926EJS (Orion5x SoC)
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 0000000..b88e569
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2012
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mini2440.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
new file mode 100644
index 0000000..e97d981
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include "mini2440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void pll_delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_early_init_f(void)
+{
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
+ clk_power->clkdivn = CLKDIVN_VAL;
+
+ /* configure UPLL */
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ /* some delay between MPLL and UPLL */
+ pll_delay(100);
+
+ /* configure MPLL */
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay(10000);
+
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* IOMUX Port H : UART Configuration */
+ gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
+ IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
+
+ gpio_direction_output(GPH8, 0);
+ gpio_direction_output(GPH9, 0);
+ gpio_direction_output(GPH10, 0);
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
+
+ /*
+ * Configuring bus width and timing
+ * Initialize clocks for each bank 0..5
+ * Bank 3 and 4 are used for DM9000
+ */
+ writel(BANK_CONF, &memctl->bwscon);
+ writel(B0_CONF, &memctl->bankcon[0]);
+ writel(B1_CONF, &memctl->bankcon[1]);
+ writel(B2_CONF, &memctl->bankcon[2]);
+ writel(B3_CONF, &memctl->bankcon[3]);
+ writel(B4_CONF, &memctl->bankcon[4]);
+ writel(B5_CONF, &memctl->bankcon[5]);
+
+ /* Bank 6 and 7 are used for DRAM */
+ writel(SDRAM_64MB, &memctl->bankcon[6]);
+ writel(SDRAM_64MB, &memctl->bankcon[7]);
+
+ writel(MEM_TIMING, &memctl->refresh);
+ writel(BANKSIZE_CONF, &memctl->banksize);
+ writel(B6_MRSR, &memctl->mrsrb6);
+ writel(B7_MRSR, &memctl->mrsrb7);
+
+ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ return dm9000_initialize(bis);
+#else
+ return 0;
+#endif
+}
diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
new file mode 100644
index 0000000..db386ea
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.h
@@ -0,0 +1,144 @@
+#ifndef __MINI2440_BOARD_CONF_H__
+#define __MINI2440_BOARD_CONF_H__
+
+/* PLL Parameters */
+#define CLKDIVN_VAL 7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+
+/* BWSCON */
+#define DW8 0x0
+#define DW16 0x1
+#define DW32 0x2
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16 + WAIT + UBLB)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/*
+ * Bank Configuration
+ */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0 /* 0clk */
+#define B0_PMC 0x0 /* normal */
+
+#define B1_Tacs 0x0
+#define B1_Tcos 0x0
+#define B1_Tacc 0x7
+#define B1_Tcoh 0x0
+#define B1_Tah 0x0
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x3 /* 4clk */
+#define B3_Tacp 0x0
+#define B3_PMC 0x0
+
+#define B4_Tacs 0x0
+#define B4_Tcos 0x3
+#define B4_Tacc 0x7
+#define B4_Tcoh 0x1
+#define B4_Tah 0x3
+#define B4_Tacp 0x0
+#define B4_PMC 0x0
+
+#define B5_Tacs 0x0
+#define B5_Tcos 0x0
+#define B5_Tacc 0x7
+#define B5_Tcoh 0x0
+#define B5_Tah 0x0
+#define B5_Tacp 0x0
+#define B5_PMC 0x0
+
+/*
+ * SDRAM Configuration
+ */
+#define SDRAM_MT 0x3 /* SDRAM */
+#define SDRAM_Trcd 0x0 /* 2clk */
+#define SDRAM_SCAN_9 0x1 /* 9bit */
+#define SDRAM_SCAN_10 0x2 /* 10bit */
+
+#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+
+/*
+ * Refresh Parameter
+ */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x1 /* 3clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x0 /* unused */
+#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
+
+/*
+ * MRSR Parameter
+ */
+#define BL 0x0
+#define BT 0x0
+#define CL 0x3 /* 3 clocks */
+#define TM 0x0
+#define WBL 0x0
+
+/*
+ * BankSize Parameter
+ */
+#define BK76MAP 0x2 /* 128MB/128MB */
+#define SCLK_EN 0x1 /* SCLK active */
+#define SCKE_EN 0x1 /* SDRAM power down mode enable */
+#define BURST_EN 0x1 /* Burst enable */
+
+/*
+ * Register values
+ */
+#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
+ (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
+ (B7_BWSCON<<28)))
+
+#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
+ (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
+#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
+ (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
+#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
+ (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
+#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
+ (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
+#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
+ (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
+#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
+ (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
+
+#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
+ (Trc<<18) + (Tchr<<16) + REFCNT
+
+#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
+#define B6_MRSR (CL<<4)
+#define B7_MRSR (CL<<4)
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 3cf75c3..93eeb3c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -61,6 +61,7 @@ mx1ads arm arm920t - -
scb9328 arm arm920t - - imx
cm4008 arm arm920t - - ks8695
cm41xx arm arm920t - - ks8695
+mini2440 arm arm920t mini2440 friendlyarm s3c24x0
VCMA9 arm arm920t vcma9 mpl s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
omap1510inn arm arm925t - ti
diff --git a/doc/README.mini2440 b/doc/README.mini2440
new file mode 100644
index 0000000..311ca52
--- /dev/null
+++ b/doc/README.mini2440
@@ -0,0 +1,28 @@
+U-Boot for FriendlyARM Mini2440 (s3c2440)
+
+This file contains information for the port of U-Boot to FriendlyARM
+mini2440
+
+All information about the board can be found on :
+http://www.friendlyarm.net/products/mini2440
+
+To build u-boot : ./MAKEALL mini2440
+
+Overview :
+--------
+FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
+ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
+systems. It's a low cost board.
+
+Boot Methods :
+------------
+Mini2440 can boot from NOR or NAND.
+
+Build :
+-----
+./MAKEALL mini2440
+
+or
+
+make mini2440_config
+make
diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
new file mode 100644
index 0000000..fa7987c
--- /dev/null
+++ b/include/configs/mini2440.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009-2010
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * Configuation settings for the MINI2440 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_S3C2440_GPIO
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM920T /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
+#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
+#define CONFIG_MINI2440 /* on a MIN2440 Board */
+
+#define MACH_TYPE_MINI2440 1999
+#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
+
+/*
+ * We don't use lowlevel_init
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * input clock of PLL
+ */
+/* MINI2440 has 12.0000MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_DM9000
+#define CONFIG_DRIVER_DM9000_NO_EEPROM
+#define CONFIG_DM9000_BASE 0x20000300
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+4)
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1
+
+/*
+ * allow to overwrite serial and ethaddr
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_LONGHELP
+#define CONFIG_SYS_PROMPT "MINI2440 => "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x30000000
+#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x32000000
+
+/* boot parameters address */
+#define CONFIG_BOOT_PARAM_ADDR 0x30000100
+
+/*
+ * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
+ * it to wrap 100 times (total 1562500) to get 1 sec.
+ */
+#define CONFIG_SYS_HZ 1562500
+
+/*
+ * valid baudrates
+ */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CONFIG_SYS_FLASH_BASE 0x0
+
+/*
+ * Stack should be on the SRAM because
+ * DRAM is not init
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NOR FLASH organization
+ * Now uses the standard CFI interface
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE 0x0
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* 512 * 4096 sectors, or 32 * 64k blocks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_FLASH_SHOW_PROGRESS 1
+
+/*
+ * Config for NOR flash
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_MY_ENV_OFFSET 0x40000
+/* addr of environment */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
+/* 16k Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x4000
+
+/* ATAG configuration */
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v7] Add support for MINI2440 (s3c2440).
2012-04-30 13:16 ` [U-Boot] [PATCH 2/2 v7] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-30 13:21 ` Marek Vasut
2012-04-30 13:31 ` Gabriel Huau
0 siblings, 1 reply; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 13:21 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> Changes for v2:
> - Coding style cleanup
> - Remove unnecessary files modification
> - Remove unnecessary board configuration set
>
> Changes for v3:
> - Coding style cleanup
> - Move some macro definition from lowlevel_init.S
> to a new header
> - Remove some "magic bloat" with I/O board initialization
> - Add a pll_delay and replace loop by it
> - Somme cleanup in the configuration file
> - Cancel modifications on an SoC specific header
> - Add my name to copyright
>
> Changes for v4:
> - Move dram init to dram_init() instead low_levelinit
> - Remove u -boot env from configuration file and change
> the address of initial SP
> - Remove PLL init, now it's SoC specific
>
> Changes for v5:
> - Clean up configuration file
> - Add a MAINTAINERS entry
> - Add a README.mini2440 file
> - Use gpio/iomux interface in case of magic numbers
> - Use get_ram_size()
>
> Changes for v6:
> - Coding style cleanup
> - Remove some unused define in the board config
>
> Changes for v7:
> - Cleanup coding style
> - Changement of the commit message
>
> MAINTAINERS | 4 +
> board/friendlyarm/mini2440/Makefile | 44 ++++++++
> board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++
> board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.mini2440 | 28 +++++
> include/configs/mini2440.h | 186
> +++++++++++++++++++++++++++++++++ 7 files changed, 541 insertions(+)
> create mode 100644 board/friendlyarm/mini2440/Makefile
> create mode 100644 board/friendlyarm/mini2440/mini2440.c
> create mode 100644 board/friendlyarm/mini2440/mini2440.h
> create mode 100644 doc/README.mini2440
> create mode 100644 include/configs/mini2440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 708ded7..2611fb5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -566,6 +566,10 @@ Unknown / orphaned boards:
> # Board CPU #
> #########################################################################
>
> +Gabriel HUAU <contact@huau-gabriel.fr>
> +
> + mini2440 s3c2440
> +
> Albert ARIBAUD <albert.u.boot@aribaud.net>
>
> edminiv2 ARM926EJS (Orion5x SoC)
> diff --git a/board/friendlyarm/mini2440/Makefile
> b/board/friendlyarm/mini2440/Makefile new file mode 100644
> index 0000000..b88e569
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/Makefile
> @@ -0,0 +1,44 @@
> +#
> +# (C) Copyright 2012
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := mini2440.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/friendlyarm/mini2440/mini2440.c
> b/board/friendlyarm/mini2440/mini2440.c new file mode 100644
> index 0000000..e97d981
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.c
> @@ -0,0 +1,134 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <netdev.h>
> +#include "mini2440.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static inline void pll_delay(unsigned long loops)
> +{
> + __asm__ volatile ("1:\n"
> + "subs %0, %1, #1\n"
> + "bne 1b" : "=r" (loops) : "0" (loops));
> +}
> +
> +int board_early_init_f(void)
> +{
> + struct s3c24x0_clock_power * const clk_power =
> + s3c24x0_get_base_clock_power();
> +
> + /* to reduce PLL lock time, adjust the LOCKTIME register */
> + clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
> + clk_power->clkdivn = CLKDIVN_VAL;
> +
> + /* configure UPLL */
> + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
> + /* some delay between MPLL and UPLL */
> + pll_delay(100);
> +
> + /* configure MPLL */
> + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
> +
> + /* some delay between MPLL and UPLL */
> + pll_delay(10000);
> +
> + return 0;
> +}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
> +
> + /* IOMUX Port H : UART Configuration */
> + gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
> + IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
> +
> + gpio_direction_output(GPH8, 0);
> + gpio_direction_output(GPH9, 0);
> + gpio_direction_output(GPH10, 0);
> +
> + /* adress of boot parameters */
> + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
> +
> + /*
> + * Configuring bus width and timing
> + * Initialize clocks for each bank 0..5
> + * Bank 3 and 4 are used for DM9000
> + */
> + writel(BANK_CONF, &memctl->bwscon);
> + writel(B0_CONF, &memctl->bankcon[0]);
> + writel(B1_CONF, &memctl->bankcon[1]);
> + writel(B2_CONF, &memctl->bankcon[2]);
> + writel(B3_CONF, &memctl->bankcon[3]);
> + writel(B4_CONF, &memctl->bankcon[4]);
> + writel(B5_CONF, &memctl->bankcon[5]);
> +
> + /* Bank 6 and 7 are used for DRAM */
> + writel(SDRAM_64MB, &memctl->bankcon[6]);
> + writel(SDRAM_64MB, &memctl->bankcon[7]);
> +
> + writel(MEM_TIMING, &memctl->refresh);
> + writel(BANKSIZE_CONF, &memctl->banksize);
> + writel(B6_MRSR, &memctl->mrsrb6);
> + writel(B7_MRSR, &memctl->mrsrb7);
> +
> + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
> + PHYS_SDRAM_SIZE);
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#ifdef CONFIG_DRIVER_DM9000
> + return dm9000_initialize(bis);
> +#else
> + return 0;
> +#endif
> +}
> diff --git a/board/friendlyarm/mini2440/mini2440.h
> b/board/friendlyarm/mini2440/mini2440.h new file mode 100644
> index 0000000..db386ea
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.h
> @@ -0,0 +1,144 @@
> +#ifndef __MINI2440_BOARD_CONF_H__
> +#define __MINI2440_BOARD_CONF_H__
> +
> +/* PLL Parameters */
> +#define CLKDIVN_VAL 7
> +#define M_MDIV 0x7f
> +#define M_PDIV 0x2
> +#define M_SDIV 0x1
> +
> +#define U_M_MDIV 0x38
> +#define U_M_PDIV 0x2
> +#define U_M_SDIV 0x2
> +
> +/* BWSCON */
> +#define DW8 0x0
> +#define DW16 0x1
> +#define DW32 0x2
> +#define WAIT (0x1<<2)
> +#define UBLB (0x1<<3)
> +
> +#define B1_BWSCON (DW32)
> +#define B2_BWSCON (DW16)
> +#define B3_BWSCON (DW16 + WAIT + UBLB)
> +#define B4_BWSCON (DW16 + WAIT + UBLB)
> +#define B5_BWSCON (DW16)
> +#define B6_BWSCON (DW32)
> +#define B7_BWSCON (DW32)
> +
> +/*
> + * Bank Configuration
> + */
> +#define B0_Tacs 0x0 /* 0clk */
> +#define B0_Tcos 0x0 /* 0clk */
> +#define B0_Tacc 0x7 /* 14clk */
> +#define B0_Tcoh 0x0 /* 0clk */
> +#define B0_Tah 0x0 /* 0clk */
> +#define B0_Tacp 0x0 /* 0clk */
> +#define B0_PMC 0x0 /* normal */
> +
> +#define B1_Tacs 0x0
> +#define B1_Tcos 0x0
> +#define B1_Tacc 0x7
> +#define B1_Tcoh 0x0
> +#define B1_Tah 0x0
> +#define B1_Tacp 0x0
> +#define B1_PMC 0x0
> +
> +#define B2_Tacs 0x0
> +#define B2_Tcos 0x0
> +#define B2_Tacc 0x7
> +#define B2_Tcoh 0x0
> +#define B2_Tah 0x0
> +#define B2_Tacp 0x0
> +#define B2_PMC 0x0
> +
> +#define B3_Tacs 0x0
> +#define B3_Tcos 0x3 /* 4clk */
> +#define B3_Tacc 0x7
> +#define B3_Tcoh 0x1 /* 1clk */
> +#define B3_Tah 0x3 /* 4clk */
> +#define B3_Tacp 0x0
> +#define B3_PMC 0x0
> +
> +#define B4_Tacs 0x0
> +#define B4_Tcos 0x3
> +#define B4_Tacc 0x7
> +#define B4_Tcoh 0x1
> +#define B4_Tah 0x3
> +#define B4_Tacp 0x0
> +#define B4_PMC 0x0
> +
> +#define B5_Tacs 0x0
> +#define B5_Tcos 0x0
> +#define B5_Tacc 0x7
> +#define B5_Tcoh 0x0
> +#define B5_Tah 0x0
> +#define B5_Tacp 0x0
> +#define B5_PMC 0x0
> +
> +/*
> + * SDRAM Configuration
> + */
> +#define SDRAM_MT 0x3 /* SDRAM */
> +#define SDRAM_Trcd 0x0 /* 2clk */
> +#define SDRAM_SCAN_9 0x1 /* 9bit */
> +#define SDRAM_SCAN_10 0x2 /* 10bit */
> +
> +#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
> +
> +/*
> + * Refresh Parameter
> + */
> +#define REFEN 0x1 /* Refresh enable */
> +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
> +#define Trp 0x1 /* 3clk */
> +#define Trc 0x3 /* 7clk */
> +#define Tchr 0x0 /* unused */
> +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 +
1-10.37*100)
> */ +
> +/*
> + * MRSR Parameter
> + */
> +#define BL 0x0
> +#define BT 0x0
> +#define CL 0x3 /* 3 clocks */
> +#define TM 0x0
> +#define WBL 0x0
> +
> +/*
> + * BankSize Parameter
> + */
> +#define BK76MAP 0x2 /* 128MB/128MB */
> +#define SCLK_EN 0x1 /* SCLK active */
> +#define SCKE_EN 0x1 /* SDRAM power down mode enable */
> +#define BURST_EN 0x1 /* Burst enable */
> +
> +/*
> + * Register values
> + */
> +#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12)
> + \ + (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
> + (B7_BWSCON<<28)))
> +
> +#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
> + (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
> +#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
> + (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
> +#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
> + (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
> +#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
> + (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
> +#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
> + (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
> +#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
> + (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
> +
> +#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
> + (Trc<<18) + (Tchr<<16) + REFCNT
> +
> +#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) +
> (BURST_EN<<7) +#define B6_MRSR (CL<<4)
> +#define B7_MRSR (CL<<4)
> +
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 3cf75c3..93eeb3c 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -61,6 +61,7 @@ mx1ads arm arm920t -
> - scb9328 arm arm920t -
> - imx cm4008 arm
> arm920t - - ks8695 cm41xx
> arm arm920t - - ks8695
> +mini2440 arm arm920t mini2440
> friendlyarm s3c24x0 VCMA9 arm arm920t
> vcma9 mpl s3c24x0 smdk2410
> arm arm920t - samsung s3c24x0
> omap1510inn arm arm925t -
> ti diff --git a/doc/README.mini2440 b/doc/README.mini2440
> new file mode 100644
> index 0000000..311ca52
> --- /dev/null
> +++ b/doc/README.mini2440
> @@ -0,0 +1,28 @@
> +U-Boot for FriendlyARM Mini2440 (s3c2440)
> +
> +This file contains information for the port of U-Boot to FriendlyARM
> +mini2440
> +
> +All information about the board can be found on :
> +http://www.friendlyarm.net/products/mini2440
> +
> +To build u-boot : ./MAKEALL mini2440
> +
> +Overview :
> +--------
> +FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung
> S3C2440 +ARM9 processor. The board measures 100 x 100 mm, ideal for
> learning about ARM9 +systems. It's a low cost board.
> +
> +Boot Methods :
> +------------
> +Mini2440 can boot from NOR or NAND.
> +
> +Build :
> +-----
> +./MAKEALL mini2440
> +
> +or
> +
> +make mini2440_config
> +make
> diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
> new file mode 100644
> index 0000000..fa7987c
> --- /dev/null
> +++ b/include/configs/mini2440.h
> @@ -0,0 +1,186 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + * Gary Jennejohn <gj@denx.de>
> + * David Mueller <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009-2010
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * Configuation settings for the MINI2440 board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_SYS_TEXT_BASE 0x0
> +#define CONFIG_S3C2440_GPIO
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARM920T /* This is an ARM920T Core
*/
> +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
> +#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
> +#define CONFIG_MINI2440 /* on a MIN2440 Board */
> +
> +#define MACH_TYPE_MINI2440 1999
> +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
> +
> +/*
> + * We don't use lowlevel_init
> + */
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +/*
> + * input clock of PLL
> + */
> +/* MINI2440 has 12.0000MHz input clock */
> +#define CONFIG_SYS_CLK_FREQ 12000000
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_DRIVER_DM9000
> +#define CONFIG_DRIVER_DM9000_NO_EEPROM
> +#define CONFIG_DM9000_BASE 0x20000300
> +#define DM9000_IO CONFIG_DM9000_BASE
> +#define DM9000_DATA (CONFIG_DM9000_BASE+4)
> +
> +/*
> + * select serial console configuration
> + */
> +#define CONFIG_S3C24X0_SERIAL
> +#define CONFIG_SERIAL1
> +
> +/*
> + * allow to overwrite serial and ethaddr
> + */
> +#define CONFIG_ENV_OVERWRITE
> +
> +/*
> + * Command definition
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PORTIO
> +#define CONFIG_CMD_REGINFO
> +#define CONFIG_CMD_SAVES
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_LONGHELP
> +#define CONFIG_SYS_PROMPT "MINI2440 => "
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> +#define CONFIG_SYS_MAXARGS 32
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define[tab] mixed with #define[space] ... also, please Cc Albert Aribaud for
the next round, he'll likely pick this up.
> +
> +#define CONFIG_SYS_MEMTEST_START 0x30000000
> +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM
*/
> +
> +/* default load address */
> +#define CONFIG_SYS_LOAD_ADDR 0x32000000
> +
> +/* boot parameters address */
> +#define CONFIG_BOOT_PARAM_ADDR 0x30000100
> +
> +/*
> + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
> + * it to wrap 100 times (total 1562500) to get 1 sec.
> + */
> +#define CONFIG_SYS_HZ 1562500
> +
> +/*
> + * valid baudrates
> + */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +#define CONFIG_BAUDRATE 115200
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
> +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> +#endif
> +
> +/*
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM
> */ +#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
> +#define CONFIG_SYS_SDRAM_BASE 0x30000000
> +#define CONFIG_SYS_FLASH_BASE 0x0
> +
> +/*
> + * Stack should be on the SRAM because
> + * DRAM is not init
> + */
> +#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 -
GENERATED_GBL_DATA_SIZE)
> +
> +/*
> + * NOR FLASH organization
> + * Now uses the standard CFI interface
> + * FLASH and environment organization
> + */
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> +#define CONFIG_SYS_MONITOR_BASE 0x0
> +/* max number of memory banks */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +/* 512 * 4096 sectors, or 32 * 64k blocks */
> +#define CONFIG_SYS_MAX_FLASH_SECT 512
> +#define CONFIG_FLASH_SHOW_PROGRESS 1
> +
> +/*
> + * Config for NOR flash
> + */
> +#define CONFIG_ENV_IS_IN_FLASH
> +#define CONFIG_MY_ENV_OFFSET 0x40000
> +/* addr of environment */
> +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE +
CONFIG_MY_ENV_OFFSET)
> +/* 16k Total Size of Environment Sector */
> +#define CONFIG_ENV_SIZE 0x4000
> +
> +/* ATAG configuration */
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_AUTO_COMPLETE
> +
> +#endif /* __CONFIG_H */
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v7] Add support for MINI2440 (s3c2440).
2012-04-30 13:21 ` Marek Vasut
@ 2012-04-30 13:31 ` Gabriel Huau
2012-04-30 13:49 ` Marek Vasut
0 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 13:31 UTC (permalink / raw)
To: u-boot
On Mon, Apr 30, 2012 at 03:21:49PM +0200, Marek Vasut wrote:
> Dear Gabriel Huau,
>
> > +
> > +/*
> > + * Miscellaneous configurable options
> > + */
> > +#define CONFIG_LONGHELP
> > +#define CONFIG_SYS_PROMPT "MINI2440 => "
> > +#define CONFIG_SYS_CBSIZE 256
> > +#define CONFIG_SYS_PBSIZE
> (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> > +#define CONFIG_SYS_MAXARGS 32
> > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
>
> #define[tab] mixed with #define[space] ... also, please Cc Albert Aribaud for
> the next round, he'll likely pick this up.
>
You gonna to kill me ... :P. checkpatch.pl didn't see this obfuscation
;).
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 2/2 v7] Add support for MINI2440 (s3c2440).
2012-04-30 13:31 ` Gabriel Huau
@ 2012-04-30 13:49 ` Marek Vasut
0 siblings, 0 replies; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 13:49 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> On Mon, Apr 30, 2012 at 03:21:49PM +0200, Marek Vasut wrote:
> > Dear Gabriel Huau,
> >
> > > +
> > > +/*
> > > + * Miscellaneous configurable options
> > > + */
> > > +#define CONFIG_LONGHELP
> > > +#define CONFIG_SYS_PROMPT "MINI2440 => "
> > > +#define CONFIG_SYS_CBSIZE 256
> > > +#define CONFIG_SYS_PBSIZE
> >
> > (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> >
> > > +#define CONFIG_SYS_MAXARGS 32
> > > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> >
> > #define[tab] mixed with #define[space] ... also, please Cc Albert Aribaud
> > for the next round, he'll likely pick this up.
>
> You gonna to kill me ... :P. checkpatch.pl didn't see this obfuscation
> ;).
Fix checkpatch or report it ... this might be a worthy addition.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-30 13:16 ` [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
2012-04-30 13:16 ` [U-Boot] [PATCH 2/2 v7] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-30 13:20 ` Marek Vasut
2012-04-30 13:29 ` Gabriel Huau
1 sibling, 1 reply; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 13:20 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> Changes for v2:
> - Modification of the coding style
> - Add my email address to copyright
> - Remove a typedef
> - Move some defines to driver file
>
> Changes for v3:
> - Cleanup coding style
> - Changement of the commit message
There is no commit message here ;-)
>
> arch/arm/include/asm/arch-s3c24x0/gpio.h | 171 ++++++++++++++++++++++++
> arch/arm/include/asm/arch-s3c24x0/iomux.h | 200
> +++++++++++++++++++++++++++++ drivers/gpio/Makefile |
> 1 +
> drivers/gpio/s3c2440_gpio.c | 94 ++++++++++++++
> 4 files changed, 466 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
> create mode 100644 drivers/gpio/s3c2440_gpio.c
>
> diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h
> b/arch/arm/include/asm/arch-s3c24x0/gpio.h new file mode 100644
> index 0000000..76bc52c
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
> @@ -0,0 +1,171 @@
> +/*
> + * Copyright (c) 2012.
> + *
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_GPIO_H_
> +#define _S3C24X0_GPIO_H_
> +
> +enum s3c2440_gpio {
> + GPA0,
> + GPA1,
> + GPA2,
> + GPA3,
> + GPA4,
> + GPA5,
> + GPA6,
> + GPA7,
> + GPA8,
> + GPA9,
> + GPA10,
> + GPA11,
> + GPA12,
> + GPA13,
> + GPA14,
> + GPA15,
> + GPA16,
> + GPA17,
> + GPA18,
> + GPA19,
> + GPA20,
> + GPA21,
> + GPA22,
> + GPA23,
> + GPA24,
> +
> + GPB0 = 32,
> + GPB1,
> + GPB2,
> + GPB3,
> + GPB4,
> + GPB5,
> + GPB6,
> + GPB7,
> + GPB8,
> + GPB9,
> + GPB10,
> +
> + GPC0 = 64,
> + GPC1,
> + GPC2,
> + GPC3,
> + GPC4,
> + GPC5,
> + GPC6,
> + GPC7,
> + GPC8,
> + GPC9,
> + GPC10,
> + GPC11,
> + GPC12,
> + GPC13,
> + GPC14,
> + GPC15,
> +
> + GPD0 = 96,
> + GPD1,
> + GPD2,
> + GPD3,
> + GPD4,
> + GPD5,
> + GPD6,
> + GPD7,
> + GPD8,
> + GPD9,
> + GPD10,
> + GPD11,
> + GPD12,
> + GPD13,
> + GPD14,
> + GPD15,
> +
> + GPE0 = 128,
> + GPE1,
> + GPE2,
> + GPE3,
> + GPE4,
> + GPE5,
> + GPE6,
> + GPE7,
> + GPE8,
> + GPE9,
> + GPE10,
> + GPE11,
> + GPE12,
> + GPE13,
> + GPE14,
> + GPE15,
> +
> + GPF0 = 160,
> + GPF1,
> + GPF2,
> + GPF3,
> + GPF4,
> + GPF5,
> + GPF6,
> + GPF7,
> +
> + GPG0 = 192,
> + GPG1,
> + GPG2,
> + GPG3,
> + GPG4,
> + GPG5,
> + GPG6,
> + GPG7,
> + GPG8,
> + GPG9,
> + GPG10,
> + GPG11,
> + GPG12,
> + GPG13,
> + GPG14,
> + GPG15,
> +
> + GPH0 = 224,
> + GPH1,
> + GPH2,
> + GPH3,
> + GPH4,
> + GPH5,
> + GPH6,
> + GPH7,
> + GPH8,
> + GPH9,
> + GPH10,
> +
> + GPJ0 = 256,
> + GPJ1,
> + GPJ2,
> + GPJ3,
> + GPJ4,
> + GPJ5,
> + GPJ6,
> + GPJ7,
> + GPJ8,
> + GPJ9,
> + GPJ10,
> + GPJ11,
> + GPJ12,
> +};
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h
> b/arch/arm/include/asm/arch-s3c24x0/iomux.h new file mode 100644
> index 0000000..cc22de7
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
> @@ -0,0 +1,200 @@
> +/*
> + * Copyright (c) 2012
> + *
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_IOMUX_H_
> +#define _S3C24X0_IOMUX_H_
> +
> +enum s3c2440_iomux_func {
> + /* PORT A */
> + IOMUXA_ADDR0 = 1,
> + IOMUXA_ADDR16 = (1 << 1),
> + IOMUXA_ADDR17 = (1 << 2),
> + IOMUXA_ADDR18 = (1 << 3),
> + IOMUXA_ADDR19 = (1 << 4),
> + IOMUXA_ADDR20 = (1 << 5),
> + IOMUXA_ADDR21 = (1 << 6),
> + IOMUXA_ADDR22 = (1 << 7),
> + IOMUXA_ADDR23 = (1 << 8),
> + IOMUXA_ADDR24 = (1 << 9),
> + IOMUXA_ADDR25 = (1 << 10),
> + IOMUXA_ADDR26 = (1 << 11),
> + IOMUXA_nGCS1 = (1 << 12),
> + IOMUXA_nGCS2 = (1 << 13),
> + IOMUXA_nGCS3 = (1 << 14),
> + IOMUXA_nGCS4 = (1 << 15),
> + IOMUXA_nGCS5 = (1 << 16),
> + IOMUXA_CLE = (1 << 17),
> + IOMUXA_ALE = (1 << 18),
> + IOMUXA_nFWE = (1 << 19),
> + IOMUXA_nFRE = (1 << 20),
> + IOMUXA_nRSTOUT = (1 << 21),
> + IOMUXA_nFCE = (1 << 22),
> +
> + /* PORT B */
> + IOMUXB_nXDREQ0 = (2 << 20),
> + IOMUXB_nXDACK0 = (2 << 18),
> + IOMUXB_nXDREQ1 = (2 << 16),
> + IOMUXB_nXDACK1 = (2 << 14),
> + IOMUXB_nXBREQ = (2 << 12),
> + IOMUXB_nXBACK = (2 << 10),
> + IOMUXB_TCLK0 = (2 << 8),
> + IOMUXB_TOUT3 = (2 << 6),
> + IOMUXB_TOUT2 = (2 << 4),
> + IOMUXB_TOUT1 = (2 << 2),
> + IOMUXB_TOUT0 = 2,
> +
> + /* PORT C */
> + IOMUXC_VS7 = (2 << 30),
> + IOMUXC_VS6 = (2 << 28),
> + IOMUXC_VS5 = (2 << 26),
> + IOMUXC_VS4 = (2 << 24),
> + IOMUXC_VS3 = (2 << 22),
> + IOMUXC_VS2 = (2 << 20),
> + IOMUXC_VS1 = (2 << 18),
> + IOMUXC_VS0 = (2 << 16),
> + IOMUXC_LCD_LPCREVB = (2 << 14),
> + IOMUXC_LCD_LPCREV = (2 << 12),
> + IOMUXC_LCD_LPCOE = (2 << 10),
> + IOMUXC_VM = (2 << 8),
> + IOMUXC_VFRAME = (2 << 6),
> + IOMUXC_VLINE = (2 << 4),
> + IOMUXC_VCLK = (2 << 2),
> + IOMUXC_LEND = 2,
> + IOMUXC_I2SSDI = (3 << 8),
> +
> + /* PORT D */
> + IOMUXD_VS23 = (2 << 30),
> + IOMUXD_VS22 = (2 << 28),
> + IOMUXD_VS21 = (2 << 26),
> + IOMUXD_VS20 = (2 << 24),
> + IOMUXD_VS19 = (2 << 22),
> + IOMUXD_VS18 = (2 << 20),
> + IOMUXD_VS17 = (2 << 18),
> + IOMUXD_VS16 = (2 << 16),
> + IOMUXD_VS15 = (2 << 14),
> + IOMUXD_VS14 = (2 << 12),
> + IOMUXD_VS13 = (2 << 10),
> + IOMUXD_VS12 = (2 << 8),
> + IOMUXD_VS11 = (2 << 6),
> + IOMUXD_VS10 = (2 << 4),
> + IOMUXD_VS9 = (2 << 2),
> + IOMUXD_VS8 = 2,
> + IOMUXD_nSS0 = (3 << 30),
> + IOMUXD_nSS1 = (3 << 28),
> + IOMUXD_SPICLK1 = (3 << 20),
> + IOMUXD_SPIMOSI1 = (3 << 18),
> + IOMUXD_SPIMISO1 = (3 << 16),
> +
> + /* PORT E */
> + IOMUXE_IICSDA = (2 << 30),
> + IOMUXE_IICSCL = (2 << 28),
> + IOMUXE_SPICLK0 = (2 << 26),
> + IOMUXE_SPIMOSI0 = (2 << 24),
> + IOMUXE_SPIMISO0 = (2 << 22),
> + IOMUXE_SDDAT3 = (2 << 20),
> + IOMUXE_SDDAT2 = (2 << 18),
> + IOMUXE_SDDAT1 = (2 << 16),
> + IOMUXE_SDDAT0 = (2 << 14),
> + IOMUXE_SDCMD = (2 << 12),
> + IOMUXE_SDCLK = (2 << 10),
> + IOMUXE_I2SDO = (2 << 8),
> + IOMUXE_I2SDI = (2 << 6),
> + IOMUXE_CDCLK = (2 << 4),
> + IOMUXE_I2SSCLK = (2 << 2),
> + IOMUXE_I2SLRCK = 2,
> + IOMUXE_AC_SDATA_OUT = (3 << 8),
> + IOMUXE_AC_SDATA_IN = (3 << 6),
> + IOMUXE_AC_nRESET = (3 << 4),
> + IOMUXE_AC_BIT_CLK = (3 << 2),
> + IOMUXE_AC_SYNC = 3,
> +
> + /* PORT F */
> + IOMUXF_EINT7 = (2 << 14),
> + IOMUXF_EINT6 = (2 << 12),
> + IOMUXF_EINT5 = (2 << 10),
> + IOMUXF_EINT4 = (2 << 8),
> + IOMUXF_EINT3 = (2 << 6),
> + IOMUXF_EINT2 = (2 << 4),
> + IOMUXF_EINT1 = (2 << 2),
> + IOMUXF_EINT0 = 2,
> +
> + /* PORT G */
> + IOMUXG_EINT23 = (2 << 30),
> + IOMUXG_EINT22 = (2 << 28),
> + IOMUXG_EINT21 = (2 << 26),
> + IOMUXG_EINT20 = (2 << 24),
> + IOMUXG_EINT19 = (2 << 22),
> + IOMUXG_EINT18 = (2 << 20),
> + IOMUXG_EINT17 = (2 << 18),
> + IOMUXG_EINT16 = (2 << 16),
> + IOMUXG_EINT15 = (2 << 14),
> + IOMUXG_EINT14 = (2 << 12),
> + IOMUXG_EINT13 = (2 << 10),
> + IOMUXG_EINT12 = (2 << 8),
> + IOMUXG_EINT11 = (2 << 6),
> + IOMUXG_EINT10 = (2 << 4),
> + IOMUXG_EINT9 = (2 << 2),
> + IOMUXG_EINT8 = 2,
> + IOMUXG_TCLK1 = (3 << 22),
> + IOMUXG_nCTS1 = (3 << 20),
> + IOMUXG_nRTS1 = (3 << 18),
> + IOMUXG_SPICLK1 = (3 << 14),
> + IOMUXG_SPIMOSI1 = (3 << 12),
> + IOMUXG_SPIMISO1 = (3 << 10),
> + IOMUXG_LCD_PWRDN = (3 << 8),
> + IOMUXG_nSS1 = (3 << 6),
> + IOMUXG_nSS0 = (3 << 4),
> +
> + /* PORT H */
> + IOMUXH_CLKOUT1 = (2 << 20),
> + IOMUXH_CLKOUT0 = (2 << 18),
> + IOMUXH_UEXTCLK = (2 << 16),
> + IOMUXH_RXD2 = (2 << 14),
> + IOMUXH_TXD2 = (2 << 12),
> + IOMUXH_RXD1 = (2 << 10),
> + IOMUXH_TXD1 = (2 << 8),
> + IOMUXH_RXD0 = (2 << 6),
> + IOMUXH_TXD0 = (2 << 4),
> + IOMUXH_nRTS0 = (2 << 2),
> + IOMUXH_nCTS0 = 2,
> + IOMUXH_nCTS1 = (3 << 14),
> + IOMUXH_nRTS1 = (3 << 12),
> +
> + /* PORT J */
> + IOMUXJ_CAMRESET = (2 << 24),
> + IOMUXJ_CAMCLKOUT = (2 << 22),
> + IOMUXJ_CAMHREF = (2 << 20),
> + IOMUXJ_CAMVSYNC = (2 << 18),
> + IOMUXJ_CAMPCLK = (2 << 16),
> + IOMUXJ_CAMDATA7 = (2 << 14),
> + IOMUXJ_CAMDATA6 = (2 << 12),
> + IOMUXJ_CAMDATA5 = (2 << 10),
> + IOMUXJ_CAMDATA4 = (2 << 8),
> + IOMUXJ_CAMDATA3 = (2 << 6),
> + IOMUXJ_CAMDATA2 = (2 << 4),
> + IOMUXJ_CAMDATA1 = (2 << 2),
> + IOMUXJ_CAMDATA0 = 2
> +};
> +
> +#endif
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index fb3b09a..7ae6f84 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
> COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
> COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
> COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
> +COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
>
> COBJS := $(COBJS-y)
> SRCS := $(COBJS:.o=.c)
> diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
> new file mode 100644
> index 0000000..12a9043
> --- /dev/null
> +++ b/drivers/gpio/s3c2440_gpio.c
> @@ -0,0 +1,94 @@
> +/*
> + * Copyright (C) 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +
> +#define GPIO_INPUT 0x0
> +#define GPIO_OUTPUT 0x1
> +
> +/* 0x4 means that we want DAT and not CON register */
> +#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
> +#define GPIO_BIT(x) ((x) & 0x3f)
> +
> +/*
> + * It's how we calculate the full port address
> + * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
> + * We move it at the second digit, and finally we add 0x4 because we want
> + * to modify GPIO DAT and not CON
> + */
> +#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) <<
> 1)) +
> +int gpio_set_value(unsigned gpio, int value)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> + unsigned port = GPIO_FULLPORT(gpio);
> +
> + /*
> + * All GPIO Port have a configuration on
> + * 2 bits excepted the first GPIO (A) which
> + * have only 1 bit of configuration.
> + */
> + if (value)
> + if (!GPIO_PORT(gpio))
> + l |= (0x1 << GPIO_BIT(gpio));
> + else
> + l |= (0x3 << GPIO_BIT(gpio));
> + else
> + if (!GPIO_PORT(gpio))
> + l &= ~(0x1 << GPIO_BIT(gpio));
> + else
> + l &= ~(0x3 << GPIO_BIT(gpio));
> + return writel(port, l);
> +}
> +
> +int gpio_get_value(unsigned gpio)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> +
> + if (GPIO_PORT(gpio) == 0) /* PORT A */
> + return (l >> GPIO_BIT(gpio)) & 0x1;
> + return (l >> GPIO_BIT(gpio)) & 0x3;
> +}
> +
> +int gpio_request(unsigned gpio, const char *label)
> +{
> + return 0;
> +}
> +
> +int gpio_free(unsigned gpio)
> +{
> + return 0;
> +}
> +
> +int gpio_direction_input(unsigned gpio)
> +{
> + return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
> +}
> +
> +int gpio_direction_output(unsigned gpio, int value)
> +{
> + writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
> + return gpio_set_value(gpio, value);
> +}
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-30 13:20 ` [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440 Marek Vasut
@ 2012-04-30 13:29 ` Gabriel Huau
2012-04-30 13:50 ` Marek Vasut
0 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 13:29 UTC (permalink / raw)
To: u-boot
On Mon, Apr 30, 2012 at 03:20:42PM +0200, Marek Vasut wrote:
> Dear Gabriel Huau,
>
> > Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> > ---
> > Changes for v2:
> > - Modification of the coding style
> > - Add my email address to copyright
> > - Remove a typedef
> > - Move some defines to driver file
> >
> > Changes for v3:
> > - Cleanup coding style
> > - Changement of the commit message
>
> There is no commit message here ;-)
>
As I explained in another mail, Only the second line of the commit
message in the text body :)
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440
2012-04-30 13:29 ` Gabriel Huau
@ 2012-04-30 13:50 ` Marek Vasut
0 siblings, 0 replies; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 13:50 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> On Mon, Apr 30, 2012 at 03:20:42PM +0200, Marek Vasut wrote:
> > Dear Gabriel Huau,
> >
> > > Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> > > ---
> > >
> > > Changes for v2:
> > > - Modification of the coding style
> > > - Add my email address to copyright
> > > - Remove a typedef
> > > - Move some defines to driver file
> > >
> > > Changes for v3:
> > > - Cleanup coding style
> > > - Changement of the commit message
> >
> > There is no commit message here ;-)
>
> As I explained in another mail, Only the second line of the commit
> message in the text body :)
I don't follow, but anyway, looking forward to V4 with proper commit message ;-)
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 2/2 v8] Add support for MINI2440 (s3c2440).
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (7 preceding siblings ...)
2012-04-30 13:16 ` [U-Boot] [PATCH 1/2 v3] Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-04-30 13:38 ` Gabriel Huau
2012-04-30 13:51 ` Marek Vasut
2012-05-02 0:15 ` Minkyu Kang
2012-04-30 14:11 ` [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
` (4 subsequent siblings)
13 siblings, 2 replies; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 13:38 UTC (permalink / raw)
To: u-boot
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
Changes for v2:
- Coding style cleanup
- Remove unnecessary files modification
- Remove unnecessary board configuration set
Changes for v3:
- Coding style cleanup
- Move some macro definition from lowlevel_init.S
to a new header
- Remove some "magic bloat" with I/O board initialization
- Add a pll_delay and replace loop by it
- Somme cleanup in the configuration file
- Cancel modifications on an SoC specific header
- Add my name to copyright
Changes for v4:
- Move dram init to dram_init() instead low_levelinit
- Remove u -boot env from configuration file and change
the address of initial SP
- Remove PLL init, now it's SoC specific
Changes for v5:
- Clean up configuration file
- Add a MAINTAINERS entry
- Add a README.mini2440 file
- Use gpio/iomux interface in case of magic numbers
- Use get_ram_size()
Changes for v6:
- Coding style cleanup
- Remove some unused define in the board config
Changes for v7:
- Cleanup coding style
- Changement of the commit message
Changes for v8:
- Replace define[tab] by define[space]
MAINTAINERS | 4 +
board/friendlyarm/mini2440/Makefile | 44 ++++++++
board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++
board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.mini2440 | 28 +++++
include/configs/mini2440.h | 186 +++++++++++++++++++++++++++++++++
7 files changed, 541 insertions(+)
create mode 100644 board/friendlyarm/mini2440/Makefile
create mode 100644 board/friendlyarm/mini2440/mini2440.c
create mode 100644 board/friendlyarm/mini2440/mini2440.h
create mode 100644 doc/README.mini2440
create mode 100644 include/configs/mini2440.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 708ded7..2611fb5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -566,6 +566,10 @@ Unknown / orphaned boards:
# Board CPU #
#########################################################################
+Gabriel HUAU <contact@huau-gabriel.fr>
+
+ mini2440 s3c2440
+
Albert ARIBAUD <albert.u.boot@aribaud.net>
edminiv2 ARM926EJS (Orion5x SoC)
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 0000000..b88e569
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2012
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mini2440.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
new file mode 100644
index 0000000..e97d981
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include "mini2440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void pll_delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_early_init_f(void)
+{
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
+ clk_power->clkdivn = CLKDIVN_VAL;
+
+ /* configure UPLL */
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ /* some delay between MPLL and UPLL */
+ pll_delay(100);
+
+ /* configure MPLL */
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay(10000);
+
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* IOMUX Port H : UART Configuration */
+ gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
+ IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
+
+ gpio_direction_output(GPH8, 0);
+ gpio_direction_output(GPH9, 0);
+ gpio_direction_output(GPH10, 0);
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
+
+ /*
+ * Configuring bus width and timing
+ * Initialize clocks for each bank 0..5
+ * Bank 3 and 4 are used for DM9000
+ */
+ writel(BANK_CONF, &memctl->bwscon);
+ writel(B0_CONF, &memctl->bankcon[0]);
+ writel(B1_CONF, &memctl->bankcon[1]);
+ writel(B2_CONF, &memctl->bankcon[2]);
+ writel(B3_CONF, &memctl->bankcon[3]);
+ writel(B4_CONF, &memctl->bankcon[4]);
+ writel(B5_CONF, &memctl->bankcon[5]);
+
+ /* Bank 6 and 7 are used for DRAM */
+ writel(SDRAM_64MB, &memctl->bankcon[6]);
+ writel(SDRAM_64MB, &memctl->bankcon[7]);
+
+ writel(MEM_TIMING, &memctl->refresh);
+ writel(BANKSIZE_CONF, &memctl->banksize);
+ writel(B6_MRSR, &memctl->mrsrb6);
+ writel(B7_MRSR, &memctl->mrsrb7);
+
+ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ return dm9000_initialize(bis);
+#else
+ return 0;
+#endif
+}
diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
new file mode 100644
index 0000000..db386ea
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.h
@@ -0,0 +1,144 @@
+#ifndef __MINI2440_BOARD_CONF_H__
+#define __MINI2440_BOARD_CONF_H__
+
+/* PLL Parameters */
+#define CLKDIVN_VAL 7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+
+/* BWSCON */
+#define DW8 0x0
+#define DW16 0x1
+#define DW32 0x2
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16 + WAIT + UBLB)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/*
+ * Bank Configuration
+ */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0 /* 0clk */
+#define B0_PMC 0x0 /* normal */
+
+#define B1_Tacs 0x0
+#define B1_Tcos 0x0
+#define B1_Tacc 0x7
+#define B1_Tcoh 0x0
+#define B1_Tah 0x0
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x3 /* 4clk */
+#define B3_Tacp 0x0
+#define B3_PMC 0x0
+
+#define B4_Tacs 0x0
+#define B4_Tcos 0x3
+#define B4_Tacc 0x7
+#define B4_Tcoh 0x1
+#define B4_Tah 0x3
+#define B4_Tacp 0x0
+#define B4_PMC 0x0
+
+#define B5_Tacs 0x0
+#define B5_Tcos 0x0
+#define B5_Tacc 0x7
+#define B5_Tcoh 0x0
+#define B5_Tah 0x0
+#define B5_Tacp 0x0
+#define B5_PMC 0x0
+
+/*
+ * SDRAM Configuration
+ */
+#define SDRAM_MT 0x3 /* SDRAM */
+#define SDRAM_Trcd 0x0 /* 2clk */
+#define SDRAM_SCAN_9 0x1 /* 9bit */
+#define SDRAM_SCAN_10 0x2 /* 10bit */
+
+#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+
+/*
+ * Refresh Parameter
+ */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x1 /* 3clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x0 /* unused */
+#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
+
+/*
+ * MRSR Parameter
+ */
+#define BL 0x0
+#define BT 0x0
+#define CL 0x3 /* 3 clocks */
+#define TM 0x0
+#define WBL 0x0
+
+/*
+ * BankSize Parameter
+ */
+#define BK76MAP 0x2 /* 128MB/128MB */
+#define SCLK_EN 0x1 /* SCLK active */
+#define SCKE_EN 0x1 /* SDRAM power down mode enable */
+#define BURST_EN 0x1 /* Burst enable */
+
+/*
+ * Register values
+ */
+#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
+ (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
+ (B7_BWSCON<<28)))
+
+#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
+ (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
+#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
+ (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
+#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
+ (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
+#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
+ (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
+#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
+ (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
+#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
+ (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
+
+#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
+ (Trc<<18) + (Tchr<<16) + REFCNT
+
+#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
+#define B6_MRSR (CL<<4)
+#define B7_MRSR (CL<<4)
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 3cf75c3..93eeb3c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -61,6 +61,7 @@ mx1ads arm arm920t - -
scb9328 arm arm920t - - imx
cm4008 arm arm920t - - ks8695
cm41xx arm arm920t - - ks8695
+mini2440 arm arm920t mini2440 friendlyarm s3c24x0
VCMA9 arm arm920t vcma9 mpl s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
omap1510inn arm arm925t - ti
diff --git a/doc/README.mini2440 b/doc/README.mini2440
new file mode 100644
index 0000000..311ca52
--- /dev/null
+++ b/doc/README.mini2440
@@ -0,0 +1,28 @@
+U-Boot for FriendlyARM Mini2440 (s3c2440)
+
+This file contains information for the port of U-Boot to FriendlyARM
+mini2440
+
+All information about the board can be found on :
+http://www.friendlyarm.net/products/mini2440
+
+To build u-boot : ./MAKEALL mini2440
+
+Overview :
+--------
+FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
+ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
+systems. It's a low cost board.
+
+Boot Methods :
+------------
+Mini2440 can boot from NOR or NAND.
+
+Build :
+-----
+./MAKEALL mini2440
+
+or
+
+make mini2440_config
+make
diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
new file mode 100644
index 0000000..980b4a5
--- /dev/null
+++ b/include/configs/mini2440.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009-2010
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * Configuation settings for the MINI2440 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_S3C2440_GPIO
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM920T /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
+#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
+#define CONFIG_MINI2440 /* on a MIN2440 Board */
+
+#define MACH_TYPE_MINI2440 1999
+#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
+
+/*
+ * We don't use lowlevel_init
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * input clock of PLL
+ */
+/* MINI2440 has 12.0000MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_DM9000
+#define CONFIG_DRIVER_DM9000_NO_EEPROM
+#define CONFIG_DM9000_BASE 0x20000300
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+4)
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1
+
+/*
+ * allow to overwrite serial and ethaddr
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_LONGHELP
+#define CONFIG_SYS_PROMPT "MINI2440 => "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x30000000
+#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x32000000
+
+/* boot parameters address */
+#define CONFIG_BOOT_PARAM_ADDR 0x30000100
+
+/*
+ * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
+ * it to wrap 100 times (total 1562500) to get 1 sec.
+ */
+#define CONFIG_SYS_HZ 1562500
+
+/*
+ * valid baudrates
+ */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CONFIG_SYS_FLASH_BASE 0x0
+
+/*
+ * Stack should be on the SRAM because
+ * DRAM is not init
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NOR FLASH organization
+ * Now uses the standard CFI interface
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE 0x0
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* 512 * 4096 sectors, or 32 * 64k blocks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_FLASH_SHOW_PROGRESS 1
+
+/*
+ * Config for NOR flash
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_MY_ENV_OFFSET 0x40000
+/* addr of environment */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
+/* 16k Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x4000
+
+/* ATAG configuration */
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v8] Add support for MINI2440 (s3c2440).
2012-04-30 13:38 ` [U-Boot] [PATCH 2/2 v8] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-30 13:51 ` Marek Vasut
2012-05-02 0:15 ` Minkyu Kang
1 sibling, 0 replies; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 13:51 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Cc albert please to see what's his opinion ... I'm fine with this as is.
> ---
> Changes for v2:
> - Coding style cleanup
> - Remove unnecessary files modification
> - Remove unnecessary board configuration set
>
> Changes for v3:
> - Coding style cleanup
> - Move some macro definition from lowlevel_init.S
> to a new header
> - Remove some "magic bloat" with I/O board initialization
> - Add a pll_delay and replace loop by it
> - Somme cleanup in the configuration file
> - Cancel modifications on an SoC specific header
> - Add my name to copyright
>
> Changes for v4:
> - Move dram init to dram_init() instead low_levelinit
> - Remove u -boot env from configuration file and change
> the address of initial SP
> - Remove PLL init, now it's SoC specific
>
> Changes for v5:
> - Clean up configuration file
> - Add a MAINTAINERS entry
> - Add a README.mini2440 file
> - Use gpio/iomux interface in case of magic numbers
> - Use get_ram_size()
>
> Changes for v6:
> - Coding style cleanup
> - Remove some unused define in the board config
>
> Changes for v7:
> - Cleanup coding style
> - Changement of the commit message
>
> Changes for v8:
> - Replace define[tab] by define[space]
>
> MAINTAINERS | 4 +
> board/friendlyarm/mini2440/Makefile | 44 ++++++++
> board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++
> board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.mini2440 | 28 +++++
> include/configs/mini2440.h | 186
> +++++++++++++++++++++++++++++++++ 7 files changed, 541 insertions(+)
> create mode 100644 board/friendlyarm/mini2440/Makefile
> create mode 100644 board/friendlyarm/mini2440/mini2440.c
> create mode 100644 board/friendlyarm/mini2440/mini2440.h
> create mode 100644 doc/README.mini2440
> create mode 100644 include/configs/mini2440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 708ded7..2611fb5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -566,6 +566,10 @@ Unknown / orphaned boards:
> # Board CPU #
> #########################################################################
>
> +Gabriel HUAU <contact@huau-gabriel.fr>
> +
> + mini2440 s3c2440
> +
> Albert ARIBAUD <albert.u.boot@aribaud.net>
>
> edminiv2 ARM926EJS (Orion5x SoC)
> diff --git a/board/friendlyarm/mini2440/Makefile
> b/board/friendlyarm/mini2440/Makefile new file mode 100644
> index 0000000..b88e569
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/Makefile
> @@ -0,0 +1,44 @@
> +#
> +# (C) Copyright 2012
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := mini2440.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/friendlyarm/mini2440/mini2440.c
> b/board/friendlyarm/mini2440/mini2440.c new file mode 100644
> index 0000000..e97d981
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.c
> @@ -0,0 +1,134 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <netdev.h>
> +#include "mini2440.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static inline void pll_delay(unsigned long loops)
> +{
> + __asm__ volatile ("1:\n"
> + "subs %0, %1, #1\n"
> + "bne 1b" : "=r" (loops) : "0" (loops));
> +}
> +
> +int board_early_init_f(void)
> +{
> + struct s3c24x0_clock_power * const clk_power =
> + s3c24x0_get_base_clock_power();
> +
> + /* to reduce PLL lock time, adjust the LOCKTIME register */
> + clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
> + clk_power->clkdivn = CLKDIVN_VAL;
> +
> + /* configure UPLL */
> + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
> + /* some delay between MPLL and UPLL */
> + pll_delay(100);
> +
> + /* configure MPLL */
> + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
> +
> + /* some delay between MPLL and UPLL */
> + pll_delay(10000);
> +
> + return 0;
> +}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
> +
> + /* IOMUX Port H : UART Configuration */
> + gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
> + IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
> +
> + gpio_direction_output(GPH8, 0);
> + gpio_direction_output(GPH9, 0);
> + gpio_direction_output(GPH10, 0);
> +
> + /* adress of boot parameters */
> + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
> +
> + /*
> + * Configuring bus width and timing
> + * Initialize clocks for each bank 0..5
> + * Bank 3 and 4 are used for DM9000
> + */
> + writel(BANK_CONF, &memctl->bwscon);
> + writel(B0_CONF, &memctl->bankcon[0]);
> + writel(B1_CONF, &memctl->bankcon[1]);
> + writel(B2_CONF, &memctl->bankcon[2]);
> + writel(B3_CONF, &memctl->bankcon[3]);
> + writel(B4_CONF, &memctl->bankcon[4]);
> + writel(B5_CONF, &memctl->bankcon[5]);
> +
> + /* Bank 6 and 7 are used for DRAM */
> + writel(SDRAM_64MB, &memctl->bankcon[6]);
> + writel(SDRAM_64MB, &memctl->bankcon[7]);
> +
> + writel(MEM_TIMING, &memctl->refresh);
> + writel(BANKSIZE_CONF, &memctl->banksize);
> + writel(B6_MRSR, &memctl->mrsrb6);
> + writel(B7_MRSR, &memctl->mrsrb7);
> +
> + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
> + PHYS_SDRAM_SIZE);
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#ifdef CONFIG_DRIVER_DM9000
> + return dm9000_initialize(bis);
> +#else
> + return 0;
> +#endif
> +}
> diff --git a/board/friendlyarm/mini2440/mini2440.h
> b/board/friendlyarm/mini2440/mini2440.h new file mode 100644
> index 0000000..db386ea
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.h
> @@ -0,0 +1,144 @@
> +#ifndef __MINI2440_BOARD_CONF_H__
> +#define __MINI2440_BOARD_CONF_H__
> +
> +/* PLL Parameters */
> +#define CLKDIVN_VAL 7
> +#define M_MDIV 0x7f
> +#define M_PDIV 0x2
> +#define M_SDIV 0x1
> +
> +#define U_M_MDIV 0x38
> +#define U_M_PDIV 0x2
> +#define U_M_SDIV 0x2
> +
> +/* BWSCON */
> +#define DW8 0x0
> +#define DW16 0x1
> +#define DW32 0x2
> +#define WAIT (0x1<<2)
> +#define UBLB (0x1<<3)
> +
> +#define B1_BWSCON (DW32)
> +#define B2_BWSCON (DW16)
> +#define B3_BWSCON (DW16 + WAIT + UBLB)
> +#define B4_BWSCON (DW16 + WAIT + UBLB)
> +#define B5_BWSCON (DW16)
> +#define B6_BWSCON (DW32)
> +#define B7_BWSCON (DW32)
> +
> +/*
> + * Bank Configuration
> + */
> +#define B0_Tacs 0x0 /* 0clk */
> +#define B0_Tcos 0x0 /* 0clk */
> +#define B0_Tacc 0x7 /* 14clk */
> +#define B0_Tcoh 0x0 /* 0clk */
> +#define B0_Tah 0x0 /* 0clk */
> +#define B0_Tacp 0x0 /* 0clk */
> +#define B0_PMC 0x0 /* normal */
> +
> +#define B1_Tacs 0x0
> +#define B1_Tcos 0x0
> +#define B1_Tacc 0x7
> +#define B1_Tcoh 0x0
> +#define B1_Tah 0x0
> +#define B1_Tacp 0x0
> +#define B1_PMC 0x0
> +
> +#define B2_Tacs 0x0
> +#define B2_Tcos 0x0
> +#define B2_Tacc 0x7
> +#define B2_Tcoh 0x0
> +#define B2_Tah 0x0
> +#define B2_Tacp 0x0
> +#define B2_PMC 0x0
> +
> +#define B3_Tacs 0x0
> +#define B3_Tcos 0x3 /* 4clk */
> +#define B3_Tacc 0x7
> +#define B3_Tcoh 0x1 /* 1clk */
> +#define B3_Tah 0x3 /* 4clk */
> +#define B3_Tacp 0x0
> +#define B3_PMC 0x0
> +
> +#define B4_Tacs 0x0
> +#define B4_Tcos 0x3
> +#define B4_Tacc 0x7
> +#define B4_Tcoh 0x1
> +#define B4_Tah 0x3
> +#define B4_Tacp 0x0
> +#define B4_PMC 0x0
> +
> +#define B5_Tacs 0x0
> +#define B5_Tcos 0x0
> +#define B5_Tacc 0x7
> +#define B5_Tcoh 0x0
> +#define B5_Tah 0x0
> +#define B5_Tacp 0x0
> +#define B5_PMC 0x0
> +
> +/*
> + * SDRAM Configuration
> + */
> +#define SDRAM_MT 0x3 /* SDRAM */
> +#define SDRAM_Trcd 0x0 /* 2clk */
> +#define SDRAM_SCAN_9 0x1 /* 9bit */
> +#define SDRAM_SCAN_10 0x2 /* 10bit */
> +
> +#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
> +
> +/*
> + * Refresh Parameter
> + */
> +#define REFEN 0x1 /* Refresh enable */
> +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
> +#define Trp 0x1 /* 3clk */
> +#define Trc 0x3 /* 7clk */
> +#define Tchr 0x0 /* unused */
> +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 +
1-10.37*100)
> */ +
> +/*
> + * MRSR Parameter
> + */
> +#define BL 0x0
> +#define BT 0x0
> +#define CL 0x3 /* 3 clocks */
> +#define TM 0x0
> +#define WBL 0x0
> +
> +/*
> + * BankSize Parameter
> + */
> +#define BK76MAP 0x2 /* 128MB/128MB */
> +#define SCLK_EN 0x1 /* SCLK active */
> +#define SCKE_EN 0x1 /* SDRAM power down mode enable */
> +#define BURST_EN 0x1 /* Burst enable */
> +
> +/*
> + * Register values
> + */
> +#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12)
> + \ + (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
> + (B7_BWSCON<<28)))
> +
> +#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
> + (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
> +#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
> + (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
> +#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
> + (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
> +#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
> + (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
> +#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
> + (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
> +#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
> + (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
> +
> +#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
> + (Trc<<18) + (Tchr<<16) + REFCNT
> +
> +#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) +
> (BURST_EN<<7) +#define B6_MRSR (CL<<4)
> +#define B7_MRSR (CL<<4)
> +
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 3cf75c3..93eeb3c 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -61,6 +61,7 @@ mx1ads arm arm920t -
> - scb9328 arm arm920t -
> - imx cm4008 arm
> arm920t - - ks8695 cm41xx
> arm arm920t - - ks8695
> +mini2440 arm arm920t mini2440
> friendlyarm s3c24x0 VCMA9 arm arm920t
> vcma9 mpl s3c24x0 smdk2410
> arm arm920t - samsung s3c24x0
> omap1510inn arm arm925t -
> ti diff --git a/doc/README.mini2440 b/doc/README.mini2440
> new file mode 100644
> index 0000000..311ca52
> --- /dev/null
> +++ b/doc/README.mini2440
> @@ -0,0 +1,28 @@
> +U-Boot for FriendlyARM Mini2440 (s3c2440)
> +
> +This file contains information for the port of U-Boot to FriendlyARM
> +mini2440
> +
> +All information about the board can be found on :
> +http://www.friendlyarm.net/products/mini2440
> +
> +To build u-boot : ./MAKEALL mini2440
> +
> +Overview :
> +--------
> +FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung
> S3C2440 +ARM9 processor. The board measures 100 x 100 mm, ideal for
> learning about ARM9 +systems. It's a low cost board.
> +
> +Boot Methods :
> +------------
> +Mini2440 can boot from NOR or NAND.
> +
> +Build :
> +-----
> +./MAKEALL mini2440
> +
> +or
> +
> +make mini2440_config
> +make
> diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
> new file mode 100644
> index 0000000..980b4a5
> --- /dev/null
> +++ b/include/configs/mini2440.h
> @@ -0,0 +1,186 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + * Gary Jennejohn <gj@denx.de>
> + * David Mueller <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009-2010
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * Configuation settings for the MINI2440 board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_SYS_TEXT_BASE 0x0
> +#define CONFIG_S3C2440_GPIO
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARM920T /* This is an ARM920T Core
*/
> +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
> +#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
> +#define CONFIG_MINI2440 /* on a MIN2440 Board */
> +
> +#define MACH_TYPE_MINI2440 1999
> +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
> +
> +/*
> + * We don't use lowlevel_init
> + */
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +/*
> + * input clock of PLL
> + */
> +/* MINI2440 has 12.0000MHz input clock */
> +#define CONFIG_SYS_CLK_FREQ 12000000
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_DRIVER_DM9000
> +#define CONFIG_DRIVER_DM9000_NO_EEPROM
> +#define CONFIG_DM9000_BASE 0x20000300
> +#define DM9000_IO CONFIG_DM9000_BASE
> +#define DM9000_DATA (CONFIG_DM9000_BASE+4)
> +
> +/*
> + * select serial console configuration
> + */
> +#define CONFIG_S3C24X0_SERIAL
> +#define CONFIG_SERIAL1
> +
> +/*
> + * allow to overwrite serial and ethaddr
> + */
> +#define CONFIG_ENV_OVERWRITE
> +
> +/*
> + * Command definition
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PORTIO
> +#define CONFIG_CMD_REGINFO
> +#define CONFIG_CMD_SAVES
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_LONGHELP
> +#define CONFIG_SYS_PROMPT "MINI2440 => "
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> +#define CONFIG_SYS_MAXARGS 32
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START 0x30000000
> +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM
*/
> +
> +/* default load address */
> +#define CONFIG_SYS_LOAD_ADDR 0x32000000
> +
> +/* boot parameters address */
> +#define CONFIG_BOOT_PARAM_ADDR 0x30000100
> +
> +/*
> + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
> + * it to wrap 100 times (total 1562500) to get 1 sec.
> + */
> +#define CONFIG_SYS_HZ 1562500
> +
> +/*
> + * valid baudrates
> + */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +#define CONFIG_BAUDRATE 115200
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
> +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> +#endif
> +
> +/*
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM
> */ +#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
> +#define CONFIG_SYS_SDRAM_BASE 0x30000000
> +#define CONFIG_SYS_FLASH_BASE 0x0
> +
> +/*
> + * Stack should be on the SRAM because
> + * DRAM is not init
> + */
> +#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 -
GENERATED_GBL_DATA_SIZE)
> +
> +/*
> + * NOR FLASH organization
> + * Now uses the standard CFI interface
> + * FLASH and environment organization
> + */
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> +#define CONFIG_SYS_MONITOR_BASE 0x0
> +/* max number of memory banks */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +/* 512 * 4096 sectors, or 32 * 64k blocks */
> +#define CONFIG_SYS_MAX_FLASH_SECT 512
> +#define CONFIG_FLASH_SHOW_PROGRESS 1
> +
> +/*
> + * Config for NOR flash
> + */
> +#define CONFIG_ENV_IS_IN_FLASH
> +#define CONFIG_MY_ENV_OFFSET 0x40000
> +/* addr of environment */
> +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE +
CONFIG_MY_ENV_OFFSET)
> +/* 16k Total Size of Environment Sector */
> +#define CONFIG_ENV_SIZE 0x4000
> +
> +/* ATAG configuration */
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_AUTO_COMPLETE
> +
> +#endif /* __CONFIG_H */
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v8] Add support for MINI2440 (s3c2440).
2012-04-30 13:38 ` [U-Boot] [PATCH 2/2 v8] Add support for MINI2440 (s3c2440) Gabriel Huau
2012-04-30 13:51 ` Marek Vasut
@ 2012-05-02 0:15 ` Minkyu Kang
1 sibling, 0 replies; 50+ messages in thread
From: Minkyu Kang @ 2012-05-02 0:15 UTC (permalink / raw)
To: u-boot
On 30 April 2012 22:38, Gabriel Huau <contact@huau-gabriel.fr> wrote:
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> Changes for v2:
> ? ? ? ?- Coding style cleanup
> ? ? ? ?- Remove unnecessary files modification
> ? ? ? ?- Remove unnecessary board configuration set
>
> Changes for v3:
> ? ? ? ?- Coding style cleanup
> ? ? ? ?- Move some macro definition from lowlevel_init.S
> ? ? ? ?to a new header
> ? ? ? ?- Remove some "magic bloat" with I/O board initialization
> ? ? ? ?- Add a pll_delay and replace loop by it
> ? ? ? ?- Somme cleanup in the configuration file
> ? ? ? ?- Cancel modifications on an SoC specific header
> ? ? ? ?- Add my name to copyright
>
> Changes for v4:
> ? ? ? ?- Move dram init to dram_init() instead low_levelinit
> ? ? ? ?- Remove u ? ? ?-boot env from configuration file and change
> ? ? ? ?the address of initial SP
> ? ? ? ?- Remove PLL init, now it's SoC specific
>
> Changes for v5:
> ? ? ? ?- Clean up configuration file
> ? ? ? ?- Add a MAINTAINERS entry
> ? ? ? ?- Add a README.mini2440 file
> ? ? ? ?- Use gpio/iomux interface in case of magic numbers
> ? ? ? ?- Use get_ram_size()
>
> Changes for v6:
> ? ? ? ?- Coding style cleanup
> ? ? ? ?- Remove some unused define in the board config
>
> Changes for v7:
> ? ? ? ?- Cleanup coding style
> ? ? ? ?- Changement of the commit message
>
> Changes for v8:
> ? ? ? ?- Replace define[tab] by define[space]
>
> ?MAINTAINERS ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?4 +
> ?board/friendlyarm/mini2440/Makefile ? | ? 44 ++++++++
> ?board/friendlyarm/mini2440/mini2440.c | ?134 ++++++++++++++++++++++++
> ?board/friendlyarm/mini2440/mini2440.h | ?144 +++++++++++++++++++++++++
> ?boards.cfg ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
> ?doc/README.mini2440 ? ? ? ? ? ? ? ? ? | ? 28 +++++
> ?include/configs/mini2440.h ? ? ? ? ? ?| ?186 +++++++++++++++++++++++++++++++++
> ?7 files changed, 541 insertions(+)
> ?create mode 100644 board/friendlyarm/mini2440/Makefile
> ?create mode 100644 board/friendlyarm/mini2440/mini2440.c
> ?create mode 100644 board/friendlyarm/mini2440/mini2440.h
> ?create mode 100644 doc/README.mini2440
> ?create mode 100644 include/configs/mini2440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 708ded7..2611fb5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -566,6 +566,10 @@ Unknown / orphaned boards:
> ?# ? ? ?Board ? ? ? ? ? CPU ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? #
> ?#########################################################################
>
> +Gabriel HUAU <contact@huau-gabriel.fr>
> +
> + ? ? ? mini2440 ? ? ? ?s3c2440
> +
Please keep this list to alphabetically. (by last name)
> ?Albert ARIBAUD <albert.u.boot@aribaud.net>
>
> ? ? ? ?edminiv2 ? ? ? ?ARM926EJS (Orion5x SoC)
Thanks.
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (8 preceding siblings ...)
2012-04-30 13:38 ` [U-Boot] [PATCH 2/2 v8] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-30 14:11 ` Gabriel Huau
2012-04-30 14:11 ` [U-Boot] [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440) Gabriel Huau
` (2 more replies)
2012-04-30 15:44 ` [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (3 subsequent siblings)
13 siblings, 3 replies; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 14:11 UTC (permalink / raw)
To: u-boot
It's now possible to use the gpio driver interface
for s3c2440. This patch add iomux definitions too.
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
Changes for v2:
- Modification of the coding style
- Add my email address to copyright
- Remove a typedef
- Move some defines to driver file
Changes for v3:
- Cleanup coding style
- Changement of the commit message
Changes for v4:
- Add a nice commit message
arch/arm/include/asm/arch-s3c24x0/gpio.h | 171 ++++++++++++++++++++++++
arch/arm/include/asm/arch-s3c24x0/iomux.h | 200 +++++++++++++++++++++++++++++
drivers/gpio/Makefile | 1 +
drivers/gpio/s3c2440_gpio.c | 94 ++++++++++++++
4 files changed, 466 insertions(+)
create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
create mode 100644 drivers/gpio/s3c2440_gpio.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 0000000..76bc52c
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 0000000..cc22de7
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_IOMUX_H_
+#define _S3C24X0_IOMUX_H_
+
+enum s3c2440_iomux_func {
+ /* PORT A */
+ IOMUXA_ADDR0 = 1,
+ IOMUXA_ADDR16 = (1 << 1),
+ IOMUXA_ADDR17 = (1 << 2),
+ IOMUXA_ADDR18 = (1 << 3),
+ IOMUXA_ADDR19 = (1 << 4),
+ IOMUXA_ADDR20 = (1 << 5),
+ IOMUXA_ADDR21 = (1 << 6),
+ IOMUXA_ADDR22 = (1 << 7),
+ IOMUXA_ADDR23 = (1 << 8),
+ IOMUXA_ADDR24 = (1 << 9),
+ IOMUXA_ADDR25 = (1 << 10),
+ IOMUXA_ADDR26 = (1 << 11),
+ IOMUXA_nGCS1 = (1 << 12),
+ IOMUXA_nGCS2 = (1 << 13),
+ IOMUXA_nGCS3 = (1 << 14),
+ IOMUXA_nGCS4 = (1 << 15),
+ IOMUXA_nGCS5 = (1 << 16),
+ IOMUXA_CLE = (1 << 17),
+ IOMUXA_ALE = (1 << 18),
+ IOMUXA_nFWE = (1 << 19),
+ IOMUXA_nFRE = (1 << 20),
+ IOMUXA_nRSTOUT = (1 << 21),
+ IOMUXA_nFCE = (1 << 22),
+
+ /* PORT B */
+ IOMUXB_nXDREQ0 = (2 << 20),
+ IOMUXB_nXDACK0 = (2 << 18),
+ IOMUXB_nXDREQ1 = (2 << 16),
+ IOMUXB_nXDACK1 = (2 << 14),
+ IOMUXB_nXBREQ = (2 << 12),
+ IOMUXB_nXBACK = (2 << 10),
+ IOMUXB_TCLK0 = (2 << 8),
+ IOMUXB_TOUT3 = (2 << 6),
+ IOMUXB_TOUT2 = (2 << 4),
+ IOMUXB_TOUT1 = (2 << 2),
+ IOMUXB_TOUT0 = 2,
+
+ /* PORT C */
+ IOMUXC_VS7 = (2 << 30),
+ IOMUXC_VS6 = (2 << 28),
+ IOMUXC_VS5 = (2 << 26),
+ IOMUXC_VS4 = (2 << 24),
+ IOMUXC_VS3 = (2 << 22),
+ IOMUXC_VS2 = (2 << 20),
+ IOMUXC_VS1 = (2 << 18),
+ IOMUXC_VS0 = (2 << 16),
+ IOMUXC_LCD_LPCREVB = (2 << 14),
+ IOMUXC_LCD_LPCREV = (2 << 12),
+ IOMUXC_LCD_LPCOE = (2 << 10),
+ IOMUXC_VM = (2 << 8),
+ IOMUXC_VFRAME = (2 << 6),
+ IOMUXC_VLINE = (2 << 4),
+ IOMUXC_VCLK = (2 << 2),
+ IOMUXC_LEND = 2,
+ IOMUXC_I2SSDI = (3 << 8),
+
+ /* PORT D */
+ IOMUXD_VS23 = (2 << 30),
+ IOMUXD_VS22 = (2 << 28),
+ IOMUXD_VS21 = (2 << 26),
+ IOMUXD_VS20 = (2 << 24),
+ IOMUXD_VS19 = (2 << 22),
+ IOMUXD_VS18 = (2 << 20),
+ IOMUXD_VS17 = (2 << 18),
+ IOMUXD_VS16 = (2 << 16),
+ IOMUXD_VS15 = (2 << 14),
+ IOMUXD_VS14 = (2 << 12),
+ IOMUXD_VS13 = (2 << 10),
+ IOMUXD_VS12 = (2 << 8),
+ IOMUXD_VS11 = (2 << 6),
+ IOMUXD_VS10 = (2 << 4),
+ IOMUXD_VS9 = (2 << 2),
+ IOMUXD_VS8 = 2,
+ IOMUXD_nSS0 = (3 << 30),
+ IOMUXD_nSS1 = (3 << 28),
+ IOMUXD_SPICLK1 = (3 << 20),
+ IOMUXD_SPIMOSI1 = (3 << 18),
+ IOMUXD_SPIMISO1 = (3 << 16),
+
+ /* PORT E */
+ IOMUXE_IICSDA = (2 << 30),
+ IOMUXE_IICSCL = (2 << 28),
+ IOMUXE_SPICLK0 = (2 << 26),
+ IOMUXE_SPIMOSI0 = (2 << 24),
+ IOMUXE_SPIMISO0 = (2 << 22),
+ IOMUXE_SDDAT3 = (2 << 20),
+ IOMUXE_SDDAT2 = (2 << 18),
+ IOMUXE_SDDAT1 = (2 << 16),
+ IOMUXE_SDDAT0 = (2 << 14),
+ IOMUXE_SDCMD = (2 << 12),
+ IOMUXE_SDCLK = (2 << 10),
+ IOMUXE_I2SDO = (2 << 8),
+ IOMUXE_I2SDI = (2 << 6),
+ IOMUXE_CDCLK = (2 << 4),
+ IOMUXE_I2SSCLK = (2 << 2),
+ IOMUXE_I2SLRCK = 2,
+ IOMUXE_AC_SDATA_OUT = (3 << 8),
+ IOMUXE_AC_SDATA_IN = (3 << 6),
+ IOMUXE_AC_nRESET = (3 << 4),
+ IOMUXE_AC_BIT_CLK = (3 << 2),
+ IOMUXE_AC_SYNC = 3,
+
+ /* PORT F */
+ IOMUXF_EINT7 = (2 << 14),
+ IOMUXF_EINT6 = (2 << 12),
+ IOMUXF_EINT5 = (2 << 10),
+ IOMUXF_EINT4 = (2 << 8),
+ IOMUXF_EINT3 = (2 << 6),
+ IOMUXF_EINT2 = (2 << 4),
+ IOMUXF_EINT1 = (2 << 2),
+ IOMUXF_EINT0 = 2,
+
+ /* PORT G */
+ IOMUXG_EINT23 = (2 << 30),
+ IOMUXG_EINT22 = (2 << 28),
+ IOMUXG_EINT21 = (2 << 26),
+ IOMUXG_EINT20 = (2 << 24),
+ IOMUXG_EINT19 = (2 << 22),
+ IOMUXG_EINT18 = (2 << 20),
+ IOMUXG_EINT17 = (2 << 18),
+ IOMUXG_EINT16 = (2 << 16),
+ IOMUXG_EINT15 = (2 << 14),
+ IOMUXG_EINT14 = (2 << 12),
+ IOMUXG_EINT13 = (2 << 10),
+ IOMUXG_EINT12 = (2 << 8),
+ IOMUXG_EINT11 = (2 << 6),
+ IOMUXG_EINT10 = (2 << 4),
+ IOMUXG_EINT9 = (2 << 2),
+ IOMUXG_EINT8 = 2,
+ IOMUXG_TCLK1 = (3 << 22),
+ IOMUXG_nCTS1 = (3 << 20),
+ IOMUXG_nRTS1 = (3 << 18),
+ IOMUXG_SPICLK1 = (3 << 14),
+ IOMUXG_SPIMOSI1 = (3 << 12),
+ IOMUXG_SPIMISO1 = (3 << 10),
+ IOMUXG_LCD_PWRDN = (3 << 8),
+ IOMUXG_nSS1 = (3 << 6),
+ IOMUXG_nSS0 = (3 << 4),
+
+ /* PORT H */
+ IOMUXH_CLKOUT1 = (2 << 20),
+ IOMUXH_CLKOUT0 = (2 << 18),
+ IOMUXH_UEXTCLK = (2 << 16),
+ IOMUXH_RXD2 = (2 << 14),
+ IOMUXH_TXD2 = (2 << 12),
+ IOMUXH_RXD1 = (2 << 10),
+ IOMUXH_TXD1 = (2 << 8),
+ IOMUXH_RXD0 = (2 << 6),
+ IOMUXH_TXD0 = (2 << 4),
+ IOMUXH_nRTS0 = (2 << 2),
+ IOMUXH_nCTS0 = 2,
+ IOMUXH_nCTS1 = (3 << 14),
+ IOMUXH_nRTS1 = (3 << 12),
+
+ /* PORT J */
+ IOMUXJ_CAMRESET = (2 << 24),
+ IOMUXJ_CAMCLKOUT = (2 << 22),
+ IOMUXJ_CAMHREF = (2 << 20),
+ IOMUXJ_CAMVSYNC = (2 << 18),
+ IOMUXJ_CAMPCLK = (2 << 16),
+ IOMUXJ_CAMDATA7 = (2 << 14),
+ IOMUXJ_CAMDATA6 = (2 << 12),
+ IOMUXJ_CAMDATA5 = (2 << 10),
+ IOMUXJ_CAMDATA4 = (2 << 8),
+ IOMUXJ_CAMDATA3 = (2 << 6),
+ IOMUXJ_CAMDATA2 = (2 << 4),
+ IOMUXJ_CAMDATA1 = (2 << 2),
+ IOMUXJ_CAMDATA0 = 2
+};
+
+#endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb3b09a..7ae6f84 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
+COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
new file mode 100644
index 0000000..12a9043
--- /dev/null
+++ b/drivers/gpio/s3c2440_gpio.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+
+/* 0x4 means that we want DAT and not CON register */
+#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
+#define GPIO_BIT(x) ((x) & 0x3f)
+
+/*
+ * It's how we calculate the full port address
+ * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
+ * We move it at the second digit, and finally we add 0x4 because we want
+ * to modify GPIO DAT and not CON
+ */
+#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) << 1))
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+ unsigned port = GPIO_FULLPORT(gpio);
+
+ /*
+ * All GPIO Port have a configuration on
+ * 2 bits excepted the first GPIO (A) which
+ * have only 1 bit of configuration.
+ */
+ if (value)
+ if (!GPIO_PORT(gpio))
+ l |= (0x1 << GPIO_BIT(gpio));
+ else
+ l |= (0x3 << GPIO_BIT(gpio));
+ else
+ if (!GPIO_PORT(gpio))
+ l &= ~(0x1 << GPIO_BIT(gpio));
+ else
+ l &= ~(0x3 << GPIO_BIT(gpio));
+ return writel(port, l);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+
+ if (GPIO_PORT(gpio) == 0) /* PORT A */
+ return (l >> GPIO_BIT(gpio)) & 0x1;
+ return (l >> GPIO_BIT(gpio)) & 0x3;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
+ return gpio_set_value(gpio, value);
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440).
2012-04-30 14:11 ` [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-04-30 14:11 ` Gabriel Huau
2012-04-30 14:17 ` Marek Vasut
2012-05-02 0:17 ` Minkyu Kang
2012-04-30 14:16 ` [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Marek Vasut
2012-05-02 1:21 ` Minkyu Kang
2 siblings, 2 replies; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 14:11 UTC (permalink / raw)
To: u-boot
Support of the MINI2440 board from FriendlyARM from
an old version of u-boot :
http://repo.or.cz/r/u-boot-openmoko/mini2440.git
Currently, supporting only boot from NOR.
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
Changes for v2:
- Coding style cleanup
- Remove unnecessary files modification
- Remove unnecessary board configuration set
Changes for v3:
- Coding style cleanup
- Move some macro definition from lowlevel_init.S
to a new header
- Remove some "magic bloat" with I/O board initialization
- Add a pll_delay and replace loop by it
- Somme cleanup in the configuration file
- Cancel modifications on an SoC specific header
- Add my name to copyright
Changes for v4:
- Move dram init to dram_init() instead low_levelinit
- Remove u -boot env from configuration file and change
the address of initial SP
- Remove PLL init, now it's SoC specific
Changes for v5:
- Clean up configuration file
- Add a MAINTAINERS entry
- Add a README.mini2440 file
- Use gpio/iomux interface in case of magic numbers
- Use get_ram_size()
Changes for v6:
- Coding style cleanup
- Remove some unused define in the board config
Changes for v7:
- Cleanup coding style
- Changement of the commit message
Changes for v8:
- Replace define[tab] by define[space]
Changes for v9:
- Add a nice commit message
MAINTAINERS | 4 +
board/friendlyarm/mini2440/Makefile | 44 ++++++++
board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++
board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.mini2440 | 28 +++++
include/configs/mini2440.h | 186 +++++++++++++++++++++++++++++++++
7 files changed, 541 insertions(+)
create mode 100644 board/friendlyarm/mini2440/Makefile
create mode 100644 board/friendlyarm/mini2440/mini2440.c
create mode 100644 board/friendlyarm/mini2440/mini2440.h
create mode 100644 doc/README.mini2440
create mode 100644 include/configs/mini2440.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 708ded7..2611fb5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -566,6 +566,10 @@ Unknown / orphaned boards:
# Board CPU #
#########################################################################
+Gabriel HUAU <contact@huau-gabriel.fr>
+
+ mini2440 s3c2440
+
Albert ARIBAUD <albert.u.boot@aribaud.net>
edminiv2 ARM926EJS (Orion5x SoC)
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 0000000..b88e569
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2012
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mini2440.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
new file mode 100644
index 0000000..e97d981
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include "mini2440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void pll_delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_early_init_f(void)
+{
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
+ clk_power->clkdivn = CLKDIVN_VAL;
+
+ /* configure UPLL */
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ /* some delay between MPLL and UPLL */
+ pll_delay(100);
+
+ /* configure MPLL */
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay(10000);
+
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* IOMUX Port H : UART Configuration */
+ gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
+ IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
+
+ gpio_direction_output(GPH8, 0);
+ gpio_direction_output(GPH9, 0);
+ gpio_direction_output(GPH10, 0);
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
+
+ /*
+ * Configuring bus width and timing
+ * Initialize clocks for each bank 0..5
+ * Bank 3 and 4 are used for DM9000
+ */
+ writel(BANK_CONF, &memctl->bwscon);
+ writel(B0_CONF, &memctl->bankcon[0]);
+ writel(B1_CONF, &memctl->bankcon[1]);
+ writel(B2_CONF, &memctl->bankcon[2]);
+ writel(B3_CONF, &memctl->bankcon[3]);
+ writel(B4_CONF, &memctl->bankcon[4]);
+ writel(B5_CONF, &memctl->bankcon[5]);
+
+ /* Bank 6 and 7 are used for DRAM */
+ writel(SDRAM_64MB, &memctl->bankcon[6]);
+ writel(SDRAM_64MB, &memctl->bankcon[7]);
+
+ writel(MEM_TIMING, &memctl->refresh);
+ writel(BANKSIZE_CONF, &memctl->banksize);
+ writel(B6_MRSR, &memctl->mrsrb6);
+ writel(B7_MRSR, &memctl->mrsrb7);
+
+ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ return dm9000_initialize(bis);
+#else
+ return 0;
+#endif
+}
diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
new file mode 100644
index 0000000..db386ea
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.h
@@ -0,0 +1,144 @@
+#ifndef __MINI2440_BOARD_CONF_H__
+#define __MINI2440_BOARD_CONF_H__
+
+/* PLL Parameters */
+#define CLKDIVN_VAL 7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+
+/* BWSCON */
+#define DW8 0x0
+#define DW16 0x1
+#define DW32 0x2
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16 + WAIT + UBLB)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/*
+ * Bank Configuration
+ */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0 /* 0clk */
+#define B0_PMC 0x0 /* normal */
+
+#define B1_Tacs 0x0
+#define B1_Tcos 0x0
+#define B1_Tacc 0x7
+#define B1_Tcoh 0x0
+#define B1_Tah 0x0
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x3 /* 4clk */
+#define B3_Tacp 0x0
+#define B3_PMC 0x0
+
+#define B4_Tacs 0x0
+#define B4_Tcos 0x3
+#define B4_Tacc 0x7
+#define B4_Tcoh 0x1
+#define B4_Tah 0x3
+#define B4_Tacp 0x0
+#define B4_PMC 0x0
+
+#define B5_Tacs 0x0
+#define B5_Tcos 0x0
+#define B5_Tacc 0x7
+#define B5_Tcoh 0x0
+#define B5_Tah 0x0
+#define B5_Tacp 0x0
+#define B5_PMC 0x0
+
+/*
+ * SDRAM Configuration
+ */
+#define SDRAM_MT 0x3 /* SDRAM */
+#define SDRAM_Trcd 0x0 /* 2clk */
+#define SDRAM_SCAN_9 0x1 /* 9bit */
+#define SDRAM_SCAN_10 0x2 /* 10bit */
+
+#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+
+/*
+ * Refresh Parameter
+ */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x1 /* 3clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x0 /* unused */
+#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
+
+/*
+ * MRSR Parameter
+ */
+#define BL 0x0
+#define BT 0x0
+#define CL 0x3 /* 3 clocks */
+#define TM 0x0
+#define WBL 0x0
+
+/*
+ * BankSize Parameter
+ */
+#define BK76MAP 0x2 /* 128MB/128MB */
+#define SCLK_EN 0x1 /* SCLK active */
+#define SCKE_EN 0x1 /* SDRAM power down mode enable */
+#define BURST_EN 0x1 /* Burst enable */
+
+/*
+ * Register values
+ */
+#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
+ (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
+ (B7_BWSCON<<28)))
+
+#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
+ (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
+#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
+ (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
+#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
+ (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
+#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
+ (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
+#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
+ (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
+#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
+ (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
+
+#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
+ (Trc<<18) + (Tchr<<16) + REFCNT
+
+#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
+#define B6_MRSR (CL<<4)
+#define B7_MRSR (CL<<4)
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 3cf75c3..93eeb3c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -61,6 +61,7 @@ mx1ads arm arm920t - -
scb9328 arm arm920t - - imx
cm4008 arm arm920t - - ks8695
cm41xx arm arm920t - - ks8695
+mini2440 arm arm920t mini2440 friendlyarm s3c24x0
VCMA9 arm arm920t vcma9 mpl s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
omap1510inn arm arm925t - ti
diff --git a/doc/README.mini2440 b/doc/README.mini2440
new file mode 100644
index 0000000..311ca52
--- /dev/null
+++ b/doc/README.mini2440
@@ -0,0 +1,28 @@
+U-Boot for FriendlyARM Mini2440 (s3c2440)
+
+This file contains information for the port of U-Boot to FriendlyARM
+mini2440
+
+All information about the board can be found on :
+http://www.friendlyarm.net/products/mini2440
+
+To build u-boot : ./MAKEALL mini2440
+
+Overview :
+--------
+FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
+ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
+systems. It's a low cost board.
+
+Boot Methods :
+------------
+Mini2440 can boot from NOR or NAND.
+
+Build :
+-----
+./MAKEALL mini2440
+
+or
+
+make mini2440_config
+make
diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
new file mode 100644
index 0000000..980b4a5
--- /dev/null
+++ b/include/configs/mini2440.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009-2010
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * Configuation settings for the MINI2440 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_S3C2440_GPIO
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM920T /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
+#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
+#define CONFIG_MINI2440 /* on a MIN2440 Board */
+
+#define MACH_TYPE_MINI2440 1999
+#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
+
+/*
+ * We don't use lowlevel_init
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * input clock of PLL
+ */
+/* MINI2440 has 12.0000MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_DM9000
+#define CONFIG_DRIVER_DM9000_NO_EEPROM
+#define CONFIG_DM9000_BASE 0x20000300
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+4)
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1
+
+/*
+ * allow to overwrite serial and ethaddr
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_LONGHELP
+#define CONFIG_SYS_PROMPT "MINI2440 => "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x30000000
+#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x32000000
+
+/* boot parameters address */
+#define CONFIG_BOOT_PARAM_ADDR 0x30000100
+
+/*
+ * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
+ * it to wrap 100 times (total 1562500) to get 1 sec.
+ */
+#define CONFIG_SYS_HZ 1562500
+
+/*
+ * valid baudrates
+ */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CONFIG_SYS_FLASH_BASE 0x0
+
+/*
+ * Stack should be on the SRAM because
+ * DRAM is not init
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NOR FLASH organization
+ * Now uses the standard CFI interface
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE 0x0
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* 512 * 4096 sectors, or 32 * 64k blocks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_FLASH_SHOW_PROGRESS 1
+
+/*
+ * Config for NOR flash
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_MY_ENV_OFFSET 0x40000
+/* addr of environment */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
+/* 16k Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x4000
+
+/* ATAG configuration */
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440).
2012-04-30 14:11 ` [U-Boot] [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-30 14:17 ` Marek Vasut
2012-05-02 0:17 ` Minkyu Kang
1 sibling, 0 replies; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 14:17 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> Support of the MINI2440 board from FriendlyARM from
> an old version of u-boot :
> http://repo.or.cz/r/u-boot-openmoko/mini2440.git
>
> Currently, supporting only boot from NOR.
Acked-by: Marek Vasut <marex@denx.de>
>
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> Changes for v2:
> - Coding style cleanup
> - Remove unnecessary files modification
> - Remove unnecessary board configuration set
>
> Changes for v3:
> - Coding style cleanup
> - Move some macro definition from lowlevel_init.S
> to a new header
> - Remove some "magic bloat" with I/O board initialization
> - Add a pll_delay and replace loop by it
> - Somme cleanup in the configuration file
> - Cancel modifications on an SoC specific header
> - Add my name to copyright
>
> Changes for v4:
> - Move dram init to dram_init() instead low_levelinit
> - Remove u -boot env from configuration file and change
> the address of initial SP
> - Remove PLL init, now it's SoC specific
>
> Changes for v5:
> - Clean up configuration file
> - Add a MAINTAINERS entry
> - Add a README.mini2440 file
> - Use gpio/iomux interface in case of magic numbers
> - Use get_ram_size()
>
> Changes for v6:
> - Coding style cleanup
> - Remove some unused define in the board config
>
> Changes for v7:
> - Cleanup coding style
> - Changement of the commit message
>
> Changes for v8:
> - Replace define[tab] by define[space]
>
> Changes for v9:
> - Add a nice commit message
>
> MAINTAINERS | 4 +
> board/friendlyarm/mini2440/Makefile | 44 ++++++++
> board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++
> board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.mini2440 | 28 +++++
> include/configs/mini2440.h | 186
> +++++++++++++++++++++++++++++++++ 7 files changed, 541 insertions(+)
> create mode 100644 board/friendlyarm/mini2440/Makefile
> create mode 100644 board/friendlyarm/mini2440/mini2440.c
> create mode 100644 board/friendlyarm/mini2440/mini2440.h
> create mode 100644 doc/README.mini2440
> create mode 100644 include/configs/mini2440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 708ded7..2611fb5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -566,6 +566,10 @@ Unknown / orphaned boards:
> # Board CPU #
> #########################################################################
>
> +Gabriel HUAU <contact@huau-gabriel.fr>
> +
> + mini2440 s3c2440
> +
> Albert ARIBAUD <albert.u.boot@aribaud.net>
>
> edminiv2 ARM926EJS (Orion5x SoC)
> diff --git a/board/friendlyarm/mini2440/Makefile
> b/board/friendlyarm/mini2440/Makefile new file mode 100644
> index 0000000..b88e569
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/Makefile
> @@ -0,0 +1,44 @@
> +#
> +# (C) Copyright 2012
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := mini2440.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/friendlyarm/mini2440/mini2440.c
> b/board/friendlyarm/mini2440/mini2440.c new file mode 100644
> index 0000000..e97d981
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.c
> @@ -0,0 +1,134 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <netdev.h>
> +#include "mini2440.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static inline void pll_delay(unsigned long loops)
> +{
> + __asm__ volatile ("1:\n"
> + "subs %0, %1, #1\n"
> + "bne 1b" : "=r" (loops) : "0" (loops));
> +}
> +
> +int board_early_init_f(void)
> +{
> + struct s3c24x0_clock_power * const clk_power =
> + s3c24x0_get_base_clock_power();
> +
> + /* to reduce PLL lock time, adjust the LOCKTIME register */
> + clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
> + clk_power->clkdivn = CLKDIVN_VAL;
> +
> + /* configure UPLL */
> + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
> + /* some delay between MPLL and UPLL */
> + pll_delay(100);
> +
> + /* configure MPLL */
> + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
> +
> + /* some delay between MPLL and UPLL */
> + pll_delay(10000);
> +
> + return 0;
> +}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
> +
> + /* IOMUX Port H : UART Configuration */
> + gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
> + IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
> +
> + gpio_direction_output(GPH8, 0);
> + gpio_direction_output(GPH9, 0);
> + gpio_direction_output(GPH10, 0);
> +
> + /* adress of boot parameters */
> + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
> +
> + /*
> + * Configuring bus width and timing
> + * Initialize clocks for each bank 0..5
> + * Bank 3 and 4 are used for DM9000
> + */
> + writel(BANK_CONF, &memctl->bwscon);
> + writel(B0_CONF, &memctl->bankcon[0]);
> + writel(B1_CONF, &memctl->bankcon[1]);
> + writel(B2_CONF, &memctl->bankcon[2]);
> + writel(B3_CONF, &memctl->bankcon[3]);
> + writel(B4_CONF, &memctl->bankcon[4]);
> + writel(B5_CONF, &memctl->bankcon[5]);
> +
> + /* Bank 6 and 7 are used for DRAM */
> + writel(SDRAM_64MB, &memctl->bankcon[6]);
> + writel(SDRAM_64MB, &memctl->bankcon[7]);
> +
> + writel(MEM_TIMING, &memctl->refresh);
> + writel(BANKSIZE_CONF, &memctl->banksize);
> + writel(B6_MRSR, &memctl->mrsrb6);
> + writel(B7_MRSR, &memctl->mrsrb7);
> +
> + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
> + PHYS_SDRAM_SIZE);
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#ifdef CONFIG_DRIVER_DM9000
> + return dm9000_initialize(bis);
> +#else
> + return 0;
> +#endif
> +}
> diff --git a/board/friendlyarm/mini2440/mini2440.h
> b/board/friendlyarm/mini2440/mini2440.h new file mode 100644
> index 0000000..db386ea
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.h
> @@ -0,0 +1,144 @@
> +#ifndef __MINI2440_BOARD_CONF_H__
> +#define __MINI2440_BOARD_CONF_H__
> +
> +/* PLL Parameters */
> +#define CLKDIVN_VAL 7
> +#define M_MDIV 0x7f
> +#define M_PDIV 0x2
> +#define M_SDIV 0x1
> +
> +#define U_M_MDIV 0x38
> +#define U_M_PDIV 0x2
> +#define U_M_SDIV 0x2
> +
> +/* BWSCON */
> +#define DW8 0x0
> +#define DW16 0x1
> +#define DW32 0x2
> +#define WAIT (0x1<<2)
> +#define UBLB (0x1<<3)
> +
> +#define B1_BWSCON (DW32)
> +#define B2_BWSCON (DW16)
> +#define B3_BWSCON (DW16 + WAIT + UBLB)
> +#define B4_BWSCON (DW16 + WAIT + UBLB)
> +#define B5_BWSCON (DW16)
> +#define B6_BWSCON (DW32)
> +#define B7_BWSCON (DW32)
> +
> +/*
> + * Bank Configuration
> + */
> +#define B0_Tacs 0x0 /* 0clk */
> +#define B0_Tcos 0x0 /* 0clk */
> +#define B0_Tacc 0x7 /* 14clk */
> +#define B0_Tcoh 0x0 /* 0clk */
> +#define B0_Tah 0x0 /* 0clk */
> +#define B0_Tacp 0x0 /* 0clk */
> +#define B0_PMC 0x0 /* normal */
> +
> +#define B1_Tacs 0x0
> +#define B1_Tcos 0x0
> +#define B1_Tacc 0x7
> +#define B1_Tcoh 0x0
> +#define B1_Tah 0x0
> +#define B1_Tacp 0x0
> +#define B1_PMC 0x0
> +
> +#define B2_Tacs 0x0
> +#define B2_Tcos 0x0
> +#define B2_Tacc 0x7
> +#define B2_Tcoh 0x0
> +#define B2_Tah 0x0
> +#define B2_Tacp 0x0
> +#define B2_PMC 0x0
> +
> +#define B3_Tacs 0x0
> +#define B3_Tcos 0x3 /* 4clk */
> +#define B3_Tacc 0x7
> +#define B3_Tcoh 0x1 /* 1clk */
> +#define B3_Tah 0x3 /* 4clk */
> +#define B3_Tacp 0x0
> +#define B3_PMC 0x0
> +
> +#define B4_Tacs 0x0
> +#define B4_Tcos 0x3
> +#define B4_Tacc 0x7
> +#define B4_Tcoh 0x1
> +#define B4_Tah 0x3
> +#define B4_Tacp 0x0
> +#define B4_PMC 0x0
> +
> +#define B5_Tacs 0x0
> +#define B5_Tcos 0x0
> +#define B5_Tacc 0x7
> +#define B5_Tcoh 0x0
> +#define B5_Tah 0x0
> +#define B5_Tacp 0x0
> +#define B5_PMC 0x0
> +
> +/*
> + * SDRAM Configuration
> + */
> +#define SDRAM_MT 0x3 /* SDRAM */
> +#define SDRAM_Trcd 0x0 /* 2clk */
> +#define SDRAM_SCAN_9 0x1 /* 9bit */
> +#define SDRAM_SCAN_10 0x2 /* 10bit */
> +
> +#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
> +
> +/*
> + * Refresh Parameter
> + */
> +#define REFEN 0x1 /* Refresh enable */
> +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
> +#define Trp 0x1 /* 3clk */
> +#define Trc 0x3 /* 7clk */
> +#define Tchr 0x0 /* unused */
> +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 +
1-10.37*100)
> */ +
> +/*
> + * MRSR Parameter
> + */
> +#define BL 0x0
> +#define BT 0x0
> +#define CL 0x3 /* 3 clocks */
> +#define TM 0x0
> +#define WBL 0x0
> +
> +/*
> + * BankSize Parameter
> + */
> +#define BK76MAP 0x2 /* 128MB/128MB */
> +#define SCLK_EN 0x1 /* SCLK active */
> +#define SCKE_EN 0x1 /* SDRAM power down mode enable */
> +#define BURST_EN 0x1 /* Burst enable */
> +
> +/*
> + * Register values
> + */
> +#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12)
> + \ + (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
> + (B7_BWSCON<<28)))
> +
> +#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
> + (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
> +#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
> + (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
> +#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
> + (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
> +#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
> + (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
> +#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
> + (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
> +#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
> + (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
> +
> +#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
> + (Trc<<18) + (Tchr<<16) + REFCNT
> +
> +#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) +
> (BURST_EN<<7) +#define B6_MRSR (CL<<4)
> +#define B7_MRSR (CL<<4)
> +
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 3cf75c3..93eeb3c 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -61,6 +61,7 @@ mx1ads arm arm920t -
> - scb9328 arm arm920t -
> - imx cm4008 arm
> arm920t - - ks8695 cm41xx
> arm arm920t - - ks8695
> +mini2440 arm arm920t mini2440
> friendlyarm s3c24x0 VCMA9 arm arm920t
> vcma9 mpl s3c24x0 smdk2410
> arm arm920t - samsung s3c24x0
> omap1510inn arm arm925t -
> ti diff --git a/doc/README.mini2440 b/doc/README.mini2440
> new file mode 100644
> index 0000000..311ca52
> --- /dev/null
> +++ b/doc/README.mini2440
> @@ -0,0 +1,28 @@
> +U-Boot for FriendlyARM Mini2440 (s3c2440)
> +
> +This file contains information for the port of U-Boot to FriendlyARM
> +mini2440
> +
> +All information about the board can be found on :
> +http://www.friendlyarm.net/products/mini2440
> +
> +To build u-boot : ./MAKEALL mini2440
> +
> +Overview :
> +--------
> +FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung
> S3C2440 +ARM9 processor. The board measures 100 x 100 mm, ideal for
> learning about ARM9 +systems. It's a low cost board.
> +
> +Boot Methods :
> +------------
> +Mini2440 can boot from NOR or NAND.
> +
> +Build :
> +-----
> +./MAKEALL mini2440
> +
> +or
> +
> +make mini2440_config
> +make
> diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
> new file mode 100644
> index 0000000..980b4a5
> --- /dev/null
> +++ b/include/configs/mini2440.h
> @@ -0,0 +1,186 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + * Gary Jennejohn <gj@denx.de>
> + * David Mueller <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009-2010
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * Configuation settings for the MINI2440 board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_SYS_TEXT_BASE 0x0
> +#define CONFIG_S3C2440_GPIO
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARM920T /* This is an ARM920T Core
*/
> +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
> +#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
> +#define CONFIG_MINI2440 /* on a MIN2440 Board */
> +
> +#define MACH_TYPE_MINI2440 1999
> +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
> +
> +/*
> + * We don't use lowlevel_init
> + */
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +/*
> + * input clock of PLL
> + */
> +/* MINI2440 has 12.0000MHz input clock */
> +#define CONFIG_SYS_CLK_FREQ 12000000
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_DRIVER_DM9000
> +#define CONFIG_DRIVER_DM9000_NO_EEPROM
> +#define CONFIG_DM9000_BASE 0x20000300
> +#define DM9000_IO CONFIG_DM9000_BASE
> +#define DM9000_DATA (CONFIG_DM9000_BASE+4)
> +
> +/*
> + * select serial console configuration
> + */
> +#define CONFIG_S3C24X0_SERIAL
> +#define CONFIG_SERIAL1
> +
> +/*
> + * allow to overwrite serial and ethaddr
> + */
> +#define CONFIG_ENV_OVERWRITE
> +
> +/*
> + * Command definition
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PORTIO
> +#define CONFIG_CMD_REGINFO
> +#define CONFIG_CMD_SAVES
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_LONGHELP
> +#define CONFIG_SYS_PROMPT "MINI2440 => "
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> +#define CONFIG_SYS_MAXARGS 32
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START 0x30000000
> +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM
*/
> +
> +/* default load address */
> +#define CONFIG_SYS_LOAD_ADDR 0x32000000
> +
> +/* boot parameters address */
> +#define CONFIG_BOOT_PARAM_ADDR 0x30000100
> +
> +/*
> + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
> + * it to wrap 100 times (total 1562500) to get 1 sec.
> + */
> +#define CONFIG_SYS_HZ 1562500
> +
> +/*
> + * valid baudrates
> + */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +#define CONFIG_BAUDRATE 115200
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
> +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> +#endif
> +
> +/*
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM
> */ +#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
> +#define CONFIG_SYS_SDRAM_BASE 0x30000000
> +#define CONFIG_SYS_FLASH_BASE 0x0
> +
> +/*
> + * Stack should be on the SRAM because
> + * DRAM is not init
> + */
> +#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 -
GENERATED_GBL_DATA_SIZE)
> +
> +/*
> + * NOR FLASH organization
> + * Now uses the standard CFI interface
> + * FLASH and environment organization
> + */
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> +#define CONFIG_SYS_MONITOR_BASE 0x0
> +/* max number of memory banks */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +/* 512 * 4096 sectors, or 32 * 64k blocks */
> +#define CONFIG_SYS_MAX_FLASH_SECT 512
> +#define CONFIG_FLASH_SHOW_PROGRESS 1
> +
> +/*
> + * Config for NOR flash
> + */
> +#define CONFIG_ENV_IS_IN_FLASH
> +#define CONFIG_MY_ENV_OFFSET 0x40000
> +/* addr of environment */
> +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE +
CONFIG_MY_ENV_OFFSET)
> +/* 16k Total Size of Environment Sector */
> +#define CONFIG_ENV_SIZE 0x4000
> +
> +/* ATAG configuration */
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_AUTO_COMPLETE
> +
> +#endif /* __CONFIG_H */
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440).
2012-04-30 14:11 ` [U-Boot] [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440) Gabriel Huau
2012-04-30 14:17 ` Marek Vasut
@ 2012-05-02 0:17 ` Minkyu Kang
1 sibling, 0 replies; 50+ messages in thread
From: Minkyu Kang @ 2012-05-02 0:17 UTC (permalink / raw)
To: u-boot
On 30 April 2012 23:11, Gabriel Huau <contact@huau-gabriel.fr> wrote:
> Support of the MINI2440 board from FriendlyARM from
> an old version of u-boot :
> http://repo.or.cz/r/u-boot-openmoko/mini2440.git
>
> Currently, supporting only boot from NOR.
>
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> Changes for v2:
> ? ? ? ?- Coding style cleanup
> ? ? ? ?- Remove unnecessary files modification
> ? ? ? ?- Remove unnecessary board configuration set
>
> Changes for v3:
> ? ? ? ?- Coding style cleanup
> ? ? ? ?- Move some macro definition from lowlevel_init.S
> ? ? ? ?to a new header
> ? ? ? ?- Remove some "magic bloat" with I/O board initialization
> ? ? ? ?- Add a pll_delay and replace loop by it
> ? ? ? ?- Somme cleanup in the configuration file
> ? ? ? ?- Cancel modifications on an SoC specific header
> ? ? ? ?- Add my name to copyright
>
> Changes for v4:
> ? ? ? ?- Move dram init to dram_init() instead low_levelinit
> ? ? ? ?- Remove u ? ? ?-boot env from configuration file and change
> ? ? ? ?the address of initial SP
> ? ? ? ?- Remove PLL init, now it's SoC specific
>
> Changes for v5:
> ? ? ? ?- Clean up configuration file
> ? ? ? ?- Add a MAINTAINERS entry
> ? ? ? ?- Add a README.mini2440 file
> ? ? ? ?- Use gpio/iomux interface in case of magic numbers
> ? ? ? ?- Use get_ram_size()
>
> Changes for v6:
> ? ? ? ?- Coding style cleanup
> ? ? ? ?- Remove some unused define in the board config
>
> Changes for v7:
> ? ? ? ?- Cleanup coding style
> ? ? ? ?- Changement of the commit message
>
> Changes for v8:
> ? ? ? ?- Replace define[tab] by define[space]
>
> Changes for v9:
> ? ? ? ?- Add a nice commit message
>
> ?MAINTAINERS ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?4 +
> ?board/friendlyarm/mini2440/Makefile ? | ? 44 ++++++++
> ?board/friendlyarm/mini2440/mini2440.c | ?134 ++++++++++++++++++++++++
> ?board/friendlyarm/mini2440/mini2440.h | ?144 +++++++++++++++++++++++++
> ?boards.cfg ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
> ?doc/README.mini2440 ? ? ? ? ? ? ? ? ? | ? 28 +++++
> ?include/configs/mini2440.h ? ? ? ? ? ?| ?186 +++++++++++++++++++++++++++++++++
> ?7 files changed, 541 insertions(+)
> ?create mode 100644 board/friendlyarm/mini2440/Makefile
> ?create mode 100644 board/friendlyarm/mini2440/mini2440.c
> ?create mode 100644 board/friendlyarm/mini2440/mini2440.h
> ?create mode 100644 doc/README.mini2440
> ?create mode 100644 include/configs/mini2440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 708ded7..2611fb5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -566,6 +566,10 @@ Unknown / orphaned boards:
> ?# ? ? ?Board ? ? ? ? ? CPU ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? #
> ?#########################################################################
>
> +Gabriel HUAU <contact@huau-gabriel.fr>
> +
> + ? ? ? mini2440 ? ? ? ?s3c2440
> +
Please keep this list to alphabetically. (by last name)
> ?Albert ARIBAUD <albert.u.boot@aribaud.net>
>
> ? ? ? ?edminiv2 ? ? ? ?ARM926EJS (Orion5x SoC)
Thanks.
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-04-30 14:11 ` [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
2012-04-30 14:11 ` [U-Boot] [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-04-30 14:16 ` Marek Vasut
2012-05-02 1:21 ` Minkyu Kang
2 siblings, 0 replies; 50+ messages in thread
From: Marek Vasut @ 2012-04-30 14:16 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
> It's now possible to use the gpio driver interface
> for s3c2440. This patch add iomux definitions too.
All right, I guess I can't rub my sadistic reviewing pleasures on you anymore
;-)
Acked-by: Marek Vasut <marex@denx.de>
>
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> Changes for v2:
> - Modification of the coding style
> - Add my email address to copyright
> - Remove a typedef
> - Move some defines to driver file
>
> Changes for v3:
> - Cleanup coding style
> - Changement of the commit message
>
> Changes for v4:
> - Add a nice commit message
>
> arch/arm/include/asm/arch-s3c24x0/gpio.h | 171 ++++++++++++++++++++++++
> arch/arm/include/asm/arch-s3c24x0/iomux.h | 200
> +++++++++++++++++++++++++++++ drivers/gpio/Makefile |
> 1 +
> drivers/gpio/s3c2440_gpio.c | 94 ++++++++++++++
> 4 files changed, 466 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
> create mode 100644 drivers/gpio/s3c2440_gpio.c
>
> diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h
> b/arch/arm/include/asm/arch-s3c24x0/gpio.h new file mode 100644
> index 0000000..76bc52c
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
> @@ -0,0 +1,171 @@
> +/*
> + * Copyright (c) 2012.
> + *
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_GPIO_H_
> +#define _S3C24X0_GPIO_H_
> +
> +enum s3c2440_gpio {
> + GPA0,
> + GPA1,
> + GPA2,
> + GPA3,
> + GPA4,
> + GPA5,
> + GPA6,
> + GPA7,
> + GPA8,
> + GPA9,
> + GPA10,
> + GPA11,
> + GPA12,
> + GPA13,
> + GPA14,
> + GPA15,
> + GPA16,
> + GPA17,
> + GPA18,
> + GPA19,
> + GPA20,
> + GPA21,
> + GPA22,
> + GPA23,
> + GPA24,
> +
> + GPB0 = 32,
> + GPB1,
> + GPB2,
> + GPB3,
> + GPB4,
> + GPB5,
> + GPB6,
> + GPB7,
> + GPB8,
> + GPB9,
> + GPB10,
> +
> + GPC0 = 64,
> + GPC1,
> + GPC2,
> + GPC3,
> + GPC4,
> + GPC5,
> + GPC6,
> + GPC7,
> + GPC8,
> + GPC9,
> + GPC10,
> + GPC11,
> + GPC12,
> + GPC13,
> + GPC14,
> + GPC15,
> +
> + GPD0 = 96,
> + GPD1,
> + GPD2,
> + GPD3,
> + GPD4,
> + GPD5,
> + GPD6,
> + GPD7,
> + GPD8,
> + GPD9,
> + GPD10,
> + GPD11,
> + GPD12,
> + GPD13,
> + GPD14,
> + GPD15,
> +
> + GPE0 = 128,
> + GPE1,
> + GPE2,
> + GPE3,
> + GPE4,
> + GPE5,
> + GPE6,
> + GPE7,
> + GPE8,
> + GPE9,
> + GPE10,
> + GPE11,
> + GPE12,
> + GPE13,
> + GPE14,
> + GPE15,
> +
> + GPF0 = 160,
> + GPF1,
> + GPF2,
> + GPF3,
> + GPF4,
> + GPF5,
> + GPF6,
> + GPF7,
> +
> + GPG0 = 192,
> + GPG1,
> + GPG2,
> + GPG3,
> + GPG4,
> + GPG5,
> + GPG6,
> + GPG7,
> + GPG8,
> + GPG9,
> + GPG10,
> + GPG11,
> + GPG12,
> + GPG13,
> + GPG14,
> + GPG15,
> +
> + GPH0 = 224,
> + GPH1,
> + GPH2,
> + GPH3,
> + GPH4,
> + GPH5,
> + GPH6,
> + GPH7,
> + GPH8,
> + GPH9,
> + GPH10,
> +
> + GPJ0 = 256,
> + GPJ1,
> + GPJ2,
> + GPJ3,
> + GPJ4,
> + GPJ5,
> + GPJ6,
> + GPJ7,
> + GPJ8,
> + GPJ9,
> + GPJ10,
> + GPJ11,
> + GPJ12,
> +};
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h
> b/arch/arm/include/asm/arch-s3c24x0/iomux.h new file mode 100644
> index 0000000..cc22de7
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
> @@ -0,0 +1,200 @@
> +/*
> + * Copyright (c) 2012
> + *
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_IOMUX_H_
> +#define _S3C24X0_IOMUX_H_
> +
> +enum s3c2440_iomux_func {
> + /* PORT A */
> + IOMUXA_ADDR0 = 1,
> + IOMUXA_ADDR16 = (1 << 1),
> + IOMUXA_ADDR17 = (1 << 2),
> + IOMUXA_ADDR18 = (1 << 3),
> + IOMUXA_ADDR19 = (1 << 4),
> + IOMUXA_ADDR20 = (1 << 5),
> + IOMUXA_ADDR21 = (1 << 6),
> + IOMUXA_ADDR22 = (1 << 7),
> + IOMUXA_ADDR23 = (1 << 8),
> + IOMUXA_ADDR24 = (1 << 9),
> + IOMUXA_ADDR25 = (1 << 10),
> + IOMUXA_ADDR26 = (1 << 11),
> + IOMUXA_nGCS1 = (1 << 12),
> + IOMUXA_nGCS2 = (1 << 13),
> + IOMUXA_nGCS3 = (1 << 14),
> + IOMUXA_nGCS4 = (1 << 15),
> + IOMUXA_nGCS5 = (1 << 16),
> + IOMUXA_CLE = (1 << 17),
> + IOMUXA_ALE = (1 << 18),
> + IOMUXA_nFWE = (1 << 19),
> + IOMUXA_nFRE = (1 << 20),
> + IOMUXA_nRSTOUT = (1 << 21),
> + IOMUXA_nFCE = (1 << 22),
> +
> + /* PORT B */
> + IOMUXB_nXDREQ0 = (2 << 20),
> + IOMUXB_nXDACK0 = (2 << 18),
> + IOMUXB_nXDREQ1 = (2 << 16),
> + IOMUXB_nXDACK1 = (2 << 14),
> + IOMUXB_nXBREQ = (2 << 12),
> + IOMUXB_nXBACK = (2 << 10),
> + IOMUXB_TCLK0 = (2 << 8),
> + IOMUXB_TOUT3 = (2 << 6),
> + IOMUXB_TOUT2 = (2 << 4),
> + IOMUXB_TOUT1 = (2 << 2),
> + IOMUXB_TOUT0 = 2,
> +
> + /* PORT C */
> + IOMUXC_VS7 = (2 << 30),
> + IOMUXC_VS6 = (2 << 28),
> + IOMUXC_VS5 = (2 << 26),
> + IOMUXC_VS4 = (2 << 24),
> + IOMUXC_VS3 = (2 << 22),
> + IOMUXC_VS2 = (2 << 20),
> + IOMUXC_VS1 = (2 << 18),
> + IOMUXC_VS0 = (2 << 16),
> + IOMUXC_LCD_LPCREVB = (2 << 14),
> + IOMUXC_LCD_LPCREV = (2 << 12),
> + IOMUXC_LCD_LPCOE = (2 << 10),
> + IOMUXC_VM = (2 << 8),
> + IOMUXC_VFRAME = (2 << 6),
> + IOMUXC_VLINE = (2 << 4),
> + IOMUXC_VCLK = (2 << 2),
> + IOMUXC_LEND = 2,
> + IOMUXC_I2SSDI = (3 << 8),
> +
> + /* PORT D */
> + IOMUXD_VS23 = (2 << 30),
> + IOMUXD_VS22 = (2 << 28),
> + IOMUXD_VS21 = (2 << 26),
> + IOMUXD_VS20 = (2 << 24),
> + IOMUXD_VS19 = (2 << 22),
> + IOMUXD_VS18 = (2 << 20),
> + IOMUXD_VS17 = (2 << 18),
> + IOMUXD_VS16 = (2 << 16),
> + IOMUXD_VS15 = (2 << 14),
> + IOMUXD_VS14 = (2 << 12),
> + IOMUXD_VS13 = (2 << 10),
> + IOMUXD_VS12 = (2 << 8),
> + IOMUXD_VS11 = (2 << 6),
> + IOMUXD_VS10 = (2 << 4),
> + IOMUXD_VS9 = (2 << 2),
> + IOMUXD_VS8 = 2,
> + IOMUXD_nSS0 = (3 << 30),
> + IOMUXD_nSS1 = (3 << 28),
> + IOMUXD_SPICLK1 = (3 << 20),
> + IOMUXD_SPIMOSI1 = (3 << 18),
> + IOMUXD_SPIMISO1 = (3 << 16),
> +
> + /* PORT E */
> + IOMUXE_IICSDA = (2 << 30),
> + IOMUXE_IICSCL = (2 << 28),
> + IOMUXE_SPICLK0 = (2 << 26),
> + IOMUXE_SPIMOSI0 = (2 << 24),
> + IOMUXE_SPIMISO0 = (2 << 22),
> + IOMUXE_SDDAT3 = (2 << 20),
> + IOMUXE_SDDAT2 = (2 << 18),
> + IOMUXE_SDDAT1 = (2 << 16),
> + IOMUXE_SDDAT0 = (2 << 14),
> + IOMUXE_SDCMD = (2 << 12),
> + IOMUXE_SDCLK = (2 << 10),
> + IOMUXE_I2SDO = (2 << 8),
> + IOMUXE_I2SDI = (2 << 6),
> + IOMUXE_CDCLK = (2 << 4),
> + IOMUXE_I2SSCLK = (2 << 2),
> + IOMUXE_I2SLRCK = 2,
> + IOMUXE_AC_SDATA_OUT = (3 << 8),
> + IOMUXE_AC_SDATA_IN = (3 << 6),
> + IOMUXE_AC_nRESET = (3 << 4),
> + IOMUXE_AC_BIT_CLK = (3 << 2),
> + IOMUXE_AC_SYNC = 3,
> +
> + /* PORT F */
> + IOMUXF_EINT7 = (2 << 14),
> + IOMUXF_EINT6 = (2 << 12),
> + IOMUXF_EINT5 = (2 << 10),
> + IOMUXF_EINT4 = (2 << 8),
> + IOMUXF_EINT3 = (2 << 6),
> + IOMUXF_EINT2 = (2 << 4),
> + IOMUXF_EINT1 = (2 << 2),
> + IOMUXF_EINT0 = 2,
> +
> + /* PORT G */
> + IOMUXG_EINT23 = (2 << 30),
> + IOMUXG_EINT22 = (2 << 28),
> + IOMUXG_EINT21 = (2 << 26),
> + IOMUXG_EINT20 = (2 << 24),
> + IOMUXG_EINT19 = (2 << 22),
> + IOMUXG_EINT18 = (2 << 20),
> + IOMUXG_EINT17 = (2 << 18),
> + IOMUXG_EINT16 = (2 << 16),
> + IOMUXG_EINT15 = (2 << 14),
> + IOMUXG_EINT14 = (2 << 12),
> + IOMUXG_EINT13 = (2 << 10),
> + IOMUXG_EINT12 = (2 << 8),
> + IOMUXG_EINT11 = (2 << 6),
> + IOMUXG_EINT10 = (2 << 4),
> + IOMUXG_EINT9 = (2 << 2),
> + IOMUXG_EINT8 = 2,
> + IOMUXG_TCLK1 = (3 << 22),
> + IOMUXG_nCTS1 = (3 << 20),
> + IOMUXG_nRTS1 = (3 << 18),
> + IOMUXG_SPICLK1 = (3 << 14),
> + IOMUXG_SPIMOSI1 = (3 << 12),
> + IOMUXG_SPIMISO1 = (3 << 10),
> + IOMUXG_LCD_PWRDN = (3 << 8),
> + IOMUXG_nSS1 = (3 << 6),
> + IOMUXG_nSS0 = (3 << 4),
> +
> + /* PORT H */
> + IOMUXH_CLKOUT1 = (2 << 20),
> + IOMUXH_CLKOUT0 = (2 << 18),
> + IOMUXH_UEXTCLK = (2 << 16),
> + IOMUXH_RXD2 = (2 << 14),
> + IOMUXH_TXD2 = (2 << 12),
> + IOMUXH_RXD1 = (2 << 10),
> + IOMUXH_TXD1 = (2 << 8),
> + IOMUXH_RXD0 = (2 << 6),
> + IOMUXH_TXD0 = (2 << 4),
> + IOMUXH_nRTS0 = (2 << 2),
> + IOMUXH_nCTS0 = 2,
> + IOMUXH_nCTS1 = (3 << 14),
> + IOMUXH_nRTS1 = (3 << 12),
> +
> + /* PORT J */
> + IOMUXJ_CAMRESET = (2 << 24),
> + IOMUXJ_CAMCLKOUT = (2 << 22),
> + IOMUXJ_CAMHREF = (2 << 20),
> + IOMUXJ_CAMVSYNC = (2 << 18),
> + IOMUXJ_CAMPCLK = (2 << 16),
> + IOMUXJ_CAMDATA7 = (2 << 14),
> + IOMUXJ_CAMDATA6 = (2 << 12),
> + IOMUXJ_CAMDATA5 = (2 << 10),
> + IOMUXJ_CAMDATA4 = (2 << 8),
> + IOMUXJ_CAMDATA3 = (2 << 6),
> + IOMUXJ_CAMDATA2 = (2 << 4),
> + IOMUXJ_CAMDATA1 = (2 << 2),
> + IOMUXJ_CAMDATA0 = 2
> +};
> +
> +#endif
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index fb3b09a..7ae6f84 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
> COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
> COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
> COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
> +COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
>
> COBJS := $(COBJS-y)
> SRCS := $(COBJS:.o=.c)
> diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
> new file mode 100644
> index 0000000..12a9043
> --- /dev/null
> +++ b/drivers/gpio/s3c2440_gpio.c
> @@ -0,0 +1,94 @@
> +/*
> + * Copyright (C) 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +
> +#define GPIO_INPUT 0x0
> +#define GPIO_OUTPUT 0x1
> +
> +/* 0x4 means that we want DAT and not CON register */
> +#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
> +#define GPIO_BIT(x) ((x) & 0x3f)
> +
> +/*
> + * It's how we calculate the full port address
> + * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
> + * We move it at the second digit, and finally we add 0x4 because we want
> + * to modify GPIO DAT and not CON
> + */
> +#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) <<
> 1)) +
> +int gpio_set_value(unsigned gpio, int value)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> + unsigned port = GPIO_FULLPORT(gpio);
> +
> + /*
> + * All GPIO Port have a configuration on
> + * 2 bits excepted the first GPIO (A) which
> + * have only 1 bit of configuration.
> + */
> + if (value)
> + if (!GPIO_PORT(gpio))
> + l |= (0x1 << GPIO_BIT(gpio));
> + else
> + l |= (0x3 << GPIO_BIT(gpio));
> + else
> + if (!GPIO_PORT(gpio))
> + l &= ~(0x1 << GPIO_BIT(gpio));
> + else
> + l &= ~(0x3 << GPIO_BIT(gpio));
> + return writel(port, l);
> +}
> +
> +int gpio_get_value(unsigned gpio)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> +
> + if (GPIO_PORT(gpio) == 0) /* PORT A */
> + return (l >> GPIO_BIT(gpio)) & 0x1;
> + return (l >> GPIO_BIT(gpio)) & 0x3;
> +}
> +
> +int gpio_request(unsigned gpio, const char *label)
> +{
> + return 0;
> +}
> +
> +int gpio_free(unsigned gpio)
> +{
> + return 0;
> +}
> +
> +int gpio_direction_input(unsigned gpio)
> +{
> + return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
> +}
> +
> +int gpio_direction_output(unsigned gpio, int value)
> +{
> + writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
> + return gpio_set_value(gpio, value);
> +}
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-04-30 14:11 ` [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
2012-04-30 14:11 ` [U-Boot] [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440) Gabriel Huau
2012-04-30 14:16 ` [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Marek Vasut
@ 2012-05-02 1:21 ` Minkyu Kang
2012-05-02 2:44 ` Marek Vasut
2 siblings, 1 reply; 50+ messages in thread
From: Minkyu Kang @ 2012-05-02 1:21 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
On 30 April 2012 23:11, Gabriel Huau <contact@huau-gabriel.fr> wrote:
> It's now possible to use the gpio driver interface
> for s3c2440. This patch add iomux definitions too.
>
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> Changes for v2:
> ? ? ? ?- Modification of the coding style
> ? ? ? ?- Add my email address to copyright
> ? ? ? ?- Remove a typedef
> ? ? ? ?- Move some defines to driver file
>
> Changes for v3:
> ? ? ? ?- Cleanup coding style
> ? ? ? ?- Changement of the commit message
>
> Changes for v4:
> ? ? ? ?- Add a nice commit message
>
> ?arch/arm/include/asm/arch-s3c24x0/gpio.h ?| ?171 ++++++++++++++++++++++++
> ?arch/arm/include/asm/arch-s3c24x0/iomux.h | ?200 +++++++++++++++++++++++++++++
> ?drivers/gpio/Makefile ? ? ? ? ? ? ? ? ? ? | ? ?1 +
> ?drivers/gpio/s3c2440_gpio.c ? ? ? ? ? ? ? | ? 94 ++++++++++++++
> ?4 files changed, 466 insertions(+)
> ?create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
> ?create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
> ?create mode 100644 drivers/gpio/s3c2440_gpio.c
>
> diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
> new file mode 100644
> index 0000000..12a9043
> --- /dev/null
> +++ b/drivers/gpio/s3c2440_gpio.c
> @@ -0,0 +1,94 @@
> +/*
> + * Copyright (C) 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +
> +#define GPIO_INPUT ?0x0
> +#define GPIO_OUTPUT 0x1
> +
> +/* 0x4 means that we want DAT and not CON register */
> +#define GPIO_PORT(x) ? ((((x) >> 5) & 0x3) + 0x4)
> +#define GPIO_BIT(x) ? ? ? ? ? ?((x) & 0x3f)
> +
> +/*
> + * It's how we calculate the full port address
> + * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
> + * We move it at the second digit, and finally we add 0x4 because we want
> + * to modify GPIO DAT and not CON
> + */
> +#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) << 1))
> +
> +int gpio_set_value(unsigned gpio, int value)
> +{
> + ? ? ? unsigned l = readl(GPIO_FULLPORT(gpio));
> + ? ? ? unsigned port = GPIO_FULLPORT(gpio);
> +
> + ? ? ? /*
> + ? ? ? ?* All GPIO Port have a configuration on
> + ? ? ? ?* 2 bits excepted the first GPIO (A) which
> + ? ? ? ?* have only 1 bit of configuration.
> + ? ? ? ?*/
> + ? ? ? if (value)
> + ? ? ? ? ? ? ? if (!GPIO_PORT(gpio))
> + ? ? ? ? ? ? ? ? ? ? ? l |= (0x1 << GPIO_BIT(gpio));
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? l |= (0x3 << GPIO_BIT(gpio));
> + ? ? ? else
> + ? ? ? ? ? ? ? if (!GPIO_PORT(gpio))
> + ? ? ? ? ? ? ? ? ? ? ? l &= ~(0x1 << GPIO_BIT(gpio));
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? l &= ~(0x3 << GPIO_BIT(gpio));
Need brace@this if..else statement.
> + ? ? ? return writel(port, l);
> +}
> +
> +int gpio_get_value(unsigned gpio)
> +{
> + ? ? ? unsigned l = readl(GPIO_FULLPORT(gpio));
> +
> + ? ? ? if (GPIO_PORT(gpio) == 0) /* PORT A */
> + ? ? ? ? ? ? ? return (l >> GPIO_BIT(gpio)) & 0x1;
> + ? ? ? return (l >> GPIO_BIT(gpio)) & 0x3;
> +}
> +
> +int gpio_request(unsigned gpio, const char *label)
> +{
> + ? ? ? return 0;
> +}
> +
> +int gpio_free(unsigned gpio)
> +{
> + ? ? ? return 0;
> +}
> +
> +int gpio_direction_input(unsigned gpio)
> +{
> + ? ? ? return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
> +}
> +
> +int gpio_direction_output(unsigned gpio, int value)
> +{
> + ? ? ? writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
> + ? ? ? return gpio_set_value(gpio, value);
> +}
> --
> 1.7.9.5
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Thanks.
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-05-02 1:21 ` Minkyu Kang
@ 2012-05-02 2:44 ` Marek Vasut
2012-05-02 6:16 ` Minkyu Kang
0 siblings, 1 reply; 50+ messages in thread
From: Marek Vasut @ 2012-05-02 2:44 UTC (permalink / raw)
To: u-boot
Dear Minkyu Kang,
> Dear Gabriel Huau,
>
> On 30 April 2012 23:11, Gabriel Huau <contact@huau-gabriel.fr> wrote:
> > It's now possible to use the gpio driver interface
> > for s3c2440. This patch add iomux definitions too.
> >
> > Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> > ---
> > Changes for v2:
> > - Modification of the coding style
> > - Add my email address to copyright
> > - Remove a typedef
> > - Move some defines to driver file
> >
> > Changes for v3:
> > - Cleanup coding style
> > - Changement of the commit message
> >
> > Changes for v4:
> > - Add a nice commit message
> >
> > arch/arm/include/asm/arch-s3c24x0/gpio.h | 171
> > ++++++++++++++++++++++++ arch/arm/include/asm/arch-s3c24x0/iomux.h |
> > 200 +++++++++++++++++++++++++++++ drivers/gpio/Makefile
> > | 1 +
> > drivers/gpio/s3c2440_gpio.c | 94 ++++++++++++++
> > 4 files changed, 466 insertions(+)
> > create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
> > create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
> > create mode 100644 drivers/gpio/s3c2440_gpio.c
> >
> > diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
> > new file mode 100644
> > index 0000000..12a9043
> > --- /dev/null
> > +++ b/drivers/gpio/s3c2440_gpio.c
> > @@ -0,0 +1,94 @@
> > +/*
> > + * Copyright (C) 2012
> > + * Gabriel Huau <contact@huau-gabriel.fr>
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +#include <common.h>
> > +#include <asm/arch/s3c2440.h>
> > +#include <asm/gpio.h>
> > +#include <asm/io.h>
> > +
> > +#define GPIO_INPUT 0x0
> > +#define GPIO_OUTPUT 0x1
> > +
> > +/* 0x4 means that we want DAT and not CON register */
> > +#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
> > +#define GPIO_BIT(x) ((x) & 0x3f)
> > +
> > +/*
> > + * It's how we calculate the full port address
> > + * We have to get the number of the port + 1 (Port A is at 0x56000001
> > ...) + * We move it at the second digit, and finally we add 0x4 because
> > we want + * to modify GPIO DAT and not CON
> > + */
> > +#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) <<
> > 1)) +
> > +int gpio_set_value(unsigned gpio, int value)
> > +{
> > + unsigned l = readl(GPIO_FULLPORT(gpio));
> > + unsigned port = GPIO_FULLPORT(gpio);
> > +
> > + /*
> > + * All GPIO Port have a configuration on
> > + * 2 bits excepted the first GPIO (A) which
> > + * have only 1 bit of configuration.
> > + */
> > + if (value)
> > + if (!GPIO_PORT(gpio))
> > + l |= (0x1 << GPIO_BIT(gpio));
> > + else
> > + l |= (0x3 << GPIO_BIT(gpio));
> > + else
> > + if (!GPIO_PORT(gpio))
> > + l &= ~(0x1 << GPIO_BIT(gpio));
> > + else
> > + l &= ~(0x3 << GPIO_BIT(gpio));
>
> Need brace at this if..else statement.
I wanted to ask why, but ... C isn't python, good point ;-)
> > + return writel(port, l);
> > +}
> > +
> > +int gpio_get_value(unsigned gpio)
> > +{
> > + unsigned l = readl(GPIO_FULLPORT(gpio));
> > +
> > + if (GPIO_PORT(gpio) == 0) /* PORT A */
> > + return (l >> GPIO_BIT(gpio)) & 0x1;
> > + return (l >> GPIO_BIT(gpio)) & 0x3;
> > +}
> > +
> > +int gpio_request(unsigned gpio, const char *label)
> > +{
> > + return 0;
> > +}
> > +
> > +int gpio_free(unsigned gpio)
> > +{
> > + return 0;
> > +}
> > +
> > +int gpio_direction_input(unsigned gpio)
> > +{
> > + return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
> > +}
> > +
> > +int gpio_direction_output(unsigned gpio, int value)
> > +{
> > + writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
> > + return gpio_set_value(gpio, value);
> > +}
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
>
> Thanks.
> Minkyu Kang.
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-05-02 2:44 ` Marek Vasut
@ 2012-05-02 6:16 ` Minkyu Kang
2012-05-02 18:40 ` Scott Wood
0 siblings, 1 reply; 50+ messages in thread
From: Minkyu Kang @ 2012-05-02 6:16 UTC (permalink / raw)
To: u-boot
Dear Marek,
On 2 May 2012 11:44, Marek Vasut <marex@denx.de> wrote:
>> > +int gpio_set_value(unsigned gpio, int value)
>> > +{
>> > + ? ? ? unsigned l = readl(GPIO_FULLPORT(gpio));
>> > + ? ? ? unsigned port = GPIO_FULLPORT(gpio);
>> > +
>> > + ? ? ? /*
>> > + ? ? ? ?* All GPIO Port have a configuration on
>> > + ? ? ? ?* 2 bits excepted the first GPIO (A) which
>> > + ? ? ? ?* have only 1 bit of configuration.
>> > + ? ? ? ?*/
>> > + ? ? ? if (value)
>> > + ? ? ? ? ? ? ? if (!GPIO_PORT(gpio))
>> > + ? ? ? ? ? ? ? ? ? ? ? l |= (0x1 << GPIO_BIT(gpio));
>> > + ? ? ? ? ? ? ? else
>> > + ? ? ? ? ? ? ? ? ? ? ? l |= (0x3 << GPIO_BIT(gpio));
>> > + ? ? ? else
>> > + ? ? ? ? ? ? ? if (!GPIO_PORT(gpio))
>> > + ? ? ? ? ? ? ? ? ? ? ? l &= ~(0x1 << GPIO_BIT(gpio));
>> > + ? ? ? ? ? ? ? else
>> > + ? ? ? ? ? ? ? ? ? ? ? l &= ~(0x3 << GPIO_BIT(gpio));
>>
>> Need brace at this if..else statement.
>
> I wanted to ask why, but ... C isn't python, good point ;-)
As I know, it's a rule of u-boot.. maybe. :)
Thanks.
Minkyu Kang.
--
from. prom.
www.promsoft.net
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-05-02 6:16 ` Minkyu Kang
@ 2012-05-02 18:40 ` Scott Wood
2012-05-02 20:16 ` Gabriel Huau
0 siblings, 1 reply; 50+ messages in thread
From: Scott Wood @ 2012-05-02 18:40 UTC (permalink / raw)
To: u-boot
On 05/02/2012 01:16 AM, Minkyu Kang wrote:
> Dear Marek,
>
> On 2 May 2012 11:44, Marek Vasut <marex@denx.de> wrote:
>>>> +int gpio_set_value(unsigned gpio, int value)
>>>> +{
>>>> + unsigned l = readl(GPIO_FULLPORT(gpio));
>>>> + unsigned port = GPIO_FULLPORT(gpio);
>>>> +
>>>> + /*
>>>> + * All GPIO Port have a configuration on
>>>> + * 2 bits excepted the first GPIO (A) which
>>>> + * have only 1 bit of configuration.
>>>> + */
>>>> + if (value)
>>>> + if (!GPIO_PORT(gpio))
>>>> + l |= (0x1 << GPIO_BIT(gpio));
>>>> + else
>>>> + l |= (0x3 << GPIO_BIT(gpio));
>>>> + else
>>>> + if (!GPIO_PORT(gpio))
>>>> + l &= ~(0x1 << GPIO_BIT(gpio));
>>>> + else
>>>> + l &= ~(0x3 << GPIO_BIT(gpio));
>>>
>>> Need brace at this if..else statement.
>>
>> I wanted to ask why, but ... C isn't python, good point ;-)
>
> As I know, it's a rule of u-boot.. maybe. :)
It is a U-Boot rule (multi-line if/loop body), and also it's good to
avoid the ambiguous "if/if/else" construct, but wouldn't this be better as:
if (GPIO_PORT(gpio))
bit = 1 << GPIO_BIT(gpio);
else
bit = 3 << GPIO_BIT(gpio);
if (value)
l |= bit;
else
l &= ~bit;
?
-Scott
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-05-02 18:40 ` Scott Wood
@ 2012-05-02 20:16 ` Gabriel Huau
2012-05-02 20:21 ` Scott Wood
0 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-05-02 20:16 UTC (permalink / raw)
To: u-boot
On Wed, May 02, 2012 at 01:40:35PM -0500, Scott Wood wrote:
> On 05/02/2012 01:16 AM, Minkyu Kang wrote:
> > Dear Marek,
> >
> > On 2 May 2012 11:44, Marek Vasut <marex@denx.de> wrote:
> >>>> +int gpio_set_value(unsigned gpio, int value)
> >>>> +{
> >>>> + unsigned l = readl(GPIO_FULLPORT(gpio));
> >>>> + unsigned port = GPIO_FULLPORT(gpio);
> >>>> +
> >>>> + /*
> >>>> + * All GPIO Port have a configuration on
> >>>> + * 2 bits excepted the first GPIO (A) which
> >>>> + * have only 1 bit of configuration.
> >>>> + */
> >>>> + if (value)
> >>>> + if (!GPIO_PORT(gpio))
> >>>> + l |= (0x1 << GPIO_BIT(gpio));
> >>>> + else
> >>>> + l |= (0x3 << GPIO_BIT(gpio));
> >>>> + else
> >>>> + if (!GPIO_PORT(gpio))
> >>>> + l &= ~(0x1 << GPIO_BIT(gpio));
> >>>> + else
> >>>> + l &= ~(0x3 << GPIO_BIT(gpio));
> >>>
> >>> Need brace at this if..else statement.
> >>
> >> I wanted to ask why, but ... C isn't python, good point ;-)
> >
> > As I know, it's a rule of u-boot.. maybe. :)
>
> It is a U-Boot rule (multi-line if/loop body), and also it's good to
> avoid the ambiguous "if/if/else" construct, but wouldn't this be better as:
>
> if (GPIO_PORT(gpio))
> bit = 1 << GPIO_BIT(gpio);
> else
> bit = 3 << GPIO_BIT(gpio);
>
> if (value)
> l |= bit;
> else
> l &= ~bit;
>
> ?
>
For multi-line, we should maybe patch the checkpatch.pl to check this
statement. But, indeed, I will do the modification of Scott.
> -Scott
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-05-02 20:16 ` Gabriel Huau
@ 2012-05-02 20:21 ` Scott Wood
0 siblings, 0 replies; 50+ messages in thread
From: Scott Wood @ 2012-05-02 20:21 UTC (permalink / raw)
To: u-boot
On 05/02/2012 03:16 PM, Gabriel Huau wrote:
> On Wed, May 02, 2012 at 01:40:35PM -0500, Scott Wood wrote:
>> On 05/02/2012 01:16 AM, Minkyu Kang wrote:
>>> Dear Marek,
>>>
>>> On 2 May 2012 11:44, Marek Vasut <marex@denx.de> wrote:
>>>>>> +int gpio_set_value(unsigned gpio, int value)
>>>>>> +{
>>>>>> + unsigned l = readl(GPIO_FULLPORT(gpio));
>>>>>> + unsigned port = GPIO_FULLPORT(gpio);
>>>>>> +
>>>>>> + /*
>>>>>> + * All GPIO Port have a configuration on
>>>>>> + * 2 bits excepted the first GPIO (A) which
>>>>>> + * have only 1 bit of configuration.
>>>>>> + */
>>>>>> + if (value)
>>>>>> + if (!GPIO_PORT(gpio))
>>>>>> + l |= (0x1 << GPIO_BIT(gpio));
>>>>>> + else
>>>>>> + l |= (0x3 << GPIO_BIT(gpio));
>>>>>> + else
>>>>>> + if (!GPIO_PORT(gpio))
>>>>>> + l &= ~(0x1 << GPIO_BIT(gpio));
>>>>>> + else
>>>>>> + l &= ~(0x3 << GPIO_BIT(gpio));
>>>>>
>>>>> Need brace at this if..else statement.
>>>>
>>>> I wanted to ask why, but ... C isn't python, good point ;-)
>>>
>>> As I know, it's a rule of u-boot.. maybe. :)
>>
>> It is a U-Boot rule (multi-line if/loop body), and also it's good to
>> avoid the ambiguous "if/if/else" construct, but wouldn't this be better as:
>>
>> if (GPIO_PORT(gpio))
>> bit = 1 << GPIO_BIT(gpio);
>> else
>> bit = 3 << GPIO_BIT(gpio);
>>
>> if (value)
>> l |= bit;
>> else
>> l &= ~bit;
>>
>> ?
>>
>
> For multi-line, we should maybe patch the checkpatch.pl to check this
> statement. But, indeed, I will do the modification of Scott.
...with the "1" and "3" swapped in the first if/else, of course. :-P
-Scott
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (9 preceding siblings ...)
2012-04-30 14:11 ` [U-Boot] [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-04-30 15:44 ` Gabriel Huau
2012-05-02 20:48 ` [U-Boot] [PATCH 2/2 v10] ARM : " Gabriel Huau
` (2 subsequent siblings)
13 siblings, 0 replies; 50+ messages in thread
From: Gabriel Huau @ 2012-04-30 15:44 UTC (permalink / raw)
To: u-boot
Hi Minkyu Kang,
Can you review/apply theses patches please ? (Marex have already
tortured me ...) :
- [PATCH 1/2 v4] ARM : Add GPIO Driver and IOMUX definition for S3C2440
- [PATCH 2/2 v9] ARM : Add support for MINI2440 (s3c2440).
Thanks,
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v10] ARM : Add support for MINI2440 (s3c2440).
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (10 preceding siblings ...)
2012-04-30 15:44 ` [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-05-02 20:48 ` Gabriel Huau
2012-10-03 8:54 ` Albert ARIBAUD
2012-05-02 20:49 ` [U-Boot] [PATCH 1/2 v5] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
2012-05-21 20:38 ` [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
13 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-05-02 20:48 UTC (permalink / raw)
To: u-boot
Support of the MINI2440 board from FriendlyARM from
an old version of u-boot :
http://repo.or.cz/r/u-boot-openmoko/mini2440.git
Currently, supporting only boot from NOR.
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
Changes for v2:
- Coding style cleanup
- Remove unnecessary files modification
- Remove unnecessary board configuration set
Changes for v3:
- Coding style cleanup
- Move some macro definition from lowlevel_init.S
to a new header
- Remove some "magic bloat" with I/O board initialization
- Add a pll_delay and replace loop by it
- Somme cleanup in the configuration file
- Cancel modifications on an SoC specific header
- Add my name to copyright
Changes for v4:
- Move dram init to dram_init() instead low_levelinit
- Remove u -boot env from configuration file and change
the address of initial SP
- Remove PLL init, now it's SoC specific
Changes for v5:
- Clean up configuration file
- Add a MAINTAINERS entry
- Add a README.mini2440 file
- Use gpio/iomux interface in case of magic numbers
- Use get_ram_size()
Changes for v6:
- Coding style cleanup
- Remove some unused define in the board config
Changes for v7:
- Cleanup coding style
- Changement of the commit message
Changes for v8:
- Replace define[tab] by define[space]
Changes for v9:
- Add a nice commit message
Changes for v10:
- Sort the MAINTAINERS file
MAINTAINERS | 4 +
board/friendlyarm/mini2440/Makefile | 44 ++++++++
board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++
board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.mini2440 | 28 +++++
include/configs/mini2440.h | 186 +++++++++++++++++++++++++++++++++
7 files changed, 541 insertions(+)
create mode 100644 board/friendlyarm/mini2440/Makefile
create mode 100644 board/friendlyarm/mini2440/mini2440.c
create mode 100644 board/friendlyarm/mini2440/mini2440.h
create mode 100644 doc/README.mini2440
create mode 100644 include/configs/mini2440.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 708ded7..c31ae6f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -677,6 +677,10 @@ Vaibhav Hiremath <hvaibhav@ti.com>
am3517_evm ARM ARMV7 (AM35x SoC)
+Gabriel Huau <contact@huau-gabriel.fr>
+
+ mini2440 s3c2440
+
Grazvydas Ignotas <notasas@gmail.com>
omap3_pandora ARM ARMV7 (OMAP3xx SoC)
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 0000000..b88e569
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2012
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mini2440.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
new file mode 100644
index 0000000..e97d981
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include "mini2440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void pll_delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_early_init_f(void)
+{
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
+ clk_power->clkdivn = CLKDIVN_VAL;
+
+ /* configure UPLL */
+ clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+ /* some delay between MPLL and UPLL */
+ pll_delay(100);
+
+ /* configure MPLL */
+ clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay(10000);
+
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* IOMUX Port H : UART Configuration */
+ gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
+ IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
+
+ gpio_direction_output(GPH8, 0);
+ gpio_direction_output(GPH9, 0);
+ gpio_direction_output(GPH10, 0);
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
+
+ /*
+ * Configuring bus width and timing
+ * Initialize clocks for each bank 0..5
+ * Bank 3 and 4 are used for DM9000
+ */
+ writel(BANK_CONF, &memctl->bwscon);
+ writel(B0_CONF, &memctl->bankcon[0]);
+ writel(B1_CONF, &memctl->bankcon[1]);
+ writel(B2_CONF, &memctl->bankcon[2]);
+ writel(B3_CONF, &memctl->bankcon[3]);
+ writel(B4_CONF, &memctl->bankcon[4]);
+ writel(B5_CONF, &memctl->bankcon[5]);
+
+ /* Bank 6 and 7 are used for DRAM */
+ writel(SDRAM_64MB, &memctl->bankcon[6]);
+ writel(SDRAM_64MB, &memctl->bankcon[7]);
+
+ writel(MEM_TIMING, &memctl->refresh);
+ writel(BANKSIZE_CONF, &memctl->banksize);
+ writel(B6_MRSR, &memctl->mrsrb6);
+ writel(B7_MRSR, &memctl->mrsrb7);
+
+ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ return dm9000_initialize(bis);
+#else
+ return 0;
+#endif
+}
diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
new file mode 100644
index 0000000..db386ea
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.h
@@ -0,0 +1,144 @@
+#ifndef __MINI2440_BOARD_CONF_H__
+#define __MINI2440_BOARD_CONF_H__
+
+/* PLL Parameters */
+#define CLKDIVN_VAL 7
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
+
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
+#define U_M_SDIV 0x2
+
+/* BWSCON */
+#define DW8 0x0
+#define DW16 0x1
+#define DW32 0x2
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16 + WAIT + UBLB)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/*
+ * Bank Configuration
+ */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0 /* 0clk */
+#define B0_PMC 0x0 /* normal */
+
+#define B1_Tacs 0x0
+#define B1_Tcos 0x0
+#define B1_Tacc 0x7
+#define B1_Tcoh 0x0
+#define B1_Tah 0x0
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x3 /* 4clk */
+#define B3_Tacp 0x0
+#define B3_PMC 0x0
+
+#define B4_Tacs 0x0
+#define B4_Tcos 0x3
+#define B4_Tacc 0x7
+#define B4_Tcoh 0x1
+#define B4_Tah 0x3
+#define B4_Tacp 0x0
+#define B4_PMC 0x0
+
+#define B5_Tacs 0x0
+#define B5_Tcos 0x0
+#define B5_Tacc 0x7
+#define B5_Tcoh 0x0
+#define B5_Tah 0x0
+#define B5_Tacp 0x0
+#define B5_PMC 0x0
+
+/*
+ * SDRAM Configuration
+ */
+#define SDRAM_MT 0x3 /* SDRAM */
+#define SDRAM_Trcd 0x0 /* 2clk */
+#define SDRAM_SCAN_9 0x1 /* 9bit */
+#define SDRAM_SCAN_10 0x2 /* 10bit */
+
+#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+
+/*
+ * Refresh Parameter
+ */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x1 /* 3clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x0 /* unused */
+#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
+
+/*
+ * MRSR Parameter
+ */
+#define BL 0x0
+#define BT 0x0
+#define CL 0x3 /* 3 clocks */
+#define TM 0x0
+#define WBL 0x0
+
+/*
+ * BankSize Parameter
+ */
+#define BK76MAP 0x2 /* 128MB/128MB */
+#define SCLK_EN 0x1 /* SCLK active */
+#define SCKE_EN 0x1 /* SDRAM power down mode enable */
+#define BURST_EN 0x1 /* Burst enable */
+
+/*
+ * Register values
+ */
+#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
+ (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
+ (B7_BWSCON<<28)))
+
+#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
+ (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
+#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
+ (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
+#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
+ (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
+#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
+ (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
+#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
+ (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
+#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
+ (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
+
+#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
+ (Trc<<18) + (Tchr<<16) + REFCNT
+
+#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
+#define B6_MRSR (CL<<4)
+#define B7_MRSR (CL<<4)
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 3cf75c3..93eeb3c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -61,6 +61,7 @@ mx1ads arm arm920t - -
scb9328 arm arm920t - - imx
cm4008 arm arm920t - - ks8695
cm41xx arm arm920t - - ks8695
+mini2440 arm arm920t mini2440 friendlyarm s3c24x0
VCMA9 arm arm920t vcma9 mpl s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
omap1510inn arm arm925t - ti
diff --git a/doc/README.mini2440 b/doc/README.mini2440
new file mode 100644
index 0000000..311ca52
--- /dev/null
+++ b/doc/README.mini2440
@@ -0,0 +1,28 @@
+U-Boot for FriendlyARM Mini2440 (s3c2440)
+
+This file contains information for the port of U-Boot to FriendlyARM
+mini2440
+
+All information about the board can be found on :
+http://www.friendlyarm.net/products/mini2440
+
+To build u-boot : ./MAKEALL mini2440
+
+Overview :
+--------
+FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
+ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
+systems. It's a low cost board.
+
+Boot Methods :
+------------
+Mini2440 can boot from NOR or NAND.
+
+Build :
+-----
+./MAKEALL mini2440
+
+or
+
+make mini2440_config
+make
diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
new file mode 100644
index 0000000..980b4a5
--- /dev/null
+++ b/include/configs/mini2440.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009-2010
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * Configuation settings for the MINI2440 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_S3C2440_GPIO
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM920T /* This is an ARM920T Core */
+#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
+#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
+#define CONFIG_MINI2440 /* on a MIN2440 Board */
+
+#define MACH_TYPE_MINI2440 1999
+#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
+
+/*
+ * We don't use lowlevel_init
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * input clock of PLL
+ */
+/* MINI2440 has 12.0000MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_DM9000
+#define CONFIG_DRIVER_DM9000_NO_EEPROM
+#define CONFIG_DM9000_BASE 0x20000300
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+4)
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1
+
+/*
+ * allow to overwrite serial and ethaddr
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_LONGHELP
+#define CONFIG_SYS_PROMPT "MINI2440 => "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x30000000
+#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x32000000
+
+/* boot parameters address */
+#define CONFIG_BOOT_PARAM_ADDR 0x30000100
+
+/*
+ * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
+ * it to wrap 100 times (total 1562500) to get 1 sec.
+ */
+#define CONFIG_SYS_HZ 1562500
+
+/*
+ * valid baudrates
+ */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CONFIG_SYS_FLASH_BASE 0x0
+
+/*
+ * Stack should be on the SRAM because
+ * DRAM is not init
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NOR FLASH organization
+ * Now uses the standard CFI interface
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE 0x0
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* 512 * 4096 sectors, or 32 * 64k blocks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_FLASH_SHOW_PROGRESS 1
+
+/*
+ * Config for NOR flash
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_MY_ENV_OFFSET 0x40000
+/* addr of environment */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
+/* 16k Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE 0x4000
+
+/* ATAG configuration */
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 2/2 v10] ARM : Add support for MINI2440 (s3c2440).
2012-05-02 20:48 ` [U-Boot] [PATCH 2/2 v10] ARM : " Gabriel Huau
@ 2012-10-03 8:54 ` Albert ARIBAUD
0 siblings, 0 replies; 50+ messages in thread
From: Albert ARIBAUD @ 2012-10-03 8:54 UTC (permalink / raw)
To: u-boot
Hi Gabriel,
On Wed, 2 May 2012 22:48:37 +0200, Gabriel Huau
<contact@huau-gabriel.fr> wrote:
> Support of the MINI2440 board from FriendlyARM from
> an old version of u-boot :
> http://repo.or.cz/r/u-boot-openmoko/mini2440.git
>
> Currently, supporting only boot from NOR.
>
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> Changes for v2:
> - Coding style cleanup
> - Remove unnecessary files modification
> - Remove unnecessary board configuration set
>
> Changes for v3:
> - Coding style cleanup
> - Move some macro definition from lowlevel_init.S
> to a new header
> - Remove some "magic bloat" with I/O board initialization
> - Add a pll_delay and replace loop by it
> - Somme cleanup in the configuration file
> - Cancel modifications on an SoC specific header
> - Add my name to copyright
>
> Changes for v4:
> - Move dram init to dram_init() instead low_levelinit
> - Remove u -boot env from configuration file and change
> the address of initial SP
> - Remove PLL init, now it's SoC specific
>
> Changes for v5:
> - Clean up configuration file
> - Add a MAINTAINERS entry
> - Add a README.mini2440 file
> - Use gpio/iomux interface in case of magic numbers
> - Use get_ram_size()
>
> Changes for v6:
> - Coding style cleanup
> - Remove some unused define in the board config
>
> Changes for v7:
> - Cleanup coding style
> - Changement of the commit message
>
> Changes for v8:
> - Replace define[tab] by define[space]
>
> Changes for v9:
> - Add a nice commit message
>
> Changes for v10:
> - Sort the MAINTAINERS file
>
> MAINTAINERS | 4 +
> board/friendlyarm/mini2440/Makefile | 44 ++++++++
> board/friendlyarm/mini2440/mini2440.c | 134 ++++++++++++++++++++++++
> board/friendlyarm/mini2440/mini2440.h | 144 +++++++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.mini2440 | 28 +++++
> include/configs/mini2440.h | 186 +++++++++++++++++++++++++++++++++
> 7 files changed, 541 insertions(+)
> create mode 100644 board/friendlyarm/mini2440/Makefile
> create mode 100644 board/friendlyarm/mini2440/mini2440.c
> create mode 100644 board/friendlyarm/mini2440/mini2440.h
> create mode 100644 doc/README.mini2440
> create mode 100644 include/configs/mini2440.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 708ded7..c31ae6f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -677,6 +677,10 @@ Vaibhav Hiremath <hvaibhav@ti.com>
>
> am3517_evm ARM ARMV7 (AM35x SoC)
>
> +Gabriel Huau <contact@huau-gabriel.fr>
> +
> + mini2440 s3c2440
> +
> Grazvydas Ignotas <notasas@gmail.com>
>
> omap3_pandora ARM ARMV7 (OMAP3xx SoC)
> diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
> new file mode 100644
> index 0000000..b88e569
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/Makefile
> @@ -0,0 +1,44 @@
> +#
> +# (C) Copyright 2012
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := mini2440.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
> new file mode 100644
> index 0000000..e97d981
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.c
> @@ -0,0 +1,134 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/io.h>
> +#include <asm/gpio.h>
> +#include <netdev.h>
> +#include "mini2440.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static inline void pll_delay(unsigned long loops)
> +{
> + __asm__ volatile ("1:\n"
> + "subs %0, %1, #1\n"
> + "bne 1b" : "=r" (loops) : "0" (loops));
> +}
> +
> +int board_early_init_f(void)
> +{
> + struct s3c24x0_clock_power * const clk_power =
> + s3c24x0_get_base_clock_power();
> +
> + /* to reduce PLL lock time, adjust the LOCKTIME register */
> + clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
> + clk_power->clkdivn = CLKDIVN_VAL;
> +
> + /* configure UPLL */
> + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
> + /* some delay between MPLL and UPLL */
> + pll_delay(100);
> +
> + /* configure MPLL */
> + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
> +
> + /* some delay between MPLL and UPLL */
> + pll_delay(10000);
> +
> + return 0;
> +}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
> +
> + /* IOMUX Port H : UART Configuration */
> + gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
> + IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
> +
> + gpio_direction_output(GPH8, 0);
> + gpio_direction_output(GPH9, 0);
> + gpio_direction_output(GPH10, 0);
> +
> + /* adress of boot parameters */
> + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
> +
> + /*
> + * Configuring bus width and timing
> + * Initialize clocks for each bank 0..5
> + * Bank 3 and 4 are used for DM9000
> + */
> + writel(BANK_CONF, &memctl->bwscon);
> + writel(B0_CONF, &memctl->bankcon[0]);
> + writel(B1_CONF, &memctl->bankcon[1]);
> + writel(B2_CONF, &memctl->bankcon[2]);
> + writel(B3_CONF, &memctl->bankcon[3]);
> + writel(B4_CONF, &memctl->bankcon[4]);
> + writel(B5_CONF, &memctl->bankcon[5]);
> +
> + /* Bank 6 and 7 are used for DRAM */
> + writel(SDRAM_64MB, &memctl->bankcon[6]);
> + writel(SDRAM_64MB, &memctl->bankcon[7]);
> +
> + writel(MEM_TIMING, &memctl->refresh);
> + writel(BANKSIZE_CONF, &memctl->banksize);
> + writel(B6_MRSR, &memctl->mrsrb6);
> + writel(B7_MRSR, &memctl->mrsrb7);
> +
> + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
> + PHYS_SDRAM_SIZE);
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#ifdef CONFIG_DRIVER_DM9000
> + return dm9000_initialize(bis);
> +#else
> + return 0;
> +#endif
> +}
> diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
> new file mode 100644
> index 0000000..db386ea
> --- /dev/null
> +++ b/board/friendlyarm/mini2440/mini2440.h
> @@ -0,0 +1,144 @@
> +#ifndef __MINI2440_BOARD_CONF_H__
> +#define __MINI2440_BOARD_CONF_H__
> +
> +/* PLL Parameters */
> +#define CLKDIVN_VAL 7
> +#define M_MDIV 0x7f
> +#define M_PDIV 0x2
> +#define M_SDIV 0x1
> +
> +#define U_M_MDIV 0x38
> +#define U_M_PDIV 0x2
> +#define U_M_SDIV 0x2
> +
> +/* BWSCON */
> +#define DW8 0x0
> +#define DW16 0x1
> +#define DW32 0x2
> +#define WAIT (0x1<<2)
> +#define UBLB (0x1<<3)
> +
> +#define B1_BWSCON (DW32)
> +#define B2_BWSCON (DW16)
> +#define B3_BWSCON (DW16 + WAIT + UBLB)
> +#define B4_BWSCON (DW16 + WAIT + UBLB)
> +#define B5_BWSCON (DW16)
> +#define B6_BWSCON (DW32)
> +#define B7_BWSCON (DW32)
> +
> +/*
> + * Bank Configuration
> + */
> +#define B0_Tacs 0x0 /* 0clk */
> +#define B0_Tcos 0x0 /* 0clk */
> +#define B0_Tacc 0x7 /* 14clk */
> +#define B0_Tcoh 0x0 /* 0clk */
> +#define B0_Tah 0x0 /* 0clk */
> +#define B0_Tacp 0x0 /* 0clk */
> +#define B0_PMC 0x0 /* normal */
> +
> +#define B1_Tacs 0x0
> +#define B1_Tcos 0x0
> +#define B1_Tacc 0x7
> +#define B1_Tcoh 0x0
> +#define B1_Tah 0x0
> +#define B1_Tacp 0x0
> +#define B1_PMC 0x0
> +
> +#define B2_Tacs 0x0
> +#define B2_Tcos 0x0
> +#define B2_Tacc 0x7
> +#define B2_Tcoh 0x0
> +#define B2_Tah 0x0
> +#define B2_Tacp 0x0
> +#define B2_PMC 0x0
> +
> +#define B3_Tacs 0x0
> +#define B3_Tcos 0x3 /* 4clk */
> +#define B3_Tacc 0x7
> +#define B3_Tcoh 0x1 /* 1clk */
> +#define B3_Tah 0x3 /* 4clk */
> +#define B3_Tacp 0x0
> +#define B3_PMC 0x0
> +
> +#define B4_Tacs 0x0
> +#define B4_Tcos 0x3
> +#define B4_Tacc 0x7
> +#define B4_Tcoh 0x1
> +#define B4_Tah 0x3
> +#define B4_Tacp 0x0
> +#define B4_PMC 0x0
> +
> +#define B5_Tacs 0x0
> +#define B5_Tcos 0x0
> +#define B5_Tacc 0x7
> +#define B5_Tcoh 0x0
> +#define B5_Tah 0x0
> +#define B5_Tacp 0x0
> +#define B5_PMC 0x0
> +
> +/*
> + * SDRAM Configuration
> + */
> +#define SDRAM_MT 0x3 /* SDRAM */
> +#define SDRAM_Trcd 0x0 /* 2clk */
> +#define SDRAM_SCAN_9 0x1 /* 9bit */
> +#define SDRAM_SCAN_10 0x2 /* 10bit */
> +
> +#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
> +
> +/*
> + * Refresh Parameter
> + */
> +#define REFEN 0x1 /* Refresh enable */
> +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
> +#define Trp 0x1 /* 3clk */
> +#define Trc 0x3 /* 7clk */
> +#define Tchr 0x0 /* unused */
> +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
> +
> +/*
> + * MRSR Parameter
> + */
> +#define BL 0x0
> +#define BT 0x0
> +#define CL 0x3 /* 3 clocks */
> +#define TM 0x0
> +#define WBL 0x0
> +
> +/*
> + * BankSize Parameter
> + */
> +#define BK76MAP 0x2 /* 128MB/128MB */
> +#define SCLK_EN 0x1 /* SCLK active */
> +#define SCKE_EN 0x1 /* SDRAM power down mode enable */
> +#define BURST_EN 0x1 /* Burst enable */
> +
> +/*
> + * Register values
> + */
> +#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
> + (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
> + (B7_BWSCON<<28)))
> +
> +#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
> + (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
> +#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
> + (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
> +#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
> + (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
> +#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
> + (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
> +#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
> + (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
> +#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
> + (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
> +
> +#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
> + (Trc<<18) + (Tchr<<16) + REFCNT
> +
> +#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
> +#define B6_MRSR (CL<<4)
> +#define B7_MRSR (CL<<4)
> +
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 3cf75c3..93eeb3c 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -61,6 +61,7 @@ mx1ads arm arm920t - -
> scb9328 arm arm920t - - imx
> cm4008 arm arm920t - - ks8695
> cm41xx arm arm920t - - ks8695
> +mini2440 arm arm920t mini2440 friendlyarm s3c24x0
> VCMA9 arm arm920t vcma9 mpl s3c24x0
> smdk2410 arm arm920t - samsung s3c24x0
> omap1510inn arm arm925t - ti
> diff --git a/doc/README.mini2440 b/doc/README.mini2440
> new file mode 100644
> index 0000000..311ca52
> --- /dev/null
> +++ b/doc/README.mini2440
> @@ -0,0 +1,28 @@
> +U-Boot for FriendlyARM Mini2440 (s3c2440)
> +
> +This file contains information for the port of U-Boot to FriendlyARM
> +mini2440
> +
> +All information about the board can be found on :
> +http://www.friendlyarm.net/products/mini2440
> +
> +To build u-boot : ./MAKEALL mini2440
> +
> +Overview :
> +--------
> +FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
> +ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
> +systems. It's a low cost board.
> +
> +Boot Methods :
> +------------
> +Mini2440 can boot from NOR or NAND.
> +
> +Build :
> +-----
> +./MAKEALL mini2440
> +
> +or
> +
> +make mini2440_config
> +make
> diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h
> new file mode 100644
> index 0000000..980b4a5
> --- /dev/null
> +++ b/include/configs/mini2440.h
> @@ -0,0 +1,186 @@
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + * Gary Jennejohn <gj@denx.de>
> + * David Mueller <d.mueller@elsoft.ch>
> + *
> + * (C) Copyright 2009-2010
> + * Michel Pollet <buserror@gmail.com>
> + *
> + * (C) Copyright 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * Configuation settings for the MINI2440 board.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_SYS_TEXT_BASE 0x0
> +#define CONFIG_S3C2440_GPIO
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARM920T /* This is an ARM920T Core */
> +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
> +#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
> +#define CONFIG_MINI2440 /* on a MIN2440 Board */
> +
> +#define MACH_TYPE_MINI2440 1999
> +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
> +
> +/*
> + * We don't use lowlevel_init
> + */
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +/*
> + * input clock of PLL
> + */
> +/* MINI2440 has 12.0000MHz input clock */
> +#define CONFIG_SYS_CLK_FREQ 12000000
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
> +
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_DRIVER_DM9000
> +#define CONFIG_DRIVER_DM9000_NO_EEPROM
> +#define CONFIG_DM9000_BASE 0x20000300
> +#define DM9000_IO CONFIG_DM9000_BASE
> +#define DM9000_DATA (CONFIG_DM9000_BASE+4)
> +
> +/*
> + * select serial console configuration
> + */
> +#define CONFIG_S3C24X0_SERIAL
> +#define CONFIG_SERIAL1
> +
> +/*
> + * allow to overwrite serial and ethaddr
> + */
> +#define CONFIG_ENV_OVERWRITE
> +
> +/*
> + * Command definition
> + */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PORTIO
> +#define CONFIG_CMD_REGINFO
> +#define CONFIG_CMD_SAVES
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_LONGHELP
> +#define CONFIG_SYS_PROMPT "MINI2440 => "
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> +#define CONFIG_SYS_MAXARGS 32
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START 0x30000000
> +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
> +
> +/* default load address */
> +#define CONFIG_SYS_LOAD_ADDR 0x32000000
> +
> +/* boot parameters address */
> +#define CONFIG_BOOT_PARAM_ADDR 0x30000100
> +
> +/*
> + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
> + * it to wrap 100 times (total 1562500) to get 1 sec.
> + */
> +#define CONFIG_SYS_HZ 1562500
> +
> +/*
> + * valid baudrates
> + */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +#define CONFIG_BAUDRATE 115200
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128*1024) /* regular stack */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
> +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> +#endif
> +
> +/*
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
> +#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
> +#define CONFIG_SYS_SDRAM_BASE 0x30000000
> +#define CONFIG_SYS_FLASH_BASE 0x0
> +
> +/*
> + * Stack should be on the SRAM because
> + * DRAM is not init
> + */
> +#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
> +
> +/*
> + * NOR FLASH organization
> + * Now uses the standard CFI interface
> + * FLASH and environment organization
> + */
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
> +#define CONFIG_SYS_MONITOR_BASE 0x0
> +/* max number of memory banks */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +/* 512 * 4096 sectors, or 32 * 64k blocks */
> +#define CONFIG_SYS_MAX_FLASH_SECT 512
> +#define CONFIG_FLASH_SHOW_PROGRESS 1
> +
> +/*
> + * Config for NOR flash
> + */
> +#define CONFIG_ENV_IS_IN_FLASH
> +#define CONFIG_MY_ENV_OFFSET 0x40000
> +/* addr of environment */
> +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
> +/* 16k Total Size of Environment Sector */
> +#define CONFIG_ENV_SIZE 0x4000
> +
> +/* ATAG configuration */
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_AUTO_COMPLETE
> +
> +#endif /* __CONFIG_H */
Applied to u-boot-arm/master (with trivial rebasing), thanks!
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 1/2 v5] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (11 preceding siblings ...)
2012-05-02 20:48 ` [U-Boot] [PATCH 2/2 v10] ARM : " Gabriel Huau
@ 2012-05-02 20:49 ` Gabriel Huau
2012-10-03 8:55 ` Albert ARIBAUD
2012-05-21 20:38 ` [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
13 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-05-02 20:49 UTC (permalink / raw)
To: u-boot
It's now possible to use the gpio driver interface
for s3c2440. This patch add iomux definitions too.
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
---
Changes for v2:
- Modification of the coding style
- Add my email address to copyright
- Remove a typedef
- Move some defines to driver file
Changes for v3:
- Cleanup coding style
- Changement of the commit message
Changes for v4:
- Add a nice commit message
Changes for v5:
- Coding style modification about if-else braces
arch/arm/include/asm/arch-s3c24x0/gpio.h | 171 ++++++++++++++++++++++++
arch/arm/include/asm/arch-s3c24x0/iomux.h | 200 +++++++++++++++++++++++++++++
drivers/gpio/Makefile | 1 +
drivers/gpio/s3c2440_gpio.c | 95 ++++++++++++++
4 files changed, 467 insertions(+)
create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
create mode 100644 drivers/gpio/s3c2440_gpio.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 0000000..76bc52c
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+enum s3c2440_gpio {
+ GPA0,
+ GPA1,
+ GPA2,
+ GPA3,
+ GPA4,
+ GPA5,
+ GPA6,
+ GPA7,
+ GPA8,
+ GPA9,
+ GPA10,
+ GPA11,
+ GPA12,
+ GPA13,
+ GPA14,
+ GPA15,
+ GPA16,
+ GPA17,
+ GPA18,
+ GPA19,
+ GPA20,
+ GPA21,
+ GPA22,
+ GPA23,
+ GPA24,
+
+ GPB0 = 32,
+ GPB1,
+ GPB2,
+ GPB3,
+ GPB4,
+ GPB5,
+ GPB6,
+ GPB7,
+ GPB8,
+ GPB9,
+ GPB10,
+
+ GPC0 = 64,
+ GPC1,
+ GPC2,
+ GPC3,
+ GPC4,
+ GPC5,
+ GPC6,
+ GPC7,
+ GPC8,
+ GPC9,
+ GPC10,
+ GPC11,
+ GPC12,
+ GPC13,
+ GPC14,
+ GPC15,
+
+ GPD0 = 96,
+ GPD1,
+ GPD2,
+ GPD3,
+ GPD4,
+ GPD5,
+ GPD6,
+ GPD7,
+ GPD8,
+ GPD9,
+ GPD10,
+ GPD11,
+ GPD12,
+ GPD13,
+ GPD14,
+ GPD15,
+
+ GPE0 = 128,
+ GPE1,
+ GPE2,
+ GPE3,
+ GPE4,
+ GPE5,
+ GPE6,
+ GPE7,
+ GPE8,
+ GPE9,
+ GPE10,
+ GPE11,
+ GPE12,
+ GPE13,
+ GPE14,
+ GPE15,
+
+ GPF0 = 160,
+ GPF1,
+ GPF2,
+ GPF3,
+ GPF4,
+ GPF5,
+ GPF6,
+ GPF7,
+
+ GPG0 = 192,
+ GPG1,
+ GPG2,
+ GPG3,
+ GPG4,
+ GPG5,
+ GPG6,
+ GPG7,
+ GPG8,
+ GPG9,
+ GPG10,
+ GPG11,
+ GPG12,
+ GPG13,
+ GPG14,
+ GPG15,
+
+ GPH0 = 224,
+ GPH1,
+ GPH2,
+ GPH3,
+ GPH4,
+ GPH5,
+ GPH6,
+ GPH7,
+ GPH8,
+ GPH9,
+ GPH10,
+
+ GPJ0 = 256,
+ GPJ1,
+ GPJ2,
+ GPJ3,
+ GPJ4,
+ GPJ5,
+ GPJ6,
+ GPJ7,
+ GPJ8,
+ GPJ9,
+ GPJ10,
+ GPJ11,
+ GPJ12,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 0000000..cc22de7
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_IOMUX_H_
+#define _S3C24X0_IOMUX_H_
+
+enum s3c2440_iomux_func {
+ /* PORT A */
+ IOMUXA_ADDR0 = 1,
+ IOMUXA_ADDR16 = (1 << 1),
+ IOMUXA_ADDR17 = (1 << 2),
+ IOMUXA_ADDR18 = (1 << 3),
+ IOMUXA_ADDR19 = (1 << 4),
+ IOMUXA_ADDR20 = (1 << 5),
+ IOMUXA_ADDR21 = (1 << 6),
+ IOMUXA_ADDR22 = (1 << 7),
+ IOMUXA_ADDR23 = (1 << 8),
+ IOMUXA_ADDR24 = (1 << 9),
+ IOMUXA_ADDR25 = (1 << 10),
+ IOMUXA_ADDR26 = (1 << 11),
+ IOMUXA_nGCS1 = (1 << 12),
+ IOMUXA_nGCS2 = (1 << 13),
+ IOMUXA_nGCS3 = (1 << 14),
+ IOMUXA_nGCS4 = (1 << 15),
+ IOMUXA_nGCS5 = (1 << 16),
+ IOMUXA_CLE = (1 << 17),
+ IOMUXA_ALE = (1 << 18),
+ IOMUXA_nFWE = (1 << 19),
+ IOMUXA_nFRE = (1 << 20),
+ IOMUXA_nRSTOUT = (1 << 21),
+ IOMUXA_nFCE = (1 << 22),
+
+ /* PORT B */
+ IOMUXB_nXDREQ0 = (2 << 20),
+ IOMUXB_nXDACK0 = (2 << 18),
+ IOMUXB_nXDREQ1 = (2 << 16),
+ IOMUXB_nXDACK1 = (2 << 14),
+ IOMUXB_nXBREQ = (2 << 12),
+ IOMUXB_nXBACK = (2 << 10),
+ IOMUXB_TCLK0 = (2 << 8),
+ IOMUXB_TOUT3 = (2 << 6),
+ IOMUXB_TOUT2 = (2 << 4),
+ IOMUXB_TOUT1 = (2 << 2),
+ IOMUXB_TOUT0 = 2,
+
+ /* PORT C */
+ IOMUXC_VS7 = (2 << 30),
+ IOMUXC_VS6 = (2 << 28),
+ IOMUXC_VS5 = (2 << 26),
+ IOMUXC_VS4 = (2 << 24),
+ IOMUXC_VS3 = (2 << 22),
+ IOMUXC_VS2 = (2 << 20),
+ IOMUXC_VS1 = (2 << 18),
+ IOMUXC_VS0 = (2 << 16),
+ IOMUXC_LCD_LPCREVB = (2 << 14),
+ IOMUXC_LCD_LPCREV = (2 << 12),
+ IOMUXC_LCD_LPCOE = (2 << 10),
+ IOMUXC_VM = (2 << 8),
+ IOMUXC_VFRAME = (2 << 6),
+ IOMUXC_VLINE = (2 << 4),
+ IOMUXC_VCLK = (2 << 2),
+ IOMUXC_LEND = 2,
+ IOMUXC_I2SSDI = (3 << 8),
+
+ /* PORT D */
+ IOMUXD_VS23 = (2 << 30),
+ IOMUXD_VS22 = (2 << 28),
+ IOMUXD_VS21 = (2 << 26),
+ IOMUXD_VS20 = (2 << 24),
+ IOMUXD_VS19 = (2 << 22),
+ IOMUXD_VS18 = (2 << 20),
+ IOMUXD_VS17 = (2 << 18),
+ IOMUXD_VS16 = (2 << 16),
+ IOMUXD_VS15 = (2 << 14),
+ IOMUXD_VS14 = (2 << 12),
+ IOMUXD_VS13 = (2 << 10),
+ IOMUXD_VS12 = (2 << 8),
+ IOMUXD_VS11 = (2 << 6),
+ IOMUXD_VS10 = (2 << 4),
+ IOMUXD_VS9 = (2 << 2),
+ IOMUXD_VS8 = 2,
+ IOMUXD_nSS0 = (3 << 30),
+ IOMUXD_nSS1 = (3 << 28),
+ IOMUXD_SPICLK1 = (3 << 20),
+ IOMUXD_SPIMOSI1 = (3 << 18),
+ IOMUXD_SPIMISO1 = (3 << 16),
+
+ /* PORT E */
+ IOMUXE_IICSDA = (2 << 30),
+ IOMUXE_IICSCL = (2 << 28),
+ IOMUXE_SPICLK0 = (2 << 26),
+ IOMUXE_SPIMOSI0 = (2 << 24),
+ IOMUXE_SPIMISO0 = (2 << 22),
+ IOMUXE_SDDAT3 = (2 << 20),
+ IOMUXE_SDDAT2 = (2 << 18),
+ IOMUXE_SDDAT1 = (2 << 16),
+ IOMUXE_SDDAT0 = (2 << 14),
+ IOMUXE_SDCMD = (2 << 12),
+ IOMUXE_SDCLK = (2 << 10),
+ IOMUXE_I2SDO = (2 << 8),
+ IOMUXE_I2SDI = (2 << 6),
+ IOMUXE_CDCLK = (2 << 4),
+ IOMUXE_I2SSCLK = (2 << 2),
+ IOMUXE_I2SLRCK = 2,
+ IOMUXE_AC_SDATA_OUT = (3 << 8),
+ IOMUXE_AC_SDATA_IN = (3 << 6),
+ IOMUXE_AC_nRESET = (3 << 4),
+ IOMUXE_AC_BIT_CLK = (3 << 2),
+ IOMUXE_AC_SYNC = 3,
+
+ /* PORT F */
+ IOMUXF_EINT7 = (2 << 14),
+ IOMUXF_EINT6 = (2 << 12),
+ IOMUXF_EINT5 = (2 << 10),
+ IOMUXF_EINT4 = (2 << 8),
+ IOMUXF_EINT3 = (2 << 6),
+ IOMUXF_EINT2 = (2 << 4),
+ IOMUXF_EINT1 = (2 << 2),
+ IOMUXF_EINT0 = 2,
+
+ /* PORT G */
+ IOMUXG_EINT23 = (2 << 30),
+ IOMUXG_EINT22 = (2 << 28),
+ IOMUXG_EINT21 = (2 << 26),
+ IOMUXG_EINT20 = (2 << 24),
+ IOMUXG_EINT19 = (2 << 22),
+ IOMUXG_EINT18 = (2 << 20),
+ IOMUXG_EINT17 = (2 << 18),
+ IOMUXG_EINT16 = (2 << 16),
+ IOMUXG_EINT15 = (2 << 14),
+ IOMUXG_EINT14 = (2 << 12),
+ IOMUXG_EINT13 = (2 << 10),
+ IOMUXG_EINT12 = (2 << 8),
+ IOMUXG_EINT11 = (2 << 6),
+ IOMUXG_EINT10 = (2 << 4),
+ IOMUXG_EINT9 = (2 << 2),
+ IOMUXG_EINT8 = 2,
+ IOMUXG_TCLK1 = (3 << 22),
+ IOMUXG_nCTS1 = (3 << 20),
+ IOMUXG_nRTS1 = (3 << 18),
+ IOMUXG_SPICLK1 = (3 << 14),
+ IOMUXG_SPIMOSI1 = (3 << 12),
+ IOMUXG_SPIMISO1 = (3 << 10),
+ IOMUXG_LCD_PWRDN = (3 << 8),
+ IOMUXG_nSS1 = (3 << 6),
+ IOMUXG_nSS0 = (3 << 4),
+
+ /* PORT H */
+ IOMUXH_CLKOUT1 = (2 << 20),
+ IOMUXH_CLKOUT0 = (2 << 18),
+ IOMUXH_UEXTCLK = (2 << 16),
+ IOMUXH_RXD2 = (2 << 14),
+ IOMUXH_TXD2 = (2 << 12),
+ IOMUXH_RXD1 = (2 << 10),
+ IOMUXH_TXD1 = (2 << 8),
+ IOMUXH_RXD0 = (2 << 6),
+ IOMUXH_TXD0 = (2 << 4),
+ IOMUXH_nRTS0 = (2 << 2),
+ IOMUXH_nCTS0 = 2,
+ IOMUXH_nCTS1 = (3 << 14),
+ IOMUXH_nRTS1 = (3 << 12),
+
+ /* PORT J */
+ IOMUXJ_CAMRESET = (2 << 24),
+ IOMUXJ_CAMCLKOUT = (2 << 22),
+ IOMUXJ_CAMHREF = (2 << 20),
+ IOMUXJ_CAMVSYNC = (2 << 18),
+ IOMUXJ_CAMPCLK = (2 << 16),
+ IOMUXJ_CAMDATA7 = (2 << 14),
+ IOMUXJ_CAMDATA6 = (2 << 12),
+ IOMUXJ_CAMDATA5 = (2 << 10),
+ IOMUXJ_CAMDATA4 = (2 << 8),
+ IOMUXJ_CAMDATA3 = (2 << 6),
+ IOMUXJ_CAMDATA2 = (2 << 4),
+ IOMUXJ_CAMDATA1 = (2 << 2),
+ IOMUXJ_CAMDATA0 = 2
+};
+
+#endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb3b09a..7ae6f84 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
+COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
new file mode 100644
index 0000000..43bbf11
--- /dev/null
+++ b/drivers/gpio/s3c2440_gpio.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+
+/* 0x4 means that we want DAT and not CON register */
+#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
+#define GPIO_BIT(x) ((x) & 0x3f)
+
+/*
+ * It's how we calculate the full port address
+ * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
+ * We move it at the second digit, and finally we add 0x4 because we want
+ * to modify GPIO DAT and not CON
+ */
+#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) << 1))
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+ unsigned bit;
+ unsigned port = GPIO_FULLPORT(gpio);
+
+ /*
+ * All GPIO Port have a configuration on
+ * 2 bits excepted the first GPIO (A) which
+ * have only 1 bit of configuration.
+ */
+ if (!GPIO_PORT(gpio))
+ bit = (0x1 << GPIO_BIT(gpio));
+ else
+ bit = (0x3 << GPIO_BIT(gpio));
+
+ if (value)
+ l |= bit;
+ else
+ l &= ~bit;
+
+ return writel(port, l);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ unsigned l = readl(GPIO_FULLPORT(gpio));
+
+ if (GPIO_PORT(gpio) == 0) /* PORT A */
+ return (l >> GPIO_BIT(gpio)) & 0x1;
+ return (l >> GPIO_BIT(gpio)) & 0x3;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
+ return gpio_set_value(gpio, value);
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 1/2 v5] ARM : Add GPIO Driver and IOMUX definition for S3C2440
2012-05-02 20:49 ` [U-Boot] [PATCH 1/2 v5] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-10-03 8:55 ` Albert ARIBAUD
0 siblings, 0 replies; 50+ messages in thread
From: Albert ARIBAUD @ 2012-10-03 8:55 UTC (permalink / raw)
To: u-boot
Hi Gabriel,
On Wed, 2 May 2012 22:49:55 +0200, Gabriel Huau
<contact@huau-gabriel.fr> wrote:
> It's now possible to use the gpio driver interface
> for s3c2440. This patch add iomux definitions too.
>
> Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
> ---
> Changes for v2:
> - Modification of the coding style
> - Add my email address to copyright
> - Remove a typedef
> - Move some defines to driver file
>
> Changes for v3:
> - Cleanup coding style
> - Changement of the commit message
>
> Changes for v4:
> - Add a nice commit message
>
> Changes for v5:
> - Coding style modification about if-else braces
>
> arch/arm/include/asm/arch-s3c24x0/gpio.h | 171 ++++++++++++++++++++++++
> arch/arm/include/asm/arch-s3c24x0/iomux.h | 200 +++++++++++++++++++++++++++++
> drivers/gpio/Makefile | 1 +
> drivers/gpio/s3c2440_gpio.c | 95 ++++++++++++++
> 4 files changed, 467 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
> create mode 100644 drivers/gpio/s3c2440_gpio.c
>
> diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h
> new file mode 100644
> index 0000000..76bc52c
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h
> @@ -0,0 +1,171 @@
> +/*
> + * Copyright (c) 2012.
> + *
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_GPIO_H_
> +#define _S3C24X0_GPIO_H_
> +
> +enum s3c2440_gpio {
> + GPA0,
> + GPA1,
> + GPA2,
> + GPA3,
> + GPA4,
> + GPA5,
> + GPA6,
> + GPA7,
> + GPA8,
> + GPA9,
> + GPA10,
> + GPA11,
> + GPA12,
> + GPA13,
> + GPA14,
> + GPA15,
> + GPA16,
> + GPA17,
> + GPA18,
> + GPA19,
> + GPA20,
> + GPA21,
> + GPA22,
> + GPA23,
> + GPA24,
> +
> + GPB0 = 32,
> + GPB1,
> + GPB2,
> + GPB3,
> + GPB4,
> + GPB5,
> + GPB6,
> + GPB7,
> + GPB8,
> + GPB9,
> + GPB10,
> +
> + GPC0 = 64,
> + GPC1,
> + GPC2,
> + GPC3,
> + GPC4,
> + GPC5,
> + GPC6,
> + GPC7,
> + GPC8,
> + GPC9,
> + GPC10,
> + GPC11,
> + GPC12,
> + GPC13,
> + GPC14,
> + GPC15,
> +
> + GPD0 = 96,
> + GPD1,
> + GPD2,
> + GPD3,
> + GPD4,
> + GPD5,
> + GPD6,
> + GPD7,
> + GPD8,
> + GPD9,
> + GPD10,
> + GPD11,
> + GPD12,
> + GPD13,
> + GPD14,
> + GPD15,
> +
> + GPE0 = 128,
> + GPE1,
> + GPE2,
> + GPE3,
> + GPE4,
> + GPE5,
> + GPE6,
> + GPE7,
> + GPE8,
> + GPE9,
> + GPE10,
> + GPE11,
> + GPE12,
> + GPE13,
> + GPE14,
> + GPE15,
> +
> + GPF0 = 160,
> + GPF1,
> + GPF2,
> + GPF3,
> + GPF4,
> + GPF5,
> + GPF6,
> + GPF7,
> +
> + GPG0 = 192,
> + GPG1,
> + GPG2,
> + GPG3,
> + GPG4,
> + GPG5,
> + GPG6,
> + GPG7,
> + GPG8,
> + GPG9,
> + GPG10,
> + GPG11,
> + GPG12,
> + GPG13,
> + GPG14,
> + GPG15,
> +
> + GPH0 = 224,
> + GPH1,
> + GPH2,
> + GPH3,
> + GPH4,
> + GPH5,
> + GPH6,
> + GPH7,
> + GPH8,
> + GPH9,
> + GPH10,
> +
> + GPJ0 = 256,
> + GPJ1,
> + GPJ2,
> + GPJ3,
> + GPJ4,
> + GPJ5,
> + GPJ6,
> + GPJ7,
> + GPJ8,
> + GPJ9,
> + GPJ10,
> + GPJ11,
> + GPJ12,
> +};
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h
> new file mode 100644
> index 0000000..cc22de7
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h
> @@ -0,0 +1,200 @@
> +/*
> + * Copyright (c) 2012
> + *
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _S3C24X0_IOMUX_H_
> +#define _S3C24X0_IOMUX_H_
> +
> +enum s3c2440_iomux_func {
> + /* PORT A */
> + IOMUXA_ADDR0 = 1,
> + IOMUXA_ADDR16 = (1 << 1),
> + IOMUXA_ADDR17 = (1 << 2),
> + IOMUXA_ADDR18 = (1 << 3),
> + IOMUXA_ADDR19 = (1 << 4),
> + IOMUXA_ADDR20 = (1 << 5),
> + IOMUXA_ADDR21 = (1 << 6),
> + IOMUXA_ADDR22 = (1 << 7),
> + IOMUXA_ADDR23 = (1 << 8),
> + IOMUXA_ADDR24 = (1 << 9),
> + IOMUXA_ADDR25 = (1 << 10),
> + IOMUXA_ADDR26 = (1 << 11),
> + IOMUXA_nGCS1 = (1 << 12),
> + IOMUXA_nGCS2 = (1 << 13),
> + IOMUXA_nGCS3 = (1 << 14),
> + IOMUXA_nGCS4 = (1 << 15),
> + IOMUXA_nGCS5 = (1 << 16),
> + IOMUXA_CLE = (1 << 17),
> + IOMUXA_ALE = (1 << 18),
> + IOMUXA_nFWE = (1 << 19),
> + IOMUXA_nFRE = (1 << 20),
> + IOMUXA_nRSTOUT = (1 << 21),
> + IOMUXA_nFCE = (1 << 22),
> +
> + /* PORT B */
> + IOMUXB_nXDREQ0 = (2 << 20),
> + IOMUXB_nXDACK0 = (2 << 18),
> + IOMUXB_nXDREQ1 = (2 << 16),
> + IOMUXB_nXDACK1 = (2 << 14),
> + IOMUXB_nXBREQ = (2 << 12),
> + IOMUXB_nXBACK = (2 << 10),
> + IOMUXB_TCLK0 = (2 << 8),
> + IOMUXB_TOUT3 = (2 << 6),
> + IOMUXB_TOUT2 = (2 << 4),
> + IOMUXB_TOUT1 = (2 << 2),
> + IOMUXB_TOUT0 = 2,
> +
> + /* PORT C */
> + IOMUXC_VS7 = (2 << 30),
> + IOMUXC_VS6 = (2 << 28),
> + IOMUXC_VS5 = (2 << 26),
> + IOMUXC_VS4 = (2 << 24),
> + IOMUXC_VS3 = (2 << 22),
> + IOMUXC_VS2 = (2 << 20),
> + IOMUXC_VS1 = (2 << 18),
> + IOMUXC_VS0 = (2 << 16),
> + IOMUXC_LCD_LPCREVB = (2 << 14),
> + IOMUXC_LCD_LPCREV = (2 << 12),
> + IOMUXC_LCD_LPCOE = (2 << 10),
> + IOMUXC_VM = (2 << 8),
> + IOMUXC_VFRAME = (2 << 6),
> + IOMUXC_VLINE = (2 << 4),
> + IOMUXC_VCLK = (2 << 2),
> + IOMUXC_LEND = 2,
> + IOMUXC_I2SSDI = (3 << 8),
> +
> + /* PORT D */
> + IOMUXD_VS23 = (2 << 30),
> + IOMUXD_VS22 = (2 << 28),
> + IOMUXD_VS21 = (2 << 26),
> + IOMUXD_VS20 = (2 << 24),
> + IOMUXD_VS19 = (2 << 22),
> + IOMUXD_VS18 = (2 << 20),
> + IOMUXD_VS17 = (2 << 18),
> + IOMUXD_VS16 = (2 << 16),
> + IOMUXD_VS15 = (2 << 14),
> + IOMUXD_VS14 = (2 << 12),
> + IOMUXD_VS13 = (2 << 10),
> + IOMUXD_VS12 = (2 << 8),
> + IOMUXD_VS11 = (2 << 6),
> + IOMUXD_VS10 = (2 << 4),
> + IOMUXD_VS9 = (2 << 2),
> + IOMUXD_VS8 = 2,
> + IOMUXD_nSS0 = (3 << 30),
> + IOMUXD_nSS1 = (3 << 28),
> + IOMUXD_SPICLK1 = (3 << 20),
> + IOMUXD_SPIMOSI1 = (3 << 18),
> + IOMUXD_SPIMISO1 = (3 << 16),
> +
> + /* PORT E */
> + IOMUXE_IICSDA = (2 << 30),
> + IOMUXE_IICSCL = (2 << 28),
> + IOMUXE_SPICLK0 = (2 << 26),
> + IOMUXE_SPIMOSI0 = (2 << 24),
> + IOMUXE_SPIMISO0 = (2 << 22),
> + IOMUXE_SDDAT3 = (2 << 20),
> + IOMUXE_SDDAT2 = (2 << 18),
> + IOMUXE_SDDAT1 = (2 << 16),
> + IOMUXE_SDDAT0 = (2 << 14),
> + IOMUXE_SDCMD = (2 << 12),
> + IOMUXE_SDCLK = (2 << 10),
> + IOMUXE_I2SDO = (2 << 8),
> + IOMUXE_I2SDI = (2 << 6),
> + IOMUXE_CDCLK = (2 << 4),
> + IOMUXE_I2SSCLK = (2 << 2),
> + IOMUXE_I2SLRCK = 2,
> + IOMUXE_AC_SDATA_OUT = (3 << 8),
> + IOMUXE_AC_SDATA_IN = (3 << 6),
> + IOMUXE_AC_nRESET = (3 << 4),
> + IOMUXE_AC_BIT_CLK = (3 << 2),
> + IOMUXE_AC_SYNC = 3,
> +
> + /* PORT F */
> + IOMUXF_EINT7 = (2 << 14),
> + IOMUXF_EINT6 = (2 << 12),
> + IOMUXF_EINT5 = (2 << 10),
> + IOMUXF_EINT4 = (2 << 8),
> + IOMUXF_EINT3 = (2 << 6),
> + IOMUXF_EINT2 = (2 << 4),
> + IOMUXF_EINT1 = (2 << 2),
> + IOMUXF_EINT0 = 2,
> +
> + /* PORT G */
> + IOMUXG_EINT23 = (2 << 30),
> + IOMUXG_EINT22 = (2 << 28),
> + IOMUXG_EINT21 = (2 << 26),
> + IOMUXG_EINT20 = (2 << 24),
> + IOMUXG_EINT19 = (2 << 22),
> + IOMUXG_EINT18 = (2 << 20),
> + IOMUXG_EINT17 = (2 << 18),
> + IOMUXG_EINT16 = (2 << 16),
> + IOMUXG_EINT15 = (2 << 14),
> + IOMUXG_EINT14 = (2 << 12),
> + IOMUXG_EINT13 = (2 << 10),
> + IOMUXG_EINT12 = (2 << 8),
> + IOMUXG_EINT11 = (2 << 6),
> + IOMUXG_EINT10 = (2 << 4),
> + IOMUXG_EINT9 = (2 << 2),
> + IOMUXG_EINT8 = 2,
> + IOMUXG_TCLK1 = (3 << 22),
> + IOMUXG_nCTS1 = (3 << 20),
> + IOMUXG_nRTS1 = (3 << 18),
> + IOMUXG_SPICLK1 = (3 << 14),
> + IOMUXG_SPIMOSI1 = (3 << 12),
> + IOMUXG_SPIMISO1 = (3 << 10),
> + IOMUXG_LCD_PWRDN = (3 << 8),
> + IOMUXG_nSS1 = (3 << 6),
> + IOMUXG_nSS0 = (3 << 4),
> +
> + /* PORT H */
> + IOMUXH_CLKOUT1 = (2 << 20),
> + IOMUXH_CLKOUT0 = (2 << 18),
> + IOMUXH_UEXTCLK = (2 << 16),
> + IOMUXH_RXD2 = (2 << 14),
> + IOMUXH_TXD2 = (2 << 12),
> + IOMUXH_RXD1 = (2 << 10),
> + IOMUXH_TXD1 = (2 << 8),
> + IOMUXH_RXD0 = (2 << 6),
> + IOMUXH_TXD0 = (2 << 4),
> + IOMUXH_nRTS0 = (2 << 2),
> + IOMUXH_nCTS0 = 2,
> + IOMUXH_nCTS1 = (3 << 14),
> + IOMUXH_nRTS1 = (3 << 12),
> +
> + /* PORT J */
> + IOMUXJ_CAMRESET = (2 << 24),
> + IOMUXJ_CAMCLKOUT = (2 << 22),
> + IOMUXJ_CAMHREF = (2 << 20),
> + IOMUXJ_CAMVSYNC = (2 << 18),
> + IOMUXJ_CAMPCLK = (2 << 16),
> + IOMUXJ_CAMDATA7 = (2 << 14),
> + IOMUXJ_CAMDATA6 = (2 << 12),
> + IOMUXJ_CAMDATA5 = (2 << 10),
> + IOMUXJ_CAMDATA4 = (2 << 8),
> + IOMUXJ_CAMDATA3 = (2 << 6),
> + IOMUXJ_CAMDATA2 = (2 << 4),
> + IOMUXJ_CAMDATA1 = (2 << 2),
> + IOMUXJ_CAMDATA0 = 2
> +};
> +
> +#endif
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index fb3b09a..7ae6f84 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
> COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
> COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
> COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
> +COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
>
> COBJS := $(COBJS-y)
> SRCS := $(COBJS:.o=.c)
> diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
> new file mode 100644
> index 0000000..43bbf11
> --- /dev/null
> +++ b/drivers/gpio/s3c2440_gpio.c
> @@ -0,0 +1,95 @@
> +/*
> + * Copyright (C) 2012
> + * Gabriel Huau <contact@huau-gabriel.fr>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/arch/s3c2440.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +
> +#define GPIO_INPUT 0x0
> +#define GPIO_OUTPUT 0x1
> +
> +/* 0x4 means that we want DAT and not CON register */
> +#define GPIO_PORT(x) ((((x) >> 5) & 0x3) + 0x4)
> +#define GPIO_BIT(x) ((x) & 0x3f)
> +
> +/*
> + * It's how we calculate the full port address
> + * We have to get the number of the port + 1 (Port A is at 0x56000001 ...)
> + * We move it at the second digit, and finally we add 0x4 because we want
> + * to modify GPIO DAT and not CON
> + */
> +#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) << 1))
> +
> +int gpio_set_value(unsigned gpio, int value)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> + unsigned bit;
> + unsigned port = GPIO_FULLPORT(gpio);
> +
> + /*
> + * All GPIO Port have a configuration on
> + * 2 bits excepted the first GPIO (A) which
> + * have only 1 bit of configuration.
> + */
> + if (!GPIO_PORT(gpio))
> + bit = (0x1 << GPIO_BIT(gpio));
> + else
> + bit = (0x3 << GPIO_BIT(gpio));
> +
> + if (value)
> + l |= bit;
> + else
> + l &= ~bit;
> +
> + return writel(port, l);
> +}
> +
> +int gpio_get_value(unsigned gpio)
> +{
> + unsigned l = readl(GPIO_FULLPORT(gpio));
> +
> + if (GPIO_PORT(gpio) == 0) /* PORT A */
> + return (l >> GPIO_BIT(gpio)) & 0x1;
> + return (l >> GPIO_BIT(gpio)) & 0x3;
> +}
> +
> +int gpio_request(unsigned gpio, const char *label)
> +{
> + return 0;
> +}
> +
> +int gpio_free(unsigned gpio)
> +{
> + return 0;
> +}
> +
> +int gpio_direction_input(unsigned gpio)
> +{
> + return writel(GPIO_FULLPORT(gpio), GPIO_INPUT << GPIO_BIT(gpio));
> +}
> +
> +int gpio_direction_output(unsigned gpio, int value)
> +{
> + writel(GPIO_FULLPORT(gpio), GPIO_OUTPUT << GPIO_BIT(gpio));
> + return gpio_set_value(gpio, value);
> +}
Applied to u-boot-arm/master (with trivial rebasing), thanks!
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-04-29 21:27 [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
` (12 preceding siblings ...)
2012-05-02 20:49 ` [U-Boot] [PATCH 1/2 v5] ARM : Add GPIO Driver and IOMUX definition for S3C2440 Gabriel Huau
@ 2012-05-21 20:38 ` Gabriel Huau
2012-05-21 21:55 ` Wolfgang Denk
13 siblings, 1 reply; 50+ messages in thread
From: Gabriel Huau @ 2012-05-21 20:38 UTC (permalink / raw)
To: u-boot
Is it ok ? Can we apply theses patches ?
On Sun, Apr 29, 2012 at 11:27:23PM +0200, Gabriel Huau wrote:
> From the last time, I removed the patch about the PLL initialization because
> it's board specific. I added a new patch for s3c440 gpio driver. Now in the
> board file we have no more magic bloat.
>
> >> +/*
> >> + * When booting from NAND, it is impossible to access the lowest addresses
> >> + * due to the SteppingStone being in the way. Luckily the NOR doesn't really
> >> + * care about the highest 16 bits of address, so we set the controlers
> >> + * registers to go and poke over there, instead.
> >> + */
> >> +#define PHYS_FLASH_1 0x0
> >> +#define CONFIG_SYS_FLASH_BASE 0x0
> >
> >Urghh... this sounds very much like a serious design issue?
>
> About this point, I ported it from the old version uboot as well. It may need
> some investigation, but I remember it was a big problem with this board. In the
> case of a NAND boot, we don't have access to NOR because the SteppingStone
> (SRAM) is mapped at the same range.
>
> Gabriel Huau (2):
> Add GPIO Driver and IOMUX definition for S3C2440
> Add support for MINI2440 (s3c2440).
>
> MAINTAINERS | 4 +
> arch/arm/include/asm/arch-s3c24x0/gpio.h | 183 +++++++++++++++++++++++++
> arch/arm/include/asm/arch-s3c24x0/iomux.h | 197 +++++++++++++++++++++++++++
> board/friendlyarm/mini2440/Makefile | 44 ++++++
> board/friendlyarm/mini2440/mini2440.c | 135 +++++++++++++++++++
> board/friendlyarm/mini2440/mini2440.h | 144 ++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.mini2440 | 28 ++++
> drivers/gpio/Makefile | 1 +
> drivers/gpio/s3c2440_gpio.c | 74 ++++++++++
> include/configs/mini2440.h | 209 +++++++++++++++++++++++++++++
> 11 files changed, 1020 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h
> create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h
> create mode 100644 board/friendlyarm/mini2440/Makefile
> create mode 100644 board/friendlyarm/mini2440/mini2440.c
> create mode 100644 board/friendlyarm/mini2440/mini2440.h
> create mode 100644 doc/README.mini2440
> create mode 100644 drivers/gpio/s3c2440_gpio.c
> create mode 100644 include/configs/mini2440.h
>
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 50+ messages in thread* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-05-21 20:38 ` [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440) Gabriel Huau
@ 2012-05-21 21:55 ` Wolfgang Denk
2012-05-22 18:04 ` Gabriel Huau
0 siblings, 1 reply; 50+ messages in thread
From: Wolfgang Denk @ 2012-05-21 21:55 UTC (permalink / raw)
To: u-boot
Dear Gabriel Huau,
In message <20120521203733.GC9379@debian> you wrote:
> Is it ok ? Can we apply theses patches ?
What do you mean - unfixed?
> On Sun, Apr 29, 2012 at 11:27:23PM +0200, Gabriel Huau wrote:
> > From the last time, I removed the patch about the PLL initialization because
> > it's board specific. I added a new patch for s3c440 gpio driver. Now in the
> > board file we have no more magic bloat.
> >
> > >> +/*
> > >> + * When booting from NAND, it is impossible to access the lowest addresses
> > >> + * due to the SteppingStone being in the way. Luckily the NOR doesn't really
> > >> + * care about the highest 16 bits of address, so we set the controlers
> > >> + * registers to go and poke over there, instead.
> > >> + */
> > >> +#define PHYS_FLASH_1 0x0
> > >> +#define CONFIG_SYS_FLASH_BASE 0x0
> > >
> > >Urghh... this sounds very much like a serious design issue?
> >
> > About this point, I ported it from the old version uboot as well. It may need
> > some investigation, but I remember it was a big problem with this board. In the
> > case of a NAND boot, we don't have access to NOR because the SteppingStone
> > (SRAM) is mapped at the same range.
The comment and/or definitions are apparently broken, so they should
be fixed / removed.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I will not say that women have no character; rather, they have a new
one every day. -- Heine
^ permalink raw reply [flat|nested] 50+ messages in thread
* [U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
2012-05-21 21:55 ` Wolfgang Denk
@ 2012-05-22 18:04 ` Gabriel Huau
0 siblings, 0 replies; 50+ messages in thread
From: Gabriel Huau @ 2012-05-22 18:04 UTC (permalink / raw)
To: u-boot
Hi,
I sent patches v5 and v10 and I have no more review since a few weeks,
so I think it's ok now, no ?
About the comment/definitions, it has been fixed in last patches :).
Best regards,
On Mon, May 21, 2012 at 11:55:10PM +0200, Wolfgang Denk wrote:
> Dear Gabriel Huau,
>
> In message <20120521203733.GC9379@debian> you wrote:
> > Is it ok ? Can we apply theses patches ?
>
> What do you mean - unfixed?
>
> > On Sun, Apr 29, 2012 at 11:27:23PM +0200, Gabriel Huau wrote:
> > > From the last time, I removed the patch about the PLL initialization because
> > > it's board specific. I added a new patch for s3c440 gpio driver. Now in the
> > > board file we have no more magic bloat.
> > >
> > > >> +/*
> > > >> + * When booting from NAND, it is impossible to access the lowest addresses
> > > >> + * due to the SteppingStone being in the way. Luckily the NOR doesn't really
> > > >> + * care about the highest 16 bits of address, so we set the controlers
> > > >> + * registers to go and poke over there, instead.
> > > >> + */
> > > >> +#define PHYS_FLASH_1 0x0
> > > >> +#define CONFIG_SYS_FLASH_BASE 0x0
> > > >
> > > >Urghh... this sounds very much like a serious design issue?
> > >
> > > About this point, I ported it from the old version uboot as well. It may need
> > > some investigation, but I remember it was a big problem with this board. In the
> > > case of a NAND boot, we don't have access to NOR because the SteppingStone
> > > (SRAM) is mapped at the same range.
>
> The comment and/or definitions are apparently broken, so they should
> be fixed / removed.
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> I will not say that women have no character; rather, they have a new
> one every day. -- Heine
^ permalink raw reply [flat|nested] 50+ messages in thread