* [PATCH 0/5] eDP improvements
@ 2012-10-20 18:57 Daniel Vetter
2012-10-20 18:57 ` [PATCH 1/5] drm/i915: make edp panel power sequence setup more robust Daniel Vetter
` (6 more replies)
0 siblings, 7 replies; 17+ messages in thread
From: Daniel Vetter @ 2012-10-20 18:57 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Hi all,
This is useful fallout of my futile attempts at getting the eDP panel on my ivb
working without the BIOS' help. I now at least get a backlit black screen though
;-)
Paulo said that this is good enough for his hsw eDP machine already, and it
definitely improves the code a bit and (hopefully) makes it a tad more robust.
Comments, flames and test results highly welcome.
Cheers, Daniel
Daniel Vetter (5):
drm/i915: make edp panel power sequence setup more robust
drm/i915: enable/disable backlight for eDP
drm/i915/eDP: compute the panel power clock divisor from the pch
rawclock
drm/i915/dp: compute the pch dp aux divider from the rawclk
drm/i915: extract intel_dp_init_panel_power_sequencer
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_display.c | 10 ++
drivers/gpu/drm/i915/intel_dp.c | 177 ++++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_drv.h | 2 +
4 files changed, 138 insertions(+), 56 deletions(-)
--
1.7.11.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/5] drm/i915: make edp panel power sequence setup more robust
2012-10-20 18:57 [PATCH 0/5] eDP improvements Daniel Vetter
@ 2012-10-20 18:57 ` Daniel Vetter
2012-10-22 22:04 ` Jesse Barnes
2012-10-20 18:57 ` [PATCH 2/5] drm/i915: enable/disable backlight for eDP Daniel Vetter
` (5 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-20 18:57 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
3 changes:
- If a given value is unset, use the maximal limits from the eDP spec.
- Write back the new values, since otherwise the panel power sequencing
hw will not dtrt.
- Revert the early bail-out in case the register values are unset.
The last change reverts
commit bfa3384a9a84aaaa59443bbd776c142e7dba4b0f
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Tue Apr 10 11:58:04 2012 -0700
drm/i915: check PPS regs for sanity when using eDP
v2:
- Unlock the PP regs as the very first thing. This is a required w/a
for cpu eDP on port A, and generally a good idea.
- Fixup the panel power control port selection bits.
v3: Paulo Zanoni noticed that I've fumbled the computation of the spec
limit values. Fix them up. We've also noticed that the t8/t9 values in
the vbt/bios-programmed pp are much larger than any limits. My guess
is that this is to conceal any backlight enable/disable delays. So by
using the much shorter limits from the spec, which only concerns the
sink, we risk that we might display before the backlight is fully on,
or disable the output while the backlight still has afterglow. I've
figured I don't care too much, since this will only happen when both
the pp regs are not programmed, and the vbt tables don't contain
anything useful.
v4: Don't set the port selection bits on hsw/LPT, they don't exist any
more.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++
drivers/gpu/drm/i915/intel_dp.c | 71 ++++++++++++++++++++++++++++++++++-------
2 files changed, 65 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b428fbb..3ecd8c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4018,6 +4018,11 @@
#define PANEL_LIGHT_ON_DELAY_SHIFT 0
#define PCH_PP_OFF_DELAYS 0xc720c
+#define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30)
+#define PANEL_POWER_PORT_LVDS (0 << 30)
+#define PANEL_POWER_PORT_DP_A (1 << 30)
+#define PANEL_POWER_PORT_DP_C (2 << 30)
+#define PANEL_POWER_PORT_DP_D (3 << 30)
#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
#define PANEL_POWER_DOWN_DELAY_SHIFT 16
#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f2c9ea6..265cec1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2671,20 +2671,18 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
/* Cache some DPCD data in the eDP case */
if (is_edp(intel_dp)) {
- struct edp_power_seq cur, vbt;
- u32 pp_on, pp_off, pp_div;
+ struct edp_power_seq cur, vbt, spec, final;
+ u32 pp_on, pp_off, pp_div, pp;
+
+ /* Workaround: Need to write PP_CONTROL with the unlock key as
+ * the very first thing. */
+ pp = ironlake_get_pp_control(dev_priv);
+ I915_WRITE(PCH_PP_CONTROL, pp);
pp_on = I915_READ(PCH_PP_ON_DELAYS);
pp_off = I915_READ(PCH_PP_OFF_DELAYS);
pp_div = I915_READ(PCH_PP_DIVISOR);
- if (!pp_on || !pp_off || !pp_div) {
- DRM_INFO("bad panel power sequencing delays, disabling panel\n");
- intel_dp_encoder_destroy(&intel_dp->base.base);
- intel_dp_destroy(&intel_connector->base);
- return;
- }
-
/* Pull timing values out of registers */
cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
PANEL_POWER_UP_DELAY_SHIFT;
@@ -2706,16 +2704,62 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
vbt = dev_priv->edp.pps;
+ /* Upper limits from eDP 1.3 spec. Note that we the clunky units
+ * of our hw here, which are all in 100usec. */
+ spec.t1_t3 = 210 * 10;
+ spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
+ spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
+ spec.t10 = 500 * 10;
+ /* This one is special and actually in units of 100ms, but zero
+ * based in the hw (so we need to add 100 ms). But the sw vbt
+ * table multiplies it with 1000 to make it in units of 100usec,
+ * too. */
+ spec.t11_t12 = (510 + 100) * 10;
+
DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
-#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
-
+ /* Use the max of the register setttings and vbt. If both are
+ * unset, fall back to the spec limits. */
+#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
+ spec.field : \
+ max(cur.field, vbt.field))
+ assign_final(t1_t3);
+ assign_final(t8);
+ assign_final(t9);
+ assign_final(t10);
+ assign_final(t11_t12);
+#undef assign_final
+
+#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
intel_dp->panel_power_up_delay = get_delay(t1_t3);
intel_dp->backlight_on_delay = get_delay(t8);
intel_dp->backlight_off_delay = get_delay(t9);
intel_dp->panel_power_down_delay = get_delay(t10);
intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
+#undef get_delay
+
+ /* And finally store the new values in the power sequencer. */
+ pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
+ (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
+ pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
+ (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
+ pp_div = (pp_div & PP_REFERENCE_DIVIDER_MASK) |
+ (DIV_ROUND_UP(final.t11_t12, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT);
+
+ /* Haswell doesn't have any port selection bits for the panel
+ * power sequence any more. */
+ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+ if (is_cpu_edp(intel_dp))
+ pp_on |= PANEL_POWER_PORT_DP_A;
+ else
+ pp_on |= PANEL_POWER_PORT_DP_D;
+ }
+
+ I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
+ I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
+ I915_WRITE(PCH_PP_DIVISOR, pp_div);
+
DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
@@ -2723,6 +2767,11 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
+
+ DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
+ I915_READ(PCH_PP_ON_DELAYS),
+ I915_READ(PCH_PP_OFF_DELAYS),
+ I915_READ(PCH_PP_DIVISOR));
}
intel_dp_i2c_init(intel_dp, intel_connector, name);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/5] drm/i915: enable/disable backlight for eDP
2012-10-20 18:57 [PATCH 0/5] eDP improvements Daniel Vetter
2012-10-20 18:57 ` [PATCH 1/5] drm/i915: make edp panel power sequence setup more robust Daniel Vetter
@ 2012-10-20 18:57 ` Daniel Vetter
2012-10-22 22:04 ` Jesse Barnes
2012-10-20 18:57 ` [PATCH 3/5] drm/i915/eDP: compute the panel power clock divisor from the pch rawclock Daniel Vetter
` (4 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-20 18:57 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Like we already do for the LVDS panels. This seems to help greatly
in setting up the backlight, since the BIOS might refuse to cooperate.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_dp.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 265cec1..49846c0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1128,6 +1128,8 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("Turn eDP power off\n");
+ intel_panel_disable_backlight(dev);
+
WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
pp = ironlake_get_pp_control(dev_priv);
@@ -1146,6 +1148,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe = to_intel_crtc(intel_dp->base.base.crtc)->pipe;
u32 pp;
if (!is_edp(intel_dp))
@@ -1163,6 +1166,8 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
pp |= EDP_BLC_ENABLE;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
+
+ intel_panel_enable_backlight(dev, pipe);
}
static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/5] drm/i915/eDP: compute the panel power clock divisor from the pch rawclock
2012-10-20 18:57 [PATCH 0/5] eDP improvements Daniel Vetter
2012-10-20 18:57 ` [PATCH 1/5] drm/i915: make edp panel power sequence setup more robust Daniel Vetter
2012-10-20 18:57 ` [PATCH 2/5] drm/i915: enable/disable backlight for eDP Daniel Vetter
@ 2012-10-20 18:57 ` Daniel Vetter
2012-10-22 22:07 ` Jesse Barnes
2012-10-20 18:57 ` [PATCH 4/5] drm/i915/dp: compute the pch dp aux divider from the rawclk Daniel Vetter
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-20 18:57 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
We need this when the bios forgets even to set that bit up. Most seem
to do that, even when they don't set up anything else in the panel
power sequencer.
Note that on IBX the rawclk is variable according to Bspec, but
everyone is using 125MHz. The rawclk is fixed to 125MHz on CPT, but
luckily we still have the same register available. On hsw, different
variants have different clocks, hence we need to check the register.
Since other pieces are driven by the rawclock, too, keep the little
helper in a central place.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++
drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9c17a0a7..7fb032f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -80,6 +80,16 @@ struct intel_limit {
/* FDI */
#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
+int
+intel_pch_rawclk(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ WARN_ON(!HAS_PCH_SPLIT(dev));
+
+ return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
+}
+
static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
int target, int refclk, intel_clock_t *match_clock,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 49846c0..b35d5bd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2749,8 +2749,12 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
(final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
(final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
- pp_div = (pp_div & PP_REFERENCE_DIVIDER_MASK) |
- (DIV_ROUND_UP(final.t11_t12, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT);
+ /* Compute the divisor for the pp clock, simply match the Bspec
+ * formula. */
+ pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
+ << PP_REFERENCE_DIVIDER_SHIFT;
+ pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
+ << PANEL_POWER_CYCLE_DELAY_SHIFT);
/* Haswell doesn't have any port selection bits for the panel
* power sequence any more. */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ed75a36..39bddd7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -396,6 +396,8 @@ struct intel_fbc_work {
int interval;
};
+int intel_pch_rawclk(struct drm_device *dev);
+
int intel_connector_update_modes(struct drm_connector *connector,
struct edid *edid);
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/5] drm/i915/dp: compute the pch dp aux divider from the rawclk
2012-10-20 18:57 [PATCH 0/5] eDP improvements Daniel Vetter
` (2 preceding siblings ...)
2012-10-20 18:57 ` [PATCH 3/5] drm/i915/eDP: compute the panel power clock divisor from the pch rawclock Daniel Vetter
@ 2012-10-20 18:57 ` Daniel Vetter
2012-10-22 22:08 ` Jesse Barnes
2012-10-20 18:57 ` [PATCH 5/5] drm/i915: extract intel_dp_init_panel_power_sequencer Daniel Vetter
` (2 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-20 18:57 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
Otherwise dp aux won't work on some hsw platforms, since they use a
different rawclk than the 125MHz clock used thus far.
To absolutely not change anything, round up: That way we get the old
63 divider for the default 125MHz clock.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b35d5bd..971c4e4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -372,7 +372,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
else
aux_clock_divider = 225; /* eDP input clock at 450Mhz */
} else if (HAS_PCH_SPLIT(dev))
- aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
+ aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
else
aux_clock_divider = intel_hrawclk(dev) / 2;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/5] drm/i915: extract intel_dp_init_panel_power_sequencer
2012-10-20 18:57 [PATCH 0/5] eDP improvements Daniel Vetter
` (3 preceding siblings ...)
2012-10-20 18:57 ` [PATCH 4/5] drm/i915/dp: compute the pch dp aux divider from the rawclk Daniel Vetter
@ 2012-10-20 18:57 ` Daniel Vetter
2012-10-22 22:08 ` Jesse Barnes
2012-10-21 7:37 ` [PATCH 0/5] eDP improvements Oleksij Rempel
2012-10-23 14:03 ` Paulo Zanoni
6 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-20 18:57 UTC (permalink / raw)
To: Intel Graphics Development; +Cc: Daniel Vetter
That thing has grown way too big already.
Also move around a comment to the right spot.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_dp.c | 223 +++++++++++++++++++++-------------------
1 file changed, 115 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 971c4e4..b9b9d08 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2576,6 +2576,118 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
intel_attach_broadcast_rgb_property(connector);
}
+static void
+intel_dp_init_panel_power_sequencer(struct drm_device *dev,
+ struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct edp_power_seq cur, vbt, spec, final;
+ u32 pp_on, pp_off, pp_div, pp;
+
+ /* Workaround: Need to write PP_CONTROL with the unlock key as
+ * the very first thing. */
+ pp = ironlake_get_pp_control(dev_priv);
+ I915_WRITE(PCH_PP_CONTROL, pp);
+
+ pp_on = I915_READ(PCH_PP_ON_DELAYS);
+ pp_off = I915_READ(PCH_PP_OFF_DELAYS);
+ pp_div = I915_READ(PCH_PP_DIVISOR);
+
+ /* Pull timing values out of registers */
+ cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
+ PANEL_POWER_UP_DELAY_SHIFT;
+
+ cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
+ PANEL_LIGHT_ON_DELAY_SHIFT;
+
+ cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
+ PANEL_LIGHT_OFF_DELAY_SHIFT;
+
+ cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
+ PANEL_POWER_DOWN_DELAY_SHIFT;
+
+ cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
+ PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
+
+ DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+ cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
+
+ vbt = dev_priv->edp.pps;
+
+ /* Upper limits from eDP 1.3 spec. Note that we the clunky units
+ * of our hw here, which are all in 100usec. */
+ spec.t1_t3 = 210 * 10;
+ spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
+ spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
+ spec.t10 = 500 * 10;
+ /* This one is special and actually in units of 100ms, but zero
+ * based in the hw (so we need to add 100 ms). But the sw vbt
+ * table multiplies it with 1000 to make it in units of 100usec,
+ * too. */
+ spec.t11_t12 = (510 + 100) * 10;
+
+ DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+ vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
+
+ /* Use the max of the register setttings and vbt. If both are
+ * unset, fall back to the spec limits. */
+#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
+ spec.field : \
+ max(cur.field, vbt.field))
+ assign_final(t1_t3);
+ assign_final(t8);
+ assign_final(t9);
+ assign_final(t10);
+ assign_final(t11_t12);
+#undef assign_final
+
+#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
+ intel_dp->panel_power_up_delay = get_delay(t1_t3);
+ intel_dp->backlight_on_delay = get_delay(t8);
+ intel_dp->backlight_off_delay = get_delay(t9);
+ intel_dp->panel_power_down_delay = get_delay(t10);
+ intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
+#undef get_delay
+
+ /* And finally store the new values in the power sequencer. */
+ pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
+ (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
+ pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
+ (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
+ /* Compute the divisor for the pp clock, simply match the Bspec
+ * formula. */
+ pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
+ << PP_REFERENCE_DIVIDER_SHIFT;
+ pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
+ << PANEL_POWER_CYCLE_DELAY_SHIFT);
+
+ /* Haswell doesn't have any port selection bits for the panel
+ * power sequence any more. */
+ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+ if (is_cpu_edp(intel_dp))
+ pp_on |= PANEL_POWER_PORT_DP_A;
+ else
+ pp_on |= PANEL_POWER_PORT_DP_D;
+ }
+
+ I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
+ I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
+ I915_WRITE(PCH_PP_DIVISOR, pp_div);
+
+
+ DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
+ intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
+ intel_dp->panel_power_cycle_delay);
+
+ DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
+ intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
+
+ DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
+ I915_READ(PCH_PP_ON_DELAYS),
+ I915_READ(PCH_PP_OFF_DELAYS),
+ I915_READ(PCH_PP_DIVISOR));
+}
+
void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
@@ -2674,117 +2786,12 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
break;
}
- /* Cache some DPCD data in the eDP case */
- if (is_edp(intel_dp)) {
- struct edp_power_seq cur, vbt, spec, final;
- u32 pp_on, pp_off, pp_div, pp;
-
- /* Workaround: Need to write PP_CONTROL with the unlock key as
- * the very first thing. */
- pp = ironlake_get_pp_control(dev_priv);
- I915_WRITE(PCH_PP_CONTROL, pp);
-
- pp_on = I915_READ(PCH_PP_ON_DELAYS);
- pp_off = I915_READ(PCH_PP_OFF_DELAYS);
- pp_div = I915_READ(PCH_PP_DIVISOR);
-
- /* Pull timing values out of registers */
- cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
- PANEL_POWER_UP_DELAY_SHIFT;
-
- cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
- PANEL_LIGHT_ON_DELAY_SHIFT;
-
- cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
- PANEL_LIGHT_OFF_DELAY_SHIFT;
-
- cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
- PANEL_POWER_DOWN_DELAY_SHIFT;
-
- cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
- PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
-
- DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
- cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
-
- vbt = dev_priv->edp.pps;
-
- /* Upper limits from eDP 1.3 spec. Note that we the clunky units
- * of our hw here, which are all in 100usec. */
- spec.t1_t3 = 210 * 10;
- spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
- spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
- spec.t10 = 500 * 10;
- /* This one is special and actually in units of 100ms, but zero
- * based in the hw (so we need to add 100 ms). But the sw vbt
- * table multiplies it with 1000 to make it in units of 100usec,
- * too. */
- spec.t11_t12 = (510 + 100) * 10;
-
- DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
- vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
-
- /* Use the max of the register setttings and vbt. If both are
- * unset, fall back to the spec limits. */
-#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
- spec.field : \
- max(cur.field, vbt.field))
- assign_final(t1_t3);
- assign_final(t8);
- assign_final(t9);
- assign_final(t10);
- assign_final(t11_t12);
-#undef assign_final
-
-#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
- intel_dp->panel_power_up_delay = get_delay(t1_t3);
- intel_dp->backlight_on_delay = get_delay(t8);
- intel_dp->backlight_off_delay = get_delay(t9);
- intel_dp->panel_power_down_delay = get_delay(t10);
- intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
-#undef get_delay
-
- /* And finally store the new values in the power sequencer. */
- pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
- (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
- pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
- (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
- /* Compute the divisor for the pp clock, simply match the Bspec
- * formula. */
- pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
- << PP_REFERENCE_DIVIDER_SHIFT;
- pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
- << PANEL_POWER_CYCLE_DELAY_SHIFT);
-
- /* Haswell doesn't have any port selection bits for the panel
- * power sequence any more. */
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
- if (is_cpu_edp(intel_dp))
- pp_on |= PANEL_POWER_PORT_DP_A;
- else
- pp_on |= PANEL_POWER_PORT_DP_D;
- }
-
- I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
- I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
- I915_WRITE(PCH_PP_DIVISOR, pp_div);
-
-
- DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
- intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
- intel_dp->panel_power_cycle_delay);
-
- DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
- intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
-
- DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
- I915_READ(PCH_PP_ON_DELAYS),
- I915_READ(PCH_PP_OFF_DELAYS),
- I915_READ(PCH_PP_DIVISOR));
- }
+ if (is_edp(intel_dp))
+ intel_dp_init_panel_power_sequencer(dev, intel_dp);
intel_dp_i2c_init(intel_dp, intel_connector, name);
+ /* Cache DPCD and EDID for edp. */
if (is_edp(intel_dp)) {
bool ret;
struct edid *edid;
--
1.7.11.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 0/5] eDP improvements
2012-10-20 18:57 [PATCH 0/5] eDP improvements Daniel Vetter
` (4 preceding siblings ...)
2012-10-20 18:57 ` [PATCH 5/5] drm/i915: extract intel_dp_init_panel_power_sequencer Daniel Vetter
@ 2012-10-21 7:37 ` Oleksij Rempel
2012-10-21 10:34 ` Daniel Vetter
2012-10-23 14:03 ` Paulo Zanoni
6 siblings, 1 reply; 17+ messages in thread
From: Oleksij Rempel @ 2012-10-21 7:37 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
[-- Attachment #1: Type: text/plain, Size: 1453 bytes --]
Hi Daniel,
i assume this patch set should/may fix this bug:
https://bugs.freedesktop.org/show_bug.cgi?id=48652
i tested it on top of linux/master + drm-intel-fixes + "[PATCH]
drm/i915/dp: actually nack test request".
eDP is listed now and xserver use it. But eDP stays blank/black.
I also got some warnings, see attached dmesg.
Am 20.10.2012 20:57, schrieb Daniel Vetter:
> Hi all,
>
> This is useful fallout of my futile attempts at getting the eDP panel on my ivb
> working without the BIOS' help. I now at least get a backlit black screen though
> ;-)
>
> Paulo said that this is good enough for his hsw eDP machine already, and it
> definitely improves the code a bit and (hopefully) makes it a tad more robust.
>
> Comments, flames and test results highly welcome.
>
> Cheers, Daniel
>
> Daniel Vetter (5):
> drm/i915: make edp panel power sequence setup more robust
> drm/i915: enable/disable backlight for eDP
> drm/i915/eDP: compute the panel power clock divisor from the pch
> rawclock
> drm/i915/dp: compute the pch dp aux divider from the rawclk
> drm/i915: extract intel_dp_init_panel_power_sequencer
>
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> drivers/gpu/drm/i915/intel_display.c | 10 ++
> drivers/gpu/drm/i915/intel_dp.c | 177 ++++++++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 4 files changed, 138 insertions(+), 56 deletions(-)
>
--
Regards,
Oleksij
[-- Attachment #2: dmesg --]
[-- Type: text/plain, Size: 78184 bytes --]
[ 0.000000] Linux version 3.7.0-rc1-00337-g5b9b8e9 (lex@ultralex) (gcc version 4.7.2 (Ubuntu/Linaro 4.7.2-2ubuntu1) ) #26 SMP Sun Oct 21 09:14:02 CEST 2012
[ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz root=UUID=6397efa0-91ca-4364-b4ea-733e39e4cc1b ro
[ 0.000000] e820: BIOS-provided physical RAM map:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009efff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f000-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001fffffff] usable
[ 0.000000] BIOS-e820: [mem 0x0000000020000000-0x00000000201fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000020200000-0x0000000040003fff] usable
[ 0.000000] BIOS-e820: [mem 0x0000000040004000-0x0000000040004fff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000040005000-0x00000000d97e3fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d97e4000-0x00000000d9de4fff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x00000000d9de5000-0x00000000d9de7fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9de8000-0x00000000d9dfcfff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d9dfd000-0x00000000d9e02fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9e03000-0x00000000d9e04fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d9e05000-0x00000000d9e09fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9e0a000-0x00000000d9f62fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d9f63000-0x00000000d9f66fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9f67000-0x00000000d9fa5fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d9fa6000-0x00000000d9facfff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9fad000-0x00000000d9faefff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d9faf000-0x00000000d9fccfff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9fcd000-0x00000000d9fcffff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d9fd0000-0x00000000d9fd1fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9fd2000-0x00000000d9fe8fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d9fe9000-0x00000000d9feefff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9fef000-0x00000000d9ff6fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d9ff7000-0x00000000d9ff7fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9ff8000-0x00000000da006fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da007000-0x00000000da007fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000da008000-0x00000000da012fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da013000-0x00000000da017fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000da018000-0x00000000da035fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da036000-0x00000000da037fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000da038000-0x00000000da04bfff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da04c000-0x00000000da04cfff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000da04d000-0x00000000da05efff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da05f000-0x00000000da084fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000da085000-0x00000000da098fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da099000-0x00000000da099fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000da09a000-0x00000000da09afff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da09b000-0x00000000da09cfff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000da09d000-0x00000000da09dfff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da09e000-0x00000000da0a2fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000da0a3000-0x00000000da0b7fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da0b8000-0x00000000da65bfff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000da65c000-0x00000000da8dbfff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x00000000da8dc000-0x00000000da8e0fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x00000000da8e1000-0x00000000da8e1fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000da8e2000-0x00000000da924fff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x00000000da925000-0x00000000dad33fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000dad34000-0x00000000daff3fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000daff4000-0x00000000daffffff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000dbc00000-0x00000000dfdfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed03fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000011f1fffff] usable
[ 0.000000] NX (Execute Disable) protection: active
[ 0.000000] efi: EFI v2.31 by American Megatrends
[ 0.000000] efi: ACPI=0xda8af000 ACPI 2.0=0xda8af000 SMBIOS=0xf04c0 MPS=0xfd4b0
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[ 0.000000] efi: mem24: type=4, attr=0xf, range=[0x00000000d8490000-0x00000000d8645000) (1MB)
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[ 0.000000] efi: mem29: type=3, attr=0xf, range=[0x00000000d97ba000-0x00000000d97e4000) (0MB)
[ 0.000000] efi: mem30: type=10, attr=0xf, range=[0x00000000d97e4000-0x00000000d9de5000) (6MB)
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[ 0.000000] efi: mem32: type=3, attr=0xf, range=[0x00000000d9de8000-0x00000000d9dfd000) (0MB)
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[ 0.000000] efi: mem34: type=3, attr=0xf, range=[0x00000000d9e03000-0x00000000d9e05000) (0MB)
[ 0.000000] efi: mem35: type=5, attr=0x800000000000000f, range=[0x00000000d9e05000-0x00000000d9e0a000) (0MB)
[ 0.000000] efi: mem36: type=3, attr=0xf, range=[0x00000000d9e0a000-0x00000000d9f63000) (1MB)
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[ 0.000000] efi: mem38: type=3, attr=0xf, range=[0x00000000d9f67000-0x00000000d9fa6000) (0MB)
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[ 0.000000] efi: mem47: type=3, attr=0xf, range=[0x00000000d9fef000-0x00000000d9ff7000) (0MB)
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[ 0.000000] efi: mem51: type=3, attr=0xf, range=[0x00000000da008000-0x00000000da013000) (0MB)
[ 0.000000] efi: mem52: type=5, attr=0x800000000000000f, range=[0x00000000da013000-0x00000000da018000) (0MB)
[ 0.000000] efi: mem53: type=3, attr=0xf, range=[0x00000000da018000-0x00000000da036000) (0MB)
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[ 0.000000] efi: mem55: type=3, attr=0xf, range=[0x00000000da038000-0x00000000da04c000) (0MB)
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[ 0.000000] efi: mem68: type=6, attr=0x800000000000000f, range=[0x00000000da132000-0x00000000da137000) (0MB)
[ 0.000000] efi: mem69: type=6, attr=0x800000000000000f, range=[0x00000000da137000-0x00000000da13d000) (0MB)
[ 0.000000] efi: mem70: type=6, attr=0x800000000000000f, range=[0x00000000da13d000-0x00000000da13f000) (0MB)
[ 0.000000] efi: mem71: type=6, attr=0x800000000000000f, range=[0x00000000da13f000-0x00000000da15c000) (0MB)
[ 0.000000] efi: mem72: type=0, attr=0xf, range=[0x00000000da15c000-0x00000000da28b000) (1MB)
[ 0.000000] efi: mem73: type=0, attr=0xf, range=[0x00000000da28b000-0x00000000da5f1000) (3MB)
[ 0.000000] efi: mem74: type=0, attr=0xf, range=[0x00000000da5f1000-0x00000000da5f7000) (0MB)
[ 0.000000] efi: mem75: type=0, attr=0xf, range=[0x00000000da5f7000-0x00000000da65c000) (0MB)
[ 0.000000] efi: mem76: type=10, attr=0xf, range=[0x00000000da65c000-0x00000000da72a000) (0MB)
[ 0.000000] efi: mem77: type=10, attr=0xf, range=[0x00000000da72a000-0x00000000da8c6000) (1MB)
[ 0.000000] efi: mem78: type=10, attr=0xf, range=[0x00000000da8c6000-0x00000000da8c8000) (0MB)
[ 0.000000] efi: mem79: type=10, attr=0xf, range=[0x00000000da8c8000-0x00000000da8dc000) (0MB)
[ 0.000000] efi: mem80: type=9, attr=0xf, range=[0x00000000da8dc000-0x00000000da8e0000) (0MB)
[ 0.000000] efi: mem81: type=9, attr=0xf, range=[0x00000000da8e0000-0x00000000da8e1000) (0MB)
[ 0.000000] efi: mem82: type=4, attr=0xf, range=[0x00000000da8e1000-0x00000000da8e2000) (0MB)
[ 0.000000] efi: mem83: type=10, attr=0xf, range=[0x00000000da8e2000-0x00000000da925000) (0MB)
[ 0.000000] efi: mem84: type=4, attr=0xf, range=[0x00000000da925000-0x00000000daa6f000) (1MB)
[ 0.000000] efi: mem85: type=3, attr=0xf, range=[0x00000000daa6f000-0x00000000dad05000) (2MB)
[ 0.000000] efi: mem86: type=4, attr=0xf, range=[0x00000000dad05000-0x00000000dad0a000) (0MB)
[ 0.000000] efi: mem87: type=3, attr=0xf, range=[0x00000000dad0a000-0x00000000dad0e000) (0MB)
[ 0.000000] efi: mem88: type=4, attr=0xf, range=[0x00000000dad0e000-0x00000000dad1b000) (0MB)
[ 0.000000] efi: mem89: type=3, attr=0xf, range=[0x00000000dad1b000-0x00000000dad2d000) (0MB)
[ 0.000000] efi: mem90: type=4, attr=0xf, range=[0x00000000dad2d000-0x00000000dad34000) (0MB)
[ 0.000000] efi: mem91: type=6, attr=0x800000000000000f, range=[0x00000000dad34000-0x00000000daff4000) (2MB)
[ 0.000000] efi: mem92: type=4, attr=0xf, range=[0x00000000daff4000-0x00000000db000000) (0MB)
[ 0.000000] efi: mem93: type=7, attr=0xf, range=[0x0000000100000000-0x000000011f200000) (498MB)
[ 0.000000] efi: mem94: type=0, attr=0x8000000000000000, range=[0x00000000dbc00000-0x00000000dfe00000) (66MB)
[ 0.000000] efi: mem95: type=11, attr=0x8000000000000001, range=[0x00000000f8000000-0x00000000fc000000) (64MB)
[ 0.000000] efi: mem96: type=11, attr=0x8000000000000001, range=[0x00000000fec00000-0x00000000fec01000) (0MB)
[ 0.000000] efi: mem97: type=11, attr=0x8000000000000001, range=[0x00000000fed00000-0x00000000fed04000) (0MB)
[ 0.000000] efi: mem98: type=11, attr=0x8000000000000001, range=[0x00000000fed1c000-0x00000000fed20000) (0MB)
[ 0.000000] efi: mem99: type=11, attr=0x8000000000000001, range=[0x00000000fee00000-0x00000000fee01000) (0MB)
[ 0.000000] efi: mem100: type=11, attr=0x8000000000000001, range=[0x00000000ff000000-0x0000000100000000) (16MB)
[ 0.000000] DMI 2.7 present.
[ 0.000000] DMI: ASUSTeK COMPUTER INC. UX31A/UX31A, BIOS UX31A.206 06/05/2012
[ 0.000000] e820: update [mem 0x00000000-0x0000ffff] usable ==> reserved
[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
[ 0.000000] No AGP bridge found
[ 0.000000] e820: last_pfn = 0x11f200 max_arch_pfn = 0x400000000
[ 0.000000] MTRR default type: uncachable
[ 0.000000] MTRR fixed ranges enabled:
[ 0.000000] 00000-9FFFF write-back
[ 0.000000] A0000-BFFFF uncachable
[ 0.000000] C0000-CFFFF write-protect
[ 0.000000] D0000-DFFFF uncachable
[ 0.000000] E0000-FFFFF write-protect
[ 0.000000] MTRR variable ranges enabled:
[ 0.000000] 0 base 000000000 mask F00000000 write-back
[ 0.000000] 1 base 100000000 mask FE0000000 write-back
[ 0.000000] 2 base 0E0000000 mask FE0000000 uncachable
[ 0.000000] 3 base 0DC000000 mask FFC000000 uncachable
[ 0.000000] 4 base 0DBC00000 mask FFFC00000 uncachable
[ 0.000000] 5 base 11F800000 mask FFF800000 uncachable
[ 0.000000] 6 base 11F400000 mask FFFC00000 uncachable
[ 0.000000] 7 base 11F200000 mask FFFE00000 uncachable
[ 0.000000] 8 disabled
[ 0.000000] 9 disabled
[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
[ 0.000000] e820: update [mem 0xdbc00000-0xffffffff] usable ==> reserved
[ 0.000000] e820: last_pfn = 0xdb000 max_arch_pfn = 0x400000000
[ 0.000000] initial memory mapped: [mem 0x00000000-0x1fffffff]
[ 0.000000] Base memory trampoline at [ffff880000097000] 97000 size 24576
[ 0.000000] init_memory_mapping: [mem 0x00000000-0xdaffffff]
[ 0.000000] [mem 0x00000000-0xdaffffff] page 2M
[ 0.000000] kernel direct mapping tables up to 0xdaffffff @ [mem 0x1f923000-0x1fffffff]
[ 0.000000] init_memory_mapping: [mem 0x100000000-0x11f1fffff]
[ 0.000000] [mem 0x100000000-0x11f1fffff] page 2M
[ 0.000000] kernel direct mapping tables up to 0x11f1fffff @ [mem 0xd97b4000-0xd97b9fff]
[ 0.000000] RAMDISK: [mem 0x362e4000-0x37169fff]
[ 0.000000] ACPI: RSDP 00000000da8af000 00024 (v02 _ASUS_)
[ 0.000000] ACPI: XSDT 00000000da8af088 00094 (v01 _ASUS_ Notebook 01072009 AMI 00010013)
[ 0.000000] ACPI: FACP 00000000da8c1090 000F4 (v04 _ASUS_ Notebook 01072009 AMI 00010013)
[ 0.000000] ACPI: DSDT 00000000da8af1b8 11ED6 (v02 _ASUS_ Notebook 00000013 INTL 20091112)
[ 0.000000] ACPI: FACS 00000000da8d9f80 00040
[ 0.000000] ACPI: APIC 00000000da8c1188 00072 (v03 _ASUS_ Notebook 01072009 AMI 00010013)
[ 0.000000] ACPI: FPDT 00000000da8c1200 00044 (v01 _ASUS_ Notebook 01072009 AMI 00010013)
[ 0.000000] ACPI: ECDT 00000000da8c1248 000C1 (v01 _ASUS_ Notebook 01072009 AMI. 00000005)
[ 0.000000] ACPI: MCFG 00000000da8c1310 0003C (v01 _ASUS_ Notebook 01072009 MSFT 00000097)
[ 0.000000] ACPI: SSDT 00000000da8c1350 00A3C (v01 DptfTa DptfTab 00001000 INTL 20091112)
[ 0.000000] ACPI: SSDT 00000000da8c1d90 00CA5 (v01 SADptf SADptf_ 00001000 INTL 20091112)
[ 0.000000] ACPI: SSDT 00000000da8c2a38 00098 (v01 PchDpt PchDptf 00001000 INTL 20091112)
[ 0.000000] ACPI: SSDT 00000000da8c2ad0 0091C (v01 CfgTDP CfgTDP_ 00001000 INTL 20091112)
[ 0.000000] ACPI: SLIC 00000000da8c33f0 00176 (v01 _ASUS_ Notebook 01072009 ASUS 00000001)
[ 0.000000] ACPI: HPET 00000000da8c3568 00038 (v01 _ASUS_ Notebook 01072009 AMI. 00000005)
[ 0.000000] ACPI: SSDT 00000000da8c35a0 008C8 (v01 PmRef Cpu0Ist 00003000 INTL 20051117)
[ 0.000000] ACPI: SSDT 00000000da8c3e68 00A92 (v01 PmRef CpuPm 00003000 INTL 20051117)
[ 0.000000] ACPI: DMAR 00000000da8c4900 000B8 (v01 INTEL SNB 00000001 INTL 00000001)
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] [ffffea0000000000-ffffea00047fffff] PMD -> [ffff88011a800000-ffff88011e7fffff] on node 0
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x00010000-0x00ffffff]
[ 0.000000] DMA32 [mem 0x01000000-0xffffffff]
[ 0.000000] Normal [mem 0x100000000-0x11f1fffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x00010000-0x0009efff]
[ 0.000000] node 0: [mem 0x00100000-0x1fffffff]
[ 0.000000] node 0: [mem 0x20200000-0x40003fff]
[ 0.000000] node 0: [mem 0x40005000-0xd97e3fff]
[ 0.000000] node 0: [mem 0xd9de8000-0xd9dfcfff]
[ 0.000000] node 0: [mem 0xd9e03000-0xd9e04fff]
[ 0.000000] node 0: [mem 0xd9e0a000-0xd9f62fff]
[ 0.000000] node 0: [mem 0xd9f67000-0xd9fa5fff]
[ 0.000000] node 0: [mem 0xd9fad000-0xd9faefff]
[ 0.000000] node 0: [mem 0xd9fcd000-0xd9fcffff]
[ 0.000000] node 0: [mem 0xd9fd2000-0xd9fe8fff]
[ 0.000000] node 0: [mem 0xd9fef000-0xd9ff6fff]
[ 0.000000] node 0: [mem 0xd9ff8000-0xda006fff]
[ 0.000000] node 0: [mem 0xda008000-0xda012fff]
[ 0.000000] node 0: [mem 0xda018000-0xda035fff]
[ 0.000000] node 0: [mem 0xda038000-0xda04bfff]
[ 0.000000] node 0: [mem 0xda04d000-0xda05efff]
[ 0.000000] node 0: [mem 0xda085000-0xda098fff]
[ 0.000000] node 0: [mem 0xda09a000-0xda09afff]
[ 0.000000] node 0: [mem 0xda09d000-0xda09dfff]
[ 0.000000] node 0: [mem 0xda0a3000-0xda0b7fff]
[ 0.000000] node 0: [mem 0xda8e1000-0xda8e1fff]
[ 0.000000] node 0: [mem 0xda925000-0xdad33fff]
[ 0.000000] node 0: [mem 0xdaff4000-0xdaffffff]
[ 0.000000] node 0: [mem 0x100000000-0x11f1fffff]
[ 0.000000] On node 0 totalpages: 1019370
[ 0.000000] DMA zone: 64 pages used for memmap
[ 0.000000] DMA zone: 12 pages reserved
[ 0.000000] DMA zone: 3907 pages, LIFO batch:0
[ 0.000000] DMA32 zone: 16320 pages used for memmap
[ 0.000000] DMA32 zone: 871579 pages, LIFO batch:31
[ 0.000000] Normal zone: 1992 pages used for memmap
[ 0.000000] Normal zone: 125496 pages, LIFO batch:31
[ 0.000000] ACPI: PM-Timer IO Port: 0x408
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x01] enabled)
[ 0.000000] ACPI: NR_CPUS/possible_cpus limit of 2 reached. Processor 2/0x1 ignored.
[ 0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] enabled)
[ 0.000000] ACPI: NR_CPUS/possible_cpus limit of 2 reached. Processor 3/0x3 ignored.
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
[ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
[ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[ 0.000000] ACPI: IRQ0 used by override.
[ 0.000000] ACPI: IRQ2 used by override.
[ 0.000000] ACPI: IRQ9 used by override.
[ 0.000000] Using ACPI (MADT) for SMP configuration information
[ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000
[ 0.000000] smpboot: 4 Processors exceeds NR_CPUS limit of 2
[ 0.000000] smpboot: Allowing 2 CPUs, 0 hotplug CPUs
[ 0.000000] nr_irqs_gsi: 40
[ 0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
[ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 0000000000100000
[ 0.000000] PM: Registered nosave memory: 0000000020000000 - 0000000020200000
[ 0.000000] PM: Registered nosave memory: 0000000040004000 - 0000000040005000
[ 0.000000] PM: Registered nosave memory: 00000000d97e4000 - 00000000d9de5000
[ 0.000000] PM: Registered nosave memory: 00000000d9de5000 - 00000000d9de8000
[ 0.000000] PM: Registered nosave memory: 00000000d9dfd000 - 00000000d9e03000
[ 0.000000] PM: Registered nosave memory: 00000000d9e05000 - 00000000d9e0a000
[ 0.000000] PM: Registered nosave memory: 00000000d9f63000 - 00000000d9f67000
[ 0.000000] PM: Registered nosave memory: 00000000d9fa6000 - 00000000d9fad000
[ 0.000000] PM: Registered nosave memory: 00000000d9faf000 - 00000000d9fcd000
[ 0.000000] PM: Registered nosave memory: 00000000d9fd0000 - 00000000d9fd2000
[ 0.000000] PM: Registered nosave memory: 00000000d9fe9000 - 00000000d9fef000
[ 0.000000] PM: Registered nosave memory: 00000000d9ff7000 - 00000000d9ff8000
[ 0.000000] PM: Registered nosave memory: 00000000da007000 - 00000000da008000
[ 0.000000] PM: Registered nosave memory: 00000000da013000 - 00000000da018000
[ 0.000000] PM: Registered nosave memory: 00000000da036000 - 00000000da038000
[ 0.000000] PM: Registered nosave memory: 00000000da04c000 - 00000000da04d000
[ 0.000000] PM: Registered nosave memory: 00000000da05f000 - 00000000da085000
[ 0.000000] PM: Registered nosave memory: 00000000da099000 - 00000000da09a000
[ 0.000000] PM: Registered nosave memory: 00000000da09b000 - 00000000da09d000
[ 0.000000] PM: Registered nosave memory: 00000000da09e000 - 00000000da0a3000
[ 0.000000] PM: Registered nosave memory: 00000000da0b8000 - 00000000da65c000
[ 0.000000] PM: Registered nosave memory: 00000000da65c000 - 00000000da8dc000
[ 0.000000] PM: Registered nosave memory: 00000000da8dc000 - 00000000da8e1000
[ 0.000000] PM: Registered nosave memory: 00000000da8e2000 - 00000000da925000
[ 0.000000] PM: Registered nosave memory: 00000000dad34000 - 00000000daff4000
[ 0.000000] PM: Registered nosave memory: 00000000db000000 - 00000000dbc00000
[ 0.000000] PM: Registered nosave memory: 00000000dbc00000 - 00000000dfe00000
[ 0.000000] PM: Registered nosave memory: 00000000dfe00000 - 00000000f8000000
[ 0.000000] PM: Registered nosave memory: 00000000f8000000 - 00000000fc000000
[ 0.000000] PM: Registered nosave memory: 00000000fc000000 - 00000000fec00000
[ 0.000000] PM: Registered nosave memory: 00000000fec00000 - 00000000fec01000
[ 0.000000] PM: Registered nosave memory: 00000000fec01000 - 00000000fed00000
[ 0.000000] PM: Registered nosave memory: 00000000fed00000 - 00000000fed04000
[ 0.000000] PM: Registered nosave memory: 00000000fed04000 - 00000000fed1c000
[ 0.000000] PM: Registered nosave memory: 00000000fed1c000 - 00000000fed20000
[ 0.000000] PM: Registered nosave memory: 00000000fed20000 - 00000000fee00000
[ 0.000000] PM: Registered nosave memory: 00000000fee00000 - 00000000fee01000
[ 0.000000] PM: Registered nosave memory: 00000000fee01000 - 00000000ff000000
[ 0.000000] PM: Registered nosave memory: 00000000ff000000 - 0000000100000000
[ 0.000000] e820: [mem 0xdfe00000-0xf7ffffff] available for PCI devices
[ 0.000000] setup_percpu: NR_CPUS:2 nr_cpumask_bits:2 nr_cpu_ids:2 nr_node_ids:1
[ 0.000000] PERCPU: Embedded 27 pages/cpu @ffff88011ee00000 s77888 r8192 d24512 u1048576
[ 0.000000] pcpu-alloc: s77888 r8192 d24512 u1048576 alloc=1*2097152
[ 0.000000] pcpu-alloc: [0] 0 1
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1000982
[ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz root=UUID=6397efa0-91ca-4364-b4ea-733e39e4cc1b ro
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.000000] __ex_table already sorted, skipping sort
[ 0.000000] xsave: enabled xstate_bv 0x7, cntxt size 0x340
[ 0.000000] Checking aperture...
[ 0.000000] No AGP bridge found
[ 0.000000] Memory: 3734944k/4704256k available (4802k kernel code, 626776k absent, 342536k reserved, 4065k data, 800k init)
[ 0.000000] SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] CONFIG_RCU_FANOUT set to non-default value of 32
[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled.
[ 0.000000] NR_IRQS:4352 nr_irqs:512 16
[ 0.000000] Extended CMOS year: 2000
[ 0.000000] Console: colour dummy device 80x25
[ 0.000000] console [tty0] enabled
[ 0.000000] hpet clockevent registered
[ 0.000000] tsc: Fast TSC calibration using PIT
[ 0.001000] tsc: Detected 1696.139 MHz processor
[ 0.000002] Calibrating delay loop (skipped), value calculated using timer frequency.. 3392.27 BogoMIPS (lpj=1696139)
[ 0.000011] pid_max: default: 32768 minimum: 301
[ 0.000099] init_memory_mapping: [mem 0xdbc00000-0xdfdfffff]
[ 0.000104] [mem 0xdbc00000-0xdfdfffff] page 2M
[ 0.046820] Security Framework initialized
[ 0.046856] AppArmor: AppArmor initialized
[ 0.046937] Mount-cache hash table entries: 256
[ 0.048453] CPU: Physical Processor ID: 0
[ 0.048458] CPU: Processor Core ID: 0
[ 0.048465] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
[ 0.048465] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
[ 0.049025] mce: CPU supports 7 MCE banks
[ 0.049046] CPU0: Thermal monitoring enabled (TM1)
[ 0.049055] process: using mwait in idle threads
[ 0.049062] Last level iTLB entries: 4KB 512, 2MB 0, 4MB 0
[ 0.049062] Last level dTLB entries: 4KB 512, 2MB 32, 4MB 32
[ 0.049062] tlb_flushall_shift: 1
[ 0.049251] Freeing SMP alternatives: 12k freed
[ 0.049263] ACPI: Core revision 20120913
[ 0.264994] ftrace: allocating 21888 entries in 86 pages
[ 0.280012] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[ 0.290008] smpboot: CPU0: Intel(R) Core(TM) i5-3317U CPU @ 1.70GHz (fam: 06, model: 3a, stepping: 09)
[ 0.391030] Performance Events: PEBS fmt1+, 16-deep LBR, IvyBridge events, Intel PMU driver.
[ 0.391041] ... version: 3
[ 0.391044] ... bit width: 48
[ 0.391047] ... generic registers: 4
[ 0.391050] ... value mask: 0000ffffffffffff
[ 0.391053] ... max period: 000000007fffffff
[ 0.391056] ... fixed-purpose events: 3
[ 0.391059] ... event mask: 000000070000000f
[ 0.394560] smpboot: Booting Node 0, Processors #1 OK
[ 0.408290] Brought up 2 CPUs
[ 0.408296] smpboot: Total of 2 processors activated (6784.55 BogoMIPS)
[ 0.408423] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
[ 0.412752] devtmpfs: initialized
[ 0.414323] PM: Registering ACPI NVS region [mem 0xd97e4000-0xd9de4fff] (6295552 bytes)
[ 0.418963] PM: Registering ACPI NVS region [mem 0xda65c000-0xda8dbfff] (2621440 bytes)
[ 0.420924] PM: Registering ACPI NVS region [mem 0xda8e2000-0xda924fff] (274432 bytes)
[ 0.423320] RTC time: 9:21:51, date: 10/21/12
[ 0.423678] NET: Registered protocol family 16
[ 0.425979] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
[ 0.425986] ACPI: bus type pci registered
[ 0.426607] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf8000000-0xfbffffff] (base 0xf8000000)
[ 0.426614] PCI: MMCONFIG at [mem 0xf8000000-0xfbffffff] reserved in E820
[ 0.442253] PCI: Using configuration type 1 for base access
[ 0.476365] bio: create slab <bio-0> at 0
[ 0.477112] ACPI: Added _OSI(Module Device)
[ 0.477124] ACPI: Added _OSI(Processor Device)
[ 0.477135] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 0.477145] ACPI: Added _OSI(Processor Aggregator Device)
[ 0.482147] ACPI: EC: EC description table is found, configuring boot EC
[ 0.488737] ACPI: Executed 1 blocks of module-level executable AML code
[ 0.605200] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored
[ 0.613360] ACPI: SSDT 00000000da609018 00853 (v01 PmRef Cpu0Cst 00003001 INTL 20051117)
[ 0.616583] ACPI: Dynamic OEM Table Load:
[ 0.616589] ACPI: SSDT (null) 00853 (v01 PmRef Cpu0Cst 00003001 INTL 20051117)
[ 0.623944] ACPI: SSDT 00000000da60aa98 00303 (v01 PmRef ApIst 00003000 INTL 20051117)
[ 0.629087] ACPI: Dynamic OEM Table Load:
[ 0.629093] ACPI: SSDT (null) 00303 (v01 PmRef ApIst 00003000 INTL 20051117)
[ 0.632110] ACPI: SSDT 00000000da60bc18 00119 (v01 PmRef ApCst 00003000 INTL 20051117)
[ 0.634690] ACPI: Dynamic OEM Table Load:
[ 0.634695] ACPI: SSDT (null) 00119 (v01 PmRef ApCst 00003000 INTL 20051117)
[ 0.639507] ACPI: Interpreter enabled
[ 0.639516] ACPI: (supports S0 S3 S4 S5)
[ 0.639757] ACPI: Using IOAPIC for interrupt routing
[ 0.825965] ACPI: EC: GPE = 0x19, I/O: command/status = 0x66, data = 0x62
[ 0.827903] ACPI: No dock devices found.
[ 0.827912] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 0.840905] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-3e])
[ 0.858238] PCI host bridge to bus 0000:00
[ 0.858251] pci_bus 0000:00: root bus resource [bus 00-3e]
[ 0.858263] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7]
[ 0.858273] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff]
[ 0.858284] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
[ 0.858294] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff]
[ 0.858305] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff]
[ 0.858315] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff]
[ 0.858326] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff]
[ 0.858336] pci_bus 0000:00: root bus resource [mem 0xdfe00000-0xfeafffff]
[ 0.858368] pci 0000:00:00.0: [8086:0154] type 00 class 0x060000
[ 0.858430] pci 0000:00:02.0: [8086:0166] type 00 class 0x030000
[ 0.858445] pci 0000:00:02.0: reg 10: [mem 0xf7800000-0xf7bfffff 64bit]
[ 0.858455] pci 0000:00:02.0: reg 18: [mem 0xe0000000-0xefffffff 64bit pref]
[ 0.858462] pci 0000:00:02.0: reg 20: [io 0xf000-0xf03f]
[ 0.858519] pci 0000:00:04.0: [8086:0153] type 00 class 0x118000
[ 0.858533] pci 0000:00:04.0: reg 10: [mem 0xfed98000-0xfed9ffff 64bit]
[ 0.858634] pci 0000:00:14.0: [8086:1e31] type 00 class 0x0c0330
[ 0.858663] pci 0000:00:14.0: reg 10: [mem 0xf7d00000-0xf7d0ffff 64bit]
[ 0.858756] pci 0000:00:14.0: PME# supported from D3hot D3cold
[ 0.858799] pci 0000:00:16.0: [8086:1e3a] type 00 class 0x078000
[ 0.858828] pci 0000:00:16.0: reg 10: [mem 0xf7d22000-0xf7d2200f 64bit]
[ 0.858917] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
[ 0.858978] pci 0000:00:1a.0: [8086:1e2d] type 00 class 0x0c0320
[ 0.859004] pci 0000:00:1a.0: reg 10: [mem 0xf7d20000-0xf7d203ff]
[ 0.859111] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
[ 0.859157] pci 0000:00:1b.0: [8086:1e20] type 00 class 0x040300
[ 0.859177] pci 0000:00:1b.0: reg 10: [mem 0xf7d18000-0xf7d1bfff 64bit]
[ 0.859267] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
[ 0.859309] pci 0000:00:1c.0: [8086:1e10] type 01 class 0x060400
[ 0.859411] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[ 0.859455] pci 0000:00:1c.1: [8086:1e12] type 01 class 0x060400
[ 0.859556] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
[ 0.859615] pci 0000:00:1d.0: [8086:1e26] type 00 class 0x0c0320
[ 0.859643] pci 0000:00:1d.0: reg 10: [mem 0xf7d1f000-0xf7d1f3ff]
[ 0.859783] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
[ 0.859828] pci 0000:00:1f.0: [8086:1e59] type 00 class 0x060100
[ 0.859986] pci 0000:00:1f.2: [8086:1e03] type 00 class 0x010601
[ 0.860010] pci 0000:00:1f.2: reg 10: [io 0xf0b0-0xf0b7]
[ 0.860020] pci 0000:00:1f.2: reg 14: [io 0xf0a0-0xf0a3]
[ 0.860030] pci 0000:00:1f.2: reg 18: [io 0xf090-0xf097]
[ 0.860041] pci 0000:00:1f.2: reg 1c: [io 0xf080-0xf083]
[ 0.860053] pci 0000:00:1f.2: reg 20: [io 0xf060-0xf07f]
[ 0.860064] pci 0000:00:1f.2: reg 24: [mem 0xf7d1e000-0xf7d1e7ff]
[ 0.860121] pci 0000:00:1f.2: PME# supported from D3hot
[ 0.860158] pci 0000:00:1f.3: [8086:1e22] type 00 class 0x0c0500
[ 0.860179] pci 0000:00:1f.3: reg 10: [mem 0xf7d1d000-0xf7d1d0ff 64bit]
[ 0.860207] pci 0000:00:1f.3: reg 20: [io 0xf040-0xf05f]
[ 0.860267] pci 0000:00:1f.6: [8086:1e24] type 00 class 0x118000
[ 0.860294] pci 0000:00:1f.6: reg 10: [mem 0xf7d1c000-0xf7d1cfff 64bit]
[ 0.860447] pci 0000:00:1c.0: PCI bridge to [bus 01]
[ 0.860568] pci 0000:02:00.0: [168c:002b] type 00 class 0x028000
[ 0.860599] pci 0000:02:00.0: reg 10: [mem 0xf7c00000-0xf7c0ffff 64bit]
[ 0.860767] pci 0000:02:00.0: supports D1
[ 0.860770] pci 0000:02:00.0: PME# supported from D0 D1 D3hot
[ 0.862720] pci 0000:00:1c.1: PCI bridge to [bus 02]
[ 0.862731] pci 0000:00:1c.1: bridge window [mem 0xf7c00000-0xf7cfffff]
[ 0.862752] pci_bus 0000:00: on NUMA node 0
[ 0.862771] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[ 0.870654] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP01._PRT]
[ 0.871861] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP02._PRT]
[ 0.876523] pci0000:00: Requesting ACPI _OSC control (0x1d)
[ 0.884448] pci0000:00: ACPI _OSC control (0x18) granted
[ 1.082564] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12)
[ 1.083587] ACPI: PCI Interrupt Link [LNKB] (IRQs *3 4 5 6 7 10 12)
[ 1.084603] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 *10 12)
[ 1.085635] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *10 12)
[ 1.086646] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12) *0, disabled.
[ 1.087659] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 12) *0, disabled.
[ 1.088670] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 *5 6 7 10 12)
[ 1.089678] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 *4 5 6 7 10 12)
[ 1.090817] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
[ 1.090826] vgaarb: loaded
[ 1.090829] vgaarb: bridge control possible 0000:00:02.0
[ 1.092162] SCSI subsystem initialized
[ 1.092172] ACPI: bus type scsi registered
[ 1.092662] libata version 3.00 loaded.
[ 1.092687] ACPI: bus type usb registered
[ 1.093161] usbcore: registered new interface driver usbfs
[ 1.093401] usbcore: registered new interface driver hub
[ 1.093633] usbcore: registered new device driver usb
[ 1.094189] media: Linux media interface: v0.10
[ 1.094406] Linux video capture interface: v2.00
[ 1.095196] PCI: Using ACPI for IRQ routing
[ 1.097121] PCI: pci_cache_line_size set to 64 bytes
[ 1.097133] pci 0000:00:04.0: no compatible bridge window for [mem 0xfed98000-0xfed9ffff 64bit]
[ 1.097210] e820: reserve RAM buffer [mem 0x0009f000-0x0009ffff]
[ 1.097217] e820: reserve RAM buffer [mem 0x40004000-0x43ffffff]
[ 1.097223] e820: reserve RAM buffer [mem 0xd97e4000-0xdbffffff]
[ 1.097235] e820: reserve RAM buffer [mem 0xd9dfd000-0xdbffffff]
[ 1.097248] e820: reserve RAM buffer [mem 0xd9e05000-0xdbffffff]
[ 1.097260] e820: reserve RAM buffer [mem 0xd9f63000-0xdbffffff]
[ 1.097272] e820: reserve RAM buffer [mem 0xd9fa6000-0xdbffffff]
[ 1.097284] e820: reserve RAM buffer [mem 0xd9faf000-0xdbffffff]
[ 1.097296] e820: reserve RAM buffer [mem 0xd9fd0000-0xdbffffff]
[ 1.097307] e820: reserve RAM buffer [mem 0xd9fe9000-0xdbffffff]
[ 1.097318] e820: reserve RAM buffer [mem 0xd9ff7000-0xdbffffff]
[ 1.097329] e820: reserve RAM buffer [mem 0xda007000-0xdbffffff]
[ 1.097339] e820: reserve RAM buffer [mem 0xda013000-0xdbffffff]
[ 1.097349] e820: reserve RAM buffer [mem 0xda036000-0xdbffffff]
[ 1.097359] e820: reserve RAM buffer [mem 0xda04c000-0xdbffffff]
[ 1.097371] e820: reserve RAM buffer [mem 0xda05f000-0xdbffffff]
[ 1.097380] e820: reserve RAM buffer [mem 0xda099000-0xdbffffff]
[ 1.097389] e820: reserve RAM buffer [mem 0xda09b000-0xdbffffff]
[ 1.097397] e820: reserve RAM buffer [mem 0xda09e000-0xdbffffff]
[ 1.097405] e820: reserve RAM buffer [mem 0xda0b8000-0xdbffffff]
[ 1.097413] e820: reserve RAM buffer [mem 0xda8e2000-0xdbffffff]
[ 1.097420] e820: reserve RAM buffer [mem 0xdad34000-0xdbffffff]
[ 1.097426] e820: reserve RAM buffer [mem 0xdb000000-0xdbffffff]
[ 1.097432] e820: reserve RAM buffer [mem 0x11f200000-0x11fffffff]
[ 1.098824] NET: Registered protocol family 8
[ 1.098828] NET: Registered protocol family 20
[ 1.099030] NetLabel: Initializing
[ 1.099033] NetLabel: domain hash size = 128
[ 1.099036] NetLabel: protocols = UNLABELED CIPSOv4
[ 1.099119] NetLabel: unlabeled traffic allowed by default
[ 1.099657] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
[ 1.099669] hpet0: 8 comparators, 64-bit 14.318180 MHz counter
[ 1.101733] Switching to clocksource hpet
[ 1.170111] AppArmor: AppArmor Filesystem Enabled
[ 1.170404] pnp: PnP ACPI init
[ 1.170500] ACPI: bus type pnp registered
[ 1.178431] pnp 00:00: [bus 00-3e]
[ 1.178441] pnp 00:00: [io 0x0000-0x0cf7 window]
[ 1.178449] pnp 00:00: [io 0x0cf8-0x0cff]
[ 1.178457] pnp 00:00: [io 0x0d00-0xffff window]
[ 1.178465] pnp 00:00: [mem 0x000a0000-0x000bffff window]
[ 1.178473] pnp 00:00: [mem 0x000c0000-0x000c3fff window]
[ 1.178481] pnp 00:00: [mem 0x000c4000-0x000c7fff window]
[ 1.178488] pnp 00:00: [mem 0x000c8000-0x000cbfff window]
[ 1.178497] pnp 00:00: [mem 0x000cc000-0x000cffff window]
[ 1.178505] pnp 00:00: [mem 0x000d0000-0x000d3fff window]
[ 1.178512] pnp 00:00: [mem 0x000d4000-0x000d7fff window]
[ 1.178520] pnp 00:00: [mem 0x000d8000-0x000dbfff window]
[ 1.178528] pnp 00:00: [mem 0x000dc000-0x000dffff window]
[ 1.178535] pnp 00:00: [mem 0x000e0000-0x000e3fff window]
[ 1.178543] pnp 00:00: [mem 0x000e4000-0x000e7fff window]
[ 1.178551] pnp 00:00: [mem 0x000e8000-0x000ebfff window]
[ 1.178558] pnp 00:00: [mem 0x000ec000-0x000effff window]
[ 1.178566] pnp 00:00: [mem 0x000f0000-0x000fffff window]
[ 1.178574] pnp 00:00: [mem 0xdfe00000-0xfeafffff window]
[ 1.178582] pnp 00:00: [mem 0x00010000-0x0001ffff window]
[ 1.178979] pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
[ 1.179318] pnp 00:01: [mem 0xfed40000-0xfed44fff]
[ 1.179758] system 00:01: [mem 0xfed40000-0xfed44fff] has been reserved
[ 1.179766] system 00:01: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 1.180548] pnp 00:02: [io 0x0000-0x001f]
[ 1.180556] pnp 00:02: [io 0x0081-0x0091]
[ 1.180564] pnp 00:02: [io 0x0093-0x009f]
[ 1.180571] pnp 00:02: [io 0x00c0-0x00df]
[ 1.180580] pnp 00:02: [dma 4]
[ 1.180986] pnp 00:02: Plug and Play ACPI device, IDs PNP0200 (active)
[ 1.181083] pnp 00:03: [mem 0xff000000-0xffffffff]
[ 1.181447] pnp 00:03: Plug and Play ACPI device, IDs INT0800 (active)
[ 1.182568] pnp 00:04: [mem 0xfed00000-0xfed003ff]
[ 1.182957] pnp 00:04: Plug and Play ACPI device, IDs PNP0103 (active)
[ 1.183079] pnp 00:05: [io 0x002e-0x002f]
[ 1.183087] pnp 00:05: [io 0x004e-0x004f]
[ 1.183094] pnp 00:05: [io 0x0061]
[ 1.183104] pnp 00:05: [io 0x0063]
[ 1.183112] pnp 00:05: [io 0x0065]
[ 1.183119] pnp 00:05: [io 0x0067]
[ 1.183127] pnp 00:05: [io 0x0070]
[ 1.183134] pnp 00:05: [io 0x0080]
[ 1.183142] pnp 00:05: [io 0x0092]
[ 1.183149] pnp 00:05: [io 0x00b2-0x00b3]
[ 1.183157] pnp 00:05: [io 0x0680-0x069f]
[ 1.183165] pnp 00:05: [io 0x1000-0x100f]
[ 1.183172] pnp 00:05: [io 0xffff]
[ 1.183180] pnp 00:05: [io 0xffff]
[ 1.183187] pnp 00:05: [io 0x0400-0x0453]
[ 1.183195] pnp 00:05: [io 0x0458-0x047f]
[ 1.183203] pnp 00:05: [io 0x0500-0x057f]
[ 1.183210] pnp 00:05: [io 0x164e-0x164f]
[ 1.183641] system 00:05: [io 0x0680-0x069f] has been reserved
[ 1.183671] system 00:05: [io 0x1000-0x100f] has been reserved
[ 1.183692] system 00:05: [io 0xffff] has been reserved
[ 1.183712] system 00:05: [io 0xffff] has been reserved
[ 1.183732] system 00:05: [io 0x0400-0x0453] has been reserved
[ 1.183752] system 00:05: [io 0x0458-0x047f] has been reserved
[ 1.183773] system 00:05: [io 0x0500-0x057f] has been reserved
[ 1.183793] system 00:05: [io 0x164e-0x164f] has been reserved
[ 1.183798] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.183898] pnp 00:06: [io 0x0070-0x0077]
[ 1.183915] pnp 00:06: [irq 8]
[ 1.184286] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active)
[ 1.184728] pnp 00:07: [io 0x0454-0x0457]
[ 1.185254] system 00:07: [io 0x0454-0x0457] has been reserved
[ 1.185261] system 00:07: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
[ 1.185615] pnp 00:08: [io 0x0010-0x001f]
[ 1.185623] pnp 00:08: [io 0x0022-0x003f]
[ 1.185631] pnp 00:08: [io 0x0044-0x005f]
[ 1.185638] pnp 00:08: [io 0x0072-0x007f]
[ 1.185655] pnp 00:08: [io 0x0080]
[ 1.185663] pnp 00:08: [io 0x0084-0x0086]
[ 1.185672] pnp 00:08: [io 0x0088]
[ 1.185680] pnp 00:08: [io 0x008c-0x008e]
[ 1.185687] pnp 00:08: [io 0x0090-0x009f]
[ 1.185694] pnp 00:08: [io 0x00a2-0x00bf]
[ 1.185702] pnp 00:08: [io 0x00e0-0x00ef]
[ 1.185709] pnp 00:08: [io 0x04d0-0x04d1]
[ 1.186142] system 00:08: [io 0x04d0-0x04d1] has been reserved
[ 1.186149] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.186245] pnp 00:09: [io 0x00f0-0x00ff]
[ 1.186258] pnp 00:09: [irq 13]
[ 1.186621] pnp 00:09: Plug and Play ACPI device, IDs PNP0c04 (active)
[ 1.187397] pnp 00:0a: [irq 12]
[ 1.187813] pnp 00:0a: Plug and Play ACPI device, IDs ETD0105 SYN0a00 SYN0002 PNP0f03 PNP0f13 PNP0f12 (active)
[ 1.188138] pnp 00:0b: [io 0x0060]
[ 1.188146] pnp 00:0b: [io 0x0064]
[ 1.188159] pnp 00:0b: [irq 1]
[ 1.188532] pnp 00:0b: Plug and Play ACPI device, IDs PNP0303 PNP030b (active)
[ 1.192554] pnp 00:0c: [mem 0xfed1c000-0xfed1ffff]
[ 1.192564] pnp 00:0c: [mem 0xfed10000-0xfed17fff]
[ 1.192571] pnp 00:0c: [mem 0xfed18000-0xfed18fff]
[ 1.192579] pnp 00:0c: [mem 0xfed19000-0xfed19fff]
[ 1.192587] pnp 00:0c: [mem 0xf8000000-0xfbffffff]
[ 1.192594] pnp 00:0c: [mem 0xfed20000-0xfed3ffff]
[ 1.192603] pnp 00:0c: [mem 0xfed90000-0xfed93fff]
[ 1.192610] pnp 00:0c: [mem 0xfed45000-0xfed8ffff]
[ 1.192618] pnp 00:0c: [mem 0xff000000-0xffffffff]
[ 1.192625] pnp 00:0c: [mem 0xfee00000-0xfeefffff]
[ 1.192633] pnp 00:0c: [mem 0xdfe00000-0xdfe00fff]
[ 1.193080] system 00:0c: [mem 0xfed1c000-0xfed1ffff] has been reserved
[ 1.193102] system 00:0c: [mem 0xfed10000-0xfed17fff] has been reserved
[ 1.193122] system 00:0c: [mem 0xfed18000-0xfed18fff] has been reserved
[ 1.193142] system 00:0c: [mem 0xfed19000-0xfed19fff] has been reserved
[ 1.193163] system 00:0c: [mem 0xf8000000-0xfbffffff] has been reserved
[ 1.193183] system 00:0c: [mem 0xfed20000-0xfed3ffff] has been reserved
[ 1.193204] system 00:0c: [mem 0xfed90000-0xfed93fff] has been reserved
[ 1.193227] system 00:0c: [mem 0xfed45000-0xfed8ffff] has been reserved
[ 1.193247] system 00:0c: [mem 0xff000000-0xffffffff] has been reserved
[ 1.193269] system 00:0c: [mem 0xfee00000-0xfeefffff] could not be reserved
[ 1.193289] system 00:0c: [mem 0xdfe00000-0xdfe00fff] has been reserved
[ 1.193295] system 00:0c: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.194649] pnp 00:0d: [mem 0xdfe00000-0xdfe00fff]
[ 1.195090] system 00:0d: [mem 0xdfe00000-0xdfe00fff] has been reserved
[ 1.195097] system 00:0d: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.197856] pnp 00:0e: [mem 0x20000000-0x201fffff]
[ 1.197864] pnp 00:0e: [mem 0x40004000-0x40004fff]
[ 1.198305] system 00:0e: [mem 0x20000000-0x201fffff] has been reserved
[ 1.198327] system 00:0e: [mem 0x40004000-0x40004fff] has been reserved
[ 1.198333] system 00:0e: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 1.198580] pnp: PnP ACPI: found 15 devices
[ 1.198583] ACPI: ACPI bus type pnp unregistered
[ 1.231203] pci 0000:00:04.0: BAR 0: assigned [mem 0xdfe08000-0xdfe0ffff 64bit]
[ 1.231217] pci 0000:00:1c.0: PCI bridge to [bus 01]
[ 1.231235] pci 0000:00:1c.1: PCI bridge to [bus 02]
[ 1.231243] pci 0000:00:1c.1: bridge window [mem 0xf7c00000-0xf7cfffff]
[ 1.231350] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7]
[ 1.231352] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff]
[ 1.231355] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
[ 1.231357] pci_bus 0000:00: resource 7 [mem 0x000d0000-0x000d3fff]
[ 1.231360] pci_bus 0000:00: resource 8 [mem 0x000d4000-0x000d7fff]
[ 1.231362] pci_bus 0000:00: resource 9 [mem 0x000d8000-0x000dbfff]
[ 1.231365] pci_bus 0000:00: resource 10 [mem 0x000dc000-0x000dffff]
[ 1.231367] pci_bus 0000:00: resource 11 [mem 0xdfe00000-0xfeafffff]
[ 1.231370] pci_bus 0000:02: resource 1 [mem 0xf7c00000-0xf7cfffff]
[ 1.231504] NET: Registered protocol family 2
[ 1.232132] TCP established hash table entries: 262144 (order: 10, 4194304 bytes)
[ 1.232887] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[ 1.233044] TCP: Hash tables configured (established 262144 bind 65536)
[ 1.233102] TCP: reno registered
[ 1.233111] UDP hash table entries: 2048 (order: 4, 65536 bytes)
[ 1.233132] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
[ 1.233457] NET: Registered protocol family 1
[ 1.233503] pci 0000:00:02.0: Boot video device
[ 1.265615] PCI: CLS 64 bytes, default 64
[ 1.265835] Trying to unpack rootfs image as initramfs...
[ 1.684671] Freeing initrd memory: 14872k freed
[ 1.687126] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[ 1.687135] software IO TLB [mem 0xca89f000-0xce89efff] (64MB) mapped at [ffff8800ca89f000-ffff8800ce89efff]
[ 1.688499] microcode: CPU0 sig=0x306a9, pf=0x10, revision=0x12
[ 1.688528] microcode: CPU1 sig=0x306a9, pf=0x10, revision=0x12
[ 1.688932] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
[ 1.690413] sha1_ssse3: Using AVX optimized SHA-1 implementation
[ 1.692176] audit: initializing netlink socket (disabled)
[ 1.692223] type=2000 audit(1350811312.582:1): initialized
[ 1.693994] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 1.717224] VFS: Disk quotas dquot_6.5.2
[ 1.717682] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 1.722339] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 1.722833] ROMFS MTD (C) 2007 Red Hat, Inc.
[ 1.723538] fuse init (API version 7.20)
[ 1.724644] msgmni has been set to 7673
[ 1.726357] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
[ 1.726364] io scheduler noop registered
[ 1.726367] io scheduler deadline registered
[ 1.726395] io scheduler cfq registered (default)
[ 1.726493] xz_dec_test: module loaded
[ 1.726496] xz_dec_test: Create a device node with 'mknod xz_dec_test c 251 0' and write .xz files to it.
[ 1.728179] intel_idle: MWAIT substates: 0x21120
[ 1.728182] intel_idle: v0.4 model 0x3A
[ 1.728184] intel_idle: lapic_timer_reliable_states 0xffffffff
[ 1.729972] ACPI: AC Adapter [AC0] (off-line)
[ 1.731201] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0
[ 1.737255] ACPI: Lid Switch [LID]
[ 1.737940] input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input1
[ 1.737956] ACPI: Power Button [PWRB]
[ 1.738558] input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input2
[ 1.738572] ACPI: Sleep Button [SLPB]
[ 1.743160] ACPI: Requesting acpi_cpufreq
[ 1.843166] thermal LNXTHERM:00: registered as thermal_zone0
[ 1.843174] ACPI: Thermal Zone [THRM] (58 C)
[ 1.844714] GHES: HEST is not enabled!
[ 1.844718] ERST DBG: ERST support is disabled.
[ 1.845108] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 1.851680] Linux agpgart interface v0.103
[ 1.852674] Hangcheck: starting hangcheck timer 0.9.1 (tick is 180 seconds, margin is 60 seconds).
[ 1.852681] Hangcheck: Using getrawmonotonic().
[ 1.853183] [drm] Initialized drm 1.1.0 20060810
[ 1.874817] brd: module loaded
[ 1.883741] loop: module loaded
[ 1.884499] ahci 0000:00:1f.2: version 3.0
[ 1.884741] ahci 0000:00:1f.2: irq 40 for MSI/MSI-X
[ 1.884924] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x1 impl SATA mode
[ 1.884932] ahci 0000:00:1f.2: flags: 64bit ncq pm led clo pio slum part ems apst
[ 1.884942] ahci 0000:00:1f.2: setting latency timer to 64
[ 1.895661] scsi0 : ahci
[ 1.897016] scsi1 : ahci
[ 1.898033] scsi2 : ahci
[ 1.899669] scsi3 : ahci
[ 1.900670] scsi4 : ahci
[ 1.901669] scsi5 : ahci
[ 1.902593] ata1: SATA max UDMA/133 abar m2048@0xf7d1e000 port 0xf7d1e100 irq 40
[ 1.902598] ata2: DUMMY
[ 1.902601] ata3: DUMMY
[ 1.902603] ata4: DUMMY
[ 1.902606] ata5: DUMMY
[ 1.902608] ata6: DUMMY
[ 1.903311] e1000e: Intel(R) PRO/1000 Network Driver - 2.1.4-k
[ 1.903316] e1000e: Copyright(c) 1999 - 2012 Intel Corporation.
[ 1.904157] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 1.904280] ehci_hcd 0000:00:1a.0: setting latency timer to 64
[ 1.904285] ehci_hcd 0000:00:1a.0: EHCI Host Controller
[ 1.904847] ehci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 1
[ 1.908826] ehci_hcd 0000:00:1a.0: debug port 2
[ 1.908838] ehci_hcd 0000:00:1a.0: cache line size of 64 is not supported
[ 1.908964] ehci_hcd 0000:00:1a.0: irq 16, io mem 0xf7d20000
[ 1.914787] ehci_hcd 0000:00:1a.0: USB 2.0 started, EHCI 1.00
[ 1.915032] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 1.915037] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 1.915042] usb usb1: Product: EHCI Host Controller
[ 1.915046] usb usb1: Manufacturer: Linux 3.7.0-rc1-00337-g5b9b8e9 ehci_hcd
[ 1.915050] usb usb1: SerialNumber: 0000:00:1a.0
[ 1.937080] ACPI: Battery Slot [BAT0] (battery present)
[ 1.938256] hub 1-0:1.0: USB hub found
[ 1.938328] hub 1-0:1.0: 2 ports detected
[ 1.940547] ehci_hcd 0000:00:1d.0: setting latency timer to 64
[ 1.940552] ehci_hcd 0000:00:1d.0: EHCI Host Controller
[ 1.941128] ehci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
[ 1.945100] ehci_hcd 0000:00:1d.0: debug port 2
[ 1.945113] ehci_hcd 0000:00:1d.0: cache line size of 64 is not supported
[ 1.945235] ehci_hcd 0000:00:1d.0: irq 23, io mem 0xf7d1f000
[ 1.950776] ehci_hcd 0000:00:1d.0: USB 2.0 started, EHCI 1.00
[ 1.951020] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
[ 1.951026] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 1.951031] usb usb2: Product: EHCI Host Controller
[ 1.951035] usb usb2: Manufacturer: Linux 3.7.0-rc1-00337-g5b9b8e9 ehci_hcd
[ 1.951039] usb usb2: SerialNumber: 0000:00:1d.0
[ 1.952668] hub 2-0:1.0: USB hub found
[ 1.952750] hub 2-0:1.0: 2 ports detected
[ 1.955060] uhci_hcd: USB Universal Host Controller Interface driver
[ 1.955518] usbcore: registered new interface driver uas
[ 1.955984] usbcore: registered new interface driver usbserial
[ 1.956178] usbcore: registered new interface driver usbserial_generic
[ 1.956374] usbserial: USB Serial support registered for generic
[ 1.956859] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12
[ 1.958740] i8042: Detected active multiplexing controller, rev 1.1
[ 1.959647] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 1.959667] serio: i8042 AUX0 port at 0x60,0x64 irq 12
[ 1.959897] serio: i8042 AUX1 port at 0x60,0x64 irq 12
[ 1.959926] serio: i8042 AUX2 port at 0x60,0x64 irq 12
[ 1.959942] serio: i8042 AUX3 port at 0x60,0x64 irq 12
[ 1.961019] mousedev: PS/2 mouse device common for all mice
[ 1.962633] rtc_cmos 00:06: RTC can wake from S4
[ 1.963431] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0
[ 1.963490] rtc0: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
[ 1.964111] ACPI Warning: 0x000000000000f040-0x000000000000f05f SystemIO conflicts with Region \SMB0 1 (20120913/utaddress-251)
[ 1.964130] ACPI Warning: 0x000000000000f040-0x000000000000f05f SystemIO conflicts with Region \_SB_.PCI0.SBUS.SMBI 2 (20120913/utaddress-251)
[ 1.964140] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
[ 1.965358] device-mapper: uevent: version 1.0.3
[ 1.966159] device-mapper: ioctl: 4.23.0-ioctl (2012-07-25) initialised: dm-devel@redhat.com
[ 1.966694] device-mapper: multipath: version 1.5.0 loaded
[ 1.966703] device-mapper: multipath round-robin: version 1.0.0 loaded
[ 1.968077] cpuidle: using governor ladder
[ 1.968779] cpuidle: using governor menu
[ 1.968783] EFI Variables Facility v0.08 2004-May-17
[ 1.997210] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3
[ 2.021588] usbcore: registered new interface driver usbhid
[ 2.021594] usbhid: USB HID core driver
[ 2.021781] TCP: cubic registered
[ 2.023685] NET: Registered protocol family 10
[ 2.024480] NET: Registered protocol family 17
[ 2.024506] 8021q: 802.1Q VLAN Support v1.8
[ 2.024616] Key type dns_resolver registered
[ 2.024619] openvswitch: Open vSwitch switching datapath
[ 2.027762] PM: Checking hibernation image partition /dev/sda2
[ 2.206490] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 2.217885] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out
[ 2.217949] ata1.00: ACPI cmd ef/10:06:00:00:00:a0 (SET FEATURES) succeeded
[ 2.217952] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
[ 2.218318] ata1.00: ATA-9: SanDisk SSD U100 124GB, 10.51.02, max UDMA/133
[ 2.218326] ata1.00: 242187500 sectors, multi 1: LBA48 NCQ (depth 31/32)
[ 2.231258] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out
[ 2.231318] ata1.00: ACPI cmd ef/10:06:00:00:00:a0 (SET FEATURES) succeeded
[ 2.231321] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
[ 2.231717] ata1.00: configured for UDMA/133
[ 2.232259] scsi 0:0:0:0: Direct-Access ATA SanDisk SSD U100 10.5 PQ: 0 ANSI: 5
[ 2.235383] sd 0:0:0:0: [sda] 242187500 512-byte logical blocks: (124 GB/115 GiB)
[ 2.235954] sd 0:0:0:0: [sda] Write Protect is off
[ 2.235960] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.236124] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 2.236455] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.241440] usb 1-1: new high-speed USB device number 2 using ehci_hcd
[ 2.243781] sda: sda1 sda2 sda3 sda4 sda5
[ 2.249050] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.249072] PM: Hibernation image partition 8:2 present
[ 2.249075] PM: Looking for hibernation image.
[ 2.249840] PM: Image not found (code -22)
[ 2.249842] PM: Hibernation image not present or could not be loaded.
[ 2.249870] registered taskstats version 1
[ 2.249953] kmemleak: Kernel memory leak detector initialized
[ 2.249955] kmemleak: Automatic memory scanning thread started
[ 2.251231] Magic number: 0:379:374
[ 2.251277] acpi LNXVIDEO:00: hash matches
[ 2.251437] console [netcon0] enabled
[ 2.251440] netconsole: network logging started
[ 2.251496] rtc_cmos 00:06: setting system clock to 2012-10-21 09:21:53 UTC (1350811313)
[ 2.260286] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found
[ 2.260290] EDD information not available.
[ 2.263014] Freeing unused kernel memory: 800k freed
[ 2.263102] Write protecting the kernel read-only data: 8192k
[ 2.266711] Freeing unused kernel memory: 1332k freed
[ 2.267101] Freeing unused kernel memory: 60k freed
[ 2.338754] udevd[1000]: starting version 175
[ 2.355605] usb 1-1: New USB device found, idVendor=8087, idProduct=0024
[ 2.355613] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 2.356376] hub 1-1:1.0: USB hub found
[ 2.356467] hub 1-1:1.0: 6 ports detected
[ 2.589724] EXT4-fs (sda4): INFO: recovery required on readonly filesystem
[ 2.589730] EXT4-fs (sda4): write access will be enabled during recovery
[ 2.596021] usb 2-1: new high-speed USB device number 2 using ehci_hcd
[ 2.687888] tsc: Refined TSC clocksource calibration: 1696.145 MHz
[ 2.687898] Switching to clocksource tsc
[ 2.710342] usb 2-1: New USB device found, idVendor=8087, idProduct=0024
[ 2.710348] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 2.711055] hub 2-1:1.0: USB hub found
[ 2.711190] hub 2-1:1.0: 6 ports detected
[ 2.820850] usb 1-1.2: new high-speed USB device number 3 using ehci_hcd
[ 2.906594] usb 1-1.2: New USB device found, idVendor=0bda, idProduct=0139
[ 2.906604] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 2.906610] usb 1-1.2: Product: USB2.0-CRW
[ 2.906614] usb 1-1.2: Manufacturer: Generic
[ 2.906618] usb 1-1.2: SerialNumber: 20100201396000000
[ 3.006595] EXT4-fs (sda4): recovery complete
[ 3.007679] EXT4-fs (sda4): mounted filesystem with ordered data mode. Opts: (null)
[ 3.020592] usb 2-1.5: new high-speed USB device number 3 using ehci_hcd
[ 3.199114] usb 2-1.5: New USB device found, idVendor=04f2, idProduct=b330
[ 3.199168] usb 2-1.5: New USB device strings: Mfr=3, Product=1, SerialNumber=2
[ 3.199172] usb 2-1.5: Product: USB2.0 HD UVC WebCam
[ 3.199175] usb 2-1.5: Manufacturer: Chicony Electronics Co.,Ltd.
[ 3.199178] usb 2-1.5: SerialNumber: 200901010001
[ 3.278380] usb 2-1.6: new full-speed USB device number 4 using ehci_hcd
[ 3.341168] usb 2-1.6: device descriptor read/64, error -32
[ 3.434551] Adding 4077564k swap on /dev/sda5. Priority:-1 extents:1 across:4077564k SS
[ 3.484046] udevd[1247]: starting version 175
[ 3.527974] usb 2-1.6: New USB device found, idVendor=0cf3, idProduct=3005
[ 3.527978] usb 2-1.6: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 3.791446] wmi: Mapper loaded
[ 3.858437] Bluetooth: Core ver 2.16
[ 3.858495] NET: Registered protocol family 31
[ 3.858496] Bluetooth: HCI device and connection manager initialized
[ 3.858511] Bluetooth: HCI socket layer initialized
[ 3.858519] Bluetooth: L2CAP socket layer initialized
[ 3.858542] Bluetooth: SCO socket layer initialized
[ 3.907984] EXT4-fs (sda4): re-mounted. Opts: errors=remount-ro
[ 3.935325] xhci_hcd 0000:00:14.0: setting latency timer to 64
[ 3.935330] xhci_hcd 0000:00:14.0: xHCI Host Controller
[ 3.935770] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 3
[ 3.935979] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
[ 3.936003] xhci_hcd 0000:00:14.0: irq 16, io mem 0xf7d00000
[ 3.936080] xhci_hcd 0000:00:14.0: irq 41 for MSI/MSI-X
[ 3.936408] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002
[ 3.936410] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.936412] usb usb3: Product: xHCI Host Controller
[ 3.936414] usb usb3: Manufacturer: Linux 3.7.0-rc1-00337-g5b9b8e9 xhci_hcd
[ 3.936415] usb usb3: SerialNumber: 0000:00:14.0
[ 3.937237] xHCI xhci_add_endpoint called for root hub
[ 3.937238] xHCI xhci_check_bandwidth called for root hub
[ 3.937592] hub 3-0:1.0: USB hub found
[ 3.937646] hub 3-0:1.0: 4 ports detected
[ 3.954589] usbcore: registered new interface driver btusb
[ 3.993197] cfg80211: Calling CRDA to update world regulatory domain
[ 4.110021] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[ 2.238958] ACPI: Invalid Power Resource to register!
[ 4.129555] asus_wmi: ASUS WMI generic driver loaded<6>[ 4.132040] cfg80211: World regulatory domain updated:
[ 4.132042] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
[ 4.132044] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[ 4.132046] cfg80211: (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[ 4.132047] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[ 4.132049] cfg80211: (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[ 4.132050] cfg80211: (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[ 4.140204] asus_wmi: Initialization: 0x1
[ 4.143174] asus_wmi: BIOS WMI version: 7.9<6>[ 4.152400] xhci_hcd 0000:00:14.0: xHCI Host Controller
[ 4.153176] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 4
[ 4.154335] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003
[ 4.154338] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 4.154340] usb usb4: Product: xHCI Host Controller
[ 4.154341] usb usb4: Manufacturer: Linux 3.7.0-rc1-00337-g5b9b8e9 xhci_hcd
[ 4.154343] usb usb4: SerialNumber: 0000:00:14.0
[ 4.161407] xHCI xhci_add_endpoint called for root hub
[ 4.161410] xHCI xhci_check_bandwidth called for root hub
[ 4.161791] hub 4-0:1.0: USB hub found
[ 4.161855] hub 4-0:1.0: 4 ports detected
[ 4.144600] asus_wmi: SFUN value: 0x4a2877
[ 4.235019] input: Asus WMI hotkeys as /devices/platform/asus-nb-wmi/input/input4
[ 4.258766] pci 0000:00:00.0: Intel Ivybridge Chipset
[ 4.259948] pci 0000:00:00.0: detected gtt size: 2097152K total, 262144K mappable
[ 4.260831] pci 0000:00:00.0: detected 65536K stolen memory
[ 4.260884] i915 0000:00:02.0: setting latency timer to 64
[ 4.311662] rts5139: module is from the staging directory, the quality is unknown, you have been warned.
[ 4.314961] [drm:__gen6_gt_force_wake_mt_get] *ERROR* Timed out waiting for forcewake old ack to clear.
[ 4.322650] rts51x: rts5139 detected
[ 4.324967] i915 0000:00:02.0: irq 42 for MSI/MSI-X
[ 4.325137] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[ 4.325138] [drm] Driver supports precise vblank timestamp query.
[ 4.325612] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[ 4.334369] psmouse serio4: elantech: assuming hardware version 4 (with firmware version 0x361f02)
[ 4.335387] rts51x: Vendor: 0x0bda, Product: 0x0139, Revision: 0x3960
[ 4.335389] rts51x: Interface Subclass: 0x06, Protocol: 0x50
[ 4.339753] rts51x: HW_VERSION: 0x2
[ 4.339755] rts51x: ASIC!
[ 4.339756] rts51x: sd_speed_prior = 0x01020403
[ 4.340929] rts51x: Package: LQFP48
[ 4.341589] rts51x: USB High Speed
[ 4.347385] psmouse serio4: elantech: Synaptics capabilities query result 0x00, 0x15, 0x0e.
[ 4.371286] rts51x: option enable UHS50&MMC44,sd_ctl:0x4a
[ 4.371288] rts51x: Write 0x7c to phy register 0xc2
[ 4.371665] rts51x: Enable OCP detect!
[ 4.418409] scsi6 : SCSI emulation for RTS5139 USB card reader
[ 4.419550] rts51x: Command INQUIRY (6 bytes)
[ 4.419607] scsi 6:0:0:0: Direct-Access Generic- xD/SD/M.S. 1.00 PQ: 0 ANSI: 0 CCS
[ 4.419886] usbcore: registered new interface driver rts5139
[ 4.419890] rts51x: Bad LUN (0:1)
[ 4.420132] rts51x: Bad target number (1:0)
[ 4.420361] rts51x: Bad target number (2:0)
[ 4.420613] rts51x: Bad target number (3:0)
[ 4.420892] rts51x: Bad target number (4:0)
[ 4.421124] rts51x: Bad target number (5:0)
[ 4.421359] rts51x: Bad target number (6:0)
[ 4.421584] rts51x: Bad target number (7:0)
[ 4.422728] sd 6:0:0:0: Attached scsi generic sg1 type 0
[ 4.454472] sd 6:0:0:0: [sdb] Attached SCSI removable disk
[ 4.477000] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
[ 4.543308] Registered led device: asus::kbd_backlight
[ 4.554030] input: ETPS/2 Elantech Touchpad as /devices/platform/i8042/serio4/input/input5
[ 4.590767] ath: EEPROM regdomain: 0x60
[ 4.590769] ath: EEPROM indicates we should expect a direct regpair map
[ 4.590772] ath: Country alpha2 being used: 00
[ 4.590773] ath: Regpair used: 0x60
[ 4.680516] ieee80211 phy0: Selected rate control algorithm 'ath9k_rate_control'
[ 4.683072] Registered led device: ath9k-phy0
[ 4.683078] ieee80211 phy0: Atheros AR9285 Rev:2 mem=0xffffc900040a0000, irq=17
[ 4.788147] asus_wmi: Backlight controlled by ACPI video driver
[ 4.828631] fbcon: inteldrmfb (fb0) is primary device
[ 4.992684] rts51x: Idle state!
[ 4.992689] rts51x: rts51x_ctrl_transfer: rq=00 rqtype=40 value=56fd index=303 len=0
[ 4.993048] rts51x: Close SSC clock power!
[ 5.589323] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
[ 5.825117] [drm:intel_cpt_verify_modeset] *ERROR* mode set failed: pipe 0 stuck
[ 6.054571] Console: switching to colour frame buffer device 160x64
[ 6.066422] fb0: inteldrmfb frame buffer device
[ 6.066423] drm: registered panic notifier
[ 6.111590] init: failsafe main process (1732) killed by TERM signal
[ 6.273540] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[ 6.273543] Bluetooth: BNEP filters: protocol multicast
[ 6.273566] Bluetooth: BNEP socket layer initialized
[ 6.281218] type=1400 audit(1350804117.533:2): apparmor="STATUS" operation="profile_load" name="/usr/lib/cups/backend/cups-pdf" pid=1875 comm="apparmor_parser"
[ 6.281702] type=1400 audit(1350804117.534:3): apparmor="STATUS" operation="profile_load" name="/usr/sbin/cupsd" pid=1875 comm="apparmor_parser"
[ 6.303720] type=1400 audit(1350804117.556:4): apparmor="STATUS" operation="profile_load" name="/usr/lib/x86_64-linux-gnu/lightdm-remote-session-freerdp/freerdp-session-wrapper" pid=1912 comm="apparmor_parser"
[ 6.304045] type=1400 audit(1350804117.556:5): apparmor="STATUS" operation="profile_load" name="/usr/lib/x86_64-linux-gnu/lightdm-remote-session-freerdp/freerdp-session-wrapper//chromium_browser" pid=1912 comm="apparmor_parser"
[ 6.306145] type=1400 audit(1350804117.558:6): apparmor="STATUS" operation="profile_load" name="/usr/lib/lightdm/lightdm/lightdm-guest-session-wrapper" pid=1911 comm="apparmor_parser"
[ 6.306466] type=1400 audit(1350804117.558:7): apparmor="STATUS" operation="profile_load" name="/usr/lib/lightdm/lightdm/lightdm-guest-session-wrapper//chromium_browser" pid=1911 comm="apparmor_parser"
[ 6.307770] ACPI Warning: _BQC returned an invalid level (20120913/video-472)
[ 6.333319] type=1400 audit(1350804117.585:8): apparmor="STATUS" operation="profile_load" name="/usr/lib/x86_64-linux-gnu/lightdm-remote-session-uccsconfigure/uccsconfigure-session-wrapper" pid=1916 comm="apparmor_parser"
[ 6.333692] type=1400 audit(1350804117.586:9): apparmor="STATUS" operation="profile_load" name="/usr/lib/x86_64-linux-gnu/lightdm-remote-session-uccsconfigure/uccsconfigure-session-wrapper//chromium_browser" pid=1916 comm="apparmor_parser"
[ 6.338268] Bluetooth: RFCOMM TTY layer initialized
[ 6.338295] Bluetooth: RFCOMM socket layer initialized
[ 6.338296] Bluetooth: RFCOMM ver 1.11
[ 6.339522] IPv6: ADDRCONF(NETDEV_UP): wlan1: link is not ready
[ 6.344653] type=1400 audit(1350804117.597:10): apparmor="STATUS" operation="profile_load" name="/sbin/dhclient" pid=1917 comm="apparmor_parser"
[ 6.356297] acpi device:35: registered as cooling_device2
[ 6.373203] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no)
[ 6.380443] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input6
[ 6.385380] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
[ 6.385644] snd_hda_intel 0000:00:1b.0: irq 43 for MSI/MSI-X
[ 6.466501] ALSA patch_realtek.c:1241 SKU: Nid=0x1d sku_cfg=0x40079a2d
[ 6.466502] ALSA patch_realtek.c:1243 SKU: port_connectivity=0x1
[ 6.466503] ALSA patch_realtek.c:1244 SKU: enable_pcbeep=0x0
[ 6.466504] ALSA patch_realtek.c:1245 SKU: check_sum=0x00000007
[ 6.466505] ALSA patch_realtek.c:1246 SKU: customization=0x0000009a
[ 6.466506] ALSA patch_realtek.c:1247 SKU: external_amp=0x5
[ 6.466506] ALSA patch_realtek.c:1248 SKU: platform_type=0x1
[ 6.466507] ALSA patch_realtek.c:1249 SKU: swap=0x0
[ 6.466508] ALSA patch_realtek.c:1250 SKU: override=0x1
[ 6.467076] ALSA hda_auto_parser.c:318 autoconfig: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
[ 6.467078] ALSA hda_auto_parser.c:322 speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
[ 6.467079] ALSA hda_auto_parser.c:326 hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
[ 6.467080] ALSA hda_auto_parser.c:327 mono: mono_out=0x0
[ 6.467081] ALSA hda_auto_parser.c:331 inputs:
[ 6.467082] ALSA hda_auto_parser.c:335 Internal Mic=0x12
[ 6.467083] ALSA hda_auto_parser.c:335 Mic=0x18
[ 6.468396] ALSA patch_realtek.c:1304 realtek: No valid SSID, checking pincfg 0x40079a2d for NID 0x1d
[ 6.468397] ALSA patch_realtek.c:1320 realtek: Enabling init ASM_ID=0x9a2d CODEC_ID=10ec0269
[ 6.511522] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1b.0/sound/card0/input7
[ 6.525284] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8
[ 6.526159] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9
[ 8.193299] ------------[ cut here ]------------
[ 8.193332] WARNING: at /home/lex/tmp/linux/drivers/gpu/drm/i915/intel_display.c:1019 intel_wait_for_pipe_off+0x134/0x141 [i915]()
[ 8.193335] Hardware name: UX31A
[ 8.193336] pipe_off wait timed out
[ 8.193338] Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek rfcomm bnep arc4 nls_iso8859_1 ath9k snd_hda_intel snd_hda_codec nls_cp437 snd_hwdep mac80211 snd_pcm_oss vfat fat snd_mixer_oss snd_pcm rts5139(C) coretemp kvm_intel snd_seq_dummy kvm snd_seq_oss snd_seq_midi snd_rawmidi ath9k_common ath9k_hw asus_nb_wmi asus_wmi snd_seq_midi_event i915 sparse_keymap pci_hotplug crc32c_intel snd_seq ath snd_timer snd_seq_device cfg80211 drm_kms_helper psmouse cfbcopyarea snd xhci_hcd aesni_intel btusb cfbimgblt bluetooth serio_raw cfbfillrect soundcore snd_page_alloc wmi
[ 8.193390] Pid: 2105, comm: Xorg Tainted: G C 3.7.0-rc1-00337-g5b9b8e9 #26
[ 8.193392] Call Trace:
[ 8.193401] [<ffffffff81042ee3>] warn_slowpath_common+0x83/0x9c
[ 8.193406] [<ffffffff81042f9f>] warn_slowpath_fmt+0x46/0x48
[ 8.193425] [<ffffffffa01b57e9>] intel_wait_for_pipe_off+0x134/0x141 [i915]
[ 8.193440] [<ffffffffa01b5921>] intel_disable_pipe+0x12b/0x133 [i915]
[ 8.193455] [<ffffffffa01b5f8a>] ironlake_crtc_disable+0xcb/0x7a2 [i915]
[ 8.193473] [<ffffffffa01c3856>] ? intel_dp_mode_fixup+0x1ea/0x22a [i915]
[ 8.193490] [<ffffffffa01bb77c>] intel_set_mode+0x3c4/0x812 [i915]
[ 8.193498] [<ffffffff8108aa34>] ? __module_text_address+0x12/0x58
[ 8.193515] [<ffffffffa01bc1b0>] intel_crtc_set_config+0x5e6/0x78e [i915]
[ 8.193521] [<ffffffff81212e32>] ? snprintf+0x34/0x36
[ 8.193527] [<ffffffff812c45eb>] drm_mode_setcrtc+0x421/0x484
[ 8.193531] [<ffffffff812b7400>] drm_ioctl+0x2d0/0x3b5
[ 8.193535] [<ffffffff812c41ca>] ? drm_mode_setplane+0x2f8/0x2f8
[ 8.193542] [<ffffffff8104990b>] ? local_bh_enable_ip+0xe/0x10
[ 8.193547] [<ffffffff811145ae>] vfs_ioctl+0x26/0x3d
[ 8.193551] [<ffffffff81114e7a>] do_vfs_ioctl+0x3f1/0x434
[ 8.193558] [<ffffffff814ac092>] ? _raw_spin_lock+0xe/0x10
[ 8.193561] [<ffffffff81114f14>] sys_ioctl+0x57/0x87
[ 8.193567] [<ffffffff813c2459>] ? sys_setsockopt+0x92/0xab
[ 8.193572] [<ffffffff814acd42>] system_call_fastpath+0x16/0x1b
[ 8.193575] ---[ end trace 655297f304e06882 ]---
[ 8.678359] wlan1: authenticate with 74:31:70:62:d3:cf
[ 8.688669] tun: Universal TUN/TAP device driver, 1.6
[ 8.688672] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
[ 8.706109] wlan1: send auth to 74:31:70:62:d3:cf (try 1/3)
[ 8.708064] wlan1: authenticated
[ 8.714711] wlan1: associate with 74:31:70:62:d3:cf (try 1/3)
[ 8.717458] wlan1: RX AssocResp from 74:31:70:62:d3:cf (capab=0x411 status=0 aid=2)
[ 8.717503] wlan1: associated
[ 8.717644] IPv6: ADDRCONF(NETDEV_CHANGE): wlan1: link becomes ready
[ 8.721484] IPv6: ADDRCONF(NETDEV_UP): tap0: link is not ready
[ 9.142135] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
[ 9.378932] [drm:intel_cpt_verify_modeset] *ERROR* mode set failed: pipe 0 stuck
[ 18.477029] ------------[ cut here ]------------
[ 18.477079] WARNING: at /home/lex/tmp/linux/drivers/gpu/drm/i915/intel_display.c:1019 intel_wait_for_pipe_off+0x134/0x141 [i915]()
[ 18.477082] Hardware name: UX31A
[ 18.477085] pipe_off wait timed out
[ 18.477087] Modules linked in: tun snd_hda_codec_hdmi snd_hda_codec_realtek rfcomm bnep arc4 nls_iso8859_1 ath9k snd_hda_intel snd_hda_codec nls_cp437 snd_hwdep mac80211 snd_pcm_oss vfat fat snd_mixer_oss snd_pcm rts5139(C) coretemp kvm_intel snd_seq_dummy kvm snd_seq_oss snd_seq_midi snd_rawmidi ath9k_common ath9k_hw asus_nb_wmi asus_wmi snd_seq_midi_event i915 sparse_keymap pci_hotplug crc32c_intel snd_seq ath snd_timer snd_seq_device cfg80211 drm_kms_helper psmouse cfbcopyarea snd xhci_hcd aesni_intel btusb cfbimgblt bluetooth serio_raw cfbfillrect soundcore snd_page_alloc wmi
[ 18.477164] Pid: 2105, comm: Xorg Tainted: G WC 3.7.0-rc1-00337-g5b9b8e9 #26
[ 18.477167] Call Trace:
[ 18.477183] [<ffffffff81042ee3>] warn_slowpath_common+0x83/0x9c
[ 18.477190] [<ffffffff81042f9f>] warn_slowpath_fmt+0x46/0x48
[ 18.477218] [<ffffffffa01b57e9>] intel_wait_for_pipe_off+0x134/0x141 [i915]
[ 18.477240] [<ffffffffa01b5921>] intel_disable_pipe+0x12b/0x133 [i915]
[ 18.477262] [<ffffffffa01b5f8a>] ironlake_crtc_disable+0xcb/0x7a2 [i915]
[ 18.477290] [<ffffffffa01c3856>] ? intel_dp_mode_fixup+0x1ea/0x22a [i915]
[ 18.477316] [<ffffffffa01bb77c>] intel_set_mode+0x3c4/0x812 [i915]
[ 18.477327] [<ffffffff8108aa34>] ? __module_text_address+0x12/0x58
[ 18.477354] [<ffffffffa01bc1b0>] intel_crtc_set_config+0x5e6/0x78e [i915]
[ 18.477362] [<ffffffff81212e32>] ? snprintf+0x34/0x36
[ 18.477371] [<ffffffff812c45eb>] drm_mode_setcrtc+0x421/0x484
[ 18.477378] [<ffffffff812b7400>] drm_ioctl+0x2d0/0x3b5
[ 18.477384] [<ffffffff812c41ca>] ? drm_mode_setplane+0x2f8/0x2f8
[ 18.477392] [<ffffffff810624c9>] ? __hrtimer_start_range_ns+0x295/0x2a7
[ 18.477400] [<ffffffff811145ae>] vfs_ioctl+0x26/0x3d
[ 18.477405] [<ffffffff81114e7a>] do_vfs_ioctl+0x3f1/0x434
[ 18.477411] [<ffffffff810624f3>] ? hrtimer_start+0x18/0x1a
[ 18.477419] [<ffffffff81048739>] ? do_setitimer+0x171/0x1b2
[ 18.477425] [<ffffffff81114f14>] sys_ioctl+0x57/0x87
[ 18.477433] [<ffffffff814acd42>] system_call_fastpath+0x16/0x1b
[ 18.477438] ---[ end trace 655297f304e06883 ]---
[ 19.414191] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
[ 19.651094] [drm:intel_cpt_verify_modeset] *ERROR* mode set failed: pipe 0 stuck
[ 25.734301] CPU1: Package power limit notification (total events = 1)
[ 25.734304] CPU0: Package power limit notification (total events = 1)
[ 25.739898] CPU1: Package power limit normal
[ 25.739900] CPU0: Package power limit normal
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/5] eDP improvements
2012-10-21 7:37 ` [PATCH 0/5] eDP improvements Oleksij Rempel
@ 2012-10-21 10:34 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2012-10-21 10:34 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: Intel Graphics Development
On Sun, Oct 21, 2012 at 9:37 AM, Oleksij Rempel
<bug-track@fisher-privat.net> wrote:
> i assume this patch set should/may fix this bug:
> https://bugs.freedesktop.org/show_bug.cgi?id=48652
>
> i tested it on top of linux/master + drm-intel-fixes + "[PATCH] drm/i915/dp:
> actually nack test request".
Yeah, you have the same issue as I do: eDP link training somehow fails.
> eDP is listed now and xserver use it. But eDP stays blank/black.
> I also got some warnings, see attached dmesg.
Those are expected, since we turn off the edp port when the link
training fails, which means that the entire display pipeline stops.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/5] drm/i915: make edp panel power sequence setup more robust
2012-10-20 18:57 ` [PATCH 1/5] drm/i915: make edp panel power sequence setup more robust Daniel Vetter
@ 2012-10-22 22:04 ` Jesse Barnes
2012-10-23 7:23 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: Jesse Barnes @ 2012-10-22 22:04 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Sat, 20 Oct 2012 20:57:41 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> 3 changes:
> - If a given value is unset, use the maximal limits from the eDP spec.
> - Write back the new values, since otherwise the panel power sequencing
> hw will not dtrt.
> - Revert the early bail-out in case the register values are unset.
>
> The last change reverts
>
> commit bfa3384a9a84aaaa59443bbd776c142e7dba4b0f
> Author: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Tue Apr 10 11:58:04 2012 -0700
>
> drm/i915: check PPS regs for sanity when using eDP
>
> v2:
> - Unlock the PP regs as the very first thing. This is a required w/a
> for cpu eDP on port A, and generally a good idea.
> - Fixup the panel power control port selection bits.
>
> v3: Paulo Zanoni noticed that I've fumbled the computation of the spec
> limit values. Fix them up. We've also noticed that the t8/t9 values in
> the vbt/bios-programmed pp are much larger than any limits. My guess
> is that this is to conceal any backlight enable/disable delays. So by
> using the much shorter limits from the spec, which only concerns the
> sink, we risk that we might display before the backlight is fully on,
> or disable the output while the backlight still has afterglow. I've
> figured I don't care too much, since this will only happen when both
> the pp regs are not programmed, and the vbt tables don't contain
> anything useful.
>
> v4: Don't set the port selection bits on hsw/LPT, they don't exist any
> more.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++
> drivers/gpu/drm/i915/intel_dp.c | 71 ++++++++++++++++++++++++++++++++++-------
> 2 files changed, 65 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b428fbb..3ecd8c3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4018,6 +4018,11 @@
> #define PANEL_LIGHT_ON_DELAY_SHIFT 0
>
> #define PCH_PP_OFF_DELAYS 0xc720c
> +#define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30)
> +#define PANEL_POWER_PORT_LVDS (0 << 30)
> +#define PANEL_POWER_PORT_DP_A (1 << 30)
> +#define PANEL_POWER_PORT_DP_C (2 << 30)
> +#define PANEL_POWER_PORT_DP_D (3 << 30)
> #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
> #define PANEL_POWER_DOWN_DELAY_SHIFT 16
> #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f2c9ea6..265cec1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2671,20 +2671,18 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>
> /* Cache some DPCD data in the eDP case */
> if (is_edp(intel_dp)) {
> - struct edp_power_seq cur, vbt;
> - u32 pp_on, pp_off, pp_div;
> + struct edp_power_seq cur, vbt, spec, final;
> + u32 pp_on, pp_off, pp_div, pp;
> +
> + /* Workaround: Need to write PP_CONTROL with the unlock key as
> + * the very first thing. */
> + pp = ironlake_get_pp_control(dev_priv);
> + I915_WRITE(PCH_PP_CONTROL, pp);
>
> pp_on = I915_READ(PCH_PP_ON_DELAYS);
> pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> pp_div = I915_READ(PCH_PP_DIVISOR);
>
> - if (!pp_on || !pp_off || !pp_div) {
> - DRM_INFO("bad panel power sequencing delays, disabling panel\n");
> - intel_dp_encoder_destroy(&intel_dp->base.base);
> - intel_dp_destroy(&intel_connector->base);
> - return;
> - }
> -
> /* Pull timing values out of registers */
> cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
> PANEL_POWER_UP_DELAY_SHIFT;
> @@ -2706,16 +2704,62 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>
> vbt = dev_priv->edp.pps;
>
> + /* Upper limits from eDP 1.3 spec. Note that we the clunky units
> + * of our hw here, which are all in 100usec. */
"we use the clunky" would be more sensible than "we the clunky"
> + spec.t1_t3 = 210 * 10;
> + spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
> + spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
> + spec.t10 = 500 * 10;
> + /* This one is special and actually in units of 100ms, but zero
> + * based in the hw (so we need to add 100 ms). But the sw vbt
> + * table multiplies it with 1000 to make it in units of 100usec,
> + * too. */
> + spec.t11_t12 = (510 + 100) * 10;
> +
> DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
> vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
>
> -#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
> -
> + /* Use the max of the register setttings and vbt. If both are
> + * unset, fall back to the spec limits. */
settings only needs two "t"s.
> +#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
> + spec.field : \
> + max(cur.field, vbt.field))
> + assign_final(t1_t3);
> + assign_final(t8);
> + assign_final(t9);
> + assign_final(t10);
> + assign_final(t11_t12);
> +#undef assign_final
If the current field is not zero and doesn't match the VBT, we might
add a debug statement. It could indicate a BIOS programmed value that
didn't involve a VBT update (I can imagine some vendors might do
this). Overwriting the current with the different VBT value may lead
to breakage or sub-optimal timings.
> +
> +#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
> intel_dp->panel_power_up_delay = get_delay(t1_t3);
> intel_dp->backlight_on_delay = get_delay(t8);
> intel_dp->backlight_off_delay = get_delay(t9);
> intel_dp->panel_power_down_delay = get_delay(t10);
> intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
> +#undef get_delay
> +
> + /* And finally store the new values in the power sequencer. */
> + pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
> + (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> + pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
> + (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> + pp_div = (pp_div & PP_REFERENCE_DIVIDER_MASK) |
> + (DIV_ROUND_UP(final.t11_t12, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT);
> +
> + /* Haswell doesn't have any port selection bits for the panel
> + * power sequence any more. */
> + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> + if (is_cpu_edp(intel_dp))
> + pp_on |= PANEL_POWER_PORT_DP_A;
> + else
> + pp_on |= PANEL_POWER_PORT_DP_D;
> + }
> +
> + I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
> + I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
> + I915_WRITE(PCH_PP_DIVISOR, pp_div);
> +
>
> DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
> intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
> @@ -2723,6 +2767,11 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>
> DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
> intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
> +
> + DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> + I915_READ(PCH_PP_ON_DELAYS),
> + I915_READ(PCH_PP_OFF_DELAYS),
> + I915_READ(PCH_PP_DIVISOR));
> }
>
> intel_dp_i2c_init(intel_dp, intel_connector, name);
I really hate the inline macros, but that's just me. It might be good
to factor out this stuff into a separate function too (I see you do
that in a later patch). Assuming you take care of the above.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/5] drm/i915: enable/disable backlight for eDP
2012-10-20 18:57 ` [PATCH 2/5] drm/i915: enable/disable backlight for eDP Daniel Vetter
@ 2012-10-22 22:04 ` Jesse Barnes
0 siblings, 0 replies; 17+ messages in thread
From: Jesse Barnes @ 2012-10-22 22:04 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Sat, 20 Oct 2012 20:57:42 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Like we already do for the LVDS panels. This seems to help greatly
> in setting up the backlight, since the BIOS might refuse to cooperate.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 265cec1..49846c0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1128,6 +1128,8 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
>
> DRM_DEBUG_KMS("Turn eDP power off\n");
>
> + intel_panel_disable_backlight(dev);
> +
> WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
>
> pp = ironlake_get_pp_control(dev_priv);
> @@ -1146,6 +1148,7 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + int pipe = to_intel_crtc(intel_dp->base.base.crtc)->pipe;
> u32 pp;
>
> if (!is_edp(intel_dp))
> @@ -1163,6 +1166,8 @@ static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
> pp |= EDP_BLC_ENABLE;
> I915_WRITE(PCH_PP_CONTROL, pp);
> POSTING_READ(PCH_PP_CONTROL);
> +
> + intel_panel_enable_backlight(dev, pipe);
> }
>
> static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
Probably wise.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/5] drm/i915/eDP: compute the panel power clock divisor from the pch rawclock
2012-10-20 18:57 ` [PATCH 3/5] drm/i915/eDP: compute the panel power clock divisor from the pch rawclock Daniel Vetter
@ 2012-10-22 22:07 ` Jesse Barnes
0 siblings, 0 replies; 17+ messages in thread
From: Jesse Barnes @ 2012-10-22 22:07 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Sat, 20 Oct 2012 20:57:43 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> We need this when the bios forgets even to set that bit up. Most seem
> to do that, even when they don't set up anything else in the panel
> power sequencer.
>
> Note that on IBX the rawclk is variable according to Bspec, but
> everyone is using 125MHz. The rawclk is fixed to 125MHz on CPT, but
> luckily we still have the same register available. On hsw, different
> variants have different clocks, hence we need to check the register.
>
> Since other pieces are driven by the rawclock, too, keep the little
> helper in a central place.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9c17a0a7..7fb032f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -80,6 +80,16 @@ struct intel_limit {
> /* FDI */
> #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
>
> +int
> +intel_pch_rawclk(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + WARN_ON(!HAS_PCH_SPLIT(dev));
> +
> + return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
> +}
> +
> static bool
> intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
> int target, int refclk, intel_clock_t *match_clock,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 49846c0..b35d5bd 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2749,8 +2749,12 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
> (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> - pp_div = (pp_div & PP_REFERENCE_DIVIDER_MASK) |
> - (DIV_ROUND_UP(final.t11_t12, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT);
> + /* Compute the divisor for the pp clock, simply match the Bspec
> + * formula. */
> + pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
> + << PP_REFERENCE_DIVIDER_SHIFT;
> + pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
> + << PANEL_POWER_CYCLE_DELAY_SHIFT);
>
> /* Haswell doesn't have any port selection bits for the panel
> * power sequence any more. */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index ed75a36..39bddd7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -396,6 +396,8 @@ struct intel_fbc_work {
> int interval;
> };
>
> +int intel_pch_rawclk(struct drm_device *dev);
> +
> int intel_connector_update_modes(struct drm_connector *connector,
> struct edid *edid);
> int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
Did you check that the calculation generally matched the existing value
on the machines you looked at?
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/5] drm/i915/dp: compute the pch dp aux divider from the rawclk
2012-10-20 18:57 ` [PATCH 4/5] drm/i915/dp: compute the pch dp aux divider from the rawclk Daniel Vetter
@ 2012-10-22 22:08 ` Jesse Barnes
0 siblings, 0 replies; 17+ messages in thread
From: Jesse Barnes @ 2012-10-22 22:08 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Sat, 20 Oct 2012 20:57:44 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Otherwise dp aux won't work on some hsw platforms, since they use a
> different rawclk than the 125MHz clock used thus far.
>
> To absolutely not change anything, round up: That way we get the old
> 63 divider for the default 125MHz clock.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b35d5bd..971c4e4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -372,7 +372,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> else
> aux_clock_divider = 225; /* eDP input clock at 450Mhz */
> } else if (HAS_PCH_SPLIT(dev))
> - aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
> + aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
> else
> aux_clock_divider = intel_hrawclk(dev) / 2;
>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/5] drm/i915: extract intel_dp_init_panel_power_sequencer
2012-10-20 18:57 ` [PATCH 5/5] drm/i915: extract intel_dp_init_panel_power_sequencer Daniel Vetter
@ 2012-10-22 22:08 ` Jesse Barnes
2012-10-23 15:24 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: Jesse Barnes @ 2012-10-22 22:08 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Sat, 20 Oct 2012 20:57:45 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> That thing has grown way too big already.
>
> Also move around a comment to the right spot.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 223 +++++++++++++++++++++-------------------
> 1 file changed, 115 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 971c4e4..b9b9d08 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2576,6 +2576,118 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
> intel_attach_broadcast_rgb_property(connector);
> }
>
> +static void
> +intel_dp_init_panel_power_sequencer(struct drm_device *dev,
> + struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct edp_power_seq cur, vbt, spec, final;
> + u32 pp_on, pp_off, pp_div, pp;
> +
> + /* Workaround: Need to write PP_CONTROL with the unlock key as
> + * the very first thing. */
> + pp = ironlake_get_pp_control(dev_priv);
> + I915_WRITE(PCH_PP_CONTROL, pp);
> +
> + pp_on = I915_READ(PCH_PP_ON_DELAYS);
> + pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> + pp_div = I915_READ(PCH_PP_DIVISOR);
> +
> + /* Pull timing values out of registers */
> + cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
> + PANEL_POWER_UP_DELAY_SHIFT;
> +
> + cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
> + PANEL_LIGHT_ON_DELAY_SHIFT;
> +
> + cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
> + PANEL_LIGHT_OFF_DELAY_SHIFT;
> +
> + cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> + PANEL_POWER_DOWN_DELAY_SHIFT;
> +
> + cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> + PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> +
> + DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
> + cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
> +
> + vbt = dev_priv->edp.pps;
> +
> + /* Upper limits from eDP 1.3 spec. Note that we the clunky units
> + * of our hw here, which are all in 100usec. */
> + spec.t1_t3 = 210 * 10;
> + spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
> + spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
> + spec.t10 = 500 * 10;
> + /* This one is special and actually in units of 100ms, but zero
> + * based in the hw (so we need to add 100 ms). But the sw vbt
> + * table multiplies it with 1000 to make it in units of 100usec,
> + * too. */
> + spec.t11_t12 = (510 + 100) * 10;
> +
> + DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
> + vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
> +
> + /* Use the max of the register setttings and vbt. If both are
> + * unset, fall back to the spec limits. */
> +#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
> + spec.field : \
> + max(cur.field, vbt.field))
> + assign_final(t1_t3);
> + assign_final(t8);
> + assign_final(t9);
> + assign_final(t10);
> + assign_final(t11_t12);
> +#undef assign_final
> +
> +#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
> + intel_dp->panel_power_up_delay = get_delay(t1_t3);
> + intel_dp->backlight_on_delay = get_delay(t8);
> + intel_dp->backlight_off_delay = get_delay(t9);
> + intel_dp->panel_power_down_delay = get_delay(t10);
> + intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
> +#undef get_delay
> +
> + /* And finally store the new values in the power sequencer. */
> + pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
> + (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> + pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
> + (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> + /* Compute the divisor for the pp clock, simply match the Bspec
> + * formula. */
> + pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
> + << PP_REFERENCE_DIVIDER_SHIFT;
> + pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
> + << PANEL_POWER_CYCLE_DELAY_SHIFT);
> +
> + /* Haswell doesn't have any port selection bits for the panel
> + * power sequence any more. */
> + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> + if (is_cpu_edp(intel_dp))
> + pp_on |= PANEL_POWER_PORT_DP_A;
> + else
> + pp_on |= PANEL_POWER_PORT_DP_D;
> + }
> +
> + I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
> + I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
> + I915_WRITE(PCH_PP_DIVISOR, pp_div);
> +
> +
> + DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
> + intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
> + intel_dp->panel_power_cycle_delay);
> +
> + DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
> + intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
> +
> + DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> + I915_READ(PCH_PP_ON_DELAYS),
> + I915_READ(PCH_PP_OFF_DELAYS),
> + I915_READ(PCH_PP_DIVISOR));
> +}
> +
> void
> intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> {
> @@ -2674,117 +2786,12 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> break;
> }
>
> - /* Cache some DPCD data in the eDP case */
> - if (is_edp(intel_dp)) {
> - struct edp_power_seq cur, vbt, spec, final;
> - u32 pp_on, pp_off, pp_div, pp;
> -
> - /* Workaround: Need to write PP_CONTROL with the unlock key as
> - * the very first thing. */
> - pp = ironlake_get_pp_control(dev_priv);
> - I915_WRITE(PCH_PP_CONTROL, pp);
> -
> - pp_on = I915_READ(PCH_PP_ON_DELAYS);
> - pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> - pp_div = I915_READ(PCH_PP_DIVISOR);
> -
> - /* Pull timing values out of registers */
> - cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
> - PANEL_POWER_UP_DELAY_SHIFT;
> -
> - cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
> - PANEL_LIGHT_ON_DELAY_SHIFT;
> -
> - cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
> - PANEL_LIGHT_OFF_DELAY_SHIFT;
> -
> - cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> - PANEL_POWER_DOWN_DELAY_SHIFT;
> -
> - cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> -
> - DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
> - cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
> -
> - vbt = dev_priv->edp.pps;
> -
> - /* Upper limits from eDP 1.3 spec. Note that we the clunky units
> - * of our hw here, which are all in 100usec. */
> - spec.t1_t3 = 210 * 10;
> - spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
> - spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
> - spec.t10 = 500 * 10;
> - /* This one is special and actually in units of 100ms, but zero
> - * based in the hw (so we need to add 100 ms). But the sw vbt
> - * table multiplies it with 1000 to make it in units of 100usec,
> - * too. */
> - spec.t11_t12 = (510 + 100) * 10;
> -
> - DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
> - vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
> -
> - /* Use the max of the register setttings and vbt. If both are
> - * unset, fall back to the spec limits. */
> -#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
> - spec.field : \
> - max(cur.field, vbt.field))
> - assign_final(t1_t3);
> - assign_final(t8);
> - assign_final(t9);
> - assign_final(t10);
> - assign_final(t11_t12);
> -#undef assign_final
> -
> -#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
> - intel_dp->panel_power_up_delay = get_delay(t1_t3);
> - intel_dp->backlight_on_delay = get_delay(t8);
> - intel_dp->backlight_off_delay = get_delay(t9);
> - intel_dp->panel_power_down_delay = get_delay(t10);
> - intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
> -#undef get_delay
> -
> - /* And finally store the new values in the power sequencer. */
> - pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
> - (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> - pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
> - (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> - /* Compute the divisor for the pp clock, simply match the Bspec
> - * formula. */
> - pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
> - << PP_REFERENCE_DIVIDER_SHIFT;
> - pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
> - << PANEL_POWER_CYCLE_DELAY_SHIFT);
> -
> - /* Haswell doesn't have any port selection bits for the panel
> - * power sequence any more. */
> - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> - if (is_cpu_edp(intel_dp))
> - pp_on |= PANEL_POWER_PORT_DP_A;
> - else
> - pp_on |= PANEL_POWER_PORT_DP_D;
> - }
> -
> - I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
> - I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
> - I915_WRITE(PCH_PP_DIVISOR, pp_div);
> -
> -
> - DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
> - intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
> - intel_dp->panel_power_cycle_delay);
> -
> - DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
> - intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
> -
> - DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> - I915_READ(PCH_PP_ON_DELAYS),
> - I915_READ(PCH_PP_OFF_DELAYS),
> - I915_READ(PCH_PP_DIVISOR));
> - }
> + if (is_edp(intel_dp))
> + intel_dp_init_panel_power_sequencer(dev, intel_dp);
>
> intel_dp_i2c_init(intel_dp, intel_connector, name);
>
> + /* Cache DPCD and EDID for edp. */
> if (is_edp(intel_dp)) {
> bool ret;
> struct edid *edid;
Yay.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/5] drm/i915: make edp panel power sequence setup more robust
2012-10-22 22:04 ` Jesse Barnes
@ 2012-10-23 7:23 ` Daniel Vetter
2012-10-23 14:23 ` Jesse Barnes
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2012-10-23 7:23 UTC (permalink / raw)
To: Jesse Barnes; +Cc: Intel Graphics Development
On Tue, Oct 23, 2012 at 12:04 AM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> If the current field is not zero and doesn't match the VBT, we might
> add a debug statement. It could indicate a BIOS programmed value that
> didn't involve a VBT update (I can imagine some vendors might do
> this). Overwriting the current with the different VBT value may lead
> to breakage or sub-optimal timings.
We dump the current values (read out from the PP regs), the vbt values
and now also the new values we write back into the regs. That not good
enough?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/5] eDP improvements
2012-10-20 18:57 [PATCH 0/5] eDP improvements Daniel Vetter
` (5 preceding siblings ...)
2012-10-21 7:37 ` [PATCH 0/5] eDP improvements Oleksij Rempel
@ 2012-10-23 14:03 ` Paulo Zanoni
6 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2012-10-23 14:03 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
Hi
2012/10/20 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Hi all,
>
> This is useful fallout of my futile attempts at getting the eDP panel on my ivb
> working without the BIOS' help. I now at least get a backlit black screen though
> ;-)
>
> Paulo said that this is good enough for his hsw eDP machine already, and it
> definitely improves the code a bit and (hopefully) makes it a tad more robust.
>
Yes. With this series, the Kernel is able to enable the eDP panel even
when the BIOS does not enable it. A nice improvement!
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
A few details:
- Due to the lack of more context lines, "git am" fails at properly
applying patch 02, so please make sure it compiles after you apply it
(the "int pipe" variable might be added to the wrong function)
- There's a small trivial conflict with patch 05 because dinq changed
since you submitted these.
- My Haswell eDP patches add another conflict, so I'm hoping you will
merge these before the actuall Haswell eDP patches.
> Comments, flames and test results highly welcome.
>
> Cheers, Daniel
>
> Daniel Vetter (5):
> drm/i915: make edp panel power sequence setup more robust
> drm/i915: enable/disable backlight for eDP
> drm/i915/eDP: compute the panel power clock divisor from the pch
> rawclock
> drm/i915/dp: compute the pch dp aux divider from the rawclk
> drm/i915: extract intel_dp_init_panel_power_sequencer
>
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> drivers/gpu/drm/i915/intel_display.c | 10 ++
> drivers/gpu/drm/i915/intel_dp.c | 177 ++++++++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 4 files changed, 138 insertions(+), 56 deletions(-)
>
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/5] drm/i915: make edp panel power sequence setup more robust
2012-10-23 7:23 ` Daniel Vetter
@ 2012-10-23 14:23 ` Jesse Barnes
0 siblings, 0 replies; 17+ messages in thread
From: Jesse Barnes @ 2012-10-23 14:23 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel Graphics Development
On Tue, 23 Oct 2012 09:23:00 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> On Tue, Oct 23, 2012 at 12:04 AM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > If the current field is not zero and doesn't match the VBT, we might
> > add a debug statement. It could indicate a BIOS programmed value that
> > didn't involve a VBT update (I can imagine some vendors might do
> > this). Overwriting the current with the different VBT value may lead
> > to breakage or sub-optimal timings.
>
> We dump the current values (read out from the PP regs), the vbt values
> and now also the new values we write back into the regs. That not good
> enough?
I suppose, it just means more digging if there's a mismatch.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/5] drm/i915: extract intel_dp_init_panel_power_sequencer
2012-10-22 22:08 ` Jesse Barnes
@ 2012-10-23 15:24 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2012-10-23 15:24 UTC (permalink / raw)
To: Jesse Barnes; +Cc: Daniel Vetter, Intel Graphics Development
On Mon, Oct 22, 2012 at 03:08:38PM -0700, Jesse Barnes wrote:
> On Sat, 20 Oct 2012 20:57:45 +0200
> Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
>
> > That thing has grown way too big already.
> >
> > Also move around a comment to the right spot.
> >
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 223 +++++++++++++++++++++-------------------
> > 1 file changed, 115 insertions(+), 108 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 971c4e4..b9b9d08 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2576,6 +2576,118 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
> > intel_attach_broadcast_rgb_property(connector);
> > }
> >
> > +static void
> > +intel_dp_init_panel_power_sequencer(struct drm_device *dev,
> > + struct intel_dp *intel_dp)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > + struct edp_power_seq cur, vbt, spec, final;
> > + u32 pp_on, pp_off, pp_div, pp;
> > +
> > + /* Workaround: Need to write PP_CONTROL with the unlock key as
> > + * the very first thing. */
> > + pp = ironlake_get_pp_control(dev_priv);
> > + I915_WRITE(PCH_PP_CONTROL, pp);
> > +
> > + pp_on = I915_READ(PCH_PP_ON_DELAYS);
> > + pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> > + pp_div = I915_READ(PCH_PP_DIVISOR);
> > +
> > + /* Pull timing values out of registers */
> > + cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
> > + PANEL_POWER_UP_DELAY_SHIFT;
> > +
> > + cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
> > + PANEL_LIGHT_ON_DELAY_SHIFT;
> > +
> > + cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
> > + PANEL_LIGHT_OFF_DELAY_SHIFT;
> > +
> > + cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> > + PANEL_POWER_DOWN_DELAY_SHIFT;
> > +
> > + cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> > + PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> > +
> > + DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
> > + cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
> > +
> > + vbt = dev_priv->edp.pps;
> > +
> > + /* Upper limits from eDP 1.3 spec. Note that we the clunky units
> > + * of our hw here, which are all in 100usec. */
> > + spec.t1_t3 = 210 * 10;
> > + spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
> > + spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
> > + spec.t10 = 500 * 10;
> > + /* This one is special and actually in units of 100ms, but zero
> > + * based in the hw (so we need to add 100 ms). But the sw vbt
> > + * table multiplies it with 1000 to make it in units of 100usec,
> > + * too. */
> > + spec.t11_t12 = (510 + 100) * 10;
> > +
> > + DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
> > + vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
> > +
> > + /* Use the max of the register setttings and vbt. If both are
> > + * unset, fall back to the spec limits. */
> > +#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
> > + spec.field : \
> > + max(cur.field, vbt.field))
> > + assign_final(t1_t3);
> > + assign_final(t8);
> > + assign_final(t9);
> > + assign_final(t10);
> > + assign_final(t11_t12);
> > +#undef assign_final
> > +
> > +#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
> > + intel_dp->panel_power_up_delay = get_delay(t1_t3);
> > + intel_dp->backlight_on_delay = get_delay(t8);
> > + intel_dp->backlight_off_delay = get_delay(t9);
> > + intel_dp->panel_power_down_delay = get_delay(t10);
> > + intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
> > +#undef get_delay
> > +
> > + /* And finally store the new values in the power sequencer. */
> > + pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
> > + (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> > + pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
> > + (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> > + /* Compute the divisor for the pp clock, simply match the Bspec
> > + * formula. */
> > + pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
> > + << PP_REFERENCE_DIVIDER_SHIFT;
> > + pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
> > + << PANEL_POWER_CYCLE_DELAY_SHIFT);
> > +
> > + /* Haswell doesn't have any port selection bits for the panel
> > + * power sequence any more. */
> > + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> > + if (is_cpu_edp(intel_dp))
> > + pp_on |= PANEL_POWER_PORT_DP_A;
> > + else
> > + pp_on |= PANEL_POWER_PORT_DP_D;
> > + }
> > +
> > + I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
> > + I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
> > + I915_WRITE(PCH_PP_DIVISOR, pp_div);
> > +
> > +
> > + DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
> > + intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
> > + intel_dp->panel_power_cycle_delay);
> > +
> > + DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
> > + intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
> > +
> > + DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> > + I915_READ(PCH_PP_ON_DELAYS),
> > + I915_READ(PCH_PP_OFF_DELAYS),
> > + I915_READ(PCH_PP_DIVISOR));
> > +}
> > +
> > void
> > intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> > {
> > @@ -2674,117 +2786,12 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> > break;
> > }
> >
> > - /* Cache some DPCD data in the eDP case */
> > - if (is_edp(intel_dp)) {
> > - struct edp_power_seq cur, vbt, spec, final;
> > - u32 pp_on, pp_off, pp_div, pp;
> > -
> > - /* Workaround: Need to write PP_CONTROL with the unlock key as
> > - * the very first thing. */
> > - pp = ironlake_get_pp_control(dev_priv);
> > - I915_WRITE(PCH_PP_CONTROL, pp);
> > -
> > - pp_on = I915_READ(PCH_PP_ON_DELAYS);
> > - pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> > - pp_div = I915_READ(PCH_PP_DIVISOR);
> > -
> > - /* Pull timing values out of registers */
> > - cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
> > - PANEL_POWER_UP_DELAY_SHIFT;
> > -
> > - cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
> > - PANEL_LIGHT_ON_DELAY_SHIFT;
> > -
> > - cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
> > - PANEL_LIGHT_OFF_DELAY_SHIFT;
> > -
> > - cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> > - PANEL_POWER_DOWN_DELAY_SHIFT;
> > -
> > - cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> > - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> > -
> > - DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
> > - cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
> > -
> > - vbt = dev_priv->edp.pps;
> > -
> > - /* Upper limits from eDP 1.3 spec. Note that we the clunky units
> > - * of our hw here, which are all in 100usec. */
> > - spec.t1_t3 = 210 * 10;
> > - spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
> > - spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
> > - spec.t10 = 500 * 10;
> > - /* This one is special and actually in units of 100ms, but zero
> > - * based in the hw (so we need to add 100 ms). But the sw vbt
> > - * table multiplies it with 1000 to make it in units of 100usec,
> > - * too. */
> > - spec.t11_t12 = (510 + 100) * 10;
> > -
> > - DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
> > - vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
> > -
> > - /* Use the max of the register setttings and vbt. If both are
> > - * unset, fall back to the spec limits. */
> > -#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
> > - spec.field : \
> > - max(cur.field, vbt.field))
> > - assign_final(t1_t3);
> > - assign_final(t8);
> > - assign_final(t9);
> > - assign_final(t10);
> > - assign_final(t11_t12);
> > -#undef assign_final
> > -
> > -#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
> > - intel_dp->panel_power_up_delay = get_delay(t1_t3);
> > - intel_dp->backlight_on_delay = get_delay(t8);
> > - intel_dp->backlight_off_delay = get_delay(t9);
> > - intel_dp->panel_power_down_delay = get_delay(t10);
> > - intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
> > -#undef get_delay
> > -
> > - /* And finally store the new values in the power sequencer. */
> > - pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
> > - (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> > - pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
> > - (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> > - /* Compute the divisor for the pp clock, simply match the Bspec
> > - * formula. */
> > - pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
> > - << PP_REFERENCE_DIVIDER_SHIFT;
> > - pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
> > - << PANEL_POWER_CYCLE_DELAY_SHIFT);
> > -
> > - /* Haswell doesn't have any port selection bits for the panel
> > - * power sequence any more. */
> > - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> > - if (is_cpu_edp(intel_dp))
> > - pp_on |= PANEL_POWER_PORT_DP_A;
> > - else
> > - pp_on |= PANEL_POWER_PORT_DP_D;
> > - }
> > -
> > - I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
> > - I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
> > - I915_WRITE(PCH_PP_DIVISOR, pp_div);
> > -
> > -
> > - DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
> > - intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
> > - intel_dp->panel_power_cycle_delay);
> > -
> > - DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
> > - intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
> > -
> > - DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> > - I915_READ(PCH_PP_ON_DELAYS),
> > - I915_READ(PCH_PP_OFF_DELAYS),
> > - I915_READ(PCH_PP_DIVISOR));
> > - }
> > + if (is_edp(intel_dp))
> > + intel_dp_init_panel_power_sequencer(dev, intel_dp);
> >
> > intel_dp_i2c_init(intel_dp, intel_connector, name);
> >
> > + /* Cache DPCD and EDID for edp. */
> > if (is_edp(intel_dp)) {
> > bool ret;
> > struct edid *edid;
>
> Yay.
>
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Entire series merged, thanks for review and testing.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2012-10-23 15:23 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-10-20 18:57 [PATCH 0/5] eDP improvements Daniel Vetter
2012-10-20 18:57 ` [PATCH 1/5] drm/i915: make edp panel power sequence setup more robust Daniel Vetter
2012-10-22 22:04 ` Jesse Barnes
2012-10-23 7:23 ` Daniel Vetter
2012-10-23 14:23 ` Jesse Barnes
2012-10-20 18:57 ` [PATCH 2/5] drm/i915: enable/disable backlight for eDP Daniel Vetter
2012-10-22 22:04 ` Jesse Barnes
2012-10-20 18:57 ` [PATCH 3/5] drm/i915/eDP: compute the panel power clock divisor from the pch rawclock Daniel Vetter
2012-10-22 22:07 ` Jesse Barnes
2012-10-20 18:57 ` [PATCH 4/5] drm/i915/dp: compute the pch dp aux divider from the rawclk Daniel Vetter
2012-10-22 22:08 ` Jesse Barnes
2012-10-20 18:57 ` [PATCH 5/5] drm/i915: extract intel_dp_init_panel_power_sequencer Daniel Vetter
2012-10-22 22:08 ` Jesse Barnes
2012-10-23 15:24 ` Daniel Vetter
2012-10-21 7:37 ` [PATCH 0/5] eDP improvements Oleksij Rempel
2012-10-21 10:34 ` Daniel Vetter
2012-10-23 14:03 ` Paulo Zanoni
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