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From: Andrew Lunn <andrew@lunn.ch>
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Lior Amsalem <alior@marvell.com>, Andrew Lunn <andrew@lunn.ch>,
	Ike Pan <ike.pan@canonical.com>,
	Will Deacon <will.deacon@arm.com>,
	Nadav Haklai <nadavh@marvell.com>,
	Ian Molton <ian.molton@codethink.co.uk>,
	David Marlin <dmarlin@redhat.com>,
	Yehuda Yitschak <yehuday@marvell.com>,
	Jani Monoses <jani.monoses@canonical.com>,
	Russell King <linux@arm.linux.org.uk>,
	Tawfik Bayouk <tawfik@marvell.com>,
	Dan Frazier <dann.frazier@canonical.com>,
	Eran Ben-Avi <benavi@marvell.com>, Li Li <li.li@canonical.com>,
	Leif Lindholm <leif.lindholm@arm.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Arnd Bergmann <arnd@arndb.de>, Jon Masters <jcm@redhat.com>,
	devicetree-discuss@lists.ozlabs.org,
	Rob Herring <rob.herring@calxeda.com>,
	Ben Dooks <ben-linux@fluff.org>,
	Gregory CLEMENT <gregory.clement@free-electrons.com>,
	Mike Turquette <mtur>
Subject: Re: [PATCH 3/5] arm: mvebu: Added IPI support via doorbells
Date: Tue, 23 Oct 2012 07:44:55 +0200	[thread overview]
Message-ID: <20121023054455.GP21046@lunn.ch> (raw)
In-Reply-To: <20121023071419.222c46d3@skate>

On Tue, Oct 23, 2012 at 07:14:19AM +0200, Thomas Petazzoni wrote:
> 
> On Mon, 22 Oct 2012 23:11:02 +0200, Gregory CLEMENT wrote:
> 
> > The correct explanation is that the offset +21070 is a CPU virtual offset.
> > That means that depending of the CPU core which will access to this register,
> > the controller will internally change the offset automagically to point the
> > correct offset.
> > 
> > I should have added an explanation in the commit log. I will do it for V2.
> 
> Just to expand on Gr??gory's comment: there is per-CPU banking for the
> interrupt controller registers. At 0x21070, you have "virtual"
> registers that automatically map to the interrupt controller registers
> of the current CPU. At 0x21870, you have the interrupt controllers
> registers of CPU0, regardless of which CPU you are running on.
> 
> Before this patch set, there was no SMP support for Armada 370/XP, so
> accessing the interrupt controller registers at 0x21870 was OK
> (accessing them from 0x21070 would have been OK as well). With the
> introduction of SMP support, accessing them from 0x21870 no longer
> works, so we switch to the virtual registers at 0x21070.
> 
> In other words: no it is not a bug fix and it therefore doesn't need to
> go into 3.7.

Hi Thomas

Thanks for the clear reply. Does the binding documentation make this
clear? Should it be extended to indicate which address range should be
used?

  Thanks
	Andrew

WARNING: multiple messages have this Message-ID (diff)
From: andrew@lunn.ch (Andrew Lunn)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/5] arm: mvebu: Added IPI support via doorbells
Date: Tue, 23 Oct 2012 07:44:55 +0200	[thread overview]
Message-ID: <20121023054455.GP21046@lunn.ch> (raw)
In-Reply-To: <20121023071419.222c46d3@skate>

On Tue, Oct 23, 2012 at 07:14:19AM +0200, Thomas Petazzoni wrote:
> 
> On Mon, 22 Oct 2012 23:11:02 +0200, Gregory CLEMENT wrote:
> 
> > The correct explanation is that the offset +21070 is a CPU virtual offset.
> > That means that depending of the CPU core which will access to this register,
> > the controller will internally change the offset automagically to point the
> > correct offset.
> > 
> > I should have added an explanation in the commit log. I will do it for V2.
> 
> Just to expand on Gr??gory's comment: there is per-CPU banking for the
> interrupt controller registers. At 0x21070, you have "virtual"
> registers that automatically map to the interrupt controller registers
> of the current CPU. At 0x21870, you have the interrupt controllers
> registers of CPU0, regardless of which CPU you are running on.
> 
> Before this patch set, there was no SMP support for Armada 370/XP, so
> accessing the interrupt controller registers at 0x21870 was OK
> (accessing them from 0x21070 would have been OK as well). With the
> introduction of SMP support, accessing them from 0x21870 no longer
> works, so we switch to the virtual registers at 0x21070.
> 
> In other words: no it is not a bug fix and it therefore doesn't need to
> go into 3.7.

Hi Thomas

Thanks for the clear reply. Does the binding documentation make this
clear? Should it be extended to indicate which address range should be
used?

  Thanks
	Andrew

  reply	other threads:[~2012-10-23  5:44 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-22 17:02 [PATCH 0/5] SMP support for Armada XP Gregory CLEMENT
2012-10-22 17:02 ` Gregory CLEMENT
2012-10-22 17:02 ` [PATCH 1/5] arm: mvebu: Added support for coherency fabric in mach-mvebu Gregory CLEMENT
2012-10-22 17:02   ` Gregory CLEMENT
2012-10-22 17:02 ` [PATCH 2/5] arm: mvebu: Added initial support for power managmement service unit Gregory CLEMENT
2012-10-22 17:02   ` Gregory CLEMENT
2012-10-22 17:02 ` [PATCH 3/5] arm: mvebu: Added IPI support via doorbells Gregory CLEMENT
2012-10-22 17:02   ` Gregory CLEMENT
2012-10-22 17:30   ` Andrew Lunn
2012-10-22 17:30     ` Andrew Lunn
2012-10-22 19:07     ` Gregory CLEMENT
2012-10-22 19:07       ` Gregory CLEMENT
2012-10-22 20:07       ` Andrew Lunn
2012-10-22 20:07         ` Andrew Lunn
2012-10-22 21:11         ` Gregory CLEMENT
2012-10-22 21:11           ` Gregory CLEMENT
2012-10-23  5:14           ` Thomas Petazzoni
2012-10-23  5:14             ` Thomas Petazzoni
2012-10-23  5:44             ` Andrew Lunn [this message]
2012-10-23  5:44               ` Andrew Lunn
2012-10-23  5:50               ` Thomas Petazzoni
2012-10-23  5:50                 ` Thomas Petazzoni
2012-10-22 17:02 ` [PATCH 4/5] arm: mm: Added support for PJ4B cpu and init routines Gregory CLEMENT
2012-10-22 17:02   ` Gregory CLEMENT
2012-10-22 17:02 ` [PATCH 5/5] arm: mvebu: Added SMP support for Armada XP Gregory CLEMENT
2012-10-22 17:02   ` Gregory CLEMENT
2012-10-22 18:45   ` Andrew Lunn
2012-10-22 18:45     ` Andrew Lunn
2012-10-23  9:11     ` Gregory CLEMENT
2012-10-23  9:11       ` Gregory CLEMENT
2012-10-23  9:30       ` Andrew Lunn
2012-10-23  9:30         ` Andrew Lunn
2012-10-23 10:43         ` Gregory CLEMENT
2012-10-23 10:43           ` Gregory CLEMENT

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