* [U-Boot] [PATCH] Origen: Add default clock settings for multimedia IPs
@ 2012-08-31 6:33 Tushar Behera
2012-09-04 5:47 ` Chander Kashyap
2012-10-26 21:30 ` Albert ARIBAUD
0 siblings, 2 replies; 3+ messages in thread
From: Tushar Behera @ 2012-08-31 6:33 UTC (permalink / raw)
To: u-boot
From: Annamalai Lakshmanan <annamalai.lakshmanan@linaro.org>
Added clock settings for MFC, FIMC, FB and G3D. They are clocked to
maximum respective frequencies as per datasheet.
Signed-off-by: Annamalai Lakshmanan <annamalai.lakshmanan@linaro.org>
Signed-off-by: Giridhar Maruthy <giridhar.maruthy@linaro.org>
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
---
board/samsung/origen/lowlevel_init.S | 37 ++++++++++++++++-
board/samsung/origen/origen_setup.h | 74 ++++++++++++++++++++++++++++++++++
2 files changed, 110 insertions(+), 1 deletions(-)
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index 9283201..9daa0da 100644
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -158,7 +158,22 @@ system_clock_init:
ldr r2, =CLK_SRC_PERIL0_OFFSET
str r1, [r0, r2]
- /* FIMD0 */
+ /* CAM , FIMC 0-3 */
+ ldr r1, =CLK_SRC_CAM_VAL
+ ldr r2, =CLK_SRC_CAM_OFFSET
+ str r1, [r0, r2]
+
+ /* MFC */
+ ldr r1, =CLK_SRC_MFC_VAL
+ ldr r2, =CLK_SRC_MFC_OFFSET
+ str r1, [r0, r2]
+
+ /* G3D */
+ ldr r1, =CLK_SRC_G3D_VAL
+ ldr r2, =CLK_SRC_G3D_OFFSET
+ str r1, [r0, r2]
+
+ /* LCD0 */
ldr r1, =CLK_SRC_LCD0_VAL
ldr r2, =CLK_SRC_LCD0_OFFSET
str r1, [r0, r2]
@@ -223,6 +238,26 @@ system_clock_init:
ldr r2, =CLK_DIV_PERIL0_OFFSET
str r1, [r0, r2]
+ /* CAM, FIMC 0-3: CAM Clock Divisors */
+ ldr r1, =CLK_DIV_CAM_VAL
+ ldr r2, =CLK_DIV_CAM_OFFSET
+ str r1, [r0, r2]
+
+ /* CLK_DIV_MFC: MFC Clock Divisors */
+ ldr r1, =CLK_DIV_MFC_VAL
+ ldr r2, =CLK_DIV_MFC_OFFSET
+ str r1, [r0, r2]
+
+ /* CLK_DIV_G3D: G3D Clock Divisors */
+ ldr r1, =CLK_DIV_G3D_VAL
+ ldr r2, =CLK_DIV_G3D_OFFSET
+ str r1, [r0, r2]
+
+ /* CLK_DIV_LCD0: LCD0 Clock Divisors */
+ ldr r1, =CLK_DIV_LCD0_VAL
+ ldr r2, =CLK_DIV_LCD0_OFFSET
+ str r1, [r0, r2]
+
/* Set PLL locktime */
ldr r1, =PLL_LOCKTIME
ldr r2, =APLL_LOCK_OFFSET
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index 94cccca..930b948 100644
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -53,7 +53,18 @@
#define CLK_DIV_FSYS2_OFFSET 0xC548
#define CLK_DIV_FSYS3_OFFSET 0xC54C
+#define CLK_SRC_CAM_OFFSET 0xC220
+#define CLK_SRC_TV_OFFSET 0xC224
+#define CLK_SRC_MFC_OFFSET 0xC228
+#define CLK_SRC_G3D_OFFSET 0xC22C
+#define CLK_SRC_LCD0_OFFSET 0xC234
#define CLK_SRC_PERIL0_OFFSET 0xC250
+
+#define CLK_DIV_CAM_OFFSET 0xC520
+#define CLK_DIV_TV_OFFSET 0xC524
+#define CLK_DIV_MFC_OFFSET 0xC528
+#define CLK_DIV_G3D_OFFSET 0xC52C
+#define CLK_DIV_LCD0_OFFSET 0xC534
#define CLK_DIV_PERIL0_OFFSET 0xC550
#define CLK_SRC_LCD0_OFFSET 0xC234
@@ -353,6 +364,65 @@
| (UART1_RATIO << 4) \
| (UART0_RATIO << 0))
+/* Clock Source CAM/FIMC */
+/* CLK_SRC_CAM */
+#define CAM0_SEL_XUSBXTI 1
+#define CAM1_SEL_XUSBXTI 1
+#define CSIS0_SEL_XUSBXTI 1
+#define CSIS1_SEL_XUSBXTI 1
+
+#define FIMC_SEL_SCLKMPLL 6
+#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
+#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
+#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
+#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
+
+#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
+ | (CSIS0_SEL_XUSBXTI << 24) \
+ | (CAM1_SEL_XUSBXTI << 20) \
+ | (CAM0_SEL_XUSBXTI << 16) \
+ | (FIMC3_LCLK_SEL << 12) \
+ | (FIMC2_LCLK_SEL << 8) \
+ | (FIMC1_LCLK_SEL << 4) \
+ | (FIMC0_LCLK_SEL << 0))
+
+/* SCLK CAM */
+/* CLK_DIV_CAM */
+#define FIMC0_LCLK_RATIO 4
+#define FIMC1_LCLK_RATIO 4
+#define FIMC2_LCLK_RATIO 4
+#define FIMC3_LCLK_RATIO 4
+#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
+ | (FIMC2_LCLK_RATIO << 8) \
+ | (FIMC1_LCLK_RATIO << 4) \
+ | (FIMC0_LCLK_RATIO << 0))
+
+/* SCLK MFC */
+/* CLK_SRC_MFC */
+#define MFC_SEL_MPLL 0
+#define MOUTMFC_0 0
+#define MFC_SEL MOUTMFC_0
+#define MFC_0_SEL MFC_SEL_MPLL
+#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
+
+
+/* CLK_DIV_MFC */
+#define MFC_RATIO 3
+#define CLK_DIV_MFC_VAL (MFC_RATIO)
+
+/* SCLK G3D */
+/* CLK_SRC_G3D */
+#define G3D_SEL_MPLL 0
+#define MOUTG3D_0 0
+#define G3D_SEL MOUTG3D_0
+#define G3D_0_SEL G3D_SEL_MPLL
+#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
+
+/* CLK_DIV_G3D */
+#define G3D_RATIO 1
+#define CLK_DIV_G3D_VAL (G3D_RATIO)
+
+/* SCLK LCD0 */
/* CLK_SRC_LCD0 */
#define FIMD_SEL_SCLKMPLL 6
#define MDNIE0_SEL_XUSBXTI 1
@@ -363,6 +433,10 @@
| (MDNIE0_SEL_XUSBXTI << 4) \
| (FIMD_SEL_SCLKMPLL << 0))
+/* CLK_DIV_LCD0 */
+#define FIMD0_RATIO 4
+#define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
+
/* Required period to generate a stable clock output */
/* PLL_LOCK_TIME */
#define PLL_LOCKTIME 0x1C20
--
1.7.4.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] Origen: Add default clock settings for multimedia IPs
2012-08-31 6:33 [U-Boot] [PATCH] Origen: Add default clock settings for multimedia IPs Tushar Behera
@ 2012-09-04 5:47 ` Chander Kashyap
2012-10-26 21:30 ` Albert ARIBAUD
1 sibling, 0 replies; 3+ messages in thread
From: Chander Kashyap @ 2012-09-04 5:47 UTC (permalink / raw)
To: u-boot
Hi,
On 31 August 2012 12:03, Tushar Behera <tushar.behera@linaro.org> wrote:
> From: Annamalai Lakshmanan <annamalai.lakshmanan@linaro.org>
>
> Added clock settings for MFC, FIMC, FB and G3D. They are clocked to
> maximum respective frequencies as per datasheet.
>
> Signed-off-by: Annamalai Lakshmanan <annamalai.lakshmanan@linaro.org>
> Signed-off-by: Giridhar Maruthy <giridhar.maruthy@linaro.org>
> Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
> Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
> ---
--
Acked-By: Chander Kashyap <chander.kashyap@linaro.org>
with warm regards,
Chander Kashyap
^ permalink raw reply [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] Origen: Add default clock settings for multimedia IPs
2012-08-31 6:33 [U-Boot] [PATCH] Origen: Add default clock settings for multimedia IPs Tushar Behera
2012-09-04 5:47 ` Chander Kashyap
@ 2012-10-26 21:30 ` Albert ARIBAUD
1 sibling, 0 replies; 3+ messages in thread
From: Albert ARIBAUD @ 2012-10-26 21:30 UTC (permalink / raw)
To: u-boot
Hi Tushar,
On Fri, 31 Aug 2012 12:03:58 +0530, Tushar Behera
<tushar.behera@linaro.org> wrote:
> From: Annamalai Lakshmanan <annamalai.lakshmanan@linaro.org>
>
> Added clock settings for MFC, FIMC, FB and G3D. They are clocked to
> maximum respective frequencies as per datasheet.
>
> Signed-off-by: Annamalai Lakshmanan <annamalai.lakshmanan@linaro.org>
> Signed-off-by: Giridhar Maruthy <giridhar.maruthy@linaro.org>
> Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
> Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
> ---
> board/samsung/origen/lowlevel_init.S | 37 ++++++++++++++++-
> board/samsung/origen/origen_setup.h | 74 ++++++++++++++++++++++++++++++++++
> 2 files changed, 110 insertions(+), 1 deletions(-)
>
> diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
> index 9283201..9daa0da 100644
> --- a/board/samsung/origen/lowlevel_init.S
> +++ b/board/samsung/origen/lowlevel_init.S
> @@ -158,7 +158,22 @@ system_clock_init:
> ldr r2, =CLK_SRC_PERIL0_OFFSET
> str r1, [r0, r2]
>
> - /* FIMD0 */
> + /* CAM , FIMC 0-3 */
> + ldr r1, =CLK_SRC_CAM_VAL
> + ldr r2, =CLK_SRC_CAM_OFFSET
> + str r1, [r0, r2]
> +
> + /* MFC */
> + ldr r1, =CLK_SRC_MFC_VAL
> + ldr r2, =CLK_SRC_MFC_OFFSET
> + str r1, [r0, r2]
> +
> + /* G3D */
> + ldr r1, =CLK_SRC_G3D_VAL
> + ldr r2, =CLK_SRC_G3D_OFFSET
> + str r1, [r0, r2]
> +
> + /* LCD0 */
> ldr r1, =CLK_SRC_LCD0_VAL
> ldr r2, =CLK_SRC_LCD0_OFFSET
> str r1, [r0, r2]
> @@ -223,6 +238,26 @@ system_clock_init:
> ldr r2, =CLK_DIV_PERIL0_OFFSET
> str r1, [r0, r2]
>
> + /* CAM, FIMC 0-3: CAM Clock Divisors */
> + ldr r1, =CLK_DIV_CAM_VAL
> + ldr r2, =CLK_DIV_CAM_OFFSET
> + str r1, [r0, r2]
> +
> + /* CLK_DIV_MFC: MFC Clock Divisors */
> + ldr r1, =CLK_DIV_MFC_VAL
> + ldr r2, =CLK_DIV_MFC_OFFSET
> + str r1, [r0, r2]
> +
> + /* CLK_DIV_G3D: G3D Clock Divisors */
> + ldr r1, =CLK_DIV_G3D_VAL
> + ldr r2, =CLK_DIV_G3D_OFFSET
> + str r1, [r0, r2]
> +
> + /* CLK_DIV_LCD0: LCD0 Clock Divisors */
> + ldr r1, =CLK_DIV_LCD0_VAL
> + ldr r2, =CLK_DIV_LCD0_OFFSET
> + str r1, [r0, r2]
> +
> /* Set PLL locktime */
> ldr r1, =PLL_LOCKTIME
> ldr r2, =APLL_LOCK_OFFSET
> diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
> index 94cccca..930b948 100644
> --- a/board/samsung/origen/origen_setup.h
> +++ b/board/samsung/origen/origen_setup.h
> @@ -53,7 +53,18 @@
> #define CLK_DIV_FSYS2_OFFSET 0xC548
> #define CLK_DIV_FSYS3_OFFSET 0xC54C
>
> +#define CLK_SRC_CAM_OFFSET 0xC220
> +#define CLK_SRC_TV_OFFSET 0xC224
> +#define CLK_SRC_MFC_OFFSET 0xC228
> +#define CLK_SRC_G3D_OFFSET 0xC22C
> +#define CLK_SRC_LCD0_OFFSET 0xC234
> #define CLK_SRC_PERIL0_OFFSET 0xC250
> +
> +#define CLK_DIV_CAM_OFFSET 0xC520
> +#define CLK_DIV_TV_OFFSET 0xC524
> +#define CLK_DIV_MFC_OFFSET 0xC528
> +#define CLK_DIV_G3D_OFFSET 0xC52C
> +#define CLK_DIV_LCD0_OFFSET 0xC534
> #define CLK_DIV_PERIL0_OFFSET 0xC550
>
> #define CLK_SRC_LCD0_OFFSET 0xC234
> @@ -353,6 +364,65 @@
> | (UART1_RATIO << 4) \
> | (UART0_RATIO << 0))
>
> +/* Clock Source CAM/FIMC */
> +/* CLK_SRC_CAM */
> +#define CAM0_SEL_XUSBXTI 1
> +#define CAM1_SEL_XUSBXTI 1
> +#define CSIS0_SEL_XUSBXTI 1
> +#define CSIS1_SEL_XUSBXTI 1
> +
> +#define FIMC_SEL_SCLKMPLL 6
> +#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
> +#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
> +#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
> +#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
> +
> +#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
> + | (CSIS0_SEL_XUSBXTI << 24) \
> + | (CAM1_SEL_XUSBXTI << 20) \
> + | (CAM0_SEL_XUSBXTI << 16) \
> + | (FIMC3_LCLK_SEL << 12) \
> + | (FIMC2_LCLK_SEL << 8) \
> + | (FIMC1_LCLK_SEL << 4) \
> + | (FIMC0_LCLK_SEL << 0))
> +
> +/* SCLK CAM */
> +/* CLK_DIV_CAM */
> +#define FIMC0_LCLK_RATIO 4
> +#define FIMC1_LCLK_RATIO 4
> +#define FIMC2_LCLK_RATIO 4
> +#define FIMC3_LCLK_RATIO 4
> +#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
> + | (FIMC2_LCLK_RATIO << 8) \
> + | (FIMC1_LCLK_RATIO << 4) \
> + | (FIMC0_LCLK_RATIO << 0))
> +
> +/* SCLK MFC */
> +/* CLK_SRC_MFC */
> +#define MFC_SEL_MPLL 0
> +#define MOUTMFC_0 0
> +#define MFC_SEL MOUTMFC_0
> +#define MFC_0_SEL MFC_SEL_MPLL
> +#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
> +
> +
> +/* CLK_DIV_MFC */
> +#define MFC_RATIO 3
> +#define CLK_DIV_MFC_VAL (MFC_RATIO)
> +
> +/* SCLK G3D */
> +/* CLK_SRC_G3D */
> +#define G3D_SEL_MPLL 0
> +#define MOUTG3D_0 0
> +#define G3D_SEL MOUTG3D_0
> +#define G3D_0_SEL G3D_SEL_MPLL
> +#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
> +
> +/* CLK_DIV_G3D */
> +#define G3D_RATIO 1
> +#define CLK_DIV_G3D_VAL (G3D_RATIO)
> +
> +/* SCLK LCD0 */
> /* CLK_SRC_LCD0 */
> #define FIMD_SEL_SCLKMPLL 6
> #define MDNIE0_SEL_XUSBXTI 1
> @@ -363,6 +433,10 @@
> | (MDNIE0_SEL_XUSBXTI << 4) \
> | (FIMD_SEL_SCLKMPLL << 0))
>
> +/* CLK_DIV_LCD0 */
> +#define FIMD0_RATIO 4
> +#define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
> +
> /* Required period to generate a stable clock output */
> /* PLL_LOCK_TIME */
> #define PLL_LOCKTIME 0x1C20
Applied to u-boot-arm/master, thanks!
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 3+ messages in thread
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Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2012-08-31 6:33 [U-Boot] [PATCH] Origen: Add default clock settings for multimedia IPs Tushar Behera
2012-09-04 5:47 ` Chander Kashyap
2012-10-26 21:30 ` Albert ARIBAUD
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