* [PATCH 1/4] x86: Add cpu_has_topoext
2012-10-19 8:55 [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions Andreas Herrmann
@ 2012-10-19 8:58 ` Andreas Herrmann
2012-11-13 21:58 ` [tip:x86/cpu] " tip-bot for Andreas Herrmann
2012-10-19 8:59 ` [PATCH 2/4] x86, cacheinfo: Determine number of cache leafs using CPUID 0x8000001d on AMD Andreas Herrmann
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Andreas Herrmann @ 2012-10-19 8:58 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin, Thomas Gleixner; +Cc: x86, linux-kernel
Introduce cpu_has_topoext to check for AMD's CPUID topology extensions
support. It indicates support for
CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX
See AMD's CPUID Specification, Publication # 25481
(as of Rev. 2.34 September 2010)
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
arch/x86/include/asm/cpufeature.h | 1 +
arch/x86/kernel/cpu/amd.c | 2 +-
arch/x86/kernel/smpboot.c | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 16cae42..c13a1f4 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -309,6 +309,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
+#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
# define cpu_has_invlpg 1
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f7e98a2..64e9ad4 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -304,7 +304,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
int cpu = smp_processor_id();
/* get information required for multi-node processors */
- if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
+ if (cpu_has_topoext) {
u32 eax, ebx, ecx, edx;
cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index c80a33b..732bf5c 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -313,7 +313,7 @@ do { \
static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
{
- if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
+ if (cpu_has_topoext) {
int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
if (c->phys_proc_id == o->phys_proc_id &&
--
1.7.8.6
^ permalink raw reply related [flat|nested] 12+ messages in thread* [tip:x86/cpu] x86: Add cpu_has_topoext
2012-10-19 8:58 ` [PATCH 1/4] x86: Add cpu_has_topoext Andreas Herrmann
@ 2012-11-13 21:58 ` tip-bot for Andreas Herrmann
0 siblings, 0 replies; 12+ messages in thread
From: tip-bot for Andreas Herrmann @ 2012-11-13 21:58 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, hpa, mingo, andreas.herrmann3, tglx, hpa
Commit-ID: 193f3fcb3ab769bab4a2b9fa181eef3e5699a352
Gitweb: http://git.kernel.org/tip/193f3fcb3ab769bab4a2b9fa181eef3e5699a352
Author: Andreas Herrmann <andreas.herrmann3@amd.com>
AuthorDate: Fri, 19 Oct 2012 10:58:13 +0200
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Tue, 13 Nov 2012 11:22:28 -0800
x86: Add cpu_has_topoext
Introduce cpu_has_topoext to check for AMD's CPUID topology extensions
support. It indicates support for
CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX
See AMD's CPUID Specification, Publication # 25481
(as of Rev. 2.34 September 2010)
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Link: http://lkml.kernel.org/r/20121019085813.GD26718@alberich
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
arch/x86/include/asm/cpufeature.h | 1 +
arch/x86/kernel/cpu/amd.c | 2 +-
arch/x86/kernel/smpboot.c | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 8c297aa..c22a492 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -311,6 +311,7 @@ extern const char * const x86_power_flags[32];
#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
+#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
# define cpu_has_invlpg 1
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f7e98a2..64e9ad4 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -304,7 +304,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
int cpu = smp_processor_id();
/* get information required for multi-node processors */
- if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
+ if (cpu_has_topoext) {
u32 eax, ebx, ecx, edx;
cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index c80a33b..732bf5c 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -313,7 +313,7 @@ do { \
static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
{
- if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
+ if (cpu_has_topoext) {
int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
if (c->phys_proc_id == o->phys_proc_id &&
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/4] x86, cacheinfo: Determine number of cache leafs using CPUID 0x8000001d on AMD
2012-10-19 8:55 [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions Andreas Herrmann
2012-10-19 8:58 ` [PATCH 1/4] x86: Add cpu_has_topoext Andreas Herrmann
@ 2012-10-19 8:59 ` Andreas Herrmann
2012-11-13 21:59 ` [tip:x86/cpu] " tip-bot for Andreas Herrmann
2012-10-19 9:00 ` [PATCH 3/4] x86, cacheinfo: Make use of CPUID 0x8000001d for cache information " Andreas Herrmann
` (2 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Andreas Herrmann @ 2012-10-19 8:59 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin, Thomas Gleixner; +Cc: x86, linux-kernel
CPUID 0x8000001d works quite similar to Intels' CPUID function 4.
Use it to determine number of cache leafs.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
arch/x86/include/asm/processor.h | 2 +-
arch/x86/kernel/cpu/amd.c | 7 +------
arch/x86/kernel/cpu/intel_cacheinfo.c | 28 +++++++++++++++++++++++-----
3 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index b98c0d9..4bfa500 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -187,7 +187,7 @@ extern void print_cpu_info(struct cpuinfo_x86 *);
void print_cpu_msr(struct cpuinfo_x86 *);
extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
-extern unsigned short num_cache_leaves;
+extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
extern void detect_extended_topology(struct cpuinfo_x86 *c);
extern void detect_ht(struct cpuinfo_x86 *c);
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 64e9ad4..a8538e6 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -643,12 +643,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
detect_ht(c);
#endif
- if (c->extended_cpuid_level >= 0x80000006) {
- if (cpuid_edx(0x80000006) & 0xf000)
- num_cache_leaves = 4;
- else
- num_cache_leaves = 3;
- }
+ init_amd_cacheinfo(c);
if (c->x86 >= 0xf)
set_cpu_cap(c, X86_FEATURE_K8);
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 93c5451..8ce7a83 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -557,21 +557,39 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
return 0;
}
-static int __cpuinit find_num_cache_leaves(void)
+static int __cpuinit find_num_cache_leaves(struct cpuinfo_x86 *c)
{
- unsigned int eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx, op;
union _cpuid4_leaf_eax cache_eax;
int i = -1;
+ if (c->x86_vendor == X86_VENDOR_AMD)
+ op = 0x8000001d;
+ else
+ op = 4;
+
do {
++i;
- /* Do cpuid(4) loop to find out num_cache_leaves */
- cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
+ /* Do cpuid(op) loop to find out num_cache_leaves */
+ cpuid_count(op, i, &eax, &ebx, &ecx, &edx);
cache_eax.full = eax;
} while (cache_eax.split.type != CACHE_TYPE_NULL);
return i;
}
+void __cpuinit init_amd_cacheinfo(struct cpuinfo_x86 *c)
+{
+
+ if (cpu_has_topoext) {
+ num_cache_leaves = find_num_cache_leaves(c);
+ } else if (c->extended_cpuid_level >= 0x80000006) {
+ if (cpuid_edx(0x80000006) & 0xf000)
+ num_cache_leaves = 4;
+ else
+ num_cache_leaves = 3;
+ }
+}
+
unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
{
/* Cache sizes */
@@ -588,7 +606,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
if (is_initialized == 0) {
/* Init num_cache_leaves from boot CPU */
- num_cache_leaves = find_num_cache_leaves();
+ num_cache_leaves = find_num_cache_leaves(c);
is_initialized++;
}
--
1.7.8.6
^ permalink raw reply related [flat|nested] 12+ messages in thread* [tip:x86/cpu] x86, cacheinfo: Determine number of cache leafs using CPUID 0x8000001d on AMD
2012-10-19 8:59 ` [PATCH 2/4] x86, cacheinfo: Determine number of cache leafs using CPUID 0x8000001d on AMD Andreas Herrmann
@ 2012-11-13 21:59 ` tip-bot for Andreas Herrmann
0 siblings, 0 replies; 12+ messages in thread
From: tip-bot for Andreas Herrmann @ 2012-11-13 21:59 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, hpa, mingo, andreas.herrmann3, tglx, hpa
Commit-ID: 04a1541828ea223169eb44a336bfad8ec0dfb46a
Gitweb: http://git.kernel.org/tip/04a1541828ea223169eb44a336bfad8ec0dfb46a
Author: Andreas Herrmann <andreas.herrmann3@amd.com>
AuthorDate: Fri, 19 Oct 2012 10:59:33 +0200
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Tue, 13 Nov 2012 11:22:29 -0800
x86, cacheinfo: Determine number of cache leafs using CPUID 0x8000001d on AMD
CPUID 0x8000001d works quite similar to Intels' CPUID function 4.
Use it to determine number of cache leafs.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Link: http://lkml.kernel.org/r/20121019085933.GE26718@alberich
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
arch/x86/include/asm/processor.h | 2 +-
arch/x86/kernel/cpu/amd.c | 7 +------
arch/x86/kernel/cpu/intel_cacheinfo.c | 28 +++++++++++++++++++++++-----
3 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index ad1fc85..db0d8c3 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -187,7 +187,7 @@ extern void print_cpu_info(struct cpuinfo_x86 *);
void print_cpu_msr(struct cpuinfo_x86 *);
extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
-extern unsigned short num_cache_leaves;
+extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
extern void detect_extended_topology(struct cpuinfo_x86 *c);
extern void detect_ht(struct cpuinfo_x86 *c);
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 64e9ad4..a8538e6 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -643,12 +643,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
detect_ht(c);
#endif
- if (c->extended_cpuid_level >= 0x80000006) {
- if (cpuid_edx(0x80000006) & 0xf000)
- num_cache_leaves = 4;
- else
- num_cache_leaves = 3;
- }
+ init_amd_cacheinfo(c);
if (c->x86 >= 0xf)
set_cpu_cap(c, X86_FEATURE_K8);
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 93c5451..8ce7a83 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -557,21 +557,39 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
return 0;
}
-static int __cpuinit find_num_cache_leaves(void)
+static int __cpuinit find_num_cache_leaves(struct cpuinfo_x86 *c)
{
- unsigned int eax, ebx, ecx, edx;
+ unsigned int eax, ebx, ecx, edx, op;
union _cpuid4_leaf_eax cache_eax;
int i = -1;
+ if (c->x86_vendor == X86_VENDOR_AMD)
+ op = 0x8000001d;
+ else
+ op = 4;
+
do {
++i;
- /* Do cpuid(4) loop to find out num_cache_leaves */
- cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
+ /* Do cpuid(op) loop to find out num_cache_leaves */
+ cpuid_count(op, i, &eax, &ebx, &ecx, &edx);
cache_eax.full = eax;
} while (cache_eax.split.type != CACHE_TYPE_NULL);
return i;
}
+void __cpuinit init_amd_cacheinfo(struct cpuinfo_x86 *c)
+{
+
+ if (cpu_has_topoext) {
+ num_cache_leaves = find_num_cache_leaves(c);
+ } else if (c->extended_cpuid_level >= 0x80000006) {
+ if (cpuid_edx(0x80000006) & 0xf000)
+ num_cache_leaves = 4;
+ else
+ num_cache_leaves = 3;
+ }
+}
+
unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
{
/* Cache sizes */
@@ -588,7 +606,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
if (is_initialized == 0) {
/* Init num_cache_leaves from boot CPU */
- num_cache_leaves = find_num_cache_leaves();
+ num_cache_leaves = find_num_cache_leaves(c);
is_initialized++;
}
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/4] x86, cacheinfo: Make use of CPUID 0x8000001d for cache information on AMD
2012-10-19 8:55 [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions Andreas Herrmann
2012-10-19 8:58 ` [PATCH 1/4] x86: Add cpu_has_topoext Andreas Herrmann
2012-10-19 8:59 ` [PATCH 2/4] x86, cacheinfo: Determine number of cache leafs using CPUID 0x8000001d on AMD Andreas Herrmann
@ 2012-10-19 9:00 ` Andreas Herrmann
2012-11-13 22:00 ` [tip:x86/cpu] " tip-bot for Andreas Herrmann
2012-10-19 9:02 ` [PATCH 4/4] x86, cacheinfo: Base cache sharing info on CPUID 0x8000001d " Andreas Herrmann
2012-11-06 20:47 ` [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions Jacob Shin
4 siblings, 1 reply; 12+ messages in thread
From: Andreas Herrmann @ 2012-10-19 9:00 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin, Thomas Gleixner; +Cc: x86, linux-kernel
Rely on CPUID 0x8000001d for cache information when AMD CPUID topology
extensions are available.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 8ce7a83..cd2e1cc 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -538,7 +538,11 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
unsigned edx;
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
- amd_cpuid4(index, &eax, &ebx, &ecx);
+ if (cpu_has_topoext)
+ cpuid_count(0x8000001d, index, &eax.full,
+ &ebx.full, &ecx.full, &edx);
+ else
+ amd_cpuid4(index, &eax, &ebx, &ecx);
amd_init_l3_cache(this_leaf, index);
} else {
cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
--
1.7.8.6
^ permalink raw reply related [flat|nested] 12+ messages in thread* [tip:x86/cpu] x86, cacheinfo: Make use of CPUID 0x8000001d for cache information on AMD
2012-10-19 9:00 ` [PATCH 3/4] x86, cacheinfo: Make use of CPUID 0x8000001d for cache information " Andreas Herrmann
@ 2012-11-13 22:00 ` tip-bot for Andreas Herrmann
0 siblings, 0 replies; 12+ messages in thread
From: tip-bot for Andreas Herrmann @ 2012-11-13 22:00 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, hpa, mingo, andreas.herrmann3, tglx, hpa
Commit-ID: 2e8458dfe4202df75543402c7343b8f94de4101e
Gitweb: http://git.kernel.org/tip/2e8458dfe4202df75543402c7343b8f94de4101e
Author: Andreas Herrmann <andreas.herrmann3@amd.com>
AuthorDate: Fri, 19 Oct 2012 11:00:49 +0200
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Tue, 13 Nov 2012 11:22:30 -0800
x86, cacheinfo: Make use of CPUID 0x8000001d for cache information on AMD
Rely on CPUID 0x8000001d for cache information when AMD CPUID topology
extensions are available.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Link: http://lkml.kernel.org/r/20121019090049.GF26718@alberich
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 8ce7a83..cd2e1cc 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -538,7 +538,11 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
unsigned edx;
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
- amd_cpuid4(index, &eax, &ebx, &ecx);
+ if (cpu_has_topoext)
+ cpuid_count(0x8000001d, index, &eax.full,
+ &ebx.full, &ecx.full, &edx);
+ else
+ amd_cpuid4(index, &eax, &ebx, &ecx);
amd_init_l3_cache(this_leaf, index);
} else {
cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/4] x86, cacheinfo: Base cache sharing info on CPUID 0x8000001d on AMD
2012-10-19 8:55 [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions Andreas Herrmann
` (2 preceding siblings ...)
2012-10-19 9:00 ` [PATCH 3/4] x86, cacheinfo: Make use of CPUID 0x8000001d for cache information " Andreas Herrmann
@ 2012-10-19 9:02 ` Andreas Herrmann
2012-11-13 22:01 ` [tip:x86/cpu] " tip-bot for Andreas Herrmann
2012-11-06 20:47 ` [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions Jacob Shin
4 siblings, 1 reply; 12+ messages in thread
From: Andreas Herrmann @ 2012-10-19 9:02 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin, Thomas Gleixner; +Cc: x86, linux-kernel
The patch is based on a patch submitted by Hans Rosenfeld.
See http://marc.info/?l=linux-kernel&m=133908777200931
Note that CPUID Fn8000_001D_EAX slightly differs to Intel's CPUID function 4.
Bits 14-25 contain NumSharingCache. Actual number of cores sharing
this cache. SW to add value of one to get result.
The corresponding bits on Intel are defined as "maximum number of threads
sharing this cache" (with a "plus 1" encoding).
Thus a different method to determine which cores are sharing a cache
level has to be used.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 41 +++++++++++++++++++++-----------
1 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index cd2e1cc..fe9edec 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -750,37 +750,50 @@ static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
static int __cpuinit cache_shared_amd_cpu_map_setup(unsigned int cpu, int index)
{
struct _cpuid4_info *this_leaf;
- int ret, i, sibling;
- struct cpuinfo_x86 *c = &cpu_data(cpu);
+ int i, sibling;
- ret = 0;
- if (index == 3) {
- ret = 1;
- for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
+ if (cpu_has_topoext) {
+ unsigned int apicid, nshared, first, last;
+
+ if (!per_cpu(ici_cpuid4_info, cpu))
+ return 0;
+
+ this_leaf = CPUID4_INFO_IDX(cpu, index);
+ nshared = this_leaf->base.eax.split.num_threads_sharing + 1;
+ apicid = cpu_data(cpu).apicid;
+ first = apicid - (apicid % nshared);
+ last = first + nshared - 1;
+
+ for_each_online_cpu(i) {
+ apicid = cpu_data(i).apicid;
+ if ((apicid < first) || (apicid > last))
+ continue;
if (!per_cpu(ici_cpuid4_info, i))
continue;
this_leaf = CPUID4_INFO_IDX(i, index);
- for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) {
- if (!cpu_online(sibling))
+
+ for_each_online_cpu(sibling) {
+ apicid = cpu_data(sibling).apicid;
+ if ((apicid < first) || (apicid > last))
continue;
set_bit(sibling, this_leaf->shared_cpu_map);
}
}
- } else if ((c->x86 == 0x15) && ((index == 1) || (index == 2))) {
- ret = 1;
- for_each_cpu(i, cpu_sibling_mask(cpu)) {
+ } else if (index == 3) {
+ for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
if (!per_cpu(ici_cpuid4_info, i))
continue;
this_leaf = CPUID4_INFO_IDX(i, index);
- for_each_cpu(sibling, cpu_sibling_mask(cpu)) {
+ for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) {
if (!cpu_online(sibling))
continue;
set_bit(sibling, this_leaf->shared_cpu_map);
}
}
- }
+ } else
+ return 0;
- return ret;
+ return 1;
}
static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
--
1.7.8.6
^ permalink raw reply related [flat|nested] 12+ messages in thread* [tip:x86/cpu] x86, cacheinfo: Base cache sharing info on CPUID 0x8000001d on AMD
2012-10-19 9:02 ` [PATCH 4/4] x86, cacheinfo: Base cache sharing info on CPUID 0x8000001d " Andreas Herrmann
@ 2012-11-13 22:01 ` tip-bot for Andreas Herrmann
0 siblings, 0 replies; 12+ messages in thread
From: tip-bot for Andreas Herrmann @ 2012-11-13 22:01 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, hpa, mingo, andreas.herrmann3, tglx, hpa
Commit-ID: 27d3a8a26ada7660116fdd6830096008c063ee96
Gitweb: http://git.kernel.org/tip/27d3a8a26ada7660116fdd6830096008c063ee96
Author: Andreas Herrmann <andreas.herrmann3@amd.com>
AuthorDate: Fri, 19 Oct 2012 11:02:09 +0200
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Tue, 13 Nov 2012 11:22:31 -0800
x86, cacheinfo: Base cache sharing info on CPUID 0x8000001d on AMD
The patch is based on a patch submitted by Hans Rosenfeld.
See http://marc.info/?l=linux-kernel&m=133908777200931
Note that CPUID Fn8000_001D_EAX slightly differs to Intel's CPUID function 4.
Bits 14-25 contain NumSharingCache. Actual number of cores sharing
this cache. SW to add value of one to get result.
The corresponding bits on Intel are defined as "maximum number of threads
sharing this cache" (with a "plus 1" encoding).
Thus a different method to determine which cores are sharing a cache
level has to be used.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Link: http://lkml.kernel.org/r/20121019090209.GG26718@alberich
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 41 +++++++++++++++++++++-----------
1 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index cd2e1cc..fe9edec 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -750,37 +750,50 @@ static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
static int __cpuinit cache_shared_amd_cpu_map_setup(unsigned int cpu, int index)
{
struct _cpuid4_info *this_leaf;
- int ret, i, sibling;
- struct cpuinfo_x86 *c = &cpu_data(cpu);
+ int i, sibling;
- ret = 0;
- if (index == 3) {
- ret = 1;
- for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
+ if (cpu_has_topoext) {
+ unsigned int apicid, nshared, first, last;
+
+ if (!per_cpu(ici_cpuid4_info, cpu))
+ return 0;
+
+ this_leaf = CPUID4_INFO_IDX(cpu, index);
+ nshared = this_leaf->base.eax.split.num_threads_sharing + 1;
+ apicid = cpu_data(cpu).apicid;
+ first = apicid - (apicid % nshared);
+ last = first + nshared - 1;
+
+ for_each_online_cpu(i) {
+ apicid = cpu_data(i).apicid;
+ if ((apicid < first) || (apicid > last))
+ continue;
if (!per_cpu(ici_cpuid4_info, i))
continue;
this_leaf = CPUID4_INFO_IDX(i, index);
- for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) {
- if (!cpu_online(sibling))
+
+ for_each_online_cpu(sibling) {
+ apicid = cpu_data(sibling).apicid;
+ if ((apicid < first) || (apicid > last))
continue;
set_bit(sibling, this_leaf->shared_cpu_map);
}
}
- } else if ((c->x86 == 0x15) && ((index == 1) || (index == 2))) {
- ret = 1;
- for_each_cpu(i, cpu_sibling_mask(cpu)) {
+ } else if (index == 3) {
+ for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
if (!per_cpu(ici_cpuid4_info, i))
continue;
this_leaf = CPUID4_INFO_IDX(i, index);
- for_each_cpu(sibling, cpu_sibling_mask(cpu)) {
+ for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) {
if (!cpu_online(sibling))
continue;
set_bit(sibling, this_leaf->shared_cpu_map);
}
}
- }
+ } else
+ return 0;
- return ret;
+ return 1;
}
static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions
2012-10-19 8:55 [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions Andreas Herrmann
` (3 preceding siblings ...)
2012-10-19 9:02 ` [PATCH 4/4] x86, cacheinfo: Base cache sharing info on CPUID 0x8000001d " Andreas Herrmann
@ 2012-11-06 20:47 ` Jacob Shin
2012-11-07 9:48 ` H. Peter Anvin
4 siblings, 1 reply; 12+ messages in thread
From: Jacob Shin @ 2012-11-06 20:47 UTC (permalink / raw)
To: x86
Cc: Ingo Molnar, H. Peter Anvin, Thomas Gleixner, linux-kernel,
herrmann.der.user
On Fri, Oct 19, 2012 at 10:55:19AM +0200, Andreas Herrmann wrote:
> Hi,
>
> Following patches modify cachinfo code to make use of AMD's topology
> extension CPUID functions. Thus (hopefully) we can avoid CPU specific
> modifications whenever cache topology changes.
>
> Please apply.
Acked-by: Jacob Shin <jacob.shin@amd.com>
Ping ?
Any feedback ? If not could we get it into tip ?
Thank you,
>
>
> Thanks,
>
> Andreas
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
>
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions
2012-11-06 20:47 ` [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions Jacob Shin
@ 2012-11-07 9:48 ` H. Peter Anvin
2012-11-13 18:28 ` Jacob Shin
0 siblings, 1 reply; 12+ messages in thread
From: H. Peter Anvin @ 2012-11-07 9:48 UTC (permalink / raw)
To: Jacob Shin, x86
Cc: Ingo Molnar, Thomas Gleixner, linux-kernel, herrmann.der.user
Too many of us at LCE right now...
Jacob Shin <jacob.shin@amd.com> wrote:
>On Fri, Oct 19, 2012 at 10:55:19AM +0200, Andreas Herrmann wrote:
>> Hi,
>>
>> Following patches modify cachinfo code to make use of AMD's topology
>> extension CPUID functions. Thus (hopefully) we can avoid CPU specific
>> modifications whenever cache topology changes.
>>
>> Please apply.
>
>Acked-by: Jacob Shin <jacob.shin@amd.com>
>
>
>
>Ping ?
>
>Any feedback ? If not could we get it into tip ?
>
>Thank you,
>
>>
>>
>> Thanks,
>>
>> Andreas
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe
>linux-kernel" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at http://www.tux.org/lkml/
>>
>>
>>
--
Sent from my mobile phone. Please excuse brevity and lack of formatting.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/4] x86, cacheinfo: Use AMD topology extensions
2012-11-07 9:48 ` H. Peter Anvin
@ 2012-11-13 18:28 ` Jacob Shin
0 siblings, 0 replies; 12+ messages in thread
From: Jacob Shin @ 2012-11-13 18:28 UTC (permalink / raw)
To: H. Peter Anvin
Cc: x86, Ingo Molnar, Thomas Gleixner, linux-kernel, herrmann.der.user
On Wed, Nov 07, 2012 at 10:48:35AM +0100, H. Peter Anvin wrote:
> Too many of us at LCE right now...
Hi, ping'ing once again, could you take a look at the patchset when
you get the chance, and if no problems commit them into tip?
Thanks!
-Jacob
>
> Jacob Shin <jacob.shin@amd.com> wrote:
>
> >On Fri, Oct 19, 2012 at 10:55:19AM +0200, Andreas Herrmann wrote:
> >> Hi,
> >>
> >> Following patches modify cachinfo code to make use of AMD's topology
> >> extension CPUID functions. Thus (hopefully) we can avoid CPU specific
> >> modifications whenever cache topology changes.
> >>
> >> Please apply.
> >
> >Acked-by: Jacob Shin <jacob.shin@amd.com>
> >
> >
> >
> >Ping ?
> >
> >Any feedback ? If not could we get it into tip ?
> >
> >Thank you,
> >
> >>
> >>
> >> Thanks,
> >>
> >> Andreas
> >>
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe
> >linux-kernel" in
> >> the body of a message to majordomo@vger.kernel.org
> >> More majordomo info at http://vger.kernel.org/majordomo-info.html
> >> Please read the FAQ at http://www.tux.org/lkml/
> >>
> >>
> >>
>
> --
> Sent from my mobile phone. Please excuse brevity and lack of formatting.
>
^ permalink raw reply [flat|nested] 12+ messages in thread